RFM products are now Murata products. RX5500 433.92 MHz • Designed for Short-Range Wireless Control Applications Hybrid Receiver • 3 V, Low Current Operation plus Sleep Mode • Characterized for Automotive Applications • High EMI Rejection Capability • Complies with Directive 2002/95/EC (RoHS) The RX5500 hybrid receiver is ideal for short-range wireless control applications where robust operation, small size, low power consumption and low cost are required. The RX5500 employs Murata’s amplifier- sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions are contained in the hybrid, simplifying and speeding design-in. The RX5500 is sensitive and stable. A wide dynamic range log detector provides robust performance in the presence of on-channel interference or noise. SM-20L Case Two stages of SAW filtering provide excellent receiver out-of-band rejection. The RX5500 generates virtually no RF emissions, facilitating compliance with ETSI I-ETS 300 220 and similar regulations. Absolute Maximum Ratings Rating Value Units Power Supply and All Input/Output Pins -0.3 to +4.0 V Non-Operating Case Temperature -50 to +100 °C Soldering Temperature (10 seconds / 5 cycles max.) 260 °C Electrical Characteristics Characteristic Sym Notes Minimum Typical Maximum Units Operating Frequency fo 433.72 434.12 MHz Modulation Types OOK & ASK Data Rate 19.2 kbps Receiver Performance, High Sensitivity Mode Sensitivity, 1.2 kbps, 10-3 BER, AM Test Method 1 -110.5 dBm Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Method 1 -104.5 dBm Current, 1.2 kbps (RPR = 330 K) 2 2.9 mA Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method 1 -109 dBm Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method 1 -103 dBm Current, 2.4 kbps (RPR = 330 K) 2 3.0 mA Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method 1 -105 dBm Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method 1 -99 dBm Current, 19.2 kbps 3.1 mA Receiver Performance, Low Current Mode Sensitivity, 1.2 kbps, 10-3 BER, AM Test Method 1 -104 dBm Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Method 1 -98 dBm Current, 1.2 kbps (RPR = 2000 K) 2 1.65 mA ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 1 of 9

Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 °C) Characteristic Sym Notes Minimum Typical Maximum Units Receiver Out-of-Band Rejection, ±5% fo R±5% 3 80 dB Receiver Ultimate Rejection RULT 3 100 dB Sleep Mode Current IS 0.7 µA Power Supply Voltage Range VCC 2.2 3.7 Vdc Power Supply Voltage Ripple 10 mVP-P Ambient Operating Temperature TA -40 85 °C CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. Notes: 1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure OOK/ASK receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. See Appendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to 3.7 V supply voltage range at five operating temperatures. The application/test circuit and component values are shown on the next page and in the Designer’s Guide. 2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitivity data and receiver current are given at 1.2 kbps for both high sensitivity operation (R = 330 K) and low current operation (R = 2000 K). PR PR 3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page. 4. See Table 1 on Page 8 for additional information on ASH radio event timing. SM-20L Package Drawing B C D E F ASH Transceiver Pin Out A GND1 RFIO 1 20 H VCC1 2 19 GND3 AGCCAP 3 18 CNTRL0 G PKDET 4 17 CNTRL1 mm Inches BBOUT 5 16 VCC2 Dimension CMPIN 6 15 PWIDTH Min Nom Max Min Nom Max RXDATA 7 14 PRATE A 10.795 10.922 11.049 .425 .430 .435 TXMOD 8 13 THLD1 B 9.525 9.652 9.779 .375 .380 .385 LPFADJ 9 12 THLD2 C 1.778 1.905 2.032 .070 .075 .080 10 11 D 3.048 3.175 3.302 .120 .125 .130 GND2 RREF E 0.381 0.508 0.635 .015 .020 .025 F 0.889 1.016 1.143 .035 .040 .045 G 3.175 3.302 3.429 .125 .130 .135 H 1.778 1.905 2.032 .070 .075 0.80 ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 2 of 9

ASH Receiver Application Circuit OOK Configuration + 3 VDC C DCB + R/S R R RTH1 PW PR 19 18 17 16 15 14 13 12 LAT GN3D CRNL0T CRNL1T VC2C WIDPTHRAPTE TH1LD NC 20 RFIO TOP VIEW RREF 11 R REF LESD 1 GVCNCD1 RF PK BB CMP RX GNLPDF2 10 1 A1 DET OUT IN DATA NC ADJ 2 3 4 5 6 7 8 9 RBBO RLPF + 3 CRFB1 VDC CBBO C LPF Data Output Receiver Set-Up, 3.0 Vdc, -40 to +85 °C Item Symbol OOK OOK ASK Units Notes Nominal NRZ Data Rate DR 1.2 2.4 19.2 kbps see page 1& 2 NOM Minimum Signal Pulse SP 833.33 416.67 52.08 µs single bit MIN Maximum Signal Pulse SP 3333.33 1666.68 208.32 µs 4 bits of same value MAX BBOUT Capacitor C 0.2 0.1 0.015 µF ±10% ceramic BBO BBOUT Resistor R 12 12 0 K ±5% BBO LPFAUX Capacitor C 0.01 0.0047 - µF ±5% LPF LPFADJ Resistor R 330 300 100 K ±5% LPF RREF Resistor R 100 100 100 K ±1% REF THLD1 Resistor R 0 0 0 K ±1%, typical values TH1 PRATE Resistor R 330 330 330 K ±5% PR PWIDTH Resistor R 270 to GND 270 to GND 270 to GND K ±5% PW DC Bypass Capacitor C 4.7 4.7 4.7 µF tantalum DCB RF Bypass Capacitor 1 C 100 100 100 pF ±5% NPO RFB1 Antenna Tuning Inductor L 56 56 56 nH 50 ohm antenna AT Shunt Tuning/ESD Inductor L 220 220 220 nH 50 ohm antenna ESD ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 3 of 9

ASH Receiver Theory of Operation generator, and that the two amplifiers are coupled by a surface acoustic wave (SAW) delay line, which has a typical delay of Introduction 0.5µs. Murata’s RX5500 series amplifier-sequenced hybrid (ASH) An incoming RF signal is first filtered by a narrow-band SAW filter, receivers are specifically designed for short-range wireless control and is then applied to RFA1. The pulse generator turns RFA1 ON and data communication applications. The receivers provide for 0.5 µs. The amplified signal from RFA1 emerges from the SAW robust operation, very small size, low power consumption and low delay line at the input to RFA2. RFA1 is now switched OFF and implementation cost. All critical RF functions are contained in the RFA2 is switched ON for 0.55 µs, amplifying the RF signal further. hybrid, simplifying and speeding design-in. The ASH receiver can The ON time for RFA2 is usually set at 1.1 times the ON time for be readily configured to support a wide range of data rates and RFA1, as the filtering effect of the SAW delay line stretches the protocol requirements. The receiver features virtually no RF signal pulse from RFA1 somewhat. As shown in the timing emissions, making it easy to certify to short-range (unlicensed) diagram, RFA1 and RFA2 are never on at the same time, assuring radio regulations. excellent receiver stability. Note that the narrow-band SAW filter eliminates sampling sideband responses outside of the receiver Amplifier-Sequenced Receiver Operation passband, and the SAW filter and delay line act together to provide The ASH receiver’s unique feature set is made possible by its very high receiver ultimate rejection. system architecture. The heart of the receiver is the amplifier- sequenced receiver section, which provides more than 100 dB of Amplifier-sequenced receiver operation has several interesting stable RF and detector gain without any special shielding or characteristics that can be exploited in system design. The RF decoupling provisions. Stability is achieved by distributing the total amplifiers in an amplifier-sequenced receiver can be turned on and RF gain over time. This is in contrast to a superheterodyne off almost instantly, allowing for very quick power-down (sleep) receiver, which achieves stability by distributing total RF gain over and wake-up times. Also, both RF amplifiers can be off between multiple frequencies. ON sequences to trade-off receiver noise figure for lower average current consumption. The effect on noise figure can be modeled as Figure 1 shows the basic block diagram and timing cycle for an if RFA1 is on continuously, with an attenuator placed in front of it amplifier-sequenced receiver. Note that the bias to RF amplifiers with a loss equivalent to 10*log (RFA1 duty factor), where the RFA1 and RFA2 are independently controlled by a pulse 10 duty factor is the average amount of time RFA1 is ON (up to 50%). ASH Receiver Block Diagram & Timing Cycle Antenna Detector & SAW Data SAW Filter RFA1 RFA2 Low-Pass Delay Line Out Filter P1 P2 Pulse Generator RF Input RF Data Pulse t PW1 t PRI P1 t PRC RFA1 Out Delay Line Out t PW2 P2 Figure 1 ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 4 of 9

RX5500 Series ASH Receiver Block Diagram RFA1 CNTRL1 CNTRL0 VCC1: Pin 2 VCC2: Pin 16 17 18 GND1: Pin 1 Power GND2: Pin 10 Bias Control DCoowntnrol GNCN:D 3 : P Pinin 1 89 RREF: Pin 11 CMPIN: Pin 6 NC: Pin 4 NC: Pin 12 Antenna Log BBOUT 3 RFIO SAW SAW Low-Pass RFA1 RFA2 Detector BB 20 CR Filter Delay Line Filter 5 6 7 ESD CBBO DS1 RXDATA Choke LPFADJ 9 Ref Thld R LPF Threshold Control THLD113 11RREF R TH1 Pulse Generator RREF & RF Amp Bias PRATE 14 15 PWIDTH R R PR PW Figure 2 Since an amplifier-sequenced receiver is inherently a sampling 70 dB of detector dynamic range. In combination with the 30 dB of receiver, the overall cycle time between the start of one RFA1 ON AGC range in RFA1, more than 100 dB of receiver dynamic range sequence and the start of the next RFA1 ON sequence should be is achieved. set to sample the narrowest RF data pulse at least 10 times. The detector output drives a gyrator filter. The filter provides a Otherwise, significant edge jitter will be added to the detected data three-pole, 0.05 degree equiripple low-pass response with pulse. excellent group delay flatness and minimal pulse ringing. The 3 dB RX5500 Series ASH Receiver Block Diagram bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an Figure 2 is the general block diagram of the RX5500 series ASH external resistor. receiver. Please refer to Figure 2 for the following discussions. The filter is followed by a base-band amplifier which boosts the Antenna Port detected signal to the BBOUT pin. When the receiver RF amplifiers The only external RF components needed for the receiver are the are operating at a 50%-50% duty cycle, the BBOUT signal antenna and its matching components. Antennas presenting an changes about 10 mV/dB, with a peak-to-peak signal level of up to impedance in the range of 35 to 72 ohms resistive can be 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak satisfactorily matched to the RFIO pin with a series matching coil signal level are proportionately less. The detected signal is riding and a shunt matching/ESD protection coil. Other antenna on a 1.1 Vdc level that varies somewhat with supply voltage, impedances can be matched using two or three components. For temperature, etc. BBOUT is coupled to the CMPIN pin or to an some impedances, two inductors and a capacitor will be required. external data recovery process (DSP, etc.) by a series capacitor. A DC path from RFIO to ground is required for ESD protection. The correct value of the series capacitor depends on data rate, data run length, and other factors as discussed in the ASH Receiver Chain Transceiver Designer’s Guide. The output of the SAW filter drives amplifier RFA1. The output of When the receiver is placed in the power-down (sleep) mode, the RFA1 drives the SAW delay line, which has a nominal delay of 0.5 output impedance of BBOUT becomes very high. This feature µs. helps preserve the charge on the coupling capacitor to minimize The second amplifier, RFA2, provides 51 dB of gain below data slicer stabilization time when the receiver switches out of the saturation. The output of RFA2 drives a full-wave detector with 19 sleep mode. dB of threshold gain. The onset of saturation in each section of Data Slicers RFA2 is detected and summed to provide a logarithmic response. This is added to the output of the full-wave detector to produce an The CMPIN pin drives data slicer DS1, which convert the analog overall detector response that is square law for low signal levels, signal from BBOUT back into a digital stream. Data slicer DS1 is a and transitions into a log response for high signal levels. This capacitively-coupled comparator with provisions for an adjustable combination provides excellent threshold sensitivity and more than threshold. The threshold, or squelch, offsets the comparator’s ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 5 of 9

slicing level from 0 to 90 mV, and is set with a resistor between the Sleep and Wake-Up Timing RREF and THLD1 pins. This threshold allows a trade-off between The maximum transition time from the receive mode to the power- receiver sensitivity and output noise density in the no-signal down (sleep) mode t is 10 µs after CNTRL1 and CNTRL0 are RS condition. For best sensitivity, the threshold is set to 0. In this case, both low (1 µs fall time). noise is output continuously when no signal is present. This, in The maximum transition time t from the sleep mode to the turn, requires the circuit being driven by the RXDATA pin to be able SR receive mode is 3*t , where t is the BBOUT-CMPIN to process noise (and signals) continuously. BBC BBC coupling-capacitor time constant. When the operating temperature This can be a problem if RXDATA is driving a circuit that must is limited to 60 °C, the time required to switch from sleep to receive “sleep” when data is not present to conserve power, or when it its is dramatically less for short sleep times, as less charge leaks necessary to minimize false interrupts to a multitasking processor. away from the BBOUT- CMPIN coupling capacitor. In this case, noise can be greatly reduced by increasing the Pulse Generator Timing threshold level, but at the expense of sensitivity. The best 3 dB In the low data rate mode, the interval t between the falling edge bandwidth for the low-pass filter is also affected by the threshold PRI of an ON pulse to the first RF amplifier and the rising edge of the level setting of DS1. The bandwidth must be increased as the next ON pulse to the first RF amplifier is set by a resistor R threshold is increased to minimize data pulse-width variations with PR between the PRATE pin and ground. The interval can be adjusted signal amplitude. between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 Receiver Pulse Generator and RF Amplifier Bias K. The value of the R is given by: PR The receiver amplifier-sequence operation is controlled by the R = 404* t + 10.5, where t is in µs, and R is in kilohms Pulse Generator & RF Amplifier Bias module, which in turn is PR PRI PRI PR controlled by the PRATE and PWIDTH input pins, and the Power In the high data rate mode (selected at the PWIDTH pin) the Down (sleep) Control Signal from the Bias Control function. receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the period t from the start of an ON pulse to the In the low data rate mode, the interval between the falling edge of PRC first RF amplifier to the start of the next ON pulse to the first RF one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse amplifier is controlled by the PRATE resistor over a range of 0.1 to tPRI is set by a resistor between the PRATE pin and ground. The 1.1 µs using a resistor of 11 K to 220 K. In this case R is given interval can be adjusted between 0.1 and 5 µs. In the high data rate PR by: mode (selected at the PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the start- RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms to-start period tPRC for ON pulses to RFA1 are controlled by the In the low data rate mode, the PWIDTH pin sets the width of the PRATE resistor over a range of 0.1 to 1.1 µs. ON pulse to the first RF amplifier t with a resistor R to PW1 PW In the low data rate mode, the PWIDTH pin sets the width of the ground (the ON pulse width to the second RF amplifier tPW2 is set ON pulse t to RFA1 with a resistor to ground (the ON pulse at 1.1 times the pulse width to the first RF amplifier in the low data PW1 width tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in rate mode). The ON pulse width tPW1 can be adjusted between the low data rate mode). The ON pulse width t can be adjusted 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. PW1 between 0.55 and 1 µs. However, when the PWIDTH pin is The value of RPW is given by: connected to Vcc through a 1 M resistor, the RF amplifiers operate R = 404* t - 18.6, where t is in µs and R is in kilohms PW PW1 PW1 PW at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifiers are controlled by the However, when the PWIDTH pin is connected to Vcc through a 1 PRATE resistor as described above. M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF Both receiver RF amplifiers are turned off by the Power Down amplifiers are controlled by the PRATE resistor as described Control Signal, which is invoked in the sleep mode. above. Receiver Mode Control LPF Group Delay The receiver operating modes – receive and power-down (sleep), The low-pass filter group delay is a function of the filter 3 dB are controlled by the Bias Control function, and are selected with bandwidth, which is set by a resistor R to ground at the LPFADJ LPF the CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and pin. The minimum 3 dB bandwidth f = 1445/R , where f is LPF LPF LPF CNTRL0 both high place the unit in the receive mode. Setting in kHz, and R is in kilohms. LPF CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 and CNTRL0 are CMOS compatible The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where inputs. These inputs must be held at a logic level; they cannot be tFGD is in µs, fLPF in kHz, and RLPF in kilohms. left unconnected. Receiver Event Timing Receiver event timing is summarized in Table 1. Please refer to this table for the following discussions. Turn-On Timing The maximum time t required for the receive function to become PR operational at turn on is influenced by two factors. All receiver circuitry will be operational 5 ms after the supply voltage reaches 2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC stabilized in 3 time constants (3* ). The total turn-on time to tBBC stable receiver operation for a 10 ms power supply rise time is: t = 15 ms + 3*t PR BBC ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 6 of 9

Receiver Event Timing, 3.0 Vdc, -40 to +85 °C Min/ Event Symbol Time Test Conditions Notes Max Turn On to Receive t 3*t + 15 ms max 10 ms supply voltage rise time time until receiver operational PR BBC Sleep to RX t 3*t max 1 µs CNTRL0/CNTROL 1 rise time until receiver operational SR BBC times RX to Sleep t 10 µs max 1 µs CNTRL0/CNTROL 1 fall times time until receiver is in power-down mode RS PRATE Interval t 0.1 to 5 µs range low data rate mode user selected mode PRI PWIDTH RFA1 t 0.55 to 1 µs range low data rate mode user selected mode PW1 PWIDTH RFA2 t 1.1*t range low data rate mode user selected mode PW2 PW1 PRATE Cycle t 0.1 to 1.1 µs range high data rate mode user selected mode PRC PWIDTH High (RFA1 & RFA2) t 0.05 to 0.55 µs range high data rate mode user selected mode PWH LPF Group Delay t 1750/f max t in µs, f in kHz user selected FGD LPF FGD LPF LPF 3 dB Bandwidth f 1445/R min f in kHz, R in kilohms user selected LPF LPF LPF LPF BBOUT-CMPIN Time Constant t 0.064*C min t in µs, C in pF user selected BBC BBO BBC BBO Table 1 Pin Descriptions Pin Name Description 1 GND1 GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces. 2 VCC1 VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF capacitor, which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information. 3 RFA1 4 NC This pin should be left unconnected. 5 BBOUT BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor C for internal BBO data slicer operation. The time constant t for this connection is: BBC t = 0.064*C , where t is in µs and C is in pF BBC BBO BBC BBO A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between t and BBC 1.8*t with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend BBC on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A common criteria is to set the time constant for no more than a 20% voltage droop during SP . For this case: MAX C = 70*SP , where SP is the maximum signal pulse width in µs and C is in pF BBO MAX MAX BBO The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output imped- ance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat with supply volt- age and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recommended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin becomes very high, preserving the charge on the coupling capacitor. 6 CMPIN This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance of this pin is 70 K to 100 K. 7 RXDATA RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than Vcc + 200 mV. 8 NC This pin may be left unconnected or may be grounded. ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 7 of 9

9 LPFADJ This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R between this pin and LPF ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f from 4.5 kHz to 1.8 MHz. LPF The resistor value is determined by: R = 1445/ f , where R is in kilohms, and f is in kHz LPF LPF LPF LPF A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f and 1.3* f LPF LPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting. Pin Name Description 10 GND2 GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace. 11 RREF RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF. 12 NC This pin should be left unconnected. 13 THLD1 The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R to RREF. The threshold is TH1 increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The acceptable range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by: R = 1.11*V, where R is in kilohms and the threshold V is in mV TH1 TH1 A ±1% resistor tolerance is recommended for the THLD1 resistor. 14 PRATE The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the first RF amplifier t is set by a resistor R between this pin and ground. The interval t can be adjusted between 0.1 and PRI PR PRI 5 µs with a resistor in the range of 51 K to 2000 K. The value of R is given by: PR R = 404* t + 10.5, where t is in µs, and R is in kilohms PR PRI PRI PR A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period t from start-to-start PRC of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of R is given by: PR R = 198* t - 8.51, where t is in µs and R is in kilohms PR PRC PRC PR A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5 pF to maintain stability. 15 PWIDTH The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t with a resistor R to ground (the ON pulse PW1 PW width to the second RF amplifier t is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width t PW2 PW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of R is given by: PW R = 404* t - 18.6, where t is in µs and R is in kilohms PW PW1 PW1 PW A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode. 16 VCC2 VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor. 17 CNTRL1 CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is inter- preted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected. 18 CNTRL0 CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected. 19 GND3 GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace. 20 RFIO RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an imped- ance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some imped- ances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection. ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 8 of 9

SM-20L PCB Pad Layout 5 55 5 2 72 7 7 91 3 1 12 2 . .. . .4600 .3825 .3575 .3175 .2775 .2375 .1975 .1575 .1175 .1025 .0775 0 0 0 0 0 4 7 1 0 1 2 4 0. 0.000. . . Dimensions in inches Note: Specifications subject to change without notice. ©2010-2015 by Murata Electronics N.A., Inc. www.murata.com RX5500 (R) 4/15/15 Page 9 of 9