RFM products are now Murata products. RX5000 • Designed for Short-Range Wireless Control and Data Communications • Supports RF Data Transmission Rates Up to 115.2 kbps • 3 V, Low Current Operation plus Sleep Mode 433.92 MHz • Stable, Easy to Use, Low External Parts Count Hybrid Receiver • Complies with Directive 2002/95/EC (RoHS) The RX5000 hybrid receiver is ideal for short-range wireless control and data applications where robust operation, small size, low power consumption and low cost are required. The RX5000 employs Murata’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions are contained in the hybrid, simplifying and speeding design-in. The RX5000 is sensitive and stable. A wide dynamic range log detector, in combination with digital AGC and a compound data slicer, provide robust performance in the presence of on-channel interference or noise. Two stages of SAW filtering provide excellent receiver out- of-band rejection. The RX5000 generates virtually no RF emissions, facilitating compliance with ETSI I-ETS 300 220 and similar regulations. SM-20L Case Absolute Maximum Ratings Rating Value Units Power Supply and All Input/Output Pins -0.3 to +4.0 V Non-Operating Case Temperature -50 to +100 °C Soldering Temperature (10 seconds / 5 cycles max.) 260 °C Electrical Characteristics Characteristic Sym Notes Minimum Typical Maximum Units f 433.72 434.12 MHz Operating Frequency o OOK & ASK Modulation Types 115.2 kbps Data Rate Receiver Performance, High Sensitivity Mode 1 -109 dBm Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method 1 -103 dBm Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method Current, 2.4 kbps (R = 330 K) 2 3.0 mA PR 1 -105 dBm Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method 1 -99 dBm Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method Current, 19.2 kbps (R = 330 K) 2 3.1 mA PR 1 -101 dBm Sensitivity, 115.2 kbps, 10-3 BER, AM Test Method 1 -95 dBm Sensitivity, 115.2 kbps, 10-3 BER, Pulse Test Method 3.8 mA Current, 115.2 kbps Receiver Performance, Low Current Mode 1 -104 dBm Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method 1 -98 dBm Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method Current, 2.4 kbps (R = 1100 K) 2 1.8 mA PR ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 1 of 10

Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 °C) Characteristic Sym Notes Minimum Typical Maximum Units Receiver Out-of-Band Rejection, ±5% fo R±5% 3 80 dB Receiver Ultimate Rejection RULT 3 100 dB Sleep Mode Current IS 0.7 µA Power Supply Voltage Range VCC 2.2 3.7 Vdc Power Supply Voltage Ripple 10 mVP-P Ambient Operating Temperature TA -40 85 °C CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. NOTES: 1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure OOK/ASK receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. See Appendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to 3.7 V supply voltage range at five operating temperatures. The application/test circuit and component values are shown on the next page and in the Designer’s Guide. 2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitivity data and receiver current are given at 2.4 kbps for both high sensitivity operation (R = 330 K) and low current operation (R = 1100 K). PR PR 3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page. 4. See Table 1 on Page 8 for additional information on ASH radio event timing. SM-20L Package Drawing B C D E F ASH Transceiver Pin Out A GND1 RFIO 1 20 H VCC1 2 19 GND3 G AGCCAP 3 18 CNTRL0 PKDET 4 17 CNTRL1 mm Inches BBOUT 5 16 VCC2 Dimension CMPIN 6 15 PWIDTH Min Nom Max Min Nom Max RXDATA 7 14 PRATE A 10.795 10.922 11.049 .425 .430 .435 TXMOD 8 13 THLD1 B 9.525 9.652 9.779 .375 .380 .385 LPFADJ 9 12 THLD2 C 1.778 1.905 2.032 .070 .075 .080 10 11 D 3.048 3.175 3.302 .120 .125 .130 GND2 RREF E 0.381 0.508 0.635 .015 .020 .025 F 0.889 1.016 1.143 .035 .040 .045 G 3.175 3.302 3.429 .125 .130 .135 H 1.778 1.905 2.032 .070 .075 0.80 ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 2 of 10

ASH Receiver Application Circuit ASH Receiver Application Circuit OOK Configuration ASK Configuration + 3 + 3 VDC VDC CDCB CDCB + + R/S RPW RPR RTH1 R/S RPW RPR RTH1 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 RTH2 LAT GN3D CRNL0T CRNL1T VC2C WIDPTHRAPTE TH1LD NC LAT GN3D CRNL0T CRNL1T VC2C WIDPTHRAPTE TH1LD TH2LD 20 RFIO TOP VIEW RREF 11 RREF 20 RFIO TOP VIEW RREF 11 RREF LESD 1 GVCNCD1 RF PK BB CMP RX GNLPDF2 10 LESD 1 GVCNCD1 AGC PK BB CMP RX GLNPDF2 10 1 A1 DET OUT IN DATA NC ADJ 1 CAP DET OUT IN DATA NC ADJ 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 RBBO RLPF RLPF C V+D 3C CRFB1CLPF CBBO CRFB1 V+D 3C CAGC CPKD BBO Data Output Data Output Receiver Set-Up, 3.0 Vdc, -40 to +85 °C Item Symbol OOK OOK ASK Units Notes Nominal NRZ Data Rate DR 2.4 19.2 115.2 kbps see page 1& 2 NOM Minimum Signal Pulse SP 416.67 52.08 8.68 µs single bit MIN Maximum Signal Pulse SP 1666.68 208.32 34.72 µs 4 bits of same value MAX AGCCAP Capacitor C - - 2200 pF ±10% ceramic AGC PKDET Capacitor C - - 0.001 µF ±10% ceramic PKD BBOUT Capacitor C 0.1 0.015 0.0027 µF ±10% ceramic BBO BBOUT Resistor R 12 0 0 K ±5% BBO LPFAUX Capacitor C 0.0047 - - µF ±5% LPF LPFADJ Resistor R 300 100 15 K ±5% LPF RREF Resistor R 100 100 100 K ±1% REF THLD2 Resistor R - - 100 K ±1%, for 6 dB below peak TH2 THLD1 Resistor R 0 0 10 K ±1%, typical values TH1 PRATE Resistor R 330 330 160 K ±5% PR PWIDTH Resistor R 270 to GND 270 to GND 1000 to Vcc K ±5% PW DC Bypass Capacitor C 4.7 4.7 4.7 µF tantalum DCB RF Bypass Capacitor 1 C 100 100 100 pF ±5% NPO RFB1 Antenna Tuning Inductor L 56 56 56 nH 50 ohm antenna AT Shunt Tuning/ESD Inductor L 220 220 220 nH 50 ohm antenna ESD ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 3 of 10

ASH Receiver Theory of Operation generator, and that the two amplifiers are coupled by a surface acoustic wave (SAW) delay line, which has a typical delay of Introduction 0.5µs. Murata’s RX5000 series amplifier-sequenced hybrid (ASH) An incoming RF signal is first filtered by a narrow-band SAW filter, receivers are specifically designed for short-range wireless control and is then applied to RFA1. The pulse generator turns RFA1 ON and data communication applications. The receivers provide for 0.5 µs. The amplified signal from RFA1 emerges from the SAW robust operation, very small size, low power consumption and low delay line at the input to RFA2. RFA1 is now switched OFF and implementation cost. All critical RF functions are contained in the RFA2 is switched ON for 0.55 µs, amplifying the RF signal further. hybrid, simplifying and speeding design-in. The ASH receiver can The ON time for RFA2 is usually set at 1.1 times the ON time for be readily configured to support a wide range of data rates and RFA1, as the filtering effect of the SAW delay line stretches the protocol requirements. The receiver features virtually no RF signal pulse from RFA1 somewhat. As shown in the timing emissions, making it easy to certify to short-range (unlicensed) diagram, RFA1 and RFA2 are never on at the same time, assuring radio regulations. excellent receiver stability. Note that the narrow-band SAW filter eliminates sampling sideband responses outside of the receiver Amplifier-Sequenced Receiver Operation passband, and the SAW filter and delay line act together to provide The ASH receiver’s unique feature set is made possible by its very high receiver ultimate rejection. system architecture. The heart of the receiver is the amplifier- sequenced receiver section, which provides more than 100 dB of Amplifier-sequenced receiver operation has several interesting stable RF and detector gain without any special shielding or characteristics that can be exploited in system design. The RF decoupling provisions. Stability is achieved by distributing the total amplifiers in an amplifier-sequenced receiver can be turned on and RF gain over time. This is in contrast to a superheterodyne off almost instantly, allowing for very quick power-down (sleep) receiver, which achieves stability by distributing total RF gain over and wake-up times. Also, both RF amplifiers can be off between multiple frequencies. ON sequences to trade-off receiver noise figure for lower average current consumption. The effect on noise figure can be modeled as Figure 1 shows the basic block diagram and timing cycle for an if RFA1 is on continuously, with an attenuator placed in front of it amplifier-sequenced receiver. Note that the bias to RF amplifiers with a loss equivalent to 10*log (RFA1 duty factor), where the RFA1 and RFA2 are independently controlled by a pulse 10 duty factor is the average amount of time RFA1 is ON (up to 50%). ASH Receiver Block Diagram & Timing Cycle Antenna Detector & SAW Data SAW Filter RFA1 RFA2 Low-Pass Delay Line Out Filter P1 P2 Pulse Generator RF Input RF Data Pulse t PW1 t PRI P1 t PRC RFA1 Out Delay Line Out t PW2 P2 Figure 1 ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 4 of 10

RX5000 Series ASH Receiver Block Diagram CNTRL1 CNTRL0 VCC1: Pin 2 17 18 VCC2: Pin 16 Power GND1: Pin 1 Bias Control DCoowntnrol GGNNDD23:: PPiinn 1109 NC: Pin 8 RREF: Pin 11 CMPIN: Pin 6 Antenna Log BBOUT RFIO SAW SAW Low-Pass Peak Ref DS2 RFA1 RFA2 Detector BB 20 CR Filter Delay Line Filter 5 6 Detector ESD CBBO dB Below Choke LPFADJ 9R PKDET 4CPKD Peak Thld AND 7 RXDATA LPF AGC Set AGC DS1 Gain Select Ref Thld Pulse Generator AGC AGC Reset Threshold & RF Amp Bias Control Control PRATE 14 15 PWIDTH AGCCAP 3 13 11 12 C THLD1 THLD2 RPR RPW AGC RTH1 RRTH2 REF Figure 2 Since an amplifier-sequenced receiver is inherently a sampling dB of threshold gain. The onset of saturation in each section of receiver, the overall cycle time between the start of one RFA1 ON RFA2 is detected and summed to provide a logarithmic response. sequence and the start of the next RFA1 ON sequence should be This is added to the output of the full-wave detector to produce an set to sample the narrowest RF data pulse at least 10 times. overall detector response that is square law for low signal levels, Otherwise, significant edge jitter will be added to the detected data and transitions into a log response for high signal levels. This pulse. combination provides excellent threshold sensitivity and more than 70 dB of detector dynamic range. In combination with the 30 dB of RX5000 Series ASH Receiver Block Diagram AGC range in RFA1, more than 100 dB of receiver dynamic range Figure 2 is the general block diagram of the RX5000 series ASH is achieved. receiver. Please refer to Figure 2 for the following discussions. The detector output drives a gyrator filter. The filter provides a Antenna Port three-pole, 0.05 degree equiripple low-pass response with The only external RF components needed for the receiver are the excellent group delay flatness and minimal pulse ringing. The 3 dB antenna and its matching components. Antennas presenting an bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an impedance in the range of 35 to 72 ohms resistive can be external resistor. satisfactorily matched to the RFIO pin with a series matching coil and a shunt matching/ESD protection coil. Other antenna The filter is followed by a base-band amplifier which boosts the impedances can be matched using two or three components. For detected signal to the BBOUT pin. When the receiver RF amplifiers some impedances, two inductors and a capacitor will be required. are operating at a 50%-50% duty cycle, the BBOUT signal A DC path from RFIO to ground is required for ESD protection. changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak Receiver Chain signal level are proportionately less. The detected signal is riding The output of the SAW filter drives amplifier RFA1. This amplifier on a 1.1 Vdc level that varies somewhat with supply voltage, includes provisions for detecting the onset of saturation (AGC Set), temperature, etc. BBOUT is coupled to the CMPIN pin or to an and for switching between 35 dB of gain and 5 dB of gain (Gain external data recovery process (DSP, etc.) by a series capacitor. Select). AGC Set is an input to the AGC Control function, and Gain The correct value of the series capacitor depends on data rate, Select is the AGC Control function output. ON/OFF control to data run length, and other factors as discussed in the ASH RFA1 (and RFA2) is generated by the Pulse Generator & RF Amp Transceiver Designer’s Guide. Bias function. The output of RFA1 drives the SAW delay line, which When an external data recovery process is used with AGC, has a nominal delay of 0.5 µs. BBOUT must be coupled to the external data recovery process The second amplifier, RFA2, provides 51 dB of gain below and CMPIN by separate series coupling capacitors. The AGC saturation. The output of RFA2 drives a full-wave detector with 19 reset function is driven by the signal applied to CMPIN. ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 5 of 10

When the receiver is placed in the power-down (sleep) mode, the avoid AGC chattering during runs of “0” bits in the received data output impedance of BBOUT becomes very high. This feature stream. Note that AGC operation requires the peak detector to be helps preserve the charge on the coupling capacitor to minimize functioning, even if DS2 is not being used. AGC operation can be data slicer stabilization time when the receiver switches out of the defeated by connecting the AGCCAP pin to Vcc. The AGC can be sleep mode. latched on once engaged by connecting a 150 kilohm resistor between the AGCCAP pin and ground in lieu of a capacitor. Data Slicers The CMPIN pin drives two data slicers, which convert the analog Receiver Pulse Generator and RF Amplifier Bias signal from BBOUT back into a digital stream. The best data slicer The receiver amplifier-sequence operation is controlled by the choice depends on the system operating parameters. Data slicer Pulse Generator & RF Amplifier Bias module, which in turn is DS1 is a capacitively-coupled comparator with provisions for an controlled by the PRATE and PWIDTH input pins, and the Power adjustable threshold. DS1 provides the best performance at low Down (sleep) Control Signal from the Bias Control function. signal-to-noise conditions. The threshold, or squelch, offsets the In the low data rate mode, the interval between the falling edge of comparator’s slicing level from 0 to 90 mV, and is set with a resistor one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse between the RREF and THLD1 pins. This threshold allows a trade- t is set by a resistor between the PRATE pin and ground. The off between receiver sensitivity and output noise density in the no- PRI interval can be adjusted between 0.1 and 5 µs. In the high data rate signal condition. For best sensitivity, the threshold is set to 0. In mode (selected at the PWIDTH pin) the receiver RF amplifiers this case, noise is output continuously when no signal is present. operate at a nominal 50%-50% duty cycle. In this case, the start- This, in turn, requires the circuit being driven by the RXDATA pin to-start period t for ON pulses to RFA1 are controlled by the to be able to process noise (and signals) continuously. PRC PRATE resistor over a range of 0.1 to 1.1 µs. This can be a problem if RXDATA is driving a circuit that must In the low data rate mode, the PWIDTH pin sets the width of the “sleep” when data is not present to conserve power, or when it its ON pulse t to RFA1 with a resistor to ground (the ON pulse necessary to minimize false interrupts to a multitasking processor. PW1 width t to RFA2 is set at 1.1 times the pulse width to RFA1 in In this case, noise can be greatly reduced by increasing the PW2 the low data rate mode). The ON pulse width t can be adjusted threshold level, but at the expense of sensitivity. The best 3 dB PW1 between 0.55 and 1 µs. However, when the PWIDTH pin is bandwidth for the low-pass filter is also affected by the threshold connected to Vcc through a 1 M resistor, the RF amplifiers operate level setting of DS1. The bandwidth must be increased as the at a nominal 50%-50% duty cycle, facilitating high data rate threshold is increased to minimize data pulse-width variations with operation. In this case, the RF amplifiers are controlled by the signal amplitude. PRATE resistor as described above. Data slicer DS2 can overcome this compromise once the signal Both receiver RF amplifiers are turned off by the Power Down level is high enough to enable its operation. DS2 is a “dB-below- Control Signal, which is invoked in the sleep mode. peak” slicer. The peak detector charges rapidly to the peak value of each data pulse, and decays slowly in between data pulses Receiver Mode Control (1:1000 ratio). The slicer trip point can be set from 0 to 120 mV The receiver operating modes – receive and power-down (sleep), below this peak value with a resistor between RREF and THLD2. are controlled by the Bias Control function, and are selected with A threshold of 60 mV is the most common setting, which equates the CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and to “6 dB below peak” when RFA1 and RFA2 are running a 50%- CNTRL0 both high place the unit in the receive mode. Setting 50% duty cycle. Slicing at the “6 dB-below-peak” point reduces the CNTRL1 and CNTRL0 both low place the unit in the power-down signal amplitude to data pulse-width variation, allowing a lower 3 (sleep) mode. CNTRL1 and CNTRL0 are CMOS compatible dB filter bandwidth to be used for improved sensitivity. inputs. These inputs must be held at a logic level; they cannot be left unconnected. DS2 is best for ASK modulation where the transmitted waveform has been shaped to minimize signal bandwidth. However, DS2 is Receiver Event Timing subject to being temporarily “blinded” by strong noise pulses, Receiver event timing is summarized in Table 1. Please refer to which can cause burst data errors. Note that DS1 is active when this table for the following discussions. DS2 is used, as RXDATA is the logical AND of the DS1 and DS2 Turn-On Timing outputs. DS2 can be disabled by leaving THLD2 disconnected. A The maximum time t required for the receive function to become non-zero DS1 threshold is required for proper AGC operation. PR operational at turn on is influenced by two factors. All receiver AGC Control circuitry will be operational 5 ms after the supply voltage reaches The output of the Peak Detector also provides an AGC Reset 2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC signal to the AGC Control function through the AGC comparator. stabilized in 3 time constants (3*t ). The total turn-on time to BBC The purpose of the AGC function is to extend the dynamic range stable receiver operation for a 10 ms power supply rise time is: of the receiver, so that the receiver can operate close to its t = 15 ms + 3*t transmitter when running ASK and/or high data rate modulation. PR BBC The onset of saturation in the output stage of RFA1 is detected and Sleep and Wake-Up Timing generates the AGC Set signal to the AGC Control function. The The maximum transition time from the receive mode to the power- AGC Control function then selects the 5 dB gain mode for RFA1. down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0 are The AGC Comparator will send a reset signal when the Peak both low (1 µs fall time). Detector output (multiplied by 0.8) falls below the threshold voltage The maximum transition time t from the sleep mode to the SR for DS1. receive mode is 3*t , where t is the BBOUT-CMPIN BBC BBC A capacitor at the AGCCAP pin avoids AGC “chattering” during the coupling-capacitor time constant. When the operating temperature time it takes for the signal to propagate through the low-pass filter is limited to 60 oC, the time required to switch from sleep to receive and charge the peak detector. The AGC capacitor also allows the is dramatically less for short sleep times, as less charge leaks hold-in time to be set longer than the peak detector decay time to away from the BBOUT- CMPIN coupling capacitor. ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 6 of 10

AGC Timing In the low data rate mode, the PWIDTH pin sets the width of the The maximum AGC engage time tAGC is 5 µs after the reception of ON pulse to the first RF amplifier tPW1 with a resistor RPW to a -30 dBm RF signal with a 1 µs envelope rise time. ground (the ON pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier in the low data The minimum AGC hold-in time is set by the value of the capacitor rate mode). The ON pulse width t can be adjusted between at the AGCCAP pin. The hold-in time t = C /19.1, where PW1 AGH AGC 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. t is in µs and C is in pF. AGH AGC The value of R is given by: PW Peak Detector Timing R = 404* t - 18.6, where t is in µs and R is in kilohms The Peak Detector attack time constant is set by the value of the PW PW1 PW1 PW capacitor at the PKDET pin. The attack time t = C /4167, However, when the PWIDTH pin is connected to Vcc through a 1 PKA PKD where t is in µs and C is in pF. The Peak Detector decay M resistor, the RF amplifiers operate at a nominal 50%-50% duty PKA PKD time constant t = 1000*t . cycle, facilitating high data rate operation. In this case, the RF PKD PKA amplifiers are controlled by the PRATE resistor as described Pulse Generator Timing above. In the low data rate mode, the interval t between the falling edge PRI of an ON pulse to the first RF amplifier and the rising edge of the LPF Group Delay next ON pulse to the first RF amplifier is set by a resistor R The low-pass filter group delay is a function of the filter 3 dB PR between the PRATE pin and ground. The interval can be adjusted bandwidth, which is set by a resistor RLPF to ground at the LPFADJ between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 pin. The minimum 3 dB bandwidth fLPF = 1445/RLPF, where fLPF is K. The value of the RPR is given by: in kHz, and RLPF is in kilohms. RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where t is in µs, f in kHz, and R in kilohms. In the high data rate mode (selected at the PWIDTH pin) the FGD LPF LPF receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the period t from the start of an ON pulse to the PRC first RF amplifier to the start of the next ON pulse to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this case R is given PR by: R = 198* t - 8.51, where t is in µs and R is in kilohms PR PRC PRC PR Receiver Event Timing, 3.0 Vdc, -40 to +85 °C Min/ Event Symbol Time Test Conditions Notes Max Turn On to Receive t 3*t + 15 ms max 10 ms supply voltage rise time time until receiver operational PR BBC Sleep to RX t 3*t max 1 µs CNTRL0/CNTROL 1 rise time until receiver operational SR BBC times RX to Sleep t 10 µs max 1 µs CNTRL0/CNTROL 1 fall times time until receiver is in power-down mode RS AGC Engage t 5 µs max 1 µs rise time, -30 dBm signal RFA1 switches from 35 to 5 dB gain AGC AGE Hold-In t C /19.1 min CAGC in pF, t in µs user selected; longer than t AGH AGC AGH PKD PKDET Attack Time Constant t C /4167 min C in pF, t in µs user selected PKA PKD PKD PKA PKDET Decay Time Constant t 1000*t min t and t in µs slaved to attack time PKD PKA PKD PKA PRATE Interval t 0.1 to 5 µs range low data rate mode user selected mode PRI PWIDTH RFA1 t 0.55 to 1 µs range low data rate mode user selected mode PW1 PWIDTH RFA2 t 1.1*t range low data rate mode user selected mode PW2 PW1 PRATE Cycle t 0.1 to 1.1 µs range high data rate mode user selected mode PRC PWIDTH High (RFA1 & RFA2) t 0.05 to 0.55 µs range high data rate mode user selected mode PWH LPF Group Delay t 1750/f max t in µs, f in kHz user selected FGD LPF FGD LPF LPF 3 dB Bandwidth f 1445/R min f in kHz, R in kilohms user selected LPF LPF LPF LPF BBOUT-CMPIN Time Constant t 0.064*C min t in µs, C in pF user selected BBC BBO BBC BBO Table 1 ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 7 of 10

Pin Descriptions Pin Name Description 1 GND1 GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces. 2 VCC1 VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF capacitor, which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information. 3 AGCCAP This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the AGC will hold- in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time t , the capacitor value C AGH AGC is: C = 19.1* t , where t is in µs and C is in pF AGC AGH AGH AGC A ±10% ceramic capacitor should be used at this pin. The value of C given above provides a hold-in time between t AGC AGH and 2.65* t , depending on operating voltage, temperature, etc. The hold-in time is chosen to allow the AGC to ride AGH through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time should not be set too long, or the receiver will be slow in returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional when using OOK modulation with data pulses of at least 30 µs. AGC operation can be defeated by connecting this pin to Vcc. Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 µs. The AGC can be latched on once engaged by connecting a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation depends on a functioning peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down (sleep) mode. 4 PKDET This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordinated with the base-band time constant. For a given base-band capacitor C , the capacitor value C is: BBO PKD C = 0.33* C , where C and C are in pF PKD BBO BBO PKD A ±10% ceramic capacitor should be used at this pin. This time constant will vary between t and 1.5* t with variations PKA PKA in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays through a 200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release function. The AGC hold-in time can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where low data rates and OOK modulation are used, the “dB-below-peak” data slicer and the AGC are optional. In this case, the PKDET pin and the THLD2 pin can be left unconnected, and the AGC pin can be connected to Vcc to reduce the number of external compo- nents needed. The peak detector capacitor is discharged in the receiver power-down (sleep) mode. 5 BBOUT BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor C for internal BBO data slicer operation. The time constant t for this connection is: BBC t = 0.064*C , where t is in µs and C is in pF BBC BBO BBC BBO A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between t and BBC 1.8*t with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend BBC on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A common criteria is to set the time constant for no more than a 20% voltage droop during SP . For this case: MAX C = 70*SP , where SP is the maximum signal pulse width in µs and C is in pF BBO MAX MAX BBO The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output imped- ance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat with supply volt- age and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recommended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin becomes very high, preserving the charge on the coupling capacitor. 6 CMPIN This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance of this pin is 70 K to 100 K. 7 RXDATA RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than Vcc + 200 mV. 8 NC This pin may be left unconnected or may be grounded. ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 8 of 10

9 LPFADJ This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R between this pin and LPF ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f from 4.5 kHz to 1.8 MHz. LPF The resistor value is determined by: R = 1445/ f , where R is in kilohms, and f is in kHz LPF LPF LPF LPF A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f and 1.3* f LPF LPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting. Pin Name Description 10 GND2 GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace. 11 RREF RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF. 12 THLD2 THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor R TH2 between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value (increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak, or 60 mV for a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by: R = 1.67*V, where R is in kilohms and the threshold V is in mV TH2 TH2 A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the dB-below-peak data slicer operation. 13 THLD1 The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R to RREF. The threshold is TH1 increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The value of the resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by: R = 1.11*V, where R is in kilohms and the threshold V is in mV TH1 TH1 For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a THLD1 range of 0 to 90 mV. The resistor value is given by: R = 2.22*V, where R is in kilohms and the threshold V is in mV TH1 TH1 A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for proper AGC operation. 14 PRATE The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the first RF amplifier t is set by a resistor R between this pin and ground. The interval t can be adjusted between 0.1 and PRI PR PRI 5 µs with a resistor in the range of 51 K to 2000 K. The value of R is given by: PR R = 404* t + 10.5, where t is in µs, and R is in kilohms PR PRI PRI PR A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period t from start-to-start PRC of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of R is given by: PR R = 198* t - 8.51, where t is in µs and R is in kilohms PR PRC PRC PR A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5 pF to maintain stability. 15 PWIDTH The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t with a resistor R to ground (the ON pulse PW1 PW width to the second RF amplifier t is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width t PW2 PW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of R is given by: PW R = 404* t - 18.6, where t is in µs and R is in kilohms PW PW1 PW1 PW A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode. 16 VCC2 VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor. 17 CNTRL1 CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is inter- preted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected. ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 9 of 10

SM-20L PCB Pad Layout 5 55 5 2 72 7 7 91 3 1 12 2 . .. . .4600 .3825 .3575 .3175 .2775 .2375 .1975 .1575 .1175 .1025 .0775 0 0 0 0 0 4 7 1 0 1 2 4 0. 0.000. . . Dimensions in inches Note: Specifications subject to change without notice. ©2010-2014 by Murata Electronics N.A., Inc. www.murata.com RX5000 (R) 4/14/15 Page 10 of 10