® RT9625A Dual-Channel Synchronous Rectified MOSFET Driver General Description Features The RT9625A is a high frequency, synchronous rectified,  Drive Four N-MOSFETs for Two-Phase PWM Control two phase MOSFET driver designed for normal MOSFET  Shoot Through Protection driving applications and high performance CPU VR driving  Embedded Bootstrap Diode capabilities.  Support High Switching Frequency Fast Output Rising Time  The RT9625A can be supplied from 4.5V to 13.2V. The Tri-State PWM Input for Output Shutdown  applicable power stage VIN range is from 5V to 23V. The Enable Control  RT9625A also builds in internal power switches to replace Small 16-Lead WQFN Package  external bootstrap diodes. RoHS Compliant and Halogen Free  The RT9625A can support switching frequency efficiently up to 500kHz. The RT9625A has the UGATE and LGATE Applications driving circuits for synchronous rectified DC/DC converter applications. The shoot through protection mechanism is  Core Voltage Supplies for Desktop, Motherboard CPU designed to prevent shoot through between high side and  High Frequency Low Profile DC/DC Converters low side power MOSFETs. The RT9625A has tri-state PWM  High Current Low Voltage DC/DC Converters input with shutdown and EN shutdown functions, which  Core Voltage Supplies for GFX Card can force driver to output low UGATE and LGATE signals. Marking Information The RT9625 comes in a small footprint with WQFN-16L 4x4 package. 06 : Product Code 06 YM YMDNN : Date Code DNN Simplified Application Circuit VIN 12V VCC RT9625A L1 PWM1 PWM1 PHASE1 VOUT PWM2 PWM2 Chip Enable EN1 L2 EN2 PHASE2 GND Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9625A-04 July 2015 www.richtek.com 1

RT9625A Ordering Information Pin Configurations RT9625A (TOP VIEW) Package Type 2 2 2 E E E QW : WQFN-16L 4x4 (W-Type) T S T A A A D G H G N Lead Plating System U P L G Z : ECO (Ecological Element with 16 15 14 13 Halogen Free and Pb free) BOOT2 1 12 VCC Note : GND 2 GND 11 LGATE1 PWM2 3 10 PHASE1 Richtek products are : 17 EN2 4 9 UGATE1  RoHS compliant and compatible with the current require- 5 6 7 8 ments of IPC/JEDEC J-STD-020. 1 1 R 1  Suitable for use in SnPb or Pb-free soldering processes. EN WM PO OT O P B WQFN-16L 4x4 Function Pin Description Pin No. Pin Name Pin Function 1 BOOT2 Bootstrap Power Pins for Channel 2 and Channel 1. This pin powers the high side MOSFET driver. Connect this pin to the junction of the bootstrap 8 BOOT1 capacitor and the cathode of the bootstrap diode. 2, Ground. The exposed pad must be soldered to a large PCB and connected to GND 13 (Exposed Pad) GND for maximum power dissipation. 3 PWM2 PWM Signal Input. Connect this pin to the PWM output of the controller. 6 PWM1 4 EN2 Chip Enable. When this pin is low, both UGATEx and LGATEx are driven to 5 EN1 low. 7 POR Power On Reset Signal. 9 UGATE1 High Side Gate Drive Outputs for channel 1 and channel 2. Connect this pin to Gate of high side power MOSFET. 16 UGATE2 10 PHASE1 Switch Nodes of High Side Driver 1 and Driver 2. Connect this pin to the high side MOSFET Source together with the low side MOSFET Drain and the 15 PHASE2 inductor. 11 LGATE1 Low Side Gate Drive Output for Channel 1 and Channel 2. This pin drives the 14 LGATE2 Gate of low side MOSFET. 12 VCC Supply Input. VCC supplies current for Channel 1 and Channel 2 gate drivers. Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9625A-04 July 2015 2

RT9625A Function Block Diagram VCC POR POR Bootstrap Control Enable BOOT1 EN1 Detect Internal Shoot-Through UGATE1 VDD Protection Turn Off PHASE1 Tri-State Detection PWM1 Detect VCC Shoot-Through LGATE1 Protection GND VCC1 Bootstrap Control Enable BOOT2 EN2 Detect Internal Shoot-Through UGATE2 VDD Protection Turn Off PHASE2 Tri-State Detection PWM2 Detect VCC Shoot-Through LGATE2 Protection GND Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9625A-04 July 2015 www.richtek.com 3

RT9625A Operation POR (Power On Reset) Bootstrap Control POR block detects the voltages at VCC pin. When the Bootstrap control block controls the integrated bootstrap VCC pin voltage is higher than POR rising threshold, POR switch. When LGATEx is high (low side MOSFET is pin output voltage (POR output) is high. POR output is turned on), the bootstrap switch is turned on to charge low when VCC is not higher than POR rising threshold. the bootstrap capacitor connected to BOOTx pin. When When the POR pin voltage is high, UGATEx and LGATEx LGATEx is low (low side MOSFET is turned off), the can be controlled by PWMx input voltage. If the POR pin bootstrap switch is turned off to disconnect VCC pin and voltage is low, both UGATEx and LGATEx will be pulled BOOTx pin. to low. Turn-Off Detection Enable Detect Turn-off detection block detects whether high side When ENx pin input voltage is higher/lower than EN rising MOSFET is turned off by monitoring PHASEx pin voltage. threshold, MOSFET driver is enabled/disabled. When the To avoid shoot through between high side and low side ENx input and POR output are high, UGATEx and LGATEx MOSFETs, low side MOSFET can be turned on only after can be controlled by PWMx input voltage. When ENx high side MOSFET is effectively turned off. input is low, both UGATEx and LGATEx are pulled to low. Shoot-Through Protection Tri-State Detect Shoot-through protection block implements the dead time When both POR block output and ENx pin voltages are when both high side and low side MOSFETs are turned high, UGATEx and LGATEx can be controlled by PWMx off. With shoot-through protection block, high side and input. There are three PWMx input modes, which are high, low side MOSFET are never turned on simultaneously. low, and shutdown state. If PWMx input is within the Thus, shoot through between high side and low side shutdown window, both UGATEx and LGATEx output are MOSFETs is prevented. low. When PWMx input is higher than its rising threshold, UGATEx is high and LGATEx is low. When PWMx input is lower than its falling threshold, UGATEx is low and LGATEx is high. Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9625A-04 July 2015 4

RT9625A Absolute Maximum Ratings (Note 1) Supply Voltage, VCC-------------------------------------------------------------------------------- −0.3V to 15V  BOOTx to PHASEx---------------------------------------------------------------------------------- −0.3V to 15V  PHASEx to GND  DC-------------------------------------------------------------------------------------------------------- −0.3V to 30V < 100ns------------------------------------------------------------------------------------------------- −10V to 35V LGATEx to GND  DC-------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) < 100ns------------------------------------------------------------------------------------------------- −2V to (VCC + 0.3V) UGATEx to GND  DC--------------------------------------------------------------------------------------------------------(V − 0.3V) to (V + 0.3V) PHASE BOOT < 100ns-------------------------------------------------------------------------------------------------(V − 2V) to (V + 0.3V) PHASE BOOT ENx, PWMx to GND--------------------------------------------------------------------------------- −0.3V to 7V  POR to GND------------------------------------------------------------------------------------------- −0.3V to 5V  Power Dissipation, P @ T = 25°C  D A WQFN-16L 4x4 ---------------------------------------------------------------------------------------1.852W Package Thermal Resistance (Note 2)  WQFN-16L 4x4, θ ----------------------------------------------------------------------------------54°C/W JA WQFN-16L 4x4, θ ---------------------------------------------------------------------------------7°C/W JC Lead Temperature (Soldering, 10 sec.)----------------------------------------------------------260°C  Junction Temperature--------------------------------------------------------------------------------150°C  Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C  ESD Susceptibility (Note 3)  HBM (Human Body Model)-------------------------------------------------------------------------2kV Recommended Operating Conditions (Note 4) Supply Voltage, VCC--------------------------------------------------------------------------------4.5V to 13.2V  Input Voltage, (V + VCC)-------------------------------------------------------------------------< 35V  IN Junction Temperature Range----------------------------------------------------------------------- −40°C to 125°C  Ambient Temperature Range----------------------------------------------------------------------- −40°C to 85°C  Electrical Characteristics (VCC= 12V, TA= 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Power Supply Voltage VCC 4.5 -- 13.2 V Power Supply Current IVCC VBOOTx = 12V, PWMx Floating -- 180 -- A Power On Reset (POR) POR Rising Threshold VPOR_r VCC Rising -- 4 4.4 V POR Falling Threshold VPOR_f VCC Falling 3 3.5 -- V POR Pin High Voltage VPOR_H -- 3.5 4 V POR Pin Low Voltage V -- -- 0.5 V POR_L Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9625A-04 July 2015 www.richtek.com 5

RT9625A Parameter Symbol Test Conditions Min Typ Max Unit EN Input ENx Rising Threshold VENH -- 1.3 1.6 V ENx Falling Threshold VENL 0.7 1 -- V PWM Input Maximum Input Current IPWM VPWMx = 0V or 5V -- 160 -- A PWMx Floating Voltage V PWMx = Open -- 1.8 -- V PWM_fl PWMx Rising Threshold V 2.3 2.8 3.2 V PWM_rth PWMx Falling Threshold VPWM_fth 0.7 1.1 1.4 V Timing UGATEx Rising Time tUGATEr 3nF load -- 25 -- ns UGATEx Falling Time tUGATEf 3nF load -- 12 -- ns LGATEx Rising Time t 3nF load -- 24 -- ns LGATEr LGATEx Falling Time t 3nF load -- 10 -- ns LGATEf tUGATEpdh VBOOTx VPHASEx = 12V -- 60 -- ns tUGATEpdl See Timing Diagram -- 22 -- Propagation Delay tLGATEpdh -- 30 -- See Timing Diagram ns tLGATEpdl -- 8 -- Output UGATEx Drive Source R V  V = 12V, I = 100mA -- 1.7 --  UGATEsr BOOT PHASE Source UGATEx Drive Sink R V  V = 12V, I = 100mA -- 1.4 --  UGATEsk BOOT PHASE Sink LGATEx Drive Source R I = 100mA -- 1.6 --  LGATEsr Source LGATEx Drive Sink RLGATEsk ISink = 100mA -- 1.1 --  Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9625A-04 July 2015 6

RT9625A Typical Application Circuit R1 RT9625A R2 12V 2.2 12 VCC2 BOOT1 8 1 C3 VIN C1 1µF R3 C2 12V 1µF 9 2.2 270µF x 2 UGATE1 Q1 L1 10 7 PHASE1 VOUT POR C5 R5 R4 820µF x 3 5 11 0 2.2 EN1 LGATE1 Q2 Chip Enable C4 4 EN2 R6 3.3nF 1 1 C6 BOOT2 1µF VIN 6 R7 PWM1 PWM1 16 2.2 UGATE2 Q3 3 PWM2 PWM2 L2 15 PHASE2 R9 R8 2, 13, 17 (Exposed Pad) GND LGATE2 14 0 Q4 2.2 C7 3.3nF Timing Diagram PWMx tLGATEpdl LGATEx 90% tUGATEpdl 1.5V 1.5V 90% 1.5V 1.5V UGATEx tUGATEpdh tLGATEpdh Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9625A-04 July 2015 www.richtek.com 7

® RT9625A Typical Operating Characteristics Drive Enable Drive Disable UGATE UGATE (50V/Div) (50V/Div) PHASE PHASE (20V/Div) (20V/Div) LGATE LGATE (20V/Div) (20V/Div) EN EN (10V/Div) (10V/Div) VIN = 12V, No Load VIN = 12V, No Load Time (1μs/Div) Time (1μs/Div) PWM Rising Edge PWM Falling Edge PWM PWM (10V/Div) (10V/Div) UGATE UGATE (20V/Div) (20V/Div) LGATE LGATE (10V/Div) (10V/Div) PHASE PHASE (10V/Div) (10V/Div) Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE LGATE (5V/Div) (5V/Div) Full Load Full Load Time (20ns/Div) Time (20ns/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9625A-04 July 2015 www.richtek.com 8

® RT9625A Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE LGATE (5V/Div) (5V/Div) No Load No Load Time (20ns/Div) Time (20ns/Div) Short Pulse UGATE LGATE PHASE (5V/Div) UGATE − PHASE No Load Time (20ns/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9625A-04 July 2015 www.richtek.com 9

RT9625A Application Information The RT9625A is a high frequency, two-channel The PWMx signal is acted as “High” if the signal is above synchronous rectified MOSFET driver containing Richtek's the rising threshold and acted as “Low” if the signal is advanced MOSFET driver technologies. The RT9625A is below the falling threshold. When PWM signal level enters designed to be able to adapt from normal MOSFET driving and remains within the shutdown window, the output drivers applications to high performance CPU VR driving are disabled and both MOSFET gates are pulled and held capabilities. low. If the PWMx signal is left floating, the pin will be kept around 1.8V by the internal divider and provide the PWMx Supply Voltage and Power On Reset controller with a recognizable level. The RT9625A can be utilized under both V = 5V or V CC CC = 12V applications which may happen in different fields of Bootstrap Power Switch electronics application circuits. In terms of efficiency, The RT9625A builds in internal bootstrap power switches higher V equals higher driving voltage of UGATEx/ to replace external bootstrap diode, and this can facilitate CC LGATEx which may result in higher switching loss and PCB design and reduce total BOM cost of the system. lower conduction loss of power MOSFETs. The choice of Hence, no external bootstrap diode is required in real V = 12V or V = 5V can be a tradeoff to optimize applications. CC CC system efficiency. Non-overlap Control The RT9625A controls both high side and low side N- To prevent the overlap of the gate drivers during the MOSFETs of two half-bridge power according to two UGATEx pull low and the LGATEx pull high, the non-overlap external input PWMx control signals. It has Power On circuit monitors the voltages at the PHASEx node and Reset (POR) function which held UGATEx and LGATEx high side gate drive (UGATEx − PHASEx). When the low before the VCC voltage rises to higher than rising PWMx input signal goes low, UGATEx begins to pull low threshold voltage. When V exceeds the POR threshold CC (after propagation delay). Before LGATEx is pulled high, voltage, the voltage at the POR pin will be pulled high. the non-overlap protection circuit ensures that the Enable and Disable monitored voltages have gone below 1.1V. Once the monitored voltages fall below 1.1V, LGATEx begins to turn The RT9625A includes an ENx pin for sequence control. high. By waiting for the voltages of the PHASEx pin and When the ENx pin rises above the V trip point, the ENH high side gate driver to fall below 1.1V, the non-overlap RT9625A begins a new initialization and follows the PWMx protection circuit ensures that UGATEx is low before command to control the UGATEx and LGATEx. When the LGATEx pulls high. ENx pin falls below the V trip point, the RT9625A shuts ENL down and keeps UGATEx and LGATEx low. Also to prevent the overlap of the gate drivers during LGATEx pull low and UGATEx pull high, the non-overlap Tri-state PWM Input circuit monitors the LGATEx voltage. When LGATEx goes After the initialization, the PWMx signal takes the control. below 1.1V, UGATEx goes high after propagation delay. The rising PWMx signal first forces the LGATEx signal to turn low then UGATEx signal is allowed to go high just Driving Power MOSFETs after a non-overlapping time to avoid shoot through current. The DC input impedance of the power MOSFET is The falling of PWMx signal first forces UGATEx to go low. extremely high. When V or V is at 12V or 5V, the gs1 gs2 When UGATEx and PHASEx signal reach a gate draws the current only for few nano-amperes. Thus predetermined low level, LGATEx signal is allowed to turn once the gate has been driven up to “ON” level, the high. current could be negligible. Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9625A-04 July 2015 10

RT9625A However, the capacitance at the gate to source terminal dV C x 12 g2 gs1 I C  (2) should be considered. It requires relatively large currents gs2 gs1 dt t r2 to drive the gate up and down 12V (or 5V) rapidly. It is Before driving the gate of the high side MOSFET up to also required to switch drain current on and off with the 12V, the low side MOSFET has to be off; and the high required speed. The required gate drive currents are side MOSFET will be turned off before the calculated as follows. low side is turned on. From Figure 1, the body diode “D ” 2 d1 s1 VPHASEx L will be turned on before high side MOSFETs turn on. VIN VOUT dV 12 Cgd1 Cgs1 Igd1 = Cgd1 = Cgd1 (3) dt t r1 Igd1 Igs1 Cgd2 d2 Before the low side MOSFET is turned on, the Cgd2 have Ig1 Ig2Igd2 been charged to VIN. Thus, as Cgd2 reverses its polarity g1 g2 D2 and g2 is charged up to 12V, the required current is Igs2 dV VIN 12 Cgs2 s2 Igd2 Cgd2 Cgd2 (4) dt t r2 GND It is helpful to calculate these currents in a typical case. Vg1 Assume a synchronous rectified Buck converter, input VPHASEx +12V voltage V = 12V, V = 12V, V = 12V.The high side IN gs1 gs2 MOSFET is PHB83N03LT whose C = 1660pF, iss C = 380pF, and t = 14ns. The low side MOSFET is rss r PHB95N03LT whose C = 2200pF, C = 500pF and t iss rss t = 30ns, from the equation (1) and (2) we can obtain r Vg2 12V 1660 x 10-12x 12 I  1.428 (A) (5) gs1 14 x 10-9 t 2200 x 10-12x 12 Figure 1. Equivalent Circuit and Waveforms (VCC = 12V) Igs2  30 x 10-9 0.88 (A) (6) from equation. (3) and (4) In Figure 1, the current I and I are required to move the g1 g2 gate up to 12V. The operation consists of charging C , gd1 380 x 10-12x 12 Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from Igd1  14 x 10-9 0.326 (A) (7) gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the C 500 x 10-12x 12+12 gs1 I  0.4 (A) (8) gd2 and Cgs2 are referred as “Ciss” which are the input 30 x 10-9 capacitors. C and C are the capacitors from gate to the total current required from the gate driving source can gd1 gd2 drain of the high side and the low side power MOSFETs, be calculated as following equations. respectively and referred to the data sheets as “Crss” the Ig1 Igs1 Igd1 1.4280.3261.754 (A) (9) reverse transfer capacitance. For example, t and t are r1 r2 I I I 0.880.41.28 (A) (10) the rising time of the high side and the low side power g2 gs2 gd2 MOSFETs respectively, the required current I and I , gs1 gs2 By a similar calculation, we can also get the sink current are shown as below : required from the turned off MOSFET. dV C x 12 g1 gs1 I C  (1) gs1 gs1 dt t r1 Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9625A-04 July 2015 www.richtek.com 11

RT9625A Select the Bootstrap Capacitor CBOOT 1µF 12V Figure 2 shows part of the bootstrap circuit of the RT9625A. The V (the voltage difference between BOOTx CB 10 BOOTx and PHASEx on RT9625A) provides a voltage to the gate 12V VCC UGATEx 2N7002 1µF of the high side power MOSFET. This supply needs to be RT9625A CU 3nF ensured that the MOSFET can be driven. For this, the POR POR capacitance CBOOT has to be selected properly. It is Chip Enable ENx PHASEx 2N7002 determined by the following constraints. PWMx PWNx LGATEx 20 VIN GND C3nLF BOOTx Figure 3. Power Dissipation Test Circuit UGATEx CBOOT + VCB Figure 4 shows the power dissipation of the RT9625A as PHASEx - a function of frequency and load capacitance when V = CC VCC 12V. The value of C and C are the same and the frequency LGATEx U L is varied from 100kHz to 1MHz. GND Power Dissipation vs. Frequency 1000 Figure 2. Part of Bootstrap Circuit of RT9625A 900 In practice, a low value capacitor CBOOT will lead to the W) 800 CU = CL = 3nF m over charging that could damage the IC. Therefore, to n ( 700 minimize the risk of overcharging and to reduce the ripple o 600 on V , the bootstrap capacitor should not be smaller than pati 500 CU = CL = 2nF CB si 0.1μF, and the larger the better. In general design, using Dis 400 1μF can provide better performance. At least one low-ESR er 300 w capacitor should be used to provide good local de-coupling. Po 200 CU = CL = 1nF It is recommended to adopt a ceramic or tantalum 100 VCC = 12V capacitor. 0 0 200 400 600 800 1000 Power Dissipation Frequency (kHz) To prevent driving the IC beyond the maximum Figure 4. Power Dissipation vs. Frequency recommended operating junction temperature of 125°C, The operating junction temperature can be calculated from it is necessary to calculate the power dissipation the power dissipation curves (Figure 4). Assume V = CC appropriately. This dissipation is a function of switching 12V, operating frequency is 200kHz and C = C = 1nF U L frequency and total gate charge of the selected MOSFET. which emulate the input capacitances of the high side Figure 3 shows the power dissipation test circuit. CL and and low side power MOSFETs. From Figure 4, the power CU are the UGATEx and LGATEx load capacitors, dissipation is 100mW. Thus, for example, with the SOP- respectively. The bootstrap capacitor value is 1μF. 8 package, the package thermal resistance θ is 120°C/ JA W. The operating junction temperature is then calculated as : T = (120°C/W x 100mW) + 25°C = 37°C (11) J where the ambient temperature is 25°C. Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9625A-04 July 2015 12

RT9625A Thermal Considerations Layout Consideration For continuous operation, do not exceed absolute Figure 6 shows the schematic circuit of a synchronous maximum junction temperature. The maximum power buck converter to implement the RT9625A. The converter dissipation depends on the thermal resistance of the IC operates from 5V to 12V of input Voltage. package, PCB layout, rate of surrounding airflow, and For the PCB layout, it should be very careful. The power difference between junction and ambient temperature. The circuit section is the most critical one. If not configured maximum power dissipation can be calculated by the properly, it will generate a large amount of EMI. The location following formula : of Q , Q , Lx should be very close. UGx LGx P = (T − T ) / θ D(MAX) J(MAX) A JA Next, the trace from UGATEx, and LGATEx should also where T is the maximum junction temperature, T is be short to decrease the noise of the driver output signals. J(MAX) A the ambient temperature, and θ is the junction to ambient PHASEx signals from the junction of the power MOSFET, JA thermal resistance. carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C For recommended operating condition specifications, the VCC maximum junction temperature is 125°C. The junction to should be connected to GND directly. Furthermore, the ambient thermal resistance, θ , is layout dependent. For bootstrap capacitors (CBOOTx) should always be placed as JA WQFN-16L 4x4 packages, the thermal resistance, θ , is close to the pins of the IC as possible. JA 54°C/W on a standard JEDEC 51-7 four-layer thermal test VIN board. The maximum power dissipation at T = 25°C can 12V A LIN 12V be calculated by the following formula : PD(MAX) = (125°C - 25°C) / (54°C/W) = 1.852W for +CIN CIN2 RVCC CBOOTx BOOTx VCC WQFN-16L 4x4 package RT9625A CVCC The maximum power dissipation depends on the operating VOUT QUGx UGATEx Lx ambient temperature for fixed T and thermal PWMx PWMx J(MAX) PHASEx resistance, θJA. The derating curve in Figure 5 allows the + PHB83N03LT ENx ENx COUT designer to see the effect of rising ambient temperature QLGx PHB95N03LT LGATEx GND on the maximum power dissipation. 2.0 ) Four-Layer PCB W 1.8 Figure 6. Synchronous Buck Converter Circuit n ( o 1.6 ati p 1.4 si s 1.2 Di r 1.0 e w o 0.8 P m 0.6 u m 0.4 xi Ma 0.2 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 5. Derating Curve of Maximum Power Dissipation Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9625A-04 July 2015 www.richtek.com 13

RT9625A Outline Dimension SEE DETAIL A D D2 L 1 E E2 1 1 e b 2 2 A DETAIL A A3 Pin #1 ID and Tie Bar Mark Options A1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.250 0.380 0.010 0.015 D 3.950 4.050 0.156 0.159 D2 2.000 2.450 0.079 0.096 E 3.950 4.050 0.156 0.159 E2 2.000 2.450 0.079 0.096 e 0.650 0.026 L 0.500 0.600 0.020 0.024 W-Type 16L QFN 4x4 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com DS9625A-04 July 2015 14