® RT8284N 2A, 23V, 340kHz Synchronous Step-Down Converter General Description Features The RT8284N is a high efficiency, monolithic synchronous (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) ±±±±±1.5% High Accuracy Feedback Voltage step down DC/DC converter that can deliver up to 2A output (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Input Voltage Range : 4.5V to 23V current from a 4.5V to 23V input supply. The RT8284N's (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) 2A Output Current current mode architecture and external compensation (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Integrated N-MOSFETs allow the transient response to be optimized over a wide (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Current Mode Control range of loads and output capacitors. Cycle-by-cycle (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) 340kHz Fixed Frequency Operation current limit provides protection against shorted outputs (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Output Adjustable Voltage Range : 0.923V to 20V and soft-start eliminates input current surge during start (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Efficiency Up to 95% up. The RT8284N also provides under voltage protection (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Programmable Soft-Start and thermal shutdown protection. The low current (< 3μA) (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Stable with Low ESR Ceramic Output Capacitors shutdown mode provides output disconnection, enabling (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Cycle-by-Cycle Over Current Protection easy power management in battery-powered systems. The (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Input Under Voltage Lockout RT8284N is a available in a SOP-8 and SOP-8 (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Output Under Voltage Protection (Exposed Pad) package. (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Thermal Shutdown Protection RoHS Compliant and Halogen Free (cid:122)(cid:122)(cid:122)(cid:122)(cid:122) Ordering Information Applications RT8284N Package Type Wireless AP/Router (cid:122) S : SOP-8 Set-Top-Box (cid:122) SP: SOP-8 (Exposed Pad-Option 1) Industrial and Commercial Low Power Systems (cid:122) Lead Plating System LCD Monitors and TVs G : Green (Halogen Free and Pb Free) (cid:122) Green Electronics/Appliances Note : (cid:122) Point of Load Regulation of High-Performance DSPs Richtek products are : (cid:122) (cid:96) RoHS compliant and compatible with the current require- Pin Configurations ments of IPC/JEDEC J-STD-020. (cid:96) Suitable for use in SnPb or Pb-free soldering processes. (TOP VIEW) BOOT 8 SS Marking Information VIN 2 7 EN RT8284NGS SW 3 6 COMP RT8284NGS : Product Number GND 4 5 FB RT8284N YMDNN : Date Code GSYMDNN SOP-8 BOOT 8 SS RT8284NGSP VIN 2 7 EN GND SW 3 6 COMP RT8284NGSP : Product Number 9 RT8284N GND 4 5 FB YMDNN : Date Code GSPYMDNN SOP-8 (Exposed Pad) Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS8284N-03 May 2012 www.richtek.com 1

RT8284N Typical Application Circuit VIN 2 VIN BOOT 1 4.5V to 23V CIN CBOOT L 10µF RT8284N 10nF 10µH SW 3 VOUT 3.3V/2A REN 100k 7 R1 EN 26.1k 8 5 COUT SS FB 22µF x 2 CSS CC RC R2 0.1µF 4, 9 (Exposed Pad) 6 3.3nF 13k 10k GND COMP CP Open Recommended Component Selection VOUT (V) R1 (kΩ) R2 (kΩ) RC (kΩ) CC (nF) L (μH) COUT (μF) 8 76.8 10 27 3.3 22 22 x 2 5 45.3 10 20 3.3 15 22 x 2 3.3 26.1 10 13 3.3 10 22 x 2 2.5 16.9 10 9.1 3.3 6.8 22 x 2 1.8 9.53 10 5.6 3.3 4.7 22 x 2 1.2 3 10 3.6 3.3 3.6 22 x 2 Functional Pin Description Pin No. SOP-8 Pin Name Pin Function SOP-8 (Exposed Pad) Bootstrap for High Side Gate Driver. Connect a 10nF or greater 1 1 BOOT ceramic capacitor from BOOT to SW pins. Input Supply Voltage, 4.5V to 23V. Must bypass with a suitably large 2 2 VIN ceramic capacitor. 3 3 SW Phase Node. Connect this pin to external L-C filter. 4, Ground. The exposed pad must be soldered to a large PCB and 4 GND 9 (Exposed Pad) connected to GND for maximum power dissipation. Feedback Input Pin. This pin is connected to the converter output. It is used to set the output of the converter to regulate to the desired 5 5 FB value via an internal resistive voltage divider. For an adjustable output, an external resistive voltage divider is connected to this pin. Compensation Node. COMP is used to compensate the regulation 6 6 COMP control loop. Connect a series RC network from COMP to GND. In some cases, an additional capacitor from COMP to GND is required. Enable Input pin. A logic high enables the converter; a logic low forces the RT8284N into shutdown mode reducing the supply current 7 7 EN to less than 3μA. Attach this pin to VIN with a 100kΩ pull up resistor for automatic startup. Soft-Start Control Input. SS controls the soft-start period. Connect a 8 8 SS capacitor from SS to GND to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 15.5ms . Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS8284N-03 May 2012 2

RT8284N Function Block Diagram VIN Internal Regulator Oscillator Current Sense Shutdown Slope Comp Amplifier Comparator VA VCC Foldback + VA 1.2V + Control - - 0.5V + BOOT Lockout - S Q 130mΩ Comparator UV 5k Comparator SW EN - + 2.7V + - R Q 130mΩ 3V VCC CoCmuprraernatt or GND 6µA SS + 0.923V + - Error Amp FB COMP Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS8284N-03 May 2012 www.richtek.com 3

RT8284N Absolute Maximum Ratings (Note 1) Supply Voltage, VIN ----------------------------------------------------------------------------------------------- −0.3V to 25V (cid:122) Input Voltage, SW-------------------------------------------------------------------------------------------------- −0.3V to (V + 0.3V) (cid:122) IN <20ns ----------------------------------------------------------------------------------------------------------------- −3V to (V + 3V) IN V − V --------------------------------------------------------------------------------------------------------- −0.3V to 6V (cid:122) BOOT SW Other Pins Voltages ----------------------------------------------------------------------------------------------- −0.3V to 6V (cid:122) Power Dissipation, P @ T = 25°C (cid:122) D A SOP-8----------------------------------------------------------------------------------------------------------------- 1.111W SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------------- 1.333W Package Thermal Resistance (Note 2) (cid:122) SOP-8, θ ----------------------------------------------------------------------------------------------------------- 90°C/W JA SOP-8 (Exposed Pad), θ --------------------------------------------------------------------------------------- 75°C JA SOP-8 (Exposed Pad), θ -------------------------------------------------------------------------------------- 15°C JC Junction Temperature---------------------------------------------------------------------------------------------- 150°C (cid:122) Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------ 260°C (cid:122) Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C (cid:122) ESD Susceptibility (Note 3) (cid:122) HBM (Human Body Model)--------------------------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 4) Supply Voltage, VIN ----------------------------------------------------------------------------------------------- 4.5V to 23V (cid:122) Junction Temperature Range------------------------------------------------------------------------------------- −40°C to 125°C (cid:122) Ambient Temperature Range------------------------------------------------------------------------------------- −40°C to 85°C (cid:122) Electrical Characteristics (VIN = 12V, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Supply Current V = 0V -- 0.5 3 μA EN Supply Current ICC VEN = 3 V, VFB = 1V -- 0.8 1.2 mA Feedback Voltage VFB 4.5V ≤ VIN ≤ 23V 0.909 0.923 0.937 V Error Amplifier Transconductance GEA ΔIC = ±10μA -- 940 -- μA/V High Side Switch-On Resistance RDS(ON)1 -- 130 -- mΩ Low Side Switch-On Resistance RDS(ON)2 -- 130 -- mΩ High Side Switch Leakage Current VEN = 0V, VSW = 0V -- 0 10 μA Upper Switch Current Limit Min.Duty Cycle, VBOOT−SW = 4.8V -- 4.3 -- A Low Switch Current Limit From Drain to Source -- 1.3 -- A COMP to Current Sense Transconductance GCS -- 4 -- A/V Oscillator Frequency f 300 340 380 kHz OSC1 Short Circuit Oscillation f V = 0V -- 100 -- kHz Frequency OSC2 FB Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS8284N-03 May 2012 4

RT8284N Parameter Symbol Test Conditions Min Typ Max Unit Maximum Duty Cycle DMAX VFB = 0.7V -- 93 -- % Minimum On-Time t -- 100 -- ns ON EN Input Threshold Logic-High VIH 2.7 -- 5.5 V Voltage Logic-Low V -- -- 0.4 IL Input Under Voltage Lockout Threshold VUVLO VIN Rising 3.8 4.2 4.5 V Input Under Voltage Lockout Hysteresis ΔV -- 320 -- mV UVLO Soft-Start Current I V = 0V -- 6 -- μA SS SS Soft-Start Period tSS CSS = 0.1μF -- 15.5 -- ms Thermal Shutdown (Note 5) TSD -- 150 -- °C Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.. Note 5. Guaranteed by design. Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS8284N-03 May 2012 www.richtek.com 5

RT8284N Typical Operating Characteristics Efficiency vs. Output Current Reference Voltage vs. Input Voltage 100 0.940 90 0.935 ) 7800 VVIINN == 142.5VV ge (V 0.930 y (%) 60 VIN = 23V Volta 0.925 c 50 e 0.920 n c e n Effici 3400 efere 0.915 R 0.910 20 0.905 10 VOUT = 3.3V 0 0.900 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 4 6 8 10 12 14 16 18 20 22 24 Output Current (A) Input Voltage (V) Reference Voltage vs. Temperature Output Voltage vs. Output Current 0.940 3.36 3.35 0.935 3.34 V) 0.930 ) 3.33 ge ( 0.925 e (V 3.32 Volta 0.920 oltag 33..3301 erence 0.915 Output V 33..2289 VVVIIINNN === 12423.5VVV ef 0.910 3.27 R 3.26 0.905 3.25 VOUT = 3.3V 0.900 3.24 -50 -25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Temperature (°C) Output Current (A) Frequency vs. Input Voltage Frequency vs. Temperature 380 380 370 370 z) 1 360 z) 1 360 kH 350 kH 350 y ( y ( c 340 c 340 n n e e qu 330 qu 330 e e Fr 320 Fr 320 310 310 VOUT = 3.3V, IOUT = 0A VOUT = 3.3V, VIN = 12V, IOUT = 0A 300 300 4 6 8 10 12 14 16 18 20 22 24 -50 -25 0 25 50 75 100 125 Input Voltage (V) Temperature (°C) Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS8284N-03 May 2012 6

RT8284N Current Limit vs. Temperature Load Transient Response 6.0 5.5 VOUT (100mV/Div) ) A 5.0 mit ( Li 4.5 nt e urr 4.0 C IOUT (1A/Div) 3.5 VIN = 12V, VOUT = 3.3V VIN = 12V, VOUT = 3.3V, IOUT = 0A to 2A 3.0 -50 -25 0 25 50 75 100 125 Time (100μs/Div) Temprature (°C) Load Transient Response Switching VOUT (10mV/Div) VOUT (100mV/Div) IL (1A/Div) VSW (10V/Div) IOUT (1A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 1A to 2A VIN = 12V, VOUT = 3.3V, IOUT = 2A Time (100μs/Div) Time (1μs/Div) Power On from V Power Off from V IN IN VIN VIN (5V/Div) (5V/Div) VOUT VOUT (2V/Div) (2V/Div) IL IL (1A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 2A (1A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 2A Time (10ms/Div) Time (10ms/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS8284N-03 May 2012 www.richtek.com 7

RT8284N Power On from EN Power Off from EN VEN VEN (2V/Div) (2V/Div) VOUT VOUT (2V/Div) (2V/Div) (2IAO/UDTiv) IOUT (2A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 2A VIN = 12V, VOUT = 3.3V, IOUT = 2A Time (10ms/Div) Time (10ms/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS8284N-03 May 2012 8

RT8284N Application Information The RT8284N is a synchronous high voltage buck converter Soft-Start that can support the input voltage range from 4.5V to 23V The RT8284N contains an external soft-start clamp that and the output current can be up to 2A. gradually raises the output voltage. The soft-start timing can be programmed by the external capacitor between Output Voltage Setting SS pin and GND. The chip provides a 6μA charge current The resistive voltage divider allows the FB pin to sense for the external capacitor. If 0.1μF capacitor is used to the output voltage as shown in Figure 1. set the soft-start, the period will be 15.5ms (typ.). VOUT Chip Enable Operation R1 The EN pin is the chip enable input. Pulling the EN pin FB low (<0.4V) will shut down the device. During shutdown RT8284N R2 mode, the RT8284N quiescent current drops to lower than GND 3μA. Driving the EN pin high ( > 2.7V, < 5.5V) will turn on the device again. For external timing control (e.g.RC), Figure 1. Output Voltage Setting the EN pin can also be externally pulled high by adding a The output voltage is set by an external resistive voltage R * resistor and C * capacitor from the VIN pin EN EN divider according to the following equation : (see Figure 5). ⎛ R1⎞ VOUT = VFB⎜1+ ⎟ An external MOSFET can be added to implement digital ⎝ R2⎠ control on the EN pin when no system voltage above 2.5V where V is the feedback reference voltage 0.923V (typ.). FB is available, as shown in Figure 3. In this case, a 100kΩ External Bootstrap Diode pull-up resistor, REN, is connected between VIN and the Connect a 10nF low ESR ceramic capacitor between the EN pin. MOSFET Q1 will be under logic control to pull BOOT pin and SW pin. This capacitor provides the gate down the EN pin. driver voltage for the high side MOSFET. 2 1 Ibt eitsw reeecno manm eenxdteerdn atol 5aVd da nadn eBxOteOrnTa pl ibno ofotsr treafpfic dieiondcey Chip EnaVbIlNe 1R0E0Nk CIN 7VEINNRT828B4ONSOWT3 CBOOLT VOUT improvement when input voltage is lower than 5.5V or duty Q1 R1 COUT ratio is higher than 65% .The bootstrap diode can be a 8SS FB5 low cost one such as IN4148 or BAT54. The external 5V CSS 4, 6 CC RC R2 9 (Exposed Pad) COMP can be a 5V fixed input from system or a 5V output of the GND CP RT8284N. Note that the external boot voltage must be lower than 5.5V Figure 3. Enable Control Circuit for Logic Control with Low Voltage 5V To prevent enabling circuit when V is smaller than the IN V target value, a resistive voltage divider can be placed OUT BOOT between the input voltage and ground and connected to RT8284N 10nF the EN pin to adjust IC lockout threshold, as shown in SW Figure 4. For example, if an 8V output voltage is regulated from a 12V input voltage, the resistor, R , can be EN2 selected to set input lockout threshold larger than 8V. Figure 2. External Bootstrap Diode Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS8284N-03 May 2012 www.richtek.com 9

RT8284N 1V2IVN REN1 1C0INµF2VINRT828B4ONOT1 CBOOT V8OVUT Table 2. SuAggpepslitceadt iIonnd uCcirtcoursit for Typical 100k 7EN SW3 L Component Series Dimensions REN2 R1 COUT Supplier (mm) TDK VLF10045 10 x 9.7 x 4.5 5 8 FB SS CSS 4, 6 CC RC R2 TDK SLF12565 12.5 x 12.5 x 6.5 9 (Exposed Pad) COMP TAIYO GND CP NR8040 8 x 8 x 4 YUDEN Figure 4. The Resistors can be Selected to Set IC Lockout Threshold CIN and COUT Selection The input capacitance, C is needed to filter the IN, Hiccup Mode trapezoidal current at the source of the high side MOSFET. For the RT8284N, Hiccup Mode Under Voltage Protection To prevent large ripple current, a low ESR input capacitor (UVP) is provided. When the FB voltage, VFB, drops below sized for the maximum RMS current should be used. The 0.5V, the UVP function will be triggered and the RT8284N RMS current is given by : will shut down for a period of time and then recover automatically. The Hiccup Mode UVP can reduce input IRMS = IOUT(MAX) VVOIUNT VVOIUNT −1 current in short-circuit conditions. This formula has a maximum at V = 2V , where IN OUT I = I / 2. This simple worst-case condition is RMS OUT Inductor Selection commonly used for design because even significant The inductor value and operating frequency determine the deviations do not offer much relief. ripple current according to a specific input and output Choose a capacitor rated at a higher temperature than voltage. The ripple current ΔI increases with higher V L IN required. Several capacitors may also be paralleled to and decreases with higher inductance. meet size or height requirements in the design. ΔIL =⎡⎢⎣VfO×ULT⎤⎥⎦×⎡⎢⎣1−VVOIUNT⎤⎥⎦ For the input capacitor, one 10μF low ESR ceramic Having a lower ripple current reduces not only the ESR capacitors are recommended. For the recommended losses in the output capacitors but also the output voltage capacitor, please refer to table 3 for more detail. ripple. High frequency with small ripple current can achieve The selection of C is determined by the required ESR OUT highest efficiency operation. However, it requires a large to minimize voltage ripple. inductor to achieve this goal. Moreover, the amount of bulk capacitance is also a key For the ripple current selection, the value of ΔI = 0.24(I ) L MAX for COUT selection to ensure that the control loop is stable. will be a reasonable starting point. The largest ripple Loop stability can be checked by viewing the load transient current occurs at the highest V . To guarantee that the IN response as described in a later section. ripple current stays below the specified maximum, the The output ripple, ΔV , is determined by : OUT inductor value should be chosen according to the following ⎡ 1 ⎤ equation : ΔVOUT ≤ΔIL⎢⎣ESR+8fCOUT⎥⎦ L =⎡⎢ VOUT ⎤⎥×⎡⎢1− VOUT ⎤⎥ The output ripple will be highest at the maximum input ⎣f×ΔIL(MAX)⎦ ⎣ VIN(MAX)⎦ voltage since ΔI increases with input voltage. Multiple The inductor's current rating (caused a 40°C temperature L capacitors placed in parallel may be needed to meet the rising from 25°C ambient) should be greater than the ESR and RMS current handling requirement. Dry tantalum, maximum load current and its saturation current should special polymer, aluminum electrolytic and ceramic be greater than the short circuit peak current limit. Please capacitors are all available in surface mount packages. see Table 2 for the inductor selection reference. Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS8284N-03 May 2012 10

RT8284N Special polymer capacitors offer very low ESR value. Checking Transient Response However, it provides lower capacitance density than other The regulator loop response can be checked by looking types. Although Tantalum capacitors have the highest at the load transient response. Switching regulators take capacitance density, it is important to only use types that several cycles to respond to a step in load current. When pass the surge test for use in switching power supplies. a load step occurs, V immediately shifts by an amount OUT Aluminum electrolytic capacitors have significantly higher equal to ΔI (ESR) and C also begins to be charge LOAD OUT ESR. However, it can be used in cost-sensitive applications or discharged to generate a feedback error signal for the for ripple current rating and long term reliability regulator to return V to its steady-state value. During OUT considerations. Ceramic capacitors have excellent low this recovery time, V can be monitored for overshoot or OUT ESR characteristics but can have a high voltage coefficient ringing that would indicate a stability problem. and audible piezoelectric effects. The high Q of ceramic EMI Consideration capacitors with trace inductance can also lead to significant ringing. Since parasitic inductance and capacitance effects in PCB circuitry would cause a spike voltage on SW pin when Higher values, lower cost ceramic capacitors are now high-side MOSFET is turned-on/off, this spike voltage on becoming available in smaller case sizes. Their high ripple SW may impact on EMI performance in the system. In current, high voltage rating and low ESR make them ideal order to enhance EMI performance, there are two methods for switching regulator applications. However, care must to suppress the spike voltage. One way is by placing an be taken when these capacitors are used at input and R-C snubber between SW and GND and locating them as output. When a ceramic capacitor is used at the input close as possible to the SW pin (see Figure 5). Another and the power is supplied by a wall adapter through long method is by adding a resistor in series with the bootstrap wires, a load step at the output can induce ringing at the capacitor, C , but this method will decrease the driving input, V . At best, this ringing can couple to the output BOOT IN capability to the high side MOSFET. It is strongly and be mistaken as loop instability. At worst, a sudden recommended to reserve the R-C snubber during PCB inrush of current through the long wires can potentially layout for EMI improvement. Moreover, reducing the SW cause a voltage spike at V large enough to damage the IN trace area and keeping the main power in a small loop will part. be helpful on EMI performance. For detailed PCB layout guide, please refer to the section Layout Considerations. VIN 2 VIN BOOT 1 RBOOT* 4.5V to 23V CIN CBOOT L REN* 10µF RT8284NSW 3 10nF 10µH VOUT Chip Enable 7 3.3V/2A EN CEN* RS* R1 COUT CS* 26.1k 22µFx2 8 SS 5 FB C0.S1SµF 9 (Exposed Pad4), GND COMP 6 3.C3CnF 1R3Ck 1R02k * : Optional NCCP Figure 5. Reference Circuit with Snubber and Enable Timing Control Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS8284N-03 May 2012 www.richtek.com 11

RT8284N Thermal Considerations (Exposed Pad) pad (Figure 6.a), θ is 75°C/W. Adding JA For continuous operation, do not exceed absolute copper area of pad under the SOP-8 (Exposed Pad) (Figure maximum operation junction temperature 125°C. The 6.b) reduces the θJA to 64°C/W. Even further, increasing maximum power dissipation depends on the thermal the copper area of pad to 70mm2 (Figure 6.e) reduces the resistance of IC package, PCB layout, the rate of θJA to 49°C/W. surroundings airflow and temperature difference between The maximum power dissipation depends on operating junctions to ambient. The maximum power dissipation can ambient temperature for fixed T and thermal J(MAX) be calculated by following formula : resistance θ . The of de-rating curves in Figure 7 allow JA P = (T − T ) / θ the designer to see the effect of rising ambient temperature D(MAX) J(MAX) A JA on the maximum power dissipation allowed. where T is the maximum operation junction J(MAX) 2.2 temperature, TA is the ambient temperature and the θJA Four-Layer PCB 2.0 is the junction to ambient thermal resistance. Copper Area 1.8 W) 70mm2 Fmoarx riemcuomm mjuenncdtioend toepmerpaetrinagtu croen isd i1ti2o5n°sC s.p Tehceifi jcuanticotnio,n th teo on ( 11..46 5300mmmm22 ati 10mm2 ambient thermal resistance θ is layout dependent. For p 1.2 JA si Min.Layout SOP-8 (Exposed Pad) package, the thermal resistance Dis 1.0 SOP-8 θJA is 75°C/W on the standard JEDEC 51-7 four layers wer 00..68 thermal test board. For SOP-8 package, the thermal o P 0.4 resistance θ is 90°C/W on the standard JEDEC 51-7 JA 0.2 four layers thermal test board. The maximum power 0.0 dissipation at TA = 25°C can be calculated by following 0 25 50 75 100 125 formula : Ambient Temperature (°C) P = (125°C − 25°C) / (75°C/W) = 1.33W Figure 7. Derating Curve of Maximum Power Dissipation D(MAX) (min. copper area PCB layout with SOP-8 Exposed Pad) P = (125°C − 25°C) / (49°C/W) = 2.04W D(MAX) (70mm2 copper area PCB layout with SOP-8 Exposed Pad) P = (125°C − 25°C) / (90°C/W) = 1.11W D(MAX) (min. copper area PCB layout with SOP-8) The thermal resistance θ of SOP-8 (Exposed Pad) is JA (a) Copper Area = (2.3 x 2.3) mm2, θ = 75°C/W JA determined by the package architecture design and the PCB layout design. However, the package architecture design had been designed. If possible, it's useful to increase thermal performance by the PCB layout copper design. The thermal resistance θ can be decreased by adding JA copper area under the exposed pad of SOP-8 (Exposed Pad) package. As shown in Figure 6, the amount of copper area to which (b) Copper Area = 10mm2, θ = 64°C/W JA the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS8284N-03 May 2012 12

RT8284N Layout Considerations For best performance of the RT8284N, the following layout guidelines must be strictly followed. (cid:96) Input capacitor must be placed as close to the IC as possible. (c) Copper Area = 30mm2 , θJA = 54°C/W (cid:96) SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. (cid:96) The feedback components must be connected as close to the device as possible Input capacitor must be placed The feedback components as close to the IC as possible. must be connected as close to the device as possible. GND VIN SW GND (d) Copper Area = 50mm2 , θJA = 51°C/W CIN CSS CC BOOT 8 SS RENVIN VIN 2 GND 7 EN CP RC SW 3 6 COMP RS CS GND 4 9 5 FB R1 COUT R2 L1 VOUT SW should be connected to inductor by wide and short trace. Keep sensitive VOUT components away from this trace. GND Figure 8. PCB Layout Guide (e) Copper Area = 70mm2 , θ = 49°C/W JA Figure 6. Themal Resistance vs. Copper Area Layout Design Table 3. Suggested Capacitors for C and C IN OUT Location Component Supplier Part No. Capacitance (μF) Case Size C MURATA GRM31CR61E106K 10 1206 IN C TDK C3225X5R1E106K 10 1206 IN C TAIYO YUDEN TMK316BJ106ML 10 1206 IN C MURATA GRM31CR60J476M 47 1206 OUT C TDK C3225X5R0J476M 47 1210 OUT C MURATA GRM32ER71C226M 22 1210 OUT C TDK C3225X5R1C22M 22 1210 OUT Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS8284N-03 May 2012 www.richtek.com 13

RT8284N Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS8284N-03 May 2012 14

RT8284N H A M EXPOSED THERMAL PAD Y (Bottom of Package) J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Option 1 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Option 2 Y 3.000 3.500 0.118 0.138 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS8284N-03 May 2012 www.richtek.com 15