® RT7736 SmartJitterTM PWM Flyback Controller General Description Features The RT7736 series is a high performance enhanced PWM  Proprietary SmartJitterTM Technology flyback controller with proprietary SmartJitterTM technology.  Reducing EMI Emissions of SMPS The innovative SmartJitterTM technology not only reduces  Output Jittering Ripple Elimination EMI emissions of SMPS when the system enters burst  No Load Input Power Under 100mW (RT7736G/R/L/E) switching green mode, but also eliminates output jittering  Accurate Over Load Protection ripple.  UVLO 9V/14.5V PRO Pin for External Arbitrary OVP/OTP  The RT7736 is a current mode PWM controller including IC ON/OFF Control (RT7736G/R/L)  built-in slope compensation, internal Leading Edge BNO Pin for Brown-In/Out (RT7736B/D/F)  Blanking (LEB) and cycle-by-cycle current limit. It provides Soft Driving for EMI Noise Reduction  excellent green power performance, especially under light Driver Capability : 300mA/−−−−−300mA  load and no load conditions. It allows for simpler design High Noise Immunity  and reduces external component count. RoHS Compliant and Halogen Free  This controller integrates comprehensive safety protection functions for robust designs including input Under-Voltage Applications Lockout (UVLO), Over-Voltage Protection (OVP), Over- Switching AC/DC Adaptor  Load Protection (OLP), Secondary Rectifier Short DVD Open Frame Power Supply  Protection (SRSP), CS pin open protection and cycle-by- Set-Top Box (STB)  cycle current limit. ATX Standby Power  The RT7736 is a cost-effective and compact solution for TV/Monitor Standby Power  NB adaptor applications. It is available in the SOT-23-6 PC Peripherals  package. NB Adaptor  Simplified Application Circuit Vo+ + + AC Mains (90V to 265V) Vo- VDD PRO GATE COMP RT7736 CS GND Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 1

RT7736 Ordering Information RT7736 Package Type Note : E : SOT-23-6 Richtek products are : Lead Plating System  RoHS compliant and compatible with the current require- G : Green (Halogen Free and Pb Free) ments of IPC/JEDEC J-STD-020. RT7736 Version (Refer to Version Table)  Suitable for use in SnPb or Pb-free soldering processes. Marking Information RT7736GGE RT7736RGE IFF= : Product Code 2B= : Product Code IFF=DNN 2B=DNN DNN : Date Code DNN : Date Code RT7736LGE RT7736EGE 09= : Product Code 0F= : Product Code 09=DNN 0F=DNN DNN : Date Code DNN : Date Code RT7736BGE RT7736DGE 00= : Product Code 0N= : Product Code 00=DNN 0N=DNN DNN : Date Code DNN : Date Code RT7736FGE 0P= : Product Code 0P=DNN DNN : Date Code RT7736 Version Table Version RT7736G RT7736R RT7736L RT7736E RT7736B RT7736D RT7736F Frequency 65kHz 65kHz 65kHz 65kHz 65kHz 65kHz 65kHz OLP Delay 56ms 56ms 56ms 56ms 56ms 88ms 64ms Time Auto Auto Auto Auto Auto Internal OVP Latch Latch Recovery Recovery Recovery Recovery Recovery Auto Auto Auto Auto Auto Auto Auto OLP & SRSP Recovery Recovery Recovery Recovery Recovery Recovery Recovery Auto PRO Pin High Latch Latch Latch X X X Recovery Auto Auto Auto PRO Pin Low Latch X X X Recovery Recovery Recovery External OTP Auto Auto Latch Latch X X X by PRO Recovery Recovery External X X X X ○ ○ ○ Brown-In/Out Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 2

RT7736 Pin Configurations (TOP VIEW) GATE VDD CS GATE VDD CS 6 5 4 6 5 4 2 3 2 3 GNDCOMP PRO GNDCOMP BNO RT7736G/R/L/E RT7736B/D/F SOT-23-6 SOT-23-6 Functional Pin Description Pin No. Pin Name Pin Function 1 GND Ground of the Controller. Feedback Voltage Input. Connect an opto-coupler to close the control loop and 2 COMP achieve output voltage regulation. PRO Protection Input for OVP, OTP or ON/OFF Control. (RT7736G/R/L/E) 3 BNO Brown-In/Out Detection Input for RT7736B/D/F Only. Current Sense Input. The current sense resistor between this pin and GND is used for 4 CS current limit setting. Supply Voltage Input. The controller will be enabled when VDD exceeds VTH_ON 5 VDD (14.5V typ.) and disabled when VDD decreases lower than VTH_OFF (9V typ.) 6 GATE Gate Driver Output for External Power MOSFET. Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 3

RT7736 Function Block Diagram VDD + VTH_H - IBias VTH_OTP + OVP + PRO - - 27V VTH_L + - OTP POR Secondary Rectifier Shutdown Short Protection 2V - Logic UVLO + + - 9V/14.5V Counter COMP Open Bias & Sensing Bandgap OLP TOLP : 56ms Oscillator Constant Dmax Power 5.2V Soft Driver S Q GATE - COMP - R + PWM Comparator CS Slope Ramp COMP Burst Switching Green VBURL Mode VBURH LEB X3 VDD GND Figure 1. Block Diagram for RT7736G, RT7736R, RT7736L and RT7736E Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 4

RT7736 VDD OVP + VBIN_TH/VBNO_TH + - 27V BNO - Secondary Rectifier OTP POR Short Protection Shutdown 2V - Logic + UVLO + - 9V/14.5V Counter COMP Open Sensing Bias & Bandgap OLP TOLP : 56ms (RT7736B) Oscillator TOLP : 88ms (RT7736D) TOLP : 64ms (RT7736F) Dmax Constant 5.2V Power Soft Driver S Q GATE - COMP - R + PWM Comparator CS Slope Ramp COMP Burst Switching Green VBURL Mode VBURH LEB X3 VDD GND Figure 2. Block Diagram for RT7736B, RT7736D and RT7736F Operation Burst Switching Green Mode then force switching at a very low level to supply energy to VDD pin. VDD holdup mode is also improved to hold up The burst mode is designed to reduce switching loss. V by less switching cycles. This mode is very useful When the output load reduces, and the V drops and DD COMP for reducing start-up resistor loss and keeping start-up reaches V , the controller will cease switching. After BURL time within specification. This function makes bias winding output voltage decreases and the V goes up to V , COMP BURH design and transient design easier. the switching will be resumed. Oscillator VDD Holdup Mode The oscillator runs at 65kHz and features frequency Under very light load conditions, the V may drop down DD jittering function. Its jittering depth is Δf with about T to turn-off threshold voltage. To avoid this situation when JIT envelope frequency at f . It also generates slope V drops to a set threshold, V , the hysteresis OSC DD DD_ET compensation saw-tooth, maximum duty cycle pulse and comparator will bypass PWM and burst mode loop, and overload protection slope. Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 5

RT7736 Leading Edge Blanking (LEB) Feedback Open and Opto-Coupler Short To prevent unexpectedly gate switching interruption from If the output voltage feedback loop is open or the opto- the initial spike on CS pin, the LEB delay is designed to coupler is shorted, the OVP/OLP function will be triggered block this spike at the beginning of gate switching. depending on which one occurs first. Gate Driver Secondary Rectifier Short Protection A totem pole gate driver is designed to meet both EMI The current spike during secondary rectifier short test is and efficiency requirements in low power applications. An extremely high because of the saturated main transformer. internal pull-low circuit is activated after pretty low V to Meanwhile, the transformer acts like a leakage inductance. DD prevent external MOSFET from accidentally turning on During high line, the current in power MOSFET is during UVLO. sometimes too high for OLP delay time. To offer better and easier protection design, the RT7736 will shut down PRO Pin (RT7736G/R/L/E) after a few of cycles before fuse is impacted. The RT7736G/R/L/E features a PRO pin, and it can be applied for external arbitrary OVP or OTP applications Output Short Protection (RT7736G/R/L/E), and also can be applied for IC ON/OFF The RT7736 implements output short protection by control (RT7736G/R/L). detecting GATE width with delay time. It could minimize the power loss and temperature during output short, BNO Pin (RT7736B/D/F) especially at high line input voltage. The RT7736B/D/F features a BNO pin, and it can be applied for external arbitrary brown-in/out. The BNO pin is connected to the AC line input or bulk capacitor with a resistive divider to achieve brown-in/out protection. Cycle-by-Cycle Current Limit This is a basic but very useful function and it can be implemented easily in current mode controller. Over-Load Protection In over load conditions, long time current limit will lead to system thermal stress problem. To further protect the system, the RT7736 is designed with a proprietary prolonged turn-off period during hiccup. The power loss and temperature during OLP will be averaged to an acceptable level over the ON/OFF cycle. CS Pin Open Protection When the CS pin is opened, the controller will shut down after a few cycles. Over-Voltage Protection Output voltage can be roughly sensed by the VDD pin. If the sensed voltage reaches V threshold, the controller OVP will shut down after deglitch delay. The controller will resume once the fault is removed. Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 6

RT7736 Absolute Maximum Ratings (Note 1) Supply Input Voltage, VDD to GND------------------------------------------------------------------------------------- −0.3V to 30V  GATE to GND --------------------------------------------------------------------------------------------------------------- −0.3V to 16.5V  PRO, BNO, COMP, CS to GND ---------------------------------------------------------------------------------------- −0.3V to 6.5V  Power Dissipation, P @ T = 25°C  D A SOT-23-6 --------------------------------------------------------------------------------------------------------------------- 0.38W Package Thermal Resistance (Note 2)  SOT-23-6, θ ---------------------------------------------------------------------------------------------------------------- 260.7°C/W JA Junction Temperature------------------------------------------------------------------------------------------------------ 150°C  Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------------- 260°C  Storage Temperature Range --------------------------------------------------------------------------------------------- −65°C to 150°C  ESD Susceptibility (Note 3)  HBM (Human Body Model)----------------------------------------------------------------------------------------------- 3kV MM (Machine Model) ------------------------------------------------------------------------------------------------------ 250V Recommended Operating Conditions (Note 4) Supply Input Voltage, VDD----------------------------------------------------------------------------------------------- 12V to 25V  Junction Temperature Range--------------------------------------------------------------------------------------------- −40°C to 125°C  Ambient Temperature Range--------------------------------------------------------------------------------------------- −40°C to 85°C  Electrical Characteristics (VDD = 15V, TA= 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VDD Section V Over-Voltage Protection Level V 26 27 28 V DD OVP V Zener Clamp V 29 -- -- V DD Z On Threshold Voltage VTH_ON 13.5 14.5 15.5 V Off Threshold Voltage VTH_OFF 8.5 9 9.5 V Disable Brown-in Detection to V 11 12 13 V DD_BNI Avoid Start-up Failed VDD Holdup Mode Entry Point VDD_ET VCOMP < 1.3V 9.5 10 10.5 V VDD Holdup Mode Ending Point VDD_ED VCOMP < 1.3V 10 10.5 11 V Latch-off Clamping Voltage VDD_LH -- 5.5 -- V Threshold Voltage for Latch-off V -- 5 -- V Release LH_OFF V < V  0.1V, Start-up Current I DD TH_ON -- 5 10 A DD_ST T = 40°C to 80°C A Latch-off Operating Current IDD_LH TA = 40°C to 80°C 2 -- 10 A V = 15V, GATE pin open, Operating Supply Current IDD_OP1 DD -- 1 -- mA V = 2.5V COMP V = 15V, GATE pin open, Operating Supply Current IDD_OP2 DD -- 0.9 -- mA V = 1.7V COMP I Sinking Current of Waiting For RT7736B/D/F ; V = 15V, DD IDD_BNI DD 100 150 200 A Brown-in After Start-up GATE and COMP pin open C opyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 7

RT7736 Parameter Symbol Test Conditions Min Typ Max Unit During entering auto recovery IDD Sinking Current IDD_ARP 300 400 500 A protection Oscillator Section Normal PWM Frequency fOSC VCOMP > VBS_ET 60 65 70 kHz Maximum Duty Cycle DCYMAX 70 75 80 % Minimum Burst Switching Green fBS_MIN 18.5 22 25.5 kHz Mode Frequency PWM Frequency Jittering Range f -- ±6 -- % PWM Frequency Jittering Period TJIT -- 16 -- ms Frequency Variation Versus VDD fDV VDD = 9V to 23V -- -- 2 % Deviation Frequency Variation Versus fDT TA = 30°C to105°C -- -- 5 % Temperature Deviation COMP Input Section Open Loop Voltage VCOMP_OP COMP pin open 5 5.2 5.4 V Short Circuit Current of COMP IZERO VCOMP = 0V 0.24 0.29 0.34 mA RT7736G/R/L/E/B -- 56 -- Delay Time of COMP Open-loop TOLP fOSC = 65kHz RT7736D -- 88 -- ms Protection RT7736F -- 64 -- Burst Switching Green Mode Entry VBS_ET 2.3 2.35 2.4 V Voltage Burst Switching Green Mode VBS_ED 2.1 2.15 2.2 V Ending Voltage Delay Time of Output Short fOSC = 65kHz, TD_OSP -- 8 -- ms Protection RT7736G/R/L/E/B Current Sense Section Maximum Current Limit VCS_MAX (Note 5) 1.05 1.1 1.15 V Leading Edge Blanking Time TLEB (Note 5) 150 250 350 ns Internal Propagation Delay Time TPD (Note 5) -- 100 -- ns Minimum On-Time TON_MIN 250 350 450 ns Detection On-Time of Output Short fOSC = 65kHz, TON_OSP 0.7 1.1 1.5 s Protection RT7736G/R/L/E/B (Note 6) GATE Section Rising Time TR VDD = 15V, CL = 1nF -- 60 -- ns Falling Time TF VDD = 15V, CL = 1nF -- 40 -- ns Gate Output Clamping Voltage VCLAMP VDD = 23V -- 13.5 -- V PRO Interface Section (RT7736G/R/L/E) Pull High Threshold VTH_H 1.75 1.8 1.85 V Pull Low OTP Threshold VTH_OTP 0.47 0.5 0.53 V Pull Low Threshold VTH_L 0.25 0.3 0.35 V Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 8

RT7736 Parameter Symbol Test Conditions Min Typ Max Unit Open Loop Voltage VPRO_OP PRO pin open -- 1.3 -- V Internal Bias Current IBIAS 90 100 110 A Pull High Sinking Current ISIN -- -- 500 A Delay Time of OTP by PRO T f = 65kHz -- 56 -- ms D_OTP OSC BNO Interface Section (RT7736B/D/F) Brown-In Threshold VBNI_TH 0.96 1 1.04 V Brown-Out Threshold VBNO_TH 0.81 0.85 0.89 V RT7736B -- 56 -- De-bounce Time of VBNO_TH TD_BNO fOSC = 65kHz RT7736D -- 88 -- ms RT7736F -- 24 -- Over-Temperature Protection (OTP) Section Over-Temperature Protection T On Chip OTP (Note 6) -- 140 -- C OTP Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured in natural convection (still air) at TA= 25°C with the component mounted on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Leading edge blanking time and internal propagation delay time are guaranteed by design. Note 6. Guaranteed by design. Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 9

RT7736 Typical Application Circuit Vo+ + + AC Mains (90V to 265V) Vo- (Optional) 5 3 VDD 6 PRO GATE 2 COMP RT7736G/R/L/E 4 CS GND 1 Figure 3. Application Circuit For RT7736G, RT7736R, RT7736L and RT7736E Vo+ + + AC Mains (90V to 265V) Vo- (Optional) 5 3 VDD 6 BNO GATE 2 COMP RT7736B/D/F 4 CS GND 1 Figure 4. Application Circuit for RT7736B, RT7736D and RT7736F Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 10

RT7736 Typical Operating Characteristics I vs. V I vs. Temperature DD_ST DD DD_ST 6 10 5 8 4 ) ) A A µ µ (T 3 (T 6 S S _ _ D D D D I 2 I 4 1 0 2 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 V (V) DD Temperature (°C) VTH_ON vs. Temperature VTH_OFF vs. Temperature 16.0 10.0 15.5 9.5 15.0 V) V) (ON 14.5 (OFF 9.0 H_ H_ VT VT 14.0 8.5 13.5 13.0 8.0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) V & V vs. Temperature V vs. Temperature DD_LH LH_OFF OVP 5.8 28.00 27.75 5.6 V) 27.50 (F F 27.25 _O 5.4 VDD_LH V) VLH (VP 27.00 & O H 5.2 V 26.75 L _ D D 26.50 V 5.0 VLH_OFF 26.25 4.8 26.00 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 11

RT7736 f vs. V f vs. Temperature OSC DD OSC 67.0 68 66.5 66 66.0 z) 65.5 z) 64 H H k k (C 65.0 (C S S fO 64.5 fO 62 64.0 60 63.5 63.0 58 10 13 16 19 22 25 -50 -25 0 25 50 75 100 125 VDD (V) Temperature (°C) f vs. Temperature I vs. Temperature BS_MIN DD_LH 26 8 7 24 ) 6 z H A) k µ (MIN 22 (LH 5 S_ D_ B D f I 4 20 3 18 2 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) IDD_BNI vs. Temperature IDD_ARP vs. Temperature 200 425 180 400 A) A) µ µ (BNI 160 (RP 375 _ A D _ D D I D I 140 350 120 325 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 12

RT7736 I vs. Temperature I vs. Temperature DD_OP1 DD_OP2 850 850 800 800 A) A) µ µ (P1 750 (P2 750 O O _ _ D D D D I I 700 700 650 650 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) V vs. Temperature I vs. Temperature COMP_OP ZERO 5.4 310 5.3 300 ) V ) (P µA MP_O 5.2 (ERO 290 O Z C I V 5.1 280 5 270 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) T vs. Temperature T vs. Temperature OLP OLP 62 94 RT7736G/R/L/E/B RT7736D 92 60 s) s) 90 m m (P 58 (P L L O O 88 T T 56 86 54 84 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 13

RT7736 TOLP vs. Temperature TD_BNO vs. Temperature 70 30 RT7736F RT7736F 68 28 ) s) 66 ms 26 (mP (NO L B TO 64 D_ 24 T 62 22 60 20 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) V vs. Temperature t vs. Temperature CLAMP R 15.5 80 70 14.5 ) V 60 (MP 13.5 ns) LA (R C t 50 V 12.5 40 11.5 30 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) t vs. Temperature I vs. Temperature F BIAS 60 106 50 102 40 ) ) A s µ (nF (AS 98 t 30 BI I 94 20 10 90 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 14

RT7736 VTH_H vs. Temperature VTH_OTP vs. Temperature 1.90 0.60 1.85 0.55 ) ) V (V_H 1.80 (OTP 0.50 H _ T H V T V 1.75 0.45 1.70 0.40 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) V vs. Temperature V vs. Temperature TH_L BNI_TH 0.40 1.10 0.35 1.05 V) V) (TH_L 0.30 (NI_TH 1.00 V B V 0.25 0.95 0.20 0.90 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) V vs. Temperature BNO_TH 0.95 0.90 ) V (H _T 0.85 O N B V 0.80 0.75 -50 -25 0 25 50 75 100 125 Temperature (°C) Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 15

RT7736 Application Information When the system enters green mode, a output power SmartJitterTM Technology relationship is formed between the feedback voltage V COMP The RT7736 series applies RICHTEK proprietary and the PWM switching frequency, and a new stable SmartJitterTM technology. equilibrium point is eventually reached after back-and-forth adjustments. It limits the frequency jittering range is In order to reduce switching loss for lower power limited and the improving EMI function is poor, as shown consumption during light load or no load, general PWM in Figure 5. controllers have green mode function according to the feedback voltage VCOMP. The innovative SmartJitterTM technology not only helps reduce EMI emissions of SMPS when the system entering The output power equation is : Po_DCM(VCOMP) = 1Lpx1VCOMP 2fs(VCOMP) green mode, but also eliminates output jittering ripple. 2  RCS  Where L is the magnetizing inductance of the transformer, Accurate Over-Load Protection and Tight Current P R is the current sense resistor, V is the feedback Limit Tolerance CS COMP voltage of the COMP pin. fS is the switching frequency of Generally, the saw current limit is applied to low cost the power switch, η is the conversion efficiency, and x1 is flyback controllers because of simple design. The RT7736 a constant coefficient. series applies with RICHTEK proprietary technology Output power is a function of feedback voltage V . through well foundry control, design and test/trim mode COMP Frequency jittering technique is typically used to improve in final test. Therefore, the current limit tolerance is tight EMI problems in general PWM controllers, and the enough to make design and mass production easier, and frequency jittering period is based on PWM switching it provides accurate over-load protection. frequency. General PWM Jittering Freq. Jittering Freq. RT7736 Controller Normal Normal Operating Operating fs mean= 64.85kHz fs mean= 64.61kHz Jittering Range = 6.3% Jittering Range = 6.0% Jittering Freq. General PWM Jittering Freq. RT7736 Controller Green Mode Green Mode fJsi tmteearnin=g 4 R2.a9n9gkeH z= 3.3% fJsi tmteearnin=g 4 R2.a5n8gkeH z= 7.7% Figure 5. Frequency Jittering Range During Green Mode : General PWM Controller vs. RT7736 Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 16

RT7736 Start-Up Circuit VDD Discharge Time in Auto Recovery Mode To minimize power loss, it's recommended to connect Figure 7 shows the V and V waveforms during an DD GATE the start-up circuit to the bleeding resistors. It's power auto recovery protection (e.g., OLP). In this mode, the saving and also could reset latch mode protection quickly. start-up resistors, VDD sinking current and VDD decoupling Figure 6 shows I vs. R curve. Users can apply capacitor will affect the restart time. The discharge time DD_Avg Bleeding this curve to design the adequate bleeding resistors. t of VDD voltage can be calculated by using the D_Discharge following equation : In order to prolong turn-off period and minimize the power loss and thermal rising during hiccup, the controller is CVDD(VDD_DISVTH_OFF) tD_Discharge  designed to have smaller sinking current during entering IDD_ARPIST Where the C is the VDD decoupling capacitor, the auto-recovery protection, I . Therefore, the start-up VDD DD_ARP V is the initial VDD voltage after entering the auto current at maximum AC line input voltage must be smaller DD_DIS than I (I = 300μA). Otherwise, when the recovery mode, the VTH_OFF (9V typ.) is the falling UVLO DD_ARP DD_ARP(min) voltage threshold of the controller, the I (300μA typ.) controller enters auto-recovery protection, the VDD DD_ARP is the sinking current of the VDD pin in the auto recovery capacitor won't be dropped down to V by IC's sinking TH_OFF mode, and I is the start-up current of the power system. current and then restart. The controller behaves like latch ST protection or triggers the SCR of VDD. Please note that the start-up current at high input voltage must be smaller than the I . Otherwise, the VDD The RT7736 implemented brown-in detected function DD_ARP voltage can't reach the V to activate the next start- (RT7736B/D/F) as described in “BNO Pin Application” TH_OFF up process after an auto recovery protection. Therefore, section. In order to avoid start-up failure, the controller is the system behavior resembles the behavior of latch mode. designed to have smaller sinking current after start-up and then wait for brown-in, IDD_BNI. Therefore, the start-up VDD current at brown-in voltage of AC line input must be smaller VDD_DIS than I (I = 100μA). Otherwise, the VDD VTH_ON DD_BNI DD_BN (min) VTH_OFF voltage will rise up continuously and then trigger the SCR t VGATE OLP Delay of VDD. Time tD_Discharge t Figure 7. Auto Recovery Mode (e.g., OLP) I vs. R Curve I vs. R Curve DD_Avg Bleeding DD_Avg Bleeding 90 250 80 RBleeding IDD_Avg 225 RBleeding IDD_Avg 70 RBleeding 200 RBleeding A) 60 A) 175 (μg 50 VDD (μg 150 VDD v v A A _ _ DD 40 90Vac DD 125 265Vac I 85Vac I 230Vac 30 80Vac 100 20 75 10 50 0.6 1.0 1.4 1.8 2.2 2.6 3.0 0.6 1.0 1.4 1.8 2.2 2.6 3.0 R (M Ω ) R (M Ω ) Bleeding Bleeding Figure 6. I vs. R Curve DD_Avg Bleeding Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 17

RT7736 VDD Holdup Mode The Brown-in/out detected from bulk capacitor is shown The VDD holdup mode is only designed to prevent VDD in Figure 9, and the resistive divider (RC and RD) can be from decreasing to the turn-off threshold voltage under calculated by the following equations : light load or load transient. Relative to burst mode, the VBulk_Brown-in VBNI_TH1RC   RD  VDD holdup mode brings higher switching. Hence, it is highly recommended that the system should avoid VBulk_Brown-out VBNO_TH1RC   RD  operating at this mode during light load or no load The BNO pin application from bulk capacitor can use higher conditions, normally. resistance on the divider for power saving, but this method BNO Pin Application (RT7736B/D/F) can't have brown-in/out function at light load because bulk capacitor still has energy stored when AC line input is The RT7736 features a BNO pin (RT7736B/D/F), and it turned off. The recommended bypass capacitor C is can be applied for external arbitrary brown-in/out. The BNO BNO smaller than 1nF. pin is connected to the AC line input or bulk capacitor by resistive divider to achieve brown-in/out function. To avoid start-up failure, the RT7736 implements brown- Comparing the BNO pin connected to the AC line input in detected function, as shown in Figure 10. When VDD is with bulk capacitor, the advantage of the BNO pin greater than VTH_ON, the controller starts to operate and connected to the AC line input is having brown-in/out waits for brown-in signal. If brown-in signal is not enabled function regardless of output loads. before VDD falls below VDD_BNI, the controller will be shut down and then re-start. If the brown-in signal V is higher Figure 8 shows the application circuit of the BNO pin BNO than V , the controller will be enabled. connected to AC line input with resistive divider. The BNI_TH resistive divider (R and R ) can be calculated by the A B following equations : AC Mains (90V to 265V) VBrown-in_AC_rms 2 VBNI_TH1RA  CBulk RC  RB  VBrown-out_AC_rms 2 VBNO_TH1RA  BNO  RB  RT7736 CBNO RD The sum of resistor values (R and R ) should be smaller A B GND than 1.5MΩ because parasitic capacitors of bridge of diode may make hysteresis of brown-in/out function invalid. Figure 9. Brown-in/out Detected from Bulk Capacitor AC Mains (90V to 265V) RA BNO RB CBNO RT7736 GND Figure 8. Brown-in/out Detected from AC Line Input Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 18

RT7736 VDD VTH_ON Brown-in VDD_BNI Detection VTH_OFF VBNO < VBNI_TH VBNO < VBNI_TH VBNO > VBNI_TH Entering Auto Recovery Protection (Ex : OLP) IDD 1.6mA (typ.) Operating Current IDD_ARP IDD_BNI IDD_ST Brown-in (VBNO > VBNI_TH) VAC GATE Figure 10. RT7736 Brown-in Detected Function PRO Pin Application (RT7736G/R/L/E) Auto Recovery + Deglitch The RT7736 provides a PRO pin for external arbitrary OVP/ VTH_H - Latch OTP or IC ON/OFF applications as shown in Figure 12 to Auto Figure 15. VTH_OTP + 56ms Recovery In Figure 11, when the voltage of the PRO pin is between PRO - Delay Time Latch V and V , the controller is enabled for normal TH_OTP TH_H Auto operation. If the voltage of the PRO pin is lower than VTH_L + Recovery Deglitch VTH_OTP and higher than VTH_L after delay time TD_OTP, the - Latch controller will be shut down and cease switching. If the voltage of the PRO pin is higher than V or lower than TH_H VTH_L, the controller will be shut down and cease switching VPRO after deglitch delay. Auto Recovery/Latch When the voltage of the PRO pin is pulled above VTH_H, VTH_H the supply current of the PRO pin must be higher than Normal Operating 500μA and be limited below 5mA. When IC enters latch mode, V will be clamped at latched voltage V , and DD DD_LH VTH_OTP it will be released until VDD falls to latched reset voltage Auto Recovery/Latch V . VTH_L LH_OFF Auto Recovery/Latch When the PRO pin is open, it is set at 1.3V internally. Leave the PRO pin open if it is not used. If designer needs to apply a bypass capacitor on the PRO pin, the Figure 11. PRO Pin Diagram capacitance should be less than 1nF. The internal bias current of the PRO pin is 100μA (typ.). Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 19

RT7736 PRO Because it is hard to distinguish the difference between output short and big capacitance load, circuit design must be careful to make sure GATE width is larger than T ON_OSP (t > t ) after delay time T during start- ON ON_OSP(MAX) D_OSP (Option) up. NTC Resistors on GATE Pin In Figure 16, R is applied to alleviate ringing spike of G Figure 12. External OTP gate drive loop in typical application circuits. The value of R must be considered carefully with respect to EMI and G VDD efficiency for the system. The built-in internal discharge resistor R in parallel with ID GATE pin prevents the MOSFET from any uncertain PRO conditions. If the connection between the GATE pin and (Option) the Gate of the MOSFET is disconnected, the MOSFET will be false triggered by the residual energy through the Figure 13. OVP for VDD Gate-to-Drain parasitic capacitor C of the MOSFET and GD VDD PRO the system will be damaged. Therefore, it’s highly recommended to add an external discharge-resistor R ED connected between the Gate of MOSFET and GND terminals. The energy through the C is discharged by GD (Option) the external discharge-resistor to avoid MOSFET false triggering. AC Mains Figure 14. OVP for VDD (90V to 265V) PRO Vo+ The built-in internal discharge-resistor prevents the MOSFET from any uncertain conditions. RT7736 CGD (Option) (Option) Soft GATE RG Driver RID RED Figure 15. OVP for Output Voltage CS GND Output Short Protection (RT7736G/R/L/E/B) The RT7736 implements output short protection (RT7736G/ It is recommend to add the external discharge- R/L/E/B) by detecting GATE width with delay time TD_OSP. resistor to avoid MOSFET false triggering. It can minimize the power loss during output short, Figure 16. Resistors on Gate Pin especially at high line input voltage. Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 20

RT7736 Feedback Resistor In order to enhance light load efficiency, the loss of the AC Mains feedback resistor in parallel with photo-coupler is reduced, (90V to 265V) as shown in Figure 17. Due to small feedback resistor current, shunt regulator selection (e.g. TL-431) and minimum regulation current design must be considered carefully to make sure it's able to regulate under low cathode current. VDD PRO GATE RT7736 COMP CS Vo+ GND + + Vo- R-C Filter Figure 18. R-C Filter on CS Pin Over-Temperature Protection (OTP) The RT7736 provides an internal OTP function to protect the controller itself from suffering thermal stress and Feedback Resistor permanent damage. It's not suggested to use the function as precise control of over temperature. Once the junction temperature is higher than the OTP threshold, the controller will shut down until the temperature cools down. Meanwhile, if V reaches turn-off threshold voltage DD V , the controller will hiccup till the over-temperature Figure 17. Feedback Resistor TH_OFF condition is removed. Negative Voltage Spike on Each Pin Thermal Considerations Negative voltage (< −0.3V) to the controller pins will cause For continuous operation, do not exceed absolute substrate injection and lead to controller damage or circuit maximum junction temperature. The maximum power false triggering. For example, the negative spike voltage dissipation depends on the thermal resistance of the IC at the CS pin may come from improper PCB layout or package, PCB layout, rate of surrounding airflow, and inductive current sense resistor. Therefore, it is highly difference between junction and ambient temperature. The recommended to add an R-C filter to avoid the CS pin maximum power dissipation can be calculated by the damage, as shown in Figure 18. Proper PCB layout and following formula : component selection should be considered during circuit P = (T − T ) / θ D(MAX) J(MAX) A JA design. where T is the maximum junction temperature, T is J(MAX) A the ambient temperature, and θ is the junction to ambient JA thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θ , is layout dependent. For JA Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 www.richtek.com 21

RT7736 SOT-23-6 package, the thermal resistance, θ , is Layout Consideration JA 260.7°C/W on a standard JEDEC 51-3 single-layer thermal A proper PCB layout can abate unknown noise interference test board. The maximum power dissipation at TA = 25°C and EMI issue in the switching power supply. Please refer can be calculated by the following formula : to the guidelines when you want to design PCB layout for P = (125°C − 25°C) / (260.7°C/W) = 0.38W for switching power supply : D(MAX) SOT-23-6 package  The current path (1) through bulk capacitor, transformer, The maximum power dissipation depends on the operating MOSFET, RCS returns to bulk capacitor is a high ambient temperature for fixed T and thermal frequency current loop. It must be as short as possible J(MAX) resistance, θ . The derating curve in Figure 19 allows to decrease noise coupling and keep away from other JA the designer to see the effect of rising ambient temperature low voltage traces, such as IC control circuit paths, on the maximum power dissipation. especially. 0.5  The path (2) of the RCD snubber circuit is also a high W) 1 Single-Layer PCB switching loop. Keep it as small as possible. n ( 0.4 o  Separate the ground traces of bulk capacitor(a), ati p MOSFET(b), auxiliary winding(c) and IC control circuit(d) ssi 0.3 for reducing noise, output ripple and EMI issue. Connect Di er these ground traces together at bulk capacitor ground w 0.2 o (a). The areas of these ground traces should be large P m enough. u m 0.1 xi  Place the bypass capacitor as close to the controller as a M possible. 0.0 0 25 50 75 100 125  In order to reduce reflected trace inductance and EMI, Ambient Temperature (°C) minimize the area of the loop connecting the secondary Figure 19. Derating Curve of Maximum Power winding, output diode and output filter capacitor. In Dissipation additional, apply sufficient copper area at the anode and cathode terminal of the diode for heatsinking. AC Mains CBULK (90V to 265V) (2) (a) CBULK Ground (a) Trace Trace Trace VDD (c) PRO GATE IC Auxiliary MOSFET RT7736 Ground (d) Ground (c) Ground (b) (1) COMP CS GND (d) (b) Figure 20. PCB Layout Guide Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7736-04 September 2014 22

RT7736 Outline Dimension H D L C B b A A1 e Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.889 1.295 0.031 0.051 A1 0.000 0.152 0.000 0.006 B 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 C 2.591 2.997 0.102 0.118 D 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 H 0.080 0.254 0.003 0.010 L 0.300 0.610 0.012 0.024 SOT-23-6 Surface Mount Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS7736-04 September 2014 www.richtek.com 23