Design Sample & Tools Buy ® RT7235/36/39/40 5A, 18V, 650kHz, ACOTTM Synchronous Step-Down Converter General Description Features The RT7235/36/39/40 is a synchronous step-down DC/  ACOTTM Mode Enables Fast Transient Response DC converter with Advanced Constant On-Time (ACOTTM)  4.5V to 18V Input Voltage Range mode control. It achieves high power density to deliver up  5A Output Current to 5A output current from a 4.5V to 18V input supply. The  35mΩΩΩΩΩ Internal Low Site N-MOSFET proprietary ACOTTM mode offers an optimal transient  Advanced Constant On-Time Control response over a wide range of loads and all kinds of ceramic  Support All Ceramic Capacitors capacitors, which allows the device to adopt very low ESR  Up to 95% Efficiency output capacitor for ensuring performance stabilization. In  650kHz Switching Frequency at all Load Current addition, RT7235/36/39/40 keeps an excellent constant (RT7235, RT7239) switching frequency under line and load variation and the  Discontinuous Operating Mode at Light Load integrated synchronous power switches with the ACOTTM (RT7236, RT7240) mode operation provides high efficiency in whole output  Adjustable Output Voltage from 0.765V to 8V current load range. Cycle-by-cycle current limit provides  Adjustable Soft-Start an accurate protection by a valley detection of low side  Cycle-by-Cycle Current Limit MOSFET and external soft-start setting eliminates input  Input Under Voltage Lockout current surge during startup. Protection functions include  Thermal Shutdown thermal shutdown for RT7235/36/39/40, output Under  RoHS Compliant and Halogen Free Voltage Protection (UVP) / Over Voltage Protection (OVP) Applications for RT7235/36. When the UVP/OVP is triggered, the device Industrial and Commercial Low Power Systems will enter latch mode for TSSOP-14 (Exposed Pad), and  Computer Peripherals hiccup mode for WDFN-10L 3x3.  LCD Monitors and TVs  The RT7235/36 are available in TSSOP-14 (Exposed Pad) Green Electronics/Appliances  and WDFN-10L 3x3 packages, and the RT7235 is operated Point of Load Regulation for High-Performance DSPs,  in forced continuous conduction mode. FPGAs, and ASICs The RT7239/40 are available in the SOP-8 (Exposed Pad) package, and the RT7239 is operated in forced continuous conduction mode. Simplified Application Circuit RT7235/36/39/40 VIN VIN SW VOUT VCC* BOOT Enable EN FB Power GOOD PGOOD* PGND VREG5 VS* * : VCC pin for TSSOP-14 (Exposed Pad) only. SS GND* VS pin for TSSOP-14 (Exposed Pad) only. GND pin for TSSOP-14 (Exposed Pad) only. PGOOD pin for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only. Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 1

RT7235/36/39/40 Ordering Information Marking Information Continuous Switching Mode RT7235GCP RT7235GCP : Product Number RT7235 RT7235GCP Package Type YMDNN : Date Code YMDNN CP : TSSOP-14 (Exposed Pad) QW : WDFN-10L 3x3 (W-Type) Lead Plating System RT7235GQW G : Green (Halogen Free and Pb Free) 1N= : Product Code 1N=YM YMDNN : Date Code RT7239 DNN Package Type SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System RT7239GSP G : Green (Halogen Free and Pb Free) RT7239GSP : Product Number RT7239 YMDNN : Date Code GSPYMDNN Discontinuous Operating Mode RT7236 RT7236GCP Package Type RT7236GCP : Product Number CP : TSSOP-14 (Exposed Pad) RT7236GCP YMDNN : Date Code QW : WDFN-10L 3x3 (W-Type) YMDNN Lead Plating System G : Green (Halogen Free and Pb Free) RT7236GQW 1M= : Product Code RT7240 1M=YM YMDNN : Date Code Package Type DNN SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System G : Green (Halogen Free and Pb Free) RT7240GSP Note : RT7240GSP : Product Number RT7240 Richtek products are : YMDNN : Date Code GSPYMDNN  RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering processes. Pin Configurations (TOP VIEW) VS 14 VCC FB 2 13 VIN VREG5 3 12 BOOT EN 8 VIN SS 4 PGND 11 SW EN 1 10 VIN GND 5 10 SW FB 2 ND 9 VIN FB 2 PGND 7 BOOT PGOOD 6 15 9 PGND VREGSS5 34 PG 87 BSOWOT VREG5 3 9 6 SW EN 7 8 PGND PGOOD 5 11 9 SW SS 4 5 PGND TSSOP-14 (Exposed Pad) WDFN-10L 3x3 SOP-8 (Exposed Pad) Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 2

RT7235/36/39/40 Functional Pin Description Pin No. TSSOP-14 SOP-8 Pin Name Pin Function WDFN-10L 3x3 (Exposed Pad) (Exposed Pad) 1 -- -- VS Output Voltage Sense Input. Feedback Voltage Input. It is used to regulate the output of the converter to a set value via an external 2 2 2 FB resistive voltage divider. The feedback threshold voltage is 0.765V typically. Internal Regulator Output. Connect a 1F capacitor 3 3 3 VREG5 to GND to stabilize output voltage. Soft-Start Time Setting. Connect an external capacitor 4 4 4 SS between this pin and GND to set the soft- start time. 5 -- -- GND Analog Ground. 6 5 -- PGOOD Open Drain Power Good Indicator Output. Enable Control Input. A logic-high enables the 7 1 1 EN converter; a logic-low forces the IC into shutdown mode reducing the supply current to less than 10A. Power Ground. The exposed pad must be soldered 8, 9, 15 11 5, 9 PGND to a large PCB and connected to PGND for (Exposed pad) (Exposed pad) (Exposed Pad) maximum power dissipation. Switch Node. Connect this pin to an external L-C 10, 11 6, 7 6 SW filter. Bootstrap Supply for High Side Gate Driver. Connect 12 8 7 BOOT a 0.1F capacitor between the BOOT and SW pin. Power Input. The input voltage range is from 4.5V to 13 9, 10 8 VIN 18V. Must bypass with a suitably large (10F x 2) ceramic capacitor. Supply Voltage Input for Internal Linear Regulator to 14 -- -- VCC the Control Circuitry. Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 3

RT7235/36/39/40 Function Block Diagram VCC* VREG5 BOOT POR & EN Reg Min. Off-Time VREG5 VIN VBIAS VREF OC Control Driver SW UV & OV PGND SW ZC VREG5 Ripple GND* Gen. 6µA + SS FB -- Comparator PGOOD* VIN Comparator FB - FB 0.9 x VREF + On-Time VS* * : VCC pin for TSSOP-14 (Exposed Pad) only. VS pin for TSSOP-14 (Exposed Pad) only. GND pin for TSSOP-14 (Exposed Pad) only. PGOOD pin for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only. Operation The RT7235/36/39/40 is a synchronous step-down Current Protection converter with advanced constant on-time control mode. The inductor current is monitored via the internal switches Using the ACOTTM control mode can reduce the output in cycle-by-cycle. Once the output voltage drops under capacitance and provide fast transient response. It can UV threshold, the device will enter latch mode for TSSOP- minimize the component size without additional external 14 (Exposed Pad), and hiccup mode for WDFN-10L 3x3. compensation network. UVLO Protection Power Good To protect the chip from operating at insufficient supply (for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only) voltage, the UVLO is needed. When the input voltage of After soft-start is finished, the power good function will be VCC is lower than the UVLO falling threshold voltage, the activated. When the FB is activated, the PGOOD will device will be latch-off. become an open-drain output. If the FB is below, the Output Discharge Control PGOOD pin will be pulled low. (for TSSOP-14 (Exposed Pad) only) Internal Regulator When EN pin is low, the RT7235/36 will discharge the The regulator provides 5V power to supply the internal output with an internal 50Ω MOSFET connected between control circuit. Connecting a 1μF ceramic capacitor for V to GND pin. OUT decoupling and stability is required. Thermal Shutdown Soft-Start When the junction temperature exceeds the OTP In order to prevent the converter output voltage from threshold value, the IC will shut down the switching overshooting during the startup period, the soft-start operation. Once the junction temperature cools down and function is necessary. The soft-start time is adjustable is lower than the OTP lower threshold, the converter will and can be set by an external capacitor. automatically resume switching Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 4

RT7235/36/39/40 Absolute Maximum Ratings (Note 1) Supply Voltage, VIN, VCC --------------------------------------------------------------------------------------- −0.3V to 20V  Switch Voltage, SW ----------------------------------------------------------------------------------------------- −0.8V to (V + 0.3V)  IN < 10ns ---------------------------------------------------------------------------------------------------------------- −5V to 25V BOOT to SW -------------------------------------------------------------------------------------------------------- −0.3V to 6V  EN---------------------------------------------------------------------------------------------------------------------- −0.3V to 20V  Other Pins------------------------------------------------------------------------------------------------------------ −0.3V to 6V  Power Dissipation, P @ T = 25°C  D A TSSOP-14 (Exposed Pad)--------------------------------------------------------------------------------------- 2.50W WDFN-10L 3x3------------------------------------------------------------------------------------------------------ 1.67W SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------------- 2.174W Package Thermal Resistance (Note 2)  TSSOP-14 (Exposed Pad), θ --------------------------------------------------------------------------------- 40°C/W JA WDFN-10L 3x3, θ ------------------------------------------------------------------------------------------------ 60°C/W JA WDFN-10L 3x3, θ ------------------------------------------------------------------------------------------------ 7.5°C/W JC SOP-8 (Exposed Pad), θ --------------------------------------------------------------------------------------- 46°C/W JA SOP-8 (Exposed Pad), θ -------------------------------------------------------------------------------------- 7°C/W JC Junction Temperature Range------------------------------------------------------------------------------------- 150°C  Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------ 260°C  Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C  Recommended Operating Conditions (Note 3) Supply Voltage, VIN ----------------------------------------------------------------------------------------------- 4.5V to 18V  Junction Temperature Range------------------------------------------------------------------------------------- −40°C to 125°C  Ambient Temperature Range------------------------------------------------------------------------------------- −40°C to 85°C  Electrical Characteristics (VIN = 12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Current Shutdown Current ISHDN VEN = 0V -- 1 10 A Quiescent Current IQ VEN = 5V, VFB = 0.8V -- 1 1.3 mA Logic Threshold Logic-High 1 1.15 1.25 EN Input Voltage V Logic-Low 0.85 0.94 1.15 V Voltage and Discharge Resistance FB TA = 25C 0.757 0.765 0.773 Feedback Threshold Voltage VFB V TA = 40C to 85C 0.755 -- 0.775 Feedback Input Current IFB VFB = 0.8V -- 0.01 0.1 A VOUT Discharge Resistance RDIS VEN = 0V, VS = 0.5V -- 50 100  V Output REG5 VREG5 Output Voltage VREG5 6V  VIN  18V, 0 < IVREG5  5mA 4.8 5.1 5.4 V Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 5

RT7235/36/39/40 Parameter Symbol Test Conditions Min Typ Max Unit Line Regulation 6V  VIN  18V, IVREG5 = 5mA -- -- 20 mV Load Regulation 0  IVREG5  5mA -- -- 100 mV Output Current IVREG5 VIN = 6V, VREG5 = 4V, TA = 25C -- 70 -- mA Oscillation Frequency fOSC 540 650 760 kHz R DS(ON) Switch On High-Side RDS(ON)_H (VBOOT  VSW) = 5.5V -- 120 -- m Resistance Low-Side RDS(ON)_L -- 35 -- Current Limit Current Limit ILIM 5.9 6.85 7.8 A Thermal Shutdown Thermal Shutdown Threshold TSD Shutdown Temperature -- 150 -- C Thermal Shutdown Hysteresis TSD -- 20 -- On-Time Timer Control On-Time tON VIN = 12V, VOUT = 1.05V -- 135 -- ns Minimum On-Time tON(MIN) Note 5 -- 55 80 ns Minimum Off-Time tOFF(MIN) VFB = 0.7V -- 260 310 ns Soft-Start SS Charge Current VSS = 0V -- 6 -- A SS Discharge Current VSS = 0.5V 0.1 0.2 -- mA UVLO UVLO Threshold Wake Up VREG5 3.6 3.85 4.1 V Hysteresis 0.16 0.35 0.47 Power Good VFB Rising 85 90 95 PGOOD Threshold % VFB Falling -- 85 -- PGOOD Sink Current PGOOD = 0.5V 2.5 5 -- mA Output Under Voltage and Over Voltage Protection OVP Trip Threshold OVP Detect 115 120 125 % OVP Prop Delay -- 5 -- s UVP Trip Threshold 65 70 75 % UVP Hysteresis -- 10 -- UVP Prop Delay -- 250 -- s UVP Enable Delay tUVPEN Relative to Soft-Start Time -- tSS -- ms x 1.7 Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 6

RT7235/36/39/40 Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 7

RT7235/36/39/40 Typical Application Circuit RT7235/36/39/40 L1 1.4µH VIN C1 C2 VIN SW C6 V1.O0U5TV/5A 10µF x 2 0.1µF VCC* 0.1µF C3 R1 C7 BOOT 8.25k 22µF x 2 Input Signal EN FB Power GOOD PGOOD* R2 R3 22k 100k VREG5 C4 SS VS* 1µF C5 3.9nF GND* PGND * : VCC pin for TSSOP-14 (Exposed Pad) only. VS pin for TSSOP-14 (Exposed Pad) only. GND pin for TSSOP-14 (Exposed Pad) only. PGOOD pin for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only. Table 1. Suggested Component Values (V = 12V) IN VOUT (V) R1 (k) R2 (k) C3 (pF) L1 (H) C7 (F) 1 6.81 22.1 -- 1.4 22 to 68 1.05 8.25 22.1 -- 1.4 22 to 68 1.2 12.7 22.1 -- 1.4 22 to 68 1.8 30.1 22.1 5 to 22 2 22 to 68 2.5 49.9 22.1 5 to 22 2 22 to 68 3.3 73.2 22.1 5 to 22 2 22 to 68 5 124 22.1 5 to 22 3.3 22 to 68 7 180 22.1 5 to 22 3.3 22 to 68 Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 8

RT7235/36/39/40 Typical Operating Characteristics Efficiency vs. Output Current Efficiency vs. Output Current 100 100 RT7235/39 RT7236/40 90 90 80 80 70 70 %) %) y ( 60 y ( 60 VIN = 5V Efficienc 4500 VVVIIINNN === 511V28VV Efficienc 4500 VVIINN == 1128VV 30 30 20 20 10 10 VOUT= 1.05V VOUT= 1.05V 0 0 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 Output Current (A) Output Current (A) Output Voltage vs. Input Voltage Feedback Threshold Voltage vs. Temperature 1.060 0.780 ) V 1.058 e ( 0.775 1.056 g a V) 1.054 olt ge ( 1.052 d V 0.770 a ol olt 1.050 sh 0.765 V e Output 11..004468 ack Thr 0.760 1.044 b d 0.755 e 1.042 e VIN = 4.5V to 18V, VOUT = 1.05V F VIN = 12V, VOUT = 1.05V, IOUT = 0A 1.040 0.750 4 6 8 10 12 14 16 18 -50 -25 0 25 50 75 100 125 Input Voltage (V) Temperature (°C) Output Voltage vs. Output Current Output Voltage vs. Output Current 1.10 1.10 RT7235/39 RT7236/40 1.09 1.09 1.08 1.08 ) ) V 1.07 V 1.07 e ( e ( g 1.06 g 1.06 a a olt 1.05 olt 1.05 V V ut 1.04 VIN = 18V ut 1.04 VIN = 18V Outp 1.03 VVIINN == 51V2V Outp 1.03 VVIINN == 51V2V 1.02 1.02 1.01 1.01 VOUT= 1.05V VOUT= 1.05V 1.00 1.00 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Output Current (A) Output Current (A) Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 9

RT7235/36/39/40 Switching Frequency vs. Input Voltage Switching Frequency vs. Temperature 700 700 690 690 ) 1 ) 1 z z H 680 H 680 k k y ( 670 y ( 670 c c n 660 n 660 e e u u q 650 q 650 e e r r F 640 F 640 g g n n hi 630 hi 630 c c wit 620 wit 620 S S 610 610 600 600 4 6 8 10 12 14 16 18 -50 -25 0 25 50 75 100 125 Input Voltage (V) Temperature (°C) Current Limit vs. Temperature Current Limit vs. Input Voltage 8.0 9.0 8.5 7.5 8.0 ) ) A 7.0 A mit ( mit ( 7.5 Li 6.5 Li 7.0 nt nt e e rr rr 6.5 u 6.0 u C C 6.0 5.5 5.5 VIN = 12V, VOUT = 1.05V 5.0 5.0 -50 -25 0 25 50 75 100 125 4 6 8 10 12 14 16 18 Temperature (°C) Input Voltage (V) Load Transient Response Load Transient Response RT7235/39 RT7235/36/39/40 VOUT VOUT (20mV/Div) (20mV/Div) IOUT IOUT (2A/Div) (2A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 0A to 5A VIN = 12V, VOUT = 1.05V, IOUT = 1A to 5A Time (100μs/Div) Time (100μs/Div) Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 10

RT7235/36/39/40 Switching Switching VSW VSW (10V/Div) (10V/Div) VOUT VOUT (5mV/Div) (5mV/Div) IL IL (1A/Div) (5A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 1A VIN = 12V, VOUT = 1.05V, IOUT = 5A Time (1μs/Div) Time (1μs/Div) Power On from VIN Power Off from VIN VIN VIN (10V/Div) (10V/Div) VOUT VOUT (1V/Div) (1V/Div) IOUT IOUT (2A/Div) (2A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 5A VIN = 12V, VOUT = 1.05V, IOUT = 5A Time (2.5ms/Div) Time (10ms/Div) Power On from EN Power Off from EN VEN VEN (2V/Div) (2V/Div) VOUT VOUT (1V/Div) (1V/Div) IOUT IOUT (5A/Div) (5A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 5A VIN = 12V, VOUT = 1.05V, IOUT = 5A Time (500μs/Div) Time (500μs/Div) Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 11

RT7235/36/39/40 EN Threshold Voltage vs. Temperature UVLO vs. Temperature 1.5 4.0 1.4 V) 3.9 e ( 1.3 g a 3.8 Rising olt 1.2 Rising V) d V 1.1 O ( 3.7 ol L h V es 1.0 Falling U r 3.6 h N T 0.9 Falling E 3.5 0.8 VIN = 12V, VOUT = 1.05V 0.7 3.4 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Power Good from EN Turn On Power Good from EN Turn Off RT7235/36 RT7235/36 VEN VEN (5V/Div) (5V/Div) VPGOOD VPGOOD (10V/Div) (10V/Div) VOUT VOUT (1V/Div) (1V/Div) IOUT IOUT (5A/Div) (5A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 5A VIN = 12V, VOUT = 1.05V, IOUT = 5A Time (250μs/Div) Time (2.5ms/Div) Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 12

RT7235/36/39/40 Application Information The RT7235/36/39/40 is a synchronous high voltage Buck the EN pin can also be externally pulled high by adding a converter that can support the input voltage range from R resistor and C capacitor from the VIN pin (see Figure EN EN 4.5V to 18V and the output current up to 5A. It adopts 1). ACOTTM mode control to provide a very fast transient EN response with few external compensation components. REN VIN EN RT7235/36/39/40 PWM Operation CEN It is suitable for low external component count GND configuration with appropriate amount of Equivalent Series Figure 1. External Timing Control Resistance (ESR) capacitors at the output. The output ripple valley voltage is monitored at a feedback point An external MOSFET can be added to implement digital voltage. The synchronous high side MOSFET is turned control on the EN pin when no system voltage above 2V on at the beginning of each cycle. After the internal is available, as shown in Figure 2. In this case, a 100kΩ on-time expires, the MOSFET is turned off. The pulse pull-up resistor, R , is connected between the V and EN IN width of this on-time is determined by the converter's input EN pins. MOSFET Q1 will be under logic control to pull and output voltages to keep the frequency fairly constant down the EN pin. over the entire input voltage range. REN 100k Advanced Constant On-Time Control VIN EN The RT7235/36/39/40 has a unique circuit which sets the EN Q1 RT7235/36/39/40 on-time by monitoring the input voltage and SW signal. GND The circuit ensures the switching frequency operating at 650kHz over input voltage range and loading range. Figure 2. Digital Enable Control Circuit Soft-Start To prevent enabling circuit when V is smaller than the IN The RT7235/36/39/40 contains an external soft-start clamp V target value, a resistive voltage divider can be placed OUT that gradually raises the output voltage. The soft-start between the input voltage and ground and connected to timing can be programmed by the external capacitor the EN pin to adjust IC lockout threshold, as shown in between the SS and GND pins. The chip provides a 6μA Figure 3. For example, if an 8V output voltage is regulated charge current for the external capacitor. If a 3.9nF from a 12V input voltage, the resistor R can be selected EN2 capacitor is used, the soft-start will be 0.87ms (typ.). to set input lockout threshold larger than 8V. The available capacitance range is from 2.7nF to 220nF. tSS (ms) = C5 I(nF )(1A.)365 VIN REN1 EN SS REN2 RT7235/36/39/40 Chip Enable Operation GND The EN pin is the chip enable input. Pulling the EN pin Figure 3. Resistor Divider for Lockout Threshold Setting low (<0.85V) will shut down the device. During shutdown mode, the RT7235/36/39/40's quiescent current drops to lower than 10μA. Driving the EN pin high (>1.25V, <18V) will turn on the device again. For external timing control, Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 13

RT7235/36/39/40 Output Voltage Setting highest efficiency operation. However, it requires a large The resistive divider allows the FB pin to sense the output inductor to achieve this goal. For the ripple current voltage as shown in Figure 4. selection, the value of ΔIL = 0.2(IMAX) will be a reasonable starting point. The largest ripple current occurs at the VOUT highest V . To guarantee that the ripple current stays IN R1 below the specified maximum, the inductor value should FB be chosen according to the following equation : RT7235/36/39/40 R2 L = VOUT 1 VOUT      GND fIL(MAX)  VIN(MAX) Figure 4. Output Voltage Setting Input and Output Capacitors Selection The input capacitance, C , is needed to filter the The output voltage is set by an external resistive divider IN trapezoidal current at the source of the high side MOSFET. according to the following equation. It is recommended to A low ESR input capacitor with larger ripple current rating use 1% tolerance or better divider resistors. R1 should be used for the maximum RMS current. The RMS V = 0.765(1 ) OUT R2 current is given by : Under Voltage Lockout Protection IRMS = IOUT(MAX) VOUT VIN 1 VIN VOUT The RT7235/36/39/40 has Under Voltage Lockout This formula has a maximum at V = 2V , where IN OUT Protection (UVLO) that monitors the voltage of PVCC pin. I = I / 2. This simple worst-case condition is RMS OUT When the V voltage is lower than UVLO threshold PVCC commonly used for design because even significant voltage, the RT7235/36/39/40 will be turned off in this state. deviations do not offer much relief. This is non-latch protection. Choose a capacitor rated at a higher temperature than Over Temperature Protection required. Several capacitors may also be paralleled to The RT7235/36/39/40 equips an Over Temperature meet size or height requirements in the design. For the Protection (OTP) circuitry to prevent overheating due to input capacitor, two 10μF and 0.1μF low ESR ceramic excessive power dissipation. The OTP will shut down capacitors are recommended. switching operation when junction temperature exceeds The selection of C is determined by the required ESR OUT 150°C. Once the junction temperature cools down by to minimize voltage ripple. approximately 20°C the main converter will resume Moreover, the amount of bulk capacitance is also a key operation. To keep operating at maximum, the junction for C selection to ensure that the control loop is stable. OUT temperature should be prevented from rising above 150°C. The output ripple, ΔV , is determined by : OUT Inductor Selection VOUT ILESR8fC1OUT The inductor value and operating frequency determine the The output ripple will be highest at the maximum input ripple current according to a specific input and an output voltage since ΔI increases with input voltage. Multiple voltage. The ripple current ΔI increases with higher V L L IN capacitors placed in parallel may need to meet the ESR and decreases with higher inductance. and RMS current handling requirements. IL =VfOULT1VVOIUNT Higher values, lower cost ceramic capacitors are now Having a lower ripple current reduces not only the ESR becoming available in smaller case sizes. Their high ripple losses in the output capacitors but also the output voltage current, high voltage rating and low ESR make them ideal ripple. High frequency with small ripple current can achieve for switching regulator applications. However, care must Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 14

RT7235/36/39/40 be taken when these capacitors are used at input and Thermal Considerations output. When a ceramic capacitor is used at the input For continuous operation, do not exceed absolute and the power is supplied by a wall adapter through long maximum junction temperature. The maximum power wires, a load step at the output can induce ringing at the dissipation depends on the thermal resistance of the IC input, VIN. A sudden inrush of current through the long package, PCB layout, rate of surrounding airflow, and wires can potentially cause a voltage spike at VIN large difference between junction and ambient temperature. The enough to damage the part. maximum power dissipation can be calculated by the following formula : External Bootstrap Diode P = (T − T ) / θ Connect a 0.1μF low ESR ceramic capacitor between the D(MAX) J(MAX) A JA BOOT and SW pins. This capacitor provides the gate driver where TJ(MAX) is the maximum junction temperature, TA is voltage for the high side MOSFET. It is recommended to the ambient temperature, and θJAis the junction to ambient add an external bootstrap diode between an external 5V thermal resistance. and the BOOT pin for efficiency improvement when input For recommended operating condition specifications, the voltage is lower than 5.5V or duty ratio is higher than 65%. maximum junction temperature is 125°C. The junction to The bootstrap diode can be a low cost one such as 1N4148 ambient thermal resistance, θ , is layout dependent. For JA or BAT54. The external 5V can be a 5V fixed input from TSSOP-14 (Exposed Pad) package, the thermal system or a 5V output of the RT7235/36/39/40. Note that resistance, θ , is 40°C/W on a standard JEDEC 51-7 JA the external boot voltage must be lower than 5.5V four-layer thermal test board. For WDFN-10L 3x3 package, 5V the thermal resistance, θ , is 60°C/W on a standard JA JEDEC 51-7 four-layer thermal test board. For SOP-8 (Exposed Pad) package, the thermal resistance, θ , is JA BOOT 46°C/W on a standard JEDEC 51-7 four-layer thermal test RT7235/36/39/40 0.1µF board. The maximum power dissipation at T = 25°C can A SW be calculated by the following formulas : P = (125°C − 25°C) / (40°C/W) = 2.50W for D(MAX) Figure 5. External Bootstrap Diode TSSOP-14 (Exposed Pad) package PVCC Capacitor Selection PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.67W for Decouple with a 1μF ceramic capacitor. X7R or X5R grade WDFN-10L 3x3 package dielectric ceramic capacitors are recommended for their P = (125°C − 25°C) / (46°C/W) = 2.174W for D(MAX) stable temperature characteristics. SOP-8 (Exposed Pad) package The maximum power dissipation depends on operating Over Current Protection ambient temperature for fixed T and thermal J(MAX) When the output shorts to ground, the inductor current resistance, θ . The derating curves in Figure 6 allow the JA decays very slowly during a single switching cycle. An designer to see the effect of rising ambient temperature over current detector is used to monitor inductor current on the maximum power dissipation. to prevent current runaway. The over current detector monitors the voltage between SW and GND during the low side MOS turn-on state. This is cycle-by-cycle protection. Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 15

RT7235/36/39/40 Layout Consideration 3.2 W) 1 2.8 Four-Layer PCB Follow the PCB layout guidelines for optimal performance n ( TSSOP-14 (Exposed Pad) of the RT7235/36/39/40 o 2.4 pati  Keep the traces of the main current paths as short and si 2.0 SOP-8 (Exposed Pad) s wide as possible. Di r 1.6 we WDFN-10L 3x3  Put the input capacitor as close as possible to the device o 1.2 P pins (VIN and GND). m 0.8 mu  SW node is with high frequency voltage swing and xi 0.4 should be kept at small area. Keep sensitive a M components away from the SW node to prevent stray 0.0 0 25 50 75 100 125 capacitive noise pickup. Ambient Temperature (°C)  Connect feedback network behind the output capacitors. Figure 6. Derating Curve of Maximum Power Dissipation Keep the loop area small. Place the feedback components near the RT7235/36/39/40 FB pin.  The GND and Exposed Pad should be connected to a strong ground plane for heat sinking and noise protection. Place the feedback components Place the input and output Place the feedback components Place the input and output as close to the FB as possible capacitors as close to the as close to the FB as possible capacitors as close to the for better regulation. IC as possible. for better regulation. IC as possible. PGND VOUT PGND R1 VOUT 14 VINR CIN R1R2 EN 1 10 VIN CIN FB 2 13 VIN VOUT FB 2 D 9 VIN CBOOT PVCC 3 12 BOOT CBOOT PVCC 3 GN 8 BOOT R2 CVCC GNSDS 45 PGND 1110 SSWW CVCC PGOOSDS 45 P11 67 SSWW PGOOD 6 15 9 PGND L VOUT COUT L EN 7 8 PGND COUT PGND VOUT SW should be connected to inductor by SW should be connected to inductor by Wide and short Wide and short trace. Keep sensitive trace. Keep sensitive components away from this trace. components away from this trace. (a). For TSSOP-14 (Exposed Pad) Package (b). For WDFN-10L 3x3 Package The resistor divider must Input capacitor must be placed be connected as close to as close to the IC as possible. C1 the device as possible. VOUT C2 SW should be connected to inductor by Wide and short trace. Keep sensitive R1 EN 8 VIN components away from this trace. R2 FB 2 7 BOOT GND C4 GND C6 PVCC 3 6 SW 9 C5 SS 4 5 GND L1 C7 V O U T (c). For SOP-8 (Exposed) Package Figure 7. PCB Layout Guide Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 16

RT7235/36/39/40 Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 1.000 1.200 0.039 0.047 A1 0.000 0.150 0.000 0.006 A2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 D 4.900 5.100 0.193 0.201 e 0.650 0.026 E 6.300 6.500 0.248 0.256 E1 4.300 4.500 0.169 0.177 L 0.450 0.750 0.018 0.030 U 1.900 2.900 0.075 0.114 V 1.600 2.600 0.063 0.102 14-Lead TSSOP (Exposed Pad) Plastic Package Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS7235/36/39/40-08 January 2017 www.richtek.com 17

RT7235/36/39/40 D2 D L E E2 SEE DETAIL A 1 e b 2 1 2 1 A A3 A1 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e 0.500 0.020 L 0.350 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS7235/36/39/40-08 January 2017 18

RT7235/36/39/40 H A M EXPOSED THERMAL PAD Y (Bottom of Package) J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Option 1 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Option 2 Y 3.000 3.500 0.118 0.138 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS7235/36/39/40-08 January 2017 www.richtek.com 19