REG102 REG102 REG102 SBVS024F – NOVEMBER 2000 – REVISED SEPTEMBER 2005 DMOS 250mA Low-Dropout Regulator FEATURES DESCRIPTION (cid:1) NEW DMOS TOPOLOGY: The REG102 is a family of low-noise, low-dropout linear Ultra Low Dropout Voltage: regulators with low ground pin current. The new DMOS 150mV typ at 250mA topology provides significant improvement over previous Output Capacitor not Required for Stability designs, including low-dropout voltage (only 150mV typ at (cid:1) FAST TRANSIENT RESPONSE full load), and better transient performance. In addition, no output capacitor is required for stability, unlike conventional (cid:1) VERY LOW NOISE: 28µVrms low-dropout regulators that are difficult to compensate and (cid:1) HIGH ACCURACY: ±1.5% max require expensive low ESR capacitors greater than 1µF. (cid:1) HIGH EFFICIENCY: Typical ground pin current is only 600µA (at I = 250mA) OUT µ I = 600 A at I = 250mA and drops to 10nA when not enabled. Unlike regulators with GND OUT µ Not Enabled: I = 0.01 A PNP pass devices, quiescent current remains relatively con- GND (cid:1) 2.5V, 2.8V, 2.85V, 3.0V, 3.3V, AND 5.0V stant over load variations and under dropout conditions. ADJUSTABLE OUTPUT VERSIONS The REG102 has very low output noise (typically 28µVrms (cid:1) OTHER OUTPUT VOLTAGES AVAILABLE UPON for VOUT = 3.3V with CNR = 0.01µF), making it ideal for use REQUEST in portable communications equipment. On-chip trimming (cid:1) FOLDBACK CURRENT LIMIT results in high output voltage accuracy. Accuracy is main- tained over temperature, line, and load variations. Key pa- (cid:1) THERMAL PROTECTION rameters are tested over the specified temperature range (cid:1) SMALL SURFACE-MOUNT PACKAGES: (–40°C to +85°C). SOT23-5, SOT223-5, and SO-8 The REG102 is well protected—internal circuitry provides a current limit that protects the load from damage; furthermore, APPLICATIONS thermal protection circuitry keeps the chip from being dam- aged by excessive temperature. The REG102 is available in (cid:1) PORTABLE COMMUNICATION DEVICES SOT23-5, SOT223-5, and SO-8 packages. (cid:1) BATTERY-POWERED EQUIPMENT (cid:1) PERSONAL DIGITAL ASSISTANTS (cid:1) MODEMS (cid:1) BAR-CODE SCANNERS (cid:1) BACKUP POWER SUPPLIES Enable Enable V V V V IN OUT IN OUT + 0.1µF (FixReEdG V1o0lt2age + COUT(1) + 0.1µF REG102-A R1 + COUT(1) Versions) Adj NR GND GND R2 NR = Noise Reduction NOTE: (1) Optional. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2000-2005, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC Supply Input Voltage, V .......................................................–0.3V to 12V DISCHARGE SENSITIVITY IN Enable Input Voltage, V .......................................................–0.3V to V EN IN Feedback Voltage, V ........................................................–0.3V to 6.0V FB This integrated circuit can be damaged by ESD. Texas NR Pin Voltage, V .............................................................–0.3V to 6.0V NR Output Short-Circuit Duration......................................................Indefinite Instruments recommends that all integrated circuits be handled Operating Temperature Range (TJ)................................–55°C to +125°C with appropriate precautions. Failure to observe proper han- Storage Temperature Range (T )...................................–65°C to +150°C Lead Temperature (soldering, 3As)..................................................+240°C dling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade tion to complete device failure. Precision integrated circuits device reliability. may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT V (2) OUT REG102xx-yyyy/zzz XX is package designator. YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable). ZZZ is package quantity. (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Output voltages from 2.5V to 5.1V in 50mV increments are available; minimum order quantities apply. Contact factory for details and availability. PIN CONFIGURATIONS Top View SOT23-5 SOT223-5 SO-8 V 1 5 V V (2) 1 8 V (3) IN OUT Tab is GND OUT IN GND 2 V (2) 2 7 V (3) OUT IN Enable 3 4 NR/Adjust(1) NR/Adjust(1) 3 6 NC 1 2 3 4 5 GND 4 5 Enable (N Package) VIN GND Enable (U Package) V NR/Adjust(1) OUT (G Package) NOTES: (1) For REG102A-A: voltage setting resistor pin. All other models: noise reduction capacitor pin. (2) Both pin 1 and pin 2 must be connected. (3) Both pin 7 and pin 8 must be connected. REG102 2 www.ti.com SBVS024F

ELECTRICAL CHARACTERISTICS ° ° Boldface limits apply over the specified temperature range, T = –40 C to +85 C. J At T = +25°C, V = V + 1V (V = 2.5V for REG102-A), V = 1.8V, I = 5mA, C = 0.01µF, and C = 0.1µF(1), unless otherwise noted. J IN OUT OUT ENABLE OUT NR OUT REG102NA REG102GA REG102UA PARAMETER CONDITION MIN TYP MAX UNITS OUTPUT VOLTAGE Output Voltage Range V OUT REG102-2.5 2.5 V REG102-2.8 2.8 V REG102-2.85 2.85 V REG102-3.0 3.0 V REG102-3.3 3.3 V REG102-5 5 V REG102-A 2.5 5.5 V Reference Voltage V 1.26 V REF Adjust Pin Current I 0.2 1 µA ADJ Accuracy ±0.5 ±1.5 % Over Temperature ±2.3 % vs Temperature dV /dT 50 ppm/°C OUT vs Line and Load I = 5mA to 250mA, V = (V + 0.4V) to 10V ±0.8 ±2.0 % Over Temperature OUT V = (V +I N0.6V)O tUoT 10V ±2.8 % IN OUT DC DROPOUT VOLTAGE(2) V I = 5mA 4 10 mV DROP OUT For all models I = 250mA 150 220 mV OUT Over Temperature I = 250mA 270 mV OUT VOLTAGE NOISE f = 10Hz to 100kHz V n Without C (all models) C = 0, C = 0 23µVrms/V • V µVrms NR NR OUT OUT With C (all fixed voltage models) C = 0.01µF, C = 10µF 7µVrms/V • V µVrms NR NR OUT OUT OUTPUT CURRENT Current Limit(3) I 340 400 470 mA CL Over Temperature 300 490 mA Short-Circuit Current Limit I 150 mA SC RIPPLE REJECTION f = 120Hz 65 dB ENABLE CONTROL V High (output enabled) V 1.8 V V ENABLE ENABLE IN V Low (output disabled) –0.2 0.5 V ENABLE I High (output enabled) I V = 1.8V to V , V = 1.8V to 6.5(4) 1 100 nA ENABLE ENABLE ENABLE IN IN I Low (output disabled) V = 0V to 0.5V 2 100 nA ENABLE ENABLE Output Disable Time C = 1.0µF, R = 13Ω 50 µs OUT LOAD Output Enable Softstart Time C = 1.0µF, R = 13Ω 1.5 ms OUT LOAD THERMAL SHUTDOWN Junction Temperature Shutdown 160 °C Reset from Shutdown 140 °C GROUND PIN CURRENT Ground Pin Current I I = 5mA 400 500 µA GND OUT I = 250mA 600 800 µA OUT Enable Pin Low V ≤ 0.5V 0.01 0.2 µA ENABLE INPUT VOLTAGE V IN Operating Input Voltage Range(5) 1.8 10 V Specified Input Voltage Range V > 1.8V V + 0.4 10 V IN OUT Over Temperature V > 1.8V V + 0.6 10 V IN OUT TEMPERATURE RANGE Specified Range T –40 +85 °C J Operating Range T –55 +125 °C J Storage Range T –65 +150 °C A Thermal Resistance SOT23-5 Surface-Mount θ Junction-to-Ambient 200 °C/W JA SO-8 Surface-Mount θ Junction-to-Ambient 150 °C/W JA SOT223-5 Surface-Mount θ Junction-to-Case 15 °C/W JC θ Junction-to-Ambient See Figure 8 °C/W JA NOTES: (1)The REG102 does not require a minimum output capacitor for stability, however, transient response can be improved with proper capacitor selection. (2)Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at V = V IN OUT + 1V at fixed load. (3)Current limit is the output current that produces a 10% change in output voltage from V = V + 1V and I = 5mA. IN OUT OUT (4)For V > 6.5V, see typical characteristic I vs V . ENABLE ENABLE ENABLE (5)The REG102 no longer regulates when V < V + V . In dropout, the impedance from V to V is typically less than 1Ω at T = +25°C. IN OUT DROP (MAX) IN OUT J REG102 3 SBVS024F www.ti.com

TYPICAL CHARACTERISTICS For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE OUTPUT VOLTAGE CHANGE vs I OUT (V = V + 1V, Output Voltage % Change LOAD REGULATION vs TEMPERATURE IN OUT Referred to IOUT = 125mA at +25°C) (VIN = VOUT + 1V) 0.80 0 0.60 –0.1 %) %) ange ( 00..4200 +25°C ange ( –0.2 25mA < IOUT < 250mA Ch +125°C Ch –0.3 e 0 e g g Volta –0.20 Volta –0.4 5mA < I < 250mA ut ut –0.5 OUT p –0.40 p Out –55°C Out –0.60 –0.6 –0.80 –0.7 0 25 50 75 100 125 150 175 200 225 250 –50 –25 0 25 50 75 100 125 I (mA) Temperature (°C) OUT LINE REGULATION (Referred to V = V + 1V at I = 125mA) LINE REGULATION vs TEMPERATURE IN OUT OUT 20 0 All Fixed Output I = 250mA mV) 15 Voltage Versions %) –0.05 OUT Output Voltage Change ( –1–105050 IOUT = 5mA IOUT = 125mA Output Voltage Change ( ––––0000....11220505 (VOUT + 1V) < VIN < 10V –15 (V + 0.4V) < V < 10V I = 250mA OUT IN OUT –20 –0.30 0 1 2 3 4 5 6 7 8 –50 –25 0 25 50 75 100 125 V – V (V) Temperature (°C) IN OUT DC DROPOUT VOLTAGE vs I DC DROPOUT VOLTAGE vs TEMPERATURE OUT 250 250 I = 250mA OUT mV) 200 +125°C mV) 200 e ( e ( g g a 150 a 150 olt olt V +25°C V ut ut po 100 po 100 o o Dr Dr C –55°C C D 50 D 50 0 0 0 50 100 150 200 250 –50 –25 0 25 50 75 100 125 I (mA) Temperature (°C) OUT REG102 4 www.ti.com SBVS024F

TYPICAL CHARACTERISTICS (Cont.) For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM 18 30 16 25 %) 14 %) nits ( 12 nits ( 20 U U e of 10 e of 15 g 8 g a a nt nt e 6 e 10 c c er er P 4 P 5 2 0 0 0 8 6 4 2 0 2 4 6 8 0 050505050505050505050 –1. –0. –0. –0. –0. 0. 0. 0. 0. 0. 1. 11223344556677889910 Error (%) V Drift (ppm/°C) OUT OUTPUT VOLTAGE vs TEMPERATURE (Output Voltage % Change Refered GROUND PIN CURRENT, NOT ENABLED to I = 125mA at +25°C) vs TEMPERATURE OUT 0.80 1µ V = 0.5V 0.60 ENABLE V = V + 1V %) IN OUT 0.40 nge ( 0.20 IOUT = 125mA IOUT = 5mA 100n a Ch 0 A) oltage –0.20 I (GND 10n V ut –0.40 I = 250mA p OUT 1n ut –0.60 O –0.80 –1.00 100p –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) GROUND PIN CURRENT vs I GROUND PIN CURRENT vs TEMPERATURE OUT 800 750 V = 5V I = 250mA OUT OUT 700 725 V = 5.0V OUT 600 700 500 675 µI (A)GND 430000 VOUT = 2.5V VOUT = 3.3V µI (A)GND 665205 VOUT = 3.3V 200 600 V = 2.5V OUT 100 575 0 550 0 25 50 75 100 125 150 175 200 225 250 –50 –25 0 25 50 75 100 125 I (mA) Temperature (°C) OUT REG102 5 SBVS024F www.ti.com

TYPICAL CHARACTERISTICS (Cont.) For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE RIPPLE REJECTION vs FREQUENCY RIPPLE REJECTION vs (V – V ) IN OUT 80 30 I = 2mA OUT 70 25 ction (dB) 6500 IOUT = 100mA CIOOUUTT == 21m0µAF ICOUOTU T= =1 0100mµFA ction (dB) 20 e 40 e 15 ej ej R R e 30 e pl pl 10 Rip 20 Rip Frequency = 100kHz 10 COUT = 0µF 5 CVOOUUTT == 31.03µVF I = 100mA OUT 0 0 10 100 1k 10k 100k 1M 10M 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Frequency (Hz) V – V (V) IN OUT RMS NOISE VOLTAGE vs COUT RMS NOISE VOLTAGE vs CNR 60 110 REG102-5.0 100 50 REG102-5.0 ms) ms) 90 REG102-3.3 Vr 40 Vr 80 µ µ e ( REG102-3.3 e ( 70 ag 30 ag olt olt 60 V V oise 20 oise 50 REG102-2.5 N REG102-2.5 N 40 10 COUT = 0.01µF 30 COUT = 0µF 10Hz < BW < 100kHz 10Hz < BW < 100kHz 0 20 0.1 1 10 1 10 100 1k 10k COUT (µF) CNR (pF) NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY 10 10 I = 100mA I = 100mA OUT OUT C = 0µF C = 0.01µF NR NR 1 1 Hz) COUT = 1µF Hz) √ √ V/ V/ µ (N C = 0µF µ (N COUT = 1µF e OUT e 0.1 0.1 C = 10µF COUT = 0µF OUT C = 10µF OUT 0.01 0.01 10 100 1k 10k 100k 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) REG102 6 www.ti.com SBVS024F

TYPICAL CHARACTERISTICS (Cont.) For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE CURRENT LIMIT FOLDBACK CURRENT LIMIT vs TEMPERATURE 3.5 450 V = V + 1V IN OUT 3.0 400 REG102-3.3 I = Current Limit CL V) 2.5 350 Voltage ( 2.0 ICL (mA)T300 ut 1.5 OU250 p I I = Short-Circuit Current ut SC O 1.0 200 I SC 0.5 150 0 100 0 50 100 150 200 250 300 350 400 450 –50 –25 0 25 50 75 100 125 Output Current (mA) Temperature (°C) LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE REG102-3.3 div REG102-3.3 mV/div VIN = 4.3V COUT = 0µF VOUT 50mV/ COUT = 0 IOUT = 250mA VOUT 0 20 mV/div COUT = 10µF V mV/div COUT = 10µF VOUT 50 OUT 0 0 2 250mA IOUT 5.3V V 4.3V IN 25mA 10µs/div 50µs/div TURN-ON TURN-OFF C = 0µF 1V/div RLOOAUDT = 660Ω C = 10µF RCLOOUATD == 01µ3FΩ VOUT 1V/div CROLOUATD = = C1R 10O3µUΩFT == 1 1.03µΩF VOUT ROLOUATD = 13Ω RCOUT == 606µ0FΩ LOAD LOAD v v V/di REG102-3.3 VENABLE V/di VENABLE 1 1 VIN = VOUT + 1V C = 0.01µF REG102-3.3 NR 250µs/div 200µs/div REG102 7 SBVS024F www.ti.com

TYPICAL CHARACTERISTICS (Cont.) For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE I vs V POWER UP/POWER DOWN ENABLE ENABLE 10µ V = 3.0V ROUT = 12Ω LOAD 1.0µ (A)ABLE 100n T = +25°C 0mV/div N 0 IE T = +125°C 5 10n T = –55°C 1n 6 7 8 9 10 1s/div V (V) ENABLE RMS NOISE VOLTAGE vs C ADJUST PIN CURRENT vs TEMPERATURE ADJ 80 0.350 V = 3.3V OUT 70 C = 0.1µF 0.300 OUT 10Hz < frequency < 100kHz 0.250 60 s) A) 0.200 m µ V (rN 50 I (ADJ 0.150 40 0.100 30 0.050 20 0 10 100 1k 10k 100k –50 –25 0 25 50 75 100 125 C (pF) Temperature (°C) ADJ LOAD TRANSIENT-ADJUSTABLE VERSION LINE TRANSIENT-ADJUSTABLE VERSION C = 0 C = 0 200mV/div OUT VOUT 50mV/div OUT VOUT C = 10µF 50mV/div OUT VOUT C = 10µF 200mV/div OUT V OUT REG102–A REG102–A I = 250mA V = 4.3V OUT 250mA IN 5.3V CFB = 0.01µF VOUT = 3.3V VOUT = 3.3V VIN 25mA I 4.3V OUT REG102 8 www.ti.com SBVS024F

BASIC OPERATION The REG102 series of LDO (low dropout) linear regulators offers a wide selection of fixed output voltage versions and an adjustable output version as well. The REG102 belongs Enable to a family of new generation LDO regulators that use a V In REG102 Out V IN OUT DMOS pass transistor to achieve ultra low-dropout perfor- 0.1µF GND NR COUT mance and freedom from output capacitor constraints. Ground C pin current remains under 1mA over all line, load, and 0.N0R1µF temperature conditions. All versions have thermal and over- current protection, including foldback current limit. Optional The REG102 does not require an output capacitor for regulator stability and is stable over most output currents and with almost any value and type of output capacitor up to 10µF or more. For FIGURE 1. Fixed Voltage Nominal Circuit for the REG102. applications where the regulator output current drops below several milliamps, stability can be enhanced by adding a 1kΩ the regulator from damage under all load conditions. A to 2kΩ load resistor, using capacitance values smaller than characteristic of V versus I is given in Figure 3 and in 10µF, or keeping the effective series resistance greater than OUT OUT the Typical Characteristics section. 0.05Ω including the capacitor ESR and parasitic resistance in printed circuit board traces, solder joints, and sockets. Although an input capacitor is not required, it is a good CURRENT LIMIT FOLDBACK standard analog design practice to connect a 0.1µF low ESR 3.5 capacitor across the input supply voltage. This is recom- 3 mended to counteract reactive input sources and improve REG102-3.3 ripple rejection by reducing input voltage ripple. V) 2.5 e ( ICL Figure 1 shows the basic circuit connections for the fixed ag 2 voltage models. Figure 2 gives the connections for the adjust- Volt able output version (REG102A) and example resistor values for put 1.5 ut some commonly used output voltages. Values for other volt- O 1 I SC ages can be calculated from the equation shown in Figure 2. 0.5 0 INTERNAL CURRENT LIMIT 0 50 100 150 200 250 300 350 400 450 Output Current (mA) The REG102 internal current limit has a typical value of 400mA. A foldback feature limits the short-circuit current to a typical short-circuit value of 150mA, which helps to protect FIGURE 3. Foldback Current Limit of the REG102-3.3 at 25°C. Enable 5 2 EXAMPLE RESISTOR VALUES V OUT 1 V (V) R (Ω)(1) R (Ω)(1) V C OUT 1 2 IN REG102 I R1 0.F0B1µF COUT 2.5 11.3k 11.5k ADJ 0.1µF 4 Load 1.13k 1.15k Adj 3.0 15.8k 11.5k 3 Gnd R2 1.58k 1.15k 3.3 18.7k 11.5k 1.87k 1.15k 5.0 34.0k 11.5k Optional 3.40k 1.15k Pin numbers for the SOT-223 package. NOTE: (1) Resistors are standard 1% values. V = (1 + R /R ) • 1.26V OUT 1 2 To reduce current through divider, increase resistor values (see table at right). As the impedance of the resistor divider increases, IADJ (~200nA) may introduce an error. C improves noise and transient response. FB FIGURE 2. Adjustable Voltage Circuit for the REG102A. REG102 9 SBVS024F www.ti.com

ENABLE RMS NOISE VOLTAGE vs C The Enable pin is active high and compatible with standard NR 110 TTL-CMOS levels. Inputs below 0.5V (max) turn the regula- 100 tor off and all circuitry is disabled. Under this condition, 90 ground pin current drops to approximately 10nA. When not ms) REG102-5.0 uuspe rde,s itshteo rE isn aubsleed p, iann cda onp beera ctioonnn beeclotewd 1to.8 VVI Nis. rWeqhueinre ad ,p uuslle- e (Vr 8700 REG102-3.3 g pull-up resistor values below 50kΩ. olta 60 REG102-2.5 V e s 50 oi OUTPUT NOISE N 40 A precision bandgap reference is used to generate the 30 COUT = 0µF 10Hz < BW < 100kHz internal reference voltage, V . This reference is the domi- REF 20 nant noise source within the REG102 and generates approxi- 0.1 10 100 1k 10k mately 29µVrms in the 10Hz to 100kHz bandwidth at the C (pF) NR reference output. The regulator control loop gains up the reference noise, so that the noise voltage of the regulator is FIGURE 5. Output Noise versus Noise Reduction Capacitor. approximately given by: R +R V Noise can be further reduced by carefully choosing an output VN=29µVrms 1R2 2 =29µVrms• VOREUFT (1) capacitor, COUT. Best overall noise performance is achieved with very low (< 0.22µF) or very high (> 2.2µF) values of C As the value of V is 1.26V, this relationship reduces to: OUT REF (see the RMS Noise Voltage vs C typical characteristic). OUT V =23 µVrms•V (2) The REG102 uses an internal charge pump to develop an N OUT V internal supply voltage sufficient to drive the gate of the DMOS pass element above V . The charge-pump switching Connecting a capacitor, C , from the Noise Reduction (NR) IN NR noise (nominal switching frequency = 2MHz) is not measur- pin to ground forms a low-pass filter for the voltage refer- able at the output of the regulator over most values of I ence. Adding C (as shown in Figure 4) forms a low-pass OUT NR and C . filter for the voltage reference. For C = 10nF, the total noise OUT NR in the 10Hz to 100kHz bandwidth is reduced by approxi- The REG102 adjustable version does not have the noise- mately a factor of 2.8 for V = 3.3V. This noise reduction reduction pin available; however, the adjust pin is the sum- OUT effect is shown in Figure 5 and as RMS Noise Voltage vs C ming junction of the error amplifier. A capacitor, C , con- NR FB in the Typical Characteristics section. nected from the output to the adjust pin can reduce both the output noise and the peak error from a load transient (see the typical characteristics for output noise performance). V IN NR Low-Noise (fixed output Charge Pump versions only) C NR (optional) VREF (1.26V) DMOS Output Over-Current VOUT Over Temp Enable Protection R1 Adj (adjustable R2 versions) REG102 NOTE: R and R are internal 1 2 on fixed output versions. FIGURE 4. Block Diagram. REG102 10 www.ti.com SBVS024F

DROPOUT VOLTAGE case conditions (full-scale load change with (V – V ) IN OUT voltage drop close to DC dropout levels), the REG102 can The REG102 uses an N-channel DMOS as the pass element. take several hundred microseconds to re-enter the specified When (V – V ) is less than the drop-out voltage (V ), IN OUT DROP window of regulation. the DMOS pass device behaves like a resistor; therefore, for low values of (V – V ), the regulator input-to-output IN OUT resistance is the Rds of the DMOS pass element (typically TRANSIENT RESPONSE ON 600mΩ). For static (DC) loads, the REG102 typically main- The REG102 response to transient line and load conditions tains regulation down to a (VIN – VOUT) voltage drop of 150mV improves at lower output voltages. The addition of a capacitor at full rated output current. In Figure 6, the bottom line (DC (nominal value 0.47µF) from the output pin to ground can dropout) shows the minimum VIN to VOUT voltage drop re- improve the transient response. In the adjustable version, the quired to prevent dropout under DC load conditions. addition of a capacitor, C (nominal value 10nF), from the FB For large step changes in load current, the REG102 requires output to the adjust pin can also improve the transient a larger voltage drop across it to avoid degraded transient response. response. The boundary of this transient drop-out region is shown as the top line in Figure 6 and values of V to V THERMAL PROTECTION IN OUT voltage drop above this line insure normal transient re- Power dissipated within the REG102 can cause the junction sponse. temperature to rise. The REG102 has thermal shutdown circuitry that protects the regulator from damage which dis- ables the output when the junction temperature reaches DROPOUT VOLTAGE vs IOUT approximately 160°C, allowing the device to cool. When the 350 junction temperature cools to approximately 140°C, the out- 300 put circuitry is again enabled. Depending on various condi- tions, the thermal protection circuit can cycle on and off. This V) 250 e (m 0mA to IOUT Transient limits the dissipation of the regulator, but can have an g 200 undesirable effect on the load. a olt V Any tendency to activate the thermal protection circuit indi- out 150 DC cates excessive power dissipation or an inadequate heat p Dro 100 sink. For reliable operation, junction temperature must be limited to 125°C, maximum. To estimate the margin of safety 50 in a complete design (including heat sink), increase the 0 ambient temperature until the thermal protection is triggered; 0 50 100 150 200 250 use worst-case loads and signal conditions. For good reliabil- I (mA) OUT ity, thermal protection should trigger more than 35°C above the maximum expected ambient condition of the application. FIGURE 6. Transient and DC Dropout. This produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case In the transient dropout region between DC and Transient, load. transient response recovery time increases. The time required The internal protection circuitry of the REG102 is designed to to recover from a load transient is a function of both the protect against overload conditions and is not intended to magnitude and rate of the step change in load current and the replace proper heat sinking. Continuously running the REG102 available headroom V to V voltage drop. Under worst- IN OUT into thermal shutdown will degrade reliability. REG102 11 SBVS024F www.ti.com

POWER DISSIPATION P =(V –V )•I (3) D IN OUT OUT The REG102 is available in three different package configu- Power dissipation can be minimized by using the lowest rations. The ability to remove heat from the die is different for possible input voltage necessary to assure the required each package type and, therefore, presents different consid- output voltage. erations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components REGULATOR MOUNTING moves the heat from the device to the ambient air. Although The tab of the SOT-223 package is electrically connected to it is difficult to impossible to quantify all of the variables in a ground. For best thermal performance, this tab must be thermal design of this type, performance data for several soldered directly to a circuit-board copper area. Increasing simplified configurations are shown in Figure 7. In all cases, the copper area improves heat dissipation, as shown in the PCB copper area is bare copper (free of solder resist Figure 8. mask), not solder plated, and are for 1-ounce copper. Using heavier copper will increase the effectiveness in moving the Although the tab of the SOT-223 is electrical ground, it is not heat from the device. In those examples where there is intended to carry current. The copper pad that acts as a heat copper on both sides of the PCB, no connection has been sink should be isolated from the rest of the circuit to prevent provided between the two sides. The addition of plated current flow through the device from the tab to the ground through holes will improve the heat sink effectiveness. pin. Solder pad footprint recommendations for the various REG102 devices are presented in Application Bulletin Solder Power dissipation depends on input voltage, load conditions, Pad Recommendations for Surface-Mount Devices and duty cycle and is equal to the product of the average (SBFA015), available from the Texas Instruments web site output current times the voltage across the output element, (www.ti.com). V to V voltage drop. IN OUT DEVICE DISSIPATION vs TEMPERATURE 2.5 CONDITIONS #1 s) 2 #2 CONDITION PACKAGE PCB AREA θ att #3 JA W #4 1 SOT-223 4in2 Top Side Only 53°C/W n ( 1.5 2 SOT-223 0.5in2 Top Side Only 110°C/W o ati 3 SO-8 — 150°C/W sip 4 SOT-23 — 200°C/W s 1 Di er w Po 0.5 0 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 7. Maximum Power Dissipation versus Ambient Temperature for the Various Packages and PCB Heat Sink Configurations. THERMAL RESISTANCE vs PCB COPPER AREA 180 Circuit-Board Copper Area REG102 W) 160 Surface-Mount Package C/ 140 1 oz. copper °θce, (JA112000 n a st 80 si e R 60 al m er 40 h T 20 REG102 0 SOT-223 Surface-Mount Package 0 1 2 3 4 5 Copper Area (inches2) FIGURE 8. Thermal Resistance versus PCB Area for the Five-Lead SOT-223. REG102 12 www.ti.com SBVS024F

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) REG102GA-2.5 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR R102G25 & no Sb/Br) REG102GA-2.85 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR R102285 & no Sb/Br) REG102GA-2.85G4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR R102285 & no Sb/Br) REG102GA-3 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 R102G30 & no Sb/Br) REG102GA-3.3 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 R102G33 & no Sb/Br) REG102GA-3.3/2K5 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 R102G33 & no Sb/Br) REG102GA-3.3G4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 R102G33 & no Sb/Br) REG102GA-3G4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 R102G30 & no Sb/Br) REG102GA-5 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 R102G50 & no Sb/Br) REG102GA-A ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR R102GA & no Sb/Br) REG102GA-A/2K5 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR R102GA & no Sb/Br) REG102GA-A/2K5G4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR R102GA & no Sb/Br) REG102GA-AG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS NIPDAU Level-2-260C-1 YEAR R102GA & no Sb/Br) REG102NA-2.5/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM RO2D & no Sb/Br) REG102NA-2.5/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM RO2D & no Sb/Br) REG102NA-2.8/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM RO2E & no Sb/Br) REG102NA-2.85/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM RO2N & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) REG102NA-2.85/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM RO2N & no Sb/Br) REG102NA-3.3/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2C & no Sb/Br) REG102NA-3.3/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2C & no Sb/Br) REG102NA-3/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2G & no Sb/Br) REG102NA-3/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2G & no Sb/Br) REG102NA-3/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2G & no Sb/Br) REG102NA-3/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2G & no Sb/Br) REG102NA-5/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2B & no Sb/Br) REG102NA-5/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2B & no Sb/Br) REG102NA-5/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2B & no Sb/Br) REG102NA-5/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO2B & no Sb/Br) REG102NA-A/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM RO2A & no Sb/Br) REG102NA-A/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM RO2A & no Sb/Br) REG102NA-A/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM RO2A & no Sb/Br) REG102UA-2.5 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR REG & no Sb/Br) 102U25 REG102UA-3 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 102U30 REG102UA-3.3 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 102U33 REG102UA-3.3/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 102U33 Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) REG102UA-3G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 102U30 REG102UA-5 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 102U50 REG102UA-5/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 102U50 REG102UA-5G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 102U50 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) REG102GA-3.3/2K5 SOT-223 DCQ 6 2500 330.0 12.4 7.1 7.45 1.88 8.0 12.0 Q3 REG102GA-A/2K5 SOT-223 DCQ 6 2500 330.0 12.4 7.1 7.45 1.88 8.0 12.0 Q3 REG102NA-2.5/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-2.8/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-2.8/250 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-2.85/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-2.85/250 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-2.85/3K SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-2.85/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-3.3/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-3.3/250 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-3.3/3K SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-3.3/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-3/250 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-3/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-3/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-3/3K SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-5/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) REG102NA-5/250 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-5/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-5/3K SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 REG102NA-A/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102NA-A/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG102UA-3.3/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 REG102UA-5/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) REG102GA-3.3/2K5 SOT-223 DCQ 6 2500 346.0 346.0 29.0 REG102GA-A/2K5 SOT-223 DCQ 6 2500 346.0 346.0 29.0 REG102NA-2.5/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG102NA-2.8/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG102NA-2.8/250 SOT-23 DBV 5 250 180.0 180.0 18.0 REG102NA-2.85/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG102NA-2.85/250 SOT-23 DBV 5 250 180.0 180.0 18.0 REG102NA-2.85/3K SOT-23 DBV 5 3000 180.0 180.0 18.0 REG102NA-2.85/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG102NA-3.3/250 SOT-23 DBV 5 250 203.0 203.0 35.0 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) REG102NA-3.3/250 SOT-23 DBV 5 250 180.0 180.0 18.0 REG102NA-3.3/3K SOT-23 DBV 5 3000 180.0 180.0 18.0 REG102NA-3.3/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG102NA-3/250 SOT-23 DBV 5 250 180.0 180.0 18.0 REG102NA-3/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG102NA-3/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG102NA-3/3K SOT-23 DBV 5 3000 180.0 180.0 18.0 REG102NA-5/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG102NA-5/250 SOT-23 DBV 5 250 180.0 180.0 18.0 REG102NA-5/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG102NA-5/3K SOT-23 DBV 5 3000 180.0 180.0 18.0 REG102NA-A/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG102NA-A/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG102UA-3.3/2K5 SOIC D 8 2500 367.0 367.0 35.0 REG102UA-5/2K5 SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page3

None

None

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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