REG101 REG101 SBVS026D – JULY 2001 – REVISED SEPTEMBER 2005 DMOS 100mA Low-Dropout Regulator FEATURES DESCRIPTION (cid:1) NEW DMOS TOPOLOGY: The REG101 is a family of low-noise, low-dropout linear regulators with low ground pin current. Its new DMOS Ultra Low Dropout Voltage: topology provides significant improvement over previous 60mV typ at 100mA designs, including low dropout voltage (only 60mV typ at Output capacitor NOT required for stability full load), and better transient performance. In addition, no (cid:1) FAST TRANSIENT RESPONSE output capacitor is required for stability, unlike conventional (cid:1) VERY LOW NOISE: 23µVrms low-dropout regulators that are difficult to compensate and require expensive low ESR capacitors greater than 1µF. (cid:1) HIGH ACCURACY: ±1.5% max Typical ground pin current is only 500µA (at I = 100mA) (cid:1) HIGH EFFICIENCY: OUT and drops to 10nA when not in enabled mode. Unlike regula- µ IGND = 500 A at IOUT = 100mA tors with PNP pass devices, quiescent current remains rela- Not Enabled: I = 10nA tively constant over load variation and under dropout condi- GND (cid:1) 2.5V, 2.8V, 2.85V, 3.0V, 3.3V, 5.0V, AND tions. ADJUSTABLE OUTPUT VERSIONS The REG101 has very low output noise (typically 23µVrms (cid:1) OTHER OUTPUT VOLTAGES AVAILABLE for VOUT = 3.3V with CNR = 0.01µF), making it ideal for use in portable communications equipment. Accuracy is main- UPON REQUEST tained over temperature, line, and load variations. Key (cid:1) FOLDBACK CURRENT LIMIT parameters are tested over the specified temperature range (cid:1) THERMAL PROTECTION (–40°C to +85°C). (cid:1) SMALL SURFACE-MOUNT PACKAGES: The REG101 is well protected—internal circuitry provides a current limit that protects the load from damage. Thermal SOT23-5 and SO-8 protection circuitry keeps the chip from being damaged by excessive temperature. The REG101 is available in the APPLICATIONS SOT23-5 and the SO-8 packages. (cid:1) PORTABLE COMMUNICATION DEVICES (cid:1) BATTERY-POWERED EQUIPMENT (cid:1) PERSONAL DIGITAL ASSISTANTS (cid:1) MODEMS (cid:1) BAR-CODE SCANNERS (cid:1) BACKUP POWER SUPPLIES Enable Enable V V V V IN OUT IN OUT + 0.1µF (FixReEdG V1o0lt1age + COUT(1) + 0.1µF REG101-A R1 + COUT(1) Versions) Adj NR Gnd Gnd R2 NR = Noise Reduction NOTE: (1) Optional. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2000-2005, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC Supply Input Voltage, V .......................................................–0.3V to 12V DISCHARGE SENSITIVITY IN Enable Input Voltage, V .......................................................–0.3V to V EN IN Feedback Voltage, V ........................................................–0.3V to 6.0V FB This integrated circuit can be damaged by ESD. Texas Instru- NR Pin Voltage, V .............................................................–0.3V to 6.0V NR Output Short-Circuit Duration......................................................Indefinite ments recommends that all integrated circuits be handled with Operating Temperature Range (TJ)................................–55°C to +125°C appropriate precautions. Failure to observe proper handling Storage Temperature Range (T )...................................–65°C to +150°C A and installation procedures can cause damage. Lead Temperature (soldering, 3s, SOT23-5, and SO-8).....................+240°C ESD damage can range from subtle performance degrada- NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade tion to complete device failure. Precision integrated circuits device reliability. may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT V (2) OUT REG101xx-yyyy/zzz XX is package designator. YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable). ZZZ is package quantity. (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Output voltages from 2.5V to 5.1V in 50mV increments are available; minimum order quantities apply. Contact factory for details and availability. PIN CONFIGURATIONS Top View SO-8 SOT23-5 V (2) 1 8 V (3) V 1 5 V OUT IN IN OUT V (2) 2 7 V (3) GND 2 OUT IN NR/Adjust(1) 3 6 NC Enable 3 4 NR/Adjust(1) GND 4 5 Enable (N Package) (U Package) NOTE: (1) For REG101A-A: voltage setting resistor pin. All other models: noise reduction capacitor pin. (2) Both pin 1 and pin 2 must be connected. (3) Both pin 7 and pin 8 must be connected. 2 REG101 SBVS026D

ELECTRICAL CHARACTERISTICS ° ° Boldface limits apply over the specified temperature range, T = –40 C to +85 C. J At T = +25°C, V = V + 1V (V = 2.5V for REG101-A), V = 1.8V, I = 2mA, C = 0.01µF, and C = 0.1µF(1), unless otherwise noted. J IN OUT OUT ENABLE OUT NR OUT REG101NA REG101UA PARAMETER CONDITION MIN TYP MAX UNITS OUTPUT VOLTAGE Output Voltage V OUT REG101-2.5 2.5 V REG101-2.8 2.8 V REG101-2.85 2.85 V REG101-3.0 3.0 V REG101-3.3 3.3 V REG101-5 5 V REG101-A 2.5 5.5 V Reference Voltage V 1.267 V REF Adjust Pin Current I 0.2 1 µA ADJ Accuracy ±0.5 ±1.5 % Over Temperature ±2.2 % vs Temperature dV /dT 50 ppm/°C OUT Includes Line and Load I = 2mA to 100mA, V = (V + 0.4V) to 10V ±0.8 ±2.0 % OUT IN OUT Over Temperature V = (V + 0.6V) to 10V ±2.7 % IN OUT DC DROPOUT VOLTAGE(2) V I = 2mA 4 10 mV DROP OUT For all models I = 100mA 60 100 mV OUT Over Temperature I = 100mA 130 mV OUT VOLTAGE NOISE V f = 10Hz to 100kHz n Without C C = 0, C = 0 23µVrms/V • V µVrms NR NR OUT OUT With C (all fixed voltage models) C = 0.01µF, C = 10µF 7µVrms/V • V µVrms NR NR OUT OUT OUTPUT CURRENT Current Limit(3) I 130 170 220 mA CL Over Temperature 110 240 mA Short-Circuit Current I 60 mA SC RIPPLE REJECTION f = 120Hz I = 100mA 65 dB OUT ENABLE CONTROL V High (output enabled) V 1.8 V V ENABLE ENABLE IN V Low (output disabled) –0.2 0.5 V ENABLE I High (output enabled) I V = 1.8V to V , V = 1.8V to 6.5(4) 1 100 nA ENABLE ENABLE ENABLE IN IN I Low (output disabled) V = 0V to 0.5V 2 100 nA ENABLE ENABLE Output Disable Time C = 1.0µF, R = 33Ω 200 µs OUT LOAD Output Enable Time C = 1.0µF, R = 33Ω 1.5 ms OUT LOAD THERMAL SHUTDOWN Junction Temperature Shutdown 160 °C Reset from Shutdown 140 °C GROUND PIN CURRENT Ground Pin Current I I = 2mA 400 500 µA GND OUT I = 100mA 500 650 µA OUT Enable Pin Low V ≤ 0.5V 0.01 0.2 µA ENABLE INPUT VOLTAGE V IN Operating Input Voltage Range(5) 1.8 10 V Specified Input Voltage Range V > 1.8V V + 0.4 10 V IN OUT Over Temperature V > 1.8V V + 0.6 10 V IN OUT TEMPERATURE RANGE Specified Range T –40 +85 °C J Operating Range T –55 +125 °C J Storage Range T –65 +150 °C A Thermal Resistance SOT23-5 Surface Mount θ Junction-to-Ambient 200 °C/W JA SO-8 Surface Mount θ Junction-to-Ambient 150 °C/W JA NOTES: (1)The REG101 does not require a minimum output capacitor for stability. However, transient response can be improved with proper capacitor selection. (2)Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at V = V + 1V at fixed IN OUT load. (3)Current limit is the output current that produces a 10% change in output voltage from V = V + 1V and I = 2mA. IN OUT OUT (4)For V > 6.5V, see typical characteristic “I vs V ”. ENABLE ENABLE ENABLE (5)The REG101 no longer regulates when V < V + V . In drop-out, the impedance from V to V is typically less than 1Ω at T = +25°C. IN OUT DROP (MAX) IN OUT J REG101 3 SBVS026D

TYPICAL CHARACTERISTICS For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE OUTPUT VOLTAGE CHANGE vs I OUT (V = V + 1V, Output Voltage % Change LOAD REGULATION vs TEMPERATURE IN OUT Referred to IOUT = 50mA at +25°C) (VIN = VOUT + 1V) 0.80 0.0% 0.60 %) %) Change ( 00..4200 +25°C +125°C Change ( –0.1% 10mA < IOUT < 100mA Voltage –00..2000 Voltage –0.2% Output –0.40 –55°C Output –0.3% 2mA < I < 1000mA –0.60 OUT –0.80 –0.4% 0 10 20 30 40 50 60 70 80 90 100 –50 –25 0 25 50 75 100 125 I (mA) Temperature (°C) OUT LINE REGULATION (Referred to V = V + 1V at I = 50mA) LINE REGULATION vs TEMPERATURE IN OUT OUT 20 0.10 I = 100mA OUT 15 0.08 mV) %) 0.06 Output Voltage Change ( –1–150050 IOUT =I O2UmT A= 100mIOAUT = 50mA Output Voltage Change ( –––000000......000000420246 (VOUT + 1V) < VIN < 10V –15 –0.08 (V + 0.4V) < V < 10V –20 –0.10 OUT IN 0 1 2 3 4 5 6 7 8 –50 –25 0 25 50 75 100 125 V – V (V) Temperature (°C) IN OUT DC DROPOUT VOLTAGE vs I DC DROPOUT VOLTAGE vs TEMPERATURE OUT 100 100 I = 100mA OUT V) 80 V) 80 e (m +125°C e (m g g Volta 60 +25°C Volta 60 ut ut po 40 po 40 o o C Dr –55°C C Dr D 20 D 20 0 0 0 10 20 30 40 50 60 70 80 90 100 –50 –25 0 25 50 75 100 125 I (mA) Temperature (°C) OUT 4 REG101 SBVS026D

TYPICAL CHARACTERISTICS (Cont.) For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM 18 30 16 25 %) 14 %) nits ( 12 nits ( 20 U U ge of 108 ge of 15 a a nt nt e 6 e 10 c c er er P 4 P 5 2 0 0 0 8 6 4 2 0 2 4 6 8 0 050505050505050505050 –1. –0. –0. –0. –0. 0. 0. 0. 0. 0. 1. 11223344556677889910 Error (%) V Drift (ppm/°C) OUT OUTPUT VOLTAGE vs TEMPERATURE (Output Voltage % Change Referred GROUND PIN CURRENT, NOT ENABLED to I = 50mA at +25°C) vs TEMPERATURE OUT 0.50 1µ V = 0.5V 0.40 ENABLE V = V + 1V %) 0.30 IN OUT ge ( 0.20 IOUT = 2mA 100n n a Ch 0.10 A) oltage –00..1000 IOUT = 50mA I (GND 10n V ut –0.20 p 1n Out –0.30 I = 100mA OUT –0.40 –0.50 100p –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) GROUND PIN CURRENT vs I GROUND PIN CURRENT vs TEMPERATURE OUT 600 600 V = 5V I = 100mA VOUT = 5.0V 575 OUT OUT 500 550 400 A) VOUT = 3.3V A) 525 V = 3.3V µ µ OUT (GND 300 VOUT = 2.5V (GND 500 I I 475 200 450 V = 2.5V 100 OUT 425 VIN = VOUT + 1V VIN = VOUT + 1V 0 400 0 10 20 30 40 50 60 70 80 90 100 –50 –25 0 25 50 75 100 125 I (mA) Temperature (°C) OUT REG101 5 SBVS026D

TTYPICAL CHARACTERISTICS (Cont.) For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE RIPPLE REJECTION vs FREQUENCY RIPPLE REJECTION vs (V – V ) IN OUT 80 30 IOUT = 2mA REG101-3.3 70 25 ction (dB) 6500 IOUT = 100mA CIOOUUTT == 21m0µAF ICOUOTU T= =1 0100mµFA ction (dB) 20 e 40 e 15 ej ej R R e 30 e pl pl 10 p p Ri 20 Ri 10 COUT = 0µF 5 FreqCuOeUnTc y= =1 01µ0F0kHz I = 100mA OUT 0 0 10 100 1k 10k 100k 1M 10M 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (Hz) V - V (V) IN OUT RMS NOISE VOLTAGE vs C RMS NOISE VOLTAGE vs C OUT NR 60 110 REG101-5.0 100 50 REG101-5.0 ms) ms) 90 REG101-3.3 Vr 40 Vr 80 µe ( REG101-3.3 µe ( 70 REG101-2.5 ag 30 ag olt olt 60 V V se 20 se 50 oi REG101-2.5 oi N N 40 10 CNR = 0.01µF 30 10Hz C< NBRW = <0µ 1F00kHz 10Hz < BW < 100kHz 0 20 0.1 1 10 1 10 100 1k 10k C (µF) C (pF) OUT NR NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY 10 10 I = 100mA I = 100mA OUT OUT C = 0µF C = 0.01µF NR NR 1 1 Hz) COUT = 1µF Hz) √ √ V/ V/ µ (N C = 0µF µ (N COUT = 1µF e OUT e 0.1 0.1 C = 10µF COUT = 0µF OUT C = 10µF OUT 0.01 0.01 10 100 1k 10k 100k 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) 6 REG101 SBVS026D

TYPICAL CHARACTERISTICS (Cont.) For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE FOLDBACK CURRENT LIMIT CURRENT LIMIT vs TEMPERATURE 3.5 180 3.0 160 I REG101-3.3 CL V) 2.5 140 Voltage ( 2.0 ICL (mA)T120 VIN = VOUT + 1V put 1.5 IOU100 ut O 1.0 80 I I SC SC 0.5 60 0 40 0 20 40 60 80 100 120 140 160 180 –50 –25 0 25 50 75 100 125 Output Current (mA) Temperature (°C) LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE REG101-3.3 REG101-3.3 mV/div VIN = 4.3V COUT = 0µF VOUT 0mV/div COUT = 0 IOUT = 100mA VOUT 0 5 0 2 mV/div COUT = 10µF VOUT 50mV/div COUT = 10µF VOUT 0 0 2 100mA IOUT 5.3V V 10mA 4.3V IN 10µs/div 50µs/div TURN-ON TURN-OFF RLCOOAUDT = = 1 06µ0F0Ω CROUT == 1 303µΩF v LOAD 1V/div CROLOUATD = = 1 303µΩF RCLOOUATD == 03µ3FΩ VOUT 1V/di RCOUT = = 1 06µ0F0Ω CROLUOTA D= = 1 3.03µΩF VOUT LOAD v v V/di REG101-3.3 VENABLE V/di VENABLE 1 1 VCINN =R =V O0U.0T 1+µ 1FV CRNERG =1 00.10-13µ.3F 250µs/div 200µs/div REG101 7 SBVS026D

TYPICAL CHARACTERISTICS (Cont.) For all models, at T = +25°C and V = 1.8V, unless otherwise noted. J ENABLE IENABLE vs VENABLE POWER UP/POWER DOWN 10µ V = 3.0V ROUT = 30Ω LOAD 1µ I (A)ENABLE 100n T = +125°C T = +25°C 500mV/div V V IN OUT 10n T = –55°C 1n 6 7 8 9 10 1s/div V (V) ENABLE RMS NOISE VOLTAGE vs C ADJUST PIN CURRENT vs TEMPERATURE ADJ 80 0.350 REG101–A 0.300 70 V = 3.3V OUT C = 0.1µF 0.250 60 OUT ms) 10Hz < frequency < 100kHz A) 0.200 µV (Vrn 50 µI (ADJ 0.150 40 0.100 30 0.050 20 0.000 10 100 1k 10k 100k –50 –25 0 25 50 75 100 125 C (pF) Temperature (°C) ADJ LOAD TRANSIENT-ADJUSTABLE VERSION LINE TRANSIENT-ADJUSTABLE VERSION C = 0 C = 0 200mV/div OUT VOUT 50mV/div OUT VOUT C = 10µF 50mV/div OUT VOUT C = 10µF 200mV/div OUT V OUT REG101–A REG101–A I = 100mA V = 4.3V OUT 100mA IN 5.3V CFB = 0.01µF VOUT = 3.3V VOUT = 3.3V VIN 10mA I 4.3V OUT 8 REG101 SBVS026D

BASIC OPERATION the input supply voltage. This is recommended to improve ripple rejection by reducing input voltage ripple. The REG101 series of LDO (Low Drop-Out) linear regula- Figure 1 shows the basic circuit connections for the fixed tors offers a wide selection of fixed output voltage versions voltage models. Figure 2 gives the connections for the and an adjustable output version. The REG101 belongs to a adjustable output version (REG101A) and example resistor family of new generation LDO regulators that utilize a values for some commonly used output voltages. Values for DMOS pass transistor to achieve ultra-low dropout perfor- other voltages can be calculated from the equation shown in mance and freedom from output capacitor constraints. Ground Figure 2. pin current remains under 650µA over all line, load, and temperature conditions. All versions have thermal and over- current protection, including foldback current limit. INTERNAL CURRENT LIMIT The REG101 does not require an output capacitor for regu- The REG101 internal current limit has a typical value of lator stability and is stable over most output currents and 170mA. A foldback feature limits the short-circuit current to with almost any value and type of output capacitor up to a typical short-circuit value of 60mA. This helps to protect 10µF or more. For applications where the regulator output the regulator from damage under all load conditions. A current drops below several milliamps, stability can be characteristic of VOUT versus IOUT is given in Figure 3 and enhanced by: adding a 1kΩ to 2kΩ load resistor; using in the Typical Characteristics section. capacitance values less than 10µF; or keeping the effective series resistance greater than 0.05Ω including the capacitor’s ESR and parasitic resistance in printed circuit board traces, FOLDBACK CURRENT LIMIT solder joints, and sockets. 3.5 Although an input capacitor is not required, it is good analog 3.0 design practice to connect a 0.1µF low ESR capacitor across REG101-3.3 V) 2.5 e ( ag 2.0 olt ICL V ut 1.5 p Enable ut O 1.0 VIN In REG101 Out VOUT ICL 0.5 0.1µF Gnd NR COUT 0 C NR 0 20 40 60 80 100 120 140 160 180 0.01µF Output Current (mA) Optional FIGURE 3. Foldback Current Limit of the REG101-3.3 at FIGURE 1. Fixed Voltage Nominal Circuit for REG101. 25°C. Enable 3 EXAMPLE RESISTOR VALUES 5 V OUT 1 V (V) R (W)(1) R (Ω)(1) V C OUT 1 2 IN REG101 I R1 0.F0B1µF COUT 2.5 11.3k 11.5k ADJ 0.1µF 4 Load 1.13k 1.15k Adj 3.0 15.8k 11.5k 2 Gnd R 1.58k 1.15k 2 3.3 18.7k 11.5k 1.87k 1.15k 5.0 34.0k 11.5k 3.40k 1.15k Optional NOTE: (1) Resistors are standard 1% values. Pin numbers for SOT23 package. V = (1 + R/R) • 1.267V OUT 1 2 To reduce current through divider, increase resistor values (see table at right). As the impedance of the resistor divider increases, I (~200nA) may introduce an error. ADJ C improves noise and transient response. FB FIGURE 2. Adjustable Voltage Circuit for REG101A. REG101 9 SBVS026D

ENABLE The Enable pin is active HIGH and compatible with stan- RMS NOISE VOLTAGE vs C NR dard TTL-CMOS levels. Inputs below 0.5V (max) turn the 110 regulator off and all circuitry is disabled. Under this condi- 100 REG101-5.0 tai opnu,l lg-ruopu rneds ipsitno rc uisr ruesnetd d, raonpds otop aepraptriooxni dmoawtenl yt o1 0VnA .= W 1.h8eVn ms) 90 REG101-3.3 IN Vr 80 is required, use values < 50kΩ. µ REG101-2.5 e ( 70 g a olt 60 OUTPUT NOISE V se 50 A precision band-gap reference is used for the internal oi N 40 reference voltage, VREF. This reference is the dominant 30 CNR = 0µF noise source within the REG101 and it generates approxi- 10Hz < BW < 100kHz mately 29µVrms in the 10Hz to 100kHz bandwidth at the 20 1 10 100 1k 10k reference output. The regulator control loop gains up the C (pF) reference noise, so that the noise voltage of the regulator is NR approximately given by: FIGURE 5. Output Noise versus Noise Reduction Capacitor. R +R V V =29µVrms 1 2 =29µVrms• OUT N R2 VREF achieved with very low (< 0.22µF) or very high (> 2.2µF) values of C . See “RMS Noise Voltage vs C ” in the Since the value of V is 1.267V, this relationship reduces to: OUT OUT REF Typical Characteristics section. µVrms The REG101 utilizes an internal charge pump to develop an V =23 •V N V OUT internal supply voltage sufficient to drive the gate of the DMOS pass element above V . The charge-pump switch- Connecting a capacitor, C , from the Noise Reduction (NR) IN NR ing noise (nominal switching frequency = 2MHz) is not pin to ground, as shown in Figure 4, forms a low-pass filter for measurable at the output of the regulator over most values of the voltage reference. For C = 10nF, the total noise in the NR C and I . 10Hz to 100kHz bandwidth is reduced by approximately a OUT OUT The REG101 adjustable version does not have the noise- factor of 2.8 for V = 3.3V. This noise reduction effect is O reduction pin available, however, the adjust pin is the sum- shown in Figure 5 and as “RMS Noise Voltage vs CNR” in the ming junction of the error amplifier. A capacitor, C , Typical Characteristics section. FB connected from the output to the adjust pin will reduce both Noise can be further reduced by carefully choosing an the output noise and the peak error from a load transient. See output capacitor, C . Best overall noise performance is OUT the typical characteristics for output noise performance. V IN NR Low Noise (fixed output Charge Pump versions only) C(oNpRtional) (1V.2R6EFV) DMOS Pass Transistor Over Current V OUT Over Temp Enable Protection R1 Adj (Adjustable R2 Versions) REG101 NOTE: R and R are internal 1 2 on fixed output versions. FIGURE 4. Block Diagram. 10 REG101 SBVS026D

DROP-OUT VOLTAGE TRANSIENT RESPONSE The REG101 uses an N-channel DMOS as the “pass” The REG101 response to transient line and load conditions element. When the input voltage is within a few tens of improves at lower output voltages. The addition of a capaci- millivolts of the output voltage, the DMOS device behaves tor (nominal value 0.47µF) from the output pin to ground like a resistor. Therefore, for low values of V to V , the may improve the transient response. In the adjustable ver- IN OUT regulator’s input-to-output resistance is the Rds of the sion, the addition of a capacitor, C (nominal value 10nF), ON FB DMOS pass element (typically 600mΩ). For static (DC) from the output to the adjust pin will also improve the loads, the REG101 will typically maintain regulation down transient response. to V to V voltage drop of 60mV at full rated output IN OUT current. In Figure 6, the bottom line (DC dropout) shows the THERMAL PROTECTION minimum V to V voltage drop required to prevent IN OUT The REG101 has thermal shutdown circuitry that protects drop-out under DC load conditions. the regulator from damage. The thermal protection circuitry For large step changes in load current, the REG101 requires disables the output when the junction temperature reaches a larger voltage drop across it to avoid degraded transient approximately 160°C, allowing the device to cool. When the response. The boundary of this “transient drop-out” region is junction temperature cools to approximately 140°C, the shown as the top line in Figure 6. Values of VIN to VOUT output circuitry is again enabled. Depending on various voltage drop above this line insure normal transient re- conditions, the thermal protection circuit may cycle on and sponse. off. This limits the dissipation of the regulator, but may have In the transient dropout region between “DC” and “Tran- an undesirable effect on the load. sient”, transient response recovery time increases. The time Any tendency to activate the thermal protection circuit required to recover from a load transient is a function of both indicates excessive power dissipation or an inadequate heat the magnitude and rate of the step change in load current and sink. For reliable operation, junction temperature should be the available “headroom” VIN to VOUT voltage drop. Under limited to 125°C, maximum. To estimate the margin of worst-case conditions (full-scale load change with VIN to safety in a complete design (including heat sink), increase VOUT voltage drop close to DC dropout levels), the REG101 the ambient temperature until the thermal protection is can take several hundred microseconds to re-enter the speci- triggered. Use worst-case loads and signal conditions. For fied window of regulation. good reliability, thermal protection should trigger more than 35°C above the maximum expected ambient condition of your application. This produces a worst-case junction tem- 140 perature of 125°C at the highest expected ambient tempera- ture and worst-case load. 120 The internal protection circuitry of the REG101 has been V)100 Full Scale IOUT m Transient designed to protect against overload conditions. It was not ge ( 80 intended to replace proper heat sinking. Continuously run- a olt ning the REG101 into thermal shutdown will degrade reli- V ut 60 ability. o p Dro 40 DC 20 0 0 25 50 75 100 125 150 I (mA) OUT FIGURE 6. Transient and DC Dropout. REG101 11 SBVS026D

POWER DISSIPATION Power dissipation can be minimized by using the lowest The REG101 is available in two different package configu- possible input voltage necessary to assure the required rations. The ability to remove heat from the die is different output voltage. for each package type and, therefore, presents different considerations in the printed circuit board (PCB) layout. The REGULATOR MOUNTING PCB area around the device that is free of other components Solder pad footprint recommendations for the various moves the heat from the device to the ambient air. While it REG101 devices are presented in the Application Bulletin is difficult to impossible to quantify all of the variables in a AB-132, “Solder Pad Recommendations for Surface-Mount thermal design of this type, performance data for several Devices” (SBFA015), available from the Texas Instruments configurations are shown in Figure 7. web site (www.ti.com). Power dissipation depends on input voltage, load condition, and duty cycle. Power dissipation is equal to the product of the average output current times the voltage across the output element, V to V voltage drop. IN OUT ( ) P = V –V •I D IN OUT OUT(AVG) 1.2 CONDITIONS 1.0 SOT23-5 W) SO-8 n ( 0.8 atio PACKAGE θ JA sip 0.6 SOT23-5 200°C/W s Di SO-8 150°C/W er 0.4 w o P 0.3 0 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 7. Maximum Power Dissipation versus Ambient Temperature for the Various Packages. 12 REG101 SBVS026D

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) REG101NA-2.5/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1G & no Sb/Br) REG101NA-2.5/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1G & no Sb/Br) REG101NA-2.8/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1E & no Sb/Br) REG101NA-2.85/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1N & no Sb/Br) REG101NA-2.85/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1N & no Sb/Br) REG101NA-3.3/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C & no Sb/Br) REG101NA-3.3/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C & no Sb/Br) REG101NA-3.3/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C & no Sb/Br) REG101NA-3.3/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1C & no Sb/Br) REG101NA-3/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 R01D & no Sb/Br) REG101NA-3/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 R01D & no Sb/Br) REG101NA-5/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1B & no Sb/Br) REG101NA-5/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1B & no Sb/Br) REG101NA-5/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1B & no Sb/Br) REG101NA-A/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A & no Sb/Br) REG101NA-A/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A & no Sb/Br) REG101NA-A/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 RO1A & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) REG101UA-2.5 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101U25 REG101UA-2.5G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101U25 REG101UA-3 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101U30 REG101UA-3.3 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101U33 REG101UA-3.3/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101U33 REG101UA-3.3G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101U33 REG101UA-5 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101U50 REG101UA-5/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101U50 REG101UA-A ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101UA REG101UA-AG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 REG & no Sb/Br) 101UA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) REG101NA-2.5/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-2.5/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-2.8/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-2.85/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-2.85/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-3.3/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-3.3/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-3/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-3/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-5/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-5/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-A/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101NA-A/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG101UA-3.3/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 REG101UA-5/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) REG101NA-2.5/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG101NA-2.5/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG101NA-2.8/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG101NA-2.85/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG101NA-2.85/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG101NA-3.3/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG101NA-3.3/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG101NA-3/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG101NA-3/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG101NA-5/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG101NA-5/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG101NA-A/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG101NA-A/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG101UA-3.3/2K5 SOIC D 8 2500 367.0 367.0 35.0 REG101UA-5/2K5 SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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