RClamp0514M RailClamp Low Capacitance TVS Diode Array  PPRROOTTEECCTTIIOONN PPRROODDUUCCTTSS - RailClamp PRELIMINARY Description Features RailClamps are ultra low capacitance TVS arrays (cid:139) ESD protection for high-speed data lines to designed to protect high speed data interfaces. This IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) series has been specifically designed to protect sensi- IEC 61000-4-5 (Lightning) 5A (8/20µs) tive components which are connected to high-speed IEC 61000-4-4 (EFT) 40A (5/50ns) data and transmission lines from overvoltage caused (cid:139) Array of surge rated diodes with internal TVS Diode by ESD (electrostatic discharge), CDE (Cable Discharge (cid:139) Small package saves board space Events), and EFT (electrical fast transients). (cid:139) Protects four I/O lines and one Vcc line The RClampTM0514M has a typical capacitance of only (cid:139) Low capacitance: 0.7pF typical (Line-to-Line) 0.70pF (I/O to I/O). This means it can be used on (cid:139) Low clamping voltage circuits operating in excess of 2GHz without signal (cid:139) Low operating voltage: 5.0V attenuation. They may be used to meet the ESD (cid:139) Solid-state silicon-avalanche technology immunity requirements of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge). Mechanical Characteristics These devices are in a MSOP 10L package and feature a (cid:139) JEDEC MSOP 10L package lead-free, matte tin finish. They are compatible with both (cid:139) Molding compound flammability rating: UL 94V-0 lead free and SnPb assembly techniques. They are de- (cid:139) Marking : Marking code and date code signed for easy PCB layout by allowing the traces to run (cid:139) Packaging : Tape and Reel per EIA 481 straight through the device. The combination of small size, low capacitance, and high level of ESD protection (cid:139) Lead Finish: Matte Tin makes them a flexible solution for protecting high-speed (cid:139) RoHS/WEEE Compliant HDMI and DVI video interfaces. Applications (cid:139) High Definition Multi-Media Interface (HDMI) (cid:139) Digital Visual Interface (DVI) (cid:139) 10/100/1000 Ethernet (cid:139) Monitors and Flat Panel Displays (cid:139) Notebook Computers (cid:139) Set Top Box (cid:139) Projection TV Circuit Diagram Schematic & PIN Configuration Line 1 1 NC Pin 3 NC Line 2 Vcc GND Pin 1 Pin 4 Pin 6 Pin 9 Line 3 NC NC Line 4 Pin 8 MSOP-10L (Top View) Revision 08/31/2005 1 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Absolute Maximum Rating Rating Symbol Value Units PeakPulsePower(tp =8/20µs) P 125 Watts pk PeakPulseCurrent (tp =8/20µs) I 5 A PP ESDperIEC61000-4-2(Air) V 15 kV ESD ESDperIEC61000-4-2(Contact) 8 Operating Temperature T -55to+125 °C J StorageTemperature T -55to+150 °C STG Electrical Characteristics (T=25oC) Parameter Symbol Conditions Minimum Typical Maximum Units ReverseStand-Off Voltage V Pin 3to8 5 V RWM ReverseBreakdown Voltage V I =1mA 6 V BR t Pin 3to8 ReverseLeakageCurrent I V =5V, T=25°C 1 µA R RWM Pin 3to8 Clamping Voltage V I =1A, tp =8/20µs 15 V C PP Any I/Opin toground Clamping Voltage V I =5A, tp =8/20µs 20 V C PP Any I/Opin toground V =0V, f =1MHz 0.70 0.9 pF Junction Capacitance C R j Between I/Opins V =0V, f =1MHz 1.4 pF Junction Capacitance C R j Any I/Opin toground  2005 Semtech Corp. 2 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 10 110 100 W) 90 wer - P (kPP 1 Power or IPP 678000 ak Pulse Po 0.1 % of Rated 345000 Pe 20 10 0.01 0 0.1 1 10 100 1000 0 25 50 75 100 125 150 Pulse Duration - tp (µs) Ambient Temperature - T (oC) A Pulse Waveform Clamping Voltage vs. Peak Pulse Current 110 18 Waveform 100 Parameters: 16 Line to Line 90 tr = 8µs 80 td = 20µs (V)C 14 Percent of IPP 45670000 e-t td = I /2 ping Voltage -V 110268 Line to Gnd PP m 30 a Waveform Cl 4 Parameters: 20 tr = 8µs 2 td = 20µs 10 0 0 0 1 2 3 4 5 6 0 5 10 15 20 25 30 Peak Pulse Current - I (A) PP Time (µs) Forward Voltage vs. Forward Current Normalized Capacitance vs. Reverse Voltage 3.5 1.5 3 V) 2.5 ge ( 0) 1 Line to Line olta 2 VR= d V 1.5 CJ( war R) / Line to Ground For 1 Waveform J(V 0.5 Parameters: C 0.5 tr = 8µs td = 20µs 0 f = 1 MHz 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 Peak Pulse Current (A) Reverse Voltage - V (V) R  2005 Semtech Corp. 3 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Typical Characteristics (Con’t) Insertion Loss S21 - I/O to I/O Insertion Loss S21 - I/O to GND CH1 S21 LOG 6 dB / REF 0 dB CH1 S21 LOG 6 dB / REF 0 dB 1: .23330 dB 1: .31740 dB 900 MHz 900 MHz 2: -.24620 dB 2: -.77300 dB 1.8 GHz 1.8 GHz 3: -2.1013 dB 3: -4.0112 dB 1 2 .5 GHz 2 .5 GHz 0 dB 0 dB 2 3 1 2 3 -6 dB -6 dB -12 dB -12 dB -18 dB -18 dB -24 dB -24 dB -30 dB -30 dB -36 dB -36 dB 1 10 100 1 3 1 10 100 1 3 MHz MHz MHz GHz GHz MHz MHz MHz GHz GHz START . 030 MHz STOP 3 000. 0000 00 MHz START . 030 MHz STOP 3 000. 0000 00 MHz Analog Cross Talk CH1 S21 LOG 20 dB /R EF 0 dB START . 030 MHz STOP 3 000. 0000 00 MHz  2005 Semtech Corp. 4 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Applications Information Device Connection Options for Protection of Four High-Speed Data Lines FFFFFiiiiiggggguuuuurrrrreeeee 11111..... FFFFFlllllooooowwwww ttttthhhhhrrrrrooooouuuuuggggghhhhh LLLLLaaaaayyyyyooooouuuuuttttt fffffooooorrrrr tttttwwwwwooooo LLLLLiiiiinnnnneeeee PPPPPaaaaaiiiiirrrrrsssss The RClamp0514M TVS is designed to protect four data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus Line 1 1 Line 1 diode V ) the steering diodes are forward biased, Line 2 Line 2 F conducting the transient current away from the Vcc Gnd sensitive circuitry. Line 3 Line 3 Line 4 Line 4 Flow Through Layout The RClamp0514M is designed for have ease of PCB layout by allowing the traces to run straight through the device. Figure 1 shows the proper way to design the PCB FFFFFiiiiiggggguuuuurrrrreeeee 22222..... DDDDDaaaaatttttaaaaa LLLLLiiiiinnnnneeeee aaaaannnnnddddd PPPPPooooowwwwweeeeerrrrr SSSSSuuuuupppppppppplllllyyyyy PPPPPrrrrrooooottttteeeeeccccctttttiiiiiooooonnnnn board trace in order to use the flow through layout for UUUUUsssssiiiiinnnnnggggg VVVVVcccccccccc aaaaasssss rrrrreeeeefffffeeeeerrrrreeeeennnnnccccceeeee two line pairs. The solid line represents the PCB trace. Note that the PCB traces are used to connect the pin pairs for each line (pin 1 to pin 10, pin 2 to pin 9, pin 4 Line 1 to pin 7, pin 5 to pin 6). For example, line 1 enters at Line 1 1 Line 2 pin 1 and exits at Pin 10 and the PCB trace connects pin Line 2 Gnd 1 and 10 together. This is true for lines 2, 3, and 4. The Vcc negative reference (Gnd) is connected at pin 8. This pin Line 3 Line 3 should be connected directly to a ground plane on the Line 4 Line 4 board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference is connected at pin 3. The options for connecting the positive reference are as follows: FFFFFiiiiiggggguuuuurrrrreeeee 33333..... DDDDDaaaaatttttaaaaa LLLLLiiiiinnnnneeeee PPPPPrrrrrooooottttteeeeeccccctttttiiiiiooooonnnnn UUUUUsssssiiiiinnnnnggggg IIIIInnnnnttttteeeeerrrrrnnnnnaaaaalllll TTTTTVVVVVSSSSS 1. Figure 2 shows the connection scheme to protect DDDDDiiiiiooooodddddeeeee aaaaasssss RRRRReeeeefffffeeeeerrrrreeeeennnnnccccceeeee both data lines and the power line by connecting pin 3 directly to the positive supply rail (V ). In this CC Line 1 configuration the data lines are referenced to the Line 1 1 Line 2 supply voltage. The internal TVS diode prevents Line 2 over-voltage on the supply rail. NC Gnd 2. In applications where no positive supply reference is Line 3 Line 3 available, or complete supply isolation is desired, Line 4 Line 4 figure 3 shows how the internal TVS may be used as the reference. In this case, pin 3 is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop). This ease of layout coupled with the low capacitance and clamping voltage of the RClamp0514M makes it the superior choice to protect two high speed line pairs.  2005 Semtech Corp. 5 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Applications Information (continued) ESD Protection With RailClamps RailClamps are optimized for ESD protection using the rail-to-rail topology. Along with good board layout, these devices virtually eliminate the disadvantages of using discrete components to implement this topology. Con- PIN Descriptions sider the situation shown in Figure 4 where discrete diodes or diode arrays are configured for rail-to-rail protection on a high speed line. During positive duration ESD events, the top diode will be forward biased when the voltage on the protected line exceeds the reference voltage plus the V drop of the diode. For negative F events, the bottom diode will be biased when the voltage exceeds the V of the diode. At first approximation, the F FFFFFiiiiiggggguuuuurrrrreeeee 44444 ----- “““““RRRRRaaaaaiiiiilllll-----TTTTTooooo-----RRRRRaaaaaiiiiilllll””””” PPPPPrrrrrooooottttteeeeeccccctttttiiiiiooooonnnnn TTTTTooooopppppooooolllllooooogggggyyyyy clamping voltage due to the characteristics of the protec- (((((FFFFFiiiiirrrrrsssssttttt AAAAApppppppppprrrrroooooxxxxxiiiiimmmmmaaaaatttttiiiiiooooonnnnn))))) tion diodes is given by: V = V + V (for positive duration pulses) C CC F V = -V (for negative duration pulses) C F However, for fast rise time transient events, the effects of parasitic inductance must also be considered as shown in Figure 5. Therefore, the actual clamping voltage seen by the protected circuit will be: V = V + V + L di /dt (for positive duration pulses) C CC F P ESD V = -V - L di /dt (for negative duration pulses) C F G ESD ESD current reaches a peak amplitude of 30A in 1ns for a level 4 ESD contact discharge per IEC 61000-4-2. FFFFFiiiiiggggguuuuurrrrreeeee 55555 ----- TTTTThhhhheeeee EEEEEffffffffffeeeeeccccctttttsssss ooooofffff PPPPPaaaaarrrrraaaaasssssiiiiitttttiiiiiccccc IIIIInnnnnddddduuuuuccccctttttaaaaannnnnccccceeeee Therefore, the voltage overshoot due to 1nH of series WWWWWhhhhheeeeennnnn UUUUUsssssiiiiinnnnnggggg DDDDDiiiiissssscccccrrrrreeeeettttteeeee CCCCCooooommmmmpppppooooonnnnneeeeennnnntttttsssss tttttooooo IIIIImmmmmpppppllllleeeeemmmmmeeeeennnnnttttt inductance is: RRRRRaaaaaiiiiilllll-----TTTTTooooo-----RRRRRaaaaaiiiiilllll PPPPPrrrrrooooottttteeeeeccccctttttiiiiiooooonnnnn V = L di /dt = 1X10-9 (30 / 1X10-9) = 30V P ESD Example: Consider a V = 5V, a typical V of 30V (at 30A) for the CC F steering diode and a series trace inductance of 10nH. The clamping voltage seen by the protected IC for a positive 8kV (30A) ESD pulse will be: V = 5V + 30V + (10nH X 30V/nH) = 335V C This does not take into account that the ESD current is directed into the supply rail, potentially damaging any components that are attached to that rail. Also note FFFFFiiiiiggggguuuuurrrrreeeee 66666 ----- RRRRRaaaaaiiiiilllll-----TTTTTooooo-----RRRRRaaaaaiiiiilllll PPPPPrrrrrooooottttteeeeeccccctttttiiiiiooooonnnnn UUUUUsssssiiiiinnnnnggggg RRRRRaaaaaiiiiilllllCCCCClllllaaaaammmmmppppp TTTTTVVVVVSSSSS AAAAArrrrrrrrrraaaaayyyyysssss  2005 Semtech Corp. 6 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Applications Information (continued) that it is not uncommon for the V of discrete diodes to F exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical dis- crete components. It is also possible that the power dissipation capability of the discrete diode will be ex- ceeded, thus destroying the device. The RailClamp is designed to overcome the inherent disadvantages of using discrete signal diodes for ESD suppression. The RailClamp’s integrated TVS diode helps to mitigate the effects of parasitic inductance in the power supply connection. During an ESD event, the current will be directed through the integrated TVS diode to ground. The maximum voltage seen by the protected IC due to this path will be the clamping voltage of the device. Circuit Board Layout Recommendations for Suppres- sion of ESD. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: (cid:122) Place the device near the input terminals or connec- tors to restrict transient coupling. (cid:122) Minimize the path length between the TVS and the protected line. (cid:122) Minimize all conductive loops including power and ground loops. (cid:122) The ESD transient return path to ground should be kept as short as possible. (cid:122) Never run critical signals near board edges. (cid:122) Use ground planes whenever possible. Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small com- pared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint.  2005 Semtech Corp. 7 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Applications Information The HDMI Compliance Test Specification (CTS) requires sink (receiver) ports maintain a differential impedance of 100 Ohms +/- 15%. The measurement is taken B using a Time Domain Reflectometry (TDR) method that utilizes a pulse with a risetime <= 200ps. ESD protection devices have an inherent junction capacitance. Even a small amount of added capaci- tance on an HDMI port will cause the impedance of the differential pair to drop. As such, some form of A compensation to the layout will be required to bring C the differential pairs back within the required 100 Ohm +/- 15% range. The higher the added capaci- tance, the more extreme the modifications will need to be. If the added capacitance is too high, compensa- tion may not even be possible. The RClamp0514M presents <1pF capacitance between the pairs while being rated to handle >8kV ESD contact discharges A B C (>15kV air discharge) as outlined in IEC 61000-4-2. X-axis 1.640 1.796 1.953 (nsec) As such, it is possible to make minor adjustments to Y-axis 99.3 105.3 98.7 (Ohm) the board layout parameters to compensate for the added capacitance of the RClamp0514M. Figure 7 shows how to implement the RClamp0514M in an Figure 8 - TDR Measurement using Semtech HDMI application (transmitter and receiver). Figure 8 Evaluation Board shows impedance test results using a Semtech evalua- tion board with layout compensation. As shown, the device meets the HDMI CTS impedance requirements. 1 1 1 1 Figure 7 - HDMI Schematic  2005 Semtech Corp. 8 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Applications Information Spice Model RClamp0514M Spice Model & Parameters I/O Line nH Figure 9 - RClamp0514M Spice Model Table 1-RClamp0514M Spice Parameters Parameter Unit D1(LCRD) D2(LCRD) D3(TVS) IS Amp 4.01E-18 4.01E-18 3.39E-15 BV Volt 180 20 7.66 VJ Volt 0.68 0.67 0.61 RS Ohm 0.38 0.548 0.637 IBV Amp 1E-3 1E-3 1E-3 CJO Farad 0.7E-12 0.7E-12 190E-12 TT sec 2.541E-9 2.541E-9 2.541E-9 M -- 0.01 0.01 0.23 N -- 1.1 1.1 1.1 EG eV 1.11 1.11 1.11  2005 Semtech Corp. 9 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY OOuuttlliinnee DDrraawwiinngg -- MSOS-O8P 10L DIMENSIONS e INCHES MILLIMETERS DIM A D MIN NOMMAX MIN NOMMAX N A - - .043 - - 1.10 A1 .000 - .006 0.00 - 0.15 SEE DETAIL A A2 .030 - .037 0.75 - 0.95 2X E/2 SIDE VIEW b .007 - .011 0.17 - 0.27 c .003 - .009 0.08 - 0.23 E1 E D .114 .118 .122 2.90 3.00 3.10 PIN 1 E1 .114 .118 .122 2.90 3.00 3.10 INDICATOR H E .193 BSC 4.90 BSC e .020 BSC 0.50 BSC L .016 .024 .032 0.40 0.60 0.80 ccc C 12 GAGE c L1 (.037) (.95) 2X N/2 TIPS B PLANE 0N1 0° 1-0 8° 0° 1-0 8° aaa .004 0.10 0.25 L 01 bbb .003 0.08 (L1) ccc .010 0.25 D aaa C DETAILA A2 A SEATING PLANE C A1 bxN bbb C A-B D NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS - A - AND - B - TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP 10L X DIMENSIONS DIM INCHES MILLIMETERS C (.161) (4.10) (C) G Z G .098 2.50 P .020 0.50 X .011 0.30 Y .063 1.60 Y Z .224 5.70 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.  2005 Semtech Corp. 10 www.semtech.com

RClamp0514M PROTECTION PRODUCTS PRELIMINARY Marking Codes 514M XXXX * XXXX = Date Code ** Dot indicates Pin 1 Ordering Information Lead Qtyper Reel Part Number Finish Reel Size RClamp0514M.TBT MatteSn 500 7Inch Note: Lead finish is lead-free matte tin. RailClamp and RClamp are marks of Semtech Corporation. Contact Information Semtech Corporation Protection Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2005 Semtech Corp. 11 www.semtech.com