(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5) (cid:6)(cid:7)(cid:8)(cid:9) (cid:10)(cid:11)(cid:12)(cid:10)(cid:13)(cid:14)(cid:15)(cid:1)(cid:16)(cid:17)(cid:1)(cid:18)(cid:8)(cid:19)(cid:2)(cid:15) (cid:17)(cid:14)(cid:15)(cid:1)(cid:8)(cid:20)(cid:11)(cid:17)(cid:19)(cid:8)(cid:9) (cid:8)(cid:18)(cid:14)(cid:9)(cid:11)(cid:16)(cid:11)(cid:15)(cid:1) SLOS074 − D2785, OCTOBER 1983 — REVISED JUNE 1988 • Matched Gain and Offset Between D OR P PACKAGE Amplifiers (TOP VIEW) • Unity-Gain Bandwidth...3 MHz Min • OUT 1 8 VCC+ Slew Rate...1.5 V/ns Min AMP # 1 IN− 2 7 OUT • Low Equivalent Input Noise Voltage IN+ 3 6 IN− AMP # 2 2 µV/Hz Max (20 Hz to 20 kHz) VCC− 4 5 IN+ • No Frequency Compensation Required • No Latch Up symbol (each amplifier) • Wide Common-Mode Voltage Range • Low Power Consumption IN+ + OUT • IN− − Designed to be Interchangeable with Raytheon RC4559 AVAILABLE OPTIONS SYMBOLIZATION OPERATING DEVICE PACKAGE TEMPERATURE VIO max at 25°C SUFFIX RANGE RC4559 D, P −0°C to 70°C 6 mV The D packages are available taped and reeled. Add the suffix R to the device type when ordering. (i.e.,RC4559DR) description The RC4559 is a dual high-performance operational amplifier. The high common-mode input voltage and the absence of latch-up make this amplifier ideal for low-noise signal applications such as audio preamplifiers and signal conditioners. This amplifier features a guaranteed dynamic performance and output drive capability that far exceeds that of the general-purpose type amplifiers. The RC4559 is characterized for operation from 0°C to 70°C. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V CC+ Supply voltage V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 V CC− Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V Input voltage (any input, see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V Duration of output short-circuit to ground, one amplifier at a time (see Note 4) . . . . . . . . . . . . . . . . . unlimited Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 125°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C NOTES:1. All voltage values, unless otherwise noted, are with respect to the zero reference level (ground) of the supply voltages where the zero reference level is the midpoint between VCC+ and VCC−. 2. Differential voltages are at the noninverting input terminal with respect to the inverting input terminal. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts, whichever is less. 4. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. Copyright  1991, Texas Instruments Incorporated • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5) (cid:6)(cid:7)(cid:8)(cid:9) (cid:10)(cid:11)(cid:12)(cid:10)(cid:13)(cid:14)(cid:15)(cid:1)(cid:16)(cid:17)(cid:1)(cid:18)(cid:8)(cid:19)(cid:2)(cid:15) (cid:17)(cid:14)(cid:15)(cid:1)(cid:8)(cid:20)(cid:11)(cid:17)(cid:19)(cid:8)(cid:9) (cid:8)(cid:18)(cid:14)(cid:9)(cid:11)(cid:16)(cid:11)(cid:15)(cid:1) electrical characteristics at specified free-air temperature, V = 15 V, V = −15 V CC+ CC− PARAMETER TEST CONDITIONS† TA‡ MIN TYP MAX UNIT 25°C 2 6 VIO Input offset voltage VO = 0 mV Full Range 7.5 25°C 5 100 IIO Input offset current VO = 0 nA Full range 200 25°C 40 250 IIBI nput bias current VO = 0 nA Full range 500 VI Input voltage range 25°C ±12 ±13 V RL ≥3 kΩ 25°C ±12 ±13 VOM Maximum peak output voltlage swing RL = 600 Ω 25°C ±9.5 ±10 V RL ≥2 kΩ Full range ±10 VO = ±10 V, 25°C 20 300 VI Input voltage range RL = 2 kΩ Full range 15 V/mV BOM Maximum output-swing bandwidth RVOL P=P 2 =k Ω20 V, 25°C 24 32 kHz B1 Unity-gain bandwidth 25°C 3 4 MHz ri Input resistance 25°C 0.3 1 MΩ CMRR Common-mode rejection ratio VO = 0 25°C 80 100 dB kSVS Supply voltage sensitivity (∆VIO/∆VCC) VO = 0 25°C 10 75 µV/V AVD = 100, Vn Equivalent input noise voltage (closed loop) RS = 1 kΩ, 25°C 1.4 2 µV f = 20 Hz to 20 kHz In Equivalent input noise current f = 20 Hz to 20 kHz 25°C 25 pA 25°C 3.3 5.6 ICC Supply current (both amplifiers) No load, No signal 0°C 4 6.6 mA 70°C 3 5 AVD = 100, Vo1/Vo2 Crosstalk attentuation RS = 1 kΩ, 25°C 90 dB f = 10 kHz †All characteristics are specified under open-loop operation, unless otherwise noted. ‡Full range operating free-air temperature range is 0°C to 70°C. matching characteristics at V = 15 V, V = −15 V, T = 25°C CC+ CC− A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage VO = 0 ±0.2 mV IIO Input offset current VO = 0 ±7.5 nA IIB Input bias current VO = 0 ±15 nA AVD Large-signal differential voltage amplification VO = ±10 V, RL = 2 kΩ ±1 dB operating characteristics, V = 15 V, V = −15 V, T = 25°C CC+ CC− A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Rise time VI = 20 mV, RL = 2 kΩ, CL = 100 pF 80 µs Overshoot 18% SR Slew rate at unity gain VI = 10 mV, RL = 2 kΩ, CL = 100 pF 1.5 2 V/µs • 2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) RC4559D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 RC4559 & no Sb/Br) RC4559DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 RC4559 & no Sb/Br) RC4559P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 RC4559P & no Sb/Br) RC4559PE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 RC4559P & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) RC4559DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) RC4559DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

None

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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