R32C/111 Group Datasheet Datasheet R32C/111 Group R01DS0062EJ0130 RENESAS MCU Rev.1.30 Mar 3, 2014 1. Overview 1.1 Features The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral functions, provides support for a vast range of application fields. The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture, multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on- chip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I2C-bus interface, and watchdog timer enables to minimize external components. The R32C/111 Group is the standard MCU within the R32C/100 Series. This product, provided as 100-pin plastic molded LGA, and 100-/64-pin plastic molded LQFP packages, has a maximum of nine channels of serial interface. 1.1.1 Applications Audio, cameras, television, home appliance, printer, meter, office/industrial equipment, communication/ portable devices R01DS0062EJ0130 Rev.1.30 Page 1 of 93 Mar 3, 2014

R32C/111 Group 1. Overview 1.1.2 Performance Overview Tables 1.1 to 1.4 show the performance overview of the R32C/111 Group. Table 1.1 Performance Overview for the 100-pin Package (1/2) Unit Function Explanation CPU Central R32C/100 Series CPU Core processing unit •Basic instructions: 108 •Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz) •Multiplier: 32-bit × 32-bit  64-bit •Multiply-accumulate unit: 32-bit × 32-bit + 64-bit  64-bit •IEEE-754 compatible FPU: Single precision •32-bit barrel shifter •Operating mode: Single-chip mode, memory expansion mode, microprocessor mode (optional (1)) Memory Flash memory: 256 to 512 Kbytes RAM: 32 to 63 Kbytes Data flash: 4 Kbytes × 2 blocks Refer to Table 1.5 for memory size of each product group Voltage Low voltage Optional (1) Detector detector Low voltage detection interrupt Clock Clock generator •4 circuits (main clock, sub clock, PLL, on-chip oscillator) •Oscillation stop detector: Main clock oscillator stop/restart detection •Frequency divide circuit: Divide-by-2 to divide-by-24 selectable •Low power modes: Wait mode, stop mode External Bus Bus and memory •Address space: 4 Gbytes (of which up to 64 Mbytes is user Expansion expansion accessible) •External bus Interface: Support for wait-state insertion, 4 chip select outputs, 3V/5V interface •Bus format: Separate bus/Multiplexed bus selectable, data bus width selectable (8/16 bits) Interrupts Interrupt vectors: 261 External interrupt inputs: NMI, INT × 6, key input × 4 Interrupt priority levels: 7 Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output) DMA DMAC 4 channels •Cycle-steal transfer mode •Request sources: 51 •2 transfer modes: Single transfer, repeat transfer DMAC II •Triggered by an interrupt request of any peripheral •3 characteristic transfer functions: Immediate data transfer, calculation result transfer, chain transfer I/O Ports Programmable •2 input-only ports I/O ports •82 CMOS I/O ports •2 N-channel open drain ports •A pull-up resistor is selectable for every 4 input ports Note: 1. Contact a Renesas Electronics sales office to use the optional features. R01DS0062EJ0130 Rev.1.30 Page 2 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.2 Performance Overview for the 100-pin Package (2/2) Unit Function Explanation Timer Timer A 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Two-phase pulse signal processing in event counter mode (two- phase encoder input) × 3 Timer B 16-bit timer × 6 Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Three-phase Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used) motor control 8-bit programmable dead time timer timer Serial UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels Interface •I2C-bus (UART0 to UART6) •Special mode 2 (UART0 to UART6) •IEBus (optional (1)) (UART0 to UART6) A/D Converter 10-bit resolution × 26 channels Sample and hold functionality integrated D/A Converter 8-bit resolution × 2 CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1) X-Y Converter 16 bits × 16 bits Intelligent I/O Time measurement (input capture): 16 bits × 16 Waveform generation (output compare): 16 bits × 19 Serial interface: Variable-length synchronous serial I/O mode, IEBus mode (optional (1)) Flash Memory Programming and erasure supply voltage: VCC1 = VCC2 = 3.0 to 5.5 V Minimum endurance: 1,000 program/erase cycles Security protection: ROM code protect, ID code protect Debugging: On-chip debug, on-board flash programming Operating Frequency/Supply 50 MHz/VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1 Voltage Operating Temperature -20°C to 85°C (N version) -40°C to 85°C (D version) Current Consumption 32 mA (VCC1 = VCC2 = 5.0 V, f(CPU) = 50 MHz) 8 µA (VCC1 = VCC2 = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode) Package 100-pin plastic molded LQFP (PLQP0100KB-A) 100-pin plastic molded TFLGA (PTLG0100KA-A) Note: 1. Contact a Renesas Electronics sales office to use the optional features. R01DS0062EJ0130 Rev.1.30 Page 3 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.3 Performance Overview for the 64-pin Package (1/2) Unit Function Explanation CPU Central R32C/100 Series CPU Core processing unit •Basic instructions: 108 •Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz) •Multiplier: 32-bit × 32-bit  64-bit •Multiply-accumulate unit: 32-bit × 32-bit + 64-bit  64-bit •IEEE-754 compatible FPU: Single precision •32-bit barrel shifter •Operating mode: Single-chip mode Memory Flash memory: 128/256 Kbytes RAM: 32 Kbytes Data flash: 4 Kbytes × 2 blocks Refer to Table 1.5 for memory size of each product group Voltage Low voltage Optional (1) Detector detector Low voltage detection interrupt Clock Clock generator •4 circuits (main clock, sub clock, PLL, on-chip oscillator) •Oscillation stop detector: Main clock oscillator stop/restart detection •Frequency divide circuit: Divide-by-2 to divide-by-24 selectable •Low power modes: Wait mode, stop mode Interrupts Interrupt vectors: 261 External interrupt inputs: NMI, INT × 6, key input × 4 Interrupt priority levels: 7 Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output) DMA DMAC 4 channels •Cycle-steal transfer mode •Request sources: 45 •2 transfer modes: Single transfer, repeat transfer DMAC II •Triggered by an interrupt request of any peripheral •3 characteristic transfer functions: Immediate data transfer, calculation result transfer, chain transfer I/O Ports Programmable •1 input-only port I/O ports •49 CMOS I/O ports •2 N-channel open drain ports •A pull-up resistor is selectable for every 4 input ports Note: 1. Contact a Renesas Electronics sales office to use the optional features. R01DS0062EJ0130 Rev.1.30 Page 4 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.4 Performance Overview for the 64-pin Package (2/2) Unit Function Explanation Timer Timer A 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Two-phase pulse signal processing in event counter mode (two- phase encoder input) × 3 Timer B 16-bit timer × 6 (1) Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Three-phase Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used) motor control 8-bit programmable dead time timer timer Serial UART0 to Asynchronous/synchronous serial interface × 6 channels Interface UART3, UART5, •I2C-bus (UART0 to UART3, UART5) UART8 •Special mode 2 (UART0 to UART3, UART5) •IEBus (optional (2)) (UART0 to UART3, UART5) A/D Converter 10-bit resolution × 20 channels Sample and hold functionality integrated D/A Converter 8-bit resolution × 1 CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1) X-Y Converter 16 bits × 16 bits Intelligent I/O Time measurement (input capture): 16 bits × 16 Waveform generation (output compare): 16 bits × 19 Serial interface: Variable-length synchronous serial I/O mode, IEBus mode (optional (2)) Flash Memory Programming and erasure supply voltage: VCC1 = 3.0 to 5.5 V Minimum endurance: 1,000 program/erase cycles Security protection: ROM code protect, ID code protect Debugging: On-chip debug, on-board flash programming Operating Frequency/Supply 50 MHz/VCC1 = 3.0 to 5.5 V Voltage Operating Temperature -40°C to 85°C (D version) Current Consumption 32 mA (VCC1 = 5.0 V, f(CPU) = 50 MHz) 8 µA (VCC1 = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode) Package 64-pin plastic molded LQFP (PLQP0064KB-A) Notes: 1. Timer B4 is available in timer mode only. 2. Contact a Renesas Electronics sales office to use the optional features. R01DS0062EJ0130 Rev.1.30 Page 5 of 93 Mar 3, 2014

R32C/111 Group 1. Overview 1.2 Product Information Table 1.5 lists the product information and Figure 1.1 shows the details of the part number. Table 1.5 R32C/111 Group Product List As of March, 2014 Part Number Package Code (1) ROM Capacity (2) RAM Capacity Remarks R5F64110DFB 256 Kbytes +8 Kbytes R5F64111DFB 384 Kbytes 63 Kbytes +8 Kbytes R5F64112DFB 512 Kbytes +8 Kbytes PLQP0100KB-A -40°C to 85°C (D version) R5F64114DFB 256 Kbytes +8 Kbytes R5F64115DFB 384 Kbytes 40 Kbytes +8 Kbytes R5F64116DFB 512 Kbytes +8 Kbytes R5F64111NLG 384 Kbytes +8 Kbytes 63 Kbytes R5F64112NLG 512 Kbytes PTLG0100KA-A -20°C to 85°C (N version) +8 Kbytes R5F6411FNLG 256 Kbytes 32 Kbytes +8 Kbytes R5F6411EDFN 128 Kbytes +8 Kbytes PLQP064KB-A 32 Kbytes -40°C to 85°C (D version) R5F6411FDFN 256 Kbytes +8 Kbytes Notes: 1. The old package codes are as follows: PLQP0100KB-A: 100P6Q-A PTLG0100KA-A: 100F0M PLQP0064KB-A: 64P6Q-A 2. “+ 8 Kbytes” in the ROM capacity column indicates the data flash capacity. R01DS0062EJ0130 Rev.1.30 Page 6 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Part Number R5 F 64 11 6 N XXX FB Package Code FB:PLQP0100KB-A FN:PLQP0064KB-A LG:PTLG0100KA-A ROM Number Omitted in the flash memory version Temperature Code N:-20°C to 85°C D:-40°C to 85°C ROM/RAM Capacity 0 : 256 KB/63 KB 1 : 384 KB/63 KB 2 : 512 KB/63 KB 4 : 256 KB/40 KB 5:384 KB/40 KB 6:512 KB/40 KB E : 128 KB/32 KB F : 256 KB/32 KB R32C/111 Group R32C/100 Series Memory Type F:Flash memory version Figure 1.1 Part Numbering R01DS0062EJ0130 Rev.1.30 Page 7 of 93 Mar 3, 2014

R32C/111 Group 1. Overview 1.3 Block Diagram Figures 1.2 and 1.3 show block diagram of the R32C/111 Group. 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 VCC2 VCC1 P o rt P Peripherals 7 8 Timer: A/D converter: Clock generator: Timer A 16 bits × 5 timers 10 bits × 1 circuit 4 circuits Po Timer B 16 bits × 6 timers Standard: 10 inputs -XIN-XOUT rt P Maximum: 26 inputs -XCIN-XCOUT 8 7 Three-phase motor -On-chip oscillator controller -PLL frequency synthesizer D/A converter: Serial interface: 8 bits × 2 channels P8 DMAC _ 9 channels V 5 Watchdog timer: CC X-Y converter: 15 bits DMAC II 1 16 bits × 16 bits P R32C/100 Series CPU Core Memory 9_ CRC calculator (CCITT) 1 X16 + X12 + X5 + 1 RRR23RR2R010 FLG ROM RR6R3R41 INTB TWimavee m gIneetaneselurliargetiemonnet:n 1It/:9O 16 RAAARR7R012AA67RR50145 USIPSSVCPPF MuRltAipMlier Port P9 5 Serial interface: A3A2 SVP -Variable-length FBA3 VCT synchronous serial I/O SBSFBB Floating-point unit Po -IEBus rt P 10 8 Figure 1.2 R32C/111 Group Block Diagram for the 100-pin Package R01DS0062EJ0130 Rev.1.30 Page 8 of 93 Mar 3, 2014

R32C/111 Group 1. Overview 4 3 8 4 8 8 Port P0 Port P1 Port P2 Port P3 Port P6 Port P7 Peripherals P Timer A T16im beitsr: × 5 timers 1A0/ Dbi tcso ×n 1v ecrirtceuri:t 4 cirCcluoitcsk generator: ort P8 7 Timer B 16 bits × 6 timers Standard: 8 inputs -XIN-XOUT Three-phase motor Maximum: 20 inputs -XCIN-XCOUT controller -On-chip oscillator -PLL frequency synthesizer D/A converter: P X-Y converter: 8 bits × 1 channel 8_ 16 bits × 16 bits DMAC 5 Watchdog timer: Serial interface: 15 bits DMAC II 6 channels R32C/100 Series CPU Core Memory P CRCX c16a +lc Xu1la2 +to Xr 5( C+ C1ITT) RRR23RR2R010 FLG ROM 9_3 RR6R3R41 INTB Intelligent I/O RARR7R067RR545 UISSPP RAM Time measurement: 16 A1A0 PC WS-sVeayranviarecilah gibnreolteenn-reolfearuancstge isot:hen r:i a1l9 I/O SFAABBS23FAAABB123 SVSVCVPFT Floating-Mpouilntitp ulienrit Port P10 8 -IEBus Figure 1.3 R32C/111 Group Block Diagram for the 64-pin Package R01DS0062EJ0130 Rev.1.30 Page 9 of 93 Mar 3, 2014

R32C/111 Group 1. Overview 1.4 Pin Assignments Figures 1.4 to 1.6 show the pin assignments (top view) and Tables 1.6 to 1.10 show the pin characteristics. (Note 1) P1_3 / D11 / IIO0_3 / IIO1_3P1_4 / D12 / IIO0_4 / IIO1_4P1_5 / D13 / INT3 / IIO0_5 / IIO1_5P1_6 / D14 / INT4 / IIO0_6 / IIO1_6P1_7 / D15 / INT5 / IIO0_7 / IIO1_7P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0P2_1 / A1 / [A1/D1] / AN2_1P2_2 / A2 / [A2/D2] / AN2_2P2_3 / A3 / [A3/D3] / AN2_3P2_4 / A4 / [A4/D4] / AN2_4P2_5 / A5 / [A5/D5] / AN2_5P2_6 / A6 / [A6/D6] / AN2_6P2_7 / A7 / [A7/D7] / AN2_7VSSP3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1AVCC2P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1BP3_2 / A10 / [A10/D10] / TA1OUT / VP3_3 / A11 / [A11/D11] / TA1IN / VP3_4 / A12 / [A12/D12] / TA2OUT / WP3_5 / A13 / [A13/D13] / TA2IN / WP3_6 / A14 / [A14/D14] / TA4OUT / UP3_7 / A15 / [A15/D15] / TA4IN / UP4_0 / A16 / CTS3 / RTS3 / SS3P4_1 / A17 / CLK3 75747372717069686766656463626160595857565554535251 IIO0_2 / IIO1_2 / D10 / P1_2 76 50 P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN IIO0_1 / IIO1_1 / D9 / P1_1 77 VCC2 49 P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT IIO0_0 / IIO1_0 / D8 / P1_0 78 48 P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6 AN0_7 / D7 / P0_7 79 47 P4_5 / CS2 / A21 / CLK6 AN0_6 / D6 / P0_6 80 46 P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6 AN0_5 / D5 / P0_5 81 45 P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6 AN0_4 / D4 / P0_4 82 44 P5_0 / WR0 / WR AN0_3 / D3 / P0_3 83 43 P5_1 / WR1 / BC1 AN0_2 / D2 / P0_2 84 R32C/111 GROUP 42 P5_2 / RD AN0_1 / D1 / P0_1 85 41 P5_3 / CLKOUT / BCLK AN0_0 / D0 / P0_0 86 40 P5_4 / HLDA / CS1 / TXD7 KI3 / AN_7 / P10_7 87 39 P5_5 / HOLD / CLK7 KI2 / AN_6 / P10_6 88 PLQP0100KB-A 38 P5_6 / ALE / CS2 / RXD7 KI1 / AN_5 / P10_5 89 37 P5_7 / RDY / CS3 / CTS7 / RTS7 KI0 / AN_4 / P10_4 90 (100P6Q-A) 36 P6_0 / TB0IN / CTS0 / RTS0 / SS0 AN_3 / P10_3 91 35 P6_1 / TB1IN / CLK0 AN_2 / P10_2 92 (Top view) 34 P6_2 / TB2IN / RXD0 / SCL0 / STXD0 AN_1 / P10_1 93 33 P6_3 / TXD0 / SDA0 / SRXD0 AVSS 94 32 P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 AN_0 / P10_0 95 31 P6_5 / CLK1 VREF 96 30 P6_6 / RXD1 / SCL1 / STXD1 AVCC 97 29 P6_7 / TXD1 / SDA1 / SRXD1 RXD4 / SCL4 / STXD4 / ADTRG / P9_7 98 VCC1 28 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT (Note 2) TXD4 / SDA4 / SRXD4 / ANEX1 / P9_6 99 27 P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN CLK4 / ANEX0 / P9_5 100 26 P7_2 / TA1OUT / V / CLK2 (Note 2) (Note 3) 12345678910111213141516171819202122232425 CTS4 / RTS4 / SS4 / TB4IN / DA1 / P9_4TB3IN / DA0 / P9_3VDC0P9_1VDC1NSDCNVSSXCIN / P8_7XCOUT / P8_6RESETXOUTVSSXINVCC1NMI / P8_5INT2 / P8_4INT1 / P8_3INT0 / P8_2IIO1_5 / UD0B / UD1B / CTS5 / RTS5 / SS5 / U / TA4IN / P8_1UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0IIO1_4 / UD0B / UD1B / CLK5 / TA3IN / P7_7UD1A / TXD5 / SDA5 / SRXD5 / CTS8 / RTS8 / TA3OUT / P7_6IIO1_2 / RXD8 / W / TA2IN / P7_5IIO1_1 / CLK8 / W / TA2OUT / P7_4IIO1_0 / CTS2 / RTS2 / SS2 / TXD8 / V / TA1IN / P7_3 D0A / U O1_3 / II Notes: 1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins. 2. Pins P7_0 and P7_1 are open drain outputs. 3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”. Figure 1.4 Pin Assignment for the 100-pin Package (top view) R01DS0062EJ0130 Rev.1.30 Page 10 of 93 Mar 3, 2014

R32C/111 Group 1. Overview R32C/111 GROUP PTLG0100KA-A (100F0M) (Top view) VCC1 VCC2 10 9 8 7 6 5 4 3 2 1 K P4_2 P4_3 P5_0 P5_1 P5_4 P6_0 P6_3 P6_6 P7_1 P7_2 K (Note 1) J P4_1 P4_0 P4_6 P5_2 P5_5 P6_1 P6_4 P7_0 P7_3 P7_4 J (Note 1) H P3_6 P3_7 P4_5 P5_3 P5_6 P6_2 P6_7 P7_5 P7_7 P8_0 H G P3_2 P3_3 P4_4 P4_7 P5_7 P6_5 P7_6 P8_3 / P8_5 / P8_2 / G INT1 NMI INT0 F P3_0 VCC2 P3_1 P3_4 P3_5 P8_4 / P8_1 VSS XIN VCC1 F INT2 E P2_6 P2_7 VSS P2_5 P1_6 / P0_0 P9_3 P8_6 / RESET XOUT E INT4 XCOUT D P2_2 P2_1 P2_3 P2_4 P0_5 P10_7 P10_0 P9_1 CNVSS P8_7 / D XCIN C P2_0 P1_7 / P1_1 P1_0 P0_1 P10_3 AVSS P9_7 VDC1 NSD C INT5 B P1_4 P1_5 / P0_6 P0_4 P0_2 P10_5 P10_2 AVCC P9_6 VDC0 B INT3 A P1_3 P1_2 P0_7 P0_3 P10_6 P10_4 P10_1 VREF P9_5 P9_4 A (Note 2) 10 9 8 7 6 5 4 3 2 1 VCC1 VCC2 Notes: 1. Pins P7_0 and P7_1 are open drain outputs. 2. The pin position A1 varies by product. Refer to the index mark in attached “Package Dimensions”. Figure 1.5 Pin Assignment for the 100-pin LGA Package (top view) R01DS0062EJ0130 Rev.1.30 Page 11 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.6 Pin Characteristics for the 100-pin Package (1/3) Pin No. Control Interrupt Analog Bus Control Port Timer Pin UART Pin Intelligent I/O Pin QFP LGA Pin Pin Pin Pin 1 A1 P9_4 TB4IN CTS4/RTS4/SS4 DA1 2 E4 P9_3 TB3IN DA0 3 B1 VDC0 4 D3 P9_1 5 C2 VDC1 6 C1 NSD 7 D2 CNVSS 8 D1 XCIN P8_7 9 E3 XCOUT P8_6 10 E2 RESET 11 E1 XOUT 12 F3 VSS 13 F2 XIN 14 F1 VCC1 15 G2 P8_5 NMI 16 F5 P8_4 INT2 17 G3 P8_3 INT1 18 G1 P8_2 INT0 19 F4 P8_1 TA4IN/U CTS5/RTS5/SS5 IIO1_5/UD0B/UD1B 20 H1 P8_0 TA4OUT/U RXD5/SCL5/STXD5 UD0A/UD1A 21 H2 P7_7 TA3IN CLK5 IIO1_4/UD0B/UD1B 22 G4 P7_6 TA3OUT TXD5/SDA5/ IIO1_3/UD0A/UD1A SRXD5/CTS8/RTS8 23 H3 P7_5 TA2IN/W RXD8 IIO1_2 24 J1 P7_4 TA2OUT/W CLK8 IIO1_1 25 J2 P7_3 TA1IN/V CTS2/RTS2/SS2/ IIO1_0 TXD8 26 K1 P7_2 TA1OUT/V CLK2 27 K2 P7_1 TA0IN/ RXD2/SCL2/STXD2 IIO1_7/OUTC2_2/ TB5IN ISRXD2/IEIN 28 J3 P7_0 TA0OUT TXD2/SDA2/SRXD2 IIO1_6/OUTC2_0/ ISTXD2/IEOUT 29 H4 P6_7 TXD1/SDA1/SRXD1 30 K3 P6_6 RXD1/SCL1/STXD1 31 G5 P6_5 CLK1 32 J4 P6_4 CTS1/RTS1/SS1 OUTC2_1/ISCLK2 33 K4 P6_3 TXD0/SDA0/SRXD0 34 H5 P6_2 TB2IN RXD0/SCL0/STXD0 35 J5 P6_1 TB1IN CLK0 36 K5 P6_0 TB0IN CTS0/RTS0/SS0 37 G6 P5_7 CTS7/RTS7 RDY/CS3 38 H6 P5_6 RXD7 ALE/CS2 39 J6 P5_5 CLK7 HOLD R01DS0062EJ0130 Rev.1.30 Page 12 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.7 Pin Characteristics for the 100-pin Package (2/3) Pin No. Control Interrupt Analog Bus Control Port Timer Pin UART Pin Intelligent I/O Pin QFP LGA Pin Pin Pin Pin 40 K6 P5_4 TXD7 HLDA/CS1 41 H7 P5_3 CLKOUT/ BCLK 42 J7 P5_2 RD 43 K7 P5_1 WR1/BC1 44 K8 P5_0 WR0/WR 45 G7 P4_7 TXD6/SDA6/SRXD6 CS0/A23 46 J8 P4_6 RXD6/SCL6/STXD6 CS1/A22 47 H8 P4_5 CLK6 CS2/A21 48 G8 P4_4 CTS6/RTS6/SS6 CS3/A20 49 K9 P4_3 TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/ A19 IEOUT 50 K10 P4_2 RXD3/SCL3/STXD3 ISRXD2/IEIN A18 51 J10 P4_1 CLK3 A17 52 J9 P4_0 CTS3/RTS3/SS3 A16 53 H9 P3_7 TA4IN/U A15(/D15) 54 H10 P3_6 TA4OUT/U A14(/D14) 55 F6 P3_5 TA2IN/W A13(/D13) 56 F7 P3_4 TA2OUT/W A12(/D12) 57 G9 P3_3 TA1IN/V A11(/D11) 58 G10 P3_2 TA1OUT/V A10(/D10) 59 F8 P3_1 TA3OUT UD0B/UD1B A9(/D9) 60 F9 VCC2 61 F10 P3_0 TA0OUT UD0A/UD1A A8(/D8) 62 E8 VSS 63 E9 P2_7 AN2_7 A7(/D7) 64 E10 P2_6 AN2_6 A6(/D6) 65 E7 P2_5 AN2_5 A5(/D5) 66 D7 P2_4 AN2_4 A4(/D4) 67 D8 P2_3 AN2_3 A3(/D3) 68 D10 P2_2 AN2_2 A2(/D2) 69 D9 P2_1 AN2_1 A1(/D1) 70 C10 P2_0 AN2_0 A0(/D0)/ BC0(/D0) 71 C9 P1_7 INT5 IIO0_7/IIO1_7 D15 72 E6 P1_6 INT4 IIO0_6/IIO1_6 D14 73 B9 P1_5 INT3 IIO0_5/IIO1_5 D13 74 B10 P1_4 IIO0_4/IIO1_4 D12 75 A10 P1_3 IIO0_3/IIO1_3 D11 76 A9 P1_2 IIO0_2/IIO1_2 D10 77 C8 P1_1 IIO0_1/IIO1_1 D9 78 C7 P1_0 IIO0_0/IIO1_0 D8 79 A8 P0_7 AN0_7 D7 R01DS0062EJ0130 Rev.1.30 Page 13 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.8 Pin Characteristics for the 100-pin Package (3/3) Pin No. Control Interrupt Analog Bus Control Port Timer Pin UART Pin Intelligent I/O Pin QFP LGA Pin Pin Pin Pin 80 B8 P0_6 AN0_6 D6 81 D6 P0_5 AN0_5 D5 82 B7 P0_4 AN0_4 D4 83 A7 P0_3 AN0_3 D3 84 B6 P0_2 AN0_2 D2 85 C6 P0_1 AN0_1 D1 86 E5 P0_0 AN0_0 D0 87 D5 P10_7 KI3 AN_7 88 A6 P10_6 KI2 AN_6 89 B5 P10_5 KI1 AN_5 90 A5 P10_4 KI0 AN_4 91 C5 P10_3 AN_3 92 B4 P10_2 AN_2 93 A4 P10_1 AN_1 94 C4 AVSS 95 D4 P10_0 AN_0 96 A3 VREF 97 B3 AVCC 98 C3 P9_7 RXD4/SCL4/STXD4 ADTRG 99 B2 P9_6 TXD4/SDA4/SRXD4 ANEX1 100 A2 P9_5 CLK4 ANEX0 R01DS0062EJ0130 Rev.1.30 Page 14 of 93 Mar 3, 2014

R32C/111 Group 1. Overview 1_5 D0 O 0 X P0_3 / AN0_3P1_5 / ADTRG / INT3 / IIO0_5 / IIP1_6 / INT4 / IIO0_6 / IIO1_6P1_7 / INT5 / IIO0_7 / IIO1_7P2_0 / AN2_0 / IIO0_0P2_1 / AN2_1 / IIO0_1P2_2 / AN2_2 / IIO0_2P2_3 / AN2_3 / IIO0_3P2_4 / AN2_4 / IIO0_4P2_5 / AN2_5 / IIO0_5P2_6 / AN2_6 / IIO0_6P2_7 / AN2_7 / IIO0_7P6_0 / TB0IN / CTS0 / RTS0 / SSP6_1 / TB1IN / CLK0P6_2 / TB2IN / RXD0 / SCL0 / STP6_3 / TXD0 / SDA0 / SRXD0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AN0_2 / P0_2 49 32 P3_0 / TA0OUT / CLK3 / UD0A / UD1A AN0_1 / P0_1 50 31 P3_1 / TA3OUT / RXD3 / SCL3 / STXD3 / UD0B / UD1B AN0_0 / P0_0 51 30 P3_2 / TA1OUT / V / TXD3 / SDA3 / SRXD3 KI3 / AN_7 / P10_7 52 29 P3_3 / TA1IN / V / CTS3 / RTS3 / SS3 KI2 / AN_6 / P10_6 53 28 P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 R32C/111 GROUP KI1 / AN_5 / P10_5 54 27 P6_5 / CLK1 KI0 / AN_4 / P10_4 55 26 P6_6 / RXD1 / SCL1 / STXD1 AN_3 / P10_3 56 25 P6_7 / TXD1 / SDA1 / SRXD1 AN_2 / P10_2 57 PLQP0064KB-A 24 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT (Note 1) AN_1 / P10_1 58 23 P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN AVSS 59 (64P6Q-A) 22 P7_2 / TA1OUT / V / CLK2 (Note 1) AN_0 / P10_0 60 (Top view) 21 P7_3 / TA1IN / V / CTS2 / RTS2 / SS2 / TXD8 / IIO1_0 VREF 61 20 P7_4 / TA2OUT / W / CLK8 / IIO1_1 AVCC 62 19 P7_5 / TA2IN / W / RXD8 / IIO1_2 TB3IN / DA0 / P9_3 63 18 P7_6 / TA3OUT / TXD5 / SDA5 / SRXD5 / CTS8 / RTS8 / IIO1_3 / UD0A / UD1A VDC0 64 17 P7_7 / TA3IN / CLK5 / IIO1_4 / UD0B / UD1B (Note 2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDC1NSDCNVSSXCIN / P8_7XCOUT / P8_6RESETXOUTVSSXINVCC1NMI / P8_5INT2 / P8_4INT1 / P8_3INT0 / P8_21_5 / UD0B / UD1B / CTS5 / RTS5 / SS5 / U / TA4IN / P8_1UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0 O II Notes: 1. Pins P7_0 and P7_1 are open drain outputs. 2. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”. Figure 1.6 Pin Assignment for the 64-pin Package (top view) R01DS0062EJ0130 Rev.1.30 Page 15 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.9 Pin Characteristics for the 64-pin Package (1/2) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Intelligent I/O Pin Analog Pin 1 VDC1 2 NSD 3 CNVSS 4 XCIN P8_7 5 XCOUT P8_6 6 RESET 7 XOUT 8 VSS 9 XIN 10 VCC1 11 P8_5 NMI 12 P8_4 INT2 13 P8_3 INT1 14 P8_2 INT0 15 P8_1 TA4IN/U CTS5/RTS5/SS5 IIO1_5/UD0B/UD1B 16 P8_0 TA4OUT/U RXD5/SCL5/STXD5 UD0A/UD1A 17 P7_7 TA3IN CLK5 IIO1_4/UD0B/UD1B 18 P7_6 TA3OUT TXD5/SDA5/SRXD5/ IIO1_3/UD0A/UD1A CTS8/RTS8 19 P7_5 TA2IN/W RXD8 IIO1_2 20 P7_4 TA2OUT/W CLK8 IIO1_1 21 P7_3 TA1IN/V CTS2/RTS2/SS2/TXD8 IIO1_0 22 P7_2 TA1OUT/V CLK2 23 P7_1 TA0IN/ RXD2/SCL2/STXD2 IIO1_7/OUTC2_2/ TB5IN ISRXD2/IEIN 24 P7_0 TA0OUT TXD2/SDA2/SRXD2 IIO1_6/OUTC2_0/ ISTXD2/IEOUT 25 P6_7 TXD1/SDA1/SRXD1 26 P6_6 RXD1/SCL1/STXD1 27 P6_5 CLK1 28 P6_4 CTS1/RTS1/SS1 OUTC2_1/ISCLK2 29 P3_3 TA1IN/V CTS3/RTS3/SS3 30 P3_2 TA1OUT/V TXD3/SDA3/SRXD3 31 P3_1 TA3OUT RXD3/SCL3/STXD3 UD0B/UD1B 32 P3_0 TA0OUT CLK3 UD0A/UD1A 33 P6_3 TXD0/SDA0/SRXD0 34 P6_2 TB2IN RXD0/SCL0/STXD0 35 P6_1 TB1IN CLK0 36 P6_0 TB0IN CTS0/RTS0/SS0 37 P2_7 IIO0_7 AN2_7 38 P2_6 IIO0_6 AN2_6 39 P2_5 IIO0_5 AN2_5 40 P2_4 IIO0_4 AN2_4 R01DS0062EJ0130 Rev.1.30 Page 16 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.10 Pin Characteristics for the 64-pin Package (2/2) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Intelligent I/O Pin Analog Pin 41 P2_3 IIO0_3 AN2_3 42 P2_2 IIO0_2 AN2_2 43 P2_1 IIO0_1 AN2_1 44 P2_0 IIO0_0 AN2_0 45 P1_7 INT5 IIO0_7/IIO1_7 46 P1_6 INT4 IIO0_6/IIO1_6 47 P1_5 INT3 IIO0_5/IIO1_5 ADTRG 48 P0_3 AN0_3 49 P0_2 AN0_2 50 P0_1 AN0_1 51 P0_0 AN0_0 52 P10_7 KI3 AN_7 53 P10_6 KI2 AN_6 54 P10_5 KI1 AN_5 55 P10_4 KI0 AN_4 56 P10_3 AN_3 57 P10_2 AN_2 58 P10_1 AN_1 59 AVSS 60 P10_0 AN_0 61 VREF 62 AVCC 63 P9_3 TB3IN DA0 64 VDC0 R01DS0062EJ0130 Rev.1.30 Page 17 of 93 Mar 3, 2014

R32C/111 Group 1. Overview 1.5 Pin Definitions and Functions Tables 1.11 to 1.17 show the pin definitions and functions. Table 1.11 Pin Definitions and Functions for the 100-pin Package (1/4) Power Function Symbol I/O Description Supply Power supply VCC1, VCC2, Applicable as follows: VCC1 and VCC2 = 3.0 to I — VSS 5.5 V (VCC1  VCC2), VSS = 0 V Connecting pins VDC0, VDC1 A decoupling capacitor for internal voltage should for decoupling — — be connected between VDC0 and VDC1 capacitor Analog power AVCC, AVSS Power supply for the A/D converter. AVCC and supply I VCC1 AVSS should be connected to VCC1 and VSS, respectively Reset input RESET I VCC1 The MCU is reset when this pin is driven low CNVSS CNVSS I VCC1 This pin should be connected to VSS via a resistor Debug port NSD This pin is to communicate with a debugger. It I/O VCC1 should be connected to VCC1 via a resistor of 1 to 4.7 k Main clock input XIN Input/output for the main clock oscillator. A crystal, I VCC1 or a ceramic resonator should be connected Main clock output XOUT between pins XIN and XOUT. An external clock O VCC1 should be input at the XIN while leaving the XOUT open Sub clock input XCIN Input/output for the sub clock oscillator. A crystal I VCC1 oscillator should be connected between pins XCIN Sub clock output XCOUT and XCOUT. An external clock should be input at O VCC1 the XCIN while leaving the XCOUT open BCLK output BCLK O VCC2 BCLK output Clock output CLKOUT Output of the clock with the same frequency as O VCC2 low speed clocks, f8, or f32 External interrupt INT0 to INT5 VCC1 Input for external interrupts I input VCC2 NMI input P8_5/NMI I VCC1 Input for NMI Key input interrupt KI0 to KI3 I VCC1 Input for the key input interrupt Bus control pins D0 to D7 Input/output of data (D0 to D7) while accessing an I/O VCC2 external memory space with a separate bus D8 to D15 Input/output of data (D8 to D15) while accessing I/O VCC2 an external memory space with 16-bit separate bus A0 to A23 O VCC2 Output of address bits A0 to A23 R01DS0062EJ0130 Rev.1.30 Page 18 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.12 Pin Definitions and Functions for the 100-pin Package (2/4) Power Function Symbol I/O Description Supply Bus control pins A0/D0 to A7/D7 Output of address bits (A0 to A7) and input/output I/O VCC2 of data (D0 to D7) by time-division while accessing an external memory space with multiplexed bus A8/D8 to Output of address bits (A8 to A15) and input/ A15/D15 output of data (D8 to D15) by time-division while I/O VCC2 accessing an external memory space with 16-bit multiplexed bus BC0/D0 Output of byte control (BC0) and input/output of I/O VCC2 data (D0) by time-division while accessing an external memory space with multiplexed bus CS0 to CS3 O VCC2 Chip select output WR0/WR1/WR/ Output of write, byte control, and read signals. BC0/BC1/RD Either WRx or WR and BCx can be selected by a program. Data is read when RD is low. •When WR0, WR1, and RD are selected, data is written to the following address: an even address, when WR0 is low an odd address, when WR1 is low O VCC2 on 16-bit external data bus •When WR, BC0, BC1, and RD are selected, data is written, when WR is low and the following address is accessed: an even address, when BC0 is low an odd address, when BC1 is low on 16-bit external data bus ALE O VCC2 Latch enable signal in multiplexed bus format HOLD The MCU is in a hold state while this pin is held I VCC2 low HLDA This pin is driven low while the MCU is held in a O VCC2 hold state RDY Bus cycle is extended by the CPU if this pin is low I VCC2 on the falling edge of BCLK R01DS0062EJ0130 Rev.1.30 Page 19 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.13 Pin Definitions and Functions for the 100-pin Package (3/4) Power Function Symbol I/O Description Supply I/O port P0_0 to P0_7, I/O ports in CMOS. Each port can be programmed P1_0 to P1_7, to input or output under the control of the direction P2_0 to P2_7, register. I/O VCC2 P3_0 to P3_7, Pull-up resistors are selected for the following 4- P4_0 to P4_7, pin units: Pi_0 to Pi_3 and Pi_4 to Pi_7 (i = 0 to P5_0 to P5_7, 10); however, they are enabled only for the input pins. P6_0 to P6_7, P7_0 and P7_1 outputs are N-channel open drain P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, I/O VCC1 P9_3 to P9_7, P10_0 to P10_7 Input port P9_1 Input port in CMOS. Pull-up resistors are I VCC1 selectable for P9_1 and P9_3 Timer A TA0OUT to Timers A0 to A4 input/output. VCC1 TA4OUT I/O TA0OUT output assigned for port P7_0 is N- VCC2 channel open drain TA0IN to TA4IN VCC1 Timers A0 to A4 input I VCC2 Timer B TB0IN to Timers B0 to B5 input I VCC1 TB5IN Three-phase U,U,V,V,W,W Three-phase motor control timer output VCC1 motor control O VCC2 timer output Serial interface CTS0 to CTS8 VCC1 Handshake input I VCC2 RTS0 to RTS8 VCC1 Handshake output O VCC2 CLK0 to CLK8 VCC1 Transmit/receive clock input/output I/O VCC2 RXD0 to RXD8 VCC1 Serial data input I VCC2 TXD0 to TXD8 VCC1 Serial data output. O VCC2 TXD2 output is N-channel open drain I2C-bus SDA0 to SDA6 VCC1 Serial data input/output. I/O (simplified) VCC2 SDA2 output is N-channel open drain SCL0 to SCL6 VCC1 Transmit/receive clock input/output. I/O VCC2 SCL2 output is N-channel open drain R01DS0062EJ0130 Rev.1.30 Page 20 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.14 Pin Definitions and Functions for the 100-pin Package (4/4) Power Function Symbol I/O Description Supply Serial interface STXD0 to VCC1 Serial data output in slave mode. O special functions STXD6 VCC2 STXD2 is N-channel open drain SRXD0 to VCC1 Serial data input in slave mode I SRXD6 VCC2 SS0 to SS6 VCC1 Input to control serial interface special functions I VCC2 A/D converter AN_0 to AN_7 I VCC1 Analog input for the A/D converter AN0_0 to AN0_7, I VCC2 AN2_0 to AN2_7 ADTRG I VCC1 External trigger input for the A/D converter ANEX0 Expanded analog input for the A/D converter and I/O VCC1 output in external op-amp connection mode ANEX1 I VCC1 Expanded analog input for the A/D converter D/A converter DA0, DA1 O VCC1 Output for the D/A converter Reference voltage VREF Reference voltage input for the A/D converter and I  input D/A converter Intelligent I/O IIO0_0 to VCC1 Input/output for Intelligent I/O group 0. Either input I/O IIO0_7 VCC2 capture or output compare is selectable IIO1_0 to Input/output for Intelligent I/O group 1. Either input IIO1_7 VCC1 capture or output compare is selectable. IIO1_6 I/O VCC2 and IIO1_7 outputs assigned for ports P7_0 and P7_1 are N-channel open drain UD0A, UD0B, VCC1 Input for the two-phase encoder I UD1A, UD1B VCC2 OUTC2_0 to Output for OC (output compare) of Intelligent I/O OUTC2_2 VCC1 group 2. O VCC2 OUTC2_0 and OUTC2_2 assigned for ports P7_0 and P7_1 are N-channel open drain ISCLK2 I/O Clock input/output for the serial interface ISRXD2 I Receive data input for the serial interface VCC1 ISTXD2 Transmit data output for the serial interface. VCC2 O ISTXD2 assigned for port P7_0 is N-channel open drain IEIN I Receive data input for the serial interface IEOUT VCC1 Transmit data output for the serial interface. O VCC2 IEOUT assigned for port P7_0 is N-channel open drain R01DS0062EJ0130 Rev.1.30 Page 21 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.15 Pin Definitions and Functions for 64-pin Package (1/3) Function Symbol I/O Description Power supply VCC1, VSS I Applicable as follows: VCC1 = 3.0 to 5.5 V, VSS = 0 V Connecting pins VDC0, VDC1 A decoupling capacitor for internal voltage should be for decoupling — connected between VDC0 and VDC1 capacitor Analog power AVCC, AVSS Power supply for the A/D converter. AVCC and AVSS should I supply be connected to VCC and VSS, respectively Reset input RESET I The MCU is reset when this pin is driven low CNVSS CNVSS I This pin should be connected to VSS via a resistor Debug port NSD This pin is to communicate with a debugger. It should be I/O connected to VCC1 via a resistor of 1 to 4.7 k Main clock input XIN Input/output for the main clock oscillator. A crystal, or a I ceramic resonator should be connected between pins XIN Main clock output XOUT and XOUT. An external clock should be input at the XIN while O leaving the XOUT open Sub clock input XCIN Input/output for the sub clock oscillator. A crystal oscillator I should be connected between pins XCIN and XCOUT. An Sub clock output XCOUT external clock should be input at the XCIN while leaving the O XCOUT open External interrupt INT0 to INT5 Input for external interrupts I input NMI input P8_5/NMI I Input for NMI Key input interrupt KI0 to KI3 I Input for the key input interrupt I/O port P0_0 to P0_3, I/O ports in CMOS. Each port can be programmed to input or P1_5 to P1_7, output under the control of the direction register. P2_0 to P2_7, Pull-up resistors are selected for the following 4-pin units: P3_0 to P3_3, Pi_0 to Pi_3 and Pi_4 to Pi_7 (i = 0 to 3, 6 to 10); however, P6_0 to P6_7, they are enabled only for the input pins. I/O P7_0 to P7_7, P7_0 and P7_1 outputs are N-channel open drain P8_0 to P8_4, P8_6, P8_7, P9_3, P10_0 to P10_7 Timer A TA0OUT to Timers A0 to A4 input/output. TA4OUT I/O TA0OUT output assigned for port P7_0 is N-channel open drain TA0IN to TA4IN I Timers A0 to A4 input Timer B TB0IN to Timers B0 to B3, and B5 input I TB3IN, TB5IN Three-phase U, U, V, V, W, W Three-phase motor control timer output motor control O timer output R01DS0062EJ0130 Rev.1.30 Page 22 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.16 Pin Definitions and Functions for the 64-pin Package (2/3) Function Symbol I/O Description Serial interface CTS0 to CTS3, Handshake input I CTS5, CTS8 RTS0 to RTS3, Handshake output O RTS5, RTS8 CLK0 to CLK3, Transmit/receive clock input/output I/O CLK5, CLK8 RXD0 to RXD3, Serial data input I RXD5, RXD8 TXD0 to TXD3, Serial data output. O TXD5, TXD8 TXD2 output is N-channel open drain I2C-bus SDA0 to SDA3, Serial data input/output. I/O (simplified) SDA5 SDA2 output is N-channel open drain SCL0 to SCL3, Transmit/receive clock input/output. I/O SCL5 SCL2 output is N-channel open drain Serial interface STXD0 to STXD3, Serial data output in slave mode. O special functions STXD5 STXD2 is N-channel open drain SRXD0 to Serial data input in slave mode I SRXD3, SRXD5 SS0 to SS3, SS5 I Input to control serial interface special functions A/D converter AN_0 to AN_7, Analog input for the A/D converter AN0_0 to AN0_3, I AN2_0 to AN2_7 ADTRG I External trigger input for the A/D converter D/A converter DA0 O Output for the D/A converter Reference voltage VREF Reference voltage input for the A/D converter and D/A I input converter R01DS0062EJ0130 Rev.1.30 Page 23 of 93 Mar 3, 2014

R32C/111 Group 1. Overview Table 1.17 Pin Definitions and Functions for the 64-pin Package (3/3) Function Symbol I/O Description Intelligent I/O IIO0_0 to IIO0_7 Input/output for Intelligent I/O group 0. Either input capture I/O or output compare is selectable IIO1_0 to IIO1_7 Input/output for Intelligent I/O group 1. Either input capture or output compare is selectable. IIO1_6 and IIO1_7 outputs I/O assigned for ports P7_0 and P7_1 are N-channel open drain UD0A, UD0B, Input for the two-phase encoder I UD1A, UD1B OUTC2_0 to Output for OC (output compare) of Intelligent I/O group 2. OUTC2_2 O OUTC2_0 and OUTC2_2 assigned for ports P7_0 and P7_1 are N-channel open drain ISCLK2 I/O Clock input/output for the serial interface ISRXD2 I Receive data input for the serial interface ISTXD2 Transmit data output for the serial interface. ISTXD2 O assigned for port P7_0 is N-channel open drain IEIN I Receive data input for the serial interface IEOUT Transmit data output for the serial interface. IEOUT O assigned for port P7_0 is N-channel open drain R01DS0062EJ0130 Rev.1.30 Page 24 of 93 Mar 3, 2014

R32C/111 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) The CPU contains the registers shown below. There are two register banks each consisting of registers R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB. General purpose registers b31 b23 b15 b7 b0 R2R0 R2H R2L R0H R0L R3R1 R3H R3L R1H R1L Data registers (1) R6R4 R6 R4 R7R5 R7 R5 A0 A1 Address registers (1) A2 A3 SB Static base register (1) FB Frame base register (1) USP User stack pointer ISP Interrupt stack pointer INTB Interrupt vector table base register PC Program counter FLG Flag register b31 b24 b23 b16 b15 b8 b7 b0 RND IPL U I O B S Z D C DP FU FO Blank spaces are reserved. b31 b0 Fast interrupt SVF Save flag register registers SVP Save PC register VCT Vector register b31 b23 b0 DMAC-associated registers (2) DDDMDMMDMDD0D000 DMA mode register DDDCDCCTCT0T0T00 DMA terminal count register DDDCDCCRCRR0R000 DMA terminal count reload register DDDSDSSASAA0A000 DMA source address register DDDSDSSRSRR0R000 DMA source address reload register DDDDDDDADAA0A000 DMA destination address register DDDDDDDRDRR0R000 DMA destination address reload register Notes: 1.There are two banks of these registers. 2.There are four identical sets of DMAC-associated registers. Figure 2.1 CPU Registers R01DS0062EJ0130 Rev.1.30 Page 25 of 93 Mar 3, 2014

R32C/111 Group 2. Central Processing Unit (CPU) 2.1 General Purpose Registers 2.1.1 Data Registers (R2R0, R3R1, R6R4, and R7R5) These 32-bit registers are primarily used for transfers and arithmetic/logic operations. Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into R2 and R0, R3R1 can be divided into R3 and R1, etc. Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L). 2.1.2 Address Registers (A0, A1, A2, and A3) These 32-bit registers have functions similar to data registers. They are also used for address register indirect addressing and address register relative addressing. 2.1.3 Static Base Register (SB) This 32-bit register is used for SB relative addressing. 2.1.4 Frame Base Register (FB) This 32-bit register is used for FB relative addressing. 2.1.5 Program Counter (PC) This 32-bit counter indicates the address of the instruction to be executed next. 2.1.6 Interrupt Vector Table Base Register (INTB) This 32-bit register indicates the start address of a relocatable vector table. 2.1.7 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack pointer (ISP). Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for details. To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer (USP) or the interrupt stack pointer (ISP) to a multiple of 4. 2.1.8 Flag Register (FLG) This 32-bit register indicates the CPU status. 2.1.8.1 Carry Flag (C flag) This flag retains a carry, borrow, or shifted-out bit generated by the arithmetic logic unit (ALU). 2.1.8.2 Debug Flag (D flag) This flag is only for debugging. Only set this bit to 0. 2.1.8.3 Zero Flag (Z flag) This flag becomes 1 when the result of an operation is 0; otherwise it is 0. 2.1.8.4 Sign Flag (S flag) This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0. R01DS0062EJ0130 Rev.1.30 Page 26 of 93 Mar 3, 2014

R32C/111 Group 2. Central Processing Unit (CPU) 2.1.8.5 Register Bank Select Flag (B flag) This flag selects a register bank. It indicates 0 when register bank 0 is selected, and 1 when register bank 1 is selected. 2.1.8.6 Overflow Flag (O flag) This flag becomes 1 when the result of an operation overflows; otherwise it is 0. 2.1.8.7 Interrupt Enable Flag (I flag) This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable them, set this flag to 1. When an interrupt is accepted, the flag becomes 0. 2.1.8.8 Stack Pointer Select Flag (U flag) To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set this flag to 1. It becomes 0 when a hardware interrupt is accepted or when an INT instruction designated by a software interrupt number from 0 to 127 is executed. 2.1.8.9 Floating-point Underflow Flag (FU flag) This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also becomes 1 when the operand contains invalid numbers (subnormal numbers). 2.1.8.10 Floating-point Overflow Flag (FO flag) This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also becomes 1 when the operand contains invalid numbers (subnormal numbers). 2.1.8.11 Processor Interrupt Priority Level (IPL) The processor interrupt priority level (IPL), consisting of 3 bits, selects a processor interrupt priority level from level 0 to 7. An interrupt is enabled when the interrupt request level is higher than the selected IPL. When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled. 2.1.8.12 Fixed-point Radix Point Designation Bit (DP bit) This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result to extract. It is used for the MULX instruction. 2.1.8.13 Floating-point Rounding Mode (RND) The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results. 2.1.8.14 Reserved Only set this bit to 0. The read value is undefined. R01DS0062EJ0130 Rev.1.30 Page 27 of 93 Mar 3, 2014

R32C/111 Group 2. Central Processing Unit (CPU) 2.2 Fast Interrupt Registers The following three registers are provided to minimize the overhead of the interrupt sequence. 2.2.1 Save Flag Register (SVF) This 32-bit register is used to save the flag register when a fast interrupt occurs. 2.2.2 Save PC Register (SVP) This 32-bit register is used to save the program counter when a fast interrupt occurs. 2.2.3 Vector Register (VCT) This 32-bit register is used to indicate a jump address when a fast interrupt occurs. 2.3 DMAC-associated Registers There are seven types of DMAC-associated registers. 2.3.1 DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3) These 32-bit registers are used to set DMA transfer mode, bit rate, etc. 2.3.2 DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3) These 24-bit registers are used to set the number of DMA transfers. 2.3.3 DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3) These 24-bit registers are used to set the reloaded values for DMA terminal count registers. 2.3.4 DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3) These 32-bit registers are used to set DMA source addresses. 2.3.5 DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3) These 32-bit registers are used to set the reloaded values for DMA source address registers. 2.3.6 DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3) These 32-bit registers are used to set DMA destination addresses. 2.3.7 DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and DDR3) These 32-bit registers are used to set reloaded values for DMA destination address registers. R01DS0062EJ0130 Rev.1.30 Page 28 of 93 Mar 3, 2014

R32C/111 Group 3. Memory 3. Memory Figure 3.1 shows the memory map of the R32C/111 Group. The R32C/111 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh. The internal ROM is mapped from address FFFFFFFFh in the inferior direction. For example, the 512-Kbyte internal ROM is mapped from FFF80000h to FFFFFFFFh. The fixed interrupt vector table contains the start address of interrupt handlers and is mapped from FFFFFFDCh to FFFFFFFFh. The internal RAM is mapped from address 00000400h in the superior direction. For example, the 63-Kbyte internal RAM is mapped from 00000400h to 0000FFFFh. Besides being used for data storage, the internal RAM functions as a stack(s) for subroutine calls and/or interrupt handlers. Special function registers (SFRs), which are control registers for peripheral functions, are mapped from 00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved, and no access is allowed. In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should not be accessed. 00000000h SFR1 00000400h Internal RAM Internal RAM XXXXXXXXh Capacity XXXXXXXXh Reserved 32 Kbytes 00008400h 40 Kbytes 0000A400h 00040000h SFR2 63 Kbytes 00010000h 00050000h Reserved 00060000h Internal ROM (Data space) (1) 00062000h Reserved Internal ROM 00080000h FFFFFFDCh Undefined instruction Overflow Capacity YYYYYYYYh External space (2) BRK instruction 128 Kbytes FFFE0000h Reserved 256 Kbytes FFFC0000h FFE00000h Reserved Reserved (3) Watchdog timer (5) 384 Kbytes FFFA0000h Reserved 512 Kbytes FFF80000h YYYYYYYYh Internal ROM (4) NMI FFFFFFFFh FFFFFFFFh Reset Notes: 1. The flash memory version provides two additional 4-Kbyte spaces (blocks A and B) for storing data. 2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h to FDFFFFFFh are inaccessible. 3. This space is reserved in memory expansion mode. It becomes an external space in microprocessor mode. 4. This space can be used in single-chip mode or memory expansion mode. It becomes an external space in microprocessor mode. 5. The watchdog timer interrupt shares a vector with the oscillator stop detection interrupt and low voltage detection interrupt. Figure 3.1 Memory Map R01DS0062EJ0130 Rev.1.30 Page 29 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) SFRs are memory-mapped peripheral registers that control the operation of peripherals. Tables 4.1 SFR List (1) to 4.24 SFR List (24) list the SFR details. Table 4.1 SFR List (1) Address Register Symbol Reset Value 000000h 000001h 000002h 000003h 000004h Clock Control Register CCR 0001 1000b 000005h 000006h Flash Memory Control Register FMCR 0000 0001b 000007h Protect Release Register PRR 00h 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h External Bus Control Register 3/Flash Memory Rewrite Bus EBC3/FEBC3 0000h 000011h Control Register 3 000012h Chip Selects 2 and 3 Boundary Setting Register CB23 00h 000013h 000014h External Bus Control Register 2 EBC2 0000h 000015h 000016h Chip Selects 1 and 2 Boundary Setting Register CB12 00h 000017h 000018h External Bus Control Register 1 EBC1 0000h 000019h 00001Ah Chip Selects 0 and 1 Boundary Setting Register CB01 00h 00001Bh 00001Ch External Bus Control Register 0/Flash Memory Rewrite Bus EBC0/FEBC0 0000h 00001Dh Control Register 0 00001Eh Peripheral Bus Control Register PBC 0504h 00001Fh 000020h to 00005Fh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 30 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.2 SFR List (2) Address Register Symbol Reset Value 000060h 000061h Timer B5 Interrupt Control Register TB5IC XXXX X000b 000062h UART5 Transmit/NACK Interrupt Control Register S5TIC XXXX X000b 000063h UART2 Receive/ACK Interrupt Control Register S2RIC XXXX X000b 000064h UART6 Transmit/NACK Interrupt Control Register S6TIC XXXX X000b 000065h UART3 Receive/ACK Interrupt Control Register S3RIC XXXX X000b 000066h UART5/6 Bus Collision, START Condition/STOP Condition BCN5IC/BCN6IC XXXX X000b Detection Interrupt Control Register 000067h UART4 Receive/ACK Interrupt Control Register S4RIC XXXX X000b 000068h DMA0 Transfer Complete Interrupt Control Register DM0IC XXXX X000b 000069h UART0/3 Bus Collision, START Condition/STOP Condition BCN0IC/BCN3IC XXXX X000b Detection Interrupt Control Register 00006Ah DMA2 Transfer Complete Interrupt Control Register DM2IC XXXX X000b 00006Bh A/D Converter 0 Convert Completion Interrupt Control Register AD0IC XXXX X000b 00006Ch Timer A0 Interrupt Control Register TA0IC XXXX X000b 00006Dh Intelligent I/O Interrupt Control Register 0 IIO0IC XXXX X000b 00006Eh Timer A2 Interrupt Control Register TA2IC XXXX X000b 00006Fh Intelligent I/O Interrupt Control Register 2 IIO2IC XXXX X000b 000070h Timer A4 Interrupt Control Register TA4IC XXXX X000b 000071h Intelligent I/O Interrupt Control Register 4 IIO4IC XXXX X000b 000072h UART0 Receive/ACK Interrupt Control Register S0RIC XXXX X000b 000073h Intelligent I/O Interrupt Control Register 6 IIO6IC XXXX X000b 000074h UART1 Receive/ACK Interrupt Control Register S1RIC XXXX X000b 000075h Intelligent I/O Interrupt Control Register 8 IIO8IC XXXX X000b 000076h Timer B1 Interrupt Control Register TB1IC XXXX X000b 000077h Intelligent I/O Interrupt Control Register 10 IIO10IC XXXX X000b 000078h Timer B3 Interrupt Control Register TB3IC XXXX X000b 000079h 00007Ah INT5 Interrupt Control Register INT5IC XX00 X000b 00007Bh 00007Ch INT3 Interrupt Control Register INT3IC XX00 X000b 00007Dh 00007Eh INT1 Interrupt Control Register INT1IC XX00 X000b 00007Fh 000080h 000081h UART2 Transmit/NACK Interrupt Control Register S2TIC XXXX X000b 000082h UART5 Receive/ACK Interrupt Control Register S5RIC XXXX X000b 000083h UART3 Transmit/NACK Interrupt Control Register S3TIC XXXX X000b 000084h UART6 Receive/ACK Interrupt Control Register S6RIC XXXX X000b 000085h UART4 Transmit/NACK Interrupt Control Register S4TIC XXXX X000b 000086h 000087h UART2 Bus Collision, START Condition/STOP Condition BCN2IC XXXX X000b Detection Interrupt Control Register X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 31 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.3 SFR List (3) Address Register Symbol Reset Value 000088h DMA1 Transfer Complete Interrupt Control Register DM1IC XXXX X000b 000089h UART1/4 Bus Collision, START Condition/STOP Condition BCN1IC/BCN4IC XXXX X000b Detection Interrupt Control Register 00008Ah DMA3 Transfer Complete Interrupt Control Register DM3IC XXXX X000b 00008Bh Key Input Interrupt Control Register KUPIC XXXX X000b 00008Ch Timer A1 Interrupt Control Register TA1IC XXXX X000b 00008Dh Intelligent I/O Interrupt Control Register 1 IIO1IC XXXX X000b 00008Eh Timer A3 Interrupt Control Register TA3IC XXXX X000b 00008Fh Intelligent I/O Interrupt Control Register 3 IIO3IC XXXX X000b 000090h UART0 Transmit/NACK Interrupt Control Register S0TIC XXXX X000b 000091h Intelligent I/O Interrupt Control Register 5 IIO5IC XXXX X000b 000092h UART1 Transmit/NACK Interrupt Control Register S1TIC XXXX X000b 000093h Intelligent I/O Interrupt Control Register 7 IIO7IC XXXX X000b 000094h Timer B0 Interrupt Control Register TB0IC XXXX X000b 000095h Intelligent I/O Interrupt Control Register 9 IIO9IC XXXX X000b 000096h Timer B2 Interrupt Control Register TB2IC XXXX X000b 000097h Intelligent I/O Interrupt Control Register 11 IIO11IC XXXX X000b 000098h Timer B4 Interrupt Control Register TB4IC XXXX X000b 000099h 00009Ah INT4 Interrupt Control Register INT4IC XX00 X000b 00009Bh 00009Ch INT2 Interrupt Control Register INT2IC XX00 X000b 00009Dh 00009Eh INT0 Interrupt Control Register INT0IC XX00 X000b 00009Fh 0000A0h Intelligent I/O Interrupt Request Register 0 IIO0IR 0000 0XX1b 0000A1h Intelligent I/O Interrupt Request Register 1 IIO1IR 0000 0XX1b 0000A2h Intelligent I/O Interrupt Request Register 2 IIO2IR 0000 0X01b 0000A3h Intelligent I/O Interrupt Request Register 3 IIO3IR 0000 XXX1b 0000A4h Intelligent I/O Interrupt Request Register 4 IIO4IR 000X 0XX1b 0000A5h Intelligent I/O Interrupt Request Register 5 IIO5IR 000X 0XX1b 0000A6h Intelligent I/O Interrupt Request Register 6 IIO6IR 000X 0XX1b 0000A7h Intelligent I/O Interrupt Request Register 7 IIO7IR X00X 0XX1b 0000A8h Intelligent I/O Interrupt Request Register 8 IIO8IR XX0X 0XX1b 0000A9h Intelligent I/O Interrupt Request Register 9 IIO9IR 0000 0XX1b 0000AAh Intelligent I/O Interrupt Request Register 10 IIO10IR 0000 0XX1b 0000ABh Intelligent I/O Interrupt Request Register 11 IIO11IR 0000 0XX1b 0000ACh 0000ADh 0000AEh 0000AFh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 32 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.4 SFR List (4) Address Register Symbol Reset Value 0000B0h Intelligent I/O Interrupt Enable Register 0 IIO0IE 00h 0000B1h Intelligent I/O Interrupt Enable Register 1 IIO1IE 00h 0000B2h Intelligent I/O Interrupt Enable Register 2 IIO2IE 00h 0000B3h Intelligent I/O Interrupt Enable Register 3 IIO3IE 00h 0000B4h Intelligent I/O Interrupt Enable Register 4 IIO4IE 00h 0000B5h Intelligent I/O Interrupt Enable Register 5 IIO5IE 00h 0000B6h Intelligent I/O Interrupt Enable Register 6 IIO6IE 00h 0000B7h Intelligent I/O Interrupt Enable Register 7 IIO7IE 00h 0000B8h Intelligent I/O Interrupt Enable Register 8 IIO8IE 00h 0000B9h Intelligent I/O Interrupt Enable Register 9 IIO9IE 00h 0000BAh Intelligent I/O Interrupt Enable Register 10 IIO10IE 00h 0000BBh Intelligent I/O Interrupt Enable Register 11 IIO11IE 00h 0000BCh 0000BDh 0000BEh 0000BFh 0000C0h 0000C1h 0000C2h 0000C3h 0000C4h 0000C5h 0000C6h 0000C7h 0000C8h 0000C9h 0000CAh 0000CBh 0000CCh 0000CDh 0000CEh 0000CFh 0000D0h 0000D1h 0000D2h 0000D3h 0000D4h 0000D5h 0000D6h 0000D7h 0000D8h 0000D9h 0000DAh 0000DBh 0000DCh 0000DDh UART7 Transmit Interrupt Control Register S7TIC XXXX X000b 0000DEh 0000DFh UART8 Transmit Interrupt Control Register S8TIC XXXX X000b X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 33 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.5 SFR List (5) Address Register Symbol Reset Value 0000E0h 0000E1h 0000E2h 0000E3h 0000E4h 0000E5h 0000E6h 0000E7h 0000E8h 0000E9h 0000EAh 0000EBh 0000ECh 0000EDh 0000EEh 0000EFh 0000F0h 0000F1h 0000F2h 0000F3h 0000F4h 0000F5h 0000F6h 0000F7h 0000F8h 0000F9h 0000FAh 0000FBh 0000FCh 0000FDh UART7 Receive Interrupt Control Register S7RIC XXXX X000b 0000FEh 0000FFh UART8 Receive Interrupt Control Register S8RIC XXXX X000b 000100h Group 1 Time Measurement/Waveform Generation Register 0 G1TM0/G1PO0 XXXXh 000101h 000102h Group 1 Time Measurement/Waveform Generation Register 1 G1TM1/G1PO1 XXXXh 000103h 000104h Group 1 Time Measurement/Waveform Generation Register 2 G1TM2/G1PO2 XXXXh 000105h 000106h Group 1 Time Measurement/Waveform Generation Register 3 G1TM3/G1PO3 XXXXh 000107h X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 34 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.6 SFR List (6) Address Register Symbol Reset Value 000108h Group 1 Time Measurement/Waveform Generation Register 4 G1TM4/G1PO4 XXXXh 000109h 00010Ah Group 1 Time Measurement/Waveform Generation Register 5 G1TM5/G1PO5 XXXXh 00010Bh 00010Ch Group 1 Time Measurement/Waveform Generation Register 6 G1TM6/G1PO6 XXXXh 00010Dh 00010Eh Group 1 Time Measurement/Waveform Generation Register 7 G1TM7/G1PO7 XXXXh 00010Fh 000110h Group 1 Waveform Generation Control Register 0 G1POCR0 0000 X000b 000111h Group 1 Waveform Generation Control Register 1 G1POCR1 0X00 X000b 000112h Group 1 Waveform Generation Control Register 2 G1POCR2 0X00 X000b 000113h Group 1 Waveform Generation Control Register 3 G1POCR3 0X00 X000b 000114h Group 1 Waveform Generation Control Register 4 G1POCR4 0X00 X000b 000115h Group 1 Waveform Generation Control Register 5 G1POCR5 0X00 X000b 000116h Group 1 Waveform Generation Control Register 6 G1POCR6 0X00 X000b 000117h Group 1 Waveform Generation Control Register 7 G1POCR7 0X00 X000b 000118h Group 1 Time Measurement Control Register 0 G1TMCR0 00h 000119h Group 1 Time Measurement Control Register 1 G1TMCR1 00h 00011Ah Group 1 Time Measurement Control Register 2 G1TMCR2 00h 00011Bh Group 1 Time Measurement Control Register 3 G1TMCR3 00h 00011Ch Group 1 Time Measurement Control Register 4 G1TMCR4 00h 00011Dh Group 1 Time Measurement Control Register 5 G1TMCR5 00h 00011Eh Group 1 Time Measurement Control Register 6 G1TMCR6 00h 00011Fh Group 1 Time Measurement Control Register 7 G1TMCR7 00h 000120h Group 1 Base Timer Register G1BT XXXXh 000121h 000122h Group 1 Base Timer Control Register 0 G1BCR0 0000 0000b 000123h Group 1 Base Timer Control Register 1 G1BCR1 0000 0000b 000124h Group 1 Time Measurement Prescaler Register 6 G1TPR6 00h 000125h Group 1 Time Measurement Prescaler Register 7 G1TPR7 00h 000126h Group 1 Function Enable Register G1FE 00h 000127h Group 1 Function Select Register G1FS 00h 000128h 000129h 00012Ah 00012Bh 00012Ch 00012Dh 00012Eh 00012Fh 000130h to 00013Fh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 35 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.7 SFR List (7) Address Register Symbol Reset Value 000140h Group 2 Waveform Generation Register 0 G2PO0 XXXXh 000141h 000142h Group 2 Waveform Generation Register 1 G2PO1 XXXXh 000143h 000144h Group 2 Waveform Generation Register 2 G2PO2 XXXXh 000145h 000146h Group 2 Waveform Generation Register 3 G2PO3 XXXXh 000147h 000148h Group 2 Waveform Generation Register 4 G2PO4 XXXXh 000149h 00014Ah Group 2 Waveform Generation Register 5 G2PO5 XXXXh 00014Bh 00014Ch Group 2 Waveform Generation Register 6 G2PO6 XXXXh 00014Dh 00014Eh Group 2 Waveform Generation Register 7 G2PO7 XXXXh 00014Fh 000150h Group 2 Waveform Generation Control Register 0 G2POCR0 0000 0000b 000151h Group 2 Waveform Generation Control Register 1 G2POCR1 0000 0000b 000152h Group 2 Waveform Generation Control Register 2 G2POCR2 0000 0000b 000153h Group 2 Waveform Generation Control Register 3 G2POCR3 0000 0000b 000154h Group 2 Waveform Generation Control Register 4 G2POCR4 0000 0000b 000155h Group 2 Waveform Generation Control Register 5 G2POCR5 0000 0000b 000156h Group 2 Waveform Generation Control Register 6 G2POCR6 0000 0000b 000157h Group 2 Waveform Generation Control Register 7 G2POCR7 0000 0000b 000158h 000159h 00015Ah 00015Bh 00015Ch 00015Dh 00015Eh 00015Fh 000160h Group 2 Base Timer Register G2BT XXXXh 000161h 000162h Group 2 Base Timer Control Register 0 G2BCR0 0000 0000b 000163h Group 2 Base Timer Control Register 1 G2BCR1 0000 0000b 000164h Base Timer Start Register BTSR XXXX 0000b 000165h 000166h Group 2 Function Enable Register G2FE 00h 000167h Group 2 RTP Output Buffer Register G2RTP 00h 000168h 000169h 00016Ah Group 2 Serial Interface Mode Register G2MR 00XX X000b 00016Bh Group 2 Serial Interface Control Register G2CR 0000 X110b 00016Ch Group 2 SI/O Transmit Buffer Register G2TB XXXXh 00016Dh 00016Eh Group 2 SI/O Receive Buffer Register G2RB XXXXh 00016Fh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 36 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.8 SFR List (8) Address Register Symbol Reset Value 000170h Group 2 IEBus Address Register IEAR XXXXh 000171h 000172h Group 2 IEBus Control Register IECR 00XX X000b 000173h Group 2 IEBus Transmit Interrupt Source Detect Register IETIF XXX0 0000b 000174h Group 2 IEBus Receive Interrupt Source Detect Register IERIF XXX0 0000b 000175h 000176h 000177h 000178h 000179h 00017Ah 00017Bh 00017Ch 00017Dh 00017Eh 00017Fh 000180h Group 0 Time Measurement/Waveform Generation Register 0 G0TM0/G0PO0 XXXXh 000181h 000182h Group 0 Time Measurement/Waveform Generation Register 1 G0TM1/G0PO1 XXXXh 000183h 000184h Group 0 Time Measurement/Waveform Generation Register 2 G0TM2/G0PO2 XXXXh 000185h 000186h Group 0 Time Measurement/Waveform Generation Register 3 G0TM3/G0PO3 XXXXh 000187h 000188h Group 0 Time Measurement/Waveform Generation Register 4 G0TM4/G0PO4 XXXXh 000189h 00018Ah Group 0 Time Measurement/Waveform Generation Register 5 G0TM5/G0PO5 XXXXh 00018Bh 00018Ch Group 0 Time Measurement/Waveform Generation Register 6 G0TM6/G0PO6 XXXXh 00018Dh 00018Eh Group 0 Time Measurement/Waveform Generation Register 7 G0TM7/G0PO7 XXXXh 00018Fh 000190h Group 0 Waveform Generation Control Register 0 G0POCR0 0000 X000b 000191h Group 0 Waveform Generation Control Register 1 G0POCR1 0X00 X000b 000192h Group 0 Waveform Generation Control Register 2 G0POCR2 0X00 X000b 000193h Group 0 Waveform Generation Control Register 3 G0POCR3 0X00 X000b 000194h Group 0 Waveform Generation Control Register 4 G0POCR4 0X00 X000b 000195h Group 0 Waveform Generation Control Register 5 G0POCR5 0X00 X000b 000196h Group 0 Waveform Generation Control Register 6 G0POCR6 0X00 X000b 000197h Group 0 Waveform Generation Control Register 7 G0POCR7 0X00 X000b 000198h Group 0 Time Measurement Control Register 0 G0TMCR0 00h 000199h Group 0 Time Measurement Control Register 1 G0TMCR1 00h 00019Ah Group 0 Time Measurement Control Register 2 G0TMCR2 00h 00019Bh Group 0 Time Measurement Control Register 3 G0TMCR3 00h 00019Ch Group 0 Time Measurement Control Register 4 G0TMCR4 00h 00019Dh Group 0 Time Measurement Control Register 5 G0TMCR5 00h 00019Eh Group 0 Time Measurement Control Register 6 G0TMCR6 00h 00019Fh Group 0 Time Measurement Control Register 7 G0TMCR7 00h X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 37 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.9 SFR List (9) Address Register Symbol Reset Value 0001A0h Group 0 Base Timer Register G0BT XXXXh 0001A1h 0001A2h Group 0 Base Timer Control Register 0 G0BCR0 0000 0000b 0001A3h Group 0 Base Timer Control Register 1 G0BCR1 0000 0000b 0001A4h Group 0 Time Measurement Prescaler Register 6 G0TPR6 00h 0001A5h Group 0 Time Measurement Prescaler Register 7 G0TPR7 00h 0001A6h Group 0 Function Enable Register G0FE 00h 0001A7h Group 0 Function Select Register G0FS 00h 0001A8h 0001A9h 0001AAh 0001ABh 0001ACh 0001ADh 0001AEh 0001AFh 0001B0h 0001B1h 0001B2h 0001B3h 0001B4h 0001B5h 0001B6h 0001B7h 0001B8h 0001B9h 0001BAh 0001BBh 0001BCh 0001BDh 0001BEh 0001BFh 0001C0h 0001C1h 0001C2h 0001C3h 0001C4h UART5 Special Mode Register 4 U5SMR4 00h 0001C5h UART5 Special Mode Register 3 U5SMR3 00h 0001C6h UART5 Special Mode Register 2 U5SMR2 00h 0001C7h UART5 Special Mode Register U5SMR 00h 0001C8h UART5 Transmit/Receive Mode Register U5MR 00h 0001C9h UART5 Bit Rate Register U5BRG XXh 0001CAh UART5 Transmit Buffer Register U5TB XXXXh 0001CBh 0001CCh UART5 Transmit/Receive Control Register 0 U5C0 0000 1000b 0001CDh UART5 Transmit/Receive Control Register 1 U5C1 0000 0010b 0001CEh UART5 Receive Buffer Register U5RB XXXXh 0001CFh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 38 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.10 SFR List (10) Address Register Symbol Reset Value 0001D0h 0001D1h 0001D2h 0001D3h 0001D4h UART6 Special Mode Register 4 U6SMR4 00h 0001D5h UART6 Special Mode Register 3 U6SMR3 00h 0001D6h UART6 Special Mode Register 2 U6SMR2 00h 0001D7h UART6 Special Mode Register U6SMR 00h 0001D8h UART6 Transmit/Receive Mode Register U6MR 00h 0001D9h UART6 Bit Rate Register U6BRG XXh 0001DAh UART6 Transmit Buffer Register U6TB XXXXh 0001DBh 0001DCh UART6 Transmit/Receive Control Register 0 U6C0 0000 1000b 0001DDh UART6 Transmit/Receive Control Register 1 U6C1 0000 0010b 0001DEh UART6 Receive Buffer Register U6RB XXXXh 0001DFh 0001E0h UART7 Transmit/Receive Mode Register U7MR 00h 0001E1h UART7 Bit Rate Register U7BRG XXh 0001E2h UART7 Transmit Buffer Register U7TB XXXXh 0001E3h 0001E4h UART7 Transmit/Receive Control Register 0 U7C0 00X0 1000b 0001E5h UART7 Transmit/Receive Control Register 1 U7C1 XXXX 0010b 0001E6h UART7 Receive Buffer Register U7RB XXXXh 0001E7h 0001E8h UART8 Transmit/Receive Mode Register U8MR 00h 0001E9h UART8 Bit Rate Register U8BRG XXh 0001EAh UART8 Transmit Buffer Register U8TB XXXXh 0001EBh 0001ECh UART8 Transmit/Receive Control Register 0 U8C0 00X0 1000b 0001EDh UART8 Transmit/Receive Control Register 1 U8C1 XXXX 0010b 0001EEh UART8 Receive Buffer Register U8RB XXXXh 0001EFh 0001F0h UART7, UART8 Transmit/Receive Control Register 2 U78CON X000 0000b 0001F1h 0001F2h 0001F3h 0001F4h 0001F5h 0001F6h 0001F7h 0001F8h 0001F9h 0001FAh 0001FBh 0001FCh 0001FDh 0001FEh 0001FFh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 39 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.11 SFR List (11) Address Register Symbol Reset Value 000200h to 0002BFh 0002C0h X0 Register/Y0 Register X0R/Y0R XXXXh 0002C1h 0002C2h X1 Register/Y1 Register X1R/Y1R XXXXh 0002C3h 0002C4h X2 Register/Y2 Register X2R/Y2R XXXXh 0002C5h 0002C6h X3 Register/Y3 Register X3R/Y3R XXXXh 0002C7h 0002C8h X4 Register/Y4 Register X4R/Y4R XXXXh 0002C9h 0002CAh X5 Register/Y5 Register X5R/Y5R XXXXh 0002CBh 0002CCh X6 Register/Y6 Register X6R/Y6R XXXXh 0002CDh 0002CEh X7 Register/Y7 Register X7R/Y7R XXXXh 0002CFh 0002D0h X8 Register/Y8 Register X8R/Y8R XXXXh 0002D1h 0002D2h X9 Register/Y9 Register X9R/Y9R XXXXh 0002D3h 0002D4h X10 Register/Y10 Register X10R/Y10R XXXXh 0002D5h 0002D6h X11 Register/Y11 Register X11R/Y11R XXXXh 0002D7h 0002D8h X12 Register/Y12 Register X12R/Y12R XXXXh 0002D9h 0002DAh X13 Register/Y13 Register X13R/Y13R XXXXh 0002DBh 0002DCh X14 Register/Y14 Register X14R/Y14R XXXXh 0002DDh 0002DEh X15 Register/Y15 Register X15R/Y15R XXXXh 0002DFh 0002E0h X-Y Control Register XYC XXXX XX00b 0002E1h 0002E2h 0002E3h 0002E4h UART1 Special Mode Register 4 U1SMR4 00h 0002E5h UART1 Special Mode Register 3 U1SMR3 00h 0002E6h UART1 Special Mode Register 2 U1SMR2 00h 0002E7h UART1 Special Mode Register U1SMR 00h 0002E8h UART1 Transmit/Receive Mode Register U1MR 00h 0002E9h UART1 Bit Rate Register U1BRG XXh 0002EAh UART1 Transmit Buffer Register U1TB XXXXh 0002EBh 0002ECh UART1 Transmit/Receive Control Register 0 U1C0 0000 1000b 0002EDh UART1 Transmit/Receive Control Register 1 U1C1 0000 0010b 0002EEh UART1 Receive Buffer Register U1RB XXXXh 0002EFh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 40 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.12 SFR List (12) Address Register Symbol Reset Value 0002F0h 0002F1h 0002F2h 0002F3h 0002F4h UART4 Special Mode Register 4 U4SMR4 00h 0002F5h UART4 Special Mode Register 3 U4SMR3 00h 0002F6h UART4 Special Mode Register 2 U4SMR2 00h 0002F7h UART4 Special Mode Register U4SMR 00h 0002F8h UART4 Transmit/Receive Mode Register U4MR 00h 0002F9h UART4 Bit Rate Register U4BRG XXh 0002FAh UART4 Transmit Buffer Register U4TB XXXXh 0002FBh 0002FCh UART4 Transmit/Receive Control Register 0 U4C0 0000 1000b 0002FDh UART4 Transmit/Receive Control Register 1 U4C1 0000 0010b 0002FEh UART4 Receive Buffer Register U4RB XXXXh 0002FFh 000300h Count Start Register for Timers B3, B4, and B5 TBSR 000X XXXXb 000301h 000302h Timer A1-1 Register TA11 XXXXh 000303h 000304h Timer A2-1 Register TA21 XXXXh 000305h 000306h Timer A4-1 Register TA41 XXXXh 000307h 000308h Three-phase PWM Control Register 0 INVC0 00h 000309h Three-phase PWM Control Register 1 INVC1 00h 00030Ah Three-phase Output Buffer Register 0 IDB0 XX11 1111b 00030Bh Three-phase Output Buffer Register 1 IDB1 XX11 1111b 00030Ch Dead Time Timer DTT XXh 00030Dh Timer B2 Interrupt Generating Frequency Set Counter ICTB2 XXh 00030Eh 00030Fh 000310h Timer B3 Register TB3 XXXXh 000311h 000312h Timer B4 Register TB4 XXXXh 000313h 000314h Timer B5 Register TB5 XXXXh 000315h 000316h 000317h 000318h 000319h 00031Ah 00031Bh Timer B3 Mode Register TB3MR 00XX 0000b 00031Ch Timer B4 Mode Register TB4MR 00XX 0000b 00031Dh Timer B5 Mode Register TB5MR 00XX 0000b 00031Eh 00031Fh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 41 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.13 SFR List (13) Address Register Symbol Reset Value 000320h 000321h 000322h 000323h 000324h UART3 Special Mode Register 4 U3SMR4 00h 000325h UART3 Special Mode Register 3 U3SMR3 00h 000326h UART3 Special Mode Register 2 U3SMR2 00h 000327h UART3 Special Mode Register U3SMR 00h 000328h UART3 Transmit/Receive Mode Register U3MR 00h 000329h UART3 Bit Rate Register U3BRG XXh 00032Ah UART3 Transmit Buffer Register U3TB XXXXh 00032Bh 00032Ch UART3 Transmit/Receive Control Register 0 U3C0 0000 1000b 00032Dh UART3 Transmit/Receive Control Register 1 U3C1 0000 0010b 00032Eh UART3 Receive Buffer Register U3RB XXXXh 00032Fh 000330h 000331h 000332h 000333h 000334h UART2 Special Mode Register 4 U2SMR4 00h 000335h UART2 Special Mode Register 3 U2SMR3 00h 000336h UART2 Special Mode Register 2 U2SMR2 00h 000337h UART2 Special Mode Register U2SMR 00h 000338h UART2 Transmit/Receive Mode Register U2MR 00h 000339h UART2 Bit Rate Register U2BRG XXh 00033Ah UART2 Transmit Buffer Register U2TB XXXXh 00033Bh 00033Ch UART2 Transmit/Receive Control Register 0 U2C0 0000 1000b 00033Dh UART2 Transmit/Receive Control Register 1 U2C1 0000 0010b 00033Eh UART2 Receive Buffer Register U2RB XXXXh 00033Fh 000340h Count Start Register TABSR 0000 0000b 000341h Clock Prescaler Reset Register CPSRF 0XXX XXXXb 000342h One-shot Start Register ONSF 0000 0000b 000343h Trigger Select Register TRGSR 0000 0000b 000344h Increment/Decrement Select Register UDF 0000 0000b 000345h 000346h Timer A0 Register TA0 XXXXh 000347h 000348h Timer A1 Register TA1 XXXXh 000349h 00034Ah Timer A2 Register TA2 XXXXh 00034Bh 00034Ch Timer A3 Register TA3 XXXXh 00034Dh 00034Eh Timer A4 Register TA4 XXXXh 00034Fh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 42 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.14 SFR List (14) Address Register Symbol Reset Value 000350h Timer B0 Register TB0 XXXXh 000351h 000352h Timer B1 Register TB1 XXXXh 000353h 000354h Timer B2 Register TB2 XXXXh 000355h 000356h Timer A0 Mode Register TA0MR 0000 0000b 000357h Timer A1 Mode Register TA1MR 0000 0000b 000358h Timer A2 Mode Register TA2MR 0000 0000b 000359h Timer A3 Mode Register TA3MR 0000 0000b 00035Ah Timer A4 Mode Register TA4MR 0000 0000b 00035Bh Timer B0 Mode Register TB0MR 00XX 0000b 00035Ch Timer B1 Mode Register TB1MR 00XX 0000b 00035Dh Timer B2 Mode Register TB2MR 00XX 0000b 00035Eh Timer B2 Special Mode Register TB2SC XXXX XXX0b 00035Fh Count Source Prescaler Register TCSPR 0000 0000b 000360h 000361h 000362h 000363h 000364h UART0 Special Mode Register 4 U0SMR4 00h 000365h UART0 Special Mode Register 3 U0SMR3 00h 000366h UART0 Special Mode Register 2 U0SMR2 00h 000367h UART0 Special Mode Register U0SMR 00h 000368h UART0 Transmit/Receive Mode Register U0MR 00h 000369h UART0 Bit Rate Register U0BRG XXh 00036Ah UART0 Transmit Buffer Register U0TB XXXXh 00036Bh 00036Ch UART0 Transmit/Receive Control Register 0 U0C0 0000 1000b 00036Dh UART0 Transmit/Receive Control Register 1 U0C1 0000 0010b 00036Eh UART0 Receive Buffer Register U0RB XXXXh 00036Fh 000370h 000371h 000372h 000373h 000374h 000375h 000376h 000377h 000378h 000379h 00037Ah 00037Bh 00037Ch CRC Data Register CRCD XXXXh 00037Dh 00037Eh CRC Input Register CRCIN XXh 00037Fh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 43 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.15 SFR List (15) Address Register Symbol Reset Value 000380h A/D0 Register 0 AD00 00XXh 000381h 000382h A/D0 Register 1 AD01 00XXh 000383h 000384h A/D0 Register 2 AD02 00XXh 000385h 000386h A/D0 Register 3 AD03 00XXh 000387h 000388h A/D0 Register 4 AD04 00XXh 000389h 00038Ah A/D0 Register 5 AD05 00XXh 00038Bh 00038Ch A/D0 Register 6 AD06 00XXh 00038Dh 00038Eh A/D0 Register 7 AD07 00XXh 00038Fh 000390h 000391h 000392h A/D0 Control Register 4 AD0CON4 XXXX 00XXb 000393h 000394h A/D0 Control Register 2 AD0CON2 XX0X X000b 000395h A/D0 Control Register 3 AD0CON3 XXXX X000b 000396h A/D0 Control Register 0 AD0CON0 00h 000397h A/D0 Control Register 1 AD0CON1 00h 000398h D/A Register 0 DA0 XXh 000399h 00039Ah D/A Register 1 DA1 XXh 00039Bh 00039Ch D/A Control Register DACON XXXX XX00b 00039Dh 00039Eh 00039Fh 0003A0h 0003A1h 0003A2h 0003A3h 0003A4h 0003A5h 0003A6h 0003A7h 0003A8h 0003A9h 0003AAh 0003ABh 0003ACh 0003ADh 0003AEh 0003AFh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 44 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.16 SFR List (16) Address Register Symbol Reset Value 0003B0h 0003B1h 0003B2h 0003B3h 0003B4h 0003B5h 0003B6h 0003B7h 0003B8h 0003B9h 0003BAh 0003BBh 0003BCh 0003BDh 0003BEh 0003BFh 0003C0h Port P0 Register P0 XXh 0003C1h Port P1 Register P1 XXh 0003C2h Port P0 Direction Register PD0 0000 0000b 0003C3h Port P1 Direction Register PD1 0000 0000b 0003C4h Port P2 Register P2 XXh 0003C5h Port P3 Register P3 XXh 0003C6h Port P2 Direction Register PD2 0000 0000b 0003C7h Port P3 Direction Register PD3 0000 0000b 0003C8h Port P4 Register P4 XXh 0003C9h Port P5 Register P5 XXh 0003CAh Port P4 Direction Register PD4 0000 0000b 0003CBh Port P5 Direction Register PD5 0000 0000b 0003CCh Port P6 Register P6 XXh 0003CDh Port P7 Register P7 XXh 0003CEh Port P6 Direction Register PD6 0000 0000b 0003CFh Port P7 Direction Register PD7 0000 0000b 0003D0h Port P8 Register P8 XXh 0003D1h Port P9 Register P9 XXh 0003D2h Port P8 Direction Register PD8 00X0 0000b 0003D3h Port P9 Direction Register PD9 0000 0000b 0003D4h Port P10 Register P10 XXh 0003D5h 0003D6h Port P10 Direction Register PD10 0000 0000b 0003D7h 0003D8h 0003D9h 0003DAh 0003DBh 0003DCh 0003DDh 0003DEh 0003DFh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 45 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.17 SFR List (17) Address Register Symbol Reset Value 0003E0h 0003E1h 0003E2h 0003E3h 0003E4h 0003E5h 0003E6h 0003E7h 0003E8h 0003E9h 0003EAh 0003EBh 0003ECh 0003EDh 0003EEh 0003EFh 0003F0h Pull-up Control Register 0 PUR0 0000 0000b 0003F1h Pull-up Control Register 1 PUR1 XXXX 0000b 0003F2h Pull-up Control Register 2 PUR2 0000 0000b 0003F3h Pull-up Control Register 3 PUR3 XXXX XX00b 0003F4h 0003F5h 0003F6h 0003F7h 0003F8h 0003F9h 0003FAh 0003FBh 0003FCh 0003FDh 0003FEh 0003FFh Port Control Register PCR XXXX XXX0b X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 46 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.18 SFR List (18) Address Register Symbol Reset Value 040000h Flash Memory Control Register 0 FMR0 0X01 XX00b 040001h Flash Memory Status Register 0 FMSR0 1000 0000b 040002h 040003h 040004h 040005h 040006h 040007h 040008h Flash Register Protection Unlock Register 0 FPR0 00h 040009h Flash Memory Control Register 1 FMR1 0000 0010b 04000Ah Block Protect Bit Monitor Register 0 FBPM0 ??X? ????b (1) 04000Bh Block Protect Bit Monitor Register 1 FBPM1 XXX? ????b (1) 04000Ch 04000Dh 04000Eh 04000Fh 040010h 040011h 040012h 040013h 040014h 040015h 040016h 040017h 040018h 040019h 04001Ah 04001Bh 04001Ch 04001Dh 04001Eh 04001Fh 040020h PLL Control Register 0 PLC0 0000 0001b 040021h PLL Control Register 1 PLC1 0001 1111b 040022h 040023h 040024h 040025h 040026h 040027h 040028h 040029h 04002Ah 04002Bh 04002Ch 04002Dh 04002Eh 04002Fh X: Undefined Blanks are reserved. No access is allowed. Note: 1. The reset value reflects the value of the protect bit for each block in the flash memory. R01DS0062EJ0130 Rev.1.30 Page 47 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.19 SFR List (19) Address Register Symbol Reset Value 040030h to 04003Fh 040040h 040041h 040042h 040043h 040044h Processor Mode Register 0 (1) PM0 1000 0000b (CNVSS pin = Low) 0000 0011b (CNVSS pin = High) 040045h 040046h System Clock Control Register 0 CM0 0000 1000b 040047h System Clock Control Register 1 CM1 0010 0000b 040048h Processor Mode Register 3 PM3 00h 040049h 04004Ah Protect Register PRCR XXXX X000b 04004Bh 04004Ch Protect Register 3 PRCR3 0000 0000b 04004Dh Oscillator Stop Detection Register CM2 00h 04004Eh 04004Fh 040050h 040051h 040052h 040053h Processor Mode Register 2 PM2 00h 040054h Chip Select Output Pin Setting Register 0 CSOP0 1000 XXXXb 040055h Chip Select Output Pin Setting Register 1 CSOP1 01X0 XXXXb 040056h 040057h 040058h 040059h 04005Ah Low Speed Mode Clock Control Register CM3 XXXX XX00b 04005Bh 04005Ch 04005Dh 04005Eh 04005Fh 040060h Voltage Regulator Control Register VRCR 0000 0000b 040061h 040062h Low Voltage Detector Control Register LVDC 0000 XX00b 040063h 040064h Detection Voltage Configuration Register DVCR 0000 XXXXb 040065h 040066h 040067h 040068h to 040093h X: Undefined Blanks are reserved. No access is allowed. Note: 1. The value in the PM0 register is retained even after a software reset or watchdog timer reset. R01DS0062EJ0130 Rev.1.30 Page 48 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.20 SFR List (20) Address Register Symbol Reset Value 040094h 040095h 040096h 040097h Three-phase Output Buffer Control Register IOBC 0XXX XXXXb 040098h Input Function Select Register 0 IFS0 X000 0000b (1) 040099h 04009Ah Input Function Select Register 2 IFS2 0000 00X0b (2) 04009Bh Input Function Select Register 3 IFS3 XXXX XX00b 04009Ch 04009Dh 04009Eh 04009Fh Input Function Select Register 7 (3) IFS7 XXXX XX0Xb 0400A0h Port P0_0 Function Select Register P0_0S 0XXX X000b 0400A1h Port P1_0 Function Select Register P1_0S XXXX X000b 0400A2h Port P0_1 Function Select Register P0_1S 0XXX X000b 0400A3h Port P1_1 Function Select Register P1_1S XXXX X000b 0400A4h Port P0_2 Function Select Register P0_2S 0XXX X000b 0400A5h Port P1_2 Function Select Register P1_2S XXXX X000b 0400A6h Port P0_3 Function Select Register P0_3S 0XXX X000b 0400A7h Port P1_3 Function Select Register P1_3S XXXX X000b 0400A8h Port P0_4 Function Select Register P0_4S 0XXX X000b 0400A9h Port P1_4 Function Select Register P1_4S XXXX X000b 0400AAh Port P0_5 Function Select Register P0_5S 0XXX X000b 0400ABh Port P1_5 Function Select Register P1_5S XXXX X000b 0400ACh Port P0_6 Function Select Register P0_6S 0XXX X000b 0400ADh Port P1_6 Function Select Register P1_6S XXXX X000b 0400AEh Port P0_7 Function Select Register P0_7S 0XXX X000b 0400AFh Port P1_7 Function Select Register P1_7S XXXX X000b 0400B0h Port P2_0 Function Select Register P2_0S 0XXX X000b 0400B1h Port P3_0 Function Select Register P3_0S XXXX X000b 0400B2h Port P2_1 Function Select Register P2_1S 0XXX X000b 0400B3h Port P3_1 Function Select Register P3_1S XXXX X000b 0400B4h Port P2_2 Function Select Register P2_2S 0XXX X000b 0400B5h Port P3_2 Function Select Register P3_2S XXXX X000b 0400B6h Port P2_3 Function Select Register P2_3S 0XXX X000b 0400B7h Port P3_3 Function Select Register P3_3S XXXX X000b 0400B8h Port P2_4 Function Select Register P2_4S 0XXX X000b 0400B9h Port P3_4 Function Select Register P3_4S XXXX X000b 0400BAh Port P2_5 Function Select Register P2_5S 0XXX X000b 0400BBh Port P3_5 Function Select Register P3_5S XXXX X000b 0400BCh Port P2_6 Function Select Register P2_6S 0XXX X000b 0400BDh Port P3_6 Function Select Register P3_6S XXXX X000b 0400BEh Port P2_7 Function Select Register P2_7S 0XXX X000b 0400BFh Port P3_7 Function Select Register P3_7S XXXX X000b X: Undefined Blanks are reserved. No access is allowed. Notes: 1. The reset value is 0000 0000b in the 64-pin package. 2. The reset value is 0000 000Xb in the 64-pin package. 3. This register is provided for the 64-pin package only. No access is allowed in the 100-pin package. R01DS0062EJ0130 Rev.1.30 Page 49 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.21 SFR List (21) Address Register Symbol Reset Value 0400C0h Port P4_0 Function Select Register P4_0S XXXX X000b 0400C1h Port P5_0 Function Select Register P5_0S XXXX X000b 0400C2h Port P4_1 Function Select Register P4_1S XXXX X000b 0400C3h Port P5_1 Function Select Register P5_1S XXXX X000b 0400C4h Port P4_2 Function Select Register P4_2S XXXX X000b 0400C5h Port P5_2 Function Select Register P5_2S XXXX X000b 0400C6h Port P4_3 Function Select Register P4_3S XXXX X000b 0400C7h Port P5_3 Function Select Register P5_3S XXXX X000b 0400C8h Port P4_4 Function Select Register P4_4S XXXX X000b 0400C9h Port P5_4 Function Select Register P5_4S XXXX X000b 0400CAh Port P4_5 Function Select Register P4_5S XXXX X000b 0400CBh Port P5_5 Function Select Register P5_5S XXXX X000b 0400CCh Port P4_6 Function Select Register P4_6S XXXX X000b 0400CDh Port P5_6 Function Select Register P5_6S XXXX X000b 0400CEh Port P4_7 Function Select Register P4_7S XXXX X000b 0400CFh Port P5_7 Function Select Register P5_7S XXXX X000b 0400D0h Port P6_0 Function Select Register P6_0S XXXX X000b 0400D1h Port P7_0 Function Select Register P7_0S XXXX X000b 0400D2h Port P6_1 Function Select Register P6_1S XXXX X000b 0400D3h Port P7_1 Function Select Register P7_1S XXXX X000b 0400D4h Port P6_2 Function Select Register P6_2S XXXX X000b 0400D5h Port P7_2 Function Select Register P7_2S XXXX X000b 0400D6h Port P6_3 Function Select Register P6_3S XXXX X000b 0400D7h Port P7_3 Function Select Register P7_3S XXXX X000b 0400D8h Port P6_4 Function Select Register P6_4S XXXX X000b 0400D9h Port P7_4 Function Select Register P7_4S XXXX X000b 0400DAh Port P6_5 Function Select Register P6_5S XXXX X000b 0400DBh Port P7_5 Function Select Register P7_5S XXXX X000b 0400DCh Port P6_6 Function Select Register P6_6S XXXX X000b 0400DDh Port P7_6 Function Select Register P7_6S XXXX X000b 0400DEh Port P6_7 Function Select Register P6_7S XXXX X000b 0400DFh Port P7_7 Function Select Register P7_7S XXXX X000b 0400E0h Port P8_0 Function Select Register P8_0S XXXX X000b 0400E1h 0400E2h Port P8_1 Function Select Register P8_1S XXXX X000b 0400E3h 0400E4h Port P8_2 Function Select Register P8_2S XXXX X000b 0400E5h 0400E6h Port P8_3 Function Select Register P8_3S XXXX X000b 0400E7h Port P9_3 Function Select Register P9_3S 0XXX X000b 0400E8h Port P8_4 Function Select Register P8_4S XXXX X000b 0400E9h Port P9_4 Function Select Register P9_4S 0XXX X000b 0400EAh 0400EBh Port P9_5 Function Select Register P9_5S 0XXX X000b 0400ECh Port P8_6 Function Select Register P8_6S XXXX X000b 0400EDh Port P9_6 Function Select Register P9_6S 0XXX X000b 0400EEh Port P8_7 Function Select Register P8_7S XXXX X000b 0400EFh Port P9_7 Function Select Register P9_7S XXXX X000b X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 50 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.22 SFR List (22) Address Register Symbol Reset Value 0400F0h Port P10_0 Function Select Register P10_0S 0XXX X000b 0400F1h 0400F2h Port P10_1 Function Select Register P10_1S 0XXX X000b 0400F3h 0400F4h Port P10_2 Function Select Register P10_2S 0XXX X000b 0400F5h 0400F6h Port P10_3 Function Select Register P10_3S 0XXX X000b 0400F7h 0400F8h Port P10_4 Function Select Register P10_4S 0XXX X000b 0400F9h 0400FAh Port P10_5 Function Select Register P10_5S 0XXX X000b 0400FBh 0400FCh Port P10_6 Function Select Register P10_6S 0XXX X000b 0400FDh 0400FEh Port P10_7 Function Select Register P10_7S 0XXX X000b 0400FFh 040100h 040101h 040102h 040103h 040104h 040105h 040106h 040107h 040108h 040109h 04010Ah 04010Bh 04010Ch 04010Dh 04010Eh 04010Fh 040110h 040111h 040112h 040113h 040114h 040115h 040116h 040117h 040118h 040119h 04011Ah 04011Bh 04011Ch 04011Dh 04011Eh 04011Fh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 51 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.23 SFR List (23) Address Register Symbol Reset Value 040120h to 04403Fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404Ah 04404Bh 04404Ch 04404Dh 04404Eh Watchdog Timer Start Register WDTS XXXX XXXXb 04404Fh Watchdog Timer Control Register WDC 000X XXXXb 044050h 044051h 044052h 044053h 044054h 044055h 044056h 044057h 044058h 044059h 04405Ah 04405Bh 04405Ch 04405Dh 04405Eh 04405Fh Protect Register 2 PRCR2 0XXX XXXXb X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 52 of 93 Mar 3, 2014

R32C/111 Group 4. Special Function Registers (SFRs) Table 4.24 SFR List (24) Address Register Symbol Reset Value 044060h 044061h 044062h 044063h 044064h 044065h 044066h 044067h 044068h 044069h 04406Ah 04406Bh 04406Ch 04406Dh External Interrupt Request Source Select Register 1 IFSR1 X0XX XXXXb 04406Eh 04406Fh External Interrupt Request Source Select Register 0 IFSR0 0000 0000b 044070h DMA0 Request Source Select Register 2 DM0SL2 XX00 0000b 044071h DMA1 Request Source Select Register 2 DM1SL2 XX00 0000b 044072h DMA2 Request Source Select Register 2 DM2SL2 XX00 0000b 044073h DMA3 Request Source Select Register 2 DM3SL2 XX00 0000b 044074h 044075h 044076h 044077h 044078h DMA0 Request Source Select Register DM0SL XXX0 0000b 044079h DMA1 Request Source Select Register DM1SL XXX0 0000b 04407Ah DMA2 Request Source Select Register DM2SL XXX0 0000b 04407Bh DMA3 Request Source Select Register DM3SL XXX0 0000b 04407Ch 04407Dh Wake-up IPL Setting Register 2 RIPL2 XX0X 0000b 04407Eh 04407Fh Wake-up IPL Setting Register 1 RIPL1 XX0X 0000b 044080h 044081h 044082h 044083h 044084h 044085h 044086h 044087h 044088h 044089h 04408Ah 04408Bh 04408Ch 04408Dh 04408Eh 04408Fh X: Undefined Blanks are reserved. No access is allowed. R01DS0062EJ0130 Rev.1.30 Page 53 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Absolute Maximum Ratings (1) Symbol Characteristic Condition Value (2) Unit V V Supply voltage V = AV -0.3 to 6.0 V CC1, CC2 CC1 CC V Supply voltage — -0.3 to V V CC2 CC1 AV Analog supply voltage V = AV -0.3 to 6.0 V CC CC1 CC V Input XIN, RESET, CNVSS, NSD, V , I REF voltage P6_0toP6_7, P7_2toP7_7, -0.3 to V + 0.3 V P8_0toP8_7, P9_1, P9_3toP9_7, CC1 P10_0toP10_7 (3) P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, P3_0toP3_7, -0.3 to V + 0.3 V CC2 P4_0toP4_7, P5_0toP5_7 (3) P7_0, P7_1 -0.3 to 6.0 V V Output XOUT, P6_0toP6_7, P7_2toP7_7, O voltage P8_0 to P8_4, P8_6, P8_7, -0.3 to V + 0.3 V CC1 P9_3toP9_7, P10_0toP10_7 (3) P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, P3_0toP3_7, -0.3 to V + 0.3 V CC2 P4_0toP4_7, P5_0toP5_7 (3) P7_0, P7_1 -0.3 to 6.0 V Pd Power consumption Ta = 25°C 500 mW — Operating temperature range -40 to 85 °C T Storage temperature range -65 to 150 °C stg Notes: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The V pin is available in the 100-pin package only. It should be considered as V in the 64-pin CC2 CC1 package. 3. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P4, P5, P9_1, and P9_4 to P9_7 are available in the 100-pin package only. R01DS0062EJ0130 Rev.1.30 Page 54 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Table 5.2 Operating Conditions (1/5) (1) Value (2) Symbol Characteristic Unit Min. Typ. Max. V Digital supply voltage (V  V ) CC1, CC1 CC2 3.0 5.0 5.5 V V CC2 AVCC Analog supply voltage VCC1 V V Reference voltage 3.0 V V REF CC1 V Digital ground voltage 0 V SS AV Analog ground voltage 0 V SS dV / V ramp up rate (V < 2.0 V) CC1 CC1 CC1 0.05 V/ms dt V High level P2_0toP2_7, P3_0toP3_7, P4_0toP4_7, 0.8 × IH V V input P5_0toP5_7 (4) VCC2 CC2 voltage XIN, RESET, CNVSS, NSD, P6_0toP6_7, 0.8 × P7_2toP7_7, P8_0toP8_7 (3), P9_1, V V V CC1 CC1 P9_3toP9_7, P10_0toP10_7 (4) P7_0, P7_1 0.8 × 6.0 V V CC1 P0_0toP0_7, in single-chip mode 0.8 × V V P1_0toP1_7 (4) VCC2 CC2 in memory expansion mode 0.5 × V V or microprocessor mode (5) VCC2 CC2 V Low level P2_0toP2_7, P3_0toP3_7, P4_0toP4_7, IL 0 0.2 × V V input P5_0toP5_7 (4) CC2 voltage XIN, RESET, CNVSS, NSD, P6_0toP6_7, P7_0toP7_7, P8_0toP8_7 (3), P9_1, 0 0.2 × V V CC1 P9_3toP9_7, P10_0toP10_7 (4) P0_0toP0_7, in single-chip mode 0 0.2 × V V CC2 P1_0toP1_7 (4) in memory expansion mode 0.16 × 0 V or microprocessor mode (5) VCC2 T Operating N version -20 85 °C opr temperature D version -40 85 °C range Notes: 1. The device is operationally guaranteed under these operating conditions. 2. The V pin is available in the 100-pin package only. It should be considered as V in the 64-pin CC2 CC1 package. 3. V and V for P8_7 are specified for P8_7 as a programmable port. These values are not applicable IH IL for P8_7 as XCIN. 4. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P4, P5, P9_1, and P9_4 to P9_7 are available in the 100-pin package only. 5. Memory expansion mode and microprocessor mode are available in the 100-pin package only. R01DS0062EJ0130 Rev.1.30 Page 55 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Table 5.3 Operating Conditions (2/5) (V =V =3.0to5.5V, V =0V, and T =T , unless otherwise noted) (1) CC1 CC2 SS a opr Value (2) Symbol Characteristic Unit Min. Typ. Max. C Decoupling capacitance for voltage Inter-pin voltage: 1.5 V VDC 2.4 10.0 µF regulator Notes: 1. The device is operationally guaranteed under these operating conditions. 2. This value should be met with due consideration to the following conditions: operating temperature, DC bias, aging, etc. R01DS0062EJ0130 Rev.1.30 Page 56 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Table 5.4 Operating Conditions (3/5) (V =V =3.0to5.5V, V =0V, and T =T , unless otherwise noted) (1) CC1 CC2 SS a opr Value Symbol Characteristic Unit Min. Typ. Max. I High level P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, OH(peak) peak P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, -10.0 mA output P6_0toP6_7, P7_2toP7_7, P8_0toP8_4, P8_6, current (2) P8_7, P9_3toP9_7, P10_0toP10_7 (3) I High level P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, OH(avg) average P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, -5.0 mA output P6_0toP6_7, P7_2toP7_7, P8_0toP8_4, P8_6, current (4) P8_7, P9_3toP9_7, P10_0toP10_7 (3) I Low level P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, OL(peak) peak P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, 10.0 mA output P6_0toP6_7, P7_0toP7_7, P8_0toP8_4, P8_6, current (2) P8_7, P9_3toP9_7, P10_0toP10_7 (3) I Low level P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, OL(avg) average P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, 5.0 mA output P6_0toP6_7, P7_0toP7_7, P8_0toP8_4, P8_6, current (4) P8_7, P9_3toP9_7, P10_0toP10_7 (3) Notes: 1. The device is operationally guaranteed under these operating conditions. 2. The following conditions should be satisfied: •The sum of I of ports P0, P1, P2, P8_6, P8_7, P9, and P10 is 80 mA or less. OL(peak) •The sum of I of ports P3, P4, P5, P6, P7, and P8_0toP8_4 is 80 mA or less. OL(peak) •The sum of I of ports P0, P1, and P2 is -40 mA or less. OH(peak) •The sum of I of ports P8_6, P8_7, P9, and P10 is -40 mA or less. OH(peak) •The sum of I of ports P3, P4, and P5 is -40 mA or less. OH(peak) •The sum of I of ports P6, P7, and P8_0toP8_4 is -40 mA or less. OH(peak) 3. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P4, P5, and P9_4 to P9_7 are available in the 100-pin package only. 4. Average value within 100 ms. R01DS0062EJ0130 Rev.1.30 Page 57 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Table 5.5 Operating Conditions (4/5) (V =V =3.0to5.5V, V =0V, and T =T , unless otherwise noted) (1) CC1 CC2 SS a opr Value Symbol Characteristic Unit Min. Typ. Max. f Main clock oscillator frequency 4 16 MHz (XIN) f Reference clock frequency 2 4 MHz (XRef) f PLL clock oscillator frequency 96 128 MHz (PLL) f Base clock frequency 50 MHz (Base) t Base clock cycle time 20 ns c(Base) f CPU operating frequency 50 MHz (CPU) tc(CPU) CPU clock cycle time 20 ns f Peripheral bus clock operating frequency 25 MHz (BCLK) tc(BCLK) Peripheral bus clock cycle time 40 ns f Peripheral clock source frequency 32 MHz (PER) f Sub clock oscillator frequency 32.768 62.5 kHz (XCIN) Note: 1. The device is operationally guaranteed under these operating conditions. t c(Base) Base clock (internal signal) t c(CPU) CPU clock (internal signal) t c(BCLK) Peripheral bus clock (internal signal) Figure 5.1 Clock Cycle Time R01DS0062EJ0130 Rev.1.30 Page 58 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Table 5.6 Operating Conditions (5/5) (V =V =3.0to5.5V, V =0V, and T =T , unless otherwise noted) (1) CC1 CC2 SS a opr Value Symbol Characteristic Unit Min. Typ. Max. V Allowable ripple voltage V = 5.0 V 0.5 Vp-p r(VCC1) CC1 V = 3.0 V 0.3 Vp-p CC1 V Allowable ripple voltage V = 5.0 V 0.5 Vp-p r(VCC2) CC2 V = 3.0 V 0.3 Vp-p CC2 dV /dt Ripple voltage gradient V = 5.0 V ±0.3 V/ms r(VCC1) CC1 V = 3.0 V ±0.3 V/ms CC1 dV /dt Ripple voltage gradient V = 5.0 V ±0.3 V/ms r(VCC2) CC2 V = 3.0 V ±0.3 V/ms CC2 f Allowable ripple frequency 10 kHz r(VCC1) f Allowable ripple frequency 10 kHz r(VCC2) Note: 1. The device is operationally guaranteed under these operating conditions. 1 / fr(VCC1) or 1 / fr(VCC2) VCC1 Vr(VCC1) or or VCC2 Vr(VCC2) Figure 5.2 Ripple Waveform R01DS0062EJ0130 Rev.1.30 Page 59 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Table 5.7 Electrical Characteristics of RAM (V =V =3.0to5.5V, V =0V, and Ta=T , unless otherwise noted) CC1 CC2 SS opr Measurement Value Symbol Characteristic Unit Condition Min. Typ. Max. VRDR RAM data retention voltage (1) In stop mode 2.0 V Note: 1. The value listed in the table is the minimum V to retain RAM data. CC1 Table 5.8 Electrical Characteristics of Flash Memory (V = V =3.0to5.5V, V =0V, and Ta=T , unless otherwise noted) CC1 CC2 SS opr Value Symbol Characteristic Unit Min. Typ. Max. — Program/erase cycles (1) Program area 1000 Cycles Data area 10000 Cycles — 4-word program time Program area 150 900 µs Data area 300 1700 µs — Lock bit program time Program area 70 500 µs Data area 140 1000 µs — Block erasure time 4-Kbyte block 0.12 3.0 s 32-Kbyte block 0.17 3.0 s 64-Kbyte block 0.20 3.0 s — Data retention (2) Ta = 55°C (3) 10 Years Notes: 1. Program/erase definition This value represents the number of erasures per block. When the number of program/erase cycles is n, each block can be erased n times. For example, if a 4-word write is performed in 512 different addresses in the 4-Kbyte block A and then the block is erased, this is counted as a single program/erase operation. However, the same address cannot be written to more than once per erasure (overwrite disabled). 2. Data retention includes periods when no supply voltage is applied and no clock is provided. 3. Contact a Renesas Electronics sales office for data retention times other than the above condition. R01DS0062EJ0130 Rev.1.30 Page 60 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Table 5.9 Power Supply Circuit Timing Characteristics (V =V =3.0to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Measurement Value Symbol Characteristic Unit Condition Min. Typ. Max. t Internal power supply start-up stabilization d(P-R) 2 ms time after the main power supply is turned on td(P-R) Internal power supply start-up VCC1 Operating voltage stabilization time after the main power supply is turned on td(P-R) Supply voltage for internal logic PLL oscillator- output waveform Figure 5.3 Power Supply Circuit Timing Table 5.10 Electrical Characteristics of Voltage Regulator for Internal Logic (V =V =3.0to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Measurement Value Symbol Characteristics Unit Condition Min. Typ. Max. V Output voltage 1.5 V VDC1 Table 5.11 Electrical Characteristics of Low Voltage Detector (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Measurement Value Symbol Characteristics Unit Condition Min. Typ. Max. Vdet Detected voltage error ±0.3 V Vdet(R)-Vdet(F) Hysteresis width 0 V Self-consuming current V = 5.0 V, low CC1 — 4 µA voltage detector enabled t Operation start time of low voltage detector 150 µs d(E-A) R01DS0062EJ0130 Rev.1.30 Page 61 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Table 5.12 Electrical Characteristics of Oscillator (V =V =3.0to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Measurement Value Symbol Characteristics Unit Condition Min. Typ. Max. fSO(PLL) PLL clock self-oscillation frequency 35 55 80 MHz tLOCK(PLL) PLL lock time (1) 1 ms t PLL jitter period (p-p) 2.0 ns jitter(p-p) f On-chip oscillator frequency 62.5 125 250 kHz (OCO) Note: 1. This value is applicable only when the main clock oscillation is stable. Table 5.13 Electrical Characteristics of Clock Circuitry (V =V =3.0to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Measurement Value Symbol Characteristics Unit Condition Min. Typ. Max. t Recovery time from wait mode to low power mode 225 µs rec(WAIT) trec(STOP) Recovery time from stop mode (1) 225 µs Note: 1. The recovery time from stop mode does not include the main clock oscillation stabilization time. The CPU starts operating before the oscillator is stabilized. t rec(WAIT) Interrupt for exiting wait mode Recovery time from wait mode to low power mode Sub clock oscillator output On-chip oscillator output CPU clock t rec(WAIT) t rec(STOP) Interrupt for exiting Recovery time from stop mode stop mode Main clock oscillator output On-chip oscillator output CPU clock t rec(STOP) Figure 5.4 Clock Circuit Timing R01DS0062EJ0130 Rev.1.30 Page 62 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics Timing Requirements (V = V =3.0to5.5V, V =0V, and Ta=T , unless otherwise noted) CC1 CC2 SS opr Table 5.14 Flash Memory CPU Rewrite Mode Timing Value Symbol Characteristics Unit Min. Max. t Read cycle time 200 ns cR t Chip-select setup time before read 200 ns su(S-R) t Chip-select hold time after read 0 ns h(R-S) t Address setup time before read 200 ns su(A-R) t Address hold time after read 0 ns h(R-A) t Read pulse width 100 ns w(R) t Write cycle time 200 ns cW t Chip-select setup time before write 0 ns su(S-W) t Chip-select hold time after write 30 ns h(W-S) t Address setup time before write 0 ns su(A-W) t Address hold time after write 30 ns h(W-A) t Write pulse width 50 ns w(W) Read cycle t cR t su(S-R) t h(R-S) Chip select t su(A-R) t h(R-A) Address t w(R) RD Write cycle t cW t su(S-W) t h(W-S) Chip select t su(A-W) t h(W-A) Address t w(W) WR Figure 5.5 Flash Memory CPU Rewrite Mode Timing R01DS0062EJ0130 Rev.1.30 Page 63 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Table 5.15 Electrical Characteristics (1/3) (V =V =4.2to5.5V, V =0V, T =T , and f =50MHz, unless otherwise CC1 CC2 SS a opr (CPU) noted) Measurement Value (2) Symbol Characteristic Unit Condition Min. Typ. Max. V High P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, OH level P3_0toP3_7, P4_0toP4_7, P5_0toP5_7 I = -5 mA V -2.0 V V OH CC2 CC2 output (1) voltage P6_0toP6_7, P7_2toP7_7, P8_0 to P8_4, P8_6, P8_7, P9_3toP9_7, P10_0toP10_7 I = -5 mA V -2.0 V V OH CC1 CC1 (1) P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, P3_0toP3_7, P4_0toP4_7, P5_0toP5_7 I = -200 µA V -0.3 V V OH CC2 CC2 (1) P6_0toP6_7, P7_2toP7_7, P8_0 to P8_4, P8_6, P8_7, P9_3toP9_7, P10_0toP10_7 I = -200 µA V -0.3 V V OH CC1 CC1 (1) V Low P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, OL level P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, output P6_0toP6_7, P7_0toP7_7, P8_0toP8_4, I = 5 mA 2.0 V OL voltage P8_6, P8_7, P9_3toP9_7, P10_0toP10_7 (1) P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, P6_0toP6_7, P7_0toP7_7, P8_0toP8_4, I = 200 µA 0.45 V OL P8_6, P8_7, P9_3toP9_7, P10_0toP10_7 (1) Notes: 1. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P4, P5, and P9_4 to P9_7 are available in the 100-pin package only. 2. The V pin is available in the 100-pin package only. It should be considered as V in the 64-pin CC2 CC1 package. R01DS0062EJ0130 Rev.1.30 Page 64 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Table 5.16 Electrical Characteristics (2/3) (V =V =4.2to5.5V, V =0V, T =T , and f =50MHz, unless otherwise CC1 CC2 SS a opr (CPU) noted) Measurement Value Symbol Characteristic Unit Condition Min. Typ. Max. V - V Hysteresis HOLD, RDY, NMI, INT0toINT5, KI0toKI3, T+ T- TA0INtoTA4IN, TA0OUTtoTA4OUT, TB0INtoTB5IN, CTS0toCTS8, CLK0toCLK8, RXD0toRXD8, 0.2 1.0 V SCL0toSCL6, SDA0toSDA6, SS0toSS6, SRXD0toSRXD6, ADTRG, IIO0_0toIIO0_7, IIO1_0toIIO1_7, UD0A, UD0B, UD1A, UD1B, ISCLK2, ISRXD2, IEIN (1) RESET 0.2 1.8 V I High level XIN, RESET, CNVSS, NSD, IH input P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, current P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, V = 5 V 5.0 µA I P6_0toP6_7, P7_0toP7_7, P8_0toP8_7, P9_1, P9_3toP9_7, P10_0toP10_7 (2) I Low level XIN, RESET, CNVSS, NSD, IL input P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, current P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, V = 0 V -5.0 µA I P6_0toP6_7, P7_0toP7_7, P8_0toP8_7, P9_1, P9_3toP9_7, P10_0toP10_7 (2) R Pull-up P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, PULLUP resistor P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, P6_0toP6_7, P7_2toP7_7, P8_0toP8_4, V = 0 V 30 50 170 k I P8_6, P8_7, P9_1, P9_3toP9_7, P10_0toP10_7 (2) R Feedback XIN fXIN 1.5 M resistor R Feedback XCIN fXCIN 15 M resistor Notes: 1. Pins TB4IN, CTS4, CLK4, RXD4, SCL4, SDA4, SS4, SRXD4, and UART6, and UART7 are available in the 100-pin package only. 2. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P4, P5, P9_1, and P9_4 to P9_7 are available in the 100-pin package only. R01DS0062EJ0130 Rev.1.30 Page 65 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Table 5.17 Electrical Characteristics (3/3) (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Characterist Value Symbol Measurement Condition Unit ic Min. Typ. Max. I Power supply In single-chip mode, f =50MHz, f =25MHz, CC (CPU) (BCLK) current output pins are left open f =8MHz, (XIN) 32 45 mA and others are Active: XIN, PLL, connected to V SS Stopped: XCIN, OCO f = f /24 MHz, (CPU) SO(PLL) XIN-XOUT Active: PLL (self-oscillation), 10 mA Drive strength: low Stopped: XIN, XCIN, OCO f = f = f /256 MHz, XCIN-XCOUT (CPU) (BCLK) (XIN) Drive strength: low f(XIN)=8MHz, 1.2 mA Active: XIN, Stopped: PLL, XCIN, OCO f = f = 32.768 kHz, (CPU) (BCLK) Active: XCIN, 220 µA Stopped: XIN, PLL, OCO, Main regulator: shutdown f = f = f /4 kHz, (CPU) (BCLK) (OCO) Active: OCO, 230 µA Stopped: XIN, PLL, XCIN, Main regulator: shutdown f = f = f /256 MHz, (CPU) (BCLK) (XIN) f =8MHz, (XIN) Active: XIN, 960 1600 µA Stopped: PLL, XCIN, OCO, T = 25°C, Wait mode a f = f = 32.768 kHz, (CPU) (BCLK) Active: XCIN, Stopped: XIN, PLL, OCO, 8 140 µA Main regulator: shutdown, T = 25°C, Wait mode a f = f = f /4 kHz, (CPU) (BCLK) (OCO) Active: OCO, Stopped: XIN, PLL, XCIN, 10 150 µA Main regulator: shutdown, T = 25°C, Wait mode a Stopped: all clocks, Main regulator: shutdown, 5 70 µA T = 25°C a R01DS0062EJ0130 Rev.1.30 Page 66 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Table 5.18 A/D Conversion Characteristics (V =V =AV =V =4.2to5.5V, CC1 CC2 CC REF V =AV =0 V, T =T , and f =25MHz, unless otherwise noted) SS SS a opr (BCLK) Value Symbol Characteristic Measurement Condition Unit Min. Typ. Max. — Resolution V = V 10 Bits REF CC1 Absolute error V = V = V AN_0toAN_7, REF CC1 CC2 = 5 V AN0_0toAN0_7, ±3 LSB AN2_0toAN2_7, — ANEX0, ANEX1 (1) External op-amp ±7 LSB connection mode INL Integral non-linearity V = V = V AN_0toAN_7, REF CC1 CC2 error = 5 V AN0_0toAN0_7, ±3 LSB AN2_0toAN2_7, ANEX0, ANEX1 (1) External op-amp ±7 LSB connection mode DNL Differential non-linearity ±1 LSB error — Offset error ±3 LSB — Gain error ±3 LSB R Resistor ladder V = V 4 20 k LADDER REF CC1 t Conversion time  = 16 MHz, with sample and hold CONV AD 2.06 µs (10 bits) function  = 16 MHz, without sample and hold AD 3.69 µs function t Conversion time  = 16 MHz, with sample and hold CONV AD 1.75 µs (8 bits) function  = 16 MHz, without sample and hold AD 3.06 µs function t Sampling time  = 16 MHz 0.188 µs SAMP AD V Analog input voltage 0 V V IA REF  Operating clock Without sample and hold function 0.25 16 MHz AD frequency With sample and hold function 1 16 MHz Note: 1. Pins AN0_4 to AN0_7, ANEX0, and ANEX1 are available in the 100-pin package only. R01DS0062EJ0130 Rev.1.30 Page 67 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Table 5.19 D/A Conversion Characteristics (V =V =AV =V =4.2to5.5V, CC1 CC2 CC REF V =AV =0 V, and T =T , unless otherwise noted) SS SS a opr Value Symbol Characteristic Measurement Condition Unit Min. Typ. Max. — Resolution 8 Bits — Absolute precision 1.0 % t Settling time 3 µs S R Output resistance 4 10 20 k O I Reference input current See Note 1 1.5 mA VREF Note: 1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for the A/D converter is not considered. Even when the VCUT bit in the AD0CON1 register is set to 0 (V disconnected), I is supplied. REF VREF R01DS0062EJ0130 Rev.1.30 Page 68 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Timing Requirements (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.20 External Clock Input Value Symbol Characteristic Unit Min. Max. tc(X) External clock input period 62.5 250 ns t External clock input high level pulse width 25 ns w(XH) t External clock input low level pulse width 25 ns w(XL) tr(X) External clock input rise time 5 ns tf(X) External clock input fall time 5 ns tw / tc External clock input duty 40 60 % Table 5.21 External Bus Timing Value Symbol Characteristic Unit Min. Max. tsu(D-R) Data setup time before read 40 ns th(R-D) Data hold time after read 0 ns tdis(R-D) Data disable time after read 0.5 × tc(Base) + 10 ns R01DS0062EJ0130 Rev.1.30 Page 69 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Timing Requirements (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.22 Timer A Input (counting input in event counter mode) Value Symbol Characteristic Unit Min. Max. tc(TA) TAiIN input clock cycle time 200 ns tw(TAH) TAiIN input high level pulse width 80 ns tw(TAL) TAiIN input low level pulse width 80 ns Table 5.23 Timer A Input (gating input in timer mode) Value Symbol Characteristic Unit Min. Max. tc(TA) TAiIN input clock cycle time 400 ns tw(TAH) TAiIN input high level pulse width 180 ns tw(TAL) TAiIN input low level pulse width 180 ns Table 5.24 Timer A Input (external trigger input in one-shot timer mode) Value Symbol Characteristic Unit Min. Max. tc(TA) TAiIN input clock cycle time 200 ns tw(TAH) TAiIN input high level pulse width 80 ns tw(TAL) TAiIN input low level pulse width 80 ns Table 5.25 Timer A Input (external trigger input in pulse-width modulation mode) Value Symbol Characteristic Unit Min. Max. tw(TAH) TAiIN input high level pulse width 80 ns tw(TAL) TAiIN input low level pulse width 80 ns Table 5.26 Timer A Input (increment/decrement switching input in event counter mode) Value Symbol Characteristic Unit Min. Max. tc(UP) TAiOUT input clock cycle time 2000 ns tw(UPH) TAiOUT input high level pulse width 1000 ns tw(UPL) TAiOUT input low level pulse width 1000 ns tsu(UP-TIN) TAiOUT input setup time 400 ns th(TIN-UP) TAiOUT input hold time 400 ns R01DS0062EJ0130 Rev.1.30 Page 70 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Timing Requirements (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.27 Timer B Input (counting input in event counter mode) Value Symbol Characteristic Unit Min. Max. t TBiIN input clock cycle time (one edge counting) 200 ns c(TB) tw(TBH) TBiIN input high level pulse width (one edge counting) 80 ns tw(TBL) TBiIN input low level pulse width (one edge counting) 80 ns tc(TB) TBiIN input clock cycle time (both edges counting) 200 ns tw(TBH) TBiIN input high level pulse width (both edges counting) 80 ns tw(TBL) TBiIN input low level pulse width (both edges counting) 80 ns Table 5.28 Timer B Input (pulse period measure mode) Value Symbol Characteristic Unit Min. Max. t TBiIN input clock cycle time 400 ns c(TB) tw(TBH) TBiIN input high level pulse width 180 ns tw(TBL) TBiIN input low level pulse width 180 ns Table 5.29 Timer B Input (pulse-width measure mode) Value Symbol Characteristic Unit Min. Max. t TBiIN input clock cycle time 400 ns c(TB) tw(TBH) TBiIN input high level pulse width 180 ns tw(TBL) TBiIN input low level pulse width 180 ns R01DS0062EJ0130 Rev.1.30 Page 71 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Timing Requirements (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.30 Serial Interface Value Symbol Characteristic Unit Min. Max. tc(CK) CLKi input clock cycle time 200 ns tw(CKH) CLKi input high level pulse width 80 ns tw(CKL) CLKi input low level pulse width 80 ns tsu(D-C) RXDi input setup time 80 ns th(C-D) RXDi input hold time 90 ns Table 5.31 A/D Trigger Input Value Symbol Characteristic Unit Min. Max. tw(ADH) ADTRG input high level pulse width ----3------ ns Hardware trigger input high level pulse width  AD t ADTRG input low level pulse width w(ADL) 125 ns Hardware trigger input high level pulse width Table 5.32 External Interrupt INTi Input Value Symbol Characteristic Unit Min. Max. tw(INH) INTi input high level pulse width Edge sensitive 250 ns Level sensitive tc(CPU) + 200 ns tw(INL) INTi input low level pulse width Edge sensitive 250 ns Level sensitive tc(CPU) + 200 ns Table 5.33 Intelligent I/O Value Symbol Characteristic Unit Min. Max. t ISCLK2 input clock cycle time 600 ns c(ISCLK2) t ISCLK2 input high level pulse width 270 ns w(ISCLK2H) t ISCLK2 input low level pulse width 270 ns w(ISCLK2L) t ISRXD2 input setup time 150 ns su(RXD-ISCLK2) t ISRXD2 input hold time 100 ns h(ISCLK2-RXD) R01DS0062EJ0130 Rev.1.30 Page 72 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Switching Characteristics (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.34 External Bus Timing (separate bus) Measurement Value Symbol Characteristic Unit Condition Min. Max. t Chip-select setup time before su(S-R) (1) ns read th(R-S) Chip-select hold time after read tc(Base) - 10 ns tsu(A-R) Address setup time before read (1) ns th(R-A) Address hold time after read tc(Base) - 10 ns tw(R) Read pulse width (1) ns t Chip-select setup time before su(S-W) Refer to (1) ns write Figure 5.6 th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 10 ns tsu(A-W) Address setup time before write (1) ns th(W-A) Address hold time after write 1.5 × tc(Base) - 10 ns tw(W) Write pulse width (1) ns tsu(D-W) Data setup time before write (1) ns th(W-D) Data hold time after write 0 ns Note: 1. The value is calculated using the formulas below based on the base clock cycles (t ) and c(Base) respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For details on how to set values, refer to the User’s manual. t = t = Tsu(A-R) × t - 15 [ns] su(S-R) su(A-R) c(Base) t = Tw(R) × t - 10 [ns] w(R) c(Base) t = t = Tsu(A-W) × t - 15 [ns] su(S-W) su(A-W) c(Base) t = t = Tw(W) × t - 10 [ns] w(W) su(D-W) c(Base) R01DS0062EJ0130 Rev.1.30 Page 73 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Switching Characteristics (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.35 External Bus Timing (multiplexed bus) Measurement Value Symbol Characteristic Unit Condition Min. Max. t Chip-select setup time before su(S-ALE) (1) ns ALE t Chip-select hold time after read 1.5 × t - 10 ns h(R-S) c(Base) t Address setup time before ALE (1) ns su(A-ALE) t Address hold time after ALE 0.5 × t - 5 ns h(ALE-A) c(Base) t Address hold time after read 1.5 × t - 10 ns h(R-A) c(Base) t ALE-read delay time 0.5 × t - 5 0.5 × t + 10 ns d(ALE-R) c(Base) c(Base) t ALE pulse width (1) ns w(ALE) Refer to tdis(R-A) Address disable time after read Figure 5.6 8 ns t Read pulse width (1) ns w(R) t Chip-select hold time after write 1.5 × t - 10 ns h(W-S) c(Base) t Address hold time after write 1.5 × t - 10 ns h(W-A) c(Base) t ALE-write delay time 0.5 × t - 5 0.5 × t + 10 ns d(ALE-W) c(Base) c(Base) t Write pulse width (1) ns w(W) t Data setup time before write (1) ns su(D-W) t Data hold time after write 0.5 × t ns h(W-D) c(Base) Note: 1. The value is calculated using the formulas below based on the base clock cycles (t ) and c(Base) respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For details on how to set values, refer to the User’s manual. t = t = t = (Tsu(A-R) - 0.5) × t -15 [ns] su(S-ALE) su(A-ALE) w(ALE) c(Base) t = Tw(R) × t -10 [ns] w(R) c(Base) t = t = Tw(W) × t -10 [ns] w(W) su(D-W) c(Base) R01DS0062EJ0130 Rev.1.30 Page 74 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 5 V CC1 CC2 Switching Characteristics (V =V =4.2to5.5V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.36 Serial Interface Measurement Value Symbol Characteristic Unit Condition Min. Max. td(C-Q) TXDi output delay time Refer to 80 ns th(C-Q) TXDi output hold time Figure 5.6 0 ns Table 5.37 Intelligent I/O Measurement Value Symbol Characteristic Unit Condition Min. Max. td(ISCLK2-TXD) ISTXD2 output delay time Refer to 180 ns th(ISCLK2-RXD) ISTXD2 output hold time Figure 5.6 0 ns R01DS0062EJ0130 Rev.1.30 Page 75 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Table 5.38 Electrical Characteristics (1/3) (V =V =3.0to3.6V, V =0V, T =T , and CC1 CC2 SS a opr f =50MHz, unless otherwise noted) (CPU) Measurement Value (2) Symbol Characteristic Unit Condition Min. Typ. Max. V High P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, OH V - level P3_0toP3_7, P4_0toP4_7, P5_0toP5_7 I = -1 mA CC2 V V OH CC2 0.6 output (1) voltage P6_0toP6_7, P7_2toP7_7, P8_0 to P8_4, V - P8_6, P8_7, P9_3toP9_7, P10_0toP10_7 I = -1 mA CC1 V V OH CC1 0.6 (1) V Low P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, OL level P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, output P6_0toP6_7, P7_0toP7_7, P8_0toP8_4, I = 1 mA 0.5 V OL voltage P8_6, P8_7, P9_3toP9_7, P10_0toP10_7 (1) Notes: 1. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P4, P5, and P9_4 to P9_7 are available in the 100-pin package only. 2. The V pin is available in the 100-pin package only. It should be considered as V in the 64-pin CC2 CC1 package. R01DS0062EJ0130 Rev.1.30 Page 76 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Table 5.39 Electrical Characteristics (2/3) (V =V =3.0to3.6V, V =0V, T =T , and CC1 CC2 SS a opr f =50MHz, unless otherwise noted) (CPU) Measurement Value Symbol Characteristic Unit Condition Min. Typ. Max. V - V Hysteresis HOLD, RDY, NMI, INT0toINT5, KI0toKI3, T+ T- TA0INtoTA4IN, TA0OUTtoTA4OUT, TB0INtoTB5IN, CTS0toCTS8, CLK0toCLK8, RXD0toRXD8, SCL0toSCL6, SDA0toSDA6, SS0toSS6, 0.2 1.0 V SRXD0toSRXD6, ADTRG, IIO0_0toIIO0_7, IIO1_0toIIO1_7, UD0A, UD0B, UD1A, UD1B, ISCLK2, ISRXD2, IEIN (1) RESET 0.2 1.8 V I High level XIN, RESET, CNVSS, NSD, IH input P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, current P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, V = 3.3 V 4.0 µA I P6_0toP6_7, P7_0toP7_7, P8_0toP8_7, P9_1, P9_3toP9_7, P10_0toP10_7 (2) I Low level XIN, RESET, CNVSS, NSD, IL input P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, current P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, V = 0 V -4.0 µA I P6_0toP6_7, P7_0toP7_7, P8_0toP8_7, P9_1, P9_3toP9_7, P10_0toP10_7 (2) R Pull-up P0_0toP0_7, P1_0toP1_7, P2_0toP2_7, PULLUP resistor P3_0toP3_7, P4_0toP4_7, P5_0toP5_7, P6_0toP6_7, P7_2toP7_7, P8_0toP8_4, V = 0 V 50 100 500 k I P8_6, P8_7, P9_1, P9_3toP9_7, P10_0toP10_7 (2) R Feedback XIN fXIN 3 M resistor R Feedback XCIN fXCIN 25 M resistor Notes: 1. Pins TB4IN, CTS4, CLK4, RXD4, SCL4, SDA4, SS4, SRXD4, and UART6, and UART7 are available in the 100-pin package only. 2. Ports P0_4 to P0_7, P1_0 to P1_4, P3_4 to P3_7, P4, P5, P9_1, and P9_4 to P9_7 are available in the 100-pin package only. R01DS0062EJ0130 Rev.1.30 Page 77 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Table 5.40 Electrical Characteristics (3/3) (V =V =3.0to3.6V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Characte Value Symbol Measurement Condition Unit ristic Min. Typ. Max. I Power In single-chip mode, f =50MHz, f =25MHz, CC (CPU) (BCLK) supply output pins are left open f =8MHz, (XIN) 28 40 mA current and others are Active: XIN, PLL, connected to V SS Stopped: XCIN, OCO XIN-XOUT f(CPU) = fSO(PLL)/24 MHz, Drive strength: low Active: PLL (self-oscillation), 7 mA Stopped: XIN, XCIN, OCO XCIN-XCOUT f = f = f /256 MHz, (CPU) (BCLK) (XIN) Drive strength: low f =8MHz, (XIN) 670 µA Active: XIN, Stopped: PLL, XCIN, OCO f = f = 32.768 kHz, (CPU) (BCLK) Active: XCIN, 180 µA Stopped: XIN, PLL, OCO, Main regulator: shutdown f = f = f /4 kHz, (CPU) (BCLK) (OCO) Active: OCO, 190 µA Stopped: XIN, PLL, XCIN, Main regulator: shutdown f = f = f /256 MHz, (CPU) (BCLK) (XIN) f =8MHz, (XIN) Active: XIN, 500 900 µA Stopped: PLL, XCIN, OCO, T = 25°C, Wait mode a f = f = 32.768 kHz, (CPU) (BCLK) Active: XCIN, Stopped: XIN, PLL, OCO, 8 140 µA Main regulator: shutdown, T = 25°C, Wait mode a f = f = f /4 kHz, (CPU) (BCLK) (OCO) Active: OCO, Stopped: XIN, PLL, XCIN, 10 150 µA Main regulator: shutdown, T = 25°C, Wait mode a Stopped: all clocks, Main regulator: shutdown, 5 70 µA T = 25°C a R01DS0062EJ0130 Rev.1.30 Page 78 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Table 5.41 A/D Conversion Characteristics (V =V =AV =V =3.0to3.6V, CC1 CC2 CC REF V =AV =0 V, T =T , and f =25MHz, unless otherwise noted) SS SS a opr (BCLK) Value Symbol Characteristic Measurement Condition Unit Min. Typ. Max. — Resolution V = V 10 Bits REF CC1 Absolute error V = V = AN_0toAN_7, REF CC1 V = 3.3 V AN0_0toAN0_7, CC2 ±5 LSB AN2_0toAN2_7, — ANEX0, ANEX1 (1) External op-amp ±7 LSB connection mode INL Integral non-linearity V = V = AN_0toAN_7, REF CC1 error V = 3.3 V AN0_0toAN0_7, CC2 ±5 LSB AN2_0toAN2_7, ANEX0, ANEX1 (1) External op-amp ±7 LSB connection mode DNL Differential non- V = V = V = 3.3 V REF CC1 CC2 ±1 LSB linearity error — Offset error ±3 LSB — Gain error ±3 LSB R Resistor ladder V = V 4 20 k LADDER REF CC1 t Conversion time  = 10 MHz, CONV AD 3.3 µs (10 bits) with sample and hold function t Conversion time  = 10 MHz, CONV AD 2.8 µs (8 bits) with sample and hold function t Sampling time  = 10 MHz 0.3 µs SAMP AD V Analog input voltage 0 V V IA REF  Operating clock Without sample and hold function 0.25 10 MHz AD frequency With sample and hold function 1 10 MHz Note: 1. Pins AN0_4 to AN0_7, ANEX0, and ANEX1 are available in the 100-pin package only. R01DS0062EJ0130 Rev.1.30 Page 79 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Table 5.42 D/A Conversion Characteristics (V =V =AV =V =3.0to3.6V, CC1 CC2 CC REF V =AV =0 V, and T =T , unless otherwise noted) SS SS a opr Value Symbol Characteristic Measurement Condition Unit Min. Typ. Max. — Resolution 8 Bits — Absolute precision 1.0 % t Settling time 3 µs S R Output resistance 4 10 20 k O I Reference input current See Note 1 1.0 mA VREF Note: 1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for the A/D converter is not considered. Even when the VCUT bit in the AD0CON1 register is set to 0 (V disconnected), I is supplied. REF VREF R01DS0062EJ0130 Rev.1.30 Page 80 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Timing Requirements (V =V =3.0to3.6V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.43 External Clock Input Value Symbol Characteristic Unit Min. Max. tc(X) External clock input period 62.5 250 ns t External clock input high level pulse width 25 ns w(XH) t External clock input low level pulse width 25 ns w(XL) t External clock input rise time 5 ns r(X) tf(X) External clock input fall time 5 ns tw / tc External clock input duty 40 60 % Table 5.44 External Bus Timing Value Symbol Characteristic Unit Min. Max. tsu(D-R) Data setup time before read 40 ns t Data hold time after read 0 ns h(R-D) tdis(R-D) Data disable time after read 0.5 × tc(Base) + 10 ns R01DS0062EJ0130 Rev.1.30 Page 81 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Timing Requirements (V =V =3.0to3.6V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.45 Timer A Input (counting input in event counter mode) Value Symbol Characteristic Unit Min. Max. t TAiIN input clock cycle time 200 ns c(TA) t TAiIN input high level pulse width 80 ns w(TAH) t TAiIN input low level pulse width 80 ns w(TAL) Table 5.46 Timer A Input (gating input in timer mode) Value Symbol Characteristic Unit Min. Max. t TAiIN input clock cycle time 400 ns c(TA) t TAiIN input high level pulse width 180 ns w(TAH) t TAiIN input low level pulse width 180 ns w(TAL) Table 5.47 Timer A Input (external trigger input in one-shot timer mode) Value Symbol Characteristic Unit Min. Max. t TAiIN input clock cycle time 200 ns c(TA) t TAiIN input high level pulse width 80 ns w(TAH) t TAiIN input low level pulse width 80 ns w(TAL) Table 5.48 Timer A Input (external trigger input in pulse-width modulation mode) Value Symbol Characteristic Unit Min. Max. t TAiIN input high level pulse width 80 ns w(TAH) tw(TAL) TAiIN input low level pulse width 80 ns Table 5.49 Timer A Input (increment/decrement switching input in event counter mode) Value Symbol Characteristic Unit Min. Max. t TAiOUT input clock cycle time 2000 ns c(UP) t TAiOUT input high level pulse width 1000 ns w(UPH) t TAiOUT input low level pulse width 1000 ns w(UPL) t TAiOUT input setup time 400 ns su(UP-TIN) t TAiOUT input hold time 400 ns h(TIN-UP) R01DS0062EJ0130 Rev.1.30 Page 82 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Timing Requirements (V =V =3.0to3.6V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.50 Timer B Input (counting input in event counter mode) Value Symbol Characteristic Unit Min. Max. t TBiIN input clock cycle time (one edge counting) 200 ns c(TB) t TBiIN input high level pulse width (one edge counting) 80 ns w(TBH) t TBiIN input low level pulse width (one edge counting) 80 ns w(TBL) t TBiIN input clock cycle time (both edges counting) 200 ns c(TB) t TBiIN input high level pulse width (both edges counting) 80 ns w(TBH) t TBiIN input low level pulse width (both edges counting) 80 ns w(TBL) Table 5.51 Timer B Input (pulse period measure mode) Value Symbol Characteristic Unit Min. Max. t TBiIN input clock cycle time 400 ns c(TB) t TBiIN input high level pulse width 180 ns w(TBH) t TBiIN input low level pulse width 180 ns w(TBL) Table 5.52 Timer B Input (pulse-width measure mode) Value Symbol Characteristic Unit Min. Max. t TBiIN input clock cycle time 400 ns c(TB) t TBiIN input high level pulse width 180 ns w(TBH) t TBiIN input low level pulse width 180 ns w(TBL) R01DS0062EJ0130 Rev.1.30 Page 83 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Timing Requirements (V =V =3.0to3.6V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.53 Serial Interface Value Symbol Characteristic Unit Min. Max. t CLKi input clock cycle time 200 ns c(CK) t CLKi input high level pulse width 80 ns w(CKH) t CLKi input low level pulse width 80 ns w(CKL) tsu(D-C) RXDi input setup time 80 ns t RXDi input hold time 90 ns h(C-D) Table 5.54 A/D Trigger Input Value Symbol Characteristic Unit Min. Max. tw(ADH) ADTRG input high level pulse width ----3------ ns Hardware trigger input high level pulse width  AD t ADTRG input low level pulse width w(ADL) 125 ns Hardware trigger input high level pulse width Table 5.55 External Interrupt INTi Input Value Symbol Characteristic Unit Min. Max. t INTi input high level pulse width Edge sensitive 250 ns w(INH) Level sensitive tc(CPU) + 200 ns tw(INL) INTi input low level pulse width Edge sensitive 250 ns Level sensitive tc(CPU) + 200 ns Table 5.56 Intelligent I/O Value Symbol Characteristic Unit Min. Max. tc(ISCLK2) ISCLK2 input clock cycle time 600 ns tw(ISCLK2H) ISCLK2 input high level pulse width 270 ns tw(ISCLK2L) ISCLK2 input low level pulse width 270 ns tsu(RXD-ISCLK2) ISRXD2 input setup time 150 ns th(ISCLK2-RXD) ISRXD2 input hold time 100 ns R01DS0062EJ0130 Rev.1.30 Page 84 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Switching Characteristics (V =V =3.0to3.6V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.57 External Bus Timing (separate bus) Measurement Value Symbol Characteristic Unit Condition Min. Max. t Chip-select setup time before su(S-R) (1) ns read th(R-S) Chip-select hold time after read tc(Base) - 10 ns t Address setup time before read (1) ns su(A-R) th(R-A) Address hold time after read tc(Base) - 10 ns t Read pulse width (1) ns w(R) tsu(S-W) Chip-select setup time before Refer to (1) ns write Figure 5.6 t Chip-select hold time after write 1.5 × t - 10 ns h(W-S) c(Base) t Address setup time before write (1) ns su(A-W) t Address hold time after write 1.5 × t - 10 ns h(W-A) c(Base) t Write pulse width (1) ns w(W) t Data setup time before write (1) ns su(D-W) t Data hold time after write 0 ns h(W-D) Note: 1. The value is calculated using the formulas below based on the base clock cycles (t ) and c(Base) respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For details on how to set values, refer to the User’s manual. t = t = Tsu(A-R) × t - 15 [ns] su(S-R) su(A-R) c(Base) t = Tw(R) × t - 10 [ns] w(R) c(Base) t = t = Tsu(A-W) × t - 15 [ns] su(S-W) su(A-W) c(Base) t = t = Tw(W) × t - 10 [ns] w(W) su(D-W) c(Base) R01DS0062EJ0130 Rev.1.30 Page 85 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Switching Characteristics (V =V =3.0to3.6V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.58 External Bus Timing (multiplexed bus) Measurement Value Symbol Characteristic Unit Condition Min. Max. t Chip-select setup time before su(S-ALE) (1) ns ALE t Chip-select hold time after read 1.5 × t - 10 ns h(R-S) c(Base) t Address setup time before ALE (1) ns su(A-ALE) t Address hold time after ALE 0.5 × t - 5 ns h(ALE-A) c(Base) t Address hold time after read 1.5 × t - 10 ns h(R-A) c(Base) t ALE-read delay time 0.5 × t - 5 0.5 × t + 10 ns d(ALE-R) c(Base) c(Base) tw(ALE) ALE pulse width (1) ns Refer to tdis(R-A) Address disable time after read Figure 5.6 8 ns t Read pulse width (1) ns w(R) t Chip-select hold time after write 1.5 × t - 10 ns h(W-S) c(Base) t Address hold time after write 1.5 × t - 10 ns h(W-A) c(Base) t ALE-write delay time 0.5 × t - 5 0.5 × t + 10 ns d(ALE-W) c(Base) c(Base) t Write pulse width (1) ns w(W) t Data setup time before write (1) ns su(D-W) t Data hold time after write 0.5 × t ns h(W-D) c(Base) Note: 1. The value is calculated using the formulas below based on the base clock cycles (t ) and c(Base) respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For details on how to set values, refer to the User’s manual. t = t = t = (Tsu(A-R) - 0.5) × t -15 [ns] su(S-ALE) su(A-ALE) w(ALE) c(Base) t = Tw(R) × t -10 [ns] w(R) c(Base) t = t = Tw(W) × t -10 [ns] w(W) su(D-W) c(Base) R01DS0062EJ0130 Rev.1.30 Page 86 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics V = V = 3.3 V CC1 CC2 Switching Characteristics (V =V =3.0to3.6V, V =0V, and T =T , unless otherwise noted) CC1 CC2 SS a opr Table 5.59 Serial Interface Measurement Value Symbol Characteristic Unit Condition Min. Max. td(C-Q) TXDi output delay time Refer to 80 ns th(C-Q) TXDi output hold time Figure 5.6 0 ns Table 5.60 Intelligent I/O Measurement Value Symbol Characteristic Unit Condition Min. Max. td(ISCLK2-TXD) ISTXD2 output delay time Refer to 180 ns th(ISCLK2-RXD) ISTXD2 output hold time Figure 5.6 0 ns R01DS0062EJ0130 Rev.1.30 Page 87 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics MCU Pin to be measured 30 pF Figure 5.6 Switching Characteristic Measurement Circuit t c(X) XIN t w(XH) t w(XL) t r(X) t f(X) Figure 5.7 External Clock Input Timing R01DS0062EJ0130 Rev.1.30 Page 88 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics External bus timing (separate bus) Read cycle t cR t su(S-R) t h(R-S) CS0 to CS3 t su(A-R) t h(R-A) A23 to A0, BC0 and BC1 t w(R) RD t su(D-R) t h(R-D) D15 to D0 Write cycle t cW t su(S-W) t h(W-S) CS0 to CS3 t su(A-W) t h(W-A) A23 to A0, BC0 and BC1 t w(W) WR, WR0 and WR1 t su(D-W) t h(W-D) D15 to D0 Measurement conditions Item V = V = 4.2 to 5.5 V V = V = 3.0 to 3.6 V CC1 CC2 CC1 CC2 Criterion for V IH 2.5 V 1.5 V input voltage V IL 0.8 V 0.5 V Criterion for V OH 2.0 V 2.4 V output voltage V OL 0.8 V 0.5 V Figure 5.8 External Bus Timing for Separate Bus R01DS0062EJ0130 Rev.1.30 Page 89 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics External bus timing (multiplexed bus) Read cycle t cR t su(S-ALE) t h(R-S) CS0 to CS3 t su(A-ALE) t h(R-A) A23 to A8, BC0 and BC1 t w(ALE) t h(ALE-A) ALE t su(A-ALE) t dis(R-A) t su(D-R) t h(R-D) A15/D15 to A0/D0, Address Data BC0/D0 t d(ALE-R) t w(R) t dis(R-D) RD t su(D-R) t h(R-D) D15 to D8 Write cycle t cW t su(S-ALE) t h(W-S) CS0 to CS3 t su(A-ALE) t h(W-A) A23 to A8, BC0 and BC1 t w(ALE) ALE t su(A-ALE) t h(ALE-A) t su(D-W) t h(W-D) A15/D15 to A0/D0, Address Data BC0/D0 t d(ALE-W) t w(W) WR, WR0 and WR1 t su(D-W) t h(W-D) D15 to D8 Measurement conditions Item V C C 1 = V C C 2 = 4.2 to 5.5 V V C C 1 = V C C 2 = 3.0 to 3.6 V Criterion for V IH 2.5 V 1.5 V input voltage V IL 0.8 V 0.5 V Criterion for V OH 2.0 V 2.4 V output voltage V OL 0.8 V 0.5 V Figure 5.9 External Bus Timing for Multiplexed Bus R01DS0062EJ0130 Rev.1.30 Page 90 of 93 Mar 3, 2014

R32C/111 Group 5. Electrical Characteristics t c(TA) t w(TAH) t w(TAL) TAiIN input t c(UP) t w(UPH) t w(UPL) TAiOUT input In event counter mode TAiOUT input (input for increment/ decrement switching) t su(UP-TIN) t h(TIN-UP) TAiIN input (in falling edge counting) TAiIN input (in rising edge counting) t c(TB) t w(TBH) t w(TBL) TBiIN input t c(CK) t w(CKH) t w(CKL) CLKi t d(C-Q) t h(C-Q) TXDi t su(D-C) t h(C-D) RXDi t w(ADL) t w(ADH) ADTRG input t w(INL) t w(INH) INTi input Two CPU clock cycles + Two CPU clock cycles + 300 ns or more 300 ns or more NMI input Figure 5.10 Timing of Peripherals R01DS0062EJ0130 Rev.1.30 Page 91 of 93 Mar 3, 2014

R32C/111 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP100-14x14-0.50 PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV 0.6g HD *1 D 75 51 NOTE) 1. DIMENSIONS "*1" AND "*2" 76 50 DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 *2E HE c1 c ReSfyemrebnocleDMimeinnsionN ion mMillimMetaerxs D 13.9 14.0 14.1 E 13.9 14.0 14.1 Terminal cross section A2 1.4 HD 15.8 16.0 16.2 100 26 ZE HAE 15.8 16.0 116.7.2 1 25 A1 0.05 0.1 0.15 Index mark bp 0.15 0.20 0.25 ZD F b1 0.18 c 0.09 0.145 0.20 S A A2 c1 0.125 c 0° 8° e 0.5 e y S *3 bp x A1 L1L yx 00..0088 ZD 1.0 Detail F ZE 1.0 L 0.35 0.5 0.65 L1 1.0 JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TFLGA100-5.5x5.5-0.50 PTLG0100KA-A 100F0M 0.1g φ b1 φ×M S AB φ b φ×M S AB B S w D w S A A ZD e A e K J H G B F E E D C B A ZE ReferenceDimension in Millimeters ×4 1 2 3 4 5 6 7 8 9 10 Symbol Min Nom Max v y S D 5.5 Index mark Index mark E 5.5 (Laser mark) S v 0.15 w 0.20 A 1.05 e 0.5 b 0.21 0.25 0.29 b1 0.29 0.34 0.39 x 0.08 y 0.10 ZD 0.5 ZE 0.5 R01DS0062EJ0130 Rev.1.30 Page 92 of 93 Mar 3, 2014

R32C/111 Group Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP64-10x10-0.50 PLQP0064KB-A 64P6Q-A / FP-64K / FP-64KV 0.3g HD *1 D 48 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT 49 32 INCLUDE TRIM OFFSET. bp b1 *2E HE c1 c ReSfyemrebnocleDMimiennsioNn ion mMillimMeatexrs D 9.9 10.0 10.1 E 9.9 10.0 10.1 64 17ZE Terminal cross section A2 1.4 HD 11.8 12.0 12.2 1 16 HE 11.8 12.0 12.2 ZD Index mark AA1 0.05 0.1 01.1.75 bp 0.15 0.20 0.25 F b1 0.18 S A A2 c c 0.09 0.145 0.20 c1 0.125 0° 8° e y S *3bp x A1 L1L exy 0.5 00..0088 Detail F ZD 1.25 ZE 1.25 L 0.35 0.5 0.65 L1 1.0 R01DS0062EJ0130 Rev.1.30 Page 93 of 93 Mar 3, 2014

Revision History R32C/111 Group Datasheet Description Rev. Date Page Summary 0.03 Oct 17, 2007 — Initial release 0.30 Aug 19, 2008 — Second edition released — The manual in general •Maximum operating frequency changed from 48 MHz to 50 MHz •Specification of on-chip oscillator disclosed •Microprocessor mode becomes optional •“memory-expanded mode” changed to “memory expansion mode” Chapter 1 1 •“(MCUs)” added to line 1 of 1.1 •Applications in 1.1.1 revised and modified •“Attention Users” below 1.1.1 modified to “Notes to users”; “The specification” in this box changed to “Specifications” 2 •“instructions” in “CPU” of Table 1.1 deleted •Minimum instruction execution time in “CPU” of Table 1.1 changed •Microprocessor mode in CPU” of Table 1.1 changed to optional •“TBD” for “Voltage Detection” in Table 1.1 deleted •“3 circuits” for “Clock” in Table 1.1 changed to “4 circuits” •“Total interrupt vectors” in Table 1.1 changed to “Interrupt vectors” •Trigger sources” for DMA in Table 1.1 modified to “Request sources”; Request sources for “DMA” defined as 51 •Scribal error: “peripheral interrupt sources” for “DMACII” in Table 1.1 corrected to “peripheral interrupt source” 3 •Unit names in Table 1.2 sorted in chapter order •Description for “A/D Converter” in Table 1.2 changed •“Operating frequency” in Table 1.2 changed from “48 MHz” to “50 MHz” •“version N” and “version D” added to “Operating Temperature” in Table 1.2; “optional” deleted •Values for “Current Consumption” in Table 1.2 added 4 •“version N” and “version D” added to Table 1.3 •All “version N”s in Table 1.3 become on planning phase 6 •Figure 1.2 modified 7 •Note 2 for Figure 1.3 modified 8 •Scribal error: “CLK5/” (pin No. 21) in Table 1.4 corrected to “CLK5” 11 •Description for “Connecting pins for decoupling capacitor”, “CNVSS”, and “Debug port” in Table 1.7 modified 12 •Some descriptions for “WR0/WR1/WR/BC0/BC1/RD” of “Bus control pins” in Table 1.8 modified 13, 14 •Functional category items in Tables 1.9 and 1.10 sorted in chapter order; Descriptions modified Chapter 2 — •Descriptions for this chapter modified; Expression “DMAC-related registers”s modified to “DMAC-associated registers”s 15 •“Data register” and “Address register” in Figure 2.1 pluralized; Explanation in Notes 1 and 2 for this figure revised A- 1

Revision History R32C/111 Group Datasheet Description Rev. Date Page Summary 15, 16 •“Interrupt table register” in Figure 2.1 and 2.1.6 changed to “Interrupt vector table base register” 18 •Scribal error: “24 bit” in 2.2.2 corrected to “32 bit” Chapter 3 19 •Descriptions for this chapter and Figure 3.1 modified Chapter 4 20 •“(SFR)” of chapter title changed to “(SFRs)” •Description for initial paragraph of Chapter 4 modified •Reset value for CCR and PBC in Table 4.1 changed 21, 22 •“UARTi Bus Collision Detection Interrupt Control Register” (i = 0 to 6) in Tables 4.2 and 4.3 changed to “UARTi Bus Collision, Start/Stop Condition Detection Interrupt Control Register” • “DMAi interrupt” in Tables 4.2 and 4.3 changed to “DMAi transfer complete interrupt” 22 •Reset value for IIO3IR and IIO8IR to IIO11R in Table 4.3 modified 25 •Scribal error: address “00010Fh” added to Table 4.6 32 •“Upward/Downward Counting Select Register” in Table 4.13 changed to “Increment/Decrement Counting Select Register” 38 •CSOP2 for address 040056h in Table 4.19 deleted •Reset value for CM3 in Table 4.19 changed 43 •“DMAi Source Select Register i” in Table 4.24 changed to “DMAi Request Source Select Register i” Chapter 5 — •This chapter newly added Appendix 1 81 •“Package Dimension” as title changed to “Package Dimensions” 1.10 Sep 17, 2009 — Third edition released — The manual in general •Added 100-pin plastic molded LGA and 80- and 64-pin plastic molded LQFP packages •When new tables/figures are added for 80-/64-pin packages, add the following description: “(for the 100-pin package)” to the title of corresponding current tables/figures Chapter 1. Overview 1 •Added description for 100-pin LGA and 80-/64-pin packages to lines 12 and 13 of 1.1; Added description “a maximum of” to “nine channels of serial interface”; Deleted the whole description of “Notes to users” 2 •Changed minimum RAM size “40” in Table 1.1, to “32” •Modified description for “External Bus Expansion”, to Table 1.1; Moved this unit below “Clock” 3 •Added “(optional)” for IEBus mode for “Intelligent I/O” in Table 1.2 •Modified description for “Flash memory” in Tables 1.2 •Added “100-pin plastic molded TFLGA (PTLG0100KA-A)” to Table 1.2 4-7 •Added Tables 1.3 to 1.6 to provide specifications for 80-/64-pin packages A- 2

Revision History R32C/111 Group Datasheet Description Rev. Date Page Summary 8 •Completed “under development” phase of part numbers R5F64110DFB, R5F64111DFB, R5F64112DFB, R5F64114DFB, R5F64115DFB, and R5F64116DFB in Table 1.7 •Added product information for 100-pin LGA and 80-/64-pin packages to Table 1.7 9 •Added product information for 100-pin LGA and 80-/64-pin packages, and 32-Kbyte RAM to Figure 1.1 •Deleted hyphenation for part number in Figure 1.1 11, 12, •Added Figures 1.3, 1.4, and 1.6 to 1.8 to provide block diagrams and 14, 18, pin assignment for 100-pin LGA and 80-/64-pin packages 21 13 •Changed the order of Notes in Figures 1.5 15-17 •Added pin No. for 100-pin LGA package to Tables 1.8 to 1.10 19, 20, •Added Tables 1.11 to 1.14 to provide pin characteristics for 80-/64-pin 22, 23 packages. 24 •Changed the following expression: “A ceramic resonator or a crystal oscillator” for “Main clock input/output” in Table 1.15, to “A crystal, or a ceramic resonator” 25 •Modified descriptions for HLDA and RDY of “Bus control pins” in Table 1.16 26 •Changed the following expression: “selected” for “Input port” in Table 1.17, to “selectable” •Modified description “TXD2” for TXD0 to TXD8 of “Serial interface” in Table 1.17, to “TXD2 output” 28-30 •Added Tables 1.19 to 1.21 to provide pin definitions and functions for 80-/64-pin packages Chapter 2. CPU — •Made major text modifications to this chapter 33 •Changed the following expression: “a requested interrupt’s priority level” in line 2 of 2.1.8.11, to “the interrupt request level” Chapter 3. Memory 35 •Made major text modifications to this chapter •Changed RAM size “40” in line 7 of this chapter, to “63”, and address “0000A3FFh” in line 8, to “0000FFFFh” •Added descriptions for 32-Kbyte RAM and 128-Kbyte ROM to Figure 3.1 •Changed two “can be”s in Notes 3 and 4 of Figure 3.1, to “becomes”s Chapter 4. SFRs 36 •Changed hexadecimal format of reset values for registers CCR and FMCR in Table 4.1, to binary •Added FEBC3 register to addresses 000010h-000011h in Table 4.1 •Changed FEBC register for addresses 00001Ch-00001Dh, to FEBC0 in Table 4.1 •Modified the following register name in Table 4.1: “Chip-select Boundary (between n and n + 1) Setting Register”, to “Chip-select n and n + 1 Boundary Setting Register” A- 3

Revision History R32C/111 Group Datasheet Description Rev. Date Page Summary 37, 38 •Changed register names associated with “Start/Stop Condition” for BCNiIC in Tables 4.2 and 4.3, to “Start Condition/Stop Condition” 45 •Modified reset values “XXXX XXXXb” and “XXXX 000Xb” for registers U7RB and U8RB in Table 4.10, to “XXXXh” 46 •Changed expression of register name “Xi Register Yi Register” (i = 0 to 15) and register symbol “XiR, YiR” in Table 4.11, to “Xi Register/Yi Register” and “XiR/YiR”, respectively 51 •Changed hexadecimal format of reset values for PDi in Table 4.16, to binary 54 •Modified Note 1 in Table 4.19 55 •Merged addresses 40090h to 40093h in Table 4.20, into previous page •Modified reset values for IFS0 and IFS2 in Table 4.20; Added Notes 1 to 3 for 80-/64-pin packages and IFS7 register 55-57 •Modified the following register name in Tables 4.20 to 4.22: “Port Pi_j Port Function Select Register”, to “Port Pi_j Function Select Register” 59 •Modified register name “DMAi Request Source Select Register 1” in Table 4.24, to “DMAi Request Source Select Register” •Changed register names “Wake-up Interrupt Priority Level Control Register 2” and “Wake-up Interrupt Priority Level Control Register 1” in Table 4.24, to “Wake-up IPL Setting Register 2” and “Wake-up IPL Setting Register 1”, respectively Chapter 5. Electrical Characteristics 60 •Added Notes 2 and 3 for 80-/64-pin packages to Table 5.1 61 •Added specification of “dV /dt” to Table 5.2; Added Notes 2, 4, and CC1 5 for 80-/64-pin packages 62 •Added Note 2 for Table 5.3 63 •Added Note 3 for 80-/64-pin packages to Table 5.4 65 •Modified description “V ”s in Table 5.6, to “V ”s and “V ”s CC CC1 CC2 66 •Added Table 5.7 to provide RAM electrical characteristics •Deleted specification of “t ” from Table 5.8 PS 67 •Deleted measurement condition for power supply circuit timing characteristics in Table 5.9 •Added “Supply voltage for internal logic” to Figure 5.3 and deleted “CPU clock” from the figure •Changed voltage condition for Table 5.11, from “V = V = 3.3 to CC1 CC2 5.5 V” to “V = V = 4.2 to 5.5 V”; Clarified maximum value for CC1 CC2 “Vdet” in Table 5.11; Modified self-consuming current “V ”, to CC “V ” CC1 68 •Changed typical value and maximum value for f in Table 5.12, SO(PLL) to “55” and “80” respectively •Changed the following expressions: “PLL frequency synthesizer stabilization time” in Table 5.12, to “PLL lock time” and “t ”, to OSC(PLL) “t ” LOCK(PLL) •Modified description for Note1 of Table 5.13 A- 4

Revision History R32C/111 Group Datasheet Description Rev. Date Page Summary 70, 82 •Added Notes 1 and 2 for 80-/64-pin packages to Tables 5.15 and 5.38 71, 83 •Deleted ports P7_0, P7_1, and P8_5 for R from Tables 5.16 PULLUP and 5.39; Added Notes 1 and 2 for 80-/64-pin packages 72, 84 •Added “XIN” as “Active” to first, third, and sixth rows of Tables 5.17 and 5.40 •Deleted specification of ICC under condition “Ta = 85°C” from Tables 5.17 and 5.40 73, 85 •Modified minimum value “0.125” for  in Tables 5.18 and 5.41, to AD “0.25”; Added Note 1 for 80-/64-pin packages 75, 87 •Clarified three “TBD”s for external bus timing in Tables 5.21 and 5.44 78 •Corrected a typo “t ” in Table 5.30, to “t ” h(C-Q) h(C-D) 78, 90 •Modified maximum value for t “30” in Tables 5.30 and 5.53, to h(C-D) “80” 3 •Modified minimum value for t in Tables 5.31 and 5.54, to “----------” w(ADH)  AD •Added Tables 5.33 and 5.56 to provide intelligent I/O timing requirements 79, 91 •Changed the third formula of Note 1 in Tables 5.34 and 5.57 80, 92 •Modified minimum value of th(W-D) “0” in Tables 5.35 and 5.58, to “0.5 x t ”; Changed the first formula of Note 1 c(Base) 81, 93 •Modified “Characteristic” for t in Tables 5.36 and 5.59, from h(C-Q) “TXDi hold time” to “TXDi output hold time” •Added Tables 5.37 and 5.60 to provide intelligent switching characteristics 83 •Changed measurement condition for “High level input current” in Table 5.39, from “V = 3 V” to “V = 3.3 V” I I 85 •Added a skipped word “error” after “Differential non-linearity” in Table 5.41 87 •Corrected typos “tw(H),” “tw(L)”, “tr”, and “tf” in Table 5.43, to “tw(XH)”, “t ”, “t ”, and “t ”, respectively w(XL) r(X) f(X) 95 •Changed D15 to D0 output period of write cycle in Figures 5.8 96 •Changed D15 to D8 output period of write cycle in Figures 5.9 Appendix 1 98, 99 •Added figures for 100-pin plastic molded LGA, and 80-/64-pin plastic molded LQFP packages 1.20 Sep 26, 2011 — Fourth edition released The manual in general — •Applied new Renesas templates and formats to the manual •Changed company name to “Renesas Electronics Corporation” and changed related descriptions due to business merger of Renesas Technology Corporation and NEC Electronics Corporation •Modified expressions “version N” and “version D” to “N version” and “D version”, respectively (under Chapters 1 and 5) Chapter 1. Overview — •Modified wording and enhanced description in this chapter A- 5

Revision History R32C/111 Group Datasheet Description Rev. Date Page Summary 2, 4, 6 •Modified the following expressions in Tables 1.1, 1.3, and 1.5: “Main clock oscillator stop/re-oscillation detection” to “Main clock oscillator stop/restart detection”, and “inputs/outputs” to “I/O ports” 3 •Deleted Note 1 from Table 1.2 4, 6 •Deleted memory expansion mode and microprocessor mode from the operating mode of the CPU in Tables 1.3 and 1.5 5, 7 •Deleted Note 2 from Tables 1.4 and 1.6 7 •Corrected package code in Table 1.6 to “PLQP0064KB-A” 8 •Completed “under development” phase of R5F6411EDFN in Table 1.7 10-12 •Deleted Note 1 from Figures 1.2 to 1.4 13 •Corrected a typo “R5_3” for pin number 41 in Figure 1.5 to “P5_3” 13, 18, •Changed order of signals in Figures 1.5, 1.7, and 1.8 21 15, 19, •Changed order of timer pins “TB5IN/TA0IN” in Tables 1.8, 1.11, and 22 1.13 to “TA0IN/TB5IN” 24 •Modified expression “fC” in Table 1.15 to “low speed clocks” Chapter 2. CPU — •Modified wording and enhanced description in this chapter 32 •Corrected a typo “R3R0” in line 3 of 2.1.1 to “R3R1” Chapter 3. Memory — •Modified wording and enhanced description in this chapter Chapter 4. SFRs — •Modified wording and enhanced description in this chapter 41, 42, •Changed hexadecimal format of reset values for registers G1BCR0, 44 G2BCR0, and G0BCR0 in Tables 4.6, 4.7, and 4.9 to binary 41, 44 •Changed register name “Group i Timer Measurement Prescaler Register” in Tables 4.6 and 4.9 to “Group i Time Measurement Prescaler Register” 43 •Modified expression “IE Bus” in Table 4.8 to “IEBus” 46 •Modified expression “XY Control Register” in Table 4.11 to “X-Y Control Register” 48 •Changed register name “UART2 Transmission/Receive Mode Register” and “Increment/Decrement Counting Select Register” in Table 4.13 to “UART2 Transmit/Receive Mode Register” and “Increment/Decrement Select Register”, respectively; Changed hexadecimal format of reset values for registers TABSR, ONSF, and TRGSR to binary 50 •Changed reset value “X00X X000b” for AD0CON2 register in Table 4.15 to “XX0X X000b” 59 •Changed register name “External Interrupt Source Select Register i” in Table 4.24 to “External Interrupt Request Source Select Register i” Chapter 5. Electrical Characteristics — •Modified wording and enhanced description in this chapter •Changed expression “clock period” to “clock cycle time” 61 •Changed format for ports P0 and P1 in Table 5.2 A- 6

Revision History R32C/111 Group Datasheet Description Rev. Date Page Summary 66 •Changed expression “Programming and erasure endurance” in Table 5.8 to “Program and erase cycles”; Changed its unit “times” in the table and Note 1 to “Cycles” 68 •Changed order of descriptions of “t ” and “t ” in Table rec(STOP) rec(WAIT) 5.13 and Figure 5.4 69 •Changed expressions “CS0” and “A23 to A0, BC0 to BC3” in Figure 5.5 to “Chip select” and “Address”, respectively 78, 90 •Corrected “INTi” in title of Tables 5.32 and 5.55 to “INTi” 81, 93 •Added measurement condition to Tables 5.37 and 5.60 Appendix 1. Package Dimensions 98-99 •Added a seating plane to the drawing of package dimension 1.30 Mar 3, 2014 — Fifth edition released — •Deleted description for the 80-pin package Chapter 1. Overview — •Modified wording and enhanced description in this chapter 1 •Modified expression “I2C” in line 9 of 1.1 to “I2C-bus interface” 2, 4 •Modified expressions “calculation transfer” and “chained transfer” in Tables 1.1 and 1.3 to “calculation result transfer” and “chain transfer”, respectively 5 •Deleted N version from the Operating Temperature row in Table 1.4 6 •Deleted products on planning phase from Table 1.5 20, 23 •Modified expression “I2C bus” in Tables 1.13 and 1.16 to “I2C-bus” Chapter 2. CPU — •Modified wording and enhanced description in this chapter Chapter 5. Electrical Characteristics — •Modified wording and enhanced description in this chapter 65, 77 •Deleted TXD4, STXD4, and RTS4 from Tables 5.16 and 5.39 66, 78 •Modified description “Drive power” in Tables 5.17 and 5.40 to “Drive strength” All trademarks and registered trademarks are the property of their respective owners. A- 7

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ⎯ The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product.

Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. 5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Tel: +49-211-6503-0, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333 Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 12F., 234 Teheran-ro, Gangnam-Ku, Seoul, 135-920, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 © 2014 Renesas Electronics Corporation. All rights reserved. Colophon 4.0