Datasheet RL78/L12 R01DS0157EJ0210 Rev.2.10 RENESAS MCU Sep 30, 2016 Integrated LCD controller/driver, True Low Power Platform (as low as 62.5 µA/MHz, and 0.64 µA for RTC + LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications 1. OUTLINE 1.1 Features Ultra-Low Power Technology LCD Controller/Driver • 1.6 V to 5.5 V operation from a single supply • Up to 35 seg x 8 com or 39 seg x 4 com • Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA • Supports capacitor split method, internal voltage boost • Halt (RTC + LVD): 0.64 µA method and resistance division method • Supports snooze • Supports waveform types A and B • Operating: 62.5 µA/MHz • Supports LCD contrast adjustment (16 steps) • LCD operating current (Capacitor split method): 0.12 µA • Supports LCD blinking • LCD operating current (Internal voltage boost method): 0.63 µA (VDD = 3.0 V) Direct Memory Access (DMA) Controller • Up to 2 fully programmable channels • Transfer unit: 8- or 16-bit 16-bit RL78 CPU Core • Delivers 31 DMIPS at maximum operating frequency of Multiple Communication Interfaces 24 MHz • Up to 1 × I2C multi-master • Instruction Execution: 86% of instructions can be • Up to 2 × CSI/SPI (7-, 8-bit) executed in 1 to 2 clock cycles • Up to 1 × UART (7-, 8-, 9-bit) • CISC Architecture (Harvard) with 3-stage pipeline • Up to 1 × LIN • Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1 clock cycle Extended-Function Timers • MAC: 16 x 16 to 32-bit result in 2 clock cycles • Multi-function 16-bit timers: Up to 8 channels • 16-bit barrel shifter for shift & rotate in 1 clock cycle • Real-time clock (RTC): 1 channel (full calendar and • 1-wire on-chip debug function alarm function with watch correction function) • Interval Timer: 12-bit, 1 channel Code Flash Memory • 15 kHz watchdog timer: 1 channel (window function) • Density: 8 KB to 32 KB • Block size: 1 KB Rich Analog • On-chip single voltage flash memory with protection • ADC: Up to 10 channels, 10-bit resolution, 2.1 µs conversion time from block erase/writing • Self-programming with flash shield window function • Supports 1.6 V • Internal reference voltage (1.45 V) • On-chip temperature sensor Data Flash Memory • Data flash with background operation • Data flash size: 2 KB size Safety Features (IEC or UL 60730 compliance) • Erase cycles: 1 Million (typ.) • Flash memory CRC calculation • Erase/programming voltage: 1.8 V to 5.5 V • RAM parity error check • RAM write protection • SFR write protection RAM • 1 KB and 1.5 KB size options • Illegal memory access detection • Supports operands or instructions • Clock frequency detection • Back-up retention in all modes • ADC self-test General Purpose I/O High-speed On-chip Oscillator • 5V tolerant, high-current (up to 20 mA per pin) • 24 MHz with +/− 1% accuracy over voltage (1.8 V to 5.5 • Open-Drain, Internal Pull-up support V) and temperature (−20°C to 85°C) • Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, 8 Operating Ambient Temperature MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz & 1 MHz • TA: −40 °C to +85 °C (A: Consumer applications) • TA: −40 °C to +105 °C (G: Industrial applications) Reset and Supply Management • Power-on reset (POR) monitor/generator Package Type and Pin Count • Low voltage detection (LVD) with 14 setting options From 7mm x 7mm to 12mm x 12mm (Interrupt and/or reset function) QFP: 32, 44, 48, 52, 64 R01DS0157EJ0210 Rev.2.10 Page 1 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE  ROM, RAM capacities Flash ROM Data flash RAM RL78/L12 32 pins 44 pins 48 pins 52 pins 64 pins Note 32 KB 2 KB 1.5 KB R5F10RBC R5F10RFC R5F10RGC R5F10RJC R5F10RLC Note 16 KB 2 KB 1 KB R5F10RBA R5F10RFA R5F10RGA R5F10RJA R5F10RLA 8KB 2 KB 1 KBNote R5F10RB8 R5F10RF8 R5F10RG8 R5F10RJ8 − Note In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash function is used. Remark The functions mounted depend on the product. See 1.6 Outline of Functions. R01DS0157EJ0210 Rev.2.10 Page 2 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.2 List of Part Numbers Figure 1-1 Part Number, Memory Size, and Package of RL78/L12 Part No. R 5 F 1 0 R L C A x x x F B Package type: FP : LQFP, 0.80 mm pitch FA : LQFP, 0.65 mm pitch FB : LQFP, 0.50 mm pitch NB : WQFN, 0.40 mm pitch ROM number (Omitted with blank products) Classification: A : Consumer applications, TA = -40˚C to 85˚C G : Industrial applications, TA = -40˚C to 105˚C ROM capacity: 8 : 8 KB A : 16 KB C : 32 KB Pin count: B : 32-pin F : 44-pin G : 48-pin J : 52-pin L : 64-pin RL78/L12 group Memory type: F : Flash memory Renesas MCU Renesas semiconductor product R01DS0157EJ0210 Rev.2.10 Page 3 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE Pin count Package Fields of Part Number Application Note 32 pins 32-pin plastic LQFP (7 × 7) A R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP G R5F10RB8GFP, R5F10RBAGFP, R5F10RBCGFP 44 pins 44-pin plastic LQFP (10 × 10) A R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP G R5F10RF8GFP, R5F10RFAGFP, R5F10RFCGFP 48 pins 48-pin plastic LQFP (fine pitch) A R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB (7 × 7) G R5F10RG8GFB, R5F10RGAGFB, R5F10RGCGFB 52 pins 52-pin plastic LQFP (10 × 10) A R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA G R5F10RJ8GFA, R5F10RJAGFA, R5F10RJCGFA 64 pins 64-pin plastic WQFN (8 × 8) A R5F10RLAANB, R5F10RLCANB G R5F10RLAGNB, R5F10RLCGNB 64-pin plastic LQFP (fine pitch) R5F10RLAAFB, R5F10RLCAFB A (10 × 10) G R5F10RLAGFB, R5F10RLCGFB 64-pin plastic LQFP (12 × 12) R5F10RLAAFA, R5F10RLCAFA A G R5F10RLAGFA, R5F10RLCGFA Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/L12. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0157EJ0210 Rev.2.10 Page 4 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 32-pin products • 32-pin plastic LQFP (7 × 7) <R> 6 G 4 E G S 1/SESEG5O02/ NTPP2/02/T K01/I1/INT01/TI C0O OM0OM1OM2OM3EG015/S16/SI17/S CCCCSPPP 2423222120191817 P21/ANI1/AVREFM 25 16 P30/TI01/TO01/SEG19 P20/ANI0/AVREFP 26 15 VL4 P14/ANI19/SEG32 27 14 VL2 P13/ANI18/TI00/SEG31 28 RL78/L12 13 VL1 P12/SO00/TXD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02) 29 (Top View) 12 P126/CAPL P11/SI00/RXD0/TOOLRxD/KR1/SEG29/(INTP2) 30 11 P127/CAPH P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1) 31 10 P61/SDAA0/SEG20 P140/TO00/PCLBUZ0/KR3/SEG27 32 9 P60/SCLA0/SEG21 1 2 3 4 5 6 7 8 0T0K1C S D OOLESENTPXCL21/XREGVS VD 0/TR37/I2/EP1 4 1X P P2/ 2 1 P Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0157EJ0210 Rev.2.10 Page 5 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.3.2 44-pin products • 44-pin plastic LQFP (10 × 10) <R> 6 G 4 E G S 01234/SEG05/SEG16/SEG27/SEG3SCK01/INTP1/SESI01/INTP2/SEG5SO01/TI02/TO02/ OMOMOMOMOMOMOMOM15/16/17/ CCCCCCCCPPP 33 32 31 30 29 28 27 26 25 24 23 P21/ANI1/AVREFM 34 22 P32/TI03/TO03/INTP4/SEG17 P20/ANI0/AVREFP 35 21 P31/INTP3/RTC1HZ/SEG18 P143/ANI21/SEG34 36 20 P30/TI01/TO01/SEG19 P142/ANI20/SEG33 37 19 P125/VL3 P14/ANI19/SEG32 38 RL78/L12 18 VL4 P13/ANI18/SEG31 39 17 VL2 P12/SO00/TxD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02) 40 (TopView) 16 VL1 P11/SI00/RxD0/TOOLRxD/KR1/SEG29/(INTP2) 41 15 P126/CAPL P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1) 42 14 P127/CAPH P140/TO00/PCLBUZ0/KR3/SEG27 43 13 P61/SDAA0/SEG20 P141/TI00/PCLBUZ1/SEG26 44 12 P60/SCLA0/SEG21 1 2 3 4 5 6 7 8 9 10 11 ANI17/SEG25P40/TOOL0RESETXT2/EXCLKSP123/XT1P137/INTP022/X2/EXCLKP121/X1REGCVSS VDD P120/ P124/ P1 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0157EJ0210 Rev.2.10 Page 6 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.3.3 48-pin products • 48-pin plastic LQFP (fine pitch) (7 × 7) <R> G6UZ0) OM0OM1OM2OM3OM4/SEG0OM5/SEG1OM6/SEG2OM7/SEG315/SCK01/INTP1/SEG416/SI01/INTP2/SEG517/SO01/TI02/TO02/SE50/INTP5/SEG7/(PCLB CCCCCCCCPPPP 36 35 34 33 32 31 30 29 28 27 26 25 P21/ANI1/AVREFM 37 24 P70/KR0/SEG16 P20/ANI0/AVREFP 38 23 P32/TI03/TO03/INTP4/KR1/SEG17 P144/ANI22/SEG35 39 22 P31/INTP3/RTC1HZ/KR2/SEG18 P143/ANI21/SEG34 40 21 P30/TI01/TO01/KR3/SEG19 P142/ANI20/SEG33 41 20 P125/VL3 P14/ANI19/SEG32 42 RL78/L12 19 VL4 P13/ANI18/SEG31 43 (TopView) 18 VL2 P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02) 44 17 VL1 P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2) 45 16 P126/CAPL P10/SCK00/TI07/TO07/SEG28/(INTP1) 46 15 P127/CAPH P140/TO00/PCLBUZ0/SEG27 47 14 P61/SDAA0/SEG20 P141/TI00/PCLBUZ1/SEG26 48 13 P60/SCLA0/SEG21 1 2 3 4 5 6 7 8 9 10 11 12 P120/ANI17/SEG256/TI04/TO04/SEG24P40/TOOL0RESETP124/XT2/EXCLKSP123/XT1P137/INTP0P122/X2/EXCLKP121/X1REGCVSSVDD 1 NI A 1/ P4 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0157EJ0210 Rev.2.10 Page 7 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.3.4 52-pin products • 52-pin plastic LQFP (10 × 10) <R> OM0 OM1 OM2 OM3 OM4/SEG0 OM5/SEG1 OM6/SEG2 OM7/SEG3 15/SCK01/INTP1/SEG4 16/SI01/INTP2/SEG5 17/SO01/TI02/TO02/SEG6 50/INTP5/SEG7/(PCLBUZ0) 51/TI06/TO06/SEG8 C C C C C C C C P P P P P 39 38 37 36 35 34 33 32 31 30 29 28 27 P21/ANI1/AVREFM 40 26 P71/KR1/SEG15 P20/ANI0/AVREFP 41 25 P70/KR0/SEG16 P145/ANI23/SEG36 42 24 P32/TI03/TO03/INTP4/SEG17 P144/ANI22/SEG35 43 23 P31/INTP3/RTC1HZ/KR2/SEG18 P143/ANI21/SEG34 44 22 P30/TI01/TO01/KR3/SEG19 P142/ANI20/SEG33 45 21 P125/VL3 RL78/L12 P14/ANI19/SEG32 46 20 VL4 (TopView) P13/ANI18/SEG31 47 19 VL2 P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02) 48 18 VL1 P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2) 49 17 P126/CAPL P10/SCK00/TI07/TO07/SEG28/(INTP1) 50 16 P127/CAPH P140/TO00/PCLBUZ0/SEG27 51 15 P61/SDAA0/SEG20 P141/TI00/PCLBUZ1/SEG26 52 14 P60/SCLA0/SEG21 1 2 3 4 5 6 7 8 9 10 11 12 13 P120/ANI17/SEG25 6/TI04/TO04/SEG24 2/TI05/TO05/SEG23 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 1 4 NI P A 1/ P4 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0157EJ0210 Rev.2.10 Page 8 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.3.5 64-pin products • 64-pin plastic WQFN (8 × 8) <R> )2 P 1) T OM0 OM1OM2 OM3OM4/SEG0 OM5/SEG1 OM6/SEG2OM7/SEG3 15/SCK01/INTP1/SEG416/SI01/INTP2/SEG5 17/SO01/TI02/TO02/SEG6 50/INTP5/SEG7/(PCLBUZ0)51/TI06/TO06/SEG8 52/INTP6/SEG953/TI07/TO07/SEG10/(INTP 54/SEG11/(TI02)/(TO02)/(IN exposed die pad C CC CC C CC PP P PP PP P P21/ANI1/AVREFM P74/SEG12 P20/ANI0/AVREFP P73/KR3/SEG13 P130 P72/KR2/SEG14 P147/SEG38 P71/KR1/SEG15 P146/SEG37 P70/KR0/SEG16 P145/ANI23/SEG36 P32/TI03/TO03/INTP4/SEG17 P144/ANI22/SEG35 P31/INTP3/RTC1HZ/SEG18 P143/ANI21/SEG34 RL78/L12 P30/TI01/TO01/SEG19 P142/ANI20/SEG33 (TopView) P125/VL3 P14/ANI19/SEG32 VL4 P13/ANI18/SEG31 VL2 P12/SO00/TxD0/TOOLTxD/SEG30 VL1 P11/SI00/RxD0/TOOLRxD/SEG29 P126/CAPL P10/SCK00/SEG28 P127/CAPH P140/TO00/PCLBUZ0/SEG27/(INTP6) P61/SDAA0/SEG20 P141/TI00/PCLBUZ1/SEG26/(INTP7) P60/SCLA0/SEG21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P120/ANI17/SEG256/TI04/TO04/SEG242/TI05/TO05/SEG23P43/INTP7/SEG22P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS VDD EVDD 14 NIP A 1/ P4 Cautions 1. Make EVSS pin the same potential as VSS pin. 2. Make VDD pin the same potential as EVDD pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD pins and connect the VSS and EVSS pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0157EJ0210 Rev.2.10 Page 9 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE • 64-pin plastic LQFP (fine pitch) (10 × 10) • 64-pin plastic LQFP (12 × 12) <R> )2 P 1) T OM0 OM1OM2 OM3OM4/SEG0 OM5/SEG1 OM6/SEG2OM7/SEG3 15/SCK01/INTP1/SEG416/SI01/INTP2/SEG5 17/SO01/TI02/TO02/SEG6 50/INTP5/SEG7/(PCLBUZ0)51/TI06/TO06/SEG8 52/INTP6/SEG953/TI07/TO07/SEG10/(INTP 54/SEG11/(TI02)/(TO02)/(IN C CC CC C CC PP P PP PP P P21/ANI1/AVREFM P74/SEG12 P20/ANI0/AVREFP P73/KR3/SEG13 P130 P72/KR2/SEG14 P147/SEG38 P71/KR1/SEG15 P146/SEG37 P70/KR0/SEG16 P145/ANI23/SEG36 P32/TI03/TO03/INTP4/SEG17 P144/ANI22/SEG35 P31/INTP3/RTC1HZ/SEG18 P143/ANI21/SEG34 RL78/L12 P30/TI01/TO01/SEG19 P142/ANI20/SEG33 (TopView) P125/VL3 P14/ANI19/SEG32 VL4 P13/ANI18/SEG31 VL2 P12/SO00/TxD0/TOOLTxD/SEG30 VL1 P11/SI00/RxD0/TOOLRxD/SEG29 P126/CAPL P10/SCK00/SEG28 P127/CAPH P140/TO00/PCLBUZ0/SEG27/(INTP6) P61/SDAA0/SEG20 P141/TI00/PCLBUZ1/SEG26/(INTP7) P60/SCLA0/SEG21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P120/ANI17/SEG256/TI04/TO04/SEG242/TI05/TO05/SEG23P43/INTP7/SEG22P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS VDD EVDD 14 NIP A 1/ P4 Cautions 1. Make EVSS pin the same potential as VSS pin. 2. Make VDD pin the same potential as EVDD pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD pins and connect the VSS and EVSS pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01DS0157EJ0210 Rev.2.10 Page 10 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.4 Pin Identification ANI0, ANI1, P130, P137: Port 13 ANI16 to ANI23: Analog Input P140 to P147: Port 14 AVREFM: Analog Reference PCLBUZ0, PCLBUZ1: Programmable Clock Voltage Minus Output/Buzzer Output AVREFP: Analog Reference REGC: Regulator Capacitance Voltage Plus RESET: Reset CAPH, CAPL: Capacitor for LCD RTC1HZ: Real-time Clock Correction Clock COM0 to COM7, (1 Hz) Output EVDD: Power Supply for Port RxD0: Receive Data EVSS: Ground for Port SCK00, SCK01: Serial Clock Input/Output EXCLK: External Clock Input SCLA0: Serial Clock Input/Output (Main System Clock) SDAA0: Serial Data Input/Output EXCLKS: External Clock Input SEG0 to SEG38: LCD Segment Output (Subsystem Clock) SI00, SI01: Serial Data Input INTP0 to INTP7: Interrupt Request From SO00, SO01: Serial Data Output Peripheral TI00 to TI07: Timer Input KR0 to KR3: Key Return TO00 to TO07: Timer Output P10 to P17: Port 1 TOOL0: Data Input/Output for Tool P20, P21: Port 2 TOOLRxD, TOOLTxD: Data Input/Output for External Device P30 to P32: Port 3 TxD0: Transmit Data P40 to P43: Port 4 VDD: Power Supply P50 to P54: Port 5 VL1 to VL4: LCD Power Supply P60, P61: Port 6 VSS: Ground P70 to P74: Port 7 X1, X2: Crystal Oscillator (Main System Clock) P120 to P127: Port 12 XT1, XT2: Crystal Oscillator (Subsystem Clock) R01DS0157EJ0210 Rev.2.10 Page 11 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.5 Block Diagram 1.5.1 32-pin products TIMER ARRAY UNIT0 (8ch) TI00/P13 ch0 TO00/P140 PORT 1 8 P10 to P17 TI01/TO01/P30 ch1 TI02/TO02/P17 PORT 2 2 P20, P21 ch2 (TI02/TO02/P12) ch3 PORT 3 P30 2 ANI0/P20, ANI1/P21 ch4 2 ANI18/P13, ANI19/P14 PORT 4 P40 A/D CONVERTER ch5 AVREFP/P20 ch6 AVREFM/P21 PORT 6 2 P60, P61 TI07/TO07/P10 ch7 REAL-TIME 2 P126, P127 CLOCK PORT 12 2 P121, P122 LOOWN--SCPHEIPED 12- BITT IIMNETRERVAL RCLP7U8 CODE FLASH MEMORY PORT 13 P137 OSCILLATOR CORE DATA FLASH MEMORY WINDOW PORT 14 P140 WATCHDOG TIMER BUZZER OUTPUT PCLBUZ0/P140 SEG0, SEG4 to SEG6, CLOCK OUTPUT SEG19 to SEG21, 13 LCD CONTROL CONTROLLER/ SEG27 to SEG32 DRIVER RAM 3 KR0/P12 to KR2/P10 COM0 to COM3 4 KEY RETURN VL1, VL2, VL4 RAM SPACE KR3/P140 FOR LCD DATA CAPH CAPL POWER ON RESET/ POR/LVD VOLTAGE SERIAL ARRAY DETECTOR CONTROL UNIT0 (2ch) RxD0/P11 VDD VSS TOOLRxD/P11, TxD0/P12 UART0 TOOLTxD/P12 RESET CONTROL SCK00/P10 SI00/P11 CSI00 SO00/P12 ON-CHIP DEBUG TOOL0/P40 DIRECT MEMORY SCK01/P15 ACCESS CONTROL SI01/P16 CSI01 SO01/P17 SYSTEM RESET CONTROL X1/P121 X2/EXCLK/P122 SDAA0/P61 SERIAL HIGH-SPEED SCLA0/P60 INTERFACE IICA0 OSOCNIL-CLHAITPOR MULTIPLIER& DIVIDER, VOLTAGE REGC MULITIPLY- CRC REGULATOR ACCUMULATOR INTP0/P137 INTP1/P15(INTP1/P10), 2 INTP2/P16(INTP2/P11) BCD INTERRUPT CONTROL ADJUSTMENT Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR) R01DS0157EJ0210 Rev.2.10 Page 12 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.5.2 44-pin products TIMER ARRAY UNIT0 (8ch) TI00/P141 ch0 TO00/P140 PORT 1 8 P10 to P17 TI01/TO01/P30 ch1 TI02/TO02/P17 PORT 2 2 P20, P21 ch2 (TI02/TO02/P12) TI03/TO03/P32 ch3 PORT 3 3 P30 to P32 2 ANI0/P20, ANI1/P21 ch4 3 ANI17/P120, ANI18/P13, PORT 4 P40 ANI19/P14 ch5 A/D CONVERTER 2 ANI20/P142, ANI21/P143 AVREFP/P20 ch6 AVREFM/P21 PORT 6 2 P60, P61 TI07/TO07/P10 ch7 RTC1HZ/P31 REAL-TIME PORT 12 4 P120, P125 to P127 CLOCK 4 P121 to P124 LOOWN--SCPHEIPED 12- BIT INTERVAL RCLP7U8 CODE FLASH MEMORY PORT 13 P137 OSCILLATOR TIMER CORE DATA FLASH MEMORY PORT 14 4 P140 to P143 WINDOW WATCHDOG TIMER BUZZER OUTPUT 2 PCLBUZ0/P140, SEG0 to SEG6, CLOCK OUTPUT PCLBUZ1/P141 SEG17 to SEG21, 22 LCD CONTROL SEG25 to SEG34 CONTROLLER/ COM0 to COM7 8 DRIVER RAM KEY RETURN 3 KR0/P12 to KR2/P10 VL1 to VL4 RAM SPACE KR3/P140 CAPH FOR LCD DATA CAPL POWER ON RESET/ POR/LVD VOLTAGE SERIAL ARRAY DETECTOR CONTROL UNIT0 (2ch) RxD0/P11 VDD VSS TOOLRxD/P11, TxD0/P12 UART0 TOOLTxD/P12 RESET CONTROL SCK00/P10 SI00/P11 CSI00 SO00/P12 ON-CHIP DEBUG TOOL0/P40 DIRECT MEMORY SCK01/P15 ACCESS CONTROL SI01/P16 CSI01 SO01/P17 SYSTEM RESET CONTROL X1/P121 X2/EXCLK/P122 SDAA0/P61 SERIAL HIGH-SPEED SCLA0/P60 INTERFACE IICA0 OSOCNIL-CLHAITPOR XXTT12//PE1X2C3LKS/P124 MULTIPLIER& DIVIDER, VOLTAGE REGC MULITIPLY- CRC REGULATOR ACCUMULATOR INTP0/P137 INTP1/P15(INTP1/P10), 2 INTP2/P16(INTP2/P11) BCD INTERRUPT INTP3/P31, ADJUSTMENT CONTROL 2 INTP4/P32 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR) R01DS0157EJ0210 Rev.2.10 Page 13 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.5.3 48-pin products TIMER ARRAY UNIT0 (8ch) TI00/P141 ch0 TO00/P140 PORT 1 8 P10 to P17 TI01/TO01/P30 ch1 TI02/TO02/P17 PORT 2 2 P20, P21 ch2 (TI02/TO02/P12) TI03/TO03/P32 ch3 PORT 3 3 P30 to P32 2 ANI0/P20, ANI1/P21 TI04/TO04/P41 ch4 4 ANI16/P41, ANI17/P120, PORT 4 2 P40, P41 ANI18/P13, ANI19/P14 ch5 A/D CONVERTER 3 ANI20/P142 to ANI22/P144 PORT 5 P50 AVREFP/P20 ch6 AVREFM/P21 PORT 6 2 P60, P61 TI07/TO07/P10 ch7 PORT 7 P70 RTC1HZ/P31 REAL-TIME PORT 12 4 P120, P125 to P127 CLOCK 4 P121 to P124 RL78 CODE FLASH MEMORY LOW-SPEED 12- BIT INTERVAL CPU PORT 13 P137 ON-CHIP OSCILLATOR TIMER CORE DATA FLASH MEMORY PORT 14 5 P140 to P144 WINDOW WATCHDOG TIMER BUZZER OUTPUT PCLBUZ0/P140 2 (PCLBUZ0/P50), CLOCK OUTPUT PCLBUZ1/P141 SEG0 to SEG7, SEG16 to SEG21, 26 LCD CONTROL SEG24 to SEG35 CONTROLLER/ RAM KR0/P70 COM0 to COM7 8 DRIVER KEY RETURN 3 KR1/P32 to KR3/P30 VL1 to VL4 RAM SPACE CAPH FOR LCD DATA CAPL POWER ON RESET/ POR/LVD VOLTAGE CONTROL SERIAL ARRAY DETECTOR UNIT0 (2ch) RTxxDD00//PP1112 UART0 VDD VSS TTOOOOLLRTxxDD//PP1121, RESET CONTROL SCK00/P10 SI00/P11 CSI00 SO00/P12 ON-CHIP DEBUG TOOL0/P40 DIRECT MEMORY SCK01/P15 ACCESS CONTROL SI01/P16 CSI01 SO01/P17 SYSTEM RESET CONTROL X1/P121 X2/EXCLK/P122 HIGH-SPEED SDAA0/P61 SERIAL ON-CHIP XT1/P123 SCLA0/P60 INTERFACE IICA0 OSCILLATOR XT2/EXCLKS/P124 MULTIPLIER& VOLTAGE DIVIDER, REGULATOR REGC MULITIPLY- CRC ACCUMULATOR INTP0/P137 INTP1/P15(INTP1/P10), 2 INTP2/P16(INTP2/P11) BCD INTERRUPT INTP3/P31, ADJUSTMENT CONTROL 2 INTP4/P32 INTP5/P50 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR) R01DS0157EJ0210 Rev.2.10 Page 14 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.5.4 52-pin products TIMER ARRAY UNIT0 (8ch) TI00/P141 ch0 TO00/P140 PORT 1 8 P10 to P17 TI01/TO01/P30 ch1 TI02/TO02/P17 PORT 2 2 P20, P21 ch2 (TI02/TO02/P12) TI03/TO03/P32 ch3 PORT 3 3 P30 to P32 2 ANI0/P20, ANI1/P21 TI04/TO04/P41 ch4 4 ANI16/P41, ANI17/P120, PORT 4 3 P40 to P42 ANI18/P13, ANI19/P14 A/D CONVERTER 4 ANI20/P142 to ANI23/P145 TI05/TO05/P42 ch5 PORT 5 2 P50, P51 AVREFP/P20 TI06/TO06/P51 ch6 AVREFM/P21 PORT 6 2 P60, P61 TI07/TO07/P10 ch7 PORT 7 2 P70, P71 RTC1HZ/P31 REAL-TIME 4 P120, P125 to P127 PORT 12 CLOCK 4 P121 to P124 LOOWN--SCPHEIPED 12- BIT INTERVAL RCLP7U8 CODE FLASH MEMORY PORT 13 P137 OSCILLATOR TIMER CORE DATA FLASH MEMORY WINDOW PORT 14 6 P140 to P145 WATCHDOG TIMER BUZZER OUTPUT PCLBUZ0/P140 2 (PCLBUZ0/P50), SEG0 to SEG8, CLOCK OUTPUT PCLBUZ1/P141 SEG15 to SEG21, 30 LCD CONTROL SEG23 to SEG36 CONTROLLER/ RAM 2 KR0/P70, KR1/P71 COM0 to COM7 8 DRIVER KEY RETURN 2 KR2/P31, KR3/P30 VL1 to VL4 RAM SPACE CAPH FOR LCD DATA CAPL POWER ON RESET/ POR/LVD VOLTAGE SERIAL ARRAY DETECTOR CONTROL UNIT0 (2ch) RxD0/P11 VDD VSS TOOLRxD/P11, TxD0/P12 UART0 TOOLTxD/P12 RESET CONTROL SCK00/P10 SO10/P17 CSI00 SI00/P11 SO00/P12 ON-CHIP DEBUG TOOL0/P40 DIRECT MEMORY SCK01/P15 ACCESS CONTROL CRC SI01/P16 CSI01 SYSTEM RESET CONTROL X1/P121 X2/EXCLK/P122 HIGH-SPEED SDAA0/P61 SERIAL ON-CHIP XT1/P123 SCLA0/P60 INTERFACE IICA0 OSCILLATOR XT2/EXCLKS/P124 MULTIPLIER& VOLTAGE DIVIDER, REGULATOR REGC MULITIPLY- ACCUMULATOR INTP0/P137 INTP1/P15(INTP1/P10), 2 INTP2/P16(INTP2/P11) BCD INTERRUPT INTP3/P31, ADJUSTMENT CONTROL 2 INTP4/P32 INTP5/P50 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR) R01DS0157EJ0210 Rev.2.10 Page 15 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.5.5 64-pin products TIMER ARRAY UNIT0 (8ch) TI00/P141 ch0 TO00/P140 PORT 1 8 P10 to P17 TI01/TO01/P30 ch1 TI02/TO02/P17 PORT 2 2 P20, P21 ch2 (TI02/TO02/P54) TI03/TO03/P32 ch3 PORT 3 3 P30 to P32 2 ANI0/P20, ANI1/P21 TI04/TO04/P41 ch4 4 ANI16/P41, ANI17/P120, PORT 4 4 P40 to P43 ANI18/P13, ANI19/P14 A/D CONVERTER 4 ANI20/P142 to ANI23/P145 TI05/TO05/P42 ch5 PORT 5 5 P50 to P54 AVREFP/P20 TI06/TO06/P51 ch6 AVREFM/P21 PORT 6 2 P60, P61 TI07/TO07/P53 ch7 PORT 7 5 P70 to P74 RTC1HZ/P31 REAL-TIME 4 P120, P125 to P127 CLOCK PORT 12 4 P121 to P124 CODE FLASH MEMORY LOW-SPEED 12- BIT INTERVAL RL78 PORT 13 P130 ON-CHIP CPU P137 TIMER OSCILLATOR CORE DATA FLASH MEMORY PORT 14 8 P140 to P147 WINDOW WATCHDOG TIMER BUZZER OUTPUT PCLBUZ0/P140 2 (PCLBUZ0/P50), CLOCK OUTPUT PCLBUZ1/P141 SEG0 to SEG38 39 LCD CONTROL CONTROLLER/ COM0 to COM7 8 DRIVER RAM KR0/P70 to VL1 to VL4 RAM SPACE KEY RETURN 4 KR3/P73 CAPH FOR LCD DATA CAPL POWER ON RESET/ POR/LVD SERIAL ARRAY VOLTAGE CONTROL UNIT0 (2ch) DETECTOR RTxxDD00//PP1112 UART0 EVVDDD,D EVVSSS,S TTOOOOLLRTxxDD//PP1121, SCK00/P10 RESET CONTROL SI00/P11 CSI00 SO00/P12 ON-CHIP DEBUG TOOL0/P40 SCK01/P15 DIRECT MEMORY CRC SI01/P16 CSI01 ACCESS CONTROL SO01/P17 SYSTEM RESET CONTROL X1/P121 SDAA0/P61 SERIAL HIGH-SPEED X2/EXCLK/P122 SCLA0/P60 INTERFACE IICA0 ON-CHIP XT1/P123 OSCILLATOR XT2/EXCLKS/P124 MULTIPLIER& DIVIDER, VOLTAGE MULITIPLY- REGULATOR REGC ACCUMULATOR INTP0/P137 INTP1/P15(INTP1/P53), 2 INTP2/P16(INTP2/P54) BCD INTERRUPT INTP3/P31, ADJUSTMENT CONTROL 2 INTP4/P32 INTP5/P50 INTP6/P52(INTP6/P140) INTP7/P43(INTP7/P141) Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR) R01DS0157EJ0210 Rev.2.10 Page 16 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE 1.6 Outline of Functions Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 32-pin 44-pin 48-pin 52-pin 64-pin R5F10RBx R5F10RFx R5F10RGx R5F10RJx R5F10RLx Code flash memory (KB) 8 to 32 8 to 32 8 to 32 8 to 32 16, 32 Data flash memory (KB) 2 2 2 2 2 RAM (KB) 1, 1.5 Note 1 1, 1.5 Note 1 1, 1.5 Note 1 1, 1.5 Note 1 1, 1.5Note 1 Memory space 1 MB Main High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) <R> system HS (high-speed main) operation: 1 to 20 MHz (VDD = 2.7 to 5.5 V), clock HS (high-speed main) operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (low-speed main) operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (low-voltage main) operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) High-speed on-chip HS (high-speed main) operation: 1 to 24 MHz (VDD = 2.7 to 5.5 V), oscillator clock HS (high-speed main) operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (low-speed main) operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (low-voltage main) operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock − XT1 (crystal) oscillation , external subsystem clock input (EXCLKS) 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V Low-speed on-chip oscillator clock Internal oscillation 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.04167 μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation) 0.05 μs (High-speed system clock: fMX = 20 MHz operation) 30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits) • Adder and subtractor/logical operation (8/16 bits) • Multiplication (8 bits × 8 bits) • Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total number of I/O port pins and 28 40 44 48 58 pins dedicated to drive an LCD I/O Total 20 29 33 37 47 port CMOS I/O 15 22 26 30 39 CMOS input 3 5 5 5 5 CMOS output − − − − 1 N-ch open-drain I/O 2 2 2 2 2 (EVDD tolerance) Pins dedicated to drive an LCD 8 11 11 11 11 LCD controller/driver Internal voltage boosting method, capacitor split method, and external resistance division method are switchable. Segment signal output 13 22 (18) Note 2 26 (22) Note 2 30 (26) Note 2 39 (35) Note 2 Common signal output 4 4 (8) Note 2 Notes 1. In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash function is used. 2. The values in parentheses are the number of signal outputs when 8 com is used. R01DS0157EJ0210 Rev.2.10 Page 17 of 131 Sep 30, 2016

RL78/L12 1. OUTLINE (2/2) Item 32-pin 44-pin 48-pin 52-pin 64-pin R5F10RBx R5F10RFx R5F10RGx R5F10RJx R5F10RLx Timer 16-bit timer 8 channels 8 channels (with 1 channel remote control output function) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer (IT) 1 channel Timer output 4 channels 5 channels 6 channels 8 channels (PWM outputs: 7 Note 1) (PWM outputs: (PWM outputs: (PWM outputs: 3 Note 1) 4 Note 1) 5 Note 1) RTC output − 1 • 1 Hz (subsystem clock: fSUB = 32.768 kHz or ) Clock output/buzzer output 1 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 4 channels 7 channels 9 channels 10 channels 10 channels Serial interface • CSI: 2 channel/UART (LIN-bus supported): 1 channel I2C bus 1 channel 1 channel 1 channel 1 channel 1 channel Multiplier and divider/multiply- • 16 bits × 16 bits = 32 bits (Unsigned or signed) accumulator • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored interrupt Internal 23 23 23 23 23 sources External 4 6 7 7 9 Key interrupt 4 Reset • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note 2 • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.04 V • Power-down-reset: 1.50 ±0.04 V Voltage detector • Rising edge : 1.67 V to 4.06 V (14 stages) • Falling edge : 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = −40 to +85 °C Notes 1. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). 2. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0157EJ0210 Rev.2.10 Page 18 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2. ELECTRICAL SPECIFICATIONS (A, G: T = -40 to +85°C) A This chapter describes the electrical specifications for the products "A: Consumer applications (TA = -40 to +85°C)" and "G: Industrial applications (with TA = -40 to +85°C)". Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EVDD, or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. R01DS0157EJ0210 Rev.2.10 Page 19 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/3) Parameter Symbols Conditions Ratings Unit Supply voltage VDD VDD = EVDD −0.5 to +6.5 V EVDD VDD = EVDD −0.5 to +6.5 V EVSS −0.5 to +0.3 V REGC pin input voltage VIREGC REGC −0.3 to +2.8 V and −0.3 to VDD + 0.3Note 1 Input voltage VI1 P10 to P17, P30 to P32, P40 to P43, P50 to P54, −0.3 to EVDD +0.3 V P70 to P74, P120, P125 to P127,P140 to P147 and −0.3 to VDD + 0.3Note 2 VI2 P60, P61 (N-ch open-drain) −0.3 to EVDD +0.3 V and −0.3 to VDD + 0.3Note 2 VI3 P20, P21, P121 to P124, P137, EXCLK, −0.3 to VDD + 0.3Note 2 V EXCLKS, RESET Output voltage VO1 P10 to P17, P30 to P32, P40 to P43, −0.3 to EVDD + 0.3 V P50 to P54, P60, P61, P70 to P74, P120, and −0.3 to VDD + 0.3Note 2 P125 to P127, P130, P140 to P147 VO2 P20, P21 −0.3 to VDD + 0.3 Note 2 V Analog input voltage VAI1 ANI16 to ANI23 −0.3 to EVDD + 0.3 and V −0.3 to AVREF(+) + 0.3 Notes 2, 3 VAI2 ANI0, ANI1 −0.3 to VDD + 0.3 and V −0.3 to AVREF(+) + 0.3 Notes 2, 3 Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF(+) : + side reference voltage of the A/D converter. 3. VSS : Reference voltage R01DS0157EJ0210 Rev.2.10 Page 20 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Absolute Maximum Ratings (TA = 25°C) (2/3) Parameter Symbols Conditions Ratings Unit LCD voltage VL1 VL1 voltageNote 1 −0.3 to +2.8 V and −0.3 to VL4 + 0.3 VL2 VL2 voltageNote 1 −0.3 to VL4 + 0.3 Note 2 V VL3 VL3 voltageNote 1 −0.3 to VL4 + 0.3 Note 2 V VL4 VL4 voltageNote 1 −0.3 to +6.5 V VLCAP CAPL, CAPH voltageNote 1 −0.3 to VL4 + 0.3 Note 2 V VLOUT COM0 to COM7, External resistance division −0.3 to VDD + 0.3 Note 2 V SEG0 to method SEG38, Capacitor split method −0.3 to VDD + 0.3 Note 2 output voltage Internal voltage boosting method −0.3 to VL4 + 0.3 Note 2 Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does not mean that applying voltage to these pins is recommended. When using the internal voltage boosting method or capacitance split method, connect these pins to VSS via a capacitor (0.47 μ F ± 30%) and connect a capacitor (0.47 μ F ± 30%) between the CAPL and CAPH pins. 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark VSS : Reference voltage R01DS0157EJ0210 Rev.2.10 Page 21 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Absolute Maximum Ratings (TA = 25°C) (3/3) Parameter Symbols Conditions Ratings Unit Output current, high IOH1 Per pin P10 to P17, P30 to P32, −40 mA P40 to P43, P50 to P54, P70 to P74, P120, P125 to P127, P130, P140 to P147 Total of all pins P10 to P14, P40 to P43, P120, −70 mA −170 mA P130, P140 to P147 P15 to P17, P30 to P32, −100 mA P50 to P54, P70 to P74, P125 to P127 IOH2 Per pin P20, P21 −0.5 mA Total of all pins −1 mA Output current, low IOL1 Per pin P10 to P17, P30 to P32, 40 mA P40 to P43, P50 to P54, P60, P61, P70 to P74, P120, P125 to P127, P130, P140 to P147 Total of all pins P10 to P14, P40 to P43, P120, 70 mA 170 mA P130, P140 to P147 P15 to P17, P30 to P32, 100 mA P50 to P54, P60, P61, P70 to P74, P125 to P127 IOL2 Per pin P20, P21 1 mA Total of all pins 2 mA Operating ambient TA In normal operation mode −40 to +85 °C temperature In flash memory programming mode Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 22 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.2 Oscillator Characteristics 2.2.1 X1, XT1 oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation frequency Ceramic resonator/ 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz (fX)Note crystal resonator 2.4 V ≤ VDD ≤ 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.7 V 1.0 8.0 MHz 1.6 V ≤ VDD <1.8 V 1.0 4.0 MHz XT1 clock oscillation Crystal resonator 32 32.768 35 kHz frequency (fXT)Note Note Indicates only permissible oscillator frequency ranges. Refer to 2.4 AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. 2.2.2 On-chip oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator fIH 1 24 MHz clock frequency Notes 1, 2 High-speed on-chip oscillator −20 to +85°C 1.8 V ≤ VDD ≤ 5.5 V −1 +1 % clock frequency accuracy 1.6 V ≤ VDD < 1.8 V −5 +5 % −40 to −20°C 1.8 V ≤ VDD ≤ 5.5 V −1.5 +1.5 % 1.6 V ≤ VDD < 1.8 V −5.5 +5.5 % Low-speed on-chip oscillator fIL 15 kHz clock frequency Low-speed on-chip oscillator −15 +15 % clock frequency accuracy Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to 2.4 AC Characteristics for instruction execution time. R01DS0157EJ0210 Rev.2.10 Page 23 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.3 DC Characteristics 2.3.1 Pin characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, IOH1 Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54, −10.0 mA highNote 1 P70 to P74, P120, P125 to P127, P130, P140 to P147 Note 2 Total of P10 to P14, P40 to P43, P120, 4.0 V ≤ EVDD ≤ 5.5 V −40.0 mA P130, P140 to P147 2.7 V ≤ EVDD < 4.0 V −8.0 mA (When duty = 70% Note 3) 1.8 V ≤ EVDD < 2.7 V −4.0 mA 1.6 V ≤ EVDD < 1.8 V −2.0 mA Total of P15 to P17, P30 to P32, 4.0 V ≤ EVDD ≤ 5.5 V −60.0 mA P50 to P54, P70 to P74, P125 to P127 2.7 V ≤ EVDD < 4.0 V −15.0 mA (When duty = 70% Note 3) 1.8 V ≤ EVDD < 2.7 V −8.0 mA 1.6 V ≤ EVDD < 1.8 V −4.0 mA Total of all pins −100.0 mA (When duty = 70%Note 3) IOH2 P20, P21 Per pin −0.1 mA Total of all pins 1.6 V ≤ VDD ≤ 5.5 V −0.2 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD and EVDD pins to an output pin. 2. Do not exceed the total current value. 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (I OH × 0.7)/(n × 0.01) <Example> Where n = 80% and IOH = −40.0 mA Total output current of pins = (−40.0 × 0.7)/(80 × 0.01) ≅ −35.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 24 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, IOL1 Per pin for P10 to P17, P30 to P32, P40 to P43, 20.0 mA lowNote 1 P50 to P54, P70 to P74, P120, P125 to P127, P130, Note 2 P140 to P147 Per pin for P60, P61 15.0 Note 2 mA Total of P10 to P14, P40 to P43, 4.0 V ≤ EVDD ≤ 5.5 V 70.0 mA P120, P130, P140 to P147 2.7 V ≤ EVDD < 4.0 V 15.0 mA (When duty = 70% Note 3) 1.8 V ≤ EVDD < 2.7 V 9.0 mA 1.6 V ≤ EVDD < 1.8 V 4.5 mA Total of P15 to P17, P30 to P32, 4.0 V ≤ EVDD ≤ 5.5 V 80.0 mA P50 to P54, P60, P61, P70 to P74, 2.7 V ≤ EVDD < 4.0 V 35.0 mA P125 to P127 (When duty = 70% Note 3) 1.8 V ≤ EVDD < 2.7 V 20.0 mA 1.6 V ≤ EVDD < 1.8 V 10.0 mA Total of all pins 150.0 mA (When duty = 70% Note 3) IOL2 P20, P21 Per pin 0.4 mA Total of all pins 1.6 V ≤ VDD ≤ 5.5 V 0.8 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD and EVDD pins to an output pin. 2. Do not exceed the total current value. 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (I OH × 0.7)/(n × 0.01) <Example> Where n = 80% and IOL = 70.0 mA Total output current of pins = (70.0 × 0.7)/(80 × 0.01) ≅ 61.25 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 25 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (3/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, VIH1 P10 to P17, P30 to P32, P40 to P43, Normal input buffer 0.8EVDD EVDD V high P50 to P54, P70 to P74, P120, P125 to P127, P140 to P147 VIH2 P10, P11, P15, P16 TTL input buffer 2.2 EVDD V 4.0 V ≤ EVDD ≤ 5.5 V TTL input buffer 2.0 EVDD V 3.3 V ≤ EVDD < 4.0 V TTL input buffer 1.50 EVDD V 1.6 V ≤ EVDD < 3.3 V VIH3 P20, P21 0.7VDD VDD V VIH4 P60, P61 0.7EVDD EVDD V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V Input voltage, VIL1 P10 to P17, P30 to P32, P40 to P43, Normal input buffer 0 0.2EVDD V low P50 to P54, P70 to P74, P120, P125 to P127, P140 to P147 VIL2 P10, P11, P15, P16 TTL input buffer 0 0.8 V 4.0 V ≤ EVDD ≤ 5.5 V TTL input buffer 0 0.5 V 3.3 V ≤ EVDD < 4.0 V TTL input buffer 0 0.32 V 1.6 V ≤ EVDD < 3.3 V VIL3 P20, P21 0 0.3VDD V VIL4 P60, P61 0 0.3EVDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Caution The maximum value of VIH of P10, P12, P15, P17 is EVDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 26 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (4/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, VOH1 P10 to P17, P30 to P32, P40 to P43, 4.0 V ≤ EVDD ≤ 5.5 V, EVDD−1.5 V high P50 to P54, P70 to P74, P120, IOH1 = −10 mA P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD ≤ 5.5 V, EVDD−0.7 V IOH1 = −3.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, EVDD−0.6 V IOH1 = −2.0 mA 1.8 V ≤ EVDD ≤ 5.5 V, EVDD−0.5 V IOH1 = −1.5 mA 1.6 V ≤ EVDD ≤ 5.5 V, EVDD−0.5 V IOH1 = −1.0 mA VOH2 P20, P21 1.6 V ≤ VDD ≤ 5.5 V, VDD−0.5 V IOH2 = −100 μ A Output voltage, VOL1 P10 to P17, P30 to P32, P40 to P43, 4.0 V ≤ EVDD ≤ 5.5 V, 1.3 V low P50 to P54, P70 to P74, P120, IOL1 = 20 mA P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD ≤ 5.5 V, 0.7 V IOL1 = 8.5 mA 2.7 V ≤ EVDD ≤ 5.5 V, 0.6 V IOL1 = 3.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL1 = 1.5 mA 1.8 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL1 = 0.6 mA 1.6 V ≤ EVDD < 5.5 V, 0.4 V IOL1 = 0.3 mA VOL2 P20, P21 1.6 V ≤ VDD ≤ 5.5 V, 0.4 V IOL2 = 400 μ A VOL3 P60, P61 4.0 V ≤ EVDD ≤ 5.5 V, 2.0 V IOL3 = 15.0 mA 4.0 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL3 = 5.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL3 = 3.0 mA 1.8 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL3 = 2.0 mA 1.6 V ≤ EVDD < 5.5 V, 0.4 V IOL3 = 1.0 mA Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 27 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage ILIH1 P10 to P17, P30 to P32, VI = EVDD 1 μA current, high P40 to P43, P50 to P54, P60, P61, P70 to P74, P120, P125 to P127, P140 to P147 ILIH2 P20, P21, P137, RESET VI = VDD 1 μA ILIH3 P121 to P124 VI = VDD In input port or 1 μA (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input In resonator 10 μA connection Input leakage ILIL1 P10 to P17, P30 to P32, VI = EVSS −1 μA current, low P40 to P43, P50 to P54, P60, P61, P70 to P74, P120, P125 to P127, P140 to P147 ILIL2 P20, P21, P137, RESET VI = VSS −1 μA ILIL3 P121 to P124 VI = VSS In input port or −1 μA (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input In resonator −10 μA connection On-chip pll-up RU1 VI = EVSS SEGxx port resistance 2.4 V ≤ EVDD = VDD ≤ 5.5 V 10 20 100 kΩ 1.6 V ≤ EVDD = VDD < 2.4 V 10 30 100 kΩ RU2 Ports other than above 10 20 100 kΩ (Except for P60, P61, and P130) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 28 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.3.2 Supply current characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply IDD1 Operating HS (high- fIH = 24 MHzNote 3 Basic VDD = 5.0 V 1.5 mA current mode speed main) operation Note 1 modeNote 5 Normal VVDDDD == 35..00 VV 31..35 5. 0 mmAA operation VDD = 3.0 V 3.3 5.0 mA fIH = 16 MHzNote 3 Normal VDD = 5.0 V 2.5 3.7 mA operation VDD = 3.0 V 2.5 3.7 mA LS (low-speed fIH = 8 MHzNote 3 Normal VDD = 3.0 V 1.2 1.8 mA main) modeNote operation 5 VDD = 2.0 V 1.2 1.8 mA LV (low- fIH = 4 MHzNote 3 Normal VDD = 3.0 V 1.2 1.7 mA voltage main) operation modeNote 5 VDD = 2.0 V 1.2 1.7 mA HS (high- fMX = 20 MHzNote 2, Normal Square wave input 2.8 4.4 mA smpoedeedN omte a5 in) VDD = 5.0 V operation Resonator connection 3.0 4.6 mA fMX = 20 MHzNote 2, Normal Square wave input 2.8 4.4 mA VDD = 3.0 V operation Resonator connection 3.0 4.6 mA fMX = 10 MHzNote 2, Normal Square wave input 1.8 2.6 mA VDD = 5.0 V operation Resonator connection 1.8 2.6 mA fMX = 10 MHzNote 2, Normal Square wave input 1.8 2.6 mA VDD = 3.0 V operation Resonator connection 1.8 2.6 mA LS (low-speed fMX = 8 MHzNote 2, Normal Square wave input 1.1 1.7 mA 5m ain) modeNote VDD = 3.0 V operation Resonator connection 1.1 1.7 mA fMX = 8 MHzNote 2, Normal Square wave input 1.1 1.7 mA VDD = 2.0 V operation Resonator connection 1.1 1.7 mA Subsystem fSUB = 32.768 kHzNote Normal Square wave input 3.5 4.9 μA clock 4 operation Resonator connection 3.6 5.0 μA operation TA = −40°C fSUB = 32.768 kHzNote Normal Square wave input 3.6 4.9 μA 4 operation Resonator connection 3.7 5.0 μA TA = +25°C fSUB = 32.768 kHzNote Normal Square wave input 3.7 5.5 μA 4 operation Resonator connection 3.8 5.6 μA TA = +50°C fSUB = 32.768 kHzNote Normal Square wave input 3.8 6.3 μA 4 operation Resonator connection 3.9 6.4 μA TA = +70°C fSUB = 32.768 kHzNote Normal Square wave input 4.1 7.7 μA 4 operation Resonator connection 4.2 7.8 μA TA = +85°C (Notes and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 29 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, watchdog timer, and LCD controller/driver. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0157EJ0210 Rev.2.10 Page 30 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply IDD2 HALT HS (high- fIH = 24 MHz Note 4 VDD = 5.0 V 0.44 1.28 mA current Note 2 mode speed main) Note 1 mode Note 7 VDD = 3.0 V 0.44 1.28 mA fIH = 16 MHz Note 4 VDD = 5.0 V 0.40 1.00 mA VDD = 3.0 V 0.40 1.00 mA LS (low- fIH = 8 MHz Note 4 VDD = 3.0 V 260 530 μA smpoedeed N motea 7i n) VDD = 2.0 V 260 530 μA LV (low- fIH = 4 MHz Note 4 VDD = 3.0 V 420 640 μA vmoaltina)g me ode VDD = 2.0 V 420 640 μA Note 7 HS (high- fMX = 20 MHzNote 3, Square wave input 0.28 1.00 mA speed main) mode Note 7 VDD = 5.0 V Resonator connection 0.45 1.17 mA fMX = 20 MHzNote 3, Square wave input 0.28 1.00 mA VDD = 3.0 V Resonator connection 0.45 1.17 mA fMX = 10 MHzNote 3, Square wave input 0.19 0.60 mA VDD = 5.0 V Resonator connection 0.26 0.67 mA fMX = 10 MHzNote 3, Square wave input 0.19 0.60 mA VDD = 3.0 V Resonator connection 0.26 0.67 mA LS (low- fMX = 8 MHzNote 3, Square wave input 95 330 μA smpoedeed N motea 7i n) VDD = 3.0 V Resonator connection 145 380 μA fMX = 8 MHzNote 3, Square wave input 95 330 μA VDD = 2.0 V Resonator connection 145 380 μA Subsystem fSUB = 32.768 kHzNote 5 Square wave input 0.31 0.57 μA clock TA = −40°C Resonator connection 0.50 0.76 μA operation fSUB = 32.768 kHzNote 5 Square wave input 0.37 0.57 μA TA = +25°C Resonator connection 0.56 0.76 μA fSUB = 32.768 kHzNote 5 Square wave input 0.46 1.17 μA TA = +50°C Resonator connection 0.65 1.36 μA fSUB = 32.768 kHzNote 5 Square wave input 0.57 1.97 μA TA = +70°C Resonator connection 0.76 2.16 μA fSUB = 32.768 kHzNote 5 Square wave input 0.85 3.37 μA TA = +85°C Resonator connection 1.04 3.56 μA IDD3Note 6 STOP TA = −40°C 0.17 0.50 μA mode Note 8 TA = +25°C 0.23 0.50 μA TA = +50°C 0.32 1.10 μA TA = +70°C 0.43 1.90 μA TA = +85°C 0.71 3.30 μA (Notes and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 31 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer, watchdog timer, and LCD controller/driver. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0157EJ0210 Rev.2.10 Page 32 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (3/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on- IFIL Note 1 0.20 μA chip oscillator operating current RTC operating IRTC fMAIN is stopped 0.08 μA current Notes 1, 2, 3 12-bit interval IIT 0.08 μA timer current Notes 1, 2, 4 Watchdog timer IWDT fIL = 15 kHz 0.24 μA operating Notes 1, 2, 5 current A/D converter IADC When conversion Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA operating Notes 1, 6 at maximum speed Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA current A/D converter IADREF Note 1 75.0 μA reference voltage current Temperature ITMPS Note 1 75.0 μA sensor operating current LVD operating ILVD 0.08 μA current Notes 1, 7 Self- IFSP 2.50 12.20 mA programming Notes 1, 9 operating current BGO operating IBGO 2.00 12.20 mA current Notes 1, 8 LCD operating ILCD1 External resistance division method VDD = EVDD = 5.0 V 0.04 0.20 μA current Notes 11, 12 VL4 = 5.0 V ILCD2 Note 11 Internal voltage boosting method VDD = EVDD = 5.0 V 1.12 3.70 μA VL4 = 5.1 V (VLCD = 12H) VDD = EVDD = 3.0 V 0.63 2.20 μA VL4 = 3.0 V (VLCD = 04H) ILCD3 Note 11 Capacitor split method VDD = EVDD = 3.0 V 0.12 0.50 μA VL4 = 3.0 V SNOOZE ISNOZ Note 1 ADC operation The mode is performed Note 10 0.50 0.60 mA operating The A/D conversion operations are 1.20 1.44 mA current performed, Low voltage mode, AVREFP = VDD = 3.0 V CSI/UART operation 0.70 0.84 mA (Notes and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 33 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10. For shift time to the SNOOZE mod. 11. Current flowing only to the LCD controller/driver. The supply current value of the RL78 microcontrollers is the sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1 or IDD2) when the LCD controller/driver operates in an operation mode or HALT mode. Not including the current that flows through the LCD panel. The TYP. value and MAX. value are following conditions. • When fSUB is selected for system clock, LCD clock = 128 Hz (LCDC0 = 07H) • 4-Time-Slice, 1/3 Bias Method 12. Not including the current that flows through the external divider resistor when the external resistance division method is used. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25°C R01DS0157EJ0210 Rev.2.10 Page 34 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.4 AC Characteristics 2.4.1 Basic operation (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum TCY Main HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 μs instruction execution time) scylosctek m(f MAIN) main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 1 μs operation LV (low voltage 1.6 V ≤ VDD ≤ 5.5 V 0.25 1 μs main) mode LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V 0.125 1 μs main) mode Subsystem clock (fSUB) 1.8 V ≤ VDD ≤ 5.5 V 28.5 30.5 31.3 μs operation In the self HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 μs programmin main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 1 μs g mode LV (low voltage 1.8 V ≤ VDD ≤ 5.5 V 0.25 1 μs main) mode LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V 0.125 1 μs main) mode External main system clock fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz frequency 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.4 V 1.0 8.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz fEXS 32 35 kHz External main system clock input tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns high-level width, low-level width 2.4 V ≤ VDD < 2.7 V 30 ns 1.8 V ≤ VDD < 2.4 V 60 ns 1.6 V ≤ VDD < 1.8 V 120 ns tEXHS, 13.7 μs tEXLS TI00 to TI07 input high-level tTIH, 1/fMCK+10 ns width, low-level width tTIL TO00 to TO07 output frequency fTO HS (high-speed 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz main) mode 2.7 V ≤ EVDD < 4.0 V 8 MHz 2.4 V ≤ EVDD < 2.7 V 4 MHz LS (low-speed 1.8 V ≤ EVDD ≤ 5.5 V 4 MHz main) mode LV (low voltage 1.6 V ≤ EVDD ≤ 5.5 V 2 MHz main) mode PCLBUZ0, PCLBUZ1 output fPCL HS (high-speed 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz frequency main) mode 2.7 V ≤ EVDD < 4.0 V 8 MHz 2.4 V ≤ EVDD < 2.7 V 4 MHz LS (low-speed 1.8 V ≤ EVDD ≤ 5.5 V 4 MHz main) mode LV (low-voltage 1.8 V ≤ EVDD ≤ 5.5 V 4 MHz main) mode 1.6 V ≤ EVDD < 1.8 V 2 MHz Interrupt input high-level width, tINTH, INTP0 1.6 V ≤ VDD ≤ 5.5 V 1 μs low-level width tINTL INTP1 to INTP7 1.6 V ≤ EVDD ≤ 5.5 V 1 μs Key interrupt input low-level width tKR KR0 to KR3 1.8 V ≤ EVDD ≤ 5.5 V 250 ns 1.6 V ≤ EVDD < 1.8 V 1 μs RESET low-level width tRSL 10 μs Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7)) R01DS0157EJ0210 Rev.2.10 Page 35 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 When the high-speed on-chip oscillator clock is selected µs] During self programming [Y When high-speed system clock is selected C T e m e ti cl y C 0.1 0.0625 0.04167 0.01 0 1.0 2.0 3.0 4.0 5.0 6.0 2.4 2.7 5.5 Supply voltage VDD [V] TCY vs VDD (LS (low-speed main) mode) 10 s] 1.0 µ [CY When the high-speed on-chip oscillator clock is selected T e During self programming m e ti When high-speed system clock is selected cl y C 0.125 0.1 0.01 5.5 0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 Supply voltage VDD [V] R01DS0157EJ0210 Rev.2.10 Page 36 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) TCY vs VDD (LV (low-voltage main) mode) 10 s] 1.0 µ [Y When the high-speed on-chip oscillator clock is selected C T e During self programming m e ti When high-speed system clock is selected cl Cy 0.25 0.1 0.01 5.5 0 1.0 2.0 3.0 4.0 5.0 6.0 1.61.8 Supply voltage VDD [V] AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX/ 1/fEXS tEXL/ tEXH/ tEXLS tEXHS EXCLK/EXCLKS R01DS0157EJ0210 Rev.2.10 Page 37 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) TI/TO Timing tTIL tTIH TI00 to TI07 1/fTO TO00 to TO07 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR3 RESET Input Timing tRSL RESET R01DS0157EJ0210 Rev.2.10 Page 38 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH Test points VIH/VOH VIL/VOL VIL/VOL 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. Transfer rate Note 1 2.4 V ≤ EVDD = VDD ≤ 5.5 V fMCK/6 fMCK/6 fMCK/6 bps Theoretical value of the 4.0 1.3 0.6 Mbps maximum transfer rate fMCK = fCLK Note 2 1.8 V ≤ EVDD = VDD ≤ 5.5 V fMCK/6 fMCK/6 bps Theoretical value of the 1.3 0.6 Mbps maximum transfer rate fMCK = fCLK Note 2 1.6 V ≤ EVDD = VDD ≤ 5.5 V fMCK/6 bps Theoretical value of the 0.6 Mbps maximum transfer rate fMCK = fCLK Note 2 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0157EJ0210 Rev.2.10 Page 39 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) UART mode connection diagram (during communication at same potential) TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. q: UART number (q = 0), g: PIM and POM number (g = 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0157EJ0210 Rev.2.10 Page 40 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 2.7 V ≤ EVDD ≤ 5.5 V 167 500 1000 ns Note 1 Note 1 Note 1 2.4 V ≤ EVDD ≤ 5.5 V 250 500 1000 ns Note 1 Note 1 Note 1 1.8 V ≤ EVDD ≤ 5.5 V 500 1000 ns Note 1 Note 1 1.6 V ≤ EVDD ≤ 5.5 V 1000 ns Note 1 SCKp high-/low-level width tKH1, 4.0 V ≤ EVDD ≤ 5.5 V tKCY1/2 tKCY1/2 tKCY1/2 ns tKL1 − 12 − 50 − 50 2.7 V ≤ EVDD ≤ 5.5 V tKCY1/2 tKCY1/2 tKCY1/2 ns − 18 − 50 − 50 2.4 V ≤ EVDD ≤ 5.5 V tKCY1/2 tKCY1/2 tKCY1/2 ns − 38 − 50 − 50 1.8 V ≤ EVDD ≤ 5.5 V tKCY1/2 tKCY1/2 ns − 50 − 50 1.6 V ≤ EVDD ≤ 5.5 V tKCY1/2 ns − 100 SIp setup time (to SCKp↑) tSIK1 2.7 V ≤ EVDD ≤ 5.5 V 44 110 110 ns Note 2 2.4 V ≤ EVDD ≤ 5.5 V 75 110 110 ns 1.8 V ≤ EVDD ≤ 5.5 V 110 110 ns 1.6 V ≤ EVDD ≤ 5.5 V 220 ns SIp hold time (from SCKp↑) tKSI1 2.4 V ≤ EVDD ≤ 5.5 V 19 19 19 ns Note 3 1.8 V ≤ EVDD ≤ 5.5 V 19 19 1.6 V ≤ EVDD ≤ 5.5 V 19 Delay time from SCKp↓ to tKSO1 C = 30 pF 2.4 V ≤ EVDD ≤ 5.5 V 25 25 25 ns SOp output Note 4 Note 5 1.8 V ≤ EVDD ≤ 5.5 V 25 25 1.6 V ≤ EVDD ≤ 5.5 V 25 Notes 1. For CSI00, set a cycle of 2/fMCK or longer. For CSI01, set a cycle of 4/fMCK or longer. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). (Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 41 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (1/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle timeNote tKCY2 4.0 V ≤ EVDD ≤ 5.5 V 20 MHz < fMCK 8/fMCK ns 5 fMCK ≤ 20 MHz 6/fMCK 6/fMCK 6/fMCK ns 2.7 V ≤ EVDD < 4.0 V 16 MHz < fMCK 8/fMCK ns fMCK ≤ 16 MHz 6/fMCK 6/fMCK 6/fMCK ns 2.4 V ≤ EVDD ≤ 5.5 V 6/fMCK 6/fMCK 6/fMCK ns and 500 1.8 V ≤ EVDD < 2.4 V 6/fMCK 6/fMCK ns 1.6 V ≤ EVDD < 1.8 V 6/fMCK ns SCKp high-/low- tKH2, 4.0 V ≤ EVDD ≤ 5.5 V tKCY2/2 tKCY2/2 tKCY2/2 ns level width tKL2 − 7 − 7 − 7 2.7 V ≤ EVDD < 4.0 V tKCY2/2 tKCY2/2 tKCY2/2 ns − 8 − 8 − 8 2.4 V ≤ EVDD < 2.7 V tKCY2/2 tKCY2/2 tKCY2/2 ns − 18 − 18 − 18 1.8 V ≤ EVDD < 2.4 V tKCY2/2 tKCY2/2 ns − 18 − 18 1.6 V ≤ EVDD < 1.8 V tKCY2/2 ns − 66 SIp setup time tSIK2 2.7 V ≤ EVDD ≤ 5.5 V 1/fMCK 1/fMCK 1/fMCK ns (to SCKp↑)Note 1 + 20 + 30 + 30 2.4 V ≤ EVDD < 2.7 V 1/fMCK 1/fMCK 1/fMCK + 30 + 30 + 30 1.8 V ≤ EVDD < 2.4 V 1/fMCK 1/fMCK ns + 30 + 30 1.6 V ≤ EVDD < 1.8 V 1/fMCK ns + 40 SIp hold time tKSI2 2.4 V ≤ EVDD ≤ 5.5 V 1/fMCK 1/fMCK 1/fMCK ns (from SCKp↑)Note 2 + 31 + 31 + 31 1.8 V ≤ EVDD < 2.4 V 1/fMCK 1/fMCK ns + 31 + 31 1.6 V ≤ EVDD < 1.8 V 1/fMCK ns + 250 (Notes, Caution, and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 42 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (2/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS LS (low-LV (low- Unit Para Symbol Conditions (high- speed voltage meter speed main) main) main) Mode Mode Mode Delay time from tKSO2 C = 30 pF Note 4 4.0 V ≤ EVDD ≤ 5.5 V 2/fMCK 2/fMCK 2/fMCK ns SCKp↓ to SOp + 44 + 110 + 110 output Note 3 2.7 V ≤ EVDD < 4.0 V 2/fMCK 2/fMCK 2/fMCK ns + 44 + 110 + 110 2.4 V ≤ EVDD < 2.7 V 2/fMCK 2/fMCK 2/fMCK ns + 75 + 110 + 110 1.8 V ≤ EVDD < 2.4 V 2/fMCK 2/fMCK ns + 110 + 110 1.6 V ≤ EVDD < 1.8 V 2/fMCK ns + 220 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. 5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM number (g = 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0157EJ0210 Rev.2.10 Page 43 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CSI mode connection diagram (during communication at same potential) SCKp SCK RL78 SIp SO User's device microcontroller SOp SI CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 tKSI1, 2 SIp Input data tKSO1, 2 SOp Output data CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 tKSI1, 2 SIp Input data tKSO1, 2 SOp Output data Remarks 1. p: CSI number (p = 00, 01) 2. m: Unit number, n: Channel number (mn = 00, 01) R01DS0157EJ0210 Rev.2.10 Page 44 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. Transfer rate Reception 4.0 V ≤ EVDD ≤ 5.5 V, fMCK/6 fMCK/6 fMCK/6 bps 2.7 V ≤ Vb ≤ 4.0 V Note 1 Note 1 Note 1 Theoretical value of the 4.0 1.3 0.6 Mbps maximum transfer rate fMCK = fCLK Note 3 2.7 V ≤ EVDD < 4.0 V, fMCK/6 fMCK/6 fMCK/6 bps 2.3 V ≤ Vb ≤ 2.7 V Note 1 Note 1 Note 1 Theoretical value of the 4.0 1.3 0.6 Mbps maximum transfer rate fMCK = fCLK Note 3 2.4 V ≤ EVDD < 3.3 V, fMCK/6 fMCK/6 fMCK/6 bps 1.6 V ≤ Vb ≤ 2.0 V Note 1 Note 1 Note 1 Theoretical value of the 4.0 1.3 0.6 Mbps maximum transfer rate fMCK = fCLK Note 3 1.8 V ≤ EVDD < 3.3 V, fMCK/6 fMCK/6 bps 1.6 V ≤ Vb ≤ 2.0 V Notes 1, 2 Notes 1, 2 Theoretical value of the 1.3 0.6 Mbps maximum transfer rate fMCK = fCLK Note 3 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. Use it with EVDD ≥ Vb. 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32-pin to 52- pin products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01) R01DS0157EJ0210 Rev.2.10 Page 45 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. Transfer rate Transmissio 4.0 V ≤ EVDD ≤ 5.5 V, Note 1 Note 1 Note 1 bps n 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the 2.8Note 2 2.8Note 2 2.8Note 2 Mbps maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.7 V ≤ EVDD < 4.0 V, Note 3 Note 3 Note 3 bps 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the 1.2Note 4 1.2Note 4 1.2Note 4 Mbps maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ Vb = 2.3 V 2.4 V ≤ EVDD < 3.3 V, Note 6 Note 6 Note 6 bps 1.6 V ≤ Vb ≤ 2.0 V Theoretical value of the 0.43Note 7 0.43Note 7 0.43Note 7 Mbps maximum transfer rate Cb = 50 pF, Rb = 5.5 kΩ Vb = 1.6 V 1.8 V ≤ EVDD < 3.3 V, Notes Notes bps 1.6 V ≤ Vb ≤ 2.0 V 5, 6 5, 6 Theoretical value of the 0.43Note 7 0.43Note 7 Mbps maximum transfer rate Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V 1 Maximum transfer rate = [bps] 2.2 {−Cb × Rb × ln (1 − Vb )} × 3 Transfe r1 r ate × 2 − {−Cb × Rb × ln (1 − 2V.b2 )} Baud rate error (theoretical value) = × 100 [%] 1 ( ) × Number of transferred bits Transfer rate * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. R01DS0157EJ0210 Rev.2.10 Page 46 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V 1 Maximum transfer rate = [bps] 2.0 {−Cb × Rb × ln (1 − Vb )} × 3 Transfe r1 r ate × 2 − {−Cb × Rb × ln (1 − 2V.0b )} Baud rate error (theoretical value) = × 100 [%] 1 ( ) × Number of transferred bits Transfer rate * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. Use it with EVDD ≥ Vb. 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ EVDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V 1 Maximum transfer rate = [bps] 1.5 {−Cb × Rb × ln (1 − Vb )} × 3 Transfe r1 r ate × 2 − {−Cb × Rb × ln (1 − 1V.b5 )} Baud rate error (theoretical value) = × 100 [%] 1 ( ) × Number of transferred bits Transfer rate * This value is the theoretical value of the relative difference between the transmission and reception sides. 7. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32-pin to 52- pin products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0157EJ0210 Rev.2.10 Page 47 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0, 1), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0157EJ0210 Rev.2.10 Page 48 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (5) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = −40 to +85°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- Unit speed main) main) Mode voltage main) Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD ≤ 5.5 V, 200 1150 1150 ns 2.7 V ≤ Vb ≤ 4.0 V, Note 1 Note 1 Note 1 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 300 1150 1150 ns 2.3 V ≤ Vb ≤ 2.7 V, Note 1 Note 1 Note 1 Cb = 20 pF, Rb = 2.7 kΩ SCKp high-level width tKH1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 20 pF, Rb = 1.4 kΩ − 50 − 50 − 50 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 20 pF, Rb = 2.7 kΩ − 120 − 120 − 120 SCKp low-level width tKL1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 20 pF, Rb = 1.4 kΩ − 7 − 50 − 50 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 20 pF, Rb = 2.7 kΩ − 10 − 50 − 50 SIp setup time tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 58 479 479 ns (to SCKp↑) Note 2 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 121 479 479 ns Cb = 20 pF, Rb = 2.7 kΩ SIp hold time tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 10 10 10 ns (from SCKp↑) Note 2 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 10 10 10 ns Cb = 20 pF, Rb = 2.7 kΩ Delay time from SCKp↓ to tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 60 60 60 ns SOp output Note 2 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 130 130 130 ns Cb = 20 pF, Rb = 2.7 kΩ SIp setup time tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 23 110 110 ns (to SCKp↓) Note 3 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 33 110 110 ns Cb = 20 pF, Rb = 2.7 kΩ SIp hold time tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 10 10 10 ns (from SCKp↓) Note 3 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 10 10 10 ns Cb = 20 pF, Rb = 2.7 kΩ Delay time from SCKp↑ to tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 10 10 10 ns SOp output Note 3 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 10 10 10 ns Cb = 20 pF, Rb = 2.7 kΩ (Notes, Caution and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 49 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. For CSI00, set a cycle of 2/fMCK or longer. For CSI01, set a cycle of 4/fMCK or longer. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to 52- pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01) R01DS0157EJ0210 Rev.2.10 Page 50 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- Unit speed main) main) Mode voltage main) Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD ≤ 5.5 V, 300 1150 1150 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 500 1150 1150 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1150 1150 1150 ns 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 1.8 V ≤ EVDD < 3.3 V, 1150 1150 ns 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ SCKp high-level width tKH1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 30 pF, Rb = 1.4 kΩ − 75 − 75 − 75 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 30 pF, Rb = 2.7 kΩ − 170 − 170 − 170 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 30 pF, Rb = 5.5 kΩ − 458 − 458 − 458 1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, tKCY1/2 tKCY1/2 ns Cb = 30 pF, Rb = 5.5 kΩ − 458 − 458 SCKp low-level width tKL1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 30 pF, Rb = 1.4 kΩ − 12 − 50 − 50 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 30 pF, Rb = 2.7 kΩ − 18 − 50 − 50 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 tKCY1/2 tKCY1/2 ns Cb = 30 pF, Rb = 5.5 kΩ − 50 − 50 − 50 1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, tKCY1/2 tKCY1/2 ns Cb = 30 pF, Rb = 5.5 kΩ − 50 − 50 Note Use it with EVDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to 52- pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0157EJ0210 Rev.2.10 Page 51 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low- LV (low- Unit speed main) speed main) voltage main) Mode Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. SIp setup time tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 81 479 479 ns (to SCKp↑) Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 177 479 479 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 479 479 479 ns Cb = 30 pF, Rb = 5.5 kΩ 1.8 V ≤ EVDD < 3.3 V, 479 479 ns 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ SIp hold time tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 19 19 19 ns (from SCKp↑) Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 19 19 19 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 19 19 19 ns Cb = 30 pF, Rb = 5.5 kΩ 1.8 V ≤ EVDD < 3.3 V, 19 19 ns 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ Delay time from SCKp↓ to tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 100 100 100 ns SOp output Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 195 195 195 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 483 483 483 ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD < 3.3 V, 483 483 ns 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ SIp setup time tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 44 110 110 ns (to SCKp↓) Note 2 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 44 110 110 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 110 110 110 ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD < 3.3 V, 110 110 ns 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. Use it with EVDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to 52- pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0157EJ0210 Rev.2.10 Page 52 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low- LV (low- Unit speed main) speed main) voltage main) Mode Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. SIp hold time tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 19 19 19 ns (from SCKp↓) Note 2 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 19 19 19 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 19 19 19 ns Cb = 30 pF, Rb = 5.5 kΩ 1.8 V ≤ EVDD < 3.3 V, 19 19 ns 1.6 V ≤ Vb ≤ 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 kΩ Delay time from SCKp↑ to tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 25 25 25 ns SOp output Note 2 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 25 25 25 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 25 25 25 ns Cb = 30 pF, Rb = 5.5 kΩ 1.8 V ≤ EVDD < 3.3 V, 25 25 ns 1.6 V ≤ Vb ≤ 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 kΩ Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. Use it with EVDD ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to 52- pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0157EJ0210 Rev.2.10 Page 53 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CSI mode connection diagram (during communication at different potential) <Master> Vb Vb Rb Rb SCKp SCK RL78 SIp SO User's device microcontroller SOp SI Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01) R01DS0157EJ0210 Rev.2.10 Page 54 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 tKSI1 SIp Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKH1 tKL1 SCKp tSIK1 tKSI1 SIp Input data tKSO1 SOp Output data Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) R01DS0157EJ0210 Rev.2.10 Page 55 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/2) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- Unit speed main) main) mode voltage main) mode mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD ≤ 5.5 V, 20 MHz < fMCK ≤ 24 MHz 12/fMCK ns 2.7 V ≤ Vb ≤ 4.0 V 8 MHz < fMCK ≤ 20 MHz 10/fMCK ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/fMCK ns fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 2.7 V ≤ EVDD < 4.0 V, 20 MHz < fMCK ≤ 24 MHz 16/fMCK ns 2.3 V ≤ Vb ≤ 2.7 V 16 MHz < fMCK ≤ 20 MHz 14/fMCK ns 8 MHz < fMCK ≤ 16 MHz 12/fMCK ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/fMCK ns fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 2.4 V ≤ EVDD < 3.3 V, 20 MHz < fMCK ≤ 24 MHz 36/fMCK ns 1.6 V ≤ Vb ≤ 2.0 V 16 MHz < fMCK ≤ 20 MHz 32/fMCK ns 8 MHz < fMCK ≤ 16 MHz 26/fMCK ns 4 MHz < fMCK ≤ 8 MHz 16/fMCK 16/fMCK ns fMCK ≤ 4 MHz 10/fMCK 10/fMCK 10/fMCK ns 1.8 V ≤ EVDD < 3.3 V, 4 MHz < fMCK ≤ 8 MHz 16/fMCK ns 1.6 V ≤ Vb ≤ 2.0 V Note 2 fMCK ≤ 4 MHz 10/fMCK 10/fMCK ns SCKp high-/low-level tKH2, 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 tKCY2/2 tKCY2/2 ns width tKL2 − 12 − 50 − 50 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 tKCY2/2 tKCY2/2 ns − 18 − 50 − 50 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V tKCY2/2 tKCY2/2 tKCY2/2 ns − 50 − 50 − 50 1.8 V ≤ EVDD < 3.3 V, tKCY2/2 tKCY2/2 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2 − 50 − 50 SIp setup time tSIK2 4.0 V ≤ EVDD < 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 1/fMCK + 1/fMCK + ns (to SCKp↑) Note 3 20 30 30 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 1/fMCK + 1/fMCK + ns 20 30 30 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V 1/fMCK + 1/fMCK + 1/fMCK + ns 30 30 30 1.8 V ≤ EVDD < 3.3 V, 1/fMCK + 1/fMCK + ns 1.6 V ≤ Vb ≤ 2.0 V Note 2 30 30 SIp hold time tKSI2 4.0 V ≤ EVDD < 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 1/fMCK + 1/fMCK + ns (from SCKp↑) Note 4 31 31 31 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 1/fMCK + 1/fMCK + ns 31 31 31 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V 1/fMCK + 1/fMCK + 1/fMCK + ns 31 31 31 1.8 V ≤ EVDD < 3.3 V, 1/fMCK + 1/fMCK + ns 1.6 V ≤ Vb ≤ 2.0 V Note 2 31 31 (Notes, Caution and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 56 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/2) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- Unit speed main) main) mode voltage main) mode mode MIN. MAX. MIN. MAX. MIN. MAX. Delay time from SCKp↓ tKSO2 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 2/fMCK 2/fMCK 2/fMCK ns to SOp output Note 5 Cb = 30 pF, Rb = 1.4 kΩ + 120 + 573 + 573 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 2/fMCK 2/fMCK 2/fMCK ns Cb = 30 pF, Rb = 2.7 kΩ + 214 + 573 + 573 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 2/fMCK 2/fMCK 2/fMCK ns Cb = 30 pF, Rb = 5.5 kΩ + 573 + 573 + 573 1.8 V ≤ EVDD < 3.3 V, 2/fMCK 2/fMCK ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, + 573 + 573 Cb = 30 pF, Rb = 5.5 kΩ Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. Use it with EVDD ≥ Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance (32-pin to 52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp SCK RL78 SIp SO User's device microcontroller SOp SI Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0157EJ0210 Rev.2.10 Page 57 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 SIp Input data tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp tSIK2 tKSI2 SIp Input data tKSO2 SOp Output data Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) R01DS0157EJ0210 Rev.2.10 Page 58 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.5.2 Serial interface IICA (1) I2C standard mode (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- Unit speed main) main) Mode voltage main) Mode Mode MIN. MAX. MIN. MIN. MAX. MIN. SCLA0 clock frequency fSCL Standard 2.7 V ≤ EVDD ≤ 5.5 V 0 100 0 100 0 100 kHz mode: fCLK ≥ 1 MHz 2.4 V ≤ EVDD ≤ 5.5 V 0 100 0 100 0 100 1.8 V ≤ EVDD ≤ 5.5 V 0 100 0 100 1.6 V ≤ EVDD ≤ 5.5 V 0 100 Setup time of restart condition tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 1.6 V ≤ EVDD ≤ 5.5 V 4.7 Hold time Note 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 1.6 V ≤ EVDD ≤ 5.5 V 4.0 Hold time when SCLA0 = “L” tLOW 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 1.6 V ≤ EVDD ≤ 5.5 V 4.7 Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 1.6 V ≤ EVDD ≤ 5.5 V 4.0 Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 250 250 250 ns 2.4 V ≤ EVDD ≤ 5.5 V 250 250 250 1.8 V ≤ EVDD ≤ 5.5 V 250 250 1.6 V ≤ EVDD ≤ 5.5 V 250 Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 μs 2.4 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 1.8 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 1.6 V ≤ EVDD ≤ 5.5 V 0 3.45 Setup time of stop condition tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 1.6 V ≤ EVDD ≤ 5.5 V 4.0 Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 1.6 V ≤ EVDD ≤ 5.5 V 4.7 (Notes and Remark are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 59 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ R01DS0157EJ0210 Rev.2.10 Page 60 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (2) I2C fast mode (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- Unit speed main) main) Mode voltage main) Mode Mode MIN. MAX. MIN. MIN. MAX. MIN. SCLA0 clock frequency fSCL Fast mode: 2.7 V ≤ EVDD ≤ 5.5 V 0 400 0 400 0 400 kHz fCLK ≥ 3.5 2.4 V ≤ EVDD ≤ 5.5 V 0 400 0 400 0 400 MHz 1.8 V ≤ EVDD ≤ 5.5 V 0 400 0 400 Setup time of restart condition tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 μs 2.4 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 1.8 V ≤ EVDD ≤ 5.5 V 0.6 0.6 Hold time Note 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 μs 2.4 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 1.8 V ≤ EVDD ≤ 5.5 V 0.6 0.6 Hold time when SCLA0 = “L” tLOW 2.7 V ≤ EVDD ≤ 5.5 V 1.3 1.3 1.3 μs 2.4 V ≤ EVDD ≤ 5.5 V 1.3 1.3 1.3 1.8 V ≤ EVDD ≤ 5.5 V 1.3 1.3 Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 μs 2.4 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 1.8 V ≤ EVDD ≤ 5.5 V 0.6 0.6 Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 100 100 100 ns 2.4 V ≤ EVDD ≤ 5.5 V 100 100 100 1.8 V ≤ EVDD ≤ 5.5 V 100 100 Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 0 0.9 μs 2.4 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 0 0.9 1.8 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 Setup time of stop condition tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 μs 2.4 V ≤ EVDD ≤ 5.5 V 0.6 0.6 0.6 1.8 V ≤ EVDD ≤ 5.5 V 0.6 0.6 Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 1.3 1.3 1.3 μs 2.4 V ≤ EVDD ≤ 5.5 V 1.3 1.3 1.3 1.8 V ≤ EVDD ≤ 5.5 V 1.3 1.3 Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 kΩ R01DS0157EJ0210 Rev.2.10 Page 61 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (3) I2C fast mode plus (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode plus: 2.7 V ≤ EVDD ≤ 5.5 V 0 1000 ⎯ ⎯ kHz fCLK ≥ 10 MHz Setup time of restart tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.26 ⎯ ⎯ μs condition Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.26 ⎯ ⎯ μs Hold time when SCLA0 = tLOW 2.7 V ≤ EVDD ≤ 5.5 V 0.5 ⎯ ⎯ μs “L” Hold time when SCLA0 = tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 0.26 ⎯ ⎯ μs “H” Data setup time tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 50 ⎯ ⎯ μs (reception) Data hold time tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 0.45 ⎯ ⎯ μs (transmission)Note 2 Setup time of stop tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 0.26 ⎯ ⎯ μs condition Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 0.5 ⎯ ⎯ μs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing tLOW SCLA0 tHD:DAT tHIGH tSU:STA tHD:STA tSU:STO tHD:STA tSU:DAT SDAA0 tLOW Stop Start Restart Stop condition condition condition condition R01DS0157EJ0210 Rev.2.10 Page 62 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.6 Analog Characteristics 2.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = AVREFP Reference voltage (+) = VDD Reference voltage (+) = VBGR Input channel Reference voltage (−) = AVREFM Reference voltage (−) = VSS Reference voltage (−) = AVREFM ANI0, ANI1 − Refer to 2.6.1 (3). Refer to 2.6.1 (4). ANI16 to ANI23 Refer to 2.6.1 (2). Internal reference voltage Refer to 2.6.1 (1). − Temperature sensor output voltage (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : internal reference voltage, and temperature sensor output voltage (TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.2 ±3.5 LSB AVREFP = VDD Note 3 1.6 V ≤ VDD ≤ 5.5 V Note 4 1.2 ±7.0 LSB Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.375 39 μs Target pin: Internal reference 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 μs voltage, and temperature sensor output voltage (HS 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs (high-speed main) mode) Zero-scale errorNotes 1, 2 EZS 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR AVREFP = VDD Note 3 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 ±0.50 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR AVREFP = VDD Note 3 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 ±0.50 %FSR Integral linearity ILE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±2.5 LSB errorNote 1 AVREFP = VDD Note 3 1.6 V ≤ VDD ≤ 5.5 V Note 4 ±5.0 LSB Differential linearity DLE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±1.5 LSB errorNote 1 AVREFP = VDD Note 3 1.6 V ≤ VDD ≤ 5.5 V Note 4 ±2.0 LSB Analog input voltage VAIN Internal reference voltage VBGR Note 5 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VBGR Temperature sensor output voltage VTMPS25 Note 5 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Values when the conversion time is set to 57 μs (min.) and 95 μs (max.). 5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0157EJ0210 Rev.2.10 Page 63 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI23 (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB AVREFP = EVDD = VDD 1.6 V ≤ AVREFP ≤ 5.5 V 1.2 ±8.5 LSB Note 3 Note 4 Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 μs AVREFP = EVDD = VDD 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs Note 3 1.8 V ≤ VDD ≤ 5.5 V 17 39 μs 1.6 V ≤ VDD ≤ 5.5 V 57 95 μs Zero-scale errorNotes 1, 2 EZS 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR A3 VREFP = EVDD = VDD Note 1.6 V ≤ AVREFP ≤ 5.5 V ±0.60 %FSR Note 4 Full-scale errorNotes 1, 2 EFS 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR A3 VREFP = EVDD = VDD Note 1.6 V ≤ AVREFP ≤ 5.5 V ±0.60 %FSR Note 4 Integral linearity errorNote 1 ILE 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB AVREFP = EVDD = VDD 1.6 V ≤ AVREFP ≤ 5.5 V ±6.0 LSB Note 3 Note 4 Differential linearity error DLE 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB Note 1 AVREFP = EVDD = VDD 1.6 V ≤ AVREFP ≤ 5.5 V ±2.5 LSB Note 3 Note 4 Analog input voltage VAIN 0 AVREFP V and EVDD Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV < EV = V , the MAX. values are as follows. REFP DD DD Overall error: Add ±4.0 LSB to the MAX. value when AV = V . REFP DD Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AV = V . REFP DD Integral linearity error/Differential linearity error: Add ±2.0 LSB to the MAX. value when AV = V . REFP DD 4. When the conversion time is set to 57 μs (min.) and 95 μs (max.). R01DS0157EJ0210 Rev.2.10 Page 64 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0), target pin : ANI0, ANI1, ANI16 to ANI23, internal reference voltage, and temperature sensor output voltage (TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB 1.6 V ≤ VDD ≤ 5.5 V 1.2 ±10.5 LSB Note 3 Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs 1.8 V ≤ VDD ≤ 5.5 V 17 39 μs 1.6 V ≤ VDD ≤ 5.5 V 57 95 μs 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.375 39 μs Target pin: Internal 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 μs reference voltage, and 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs temperature sensor output voltage (HS (high-speed main) mode) Zero-scale errorNotes 1, 2 EZS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR 1.6 V ≤ VDD ≤ 5.5 V ±0.85 %FSR Note 3 Full-scale errorNotes 1, 2 EFS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR 1.6 V ≤ VDD ≤ 5.5 V ±0.85 %FSR Note 3 Integral linearity errorNote 1 ILE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±4.0 LSB 1.6 V ≤ VDD ≤ 5.5 V ±6.5 LSB Note 3 Differential linearity error Note 1 DLE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±2.0 LSB 1.6 V ≤ VDD ≤ 5.5 V ±2.5 LSB Note 3 Analog input voltage VAIN ANI0, ANI1 0 VDD V ANI16 to ANI23 0 EVDD V Internal reference voltage VBGR Note 4 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage VTMPS25 Note 4 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When the conversion time is set to 57 μs (min.) and 95 μs (max.). 4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0157EJ0210 Rev.2.10 Page 65 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI16 to ANI23 (TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (−) = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 bit Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs Zero-scale errorNotes 1, 2 EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±1.0 LSB Analog input voltage VAIN 0 VBGR Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (−) = VSS, the MAX. values are as follows. Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (−) = AVREFM. Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (−) = AVREFM. Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (−) = AVREFM. 2.6.2 Temperature sensor/internal reference voltage characteristics (TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V Temperature coefficient FVTMPS Temperature sensor that depends on the −3.6 mV/°C temperature Operation stabilization wait time tAMP 5 μs R01DS0157EJ0210 Rev.2.10 Page 66 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.6.3 POR circuit characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR Power supply rise time 1.47 1.51 1.55 V VPDR Power supply fall time 1.46 1.50 1.54 V Minimum pulse widthNote TPW 300 μs Note Minimum time required for a POR reset when V exceeds below V . This is also the minimum time required for a DD PDR POR reset from when V exceeds below 0.7 V to when V exceeds V while STOP mode is entered or the main DD DD POR system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0157EJ0210 Rev.2.10 Page 67 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.6.4 LVD circuit characteristics (TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level VLVD0 Power supply rise time 3.98 4.06 4.14 V voltage Power supply fall time 3.90 3.98 4.06 V VLVD1 Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V VLVD2 Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V VLVD3 Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V VLVD4 Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V VLVD5 Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V VLVD6 Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V VLVD7 Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V VLVD8 Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V VLVD9 Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V VLVD10 Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V VLVD11 Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V VLVD12 Power supply rise time 1.74 1.77 1.81 V Power supply fall time 1.70 1.73 1.77 V VLVD13 Power supply rise time 1.64 1.67 1.70 V Power supply fall time 1.60 1.63 1.66 V Minimum pulse width tLW 300 μs Detection delay time tLD 300 μs R01DS0157EJ0210 Rev.2.10 Page 68 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset VLVDA0 VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 V mode VLVDA1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.74 1.77 1.81 V Falling interrupt voltage 1.70 1.73 1.77 V VLVDA2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 1.84 1.88 1.91 V Falling interrupt voltage 1.80 1.84 1.87 V VLVDA3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDB1 VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 V VLVDB2 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V VLVDB3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V VLVDB4 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VLVDC2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V VLVDC3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V 2.6.5 Supply voltage rise time (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V reaches the DD operating voltage range shown in 30.4 AC Characteristics. R01DS0157EJ0210 Rev.2.10 Page 69 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.7 LCD Characteristics 2.7.1 Resistance division method (1) Static display mode (TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.0 VDD V (2) 1/2 bias method, 1/4 bias method (TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.7 VDD V (3) 1/3 bias method (TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.5 VDD V R01DS0157EJ0210 Rev.2.10 Page 70 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.7.2 Internal voltage boosting method (1) 1/3 bias method (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD output voltage variation range VL1 C1 to C4Note 1 VLCD = 04H 0.90 1.00 1.08 V = 0.47 μF VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V Doubler output voltage VL2 C1 to C4Note 1 = 0.47 μF 2 VL1 2 VL1 2 VL1 V − 0.1 Tripler output voltage VL4 C1 to C4Note 1 = 0.47 μF 3 VL1 3 VL1 3 VL1 V − 0.15 Reference voltage setup time Note 2 tVWAIT1 5 ms Voltage boost wait timeNote 3 tVWAIT2 C1 to C4Note 1 = 0.47 μF 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between V and GND L1 C3: A capacitor connected between V and GND L2 C4: A capacitor connected between V and GND L4 C1 = C2 = C3 = C4 = 0.47 μF±30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). R01DS0157EJ0210 Rev.2.10 Page 71 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) (2) 1/4 bias method (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD output voltage variation range VL1 Note 4 C1 to C5Note 1 VLCD = 04H 0.90 1.00 1.08 V = 0.47 μF VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V Doubler output voltage VL2 C1 to C5Note 1 = 0.47 μF 2 VL1 − 0.08 2 VL1 2 VL1 V Tripler output voltage VL3 C1 to C5Note 1 = 0.47 μF 3 VL1 − 0.12 3 VL1 3 VL1 V Quadruply output voltage VL4 Note 4 C1 to C5Note 1 = 0.47 μF 4 VL1 − 0.16 4 VL1 4 VL1 V Reference voltage setup time Note 2 tVWAIT1 5 ms Voltage boost wait timeNote 3 tVWAIT2 C1 to C5Note 1 = 0.47 μF 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between V and GND L1 C3: A capacitor connected between V and GND L2 C4: A capacitor connected between V and GND L3 C5: A capacitor connected between V and GND L4 C1 = C2 = C3 = C4 = C5 = 0.47 μF±30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). 4. VL4 must be 5.5 V or lower. 2.7.3 Capacitor split method 1/3 bias method (TA = −40 to +85°C, 2.2 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VL4 voltage VL4 C1 to C4 = 0.47 μ FNote 2 VDD V VL2 voltage VL2 C1 to C4 = 0.47 μ FNote 2 2/3 VL4 2/3 VL4 2/3 VL4 V − 0.1 + 0.1 VL1 voltage VL1 C1 to C4 = 0.47 μ FNote 2 1/3 VL4 1/3 VL4 1/3 VL4 V − 0.1 + 0.1 Capacitor split wait timeNote 1 tVWAIT 100 ms R01DS0157EJ0210 Rev.2.10 Page 72 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). 2. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between V and GND L1 C3: A capacitor connected between V and GND L2 C4: A capacitor connected between V and GND L4 C1 = C2 = C3 = C4 = 0.47 μF±30% R01DS0157EJ0210 Rev.2.10 Page 73 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) <R> 2.8 RAM Data Retention Characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage VDDDR 1.46Note 5.5 V <R> Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. STOP mode Operation mode <R> RAM Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.9 Flash Memory Programming Characteristics (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit System clock frequency fCLK 1.8 V ≤ VDD ≤ 5.5 V 1 24 MHz <R> Number of code flash rewrites Cerwr Retained for 20 years 1,000 Times Note 1, 2, 3 TA = 85°C <R> Number of data flash rewrites Retained for 1 year 1,000,000 Note 1, 2, 3 TA = 25°C <R> Retained for 5 years 100,000 TA = 85°C <R> Retained for 20 years 10,000 TA = 85°C Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test. Remark When updating data multiple times, use the flash memory as one for updating data. 2.10 Dedicated Flash Memory Programmer Communication (UART) (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate During flash memory programming 115,200 1,000,000 bps R01DS0157EJ0210 Rev.2.10 Page 74 of 131 Sep 30, 2016

RL78/L12 2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C) 2.11 Timing Specifications for Switching Flash Memory Programming Modes (TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the tSUINIT POR and LVD reset must be released before 100 ms communication for the initial setting the external reset is released. after the external reset is released Time to release the external reset tSU POR and LVD reset must be released before 10 μ s after the TOOL0 pin is set to the the external reset is released. low level Time to hold the TOOL0 pin at the tHD POR and LVD reset must be released before 1 ms low level after the external reset is the external reset is released. released (excluding the processing time of the firmware to control the flash memory) <1> <2> <3> <4> RESET tHD+ soft processing 1-byte data for mode setting time TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after a reset is released during this period. t : Time to release the external reset after the TOOL0 pin is set to the low level SU tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0157EJ0210 Rev.2.10 Page 75 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3. ELECTRICAL SPECIFICATIONS (G: T = -40 to +105°C) A This chapter describes the electrical specifications for the products "G: Industrial applications (TA = -40 to +105°C)". Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with VSS. 3. For derating with TA = +85 to +105°C, contact our Sales Division or the vender's sales division. Derating means the specified reduction in an operating parameter to improve reliability. R01DS0157EJ0210 Rev.2.10 Page 76 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) There are following differences between the products "G: Industrial applications (TA = -40 to +105°C)" and the products “A: Consumer applications, and G: Industrial applications (TA = -40 to +85°C)”. Parameter Application A: Consumer applications, G: Industrial applications G: Industrial applications (with TA = -40 to +85°C) Operating ambient temperature TA = -40 to +85°C TA = -40 to +105°C Operating mode HS (high-speed main) mode: HS (high-speed main) mode only: Operating voltage range 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz High-speed on-chip oscillator clock 1.8 V ≤ VDD ≤ 5.5 V: 2.4 V ≤ VDD ≤ 5.5 V: accuracy ±1.0%@ TA = -20 to +85°C ±2.0%@ TA = +85 to +105°C ±1.5%@ TA = -40 to -20°C ±1.0%@ TA = -20 to +85°C 1.6 V ≤ VDD < 1.8 V: ±1.5%@ TA = -40 to -20°C ±5.0%@ TA = -20 to +85°C ±5.5%@ TA = -40 to -20°C Serial array unit UART UART CSI00: fCLK/2 (supporting 16 Mbps), fCLK/4 CSI00: fCLK/4 CSI01 CSI01 Simplified I2C communication Simplified I2C communication IICA Normal mode Normal mode Fast mode Fast mode Fast mode plus Voltage detector Rise detection voltage: 1.67 V to 4.06 V Rise detection voltage: 2.61 V to 4.06 V (14 levels) (8 levels) Fall detection voltage: 1.63 V to 3.98 V Fall detection voltage: 2.55 V to 3.98 V (14 levels) (8 levels) Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different from those of the products “A: Consumer applications, and G: Industrial applications (only with TA = -40 to +85°C)”. For details, refer to 3.1 to 3.10. R01DS0157EJ0210 Rev.2.10 Page 77 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/3) Parameter Symbols Conditions Ratings Unit Supply voltage VDD VDD = EVDD −0.5 to +6.5 V EVDD VDD = EVDD −0.5 to +6.5 V EVSS −0.5 to +0.3 V REGC pin input voltage VIREGC REGC −0.3 to +2.8 V and −0.3 to VDD + 0.3 Note 1 Input voltage VI1 P10 to P17, P30 to P32, P40 to P43, −0.3 to EVDD + 0.3 V P50 to P54, P70 to P74, P120, P125 to P127, P140 and −0.3 to VDD + 0.3Note 2 to P147 VI2 P60, P61 (N-ch open-drain) −0.3 to EVDD + 0.3 V and −0.3 to VDD + 0.3Note 2 VI3 P20, P21, P121 to P124, P137, EXCLK, EXCLKS, −0.3 to VDD + 0.3Note 2 V RESET Output voltage VO1 P10 to P17, P30 to P32, P40 to P43, P50 to P54, −0.3 to EVDD + 0.3 V P60, P61, P70 to P74, P120, P125 to P127, P130, and −0.3 to VDD + 0.3 Note 2 P140 to P147 VO2 P20, P21 −0.3 to VDD + 0.3 Note 2 V Analog input voltage VAI1 ANI16 to ANI23 −0.3 to EVDD + 0.3 V and −0.3 to AVREF(+) + 0.3Notes 2, 3 VAI2 ANI0, ANI1 −0.3 to VDD + 0.3 V and −0.3 to AVREF(+) + 0.3Notes 2, 3 Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AV (+) : + side reference voltage of the A/D converter. REF 3. V : Reference voltage SS R01DS0157EJ0210 Rev.2.10 Page 78 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Absolute Maximum Ratings (TA = 25°C) (2/3) Parameter Symbols Conditions Ratings Unit LCD voltage VL1 VL1 voltageNote 1 −0.3 to +2.8 V and −0.3 to VL4 + 0.3 VL2 VL2 voltageNote 1 −0.3 to VL4 + 0.3 Note 2 V VL3 VL3 voltageNote 1 −0.3 to VL4 + 0.3 Note 2 V VL4 VL4 voltageNote 1 −0.3 to +6.5 V VLCAP CAPL, CAPH voltageNote 1 −0.3 to VL4 + 0.3 Note 2 V VLOUT COM0 to COM7, External resistance division −0.3 to VDD + 0.3 Note 2 V SEG0 to method SEG38, Capacitor split method −0.3 to VDD + 0.3 Note 2 output voltage Internal voltage boosting method −0.3 to VL4 + 0.3 Note 2 Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does not mean that applying voltage to these pins is recommended. When using the internal voltage boosting method or capacitance split method, connect these pins to VSS via a capacitor (0.47 μ F ± 30%) and connect a capacitor (0.47 μ F ± 30%) between the CAPL and CAPH pins. 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark V : Reference voltage SS R01DS0157EJ0210 Rev.2.10 Page 79 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Absolute Maximum Ratings (TA = 25°C) (3/3) Parameter Symbols Conditions Ratings Unit Output current, high IOH1 Per pin P10 to P17, P30 to P32, P40 to P43, −40 mA P50 to P54, P70 to P74, P120, P125 to P127, P130, P140 to P147 Total of all pins P10 to P14, P40 to P43, P120, −70 mA −170 mA P130, P140 to P147 P15 to P17, P30 to P32, −100 mA P50 to P54, P70 to P74, P125 to P127 IOH2 Per pin P20, P21 −0.5 mA Total of all pins −1 mA Output current, low IOL1 Per pin P10 to P17, P30 to P32, P40 to P43, 40 mA P50 to P54, P60, P61, P70 to P74, P120, P125 to P127, P130, P140 to P147 Total of all pins P10 to P14, P40 to P43, P120, 70 mA 170 mA P130, P140 to P147 P15 to P17, P30 to P32, P50 to P54, 100 mA P60, P61, P70 to P74, P125 to P127 IOL2 Per pin P20, P21 1 mA Total of all pins 2 mA Operating ambient TA In normal operation mode −40 to +105 °C temperature In flash memory programming mode Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 80 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.2 Oscillator Characteristics 3.2.1 X1, XT1 oscillator characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation Ceramic resonator/ 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz frequency (fX)Note crystal resonator 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz XT1 clock oscillation Crystal resonator 32 32.768 35 kHz frequency (fXT)Note Note Indicates only permissible oscillator frequency ranges. Refer to 3.4 AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. 3.2.2 On-chip oscillator characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator fIH 1 24 MHz clock frequency Notes 1, 2 High-speed on-chip oscillator −20 to +85°C 2.4 V ≤ VDD ≤ 5.5 V −1 +1 % clock frequency accuracy −40 to −20°C 2.4 V ≤ VDD ≤ 5.5 V −1.5 +1.5 % +85 to +105°C 2.4 V ≤ VDD ≤ 5.5 V −2.0 +2.0 % Low-speed on-chip oscillator fIL 15 kHz clock frequency Low-speed on-chip oscillator −15 +15 % clock frequency accuracy Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to 3.4 AC Characteristics for instruction execution time. R01DS0157EJ0210 Rev.2.10 Page 81 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.3 DC Characteristics 3.3.1 Pin characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, IOH1 Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54, -3.0 Note 2 mA highNote 1 P70 to P74, P120, P125 to P127, P130, P140 to P147 Total of P10 to P14, P40 to P43, P120, 4.0 V ≤ EVDD ≤ 5.5 V -30.0 mA P130, P140 to P147 2.7 V ≤ EVDD < 4.0 V −8.0 mA (When duty = 70% Note 3) 2.4 V ≤ EVDD < 2.7 V −4.0 mA Total of P15 to P17, P30 to P32, 4.0 V ≤ EVDD ≤ 5.5 V -30.0 mA P50 to P54, P70 to P74, P125 to P127 2.7 V ≤ EVDD < 4.0 V −15.0 mA (When duty = 70% Note 3) 2.4 V ≤ EVDD < 2.7 V −8.0 mA Total of all pins -60.0 mA (When duty = 70%Note 3) IOH2 P20, P21 Per pin −0.1 mA Total of all pins 2.4 V ≤ VDD ≤ 5.5 V −0.2 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD and EVDD pins to an output pin. 2. Do not exceed the total current value. 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (I OH × 0.7)/(n × 0.01) <Example> Where n = 80% and IOH = −30.0 mA Total output current of pins = (−30.0 × 0.7)/(80 × 0.01) ≅ −26.25 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 82 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, IOL1 Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54, 8.5 Note 2 mA lowNote 1 P70 to P74, P120, P125 to P127, P130, P140 to P147 Per pin for P60, P61 15.0 Note 2 mA Total of P10 to P14, P40 to P43, P120, 4.0 V ≤ EVDD ≤ 5.5 V 40.0 mA P130, P140 to P147 2.7 V ≤ EVDD < 4.0 V 15.0 mA (When duty = 70% Note 3) 2.4 V ≤ EVDD < 2.7 V 9.0 mA Total of P15 to P17, P30 to P32, P50 4.0 V ≤ EVDD ≤ 5.5 V 40.0 mA to P54, P60, P61, P70 to P74, 2.7 V ≤ EVDD < 4.0 V 35.0 mA P125 to P127 (When duty = 70% Note 3) 2,4 V ≤ EVDD < 2.7 V 20.0 mA Total of all pins 80.0 mA (When duty = 70% Note 3) IOL2 P20, P21 Per pin 0.4 mA Total of all pins 2.4 V ≤ VDD ≤ 5.5 V 0.8 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD and EVDD pins to an output pin. 2. Do not exceed the total current value. 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (I OL × 0.7)/(n × 0.01) <Example> Where n = 80% and IOL = 40.0 mA Total output current of pins = (40.0 × 0.7)/(80 × 0.01) ≅ 35.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 83 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (3/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, VIH1 P10 to P17, P30 to P32, P40 to P43, Normal input buffer 0.8EVDD EVDD V high P50 to P54, P70 to P74, P120, P125 to P127, P140 to P147 VIH2 P10, P11, P15, P16 TTL input buffer 2.2 EVDD V 4.0 V ≤ EVDD ≤ 5.5 V TTL input buffer 2.0 EVDD V 3.3 V ≤ EVDD < 4.0 V TTL input buffer 1.50 EVDD V 2.4 V ≤ EVDD < 3.3 V VIH3 P20, P21 0.7VDD VDD V VIH4 P60, P61 0.7EVDD EVDD V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V Input voltage, low VIL1 P10 to P17, P30 to P32, P40 to P43, Normal input buffer 0 0.2EVDD V P50 to P54, P70 to P74, P120, P125 to P127, P140 to P147 VIL2 P10, P11, P15, P16 TTL input buffer 0 0.8 V 4.0 V ≤ EVDD ≤ 5.5 V TTL input buffer 0 0.5 V 3.3 V ≤ EVDD < 4.0 V TTL input buffer 0 0.32 V 2.4 V ≤ EVDD < 3.3 V VIL3 P20, P21 0 0.3VDD V VIL4 P60, P61 0 0.3EVDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Caution The maximum value of VIH of pins P10, P12, P15, and P17 is EVDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 84 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (4/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, VOH1 P10 to P17, P30 to P32, P40 to P43, 4.0 V ≤ EVDD ≤ 5.5 V, EVDD − V high P50 to P54, P70 to P74, P120, IOH1 = −3.0 mA 0.7 P125 to P127, P130, P140 to P147 2.7 V ≤ EVDD ≤ 5.5 V, EVDD − V IOH1 = −2.0 mA 0.6 2.4 V ≤ EVDD ≤ 5.5 V, EVDD − V IOH1 = −1.5 mA 0.5 VOH2 P20, P21 2.4 V ≤ VDD ≤ 5.5 V, VDD − 0.5 V IOH2 = −100 μ A Output voltage, VOL1 P10 to P17, P30 to P32, P40 to P43, 4.0 V ≤ EVDD ≤ 5.5 V, 0.7 V low P50 to P54, P70 to P74, P120, IOL1 = 8.5 mA P125 to P127, P130, P140 to P147 2.7 V ≤ EVDD ≤ 5.5 V, 0.6 V IOL1 = 3.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL1 = 1.5 mA 2.4 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL1 = 0.6 mA VOL2 P20, P21 2.4 V ≤ VDD ≤ 5.5 V, 0.4 V IOL2 = 400 μ A VOL3 P60, P61 4.0 V ≤ EVDD ≤ 5.5 V, 2.0 V IOL3 = 15.0 mA 4.0 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL3 = 5.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL3 = 3.0 mA 2.4 V ≤ EVDD ≤ 5.5 V, 0.4 V IOL3 = 2.0 mA Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 85 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage ILIH1 P10 to P17, P30 to P32, VI = EVDD 1 μA current, high P40 to P43, P50 to P54, P60, P61, P70 to P74, P120, P125 to P127, P140 to P147 ILIH2 P20, P21, P137, RESET VI = VDD 1 μA ILIH3 P121 to P124 VI = VDD In input port or 1 μA (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input In resonator 10 μA connection Input leakage ILIL1 P10 to P17, P30 to P32, VI = EVSS −1 μA current, low P40 to P43, P50 to P54, P60, P61, P70 to P74, P120, P125 to P127, P140 to P147 ILIL2 P20, P21, P137, RESET VI = VSS −1 μA ILIL3 P121 to P124 VI = VSS In input port or −1 μA (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input In resonator −10 μA connection On-chip pll-up RU1 VI = EVSS SEGxx port resistance 2.4 V ≤ EVDD = VDD ≤ 5.5 V 10 20 100 kΩ RU2 Ports other than above 10 20 100 kΩ (Except for P60, P61, and P130) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0157EJ0210 Rev.2.10 Page 86 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.3.2 Supply current characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (1/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply IDD1 Operating HS (high- fIH = 24 MHz Note 3 Basic VDD = 5.0 V 1.5 mA current mode speed main) operation Note 1 mode Note 5 VDD = 3.0 V 1.5 mA Normal VDD = 5.0 V 3.3 5.3 mA operation VDD = 3.0 V 3.3 5.3 mA fIH = 16 MHz Note 3 Normal VDD = 5.0 V 2.5 3.9 mA operation VDD = 3.0 V 2.5 3.9 mA HS (high- fMX = 20 MHzNote 2, Normal Square wave input 2.8 4.7 mA smpoedeed N motae i5n ) VDD = 5.0 V operation Resonator connection 3.0 4.8 mA fMX = 20 MHzNote 2, Normal Square wave input 2.8 4.7 mA VDD = 3.0 V operation Resonator connection 3.0 4.8 mA fMX = 10 MHzNote 2, Normal Square wave input 1.8 2.8 mA VDD = 5.0 V operation Resonator connection 1.8 2.8 mA fMX = 10 MHzNote 2, Normal Square wave input 1.8 2.8 mA VDD = 3.0 V operation Resonator connection 1.8 2.8 mA Subsystem fSUB = 32.768 kHz Normal Square wave input 3.5 4.9 μA clock Note 4 operation Resonator connection 3.6 5.0 μA operation TA = −40°C fSUB = 32.768 kHz Normal Square wave input 3.6 4.9 μA Note 4 operation Resonator connection 3.7 5.0 μA TA = +25°C fSUB = 32.768 kHz Normal Square wave input 3.7 5.5 μA Note 4 operation Resonator connection 3.8 5.6 μA TA = +50°C fSUB = 32.768 kHz Normal Square wave input 3.8 6.3 μA Note 4 operation Resonator connection 3.9 6.4 μA TA = +70°C fSUB = 32.768 kHz Normal Square wave input 4.1 7.7 μA Note 4 operation Resonator connection 4.2 7.8 μA TA = +85°C fSUB = 32.768 kHz Normal Square wave input 6.4 19.7 μA Note 4 operation Resonator connection 6.5 19.8 μA TA = +105°C (Notes and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 87 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, watchdog timer, and LCD controller/driver. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0157EJ0210 Rev.2.10 Page 88 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (2/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply IDD2 HALT HS (high- fIH = 24 MHz Note 4 VDD = 5.0 V 0.44 2.3 mA current Note 2 mode speed main) mode Note 7 VDD = 3.0 V 0.44 2.3 mA Note 1 fIH = 16 MHz Note 4 VDD = 5.0 V 0.40 1.7 mA VDD = 3.0 V 0.40 1.7 mA HS (high- fMX = 20 MHzNote 3, Square wave input 0.28 1.9 mA speed main) mode Note 7 VDD = 5.0 V Resonator connection 0.45 2.0 mA fMX = 20 MHzNote 3, Square wave input 0.28 1.9 mA VDD = 3.0 V Resonator connection 0.45 2.0 mA fMX = 10 MHzNote 3, Square wave input 0.19 1.02 mA VDD = 5.0 V Resonator connection 0.26 1.10 mA fMX = 10 MHzNote 3, Square wave input 0.19 1.02 mA VDD = 3.0 V Resonator connection 0.26 1.10 mA Subsystem fSUB = 32.768 kHzNote 5 Square wave input 0.31 0.57 μA clock TA = −40°C Resonator connection 0.50 0.76 μA operation fSUB = 32.768 kHzNote 5 Square wave input 0.37 0.57 μA TA = +25°C Resonator connection 0.56 0.76 μA fSUB = 32.768 kHzNote 5 Square wave input 0.46 1.17 μA TA = +50°C Resonator connection 0.65 1.36 μA fSUB = 32.768 kHzNote 5 Square wave input 0.57 1.97 μA TA = +70°C Resonator connection 0.76 2.16 μA fSUB = 32.768 kHzNote 5 Square wave input 0.85 3.37 μA TA = +85°C Resonator connection 1.04 3.56 μA fSUB = 32.768 kHzNote 5 Square wave input 3.04 15.37 μA TA = +105°C Resonator connection 3.23 15.56 μA IDD3Note 6 STOP TA = −40°C 0.17 0.50 μA modeNote 8 TA = +25°C 0.23 0.50 μA TA = +50°C 0.32 1.10 μA TA = +70°C 0.43 1.90 μA TA = +85°C 0.71 3.30 μA TA = +105°C 2.90 15.30 μA (Notes and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 89 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer, watchdog timer, and LCD controller/driver. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz 8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0157EJ0210 Rev.2.10 Page 90 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (3/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on- IFIL Note 1 0.20 μA chip oscillator operating current RTC operating IRTC fMAIN is stopped 0.08 μA current Notes 1, 2, 3 12-bit interval IIT 0.08 μA timer current Notes 1, 2, 4 Watchdog timer IWDT fIL = 15 kHz 0.24 μA operating Notes 1, 2, 5 current A/D converter IADC When conversion Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA operating Notes 1, 6 at maximum speed Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA current A/D converter IADREF 75.0 μA reference Note 1 voltage current Temperature ITMPS 75.0 μA sensor Note 1 operating current LVD operating ILVD 0.08 μA current Notes 1, 7 Self- IFSP 2.50 12.20 mA programming Notes 1, 9 operating current BGO operating IBGO 2.50 12.20 mA current Notes 1, 8 LCD operating ILCD1 External resistance division method VDD = EVDD = 5.0 V 0.04 0.20 μA current Notes 11, 12 VL4 = 5.0 V ILCD2 Internal voltage boosting method VDD = EVDD = 5.0 V 1.12 3.70 μA Note 11 VL4 = 5.1 V (VLCD = 12H) VDD = EVDD = 3.0 V 0.63 2.20 μA VL4 = 3.0 V (VLCD = 04H) ILCD3 Note 11 Capacitor split method VDD = EVDD = 3.0 V 0.12 0.50 μA VL4 = 3.0 V SNOOZE ISNOZ Note 1 ADC operation The mode is performed Note 10 0.50 1.10 mA operating The A/D conversion operations are 1.20 2.04 mA current performed, Low voltage mode, AVREFP = VDD = 3.0 V CSI/UART operation 0.70 1.54 mA (Notes and Remarks are listed on the next page.) R01DS0157EJ0210 Rev.2.10 Page 91 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10. For shift time to the SNOOZE mode. 11. Current flowing only to the LCD controller/driver. The supply current value of the RL78 microcontrollers is the sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1 or IDD2) when the LCD controller/driver operates in an operation mode or HALT mode. Not including the current that flows through the LCD panel. The TYP. value and MAX. value are following conditions. • When fSUB is selected for system clock, LCD clock = 128 Hz (LCDC0 = 07H) • 4-Time-Slice, 1/3 Bias Method 12. Not including the current that flows through the external divider resistor when the external resistance division method is used. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25°C R01DS0157EJ0210 Rev.2.10 Page 92 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.4 AC Characteristics 3.4.1 Basic operation (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum TCY Main HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 μs instruction execution time) system main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 1 μs clock (fMAIN) operation Subsystem clock (fSUB) 2.4 V ≤ VDD ≤ 5.5 V 28.5 30.5 31.3 μs operation In the self HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 μs programming main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 1 μs mode External system clock frequency fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz fEXS 32 35 kHz External system clock input high- tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns level width, low-level width 2.4 V ≤ VDD < 2.7 V 30 ns tEXHS, 13.7 μs tEXLS TI00 to TI07 input high-level width, tTIH, 1/fMCK+10 ns low-level width tTIL TO00 to TO07 output frequency fTO HS (high-speed 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz main) mode 2.7 V ≤ EVDD < 4.0 V 8 MHz 2.4 V ≤ EVDD < 2.7 V 4 MHz PCLBUZ0, PCLBUZ1 output fPCL HS (high-speed 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz frequency main) mode 2.7 V ≤ EVDD < 4.0 V 8 MHz 2.4 V ≤ EVDD < 2.7 V 4 MHz Interrupt input high-level width, tINTH, INTP0 2.4 V ≤ VDD ≤ 5.5 V 1 μs low-level width tINTL INTP1 to INTP7 2.4 V ≤ EVDD ≤ 5.5 V 1 μs Key interrupt input low-level width tKR KR0 to KR3 2.4 V ≤ EVDD ≤ 5.5 V 250 ns RESET low-level width tRSL 10 μs Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7)) R01DS0157EJ0210 Rev.2.10 Page 93 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 s] µ [Y When the high-speed on-chip oscillator clock is selected C e T During self programming m When high-speed system clock is selected e ti cl y C 0.1 0.0625 0.05 0.0417 0.01 5.5 0 1.0 2.0 3.0 4.0 5.0 6.0 2.4 2.7 Supply voltage VDD [V] AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX/ 1/fEXS tEXL/ tEXH/ tEXLS tEXHS EXCLK/EXCLKS R01DS0157EJ0210 Rev.2.10 Page 94 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) TI/TO Timing tTIL tTIH TI00 to TI07 1/fTO TO00 to TO07 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR3 RESET Input Timing tRSL RESET R01DS0157EJ0210 Rev.2.10 Page 95 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 3.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Note 1 fMCK/12 bps Theoretical value of the 2.0 Mbps maximum transfer rate fMCK = fCLK Note 2 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. q: UART number (q = 0), g: PIM and POM number (g = 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0157EJ0210 Rev.2.10 Page 96 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time tKCY1 2.7 V ≤ EVDD ≤ 5.5 V 334 Note 1 ns 2.4 V ≤ EVDD ≤ 5.5 V 500 Note 1 ns SCKp high-/low-level width tKH1, 4.0 V ≤ EVDD ≤ 5.5 V tKCY1/2 − 24 ns tKL1 2.7 V ≤ EVDD ≤ 5.5 V tKCY1/2 − 36 ns 2.4 V ≤ EVDD ≤ 5.5 V tKCY1/2 − 76 ns SIp setup time (to SCKp↑) Note 2 tSIK1 2.7 V ≤ EVDD ≤ 5.5 V 66 ns 2.4 V ≤ EVDD ≤ 5.5 V 113 ns SIp hold time (from SCKp↑) Note 3 tKSI1 2.4 V ≤ EVDD ≤ 5.5 V 38 ns Delay time from SCKp↓ to tKSO1 C = 30 pF Note 5 2.4 V ≤ EVDD ≤ 5.5 V 50 ns SOp output Note 4 Notes 1. Set a cycle of 4/fMCK or longer. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0157EJ0210 Rev.2.10 Page 97 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 5 tKCY2 4.0 V ≤ EVDD ≤ 5.5 V 20 MHz < fMCK 16/fMCK ns fMCK ≤ 20 MHz 12/fMCK ns 2.7 V ≤ EVDD < 4.0 V 16 MHz < fMCK 16/fMCK ns fMCK ≤ 16 MHz 12/fMCK ns 2.4 V ≤ EVDD ≤ 5.5 V 12/fMCK and 1000 ns SCKp high-/low-level tKH2, 4.0 V ≤ EVDD ≤ 5.5 V tKCY2/2 − 14 ns width tKL2 2.7 V ≤ EVDD < 4.0 V tKCY2/2 − 16 ns 2.4 V ≤ EVDD < 2.7 V tKCY2/2 − 36 ns SIp setup time tSIK2 2.7 V ≤ EVDD ≤ 5.5 V 1/fMCK + 40 ns (to SCKp↑) Note 1 2.4 V ≤ EVDD < 2.7 V 1/fMCK + 60 ns SIp hold time tKSI2 2.4 V ≤ EVDD ≤ 5.5 V 1/fMCK + 62 ns (from SCKp↑) Note 2 Delay time from SCKp↓ tKSO2 C = 30 pF Note 4 4.0 V ≤ EVDD ≤ 5.5 V 2/fMCK + 66 ns to SOp output Note 3 2.7 V ≤ EVDD < 4.0 V 2/fMCK + 66 ns 2.4 V ≤ EVDD < 2.7 V 2/fMCK + 113 Ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM number (g = 1) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) CSI mode connection diagram (during communication at same potential) SCKp SCK RL78 SIp SO User's device microcontroller SOp SI R01DS0157EJ0210 Rev.2.10 Page 98 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 tKSI1, 2 SIp Input data tKSO1, 2 SOp Output data CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 tKSI1, 2 SIp Input data tKSO1, 2 SOp Output data Remarks 1. p: CSI number (p = 00, 01) 2. m: Unit number, n: Channel number (mn = 00, 01) R01DS0157EJ0210 Rev.2.10 Page 99 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Reception 4.0 V ≤ EVDD ≤ 5.5 V, fMCK/12 Note 1 bps 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the 2.0 Mbps maximum transfer rate fMCK = fCLK Note 2 2.7 V ≤ EVDD < 4.0 V, fMCK/12 Note 1 bps 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the 2.0 Mbps maximum transfer rate fMCK = fCLK Note 2 2.4 V ≤ EVDD < 3.3 V, fMCK/12 bps 1.6 V ≤ Vb ≤ 2.0 V Note 1 Theoretical value of the 2.0 Mbps maximum transfer rate fMCK = fCLK Note 2 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32- to 52-pin products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Vb[V]: Communication line voltage 2. q: UART number (q = 0), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01) R01DS0157EJ0210 Rev.2.10 Page 100 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Transmission 4.0 V ≤ EVDD ≤ 5.5 V, Note 1 bps 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the 2.0 Note 2 Mbps maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.7 V ≤ EVDD < 4.0 V, Note 3 bps 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the 1.2 Note 4 Mbps maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 2.4 V ≤ EVDD < 3.3 V, Note 5 bps 1.6 V ≤ Vb ≤ 2.0 V Theoretical value of the 0.43 Mbps maximum transfer rate Note 6 Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V 1 Maximum transfer rate = [bps] 2.2 {−Cb × Rb × ln (1 − Vb )} × 3 Transfe r1 r ate × 2 − {−Cb × Rb × ln (1 − 2V.b2 )} Baud rate error (theoretical value) = × 100 [%] 1 ( ) × Number of transferred bits Transfer rate * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V 1 Maximum transfer rate = [bps] 2.0 {−Cb × Rb × ln (1 − Vb )} × 3 Transfe r1 r ate × 2 − {−Cb × Rb × ln (1 − 2V.0b )} Baud rate error (theoretical value) = × 100 [%] 1 ( ) × Number of transferred bits Transfer rate * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. R01DS0157EJ0210 Rev.2.10 Page 101 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 5. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ EVDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V 1 Maximum transfer rate = [bps] 1.5 {−Cb × Rb × ln (1 − Vb )} × 3 Transfe r1 r ate × 2 − {−Cb × Rb × ln (1 − 1V.b5 )} Baud rate error (theoretical value) = × 100 [%] 1 ( ) × Number of transferred bits Transfer rate * This value is the theoretical value of the relative difference between the transmission and reception sides. 6. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32- to 52-pin products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78 microcontroller User's device RxDq Tx R01DS0157EJ0210 Rev.2.10 Page 102 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0, 1), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0157EJ0210 Rev.2.10 Page 103 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 600 ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 600 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 2300 ns Cb = 30 pF, Rb = 5.5 kΩ SCKp high-level width tKH1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 150 ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 340 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 − 916 ns Cb = 30 pF, Rb = 5.5 kΩ SCKp low-level width tKL1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 24 ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 36 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 − 100 ns Cb = 30 pF, Rb = 5.5 kΩ Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32- to 52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0157EJ0210 Rev.2.10 Page 104 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SIp setup time tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 162 ns (to SCKp↑) Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 354 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 958 ns Cb = 30 pF, Rb = 5.5 kΩ SIp hold time tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 38 ns (from SCKp↑) Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 38 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 38 ns Cb = 30 pF, Rb = 5.5 kΩ Delay time from SCKp↓ to tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 200 ns SOp output Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 390 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 966 ns Cb = 30 pF, Rb = 2.7 kΩ SIp setup time tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 88 ns (to SCKp↓) Note Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 88 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 220 ns Cb = 30 pF, Rb = 5.5 kΩ SIp hold time tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 38 ns (from SCKp↓) Note 2 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 38 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 38 ns Cb = 30 pF, Rb = 5.5 kΩ Delay time from SCKp↑ to tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 50 ns SOp output Note 2 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 50 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 50 ns Cb = 30 pF, Rb = 5.5 kΩ (Notes, Caution and Remarks are listed on the page after the next page.) R01DS0157EJ0210 Rev.2.10 Page 105 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32- to 52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Master> Vb Vb Rb Rb SCKp SCK RL78 SIp SO User's device microcontroller SOp SI Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0157EJ0210 Rev.2.10 Page 106 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 tKSI1 SIp Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKH1 tKL1 SCKp tSIK1 tKSI1 SIp Input data tKSO1 SOp Output data Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) R01DS0157EJ0210 Rev.2.10 Page 107 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD ≤ 5.5 V, 20 MHz < fMCK ≤ 24 MHz 24/fMCK ns 2.7 V ≤ Vb ≤ 4.0 V 8 MHz < fMCK ≤ 20 MHz 20/fMCK ns 4 MHz < fMCK ≤ 8 MHz 16/fMCK ns fMCK ≤ 4 MHz 12/fMCK ns 2.7 V ≤ EVDD < 4.0 V, 20 MHz < fMCK ≤ 24 MHz 32/fMCK ns 2.3 V ≤ Vb ≤ 2.7 V 16 MHz < fMCK ≤ 20 MHz 28/fMCK ns 8 MHz < fMCK ≤ 16 MHz 24/fMCK ns 4 MHz < fMCK ≤ 8 MHz 16/fMCK ns fMCK ≤ 4 MHz 12/fMCK ns 2.4 V ≤ EVDD < 3.3 V, 20 MHz < fMCK ≤ 24 MHz 72/fMCK ns 1.6 V ≤ Vb ≤ 2.0 V 16 MHz < fMCK ≤ 20 MHz 64/fMCK ns 8 MHz < fMCK ≤ 16 MHz 52/fMCK ns 4 MHz < fMCK ≤ 8 MHz 32/fMCK ns fMCK ≤ 4 MHz 20/fMCK ns SCKp high-/low-level width tKH2, 4.0 V ≤ EVDD ≤ 5.5 V, tKCY2/2 − 24 ns tKL2 2.7 V ≤ Vb ≤ 4.0 V 2.7 V ≤ EVDD < 4.0 V, tKCY2/2 − 36 ns 2.3 V ≤ Vb ≤ 2.7 V 2.4 V ≤ EVDD < 3.3 V, tKCY2/2 − 100 ns 1.6 V ≤ Vb ≤ 2.0 V SIp setup time tSIK2 4.0 V ≤ EVDD < 5.5 V, 1/fMCK + 40 ns (to SCKp↑) Note2 2.7 V ≤ Vb ≤ 4.0 V 2.7 V ≤ EVDD < 4.0 V, 1/fMCK + 40 ns 2.3 V ≤ Vb ≤ 2.7 V 2.4 V ≤ EVDD < 3.3 V, 1/fMCK + 60 ns 1.6 V ≤ Vb ≤ 2.0 V SIp hold time tKSI2 4.0 V ≤ EVDD < 5.5 V, 1/fMCK + 62 ns (from SCKp↑) Note 3 2.7 V ≤ Vb ≤ 4.0 V 2.7 V ≤ EVDD < 4.0 V, 1/fMCK + 62 ns 2.3 V ≤ Vb ≤ 2.7 V 2.4 V ≤ EVDD < 3.3 V, 1/fMCK + 62 ns 1.6 V ≤ Vb ≤ 2.0 V Delay time from SCKp↓ to tKSO2 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 2/fMCK + 240 ns SOp output Note 4 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 2/fMCK + 428 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V 2/fMCK + 1146 ns Cb = 30 pF, Rb = 5.5 kΩ (Notes, Caution and Remarks are listed on the page after the next page.) R01DS0157EJ0210 Rev.2.10 Page 108 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance (32- to 52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp SCK RL78 SIp SO User's device microcontroller SOp SI Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) R01DS0157EJ0210 Rev.2.10 Page 109 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 SIp Input data tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp tSIK2 tKSI2 SIp Input data tKSO2 SOp Output data Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) R01DS0157EJ0210 Rev.2.10 Page 110 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.5.2 Serial interface IICA (1) I2C standard mode (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLA0 clock frequency fSCL Standard mode: 2.7 V ≤ EVDD ≤ 5.5 V 0 100 kHz fCLK ≥ 1 MHz 2.4 V ≤ EVDD ≤ 5.5 V 0 100 kHz Setup time of restart condition tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.7 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.7 μs Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.0 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.0 μs Hold time when SCLA0 = “L” tLOW 2.7 V ≤ EVDD ≤ 5.5 V 4.7 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.7 μs Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 4.0 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.0 μs Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 250 ns 2.4 V ≤ EVDD ≤ 5.5 V 250 ns Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 3.45 μs 2.4 V ≤ EVDD ≤ 5.5 V 0 3.45 μs Setup time of stop condition tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 4.0 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.0 μs Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 4.7 μs 2.4 V ≤ EVDD ≤ 5.5 V 4.7 μs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ R01DS0157EJ0210 Rev.2.10 Page 111 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) I2C fast mode (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLA0 clock frequency fSCL Fast mode: 2.7 V ≤ EVDD ≤ 5.5 V 0 400 kHz fCLK ≥ 3.5 MHz 2.4 V ≤ EVDD ≤ 5.5 V 0 400 Setup time of restart condition tSU:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 μs 2.4 V ≤ EVDD ≤ 5.5 V 0.6 Hold time Note 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.6 μs 2.4 V ≤ EVDD ≤ 5.5 V 0.6 Hold time when SCLA0 = “L” tLOW 2.7 V ≤ EVDD ≤ 5.5 V 1.3 μs 2.4 V ≤ EVDD ≤ 5.5 V 1.3 Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 0.6 μs 2.4 V ≤ EVDD ≤ 5.5 V 0.6 Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 100 ns 2.4 V ≤ EVDD ≤ 5.5 V 100 Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 0.9 μs 2.4 V ≤ EVDD ≤ 5.5 V 0 0.9 Setup time of stop condition tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 0.6 μs 2.4 V ≤ EVDD ≤ 5.5 V 0.6 Bus-free time tBUF 2.7 V ≤ EVDD ≤ 5.5 V 1.3 μs 2.4 V ≤ EVDD ≤ 5.5 V 1.3 Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 kΩ R01DS0157EJ0210 Rev.2.10 Page 112 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6 Analog Characteristics 3.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = AVREFP Reference voltage (+) = VDD Reference voltage (+) = VBGR Input channel Reference voltage (−) = AVREFM Reference voltage (−) = VSS Reference voltage (−) = AVREFM ANI0, ANI1 − Refer to 3.6.1 (3). Refer to 3.6.1 (4). ANI16 to ANI23 Refer to 3.6.1 (2). Internal reference voltage Refer to 3.6.1 (1). − Temperature sensor output voltage (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : internal reference voltage, and temperature sensor output voltage (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 V 1.2 ±3.5 LSB AVREFP = VDD Note 3 Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.375 39 μs Target pin: Internal reference 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 μs voltage, and temperature 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs sensor output voltage (HS (high-speed main) mode) Zero-scale errorNotes 1, 2 EZS 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR AVREFP = VDD Note 3 Full-scale errorNotes 1, 2 EFS 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR AVREFP = VDD Note 3 Integral linearity error ILE 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±2.5 LSB Note 1 AVREFP = VDD Note 3 Differential linearity error DLE 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V ±1.5 LSB Note 1 AVREFP = VDD Note 3 Analog input voltage VAIN Internal reference voltage VBGR Note 4 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage VTMPS25 Note 4 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0157EJ0210 Rev.2.10 Page 113 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI23 (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB AVREFP = EVDD = VDD Note 3 Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 μs AVREFP = EVDD = VDD Note 3 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs Zero-scale errorNotes 1, 2 EZS 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR AVREFP = EVDD = VDD Note 3 Full-scale errorNotes 1, 2 EFS 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR AVREFP = EVDD = VDD Note 3 Integral linearity errorNote 1 ILE 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB AVREFP = EVDD = VDD Note 3 Differential linearity error DLE 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB Note 1 AVREFP = EVDD = VDD Note 3 Analog input voltage VAIN ANI16 to ANI23 0 AVREFP V and EVDD Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < EVDD = VDD, the MAX. values are as follows. Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD. R01DS0157EJ0210 Rev.2.10 Page 114 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0), target pin : ANI0, ANI1, ANI16 to ANI23, internal reference voltage, and temperature sensor output voltage (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.375 39 μs Target pin: Internal reference 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 μs voltage, and temperature sensor output voltage (HS 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs (high-speed main) mode) Zero-scale errorNotes 1, 2 EZS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Integral linearity errorNote 1 ILE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±4.0 LSB Differential linearity error DLE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Note 1 Analog input voltage VAIN ANI0, ANI1 0 VDD V ANI16 to ANI23 0 EVDD V Internal reference voltage output VBGR Note 3 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage VTMPS25 Note 3 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0157EJ0210 Rev.2.10 Page 115 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI16 to ANI23 (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (−) = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 bit Conversion time tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 17 39 μs Zero-scale errorNotes 1, 2 EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±1.0 LSB Analog input voltage VAIN 0 VBGR Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (−) = VSS, the MAX. values are as follows. Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (−) = AVREFM. Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (−) = AVREFM. Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (−) = AVREFM. R01DS0157EJ0210 Rev.2.10 Page 116 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6.2 Temperature sensor/internal reference voltage characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V Temperature coefficient FVTMPS Temperature sensor that depends on the −3.6 mV/°C temperature Operation stabilization wait time tAMP 5 μs 3.6.3 POR circuit characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR Power supply rise time 1.45 1.51 1.57 V VPDR Power supply fall time 1.44 1.50 1.56 V Minimum pulse width TPW 300 μs Note Minimum time required for a POR reset when V exceeds below V . This is also the minimum time required for a DD PDR POR reset from when V exceeds below 0.7 V to when V exceeds V while STOP mode is entered or the main DD DD POR system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0157EJ0210 Rev.2.10 Page 117 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6.4 LVD circuit characteristics (TA = −40 to +105°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection Supply voltage level VLVD0 Power supply rise time 3.90 4.06 4.22 V voltage Power supply fall time 3.83 3.98 4.13 V VLVD1 Power supply rise time 3.60 3.75 3.90 V Power supply fall time 3.53 3.67 3.81 V VLVD2 Power supply rise time 3.01 3.13 3.25 V Power supply fall time 2.94 3.06 3.18 V VLVD3 Power supply rise time 2.90 3.02 3.14 V Power supply fall time 2.85 2.96 3.07 V VLVD4 Power supply rise time 2.81 2.92 3.03 V Power supply fall time 2.75 2.86 2.97 V VLVD5 Power supply rise time 2.70 2.81 2.92 V Power supply fall time 2.64 2.75 2.86 V VLVD6 Power supply rise time 2.61 2.71 2.81 V Power supply fall time 2.55 2.65 2.75 V VLVD7 Power supply rise time 2.51 2.61 2.71 V Power supply fall time 2.45 2.55 2.65 V Minimum pulse width tLW 300 μs Detection delay time 300 μs LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +105°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V mode VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.81 2.92 3.03 V Falling interrupt voltage 2.75 2.86 2.97 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.90 3.02 3.14 V Falling interrupt voltage 2.85 2.96 3.07 V VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.90 4.06 4.22 V Falling interrupt voltage 3.83 3.98 4.13 V 3.6.5 Power supply voltage rising slope characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 31.4 AC Characteristics. R01DS0157EJ0210 Rev.2.10 Page 118 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.7 LCD Characteristics 3.7.1 Resistance division method (1) Static display mode (TA = −40 to +105°C, VL4 (MIN.) ≤ VDDNote ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.0 VDD V Note Must be 2.4 V or higher. (2) 1/2 bias method, 1/4 bias method (TA = −40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.7 VDD V (3) 1/3 bias method (TA = −40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage VL4 2.5 VDD V R01DS0157EJ0210 Rev.2.10 Page 119 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.7.2 Internal voltage boosting method (1) 1/3 bias method (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD output voltage variation range VL1 C1 to C4Note 1 VLCD = 04H 0.90 1.00 1.08 V = 0.47 μF VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V Doubler output voltage VL2 C1 to C4Note 1 = 0.47 μF 2 VL1 2 VL1 2 VL1 V −0.1 Tripler output voltage VL4 C1 to C4Note 1 = 0.47 μF 3 VL1 3 VL1 3 VL1 V −0.15 Reference voltage setup time Note 2 tVWAIT1 5 ms Voltage boost wait timeNote 3 tVWAIT2 C1 to C4Note 1 = 0.47 μF 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between V and GND L1 C3: A capacitor connected between V and GND L2 C4: A capacitor connected between V and GND L4 C1 = C2 = C3 = C4 = 0.47 μF±30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). R01DS0157EJ0210 Rev.2.10 Page 120 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) 1/4 bias method (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD output voltage variation range VL1 Note 4 C1 to C5Note 1 VLCD = 04H 0.90 1.00 1.08 V = 0.47 μF VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V Doubler output voltage VL2 C1 to C5Note 1 = 0.47 μF 2 VL1 − 0.08 2 VL1 2 VL1 V Tripler output voltage VL3 C1 to C5Note 1 = 0.47 μF 3 VL1 − 0.12 3 VL1 3 VL1 V Quadruply output voltage VL4 Note 4 C1 to C5Note 1 = 0.47 μF 4 VL1 − 0.16 4 VL1 4 VL1 V Reference voltage setup time Note 2 tVWAIT1 5 ms Voltage boost wait timeNote 3 tVWAIT2 C1 to C5Note 1 = 0.47 μF 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between V and GND L1 C3: A capacitor connected between V and GND L2 C4: A capacitor connected between V and GND L3 C5: A capacitor connected between V and GND L4 C1 = C2 = C3 = C4 = C5 = 0.47 μF±30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). 4. VL4 must be 5.5 V or lower. R01DS0157EJ0210 Rev.2.10 Page 121 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.7.3 Capacitor split method 1/3 bias method (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VL4 voltage VL4 C1 to C4 = 0.47 μ FNote 2 VDD V VL2 voltage VL2 C1 to C4 = 0.47 μ FNote 2 2/3 VL4 2/3 VL4 2/3 VL4 V − 0.1 + 0.1 VL1 voltage VL1 C1 to C4 = 0.47 μ FNote 2 1/3 VL4 1/3 VL4 1/3 VL4 V − 0.1 + 0.1 Capacitor split wait timeNote 1 tVWAIT 100 ms Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). 2. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between V and GND L1 C3: A capacitor connected between V and GND L2 C4: A capacitor connected between V and GND L4 C1 = C2 = C3 = C4 = 0.47 μF±30% R01DS0157EJ0210 Rev.2.10 Page 122 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) <R> 3.8 RAM Data Retention Characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage VDDDR 1.44Note 5.5 V <R> Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. STOP mode Operation mode <R> RAM Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 3.9 Flash Memory Programming Characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit System clock frequency fCLK 1.8 V ≤ VDD ≤ 5.5 V 1 24 MHz <R> Number of code flash rewrites Cerwr Retained for 20 years 1,000 Times Notes 1, 2, 3 TA = 85°CNote 4 <R> Number of data flash rewrites Retained for 1 year 1,000,000 Notes 1, 2, 3 TA = 25°CNote 4 <R> Retained for 5 years 100,000 TA = 85°CNote 4 <R> Retained for 20 years 10,000 TA = 85°CNote 4 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test. <R> 4. This temperature is the average value at which data are retained. 3.10 Dedicated Flash Memory Programmer Communication (UART) (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate During flash memory programming 115,200 1,000,000 bps R01DS0157EJ0210 Rev.2.10 Page 123 of 131 Sep 30, 2016

RL78/L12 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.11 Timing Specifications for Switching Flash Memory Programming Modes (TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication tSUINIT POR and LVD reset must be released before 100 ms for the initial setting after the external the external reset is released. reset is released Time to release the external reset tSU POR and LVD reset must be released before 10 μ s after the TOOL0 pin is set to the low the external reset is released. level Time to hold the TOOL0 pin at the tHD POR and LVD reset must be released before 1 ms low level after the external reset is the external reset is released. released (excluding the processing time of the firmware to control the flash memory) <1> <2> <3> <4> RESET tHD+ soft processing 1-byte data for mode setting time TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released during this period. t : Time to release the external reset after the TOOL0 pin is set to the low level SU tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0157EJ0210 Rev.2.10 Page 124 of 131 Sep 30, 2016

RL78/L12 4. PACKAGE DRAWINGS 4. PACKAGE DRAWINGS 4.1 32-pin Products R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP R5F10RB8GFP, R5F10RBAGFP, R5F10RBCGFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT-1 0.2 HD 2 D 24 17 25 16 detail of lead end 1 c E HE θ L 32 9 1 8 e (UNIT:mm) 3 b x M ITEM DIMENSIONS D 7.00±0.10 A E 7.00±0.10 A2 HD 9.00±0.20 HE 9.00±0.20 A 1.70 MAX. A1 0.10±0.10 A2 1.40 b 0.37±0.05 y A1 c 0.145±0.055 L 0.50±0.20 θ 0° to 8° NOTE e 0.80 1.Dimensions “ 1” and “ 2” do not include mold flash. x 0.20 2.Dimension “ 3” does not include trim offset. y 0.10 R01DS0157EJ0210 Rev.2.10 Page 125 of 131 Sep 30, 2016

RL78/L12 4. PACKAGE DRAWINGS 4.2 44-pin Products R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP R5F10RF8GFP, R5F10RFAGFP, R5F10RFCGFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP44-10x10-0.80 PLQP0044GC-A P44GB-80-UES-2 0.36 HD D detail of lead end 33 23 A3 34 22 c L E HE Lp L1 (UNIT:mm) 44 12 ITEM DIMENSIONS 1 11 D 10.00±0.20 E 10.00±0.20 HD 12.00±0.20 ZE HE 12.00±0.20 ZD e A 1.60 MAX. A1 0.10±0.05 b x M S A A2 1.40±0.05 A3 0.25 A2 b 0.37+00..0087 S c 0.145+00..005455 L 0.50 Lp 0.60±0.15 y S A1 L1 1.00±0.20 3°+53°° e 0.80 x 0.20 NOTE y 0.10 Each lead centerline is located within 0.20 mm of ZD 1.00 its true position at maximum material condition. ZE 1.00 2012 Renesas Electronics Corporation. All rights reserved. R01DS0157EJ0210 Rev.2.10 Page 126 of 131 Sep 30, 2016

RL78/L12 4. PACKAGE DRAWINGS 4.3 48-pin Products R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB R5F10RG8GFB, R5F10RGAGFB, R5F10RGCGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16 HD D detail of lead end 36 25 A3 37 24 c L E HE Lp L1 48 13 (UNIT:mm) 1 12 ITEM DIMENSIONS D 7.00±0.20 E 7.00±0.20 ZE HD 9.00±0.20 HE 9.00±0.20 ZD e A 1.60 MAX. A1 0.10±0.05 b x M S A A2 1.40±0.05 A3 0.25 A2 b 0.22±0.05 c 0.145+00..005455 L 0.50 S Lp 0.60±0.15 L1 1.00±0.20 3°+53°° y S A1 e 0.50 x 0.08 y 0.08 ZD 0.75 NOTE Each lead centerline is located within 0.08 mm of ZE 0.75 its true position at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved. R01DS0157EJ0210 Rev.2.10 Page 127 of 131 Sep 30, 2016

RL78/L12 4. PACKAGE DRAWINGS 4.4 52-pin Products R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA R5F10RJ8GFA, R5F10RJAGFA, R5F10RJCGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP52-10x10-0.65 PLQP0052JA-A P52GB-65-GBS-1 0.3 HD 2 D 39 27 detail of lead end 40 26 c 1 E HE L 14 52 1 13 e (UNIT:mm) 3 b x M A ITEM DIMENSIONS D 10.00±0.10 A2 E 10.00±0.10 HD 12.00±0.20 HE 12.00±0.20 A 1.70 MAX. A1 0.10±0.05 A2 1.40 y A1 b 0.32±0.05 c 0.145±0.055 L 0.50±0.15 NOTE1.Dimensions “ 1” and “ 2” do not include mold flash. 0° to 8° 2.Dimension “ 3” does not include trim offset. e 0.65 x 0.13 y 0.10 2012 Renesas Electronics Corporation. All rights reserved. R01DS0157EJ0210 Rev.2.10 Page 128 of 131 Sep 30, 2016

RL78/L12 4. PACKAGE DRAWINGS 4.5 64-pin Products R5F10RLAAFA, R5F10RLCAFA R5F10RLAGFA, R5F10RLCGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET-2 0.51 HD D detail of lead end 48 33 49 32 A3 c L E HE Lp L1 (UNIT:mm) ITEM DIMENSIONS D 12.00±0.20 64 17 E 12.00±0.20 1 16 HD 14.00±0.20 HE 14.00±0.20 ZE A 1.60 MAX. A1 0.10±0.05 ZD e A2 1.40±0.05 b x M S A3 0.25 A b 0.32+00..0087 A2 c 0.145+00..005455 L 0.50 Lp 0.60±0.15 S L1 1.00±0.20 3°+53°° y S A1 e 0.65 x 0.13 y 0.10 ZD 1.125 NOTE ZE 1.125 Each lead centerline is located within 0.13 mm of its true position at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved. R01DS0157EJ0210 Rev.2.10 Page 129 of 131 Sep 30, 2016

RL78/L12 4. PACKAGE DRAWINGS R5F10RLAAFB, R5F10RLCAFB R5F10RLAGFB, R5F10RLCGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP64-10x10-0.50 PLQP0064KF-A P64GB-50-UEU-2 0.35 HD D detail of lead end 48 33 A3 49 32 c L E HE Lp L1 (UNIT:mm) 64 17 ITEM DIMENSIONS D 10.00±0.20 1 16 E 10.00±0.20 HD 12.00±0.20 ZE HE 12.00±0.20 A 1.60 MAX. ZD e A1 0.10±0.05 A2 1.40±0.05 b x M S A3 0.25 A b 0.22±0.05 A2 c 0.145+00..005455 L 0.50 Lp 0.60±0.15 S L1 1.00±0.20 3°+53°° y S A1 e 0.50 x 0.08 y 0.08 ZD 1.25 NOTE ZE 1.25 Each lead centerline is located within 0.08 mm of its true position at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved. R01DS0157EJ0210 Rev.2.10 Page 130 of 131 Sep 30, 2016

RL78/L12 4. PACKAGE DRAWINGS R5F10RLAANB, R5F10RLCANB R5F10RLAGNB, R5F10RLCGNB <R> JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-HWQFN64-8x8-0.40 PWQN0064LA-A P64K8-40-9B5-4 0.16 Unit: mm D 48 33 49 32 DETAIL OF A PART E A 64 17 A1 c2 1 16 INDEX AREA A S y S D2 Lp A EXPOSED DIE PAD Reference Dimensions in millimeters Symbol Min Nom Max 1 16 D 7.95 8.00 8.05 64 17 E 7.95 8.00 8.05 A — — 0.80 B A1 0.00 — — E2 b 0.17 0.20 0.23 e — 0.40 — ZE Lp 0.30 0.40 0.50 49 32 x — — 0.05 y — — 0.05 48 33 ZD e ZD — 1.00 — ZE — 1.00 — b M S A B x c2 0.15 0.20 0.25 D2 — 6.50 — E2 — 6.50 — © 2015 Renesas Electronics Corporation. All rights reserved. R01DS0157EJ0210 Rev.2.10 Page 131 of 131 Sep 30, 2016

Revision History RL78/L12 Datasheet Description Rev. Date Page Summary 0.01 Feb 20, 2012 - First Edition issued 0.02 Sep 26, 2012 7, 8 Modification of caution 2 in 1.3.5 64-pin products 15 Modification of I/O port in 1.6 Outline of Functions - Modification of 2. ELECTRICAL SPECIFICATIONS (TARGET) - Update of package drawings in 3. PACKAGE DRAWINGS 1.00 Jan 31, 2013 11 to 15 Modification of 1.5 Block Diagram 16 Modification of Note 2 in 1.6 Outline of Functions 17 Modification of 1.6 Outline of Functions - Deletion of target in 2. ELECTRICAL SPECIFICATIONS 18 Addition of caution 2 to 2. ELECTRICAL SPECIFICATIONS 19 Addition of description, note 3, and remark 2 to 2.1 Absolute Maximum Ratings 20 Modification of description and addition of note to 2.1 Absolute Maximum Ratings 22, 23 Modification of 2.2 Oscillator Characteristics 30 Modification of notes 1 to 4 in 2.3.2 Supply current characteristics 32 Modification of notes 1, 3 to 6, 8 in 2.3.2 Supply current characteristics 34 Modification of notes 7, 9, 11, and addition of notes 8, 12 to 2.3.2 Supply current characteristics 36 Addition of description to 2.4 AC Characteristics 38, 40 to Modification of 2.5.1 Serial array unit 42, 44 to 46, 48 to 52, 54, 55 57, 58 Modification of 2.5.2 Serial interface IICA 62 Modification of 2.6.2 Temperature sensor/internal reference voltage characteristics 64 Addition of note and caution in 2.6.5 Supply voltage rise time 69 Modification of 2.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics 69 Modification of conditions in 2.9 Timing Specs for Switching Flash Memory Programming Modes 70 Modification of 2.10 Timing Specifications for Switching Flash Memory Programming Modes 2.00 Jan 10, 2014 1 Modification of 1.1 Features 3 Modification of Figure 1-1 4 Modification of part number, note, and caution 5 to 10 Deletion of COMEXP pin in 1.3.1 to 1.3.5. 11 Modification of description in 1.4 Pin Identification 12 to 16 Deletion of COMEXP pin in 1.5.1 to 1.5.5 17 Modification of table and note 2 in 1.6 Outline of Functions 20 Modification of description in Absolute Maximum Ratings (TA = 25°C) (1/3) 21 Modification of description and note 2 in Absolute Maximum Ratings (TA = 25°C) (2/3) 23 Modification of table, note, caution, and remark in 2.2.1 X1, XT1 oscillator characteristics 23 Modification of table in 2.2.2 On-chip oscillator characteristics 24 Modification of table, notes 2 and 3 in 2.3.1 Pin characteristics (1/5) 25 Modification of notes 1 and 3 in 2.3.1 Pin characteristics (2/5) 30 Modification of notes 1 and 4 in 2.3.2 Supply current characteristics (1/3) 31, 32 Modification of table, notes 1, 5, and 6 in 2.3.2 Supply current characteristics (2/3) 33, 34 Modification of table, notes 1, 3, 4, and 5 to 10 in 2.3.2 Supply current characteristics (3/3) C - 1

Description Rev. Date Page Summary 2.00 Jan 10, 2014 35 Modification of table in 2.4 AC Characteristics 36 Addition of Minimum Instruction Execution Time during Main System Clock Operation 37 Modification of AC Timing Test Points and External System Clock Timing 39 Modification of AC Timing Test Points 39 Modification of description, notes 1 and 2 in (1) During communication at same potential (UART mode) 41, 42 Modification of description, remark 2 in (2) During communication at same potential (CSI mode) 42, 43 Modification of description in (3) During communication at same potential (CSI mode) 45 Modification of description, notes 1 and 3, and remark 3 in (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) 46, 48 Modification of description, and remark 3 in (4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) 49, 50 Modification of table, and note 1, caution, and remark 3 in (5) Communication at different potential (2.5 V, 3 V) (CSI mode) 51 Modification of table and note in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (1/3) 52 Modification of table and notes 1 to 3 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (2/3) 53, 54 Modification of table, note 3, and remark 3 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (3/3) 56 Modification of table in (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (1/2) 57 Modification of table in (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/2) 59, 60 Addition of (1) I2C standard mode 61 Addition of (2) I2C fast mode 62 Addition of (3) I2C fast mode plus 63 Addition of table in 2.6.1 A/D converter characteristics 63, 64 Modification of description and notes 3 to 5 in 2.6.1 (1) 65 Modification of description, notes 3 and 4 in 2.6.1 (2) 66 Modification of description, notes 3 and 4 in 2.6.1 (3) 67 Modification of description, notes 3 and 4 in 2.6.1 (4) 67 Modification of the table in 2.6.2 Temperature sensor/internal reference voltage characteristics 68 Modification of the table and note in 2.6.3 POR circuit characteristics 70 Modification of the table of LVD Detection Voltage of Interrupt & Reset Mode 70 Modification from VDD rise slope to Power supply voltage rising slope in 2.6.5 Supply voltage rise time 75 Modification of description in 2.10 Dedicated Flash Memory Programmer Communication (UART) 76 Modification of the figure in 2.11 Timing Specifications for Switching Flash Memory Programming Modes 77 to 126 Addition of products for industrial applications (G: TA = -40 to +105°C) 127 to 133 Addition of product names for industrial applications (G: TA = -40 to +105°C) 2.10 Sep 30, 2016 5 Modification of pin configuration in 1.3.1 32-pin products 6 Modification of pin configuration in 1.3.2 44-pin products 7 Modification of pin configuration in 1.3.3 48-pin products 8 Modification of pin configuration in 1.3.4 52-pin products 9, 10 Modification of pin configuration in 1.3.5 64-pin products 17 Modification of description of main system clock in 1.6 Outline of Functions 74 Modification of title of 2.8 RAM Data Retention Characteristics, Note, and figure 74 Modification of table of 2.9 Flash Memory Programming Characteristics 123 Modification of title of 3.8 RAM Data Retention Characteristics, Note, and figure 123 Modification of table of 3.9 Flash Memory Programming Characteristics and addition of Note 4 131 Modification of 4.5 64-pin Products C - 2

The mark “<R>” shows major revised points. The revised points can be easily searched by copying an “<R>” in the PDF file and specifying it in the “Find what:” field. All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. C - 3

NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

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