PIC32MX3XX/4XX Data Sheet High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers © 2011 Microchip Technology Inc. DS61143H

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-149-0 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS61143H-page 2 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX High-Performance, General Purpose and USB 32-bit Flash Microcontrollers High-Performance 32-bit RISC CPU: • Separate PLLs for CPU and USB clocks • Two I2C™ modules • MIPS32® M4K® 32-bit core with 5-stage pipeline • Two UART modules with: • 80 MHz maximum frequency - RS-232, RS-485 and LIN support • 1.56 DMIPS/MHz (Dhrystone 2.1) performance at - IrDA® with on-chip hardware encoder and 0 wait state Flash access decoder • Single-cycle multiply and high-performance divide • Up to two SPI modules unit • MIPS16e® mode for up to 40% smaller code size • Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit data and up to 16 address lines • Two sets of 32 core register files (32-bit) to reduce • Hardware Real-Time Clock and Calendar (RTCC) interrupt latency • Five 16-bit Timers/Counters (two 16-bit pairs • Prefetch Cache module to speed execution from combine to create two 32-bit timers) Flash • Five capture inputs Microcontroller Features: • Five compare/PWM outputs • Five external interrupt pins • Operating temperature range of -40ºC to +105ºC • High-Speed I/O pins capable of toggling at up to • Operating voltage range of 2.3V to 3.6V 80 MHz • 32K to 512K Flash memory (plus an additional • High-current sink/source (18 mA/18 mA) on all I/O 12 KB of boot Flash) pins • 8K to 32K SRAM memory • Configurable open-drain output on digital I/O pins • Pin-compatible with most PIC24/dsPIC® DSC devices Debug Features: • Multiple power management modes • Two programming and debugging Interfaces: • Multiple interrupt vectors with individually programmable priority - 2-wire interface with unintrusive access and real-time data exchange with application • Fail-Safe Clock Monitor Mode - 4-wire MIPS® standard enhanced JTAG • Configurable Watchdog Timer with on-chip interface Low-Power RC Oscillator for reliable operation • Unintrusive hardware-based instruction trace Peripheral Features: • IEEE Standard 1149.2-compatible (JTAG) boundary scan • Atomic SET, CLEAR and INVERT operation on select peripheral registers Analog Features: • Up to 4-channel hardware DMA with automatic data size detection • Up to 16-channel 10-bit Analog-to-Digital Converter: • USB 2.0-compliant full-speed device and On-The-Go (OTG) controller - 1000 ksps conversion rate • USB has a dedicated DMA channel - Conversion available during Sleep, Idle • 3 MHz to 25 MHz crystal oscillator • Two Analog Comparators • Internal 8 MHz and 32 kHz oscillators © 2011 Microchip Technology Inc. DS61143H-page 3

PIC32MX3XX/4XX TABLE 1: PIC32MX GENERAL PURPOSE – FEATURES GENERAL PURPOSE e Device Pins (2)Packages MHz ogram Memory (KB) Data Memory (KB) ers/Capture/Compar rogrammable DMA Channels VREG Trace 2C™EUART/SPI/I 10-bit ADC (ch) Comparators PMP/PSP JTAG r m P P Ti PIC32MX320F032H 64 PT, MR 40 32 + 12(1) 8 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PIC32MX320F064H 64 PT, MR 80 64 + 12(1) 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PIC32MX320F128H 64 PT, MR 80 128 + 12(1) 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes PIC32MX340F128H 64 PT, MR 80 128 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes PIC32MX340F256H 64 PT, MR 80 256 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes PIC32MX340F512H 64 PT, MR 80 512 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes 100 PT PIC32MX320F128L 80 128 + 12(1) 16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes 121 BG 100 PT PIC32MX340F128L 80 128 + 12(1) 32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes 121 BG 100 PT PIC32MX360F256L 80 256 + 12(1) 32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes 121 BG 100 PT PIC32MX360F512L 80 512 + 12(1) 32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes 121 BG Legend: PT = TQFP MR = QFN BG = XBGA Note 1: This device features 12 KB Boot Flash memory. 2: See Legend for an explanation of the acronyms. See Section30.0 “Packaging Information” for details. DS61143H-page 4 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 2: PIC32MX USB – FEATURES USB e Device Pins (2)Packages MHz ogram Memory (KB) Data Memory (KB) ers/Capture/Compar rogrammable DMA Channels edicated USB DMA Channels VREG Trace 2EUART/SPI/IC™ 10-bit ADC (ch) Comparators PMP/PSP JTAG r m P D P Ti PIC32MX420F032H 64 PT, MR 40 32 + 12(1) 8 5/5/5 0 2 Yes No 2/1/2 16 2 Yes Yes PIC32MX440F128H 64 PT, MR 80 128 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes PIC32MX440F256H 64 PT, MR 80 256 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes PIC32MX440F512H 64 PT, MR 80 512 + 12(1) 32 5/5/5 4 2 Yes No 2/1/2 16 2 Yes Yes 100 PT PIC32MX440F128L 121 BG 80 128 + 12(1) 32 5/5/5 4 2 Yes No 2/2/2 16 2 Yes Yes 100 PT PIC32MX460F256L 121 BG 80 256 + 12(1) 32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes 100 PT PIC32MX460F512L 121 BG 80 512 + 12(1) 32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes Legend: PT = TQFP MR = QFN BG = XBGA Note 1: This device features 12 KB Boot Flash memory. 2: See Legend for an explanation of the acronyms. See Section30.0 “Packaging Information” for details. © 2011 Microchip Technology Inc. DS61143H-page 5

PIC32MX3XX/4XX Pin Diagrams 64-Pin QFN (General Purpose) = Pins are up to 5V tolerant 4 D R 3/ 1 N 5C DR/ RW MD4/RE4MD3/RE3MD2/RE2 MD1/RE1MD0/RE0F1F0 NVREG/VCAPCOREN16/RD7N15/RD6 MRD/CN14/C5/IC5/PMC4/RD3 C3/RD2C2/RD1 PPP PPRR EVCC POO OO 64636261605958575655545352515049 PMD5/RE5 1 48 SOSCO/T1CK/CN0/RC14 PMD6/RE6 2 47 SOSCI/CN1/RC13 PMD7/RE7 3 46 OC1/RD0 SCK2/PMA5/CN8/RG6 4 45 IC4/PMCS1/PMA14/INT4/RD11 SDI2/PMA4/CN9/RG7 5 44 IC3/PMCS2/PMA15/INT3/RD10 SDO2/PMA3/CN10/RG8 6 PIC32MX320F032H 43 U1CTS/IC2/INT2/RD9 MCLR 7 PIC32MX320F064H 42 RTCC/IC1/INT1/RD8 SS2/PMA2/CN11/RG9 8 41 Vss PIC32MX320F128H VSS 9 PIC32MX340F128H 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKI/RC12 PIC32MX340F256H AN5/C1IN+/CN7/RB5 11 38 VDD PIC32MX340F512H AN4/C1IN-/CN6/RB4 12 37 SCL1/RG2 AN3/C2IN+/CN5/RB3 13 36 SDA1/RG3 AN2/C2IN-/SS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16 33 U1TX/SDO1/RF3 17181920212223242526272829303132 RB6RB7VDD VSSRB8RB9B10B11VSSVDD B12B13B14B15 RF4RF5 PGEC2/AN6/OCFA/PGED2/AN7/AAAN8/U2CTS/C1OUT/AN9/C2OUT/PMA7/S/AN10/CV/PMA13/RREFOUT TDO/AN11/PMA12/R TCK/AN12/PMA11/RTDI/AN13/PMA10/RN14/U2RTS/PMALH/PMA1/ROCFB/PMALL/PMA0/CN12/R SDA2/U2RX/PMA9/CN17/SCL2/U2TX/PMA8/CN18/ TM A15/ N A Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61143H-page 6 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Pin Diagrams (Continued) 64-Pin TQFP (General Purpose) = Pins are up to 5V tolerant 4 D R 3/ 1 N 5C DR/ RW MD4/RE4MD3/RE3MD2/RE2MD1/RE1MD0/RE0F1F0NVREG/VCAPCOREN16/RD7N15/RD6MRD/CN14/C5/IC5/PMC4/RD3C3/RD2C2/RD1 PPPPPRREVCCPOOOO 4321098765432109 6666655555555554 PMD5/RE5 1 48 SOSCO/T1CK/CN0/RC14 PMD6/RE6 2 47 SOSCI/CN1/RC13 PMD7/RE7 3 46 OC1/RD0 SCK2/PMA5/CN8/RG6 4 45 IC4/PMCS1/PMA14/INT4/RD11 SDI2/PMA4/CN9/RG7 5 44 IC3/PMCS2/PMA15/INT3/RD10 SDO2/PMA3/CN10/RG8 6 PIC32MX320F032H 43 U1CTS/IC2/INT2/RD9 MCLR 7 PIC32MX320F064H 42 RTCC/IC1/INT1/RD8 SS2/PMA2/CN11/RG9 8 PIC32MX320F128H 41 Vss VSS 9 PIC32MX340F128H 40 OSC2/CLKO/RC15 VDD 10 PIC32MX340F256H 39 OSC1/CLKI/RC12 AN5/C1IN+/CN7/RB5 11 PIC32MX340F512H 38 VDD AN4/C1IN-/CN6/RB4 12 37 SCL1/RG2 AN3/C2IN+/CN5/RB3 13 36 SDA1/RG3 AN2/C2IN-/SS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16 33 U1TX/SDO1/RF3 7890123456789012 1112222222222333 RB6RB7VDD VSSRB8RB9B10B11VSSVDD B12B13B14B15 RF4RF5 PGEC2/AN6/OCFA/PGED2/AN7/AAAN8/U2CTS/C1OUT/AN9/C2OUT/PMA7/S/AN10/CV/PMA13/RREFOUT TDO/AN11/PMA12/R TCK/AN12/PMA11/RTDI/AN13/PMA10/RN14/U2RTS/PMALH/PMA1/ROCFB/PMALL/PMA0/CN12/R SDA2/U2RX/PMA9/CN17/SCL2/U2TX/PMA8/CN18/ TM A15/ N A © 2011 Microchip Technology Inc. DS61143H-page 7

PIC32MX3XX/4XX Pin Diagrams (Continued) 100-Pin TQFP (General Purpose) = Pins are up to 5V tolerant 4 D PMD4/RE4PMD3/RE3PMD2/RE2TRD0/RG13TRD1/RG12TRD2/RG14PMD1/RE1PMD0/RE0TRD3/RA7TRCLK/RA6PMD8/RG0PMD9/RG1PMD10/RF1PMD11/RF0ENVREGV/VCAPCOREPMD15/CN16/RD7PMD14/CN15/RD6PMRD/CN14/RD5OC5/PMWR/CN13/RPMD13/CN19/RD13IC5/PMD12/RD12OC4/RD3OC3/RD2OC2/RD1 0987654321098765432109876 RG15 1 1099999999998888888888777775 VSS VDD 2 74 SOSCO/T1CK/CN0/RC14 PMD5/RE5 3 73 SOSCI/CN1/RC13 PMD6/RE6 4 72 OC1/RD0 PMD7/RE7 5 71 IC4/PMCS1/PMA14/RD11 T2CK/RC1 6 70 IC3/PMCS2/PMA15/RD10 T3CK/RC2 7 69 IC2/RD9 T4CK/RC3 8 68 RTCC/IC1/RD8 T5CK/RC4 9 67 INT4/RA15 SCK2/PMA5/CN8/RG6 10 66 INT3/RA14 SDI2/PMA4/CN9/RG7 11 65 VSS PIC32MX320F128L SDO2/PMA3/CN10/RG8 12 64 OSC2/CLKO/RC15 PIC32MX340F128L MCLR 13 63 OSC1/CLKI/RC12 PIC32MX360F256L PMA2/SS2/CN11/RG9 14 62 VDD VSS 15 PIC32MX360F512L 61 TDO/RA5 VDD 16 60 TDI/RA4 TMS/RA0 17 59 SDA2/RA3 INT1/RE8 18 58 SCL2/RA2 INT2/RE9 19 57 SCL1/RG2 AN5/C1IN+/CN7/RB5 20 56 SDA1/RG3 AN4/C1IN-/CN6/RB4 21 55 SCK1/INT0/RF6 AN3/C2IN+/CN5/RB3 22 54 SDI1/RF7 AN2/C2IN-/SS1/CN4/RB2 23 53 SDO1/RF8 PGEC1/AN1/CN3/RB1 24 52 U1RX/RF2 PGED1/AN0/CN2/RB0 25 51 U1TX/RF3 6789012345678901234567890 2222333333333344444444445 PGEC2/AN6/OCFA/RB6PGED2/AN7/RB7V-/CV-/PMA7/RA9REFREF+/CV+/PMA6/RA10REFREFAVDDAVSSAN8/C1OUT/RB8AN9/C2OUT/RB90/CV/PMA13/RB10REFOUTAN11/PMA12/RB11VSSVDDTCK/RA1U2RTS/RF13U2CTS/RF12AN12/PMA11/RB12AN13/PMA10/RB13AN14/PMALH/PMA1/RB14PMALL/PMA0/CN12/RB15VSSVDDU1CTS/CN20/RD14U1RTS/CN21/RD15U2RX/PMA9/CN17/RF4U2TX/PMA8/CN18/RF5 V N1 B/ A CF O 5/ 1 N A DS61143H-page 8 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Pin Diagrams (Continued) 121-Pin XBGA(1) = Pins are up to 5V tolerant PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L 1 2 3 4 5 6 7 8 9 10 11 A RE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1 B NC RG15 RE2 RE1 RA7 RF0 VCORE/ RD5 RD3 VSS RC14 VCAP C RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 D RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 E RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 F MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 G RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 H RB5 RB4 VSS VDD NC VDD NC RF7 RF6 RG2 RA2 J RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 K RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 L RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Note1: Refer to Table3 for full pin names. © 2011 Microchip Technology Inc. DS61143H-page 9

PIC32MX3XX/4XX TABLE 3: PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND PIC32MX360F512L DEVICES Pin Pin Full Pin Name Full Pin Name Number Number A1 PMD4/RE4 E8 INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 IC2/RD9 A4 PMD0/RE0 E11 INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 PMD10/RF1 F2 SDO2/PMA3/CN10/RG8 A7 ENVREG F3 SS2/PMA2/CN11/RG9 A8 VSS F4 SDI2/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC) B1 No Connect (NC) F8 VDD B2 RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 INT1/RE8 B6 PMD11/RF0 G2 INT2/RE9 B7 VCAP/VCORE G3 TMS/RA0 B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS C1 PMD6/RE6 G8 No Connect (NC) C2 VDD G9 TDO/RA5 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 C5 TRCLK/RA6 H1 AN5/C1IN+/CN7/RB5 C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC) D1 T2CK/RC1 H8 SDI1/RF7 D2 PMD7/RE7 H9 SCK1/INT0/RF6 D3 PMD5/RE5 H10 SCL1/RG2 D4 VSS H11 SCL2/RA2 D5 VSS J1 AN3/C2IN+/CN5/RB3 D6 No Connect (NC) J2 AN2/C2IN-/SS1/CN4/RB2 D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7 D8 PMD13/CN19/RD13 J4 AVDD D9 OC1/RD0 J5 AN11/PMA12/RB11 D10 No Connect (NC) J6 TCK/RA1 D11 IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12 E1 T5CK/RC4 J8 No Connect (NC) E2 T4CK/RC3 J9 No Connect (NC) E3 SCK2/PMA5/CN8/RG6 J10 SDO1/RF8 E4 T3CK/RC2 J11 SDA1/RG3 E5 VDD K1 PGEC1/AN1/CN3/RB1 E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0 E7 VSS K3 VREF+/CVREF+/PMA6/RA10 DS61143H-page 10 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 3: PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND PIC32MX360F512L DEVICES (CONTINUED) Pin Pin Full Pin Name Full Pin Name Number Number K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 U1TX/RF3 L9 CN20/U1CTS/RD14 K11 U1RX/RF2 L10 U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11 U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/PMA7/RA9 © 2011 Microchip Technology Inc. DS61143H-page 11

PIC32MX3XX/4XX Pin Diagrams (Continued) 64-Pin QFN (USB) = Pins are up to 5V tolerant 4 D R 3/ 1 N RD5WR/CD3D2 RD1 MD4/RE4MD3/RE3MD2/RE2MD1/RE1MD0/RE0F1F0NVREG/VCAPCORE N16/RD7N15/RD6MRD/CN14/C5/IC5/PM1TX/OC4/R1RX/OC3/R 1RTS/OC2/ PPPPPRREV CCPOUU U 64636261605958575655545352515049 PMD5/RE5 1 48 SOSCO/T1CK/CN0/RC14 PMD6/RE6 2 47 SOSCI/CN1/RC13 PMD7/RE7 3 46 OC1/INT0/RD0 SCK2/PMA5/CN8/RG6 4 45 IC4/PMCS1/PMA14/INT4/RD11 SDI2/PMA4/CN9/RG7 5 44 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SDO2/PMA3/CN10/RG8 6 43 U1CTS/SDA1/IC2/INT2/RD9 MCLR 7 PIC32MX420F032H 42 RTCC/IC1/INT1/RD8 SS2/PMA2/CN11/RG9 8 PIC32MX440F128H 41 Vss VSS 9 PIC32MX440F256H 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKI/RC12 PIC32MX440F512H AN5/C1IN+/VBUSON/CN7/RB5 11 38 VDD AN4/C1IN-/CN6/RB4 12 37 D+/RG2 AN3/C2IN+/CN5/RB3 13 36 D-/RG3 AN2/C2IN-/CN4/RB2 14 35 VUSB PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15 34 VBUS PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16 33 USBID/RF3 17181920212223242526272829303132 B6B7 DD SSB8B91011 SS DD 12131415F4 F5 RRVVRRBBVVBBBBR R PGEC2/AN6/OCFA/PGED2/AN7/AAAN8/U2CTS/C1OUT/AN9/C2OUT/PMA7/S/AN10/CV/PMA13/RREFOUTTDO/AN11/PMA12//R TCK/AN12/PMA11/RTDI/AN13/PMA10/RN14/U2RTS/PMALH/PMA1/ROCFB/PMALL/PMA0/CN12/RSDA2/U2RX/PMA9/CN17/ SCL2/U2TX/PMA8/CN18/ TM A15/ N A Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61143H-page 12 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Pin Diagrams (Continued) 64-Pin TQFP (USB) = Pins are up to 5V tolerant 4 D R 3/ 1 N RD5WR/CD3D2RD1 MD4/RE4MD3/RE3MD2/RE2MD1/RE1MD0/RE0F1F0NVREG/VCAPCOREN16/RD7N15/RD6MRD/CN14/C5/IC5/PM1TX/OC4/R1RX/OC3/R1RTS/OC2/ PPPPPRREVCCPOUUU 4321098765432109 6666655555555554 PMD5/RE5 1 48 SOSCO/T1CK/CN0/RC14 PMD6/RE6 2 47 SOSCI/CN1/RC13 PMD7/RE7 3 46 OC1/INT0/RD0 SCK2/PMA5/CN8/RG6 4 45 IC4/PMCS1/PMA14/INT4/RD11 SDI2/PMA4/CN9/RG7 5 44 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SDO2/PMA3/CN10/RG8 6 43 U1CTS/SDA1/IC2/INT2/RD9 PIC32MX420F032H MCLR 7 42 RTCC/IC1/INT1/RD8 PIC32MX440F128H SS2/PMA2/CN11/RG9 8 41 Vss VSS 9 PIC32MX440F256H 40 OSC2/CLKO/RC15 VDD 10 PIC32MX440F512H 39 OSC1/CLKI/RC12 AN5/C1IN+/VBUSON/CN7/RB5 11 38 VDD AN4/C1IN-/CN6/RB4 12 37 D+/RG2 AN3/C2IN+/CN5/RB3 13 36 D-/RG3 AN2/C2IN-/CN4/RB2 14 35 VUSB PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15 34 VBUS PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 16 33 USBID/RF3 7890123456789012 1112222222222333 B6B7 DD SSB8B91011 SS DD12131415F4 F5 RRVVRRBBVVBBBBR R PGEC2/AN6/OCFA/PGED2/AN7/AAAN8/U2CTS/C1OUT/AN9/C2OUT/PMA7/S/AN10/CV/PMA13/RREFOUT TDO/AN11/PMA12//R TCK/AN12/PMA11/RTDI/AN13/PMA10/RN14/U2RTS/PMALH/PMA1/ROCFB/PMALL/PMA0/CN12/RSDA2/U2RX/PMA9/CN17/ SCL2/U2TX/PMA8/CN18/ TM A15/ N A © 2011 Microchip Technology Inc. DS61143H-page 13

PIC32MX3XX/4XX Pin Diagrams (Continued) 100-Pin TQFP (USB) = Pins are up to 5V tolerant 4 D PMD4/RE4PMD3/RE3PMD2/RE2TRD0/RG13TRD1/RG12TRD2/RG14PMD1/RE1PMD0/RE0TRD3/RA7TRCLK/RA6PMD8/RG0PMD9/RG1PMD10/RF1PMD11/RF0ENVREGV/VCAPCOREPMD15/CN16/RD7PMD14/CN15/RD6PMRD/CN14/RD5OC5/PMWR/CN13/RPMD13/CN19/RD13IC5/PMD12/RD12OC4/RD3OC3/RD2OC2/RD1 0987654321098765432109876 0999999999988888888887777 RG15 1 1 75 VSS VDD 2 74 SOSCO/T1CK/CN0/RC14 PMD5/RE5 3 73 SOSCI/CN1/RC13 PMD6/RE6 4 72 SDO1/OC1/INT0/RD0 PMD7/RE7 5 71 IC4/PMCS1/PMA14/RD11 T2CK/RC1 6 70 SCK1/IC3/PMCS2/PMA15/RD10 T3CK/RC2 7 69 SS1/IC2/RD9 T4CK/RC3 8 68 RTCC/IC1/RD8 T5CK/SDI1/RC4 9 67 SDA1/INT4/RA15 SCK2/PMA5/CN8/RG6 10 66 SCL1/INT3/RA14 SDI2/PMA4/CN9/RG7 11 PIC32MX440F128L 65 VSS SDO2/PMA3/CN10/RG8 12 64 OSC2/CLKO/RC15 PIC32MX460F256L MCLR 13 63 OSC1/CLKI/RC12 SS2/PMA2/CN11/RG9 14 PIC32MX460F512L 62 VDD VSS 15 61 TDO/RA5 VDD 16 60 TDI/RA4 TMS/RA0 17 59 SDA2/RA3 INT1/RE8 18 58 SCL2/RA2 INT2/RE9 19 57 D+/RG2 AN5/C1IN+/VBUSON/CN7/RB5 20 56 D-/RG3 AN4/C1IN-/CN6/RB4 21 55 VUSB AN3/C2IN+/CN5/RB3 22 54 VBUS AN2/C2IN-/CN4/RB2 23 53 U1TX/RF8 PGEC1/AN1/CN3/RB1 24 52 U1RX/RF2 PGED1/AN0/CN2/RB0 25 51 USBID/RF3 6789012345678901234567890 2222333333333344444444445 PGEC2/AN6/OCFA/RB6PGED2/AN7/RB7V-/CV-/PMA7/RA9REFREF+/CV+/PMA6/RA10REFREFAVDDAVSSAN8/C1OUT/RB8AN9/C2OUT/RB90/CV/PMA13/RB10REFOUTAN11/PMA12/RB11VSSVDDTCK/RA1U2RTS/RF13U2CTS/RF12AN12/PMA11/RB12AN13/PMA10/RB13AN14/PMALH/PMA1/RB14PMALL/PMA0/CN12/RB15VSSVDDU1CTS/CN20/RD14U1RTS/CN21/RD15U2RX/PMA9/CN17/RF4U2TX/PMA8/CN18/RF5 V N1 B/ A CF O 5/ 1 N A DS61143H-page 14 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Pin Diagrams (Continued) 121-Pin XBGA(1) = Pins are up to 5V tolerant PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L 1 2 3 4 5 6 7 8 9 10 11 A RE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1 B NC RG15 RE2 RE1 RA7 RF0 VCORE/ RD5 RD3 VSS RC14 VCAP C RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 D RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 E RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 F MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 G RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 H RB5 RB4 VSS VDD NC VDD NC VBUS VUSB RG2 RA2 J RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 K RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 L RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Note1: Refer to Table4 for full pin names. © 2011 Microchip Technology Inc. DS61143H-page 15

PIC32MX3XX/4XX TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES Pin Pin Full Pin Name Full Pin Name Number Number A1 PMD4/RE4 E8 SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 PMD10/RF1 F2 SDO2/PMA3/CN10/RG8 A7 ENVREG F3 SS2/PMA2/CN11/RG9 A8 VSS F4 SDI2/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 VSS A10 OC3/RD2 F6 No Connect (NC) A11 OC2/RD1 F7 No Connect (NC) B1 No Connect (NC) F8 Vdd B2 RG15 F9 OSC1/CLKI/RC12 B3 PMD2/RE2 F10 VSS B4 PMD1/RE1 F11 OSC2/CLKO/RC15 B5 TRD3/RA7 G1 INT1/RE8 B6 PMD11/RF0 G2 INT2/RE9 B7 VCAP/VCORE G3 TMS/RA0 B8 PMRD/CN14/RD5 G4 No Connect (NC) B9 OC4/RD3 G5 VDD B10 VSS G6 VSS B11 SOSCO/T1CK/CN0/RC14 G7 VSS C1 PMD6/RE6 G8 No Connect (NC) C2 VDD G9 TDO/RA5 C3 TRD1/RG12 G10 SDA2/RA3 C4 TRD2/RG14 G11 TDI/RA4 C5 TRCLK/RA6 H1 AN5/C1IN+/VBUSON/CN7/RB5 C6 No Connect (NC) H2 AN4/C1IN-/CN6/RB4 C7 PMD15/CN16/RD7 H3 VSS C8 OC5/PMWR/CN13/RD4 H4 VDD C9 VDD H5 No Connect (NC) C10 SOSCI/CN1/RC13 H6 VDD C11 IC4/PMCS1/PMA14/RD11 H7 No Connect (NC) D1 T2CK/RC1 H8 VBUS D2 PMD7/RE7 H9 VUSB D3 PMD5/RE5 H10 D+/RG2 D4 VSS H11 SCL2/RA2 D5 VSS J1 AN3/C2IN+/CN5/RB3 D6 No Connect (NC) J2 AN2/C2IN-/CN4/RB2 D7 PMD14/CN15/RD6 J3 PGED2/AN7/RB7 D8 CN19/PMD13/RD13 J4 AVDD D9 SDO1/OC1/INT0/RD0 J5 AN11/PMA12/RB11 D10 No Connect (NC) J6 TCK/RA1 D11 SCK1/IC3/PMCS2/PMA15/RD10 J7 AN12/PMA11/RB12 E1 T5CK/SDI1/RC4 J8 No Connect (NC) E2 T4CK/RC3 J9 No Connect (NC) E3 SCK2/PMA5/CN8/RG6 J10 U1TX/RF8 E4 T3CK/RC2 J11 D-/RG3 E5 VDD K1 PGEC1/AN1/CN3/RB1 E6 PMD9/RG1 K2 PGED1/AN0/CN2/RB0 E7 VSS K3 VREF+/CVREF+/PMA6/RA10 DS61143H-page 16 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES (CONTINUED) Pin Pin Full Pin Name Full Pin Name Number Number K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 U1CTS/CN20/RD14 K11 U1RX/RF2 L10 U2RX/PMA9/CN17/RF4 L1 PGEC2/AN6/OCFA/RB6 L11 U2TX/PMA8/CN18/RF5 L2 VREF-/CVREF-/PMA7/RA9 © 2011 Microchip Technology Inc. DS61143H-page 17

PIC32MX3XX/4XX Table of Contents 1.0 Device Overview........................................................................................................................................................................21 2.0 Guidelines for Getting Started with 32-bit Microcontrollers........................................................................................................31 3.0 CPU............................................................................................................................................................................................37 4.0 Memory Organization.................................................................................................................................................................43 5.0 Flash Program Memory..............................................................................................................................................................85 6.0 Resets........................................................................................................................................................................................87 7.0 Interrupt Controller.....................................................................................................................................................................89 8.0 Oscillator Configuration..............................................................................................................................................................93 9.0 Prefetch Cache...........................................................................................................................................................................95 10.0 Direct Memory Access (DMA) Controller ..................................................................................................................................97 11.0 USB On-The-Go (OTG)..............................................................................................................................................................99 12.0 I/O Ports...................................................................................................................................................................................101 13.0 Timer1......................................................................................................................................................................................103 14.0 Timer2/3 and Timer4/5............................................................................................................................................................105 15.0 Input Capture............................................................................................................................................................................107 16.0 Output Compare.......................................................................................................................................................................109 17.0 Serial Peripheral Interface (SPI)...............................................................................................................................................111 18.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................113 19.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................115 20.0 Parallel Master Port (PMP) ......................................................................................................................................................119 21.0 Real-Time Clock and Calendar (RTCC)...................................................................................................................................121 22.0 10-bit Analog-to-Digital Converter (ADC).................................................................................................................................123 23.0 Comparator..............................................................................................................................................................................125 24.0 Comparator Voltage Reference (CVREF)..................................................................................................................................127 25.0 Power-Saving Features ...........................................................................................................................................................129 26.0 Special Features......................................................................................................................................................................131 27.0 Instruction Set..........................................................................................................................................................................141 28.0 Development Support...............................................................................................................................................................147 29.0 Electrical Characteristics..........................................................................................................................................................151 30.0 Packaging Information..............................................................................................................................................................191 Index................................................................................................................................................................................................. 209 DS61143H-page 18 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2011 Microchip Technology Inc. DS61143H-page 19

PIC32MX3XX/4XX NOTES: DS61143H-page 20 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 1.0 DEVICE OVERVIEW This document contains device-specific information for the PIC32MX3XX/4XX devices. Note1: This data sheet summarizes the features Figure1-1 illustrates a general block diagram of the core of the PIC32MX3XX/4XX family of and peripheral modules in the PIC32MX3XX/4XX family devices. It is not intended to be a of devices. comprehensive reference source. To complement the information in this data Table1-1 lists the functions of the various pins shown sheet, refer to the “PIC32 Family in the pinout diagrams. Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 1-1: BLOCK DIAGRAM(1,2) VCORE/VCAP OSC2/CLKO OSC/SOSC OSC1/CLKI Oscillators Power-up VDD,VSS Timer FRC/LPRC ENVREG MCLR Oscillators Voltage Oscillator Regulator Start-up Timer PLL Power-on DIVIDERS BParencdi sGioanp Reset Reference PLL-USB Watchdog USBCLK Timer SYSCLK Brown-out Timing Generation PBCLK Reset CN1-22 Peripheral Bus Clocked by SYSCLK Timer1-5 PORTA JTAG Priority PWM PORTB BSCAN CInotnetrrroulpletr OC1-5 USB DMAC ICD K 32 L C PORTC EJTAG INT B IC1-5 P MIPS32® M4K® CPU Core by d PORTD IS DS cke SPI1,2 32 32 32 Clo 32 32 32 us PORTE B I2C1,2 al Bus Matrix her 32 p PORTF eri 32 32 32 P PMP PORTG 10-bit ADC Prefetch Data RAM Peripheral Bridge Module UART1,2 128 RTCC 128-bit wide Flash Program Flash Memory Controller Comparators Note 1: Some features are not available on all device variants. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2011 Microchip Technology Inc. DS61143H-page 21

PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Buffer Pin Name Description 64-pin 100-pin 121-pin Type Type QFN/TQFP TQFP XBGA AN0 16 25 K2 I Analog Analog input channels. AN1 15 24 K1 I Analog AN2 14 23 J2 I Analog AN3 13 22 J1 I Analog AN4 12 21 H2 I Analog AN5 11 20 H1 I Analog AN6 17 26 L1 I Analog AN7 18 27 J3 I Analog AN8 21 32 K4 I Analog AN9 22 33 L4 I Analog AN10 23 34 L5 I Analog AN11 24 35 J5 I Analog AN12 27 41 J7 I Analog AN13 28 42 L7 I Analog AN14 29 43 K7 I Analog AN15 30 44 L8 I Analog CLKI 39 63 F9 I ST/CMOS External clock source input. Always associated with OSC1 pin function. CLKO 40 64 F11 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 39 63 F9 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 40 64 F11 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI 47 73 C10 I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. SOSCO 48 74 B11 O — 32.768 kHz low-power oscillator crystal output. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. DS61143H-page 22 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Buffer Pin Name Description 64-pin 100-pin 121-pin Type Type QFN/TQFP TQFP XBGA CN0 48 74 B11 I ST Change notification inputs. Can be software programmed for internal weak CN1 47 73 C10 I ST pull-ups on all inputs. CN2 16 25 K2 I ST CN3 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST CN9 5 11 F4 I ST CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST CN14 53 82 B8 I ST CN15 54 83 D7 I ST CN16 55 84 C7 I ST CN17 31 49 L10 I ST CN18 32 50 L11 I ST CN19 — 80 D8 I ST CN20 — 47 L9 I ST CN21 — 48 K9 I ST IC1 42 68 E9 I ST Capture inputs 1-5. IC2 43 69 E10 I ST IC3 44 70 D11 I ST IC4 45 71 C11 I ST IC5 52 79 A9 I ST OCFA 17 26 L1 I ST Output Compare Fault A Input. OC1 46 72 D9 O — Output Compare output 1. OC2 49 76 A11 O — Output Compare output 2 OC3 50 77 A10 O — Output Compare output 3. OC4 51 78 B9 O — Output Compare output 4. OC5 52 81 C8 O — Output Compare output 5. OCFB 30 44 L8 I ST Output Compare Fault B Input. INT0 35,46 55,72 H9,D9 I ST External interrupt 0. INT1 42 18 61 I ST External interrupt 1. INT2 43 19 62 I ST External interrupt 2. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. © 2011 Microchip Technology Inc. DS61143H-page 23

PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Buffer Pin Name Description 64-pin 100-pin 121-pin Type Type QFN/TQFP TQFP XBGA INT3 44 66 E11 I ST External interrupt 3. INT4 45 67 E8 I ST External interrupt 4. RA0 — 17 G3 I/O ST PORTA is a bidirectional I/O port. RA1 — 38 J6 I/O ST RA2 — 58 H11 I/O ST RA3 — 59 G10 I/O ST RA4 — 60 G11 I/O ST RA5 — 61 G9 I/O ST RA6 — 91 C5 I/O ST RA7 — 92 B5 I/O ST RA9 — 28 L2 I/O ST RA10 — 29 K3 I/O ST RA14 — 66 E11 I/O ST RA15 — 67 E8 I/O ST RB0 16 25 K2 I/O ST PORTB is a bidirectional I/O port. RB1 15 24 K1 I/O ST RB2 14 23 J2 I/O ST RB3 13 22 J1 I/O ST RB4 12 21 H2 I/O ST RB5 11 20 H1 I/O ST RB6 17 26 L1 I/O ST RB7 18 27 J3 I/O ST RB8 21 32 K4 I/O ST RB9 22 33 L4 I/O ST RB10 23 34 L5 I/O ST RB11 24 35 J5 I/O ST RB12 27 41 J7 I/O ST RB13 28 42 L7 I/O ST RB14 29 43 K7 I/O ST RB15 30 44 L8 I/O ST RC1 — 6 D1 I/O ST PORTC is a bidirectional I/O port. RC2 — 7 E4 I/O ST RC3 — 8 E2 I/O ST RC4 — 9 E1 I/O ST RC12 39 63 F9 I/O ST RC13 47 73 C10 I/O ST RC14 48 74 B11 I/O ST RC15 40 64 F11 I/O ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. DS61143H-page 24 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Buffer Pin Name Description 64-pin 100-pin 121-pin Type Type QFN/TQFP TQFP XBGA RD0 46 72 D9 I/O ST PORTD is a bidirectional I/O port. RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 — 80 D8 I/O ST RD14 — 47 L9 I/O ST RD15 — 48 K9 I/O ST RE0 60 93 A4 I/O ST PORTE is a bidirectional I/O port. RE1 61 94 B4 I/O ST RE2 62 98 B3 I/O ST RE3 63 99 A2 I/O ST RE4 64 100 A1 I/O ST RE5 1 3 D3 I/O ST RE6 2 4 C1 I/O ST RE7 3 5 D2 I/O ST RE8 — 18 G1 I/O ST RE9 — 19 G2 I/O ST RF0 58 87 B6 I/O ST PORTF is a bidirectional I/O port. RF1 59 88 A6 I/O ST RF2 34 52 K11 I/O ST RF3 33 51 K10 I/O ST RF4 31 49 L10 I/O ST RF5 32 50 L11 I/O ST RF6 35 55 H9 I/O ST RF7 — 54 H8 I/O ST RF8 — 53 J10 I/O ST RF12 — 40 K6 I/O ST RF13 — 39 L6 I/O ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. © 2011 Microchip Technology Inc. DS61143H-page 25

PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Buffer Pin Name Description 64-pin 100-pin 121-pin Type Type QFN/TQFP TQFP XBGA RG0 — 90 A5 I/O ST PORTG is a bidirectional I/O port. RG1 — 89 E6 I/O ST RG6 4 10 E3 I/O ST RG7 5 11 F4 I/O ST RG8 6 12 F2 I/O ST RG9 8 14 F3 I/O ST RG12 — 96 C3 I/O ST RG13 — 97 A3 I/O ST RG14 — 95 C4 I/O ST RG15 — 1 B2 I/O ST RG2 37 57 H10 I ST PORTG input pins. RG3 36 56 J11 I ST T1CK 48 74 B11 I ST Timer1 external clock input. T2CK — 6 D1 I ST Timer2 external clock input. T3CK — 7 E4 I ST Timer3 external clock input. T4CK — 8 E2 I ST Timer4 external clock input. T5CK — 9 E1 I ST Timer5 external clock input. U1CTS 43 47 L9 I ST UART1 clear to send. U1RTS 35, 49 48 K9 O — UART1 ready to send. U1RX 34, 50 52 K11 I ST UART1 receive. U1TX 33, 51 51, 53 J10, K10 O — UART1 transmit. U2CTS 21 40 K6 I ST UART2 clear to send. U2RTS 29 39 L6 O — UART2 ready to send. U2RX 31 49 L10 I ST UART2 receive. U2TX 32 50 L11 O — UART2 transmit. SCK1 35 55, 70 D11, H9 I/O ST Synchronous serial clock input/output for SPI1. SDI1 34 9, 54 E1, H8 I ST SPI1 data in. SDO1 33 53, 72 D9, J10 O — SPI1 data out. SS1 14 23, 69 E10, J2 I/O ST SPI1 slave synchronization or frame pulse I/O. SCK2 4 10 E3 I/O ST Synchronous serial clock input/output for SPI2. SDI2 5 11 F4 I ST SPI2 data in. SDO2 6 12 F2 O — SPI2 data out. SS2 8 14 F3 I/O ST SPI2 slave synchronization or frame pulse I/O. SCL1 37, 44 57, 66 E11, H10 I/O ST Synchronous serial clock input/output for I2C1. SDA1 36, 43 56, 67 E8, J11 I/O ST Synchronous serial data input/output for I2C1. SCL2 32 58 H11 I/O ST Synchronous serial clock input/output for I2C2. SDA2 31 59 G10 I/O ST Synchronous serial data input/output for I2C2. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. DS61143H-page 26 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Buffer Pin Name Description 64-pin 100-pin 121-pin Type Type QFN/TQFP TQFP XBGA TMS 23 17 G3 I ST JTAG Test mode select pin. TCK 27 38 J6 I ST JTAG test clock input pin. TDI 28 60 G11 I ST JTAG test data input pin. TDO 24 61 G9 O — JTAG test data output pin. RTCC 42 68 E9 O — Real-Time Clock Alarm Output. CVREF- 15 28 L2 I Analog Comparator Voltage Reference (low). CVREF+ 16 29 K3 I Analog Comparator Voltage Reference (high). CVREFOUT 23 34 L5 O Analog Comparator Voltage Reference Output. C1IN- 12 21 H2 I Analog Comparator 1 Negative Input. C1IN+ 11 20 H1 I Analog Comparator 1 Positive Input. C1OUT 21 32 K4 O — Comparator 1 Output. C2IN- 14 23 J2 I Analog Comparator 2 Negative Input. C2IN+ 13 22 J1 I Analog Comparator 2 Positive Input. C2OUT 22 33 L4 O — Comparator 2 Output. PMA0 30 44 L8 I/O TTL/ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 29 43 K7 I/O TTL/ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 8 14 F3 O — Parallel Master Port Address (De-multiplexed Master Modes). PMA3 6 12 F2 O — PMA4 5 11 F4 O — PMA5 4 10 E3 O — PMA6 16 29 K3 O — PMA7 22 28 L2 O — PMA8 32 50 L11 O — PMA9 31 49 L10 O — PMA10 28 42 L7 O — PMA11 27 41 J7 O — PMA12 24 35 J5 O — PMA13 23 34 L5 O — PMA14 45 71 C11 O — PMA15 44 70 D11 O — PMCS1 45 71 C11 O — Parallel Master Port Chip Select 1 Strobe. PMCS2 44 70 D11 O — Parallel Master Port Chip Select 2 Strobe. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. © 2011 Microchip Technology Inc. DS61143H-page 27

PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Buffer Pin Name Description 64-pin 100-pin 121-pin Type Type QFN/TQFP TQFP XBGA PMD0 60 93 A4 I/O TTL/ST Parallel Master Port Data (De-multiplexed Master mode) or Address/Data (Multiplexed Master modes). PMD1 61 94 B4 I/O TTL/ST PMD2 62 98 B3 I/O TTL/ST PMD3 63 99 A2 I/O TTL/ST PMD4 64 100 A1 I/O TTL/ST PMD5 1 3 D3 I/O TTL/ST PMD6 2 4 C1 I/O TTL/ST PMD7 3 5 D2 I/O TTL/ST PMD8 — 90 A5 I/O TTL/ST PMD9 — 89 E6 I/O TTL/ST PMD10 — 88 A6 I/O TTL/ST PMD11 — 87 B6 I/O TTL/ST PMD12 — 79 A9 I/O TTL/ST PMD13 — 80 D8 I/O TTL/ST PMD14 — 83 D7 I/O TTL/ST PMD15 — 84 C7 I/O TTL/ST PMRD 53 82 B8 O — Parallel Master Port Read Strobe. PMWR 52 81 C8 O — Parallel Master Port Write Strobe. PMALL 30 44 L8 O — Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). PMALH 29 43 K7 O — Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). VBUS 34 54 H8 I Analog USB Bus Power Monitor. VUSB 35 55 H9 P — USB Internal Transceiver Supply. If the USB module is not used, this pin must be connected to VDD. VBUSON 11 20 H1 O — USB Host and OTG Bus Power Control Output. D+ 37 57 H10 I/O Analog USB D+. D- 36 56 J11 I/O Analog USB D-. USBID 33 51 K10 I ST USB OTG ID Detect. ENVREG 57 86 A7 I ST Enable for On-Chip Voltage Regulator. TRCLK — 91 C5 O — Trace Clock. TRD0 — 97 A3 O — Trace Data Bits 0-3. TRD1 — 96 C3 O — TRD2 — 95 C4 O — TRD3 — 92 B5 O — PGED1 16 25 K2 I/O ST Data I/O pin for programming/debugging communication channel 1. PGEC1 15 24 K1 I ST Clock input pin for programming/debugging communication channel 1. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. DS61143H-page 28 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Buffer Pin Name Description 64-pin 100-pin 121-pin Type Type QFN/TQFP TQFP XBGA PGED2 18 27 J3 I/O ST Data I/O pin for programming/debugging communication channel 2. PGEC2 17 26 L1 I ST Clock input pin for programming/debugging communication channel 2. MCLR 7 13 F1 I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD 19 30 J4 P P Positive supply for analog modules. This pin must be connected at all times. AVSS 20 31 L3 P P Ground reference for analog modules. VDD 10, 26, 38 2, 16, 37, C2, C9, P — Positive supply for peripheral logic and I/O pins. 46, 62 E5, F8, G5, H4, H6, K8 VCORE/ 56 85 B7 P — Capacitor for Internal Voltage Regulator. VCAP Vss 9, 25, 41 15, 36, A8, B10, P — Ground reference for logic and I/O pins. 45, 65, D4, D5, 75 E7, F10, F5, G6, G7, H3 VREF+ 16 29 K3 I Analog Analog voltage reference (high) input. VREF- 15 28 L2 I Analog Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. © 2011 Microchip Technology Inc. DS61143H-page 29

PIC32MX3XX/4XX NOTES: DS61143H-page 30 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 32-BIT The use of decoupling capacitors on every pair of MICROCONTROLLERS power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure2-1. Note1: This data sheet summarizes the features Consider the following criteria when using decoupling of the PIC32MX3XX/4XX family of capacitors: devices. It is not intended to be a comprehensive reference source. To • Value and type of capacitor: Recommendation complement the information in this data of 0.1 µF (100 nF), 10-20V. This capacitor should sheet, refer to the “PIC32 Family be a low-ESR and have resonance frequency in Reference Manual”, which is available the range of 20MHz and higher. It is from the Microchip web site recommended that ceramic capacitors be used. (www.microchip.com/PIC32). • Placement on the printed circuit board: The decoupling capacitors should be placed as close 2: Some registers and associated bits to the pins as possible. It is recommended to described in this section may not be avail- place the capacitors on the same side of the able on all devices. Refer to Section4.0 board as the device. If space is constricted, the “Memory Organization” in this data capacitor can be placed on another layer on the sheet for device-specific register and bit PCB using a via; however, ensure that the trace information. length from the pin to the capacitor is within one-quarter inch (6mm) in length. 2.1 Basic Connection Requirements • Handling high frequency noise: If the board is Getting started with the PIC32MX3XX/4XX family of experiencing high frequency noise, upward of 32-bit Microcontrollers (MCUs) requires attention to a tens of MHz, add a second ceramic-type capacitor minimal set of device pin connections before in parallel to the above described decoupling proceeding with development. The following is a list of capacitor. The value of the second capacitor can pin names, which must always be connected: be in the range of 0.01µF to 0.001µF. Place this • All VDD and VSS pins second capacitor next to the primary decoupling (see Section2.2 “Decoupling Capacitors”) capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as • All AVDD and AVSS pins (regardless if ADC module close to the power and ground pins as possible. is not used) For example, 0.1 µF in parallel with 0.001 µF. (see Section2.2 “Decoupling Capacitors”) • Maximizing performance: On the board layout • VCAP/VCORE from the power supply circuit, run the power and (see Section2.3 “Capacitor on Internal Voltage return traces to the decoupling capacitors first, Regulator (VCAP/VCORE)”) and then to the device pins. This ensures that the • MCLR pin decoupling capacitors are first in the power chain. (see Section2.4 “Master Clear (MCLR) Pin”) Equally important is to keep the trace length • PGECx/PGEDx pins used for In-Circuit Serial between the capacitor and the power pins to a Programming™ (ICSP™) and debugging purposes minimum thereby reducing PCB track inductance. (see Section2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section2.8 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of ADC use and ADC voltage reference source. © 2011 Microchip Technology Inc. DS61143H-page 31

PIC32MX3XX/4XX FIGURE 2-1: RECOMMENDED 2.4 Master Clear (MCLR) Pin MINIMUM CONNECTION The MCLR pin provides for two specific device functions: 0.1 µF • Device Reset Ceramic VDD CEFC CBP • Device Programming and Debugging Pulling The MCLR pin low generates a device reset. R R1 CORE VDD VSS Figure2-2 illustrates a typical MCLR circuit. During V device programming and debugging, the resistance MCLR /P CA and capacitance that can be added to the pin must V C be considered. Device programmers and debuggers PIC32MX drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must VSS VDD not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the VDD VSS application and PCB requirements. 0.1 µF D S 0.1 µF D S D S Ceramic AV AV VD VS Ceramic For example, as illustrated in Figure2-2, it is CBP CBP recommended that the capacitor C, be isolated from 0.1 µF 0.1 µF the MCLR pin during programming and debugging 10Ω Ceramic Ceramic CBP CBP operations. Place the components shown in Figure2-2 within one-quarter inch (6mm) from the MCLR pin. 2.2.1 BULK CAPACITORS The use of a bulk capacitor is recommended to improve FIGURE 2-2: EXAMPLE OF MCLR PIN power supply stability. Typical values range from 4.7 µF CONNECTIONS to 47 µF. This capacitor should be located as close to the device as possible. VDD 2.3 Capacitor on Internal Voltage R Regulator (VCAP/VCORE) R1 MCLR 2.3.1 INTERNAL REGULATOR MODE JP PIC32MX A low-ESR (< 1 Ohm) capacitor is required on the VCAP/VCORE pin, which is used to stabilize the internal C voltage regulator output. The VCAP/VCORE pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type Note 1: R≤ 10kΩ is recommended. A suggested start- can be ceramic or tantalum. Refer to Section29.0 ing value is 10kΩ. Ensure that the MCLR pin “Electrical Characteristics” for additional information VIH and VIL specifications are met. on CEFC specifications. This mode is enabled by 2: R1≤ 470Ω will limit any current flowing into connecting the ENVREG pin to VDD. MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to 2.3.2 EXTERNAL REGULATOR MODE Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin In this mode the core voltage is supplied externally VIH and VIL specifications are met. through the VCORE/VCAP pin. A low-ESR capacitor of 3: The capacitor can be sized to prevent uninten- 10µF is recommended on the VCAP/VCORE pin. This tional resets from brief glitches or to extend the mode is enabled by grounding the ENVREG pin. device reset period during POR. The placement of this capacitor should be close to the VCAP/VCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section26.3 “On-Chip Voltage Regulator” for details. DS61143H-page 32 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 2.5 ICSP Pins Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended The PGECx and PGEDx pins are used for In-Circuit as they will interfere with the programmer/debugger Serial Programming™ (ICSP™) and debugging pur- communications to the device. If such discrete compo- poses. It is recommended to keep the trace length nents are an application requirement, they should be between the ICSP connector and the ICSP pins on the removed from the circuit during programming and device as short as possible. If the ICSP connector is debugging. Alternately, refer to the AC/DC characteris- expected to experience an ESD event, a series resistor tics and timing requirements information in the respec- is recommended, with the value in the range of a few tive device Flash programming specification for tens of Ohms, not to exceed 100 Ohms. information on capacitive loading limits and pin input Pull-up resistors, series diodes and capacitors on the voltage high (VIH) and input low (VIL) requirements. PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communi- 2.7 Trace cations to the device. If such discrete components are The trace pins can be connected to a hardware-trace- an application requirement, they should be removed enabled programmer to provide a compress real time from the circuit during programming and debugging. instruction trace. When used for trace the TRD3, Alternately, refer to the AC/DC characteristics and tim- TRD2, TRD1, TRD0 and TRCLK pins should be dedi- ing requirements information in the respective device cated for this use. The trace hardware requires a 22 Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) Ohm series resistor between the trace pins and the and input low (VIL) requirements. trace connector. Ensure that the “Communication Channel Select” (i.e., 2.8 External Oscillator Pins PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to Many MCUs have options for at least two oscillators: a MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™. high-frequency primary oscillator and a low-frequency For more information on ICD 2, ICD 3 and REAL ICE secondary oscillator (refer to Section8.0 “Oscillator connection requirements, refer to the following Configuration” for details). documents that are available on the Microchip web The oscillator circuit should be placed on the same site. side of the board as the device. Also, place the • “MPLAB® ICD 2 In-Circuit Debugger User’s oscillator circuit close to the respective oscillator pins, Guide” DS51331 not exceeding one-half inch (12mm) distance • “Using MPLAB® ICD 2” (poster) DS51265 between them. The load capacitors should be placed next to the oscillator itself, on the same side of the • “MPLAB® ICD 2 Design Advisory” DS51566 board. Use a grounded copper pour around the • “Using MPLAB® ICD 3” (poster) DS51765 oscillator circuit to isolate them from surrounding • “MPLAB® ICD 3 Design Advisory” DS51764 circuits. The grounded copper pour should be routed • “MPLAB® REAL ICE™ In-Circuit Debugger directly to the MCU ground. Do not run any signal User’s Guide” DS51616 traces or power traces inside the ground pour. Also, if • “Using MPLAB® REAL ICE™” (poster) DS51749 using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure2-3. 2.6 JTAG The TMS, TDO, TDI and TCK pins are used for testing FIGURE 2-3: SUGGESTED PLACEMENT and debugging according to the Joint Test Action OF THE OSCILLATOR Group (JTAG) standard. It is recommended to keep the CIRCUIT trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Oscillator Ohms. Secondary Guard Trace Guard Ring Main Oscillator © 2011 Microchip Technology Inc. DS61143H-page 33

PIC32MX3XX/4XX 2.9 Configuration of Analog and 2.10 Unused I/Os Digital Pins During ICSP Unused I/O pins should not be allowed to float as Operations inputs. They can be configured as outputs and driven to a logic-low state. If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the Analog- Alternately, inputs can be reserved by connecting the to-Digital input pins (ANx) as “digital” pins by setting all pin to VSS through a 1k to 10k resistor and configuring bits in the ADPCFG register. the pin as an input. The bits in this register that correspond to the Analog- to-Digital pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain Analog-to- Digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all Analog-to-Digital pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. DS61143H-page 34 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 2.11 Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note1: To access the documents listed below, browse to the documentation section of the PIC32MX460F512L product page on the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. • Section 1. “Introduction” (DS61127) • Section 2. “CPU” (DS61113) • Section 3. “Memory Organization” (DS61115) • Section 4. “Prefetch Cache” (DS61119) • Section 5. “Flash Program Memory” (DS61121) • Section 6. “Oscillator Configuration” (DS61112) • Section 7. “Resets” (DS61118) • Section 8. “Interrupt Controller” (DS61108) • Section 9. “Watchdog Timer and Power-up Timer” (DS61114) • Section 10. “Power-Saving Features” (DS61130) • Section 12. “I/O Ports” (DS61120) • Section 13. “Parallel Master Port (PMP)” (DS61128) • Section 14. “Timers” (DS61105) • Section 15. “Input Capture” (DS61122) • Section 16. “Output Compare” (DS61111) • Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) • Section 19. “Comparator” (DS61110) • Section 20. “Comparator Voltage Reference (CVREF)” (DS61109) • Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107) • Section 23. “Serial Peripheral Interface (SPI)” (DS61106) • Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS61116) • Section 27. “USB On-The-Go (OTG)” (DS61126) • Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) • Section 31. “Direct Memory Access (DMA) Controller” (DS61117) • Section 32. “Configuration” (DS61124) • Section 33. “Programming and Diagnostics” (DS61129) © 2011 Microchip Technology Inc. DS61143H-page 35

PIC32MX3XX/4XX NOTES: DS61143H-page 36 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 3.0 CPU - Atomic interrupt enable/disable - GPR shadow registers to minimize latency Note1: This data sheet summarizes the features for interrupt handlers of the PIC32MX3XX/4XX family of - Bit field manipulation instructions devices. It is not intended to be a compre- • MIPS16e® Code Compression hensive reference source. To comple- - 16-bit encoding of 32-bit instructions to ment the information in this data sheet, improve code density refer to Section 2. “CPU” (DS61113) of the “PIC32 Family Reference Manual”, - Special PC-relative instructions for efficient which is available from the Microchip web loading of addresses and constants site (www.microchip.com/PIC32). - SAVE & RESTORE macro instructions for Resources for the MIPS32® M4K® setting up and tearing down stack frames Processor Core are available at: within subroutines www.mips.com/products/cores/ - Improved support for handling 8 and 16-bit 32-64-bit-cores/mips32-m4k/. data types 2: Some registers and associated bits • Simple Fixed Mapping Translation (FMT) described in this section may not be avail- mechanism able on all devices. Refer to Section4.0 • Simple Dual Bus Interface “Memory Organization” in this data - Independent 32-bit address and data busses sheet for device-specific register and bit - Transactions can be aborted to improve information. interrupt latency The MIPS32® M4K® Processor Core is the heart of the • Autonomous Multiply/Divide Unit PIC32MX3XX/4XX family processor. The CPU fetches - Maximum issue rate of one 32x16 multiply instructions, decodes each instruction, fetches source per clock operands, executes each instruction and writes the - Maximum issue rate of one 32x32 multiply results of instruction execution to the proper destina- every other clock tions. - Early-in iterative divide. Minimum 11 and maximum 34 clock latency (dividend (rs) sign 3.1 Features extension-dependent) • 5-stage pipeline • Power Control • 32-bit Address and Data Paths - Minimum frequency: 0 MHz • MIPS32 Enhanced Architecture (Release 2) - Low-Power mode (triggered by WAIT instruction) - Multiply-Accumulate and Multiply-Subtract Instructions - Extensive use of local gated clocks - Targeted Multiply Instruction • EJTAG Debug and Instruction Trace - Zero/One Detect Instructions - Support for single stepping - WAIT Instruction - Virtual instruction and data address/value - Conditional Move Instructions (MOVN, MOVZ) - breakpoints - Vectored interrupts - PC tracing with trace compression - Programmable exception vector base FIGURE 3-1: MIPS® M4K® BLOCK DIAGRAM CPU EJTAG Trace I/F MDU Trace Off-Chip TAP Debug I/F Execution x Core FMT Bus Interface Dual Bus I/F atri (RF/ALU/Shift) M s u B System Power Coprocessor Mgmt. © 2011 Microchip Technology Inc. DS61143H-page 37

PIC32MX3XX/4XX 3.2 Architecture Overview 3.2.2 MULTIPLY/DIVIDE UNIT (MDU) The MIPS32® M4K® Processor Core contains several The MIPS32® M4K® Processor Core includes a multi- logic blocks working together in parallel, providing an ply/divide unit (MDU) that contains a separate pipeline efficient high performance computing engine. The for multiply and divide operations. This pipeline oper- following blocks are included with the core: ates in parallel with the integer unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows • Execution Unit MDU operations to be partially masked by system stalls • Multiply/Divide Unit (MDU) and/or other integer unit instructions. • System Control Coprocessor (CP0) The high-performance MDU consists of a 32x16 booth • Fixed Mapping Translation (FMT) recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary • Dual Internal Bus interfaces multiplexers and control logic. The first number shown • Power Management (‘32’ of 32x16) represents the rs operand. The second • MIPS16e Support number (‘16’ of 32x16) represents the rt operand. The • Enhanced JTAG (EJTAG) Controller PIC32MX core only checks the value of the latter (rt) operand to determine how many times the operation 3.2.1 EXECUTION UNIT must pass through the multiplier. The 16x16 and 32x16 The MIPS32® M4K® Processor Core execution unit operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an The MDU supports execution of one 16x16 or 32x16 autonomous multiply/divide unit. The core contains multiply operation every clock cycle; 32x32 multiply thirty-two 32-bit general purpose registers used for operations can be issued every other clock cycle. integer operations and address calculation. One addi- Appropriate interlocks are implemented to stall the tional register file shadow set (containing thirty-two reg- issuance of back-to-back 32x32 multiply operations. isters) is added to minimize context switching overhead The multiply operand size is automatically determined during interrupt/exception processing. The register file by logic built into the MDU. consists of two read ports and one write port and is fully Divide operations are implemented with a simple 1 bit bypassed to minimize operation latency in the pipeline. per clock iterative algorithm. An early-in detection The execution unit includes: checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16- • 32-bit adder used for calculating the data address bit-wide rs, 15 iterations are skipped, and for a 24-bit- • Address unit for calculating the next instruction wide rs, 7 iterations are skipped. Any attempt to issue address a subsequent MDU instruction while a divide is still • Logic for branch determination and branch target active causes an IU pipeline stall until the divide address calculation operation is completed. • Load aligner Table3-1 lists the repeat rate (peak issue rate of cycles • Bypass multiplexers used to avoid stalls when until the operation can be reissued) and latency (num- executing instructions streams where data ber of cycles until a result is available) for the PIC32MX producing instructions are followed closely by core multiply and divide instructions. The approximate consumers of their results latency and repeat rates are listed in terms of pipeline clocks. • Leading Zero/One detect unit for implementing the CLZ and CLO instructions • Arithmetic Logic Unit (ALU) for performing bitwise logical operations • Shifter and Store Aligner DS61143H-page 38 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 3-1: MIPS® M4K® PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate MULT/MULTU, MADD/MADDU, 16 bits 1 1 MSUB/MSUBU 32 bits 2 2 MUL 16 bits 2 1 32 bits 3 2 DIV/DIVU 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32 The MIPS architecture defines that the result of a mul- the product to the current contents of the HI and LO tiply or divide operation be placed in the HI and LO reg- registers. Similarly, the MSUB instruction multiplies two isters. Using the Move-From-HI (MFHI) and Move- operands and then subtracts the product from the HI From-LO (MFLO) instructions, these values can be and LO registers. The MADD and MSUB operations transferred to the general purpose register file. are commonly used in DSP algorithms. In addition to the HI/LO targeted operations, the 3.2.3 SYSTEM CONTROL MIPS32 architecture also defines a multiply instruction, COPROCESSOR (CP0) MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. In the MIPS architecture, CP0 is responsible for the vir- By avoiding the explicit MFLO instruction, required tual-to-physical address translation, the exception con- when using the LO register, and by supporting multiple trol system, the processor’s diagnostics capability, the destination registers, the throughput of operating modes (kernel, user and debug), and multiply-intensive operations is increased. whether interrupts are enabled or disabled. Configura- tion information, such as presence of options like Two other instructions, multiply-add (MADD) and multi- MIPS16e, is also available by accessing the CP0 ply-subtract (MSUB), are used to perform the multiply- registers, listed in Table3-2. accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds TABLE 3-2: COPROCESSOR 0 REGISTERS Register Register Function Number Name 0-6 Reserved Reserved 7 HWREna Enables access via the RDHWR instruction to selected hardware registers 8 BadVAddr(1) Reports the address for the most recent address-related exception 9 Count(1) Processor cycle count 10 Reserved Reserved 11 Compare(1) Timer interrupt control 12 Status(1) Processor status and control 12 IntCtl(1) Interrupt system status and control 12 SRSCtl(1) Shadow register set status and control 12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set 13 Cause(1) Cause of last general exception 14 EPC(1) Program counter at last exception 15 PRId Processor identification and revision 15 EBASE Exception vector base register 16 Config Configuration register 16 Config1 Configuration register 1 16 Config2 Configuration register 2 16 Config3 Configuration register 3 © 2011 Microchip Technology Inc. DS61143H-page 39

PIC32MX3XX/4XX TABLE 3-2: COPROCESSOR 0 REGISTERS (CONTINUED) Register Register Function Number Name 17-22 Reserved Reserved 23 Debug(2) Debug control and exception status 24 DEPC(2) Program counter at last debug exception 25-29 Reserved Reserved 30 ErrorEPC(1) Program counter at last error 31 DESAVE(2) Debug handler scratchpad register Note 1: Registers used in exception processing. 2: Registers used during debug. Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table3-3 shows the exception types in order of priority. TABLE 3-3: PIC32MX3XX/4XX FAMILY CORE EXCE PTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR) DSS EJTAG Debug Single Step DINT EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the EjtagBrk bit in the ECR register NMI Assertion of NMI signal Interrupt Assertion of unmasked hardware or software interrupt signal DIB EJTAG debug hardware instruction break matched AdEL Fetch address alignment error Fetch reference to protected address IBE Instruction fetch bus error DBp EJTAG Breakpoint (execution of SDBBP instruction) Sys Execution of SYSCALL instruction Bp Execution of BREAK instruction RI Execution of a Reserved Instruction CpU Execution of a coprocessor instruction for a coprocessor that is not enabled CEU Execution of a CorExtend instruction when CorExtend is not enabled Ov Execution of an arithmetic instruction that overflowed Tr Execution of a trap (when trap condition is true) DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value) AdEL Load address alignment error Load reference to protected address AdES Store address alignment error Store to protected address DBE Load or store bus error DDBL EJTAG data hardware breakpoint matched in load data compare DS61143H-page 40 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 3.3 Power Management 3.4 EJTAG Debug Support The MIPS32® M4K® Processor Core offers a number The MIPS32® M4K® Processor Core provides for an of power management features, including low-power Enhanced JTAG (EJTAG) interface for use in the design, active power management and power-down software debug of application and kernel code. In modes of operation. The core is a static design that addition to standard user mode and kernel modes of supports slowing or halting the clocks, which reduces operation, the core provides a Debug mode that is system power consumption during idle periods. entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is 3.3.1 INSTRUCTION-CONTROLLED taken and continues until a debug exception return POWER MANAGEMENT (DERET) instruction is executed. During this time, the processor executes the debug exception handler The mechanism for invoking power-down mode is routine. through execution of the WAIT instruction. For more information on power management, see Section25.0 The EJTAG interface operates through the Test Access “Power-Saving Features”. Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition 3.3.2 LOCAL CLOCK GATING to the standard JTAG instructions, special instructions defined in the EJTAG specification define what The majority of the power consumed by the registers are selected and how they are used. PIC32MX3XX/4XX family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated-clocks to reduce this dynamic power consumption. © 2011 Microchip Technology Inc. DS61143H-page 41

PIC32MX3XX/4XX NOTES: DS61143H-page 42 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 4.0 MEMORY ORGANIZATION 4.1 Key Features • 32-bit native data width Note1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of • Separate User and Kernel mode address space devices. It is not intended to be a • Flexible program Flash memory partitioning comprehensive reference source. To • Flexible data RAM partitioning for data and complement the information in this data program space sheet, refer to Section 3. “Memory • Separate boot Flash memory for protected code Organization” (DS61115) of the “PIC32 • Robust bus exception handling to intercept Family Reference Manual”, which is runaway code available from the Microchip web site (www.microchip.com/PIC32). • Simple memory mapping with Fixed Mapping Translation (FMT) unit PIC32MX3XX/4XX microcontrollers provide 4 GB of • Cacheable and non-cacheable address regions unified virtual memory address space. All memory regions including program, data memory, SFRs and 4.2 PIC32MX3XX/4XX Memory Layout Configuration registers reside in this address space at their respective unique addresses. The program and PIC32MX3XX/4XX microcontrollers implement two data memories can be optionally partitioned into user address spaces: Virtual and Physical. All hardware and kernel memories. In addition, the data memory can resources such as program memory, data memory and be made executable, allowing PIC32MX3XX/4XX to peripherals are located at their respective physical execute from data memory. addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by peripherals such as DMA and Flash controller that access memory independently of CPU. © 2011 Microchip Technology Inc. DS61143H-page 43

PIC32MX3XX/4XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX320F032H AND PIC32MX420F032H DEVICES(1) Virtual Physical Memory Map Memory Map 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration 0xBFC02FF0 Registers 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs Reserved 1 G 0xBF800000 E S K Reserved 0xBD008000 0xBD007FFF Program Flash(2) 0xBD000000 Reserved 0xA0002000 0xA0001FFF RAM(2) 0xA0000000 0x1FC03000 Device 0x1FC02FFF Reserved 0x9FC03000 Configuration 0x9FC02FFF Device Registers 0x1FC02FF0 Configuration 0x1FC02FEF Registers 0x9FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 0x9D008000 G 0x1F800000 E 0x9D007FFF S K Program Flash(2) Reserved 0x9D000000 0x1D008000 0x1D007FFF Reserved 0x80002000 Program Flash(2) 0x80001FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00002000 0x00001FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). DS61143H-page 44 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICE(1) Virtual Physical Memory Map Memory Map 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration 0xBFC02FF0 Registers 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs Reserved 1 G 0xBF800000 E S K Reserved 0xBD010000 0xBD00FFFF Program Flash(2) 0xBD000000 Reserved 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x1FC03000 Device 0x1FC02FFF Reserved 0x9FC03000 Configuration 0x9FC02FFF Device Registers 0x1FC02FF0 Configuration 0x1FC02FEF Registers 0x9FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 0x9D010000 G 0x1F800000 E 0x9D00FFFF S K Program Flash(2) Reserved 0x9D000000 0x1D010000 0x1D00FFFF Reserved 0x80004000 Program Flash(2) 0x80003FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00004000 0x00003FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). © 2011 Microchip Technology Inc. DS61143H-page 45

PIC32MX3XX/4XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX320F128H AND PIC32MX320F128L DEVICES(1) Virtual Physical Memory Map Memory Map 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration 0xBFC02FF0 Registers 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs Reserved 1 G 0xBF800000 E S K Reserved 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 Reserved 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x1FC03000 Device 0x1FC02FFF Reserved 0x9FC03000 Configuration 0x9FC02FFF Device Registers 0x1FC02FF0 Configuration 0x1FC02FEF Registers 0x9FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 0x9D020000 G 0x1F800000 E 0x9D01FFFF S K Program Flash(2) Reserved 0x9D000000 0x1D020000 0x1D01FFFF Reserved 0x80004000 Program Flash(2) 0x80003FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00004000 0x00003FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). DS61143H-page 46 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H AND PIC32MX440F128L DEVICES(1) Virtual Physical Memory Map Memory Map 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration 0xBFC02FF0 Registers 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs Reserved 1 G 0xBF800000 E S K Reserved 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x1FC03000 Device 0x1FC02FFF Reserved 0x9FC03000 Configuration 0x9FC02FFF Device Registers 0x1FC02FF0 Configuration 0x1FC02FEF Registers 0x9FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 0x9D020000 G 0x1F800000 E 0x9D01FFFF S K Program Flash(2) Reserved 0x9D000000 0x1D020000 0x1D01FFFF Reserved 0x80008000 Program Flash(2) 0x80007FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00008000 0x00007FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). © 2011 Microchip Technology Inc. DS61143H-page 47

PIC32MX3XX/4XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L, PIC32MX440F256H AND PIC32MX460F256L DEVICES(1) Virtual Physical Memory Map Memory Map 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration 0xBFC02FF0 Registers 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs Reserved 1 G 0xBF800000 E S K Reserved 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x1FC03000 Device 0x1FC02FFF Reserved 0x9FC03000 Configuration 0x9FC02FFF Device Registers 0x1FC02FF0 Configuration 0x1FC02FEF Registers 0x9FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 0x9D040000 G 0x1F800000 E 0x9D03FFFF S K Program Flash(2) Reserved 0x9D000000 0x1D040000 0x1D03FFFF Reserved 0x80008000 Program Flash(2) 0x80007FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00008000 0x00007FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). DS61143H-page 48 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H AND PIC32MX460F512L DEVICES(1) Virtual Physical Memory Map Memory Map 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration 0xBFC02FF0 Registers 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs Reserved 1 G 0xBF800000 E S K Reserved 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x1FC03000 Device 0x1FC02FFF Reserved 0x9FC03000 Configuration 0x9FC02FFF Device Registers 0x1FC02FF0 Configuration 0x1FC02FEF Registers 0x9FC02FEF Boot Flash 0x9FC02FEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 0x9D080000 G 0x1F800000 E 0x9D07FFFF S K Program Flash(2) Reserved 0x9D000000 0x1D080000 0x1D07FFFF Reserved 0x80008000 Program Flash(2) 0x80007FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00008000 0x00007FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). © 2011 Microchip Technology Inc. DS61143H-page 49

D TABLE 4-1: BUS MATRIX REGISTERS MAP P S 6 11 ss Bits IC 43H-page 5 Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 AllResets 32M 0 2000 CBOMNX(1) 3115:1:06 —— —— —— —— —— BMXC—HEDMA —— —— —— BMXW—SDRM —— BMXE—RRIXIBMXE—RRICDBMXERRDMBAMBXMAXREBR<2R:D0>SBMXERRIS 000014F2 X 3 2010 DKBPMBXA(1) 3115:1:06 — — — — — — — — BMXDK—PBA<15:0>— — — — — — — 00000000 X X BMX 31:16 — — — — — — — — — — — — — — — — 0000 2020 DUDBA(1) 15:0 BMXDUDBA<15:0> 0000 /4 BMX 31:16 — — — — — — — — — — — — — — — — 0000 X 2030 DUPBA(1) 15:0 BMXDUPBA<15:0> 0000 X BMX 31:16 xxxx 2040 BMXDRMSZ<31:0> DRMSZ 15:0 xxxx BMX 31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000 2050 PUPBA(1) 15:0 BMXPUPBA<15:0> 0000 BMX 31:16 xxxx 2060 BMXPFMSZ<31:0> PFMSZ 15:0 xxxx BMX 31:16 0000 2070 BMXBOOTSZ<31:0> BOOTSZ 15:0 3000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

© TABLE 4-2: INTERRUPT REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) 2 01 ss Bits 1 Microchip T Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets echn 1000 INTCON 3115:1:06 —— —— —— MV—EC —— — TPC—<2:0> — —— —— —— INT—4EP INT—3EP INT—2EP INT—1EP INSTS00EP 00000000 o logy 1010 INTSTAT(2)3115:1:06 —— —— —— —— —— — SRIP—L<2:0> — —— —— — — —VEC<5:0>— — — 00000000 In 31:16 0000 c 1020 IPTMR IPTMR<31:0> . 15:0 0000 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 1030 IFS0 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000 31:16 — — — — — — USBIF FCEIF — — — — DMA3IF DMA2IF DMA1IF DMA0IF 0000 1040 IFS1 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 1060 IEC0 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 — — — — — — USBIE FCEIE — — — — DMA3IE DMA2IE DMA1IE DMA0IE 0000 1070 IEC1 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000 1090 IPC0 15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000 10A0 IPC1 15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000 10B0 IPC2 15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000 10C0 IPC3 15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000 P 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 10D0 IPC4 15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000 I C 31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000 10E0 IPC5 15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 3 10F0 IPC6 31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 2 15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000 M 31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000 1100 IPC7 15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000 X 31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000 1110 IPC8 15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0> 0000 3 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000 X D 1120 IPC9 S 15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000 61 31:16 — — — — — — — — — — — — — — — — 0000 X 14 1140 IPC11 15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000 / 3H Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 -p Note 1: Except where noted, all registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV X ag Registers” for more information. e 5 2: This register does not have associated CLR, SET, and INV registers. X 1

D TABLE 4-3: INTERRUPT REGISTERS MAP FOR PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L, P S 61 PIC32MX360F256L AND PIC32MX360F512L DEVICES ONLY(1) I 1 C 43H-page 52 Virtual Address(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32M X 31:16 — — — — — — — — — — — — — — — SS0 0000 1000 INTCON 15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 3 1010 INTSTAT(2)31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000 31:16 0000 X 1020 IPTMR IPTMR<31:0> 15:0 0000 / 1030 IFS0 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 4 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000 X 31:16 — — — — — — — FCEIF — — — — DMA3IF DMA2IF DMA1IF DMA0IF 0000 1040 IFS1 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 X 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 1060 IEC0 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 — — — — — — — FCEIE — — — — DMA3IE DMA2IE DMA1IE DMA0IE 0000 1070 IEC1 15:0 RTCCIE FSCMIE I2C2MIE — — — — — SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000 1090 IPC0 15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000 10A0 IPC1 15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000 10B0 IPC2 15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000 10C0 IPC3 15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 10D0 IPC4 15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000 31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000 10E0 IPC5 15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 10F0 IPC6 15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000 © 31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000 2 1100 IPC7 0 15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000 1 1 31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000 M 1110 IPC8 15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0> 0000 ic ro 1120 IPC9 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000 ch 15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000 ip T 1140 IPC11 31:16 — — — — — — — — — — — — — — — — 0000 e 15:0 — — — — — — — — — — — FCEIP<2:0> FCEIS<1:0> 0000 ch Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. no Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV lo Registers” for more information. gy 2: This register does not have associated CLR, SET, and INV registers. In c .

© TABLE 4-4: INTERRUPT REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H AND PIC32MX320F128L 20 DEVICES ONLY(1) 1 1 M ss Bits icrochip Tec Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets h n 31:16 — — — — — — — — — — — — — — — SS0 0000 o 1000 INTCON lo 15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 g y Inc 1010 INTSTAT(2)3115:1:06 —— —— —— —— —— — SRIP—L<2:0> — —— —— — — —VEC<5:0>— — — 00000000 . 31:16 0000 1020 IPTMR IPTMR<31:0> 15:0 0000 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 1030 IFS0 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000 31:16 — — — — — — — FCEIF — — — — — — — — 0000 1040 IFS1 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 1060 IEC0 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 — — — — — — — FCEIE — — — — — — — — 0000 1070 IEC1 15:0 RTCCIE FSCMIE I2C2MIE — — — — — SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000 1090 IPC0 15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000 10A0 IPC1 15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000 10B0 IPC2 15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000 P 10C0 IPC3 15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000 I 10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 C 15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000 31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000 3 10E0 IPC5 15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 2 10F0 IPC6 31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 M 15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000 31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000 X 1100 IPC7 15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000 3 31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000 1110 IPC8 15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0> 0000 X D S6 1140 IPC11 31:16 — — — — — — — — — — — — — — — — 0000 X 1 15:0 — — — — — — — — — — — FCEIP<2:0> FCEIS<1:0> 0000 1 4 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 3 4 H Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV -p Registers” for more information. X ag 2: This register does not have associated CLR, SET, and INV registers. e 5 X 3

D TABLE 4-5: INTERRUPT REGISTERS MAP FOR PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) P S 6 1 s Bits I 143H-page 5 Virtual Addres(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 4 31:16 — — — — — — — — — — — — — — — SS0 0000 1000 INTCON 15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 X 1010 INTSTAT(2)31:16 — — — — — — — — — — — — — — — — 0000 3 15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000 X 31:16 0000 1020 IPTMR IPTMR<31:0> 15:0 0000 X 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF — — — OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 1030 IFS0 / 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000 4 1040 IFS1 31:16 — — — — — — USBIF FCEIF — — — — DMA3IF DMA2IF DMA1IF DMA0IF 0000 X 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE — — — OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 X 1060 IEC0 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 — — — — — — USBIE FCEIE — — — — DMA3IE DMA2IE DMA1IE DMA0IE 0000 1070 IEC1 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000 1090 IPC0 15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000 10A0 IPC1 15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000 10B0 IPC2 15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000 10C0 IPC3 15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 10D0 IPC4 15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000 31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000 10E0 IPC5 15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 10F0 IPC6 15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000 © 2 1100 IPC7 31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000 01 15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000 1 M 1110 IPC8 31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000 ic 15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0> 0000 ro 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000 chip 1120 IPC9 15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000 T 31:16 — — — — — — — — — — — — — — — — 0000 ec 1140 IPC11 15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000 h n Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. o lo Note 1: Except where noted, all registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section12.1.1 “CLR, SET and INV g Registers” for more information. y In 2: This register does not have associated CLR, SET, and INV registers. c .

© TABLE 4-6: INTERRUPT REGISTERS MAP FOR THE PIC32MX420F032H DEVICE ONLY(1) 2 01 ss Bits 1 Microchip T Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets echn 1000 INTCON 3115:1:06 —— —— —— MV—EC —— — TPC—<2:0> — —— —— —— INT—4EP INT—3EP INT—2EP INT—1EP INSTS00EP 00000000 o logy 1010 INTSTAT(2)3115:1:06 —— —— —— —— —— — SRIP—L<2:0> — —— —— — — —VEC<5:0>— — — 00000000 In 31:16 0000 c 1020 IPTMR IPTMR<31:0> . 15:0 0000 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF — — — OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 1030 IFS0 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000 31:16 — — — — — — USBIF FCEIF — — — — — — — — 0000 1040 IFS1 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE — — — OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 1060 IEC0 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 — — — — — — USBIE FCEIE — — — — — — — — 0000 1070 IEC1 15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000 1090 IPC0 15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000 10A0 IPC1 15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000 10B0 IPC2 15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000 10C0 IPC3 15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000 P 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 10D0 IPC4 15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000 I C 31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000 10E0 IPC5 15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 3 10F0 IPC6 31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 2 15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000 M 31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000 1100 IPC7 15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000 X 31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000 1110 IPC8 15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0> 0000 3 31:16 — — — — — — — — — — — — — — — — 0000 X DS 1140 IPC11 15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000 61 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X 14 Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV / 3 Registers” for more information. 4 H -p 2: This register does not have associated CLR, SET, and INV registers. X a g e 5 X 5

D TABLE 4-7: TIMER1-5 REGISTERS MAP(1) P S 6 1 s Bits I 143H-page 5 Virtual Addres(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 6 31:16 — — — — — — — — — — — — — — — — 0000 0600 T1CON 15:0 ON — SIDL TWDIS TWIP — — — TGATE — TCKPS<1:0> — TSYNC TCS — 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 3 0610 TMR1 15:0 TMR1<15:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 0620 PR1 X 15:0 PR1<15:0> FFFF 31:16 — — — — — — — — — — — — — — — — 0000 / 0800 T2CON 4 15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS(2) — 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 0810 TMR2 15:0 TMR2<15:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 0820 PR2 15:0 PR2<15:0> FFFF 31:16 — — — — — — — — — — — — — — — — 0000 0A00 T3CON 15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> — — TCS(2) — 0000 31:16 — — — — — — — — — — — — — — — — 0000 0A10 TMR3 15:0 TMR3<15:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 0A20 PR3 15:0 PR3<15:0> FFFF 31:16 — — — — — — — — — — — — — — — — 0000 0C00 T4CON 15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS(2) — 0000 31:16 — — — — — — — — — — — — — — — — 0000 0C10 TMR4 15:0 TMR4<15:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 0C20 PR4 15:0 PR4<15:0> FFFF 31:16 — — — — — — — — — — — — — — — — 0000 0E00 T5CON © 15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> — — TCS(2) — 0000 20 31:16 — — — — — — — — — — — — — — — — 0000 1 0E10 TMR5 1 15:0 TMR5<15:0> 0000 M icro 0E20 PR5 3115:1:06 — — — — — — — —PR5<15:0>— — — — — — — — 0F0F0F0F c hip Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. T Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more e information. c h 2: This bit is not available on 64-pin devices. n o lo g y In c .

© TABLE 4-8: INPUT CAPTURE1-5 REGISTERS MAP 2 01 ss Bits 1 Microchip T Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets ech 2000 IC1CON(1) 31:16 — — — — — — — — — — — — — — — — 0000 n 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 o lo 31:16 xxxx g 2010 IC1BUF IC1BUF<31:0> y In 15:0 xxxx c 31:16 — — — — — — — — — — — — — — — — 0000 . 2200 IC2CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 31:16 xxxx 2210 IC2BUF IC2BUF<31:0> 15:0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 2400 IC3CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 31:16 xxxx 2410 IC3BUF IC3BUF<31:0> 15:0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 2600 IC4CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 31:16 xxxx 2610 IC4BUF IC4BUF<31:0> 15:0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 2800 IC5CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 31:16 xxxx 2810 IC5BUF IC5BUF<31:0> 15:0 xxxx P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. I C 3 2 M X 3 X D S 6 X 1 1 4 / 3 4 H -p X a g e 5 X 7

D TABLE 4-9: OUTPUT COMPARE1-5 REGISTERS MAP(1) P S 6 1 s Bits I 143H-page 5 Virtual Addres(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 8 31:16 — — — — — — — — — — — — — — — — 0000 3000 OC1CON 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 X 31:16 xxxx 3 3010 OC1R OC1R<31:0> 15:0 xxxx X 31:16 xxxx 3020 OC1RS OC1RS<31:0> X 15:0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 / 3200 OC2CON 4 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 X 31:16 xxxx 3210 OC2R OC2R<31:0> 15:0 xxxx X 31:16 xxxx 3220 OC2RS OC2RS<31:0> 15:0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 3400 OC3CON 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 31:16 xxxx 3410 OC3R OC3R<31:0> 15:0 xxxx 31:16 xxxx 3420 OC3RS OC3RS<31:0> 15:0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 3600 OC4CON 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 31:16 xxxx 3610 OC4R OC4R<31:0> 15:0 xxxx 31:16 xxxx 3620 OC4RS OC4RS<31:0> 15:0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 3800 OC5CON © 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 20 31:16 xxxx 1 3810 OC5R OC5R<31:0> 1 15:0 xxxx M icro 3820 OC5RS 3115:1:06 OC5RS<31:0> xxxxxxxx c hip Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. T Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more e information. c h n o lo g y In c .

© TABLE 4-10: I2C1-2 REGISTERS MAP(1) 2 01 ss Bits 1 Microchip T Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets ech 5000 I2C1CON 31:16 — — — — — — — — — — — — — — — — 0000 n 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 o lo 31:16 — — — — — — — — — — — — — — — — 0000 g 5010 I2C1STAT y In 15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 c 0000 . 31:16 — — — — — — — — — — — — — — — — 5020 I2C1ADD 0000 15:0 — — — — — — ADD<9:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 5030 I2C1MSK 15:0 — — — — — — MSK<9:0> 0000 5040 31:16 — — — — — — — — — — — — — — — — 0000 I2C1BRG 15:0 — — — — I2C1BRG<11:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 5050 I2C1TRN 15:0 — — — — — — — — I2CT1DATA<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 5260 I2C1RCV 15:0 — — — — — — — — I2CR1DATA<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 5200 I2C2CON 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 31:16 — — — — — — — — — — — — — — — — 0000 5210 I2C2STAT 15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 — — — — — — — — — — — — — — — — 0000 5220 I2C2ADD P 15:0 — — — — — — ADD<9:0> 0000 5230 I2C2MSK 31:16 — — — — — — — — — — — — — — — — 0000 IC 15:0 — — — — — — MSK<9:0> 0000 5240 31:16 — — — — — — — — — — — — — — — — 0000 3 I2C2BRG 15:0 — — — — I2C2BRG<11:0> 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 M 5250 I2C2TRN 15:0 — — — — — — — — I2CT2DATA<7:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 5260 I2C2RCV 15:0 — — — — — — — — I2CR2DATA<7:0> 0000 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X D Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV S 6 Registers” for more information. X 1 1 4 / 3 4 H -p X a g e 5 X 9

D TABLE 4-11: UART1-2 REGISTERS MAP P S 6 1 s Bits I 143H-page 6 Virtual Addres(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 0 31:16 — — — — — — — — — — — — — — — — 0000 6000 U1MODE(1) 15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000 X 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000 3 6010 U1STA(1) 15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 X 31:16 — — — — — — — — — — — — — — — — 0000 6020 U1TXREG X 15:0 — — — — — — — TX8 Transmit Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 / 6030 U1RXREG 4 15:0 — — — — — — — RX8 Receive Register 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 6040 U1BRG(1) 15:0 BRG<15:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 6200 U2MODE(1) 15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000 6210 U2STA(1) 15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 31:16 — — — — — — — — — — — — — — — — 0000 6220 U2TXREG 15:0 — — — — — — — TX8 Transmit Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 6230 U2RXREG 15:0 — — — — — — — RX8 Receive Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 6240 U2BRG(1) 15:0 BRG<15:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

© TABLE 4-12: SPI1-2 REGISTERS MAP(1,2) 2 01 ss Bits 1 Microchip T Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets ech 5800 SPI1CON 31:16 FRMEN FRMSYNC FRMPOL — — — — — — — — — — — SPIFE — 0000 n 15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — — — — — 0000 o lo 31:16 — — — — — — — — — — — — — — — — 0000 g 5810 SPI1STAT y In 15:0 — — — — SPIBUSY — — — — SPIROV — — SPITBE — — SPIRBF 0008 c 31:16 0000 . 5820 SPI1BUF DATA<31:0> 15:0 0000 31:16 — — — — — — — — — — — — — — — — 0000 5830 SPI1BRG 15:0 — — — — — — — BRG<8:0> 0000 31:16 FRMEN FRMSYNC FRMPOL — — — — — — — — — — — SPIFE — 0008 5A00 SPI2CON 15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 5A10 SPI2STAT 15:0 — — — — SPIBUSY — — — — SPIROV — — SPITBE — — SPIRBF 0008 31:16 0000 5A20 SPI2BUF DATA<31:0> 15:0 0000 31:16 — — — — — — — — — — — — — — — — 0000 5A30 SPI2BRG 15:0 — — — — — — — BRG<8:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. 2: SPI2 Module is not present on PIC32MX420FXXXX/440FXXXX devices. P I C 3 2 M X 3 X D S 6 X 1 1 4 / 3 4 H -p X a g e 6 X 1

D TABLE 4-13: ADC REGISTERS MAP P S 6 1 s Bits I 143H-page 6 Virtual Addres(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 2 31:16 — — — — — — — — — — — — — — — — 0000 9000 AD1CON1(1) 15:0 ON — SIDL — — FORM<2:0> SSRC<2:0> CLRASAM — ASAM SAMP DONE 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 3 9010 AD1CON2(1) 15:0 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — — BUFS — SMPI<3:0> BUFM ALTS 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 9020 AD1CON3(1) X 15:0 ADRC — — SAMC<4:0> ADCS<7:0> 0000 31:16 CH0NB — — — CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000 / 9040 AD1CHS(1) 4 15:0 — — — — — — — — — — — — — — — — 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 9060 AD1PCFG(1) 15:0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 9050 AD1CSSL(1) 15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 31:16 0000 9070 ADC1BUF0 ADC Result Word 0 (ADC1BUF0<31:0>) 15:0 0000 31:16 0000 9080 ADC1BUF1 ADC Result Word 1 (ADC1BUF1<31:0>) 15:0 0000 31:16 0000 9090 ADC1BUF2 ADC Result Word 2 (ADC1BUF2<31:0>) 15:0 0000 31:16 0000 90A0 ADC1BUF3 ADC Result Word 3 (ADC1BUF3<31:0>) 15:0 0000 31:16 0000 90B0 ADC1BUF4 ADC Result Word 4 (ADC1BUF4<31:0>) 15:0 0000 31:16 0000 90C0 ADC1BUF5 ADC Result Word 5 (ADC1BUF5<31:0>) 15:0 0000 31:16 0000 90D0 ADC1BUF6 ADC Result Word 6 (ADC1BUF6<31:0>) © 15:0 0000 20 31:16 0000 1 90E0 ADC1BUF7 ADC Result Word 7 (ADC1BUF7<31:0>) 1 15:0 0000 M icro 90F0 ADC1BUF8 3115:1:06 ADC Result Word 8 (ADC1BUF8<31:0>) 00000000 c hip T 9100 ADC1BUF9 3115:1:06 ADC Result Word 9 (ADC1BUF9<31:0>) 00000000 e ch Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. no Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. lo g y In c .

© TABLE 4-13: ADC REGISTERS MAP (CONTINUED) 2 0 s Bits 1 s 1 Microchip Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T e 31:16 0000 c 9110 ADC1BUFA ADC Result Word A (ADC1BUFA<31:0>) hn 15:0 0000 o lo 31:16 0000 g 9120 ADC1BUFB ADC Result Word B (ADC1BUFB<31:0>) y 15:0 0000 Inc 31:16 0000 . 9130 ADC1BUFC ADC Result Word C (ADC1BUFC<31:0>) 15:0 0000 31:16 0000 9140 ADC1BUFD ADC Result Word D (ADC1BUFD<31:0>) 15:0 0000 31:16 0000 9150 ADC1BUFE ADC Result Word E (ADC1BUFE<31:0>) 15:0 0000 31:16 0000 9160 ADC1BUFF ADC Result Word F (ADC1BUFF<31:0>) 15:0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. P I C 3 2 M X 3 X D S 6 X 1 1 4 / 3 4 H -p X a g e 6 X 3

D TABLE 4-14: DMA GLOBAL REGISTERS MAPFOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY P S 6 1 s Bits I 143H-page 6 Virtual Addres(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 4 31:16 — — — — — — — — — — — — — — — — 0000 3000 DMACON(1) 15:0 ON — SIDL SUSPEND — — — — — — — — — — — — 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 3 3010 DMASTAT 15:0 — — — — — — — — — — — — RDWR — DMACH<1:0> 0000 X 31:16 0000 3020 DMAADDR DMAADDR<31:0> X 15:0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 4 Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. X TABLE 4-15: DMA CRC REGISTERS MAPFOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) X s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — 0000 3030 DCRCCON 15:0 — — — — PLEN<3:0> CRCEN CRCAPP — — — — CRCCH<1:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 3040 DCRCDATA 15:0 DCRCDATA<15:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 3050 DCRCXOR 15:0 DCRCXOR<15:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

© TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX 20 DEVICES ONLY(1) 1 1 M ss Bits icrochip Tec Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets h n 31:16 — — — — — — — — — — — — — — — — 0000 olo 3060 DCH0CON 15:0 — — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000 g y In 3070 DCH0ECON31:16 — — — — — — — — CHAIRQ<7:0> 00FF c. 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 3080 DCH0INT 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 3090 DCH0SSA CHSSA<31:0> 15:0 0000 31:16 0000 30A0 DCH0DSA CHDSA<31:0> 15:0 0000 31:16 — — — — — — — — — — — — — — — — 0000 30B0 DCH0SSIZ 15:0 — — — — — — — — CHSSIZ<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 30C0 DCH0DSIZ 15:0 — — — — — — — — CHDSIZ<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 30D0 DCH0SPTR 15:0 — — — — — — — — CHSTR<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 30E0 DCH0DPTR 15:0 — — — — — — — — CHDPTR<7:0> 0000 30F0 DCH0CSIZ 31:16 — — — — — — — — — — — — — — — — 0000 P 15:0 — — — — — — — — CHCSIZ<7:0> 0000 I 31:16 — — — — — — — — — — — — — — — — 0000 C 3100 DCH0CPTR 15:0 — — — — — — — — CHCPTR<7:0> 0000 3 31:16 — — — — — — — — — — — — — — — — 0000 3110 DCH0DAT 15:0 — — — — — — — — CHPDAT<7:0> 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 M 3120 DCH1CON 15:0 — — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000 X 31:16 — — — — — — — — CHAIRQ<7:0> 00FF 3130 DCH1ECON 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00 3 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 X D 3140 DCH1INT S6 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 X 114 3150 DCH1SSA 31:16 CHSSA<31:0> 0000 / 3 15:0 0000 4 H -p Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X a Note 1: All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, g e 6 SET and INV Registers” for more information. X 5

D TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX P S6 DEVICES ONLY(1) (CONTINUED) 1 I 1 C 4 s Bits 3 s H-page 66 Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32M 31:16 0000 X 3160 DCH1DSA CHDSA<31:0> 15:0 0000 3 3170 DCH1SSIZ 31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 — — — — — — — — CHSSIZ<7:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 3180 DCH1DSIZ 15:0 — — — — — — — — CHDSIZ<7:0> 0000 / 4 31:16 — — — — — — — — — — — — — — — — 0000 3190 DCH1SPTR X 15:0 — — — — — — — — CHSPTR<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 31A0 DCH1DPTR 15:0 — — — — — — — — CHDPTR<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 31B0 DCH1CSIZ 15:0 — — — — — — — — CHCSIZ<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 31C0 DCH1CPTR 15:0 — — — — — — — — CHCPTR<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 31D0 DCH1DAT 15:0 — — — — — — — — CHPDAT<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 31E0 DCH2CON 15:0 — — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000 31:16 — — — — — — — — CHAIRQ<7:0> 00FF 31F0 DCH2ECON 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 3200 DCH2INT 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 3210 DCH2SSA CHSSA<31:0> 15:0 0000 © 31:16 0000 20 3220 DCH2DSA 15:0 CHDSA<31:0> 0000 1 1 31:16 — — — — — — — — — — — — — — — — 0000 M 3230 DCH2SSIZ ic 15:0 — — — — — — — — CHSSIZ<7:0> 0000 ro 31:16 — — — — — — — — — — — — — — — — 0000 c 3240 DCH2DSIZ hip 15:0 — — — — — — — — CHDSIZ<7:0> 0000 T 31:16 — — — — — — — — — — — — — — — — 0000 e 3250 DCH2SPTR ch 15:0 — — — — — — — — CHSPTR<7:0> 0000 no Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. lo Note 1: All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, g y SET and INV Registers” for more information. In c .

© TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX 20 DEVICES ONLY(1) (CONTINUED) 1 1 M ss Bits icrochip Tec Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets hn 31:16 — — — — — — — — — — — — — — — — 0000 o 3260 DCH2DPTR lo 15:0 — — — — — — — — CHDPTR<7:0> 0000 g y In 3270 DCH2CSIZ 31:16 — — — — — — — — — — — — — — — — 0000 c 15:0 — — — — — — — — CHCSIZ<7:0> 0000 . 31:16 — — — — — — — — — — — — — — — — 0000 3280 DCH2CPTR 15:0 — — — — — — — — CHCPTR<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 3290 DCH2DAT 15:0 — — — — — — — — CHPDAT<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 32A0 DCH3CON 15:0 — — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000 31:16 — — — — — — — — CHAIRQ<7:0> 00FF 32B0 DCH3ECON 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 32C0 DCH3INT 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 32D0 DCH3SSA CHSSA<31:0> 15:0 0000 31:16 0000 32E0 DCH3DSA CHDSA<31:0> 15:0 0000 31:16 — — — — — — — — — — — — — — — — 0000 32F0 DCH3SSIZ P 15:0 — — — — — — — — CHSSIZ<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 I 3300 DCH3DSIZ C 15:0 — — — — — — — — CHDSIZ<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 3 3310 DCH3SPTR 15:0 — — — — — — — — CHSTR<7:0> 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 M 3320 DCH3DPTR 15:0 — — — — — — — — CHDPTR<7:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 3330 DCH3CSIZ 15:0 — — — — — — — — CHCSIZ<7:0> 0000 3 31:16 — — — — — — — — — — — — — — — — 0000 X D 3340 DCH3CPTR S 15:0 — — — — — — — — CHCPTR<7:0> 0000 6 X 1 31:16 — — — — — — — — — — — — — — — — 0000 1 3350 DCH3DAT 43 15:0 — — — — — — — — CHPDAT<7:0> 0000 /4 H Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. -pa Note 1: All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, X g SET and INV Registers” for more information. e 6 X 7

D TABLE 4-17: COMPARATOR REGISTERS MAP(1) P S 6 1 s Bits I 143H-page 6 Virtual Addres(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 8 31:16 — — — — — — — — — — — — — — — — 0000 A000 CM1CON 15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3 X 31:16 — — — — — — — — — — — — — — — — 0000 3 A010 CM2CON 15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3 X 31:16 — — — — — — — — — — — — — — — — 0000 A060 CMSTAT X 15:0 — — SIDL — — — — — — — — — — — C2OUT C1OUT 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 4 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. X X TABLE 4-18: COMPARATOR VOLTAGE REFERENCE REGISTERS MAP(1) s Bits s Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — 0000 9800 CVRCON 15:0 ON — — — — — — — — CVROE CVRR CVRSS CVR<3:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

© TABLE 4-19: FLASH CONTROLLER REGISTERS MAP 2 01 ss Bits 1 Microchip T Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets ech F400 NVMCON(1) 31:16 — — — — — — — — — — — — — — — — 0000 n 15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — NVMOP<3:0> 0000 o lo 31:16 0000 g F410 NVMKEY NVMKEY<31:0> y In 15:0 0000 c 31:16 0000 . F420 NVMADDR(1) NVMADDR<31:0> 15:0 0000 31:16 0000 F430 NVMDATA NVMDATA<31:0> 15:0 0000 NVMSRC 31:16 0000 F440 NVMSRCADDR<31:0> ADDR 15:0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-20: SYSTEM CONTROL REGISTERS MAP(1,2) s Bits s Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — PLLODIV<2:0> FRCDIV<2:0> — SOSCRDY — PBDIV<1:0> PLLMULT<2:0> 0000 P F000 OSCCON 15:0 — COSC<2:0> — NOSC<2:0> CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN SOSCEN OSWEN 0000 I 31:16 — — — — — — — — — — — — — — — — 0000 C F010 OSCTUN 15:0 — — — — — — — — — — TUN<5:0> 0000 3 0000 WDTCON 31:16 — — — — — — — — — — — — — — — — 0000 2 15:0 ON — — — — — — — — SWDTPS<4:0> — WDTCLR 0000 M 31:16 — — — — — — — — — — — — — — — — 0000 F600 RCON 15:0 — — — — — — CMR VREGS EXTR SWR — WDTO SLEEP IDLE BOR POR 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 F610 RSWRST 3 15:0 — — — — — — — — — — — — — — — SWRST 0000 X D 31:16 0000 S F230 SYSKEY(3) SYSKEY<31:0> 6 15:0 0000 X 1 14 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 3 Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV 4 H -p Registers” for more information. X a 2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. g e 6 3: This register does not have associated CLR, SET, and INV registers. X 9

D TABLE 4-21: PORTA REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, P S 61 PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) I 1 C 43H-page 70 Virtual Address(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32M X 31:16 — — — — — — — — — — — — — — — — 0000 6000 TRISA 15:0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF 3 31:16 — — — — — — — — — — — — — — — — 0000 X 6010 PORTA 15:0 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx X 31:16 — — — — — — — — — — — — — — — — 0000 6020 LATA 15:0 LATA15 LATA14 — — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx /4 31:16 — — — — — — — — — — — — — — — — 0000 6030 ODCA X 15:0 ODCA15 ODCA14 — — — ODCA10 ODCA9 — ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-22: PORTB REGISTERS MAP(1) s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — 0000 6040 TRISB 15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF 31:16 — — — — — — — — — — — — — — — — 0000 6050 PORTB 15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 6060 LATB 15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx © 2 6070 ODCB 31:16 — — — — — — — — — — — — — — — — 0000 01 15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 1 M Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ic Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more ro information. c h ip T e c h n o lo g y In c .

© TABLE 4-23: PORTC REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, 20 PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) 1 1 M ss Bits icrochip Tec Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets h n 31:16 — — — — — — — — — — — — — — — — 0000 olo 6080 TRISC 15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F01E g y In 6090 PORTC 31:16 — — — — — — — — — — — — — — — — 0000 c. 15:0 RC15 RC14 RC13 RC12 — — — — — — — RC4 RC3 RC2 RC1 — xxxx 31:16 — — — — — — — — — — — — — — — — 0000 60A0 LATC 15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 — xxxx 31:16 — — — — — — — — — — — — — — — — 0000 60B0 ODCC 15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — ODCC4 ODCC3 ODCC2 ODCC1 — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-24: PORTC REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets PI 31:16 — — — — — — — — — — — — — — — — 0000 C 6080 TRISC 15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000 3 31:16 — — — — — — — — — — — — — — — — 0000 6090 PORTC 2 15:0 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx M 31:16 — — — — — — — — — — — — — — — — 0000 60A0 LATC 15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — — — — — — xxxx X 31:16 — — — — — — — — — — — — — — — — 0000 60B0 ODCC 3 15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — — — — — — 0000 X D Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S6 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more X 1 information. 1 4 / 3 4 H -p X a g e 7 X 1

D TABLE 4-25: PORTD REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, P S 61 PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) I 1 C 43H-page 72 Virtual Address(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32M X 31:16 — — — — — — — — — — — — — — — — 0000 60C0 TRISD 15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF 3 31:16 — — — — — — — — — — — — — — — — 0000 X 60D0 PORTD 15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx X 31:16 — — — — — — — — — — — — — — — — 0000 60E0 LATD 15:0 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx /4 31:16 — — — — — — — — — — — — — — — — 0000 60F0 ODCD X 15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-26: PORTD REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — 0000 60C0 TRISD 15:0 — — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0FFF 31:16 — — — — — — — — — — — — — — — — 0000 60D0 PORTD 15:0 — — — — RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx © 20 60E0 LATD 31:16 — — — — — — — — — — — — — — — — 0000 1 15:0 — — — — LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx 1 M 31:16 — — — — — — — — — — — — — — — — 0000 icro 60F0 ODCD 15:0 — — — — ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 c Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. h ip Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more T information. e c h n o lo g y In c .

© TABLE 4-27: PORTE REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, 20 PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) 1 1 M ss Bits icrochip Tec Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets h n 31:16 — — — — — — — — — — — — — — — — 0000 olo 6100 TRISE 15:0 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF g y In 6110 PORTE 31:16 — — — — — — — — — — — — — — — — 0000 c. 15:0 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 6120 LATE 15:0 — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 6130 ODCE 15:0 — — — — — — ODCE9 ODCE8 ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-28: PORTE REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets PI 31:16 — — — — — — — — — — — — — — — — 0000 C 6100 TRISE 15:0 — — — — — — — — TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF 3 31:16 — — — — — — — — — — — — — — — — 0000 6110 PORTE 2 15:0 — — — — — — — — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx M 31:16 — — — — — — — — — — — — — — — — 0000 6120 LATE 15:0 — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx X 31:16 — — — — — — — — — — — — — — — — 0000 6130 ODCE 3 15:0 — — — — — — — — ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 X D Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S6 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more X 1 information. 1 4 / 3 4 H -p X a g e 7 X 3

D TABLE 4-29: PORTF REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L AND PIC32MX360F512L DEVICES P S 61 ONLY(1) I 1 C 43H-page 74 Virtual Address(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32M X 31:16 — — — — — — — — — — — — — — — — 0000 6140 TRISF 15:0 — — TRISF13 TRISF12 — — — TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FF 3 31:16 — — — — — — — — — — — — — — — — 0000 X 6150 PORTF 15:0 — — RF13 RF12 — — — RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx X 31:16 — — — — — — — — — — — — — — — — 0000 6160 LATF 15:0 — — LATF13 LATF12 — — — LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx /4 31:16 — — — — — — — — — — — — — — — — 0000 6170 ODCF X 15:0 — — ODCF13 ODCF12 — — — ODCF8 ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-30: PORTF REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — 0000 6140 TRISF 15:0 — — TRISF13 TRISF12 — — — TRISF8 — — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F 31:16 — — — — — — — — — — — — — — — — 0000 6150 PORTF 15:0 — — RF13 RF12 — — — RF8 — — RF5 RF4 RF3 RF2 RF1 RF0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 6160 LATF 15:0 — — LATF13 LATF12 — — — LATF8 — — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx © 2 6170 ODCF 31:16 — — — — — — — — — — — — — — — — 0000 01 15:0 — — ODCF13 ODCF12 — — — ODCF8 — — ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 1 M Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ic Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more ro information. c h ip T e c h n o lo g y In c .

© TABLE 4-31: PORTF REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, 20 PIC32MX340F256H AND PIC32MX340F512H DEVICES ONLY(1) 1 1 M ss Bits icrochip Tec Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets h n 31:16 — — — — — — — — — — — — — — — — 0000 olo 6140 TRISF 15:0 — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 07FF g y In 6150 PORTF 31:16 — — — — — — — — — — — — — — — — 0000 c. 15:0 — — — — — — — — — RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 6160 LATF 15:0 — — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 6170 ODCF 15:0 — — — — — — — — — ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-32: PORTF REGISTERS MAP FOR PIC32MX420F032H, PIC32MX440F128H AND PIC2MX440F256H DEVICES ONLY(1) s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — 0000 P 6140 TRISF 15:0 — — — — — — — — — — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 03FF I 31:16 — — — — — — — — — — — — — — — — 0000 C 6150 PORTF 15:0 — — — — — — — — — — RF5 RF4 RF3 RF2 RF1 RF0 xxxx 3 31:16 — — — — — — — — — — — — — — — — 0000 6160 LATF 2 15:0 — — — — — — — — — — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx M 31:16 — — — — — — — — — — — — — — — — 0000 6170 ODCF 15:0 — — — — — — — — — — ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 X Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more 3 information. X D S 6 X 1 1 4 / 3 4 H -p X a g e 7 X 5

D TABLE 4-33: PORTG REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, P S 61 PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) I 1 C 43H-page 76 Virtual Address(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32M X 31:16 — — — — — — — — — — — — — — — — 0000 6180 TRISG 15:0 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF 3 31:16 — — — — — — — — — — — — — — — — 0000 X 6190 PORTG 15:0 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx X 31:16 — — — — — — — — — — — — — — — — 0000 61A0 LATG 15:0 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx /4 31:16 — — — — — — — — — — — — — — — — 0000 61B0 ODCG X 15:0 ODCG15 ODCG14 ODCG13 ODCG12 — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 ODCG1 ODCG0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-34: PORTG REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — 0000 6180 TRISG 15:0 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 — — 03cc 31:16 — — — — — — — — — — — — — — — — 0000 6190 PORTG 15:0 — — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 — — xxxx © 20 61A0 LATG 31:16 — — — — — — — — — — — — — — — — 0000 1 15:0 — — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 — — xxxx 1 M 31:16 — — — — — — — — — — — — — — — — 0000 icro 61B0 ODCG 15:0 — — — — — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 — — 0000 c Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. h ip Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more T information. e c h n o lo g y In c .

© TABLE 4-35: CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, 20 PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1) 1 1 M ss Bits icrochip Tec Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets h n 31:16 — — — — — — — — — — — — — — — — 0000 olo 61C0 CNCON 15:0 ON — SIDL — — — — — — — — — — — — — 0000 g y In 61D0 CNEN 31:16 — — — — — — — — — — CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000 c. 15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000 31:16 — — — — — — — — — — CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000 61E0 CNPUE 15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE1 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1) s Bits s Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — 0000 P 61C0 CNCON 15:0 ON — SIDL — — — — — — — — — — — — — 0000 I 31:16 — — — — — — — — — — — — — CNEN18 CNEN17 CNEN16 0000 C 61D0 CNEN 15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000 3 31:16 — — — — — — — — — — — — — CNPUE18 CNPUE17 CNPUE16 0000 61E0 CNPUE 2 15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE1 0000 M Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more X information. 3 X D S 6 X 1 1 4 / 3 4 H -p X a g e 7 X 7

D P S 61 TABLE 4-37: PARALLEL MASTER PORT REGISTERS MAP(1) I 1 C 43H-page 78 Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32M X 31:16 — — — — — — — — — — — — — — — — 0000 7000 PMCON 15:0 ON — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P — WRSP RDSP 0000 3 31:16 — — — — — — — — — — — — — — — — 0000 X 7010 PMMODE 15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 7020 PMADDR 15:0 CS2EN/A15CS1EN/A14 ADDR<13:0> 0000 /4 31:16 0000 7030 PMDOUT DATAOUT<31:0> X 15:0 0000 31:16 0000 X 7040 PMDIN DATAIN<31:0> 15:0 0000 31:16 — — — — — — — — — — — — — — — — 0000 7050 PMAEN 15:0 PTEN<15:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 7060 PMSTAT 15:0 IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-38: PROGRAMMING AND DIAGNOSTICS REGISTERS MAP s Bits s Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets © 2 F200 DDPCON 31:16 — — — — — — — — — — — — — — — — 0000 01 15:0 — — — — — — — — — — — — JTAGEN TROEN — — 0008 1 M Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ic ro c h ip T e c h n o lo g y In c .

© TABLE 4-39: PREFETCH REGISTERS MAP 2 0 s Bits 1 s 1 Microchip Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T e 31:16 — — — — — — — — — — — — — — — CHECOH 0000 c 4000 CHECON(1) hn 15:0 — — — — — — DCSZ<1:0> — — PREFEN<1:0> — PFMWS<2:0> 0007 o logy 4010 CHEACC(1) 3115::106 CHE—WEN —— —— —— —— —— —— —— —— —— —— —— — —CHEIDX<3:0—> — 00000x0x In 31:16 LTAGBOOT — — — — — — — LTAG<23:16> xxx0 c. 4020 CHETAG(1) 15:0 LTAG<15:4> LVALID LLOCK LTYPE — xxx2 31:16 — — — — — — — — — — — — — — — — 0000 4030 CHEMSK(1) 15:0 LMASK<15:5> — — — — — xxxx 31:16 xxxx 4040 CHEW0 CHEW0<31:0> 15:0 xxxx 31:16 xxxx 4050 CHEW1 CHEW1<31:0> 15:0 xxxx 31:16 xxxx 4060 CHEW2 CHEW2<31:0> 15:0 xxxx 31:16 xxxx 4070 CHEW3 CHEW3<31:0> 15:0 xxxx 31:16 — — — — — — — CHELRU<24:16> 0000 4080 CHELRU 15:0 CHELRU<15:0> 0000 31:16 xxxx 4090 CHEHIT CHEHIT<31:0> 15:0 xxxx 31:16 xxxx 40A0 CHEMIS CHEMIS<31:0> P 15:0 xxxx 31:16 xxxx I 40C0 CHEPFABT CHEPFABT<31:0> C 15:0 xxxx Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. 2 M X 3 X D S 6 X 1 1 4 / 3 4 H -p X a g e 7 X 9

D TABLE 4-40: RTCC REGISTERS MAP(1) P S 6 1 s Bits I 143H-page 8 Virtual Addres(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 0 31:16 — — — — — — CAL<11:0> 0000 0200 RTCCON 15:0 ON — SIDL — — — — — RTSECSELRTCCLKON — — RTCWREN RTCSYNC HALFSEC RTCOE 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 3 0210 RTCALRM 15:0 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000 X 31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx 0220 RTCTIME X 15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00 31:16 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> xxxx / 0230 RTCDATE 4 15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx0x X 31:16 MIN10<3:0> MIN01<3:0> MIN10<3:0> MIN01<3:0> xxxx 0240 ALRMTIME 15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00 X 31:16 — — — — — — — — MONTH10<3:0> MONTH01<3:0> 00xx 0250 ALRMDATE 15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx0x Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-41: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY s Bits s Virtual Addre(BFC0_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 31:16 — — — — — — — — — — — — — — — — xxxx 2FF0 DEVCFG3 15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8 USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0 xxxx 31:16 — — — — — — — — — — — — — FPLLODIV<2:0> xxxx 2FF4 DEVCFG2 © 15:0 UPLLEN(1) — — — — UPLLIDIV<2:0>(1) — FPLLMUL<2:0> — FPLLIDIV<2:0> xxxx 2 0 31:16 — — — — — — — — FWDTEN — — WDTPS<4:0> xxxx 1 2FF8 DEVCFG1 1 M 15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0> IESO — FSOSCEN — — FNOSC<2:0> xxxx ic 31:16 — — — CP — — — BWP — — — — PWP19 PWP18 PWP17 PWP16 xxxx roc 2FFC DEVCFG0 15:0 PWP15 PWP14 PWP13 PWP12 — — — — — — — — ICESEL — DEBUG<1:0> xxxx h ip Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. T Note 1: These bits are only available on PIC32MX4XX devices. e c h n o lo g y In c .

© TABLE 4-42: DEVICE AND REVISION ID SUMMARY 2 0 s Bits 1 s 1 Microchip Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T e 31:16 VER<3:0> DEVID<27:16> xxxx c F220 DEVID hn 15:0 DEVID<15:0> xxxx olo Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. g y In c . P I C 3 2 M X 3 X D S 6 X 1 1 4 / 3 4 H -p X a g e 8 X 1

D TABLE 4-43: USB REGISTERS MAP(1) P S 6 1 s Bits I 143H-page 8 Virtual Addres(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 2 U1OTG 31:16 — — — — — — — — — — — — — — — — 5040 IR(2) 15:0 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000 X U1OTG 31:16 — — — — — — — — — — — — — — — — 0000 3 5050 IE 15:0 — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE 0000 X U1OTG 31:16 — — — — — — — — — — — — — — — — 0000 5060 STAT(3) 15:0 — — — — — — — — ID — LSTATE — SESVD SESEND — VBUSVD 0000 X 5070 U1OTG 31:16 — — — — — — — — — — — — — — — — 0000 /4 CON 15:0 — — — — — — — — DPPULUP DMPULUPDPPULDWNDMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 5080 U1PWRC 15:0 — — — — — — — — UACTPND(4) — — USLPGRD — — USUSPEND USBPWR 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 5200 U1IR(2) URSTIF 0000 15:0 — — — — — — — — STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF 0000 31:16 — — — — — — — — — — — — — — — — 0000 5210 U1IE URSTIE 0000 15:0 — — — — — — — — STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE DETACHIE 0000 31:16 — — — — — — — — — — — — — — — — 0000 5220 U1EIR CRC5EF 0000 15:0 — — — — — — — — BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF PIDEF EOFEF 0000 31:16 — — — — — — — — — — — — — — — — 0000 5230 U1EIE CRC5EE 0000 15:0 — — — — — — — — BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE PIDEE EOFEE 0000 31:16 — — — — — — — — — — — — — — — — 0000 5240 U1STAT(3) 15:0 — — — — — — — — ENDPT<3:0>(4) DIR PPBI — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 © 5250 U1CON PKTDIS USBEN 0000 20 15:0 — — — — — — — — JSTATE(4) SE0(4) TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN 0000 1 1 31:16 — — — — — — — — — — — — — — — — 0000 M 5260 U1ADDR ic 15:0 — — — — — — — — LSPDEN DEVADDR<6:0> 0000 ro 31:16 — — — — — — — — — — — — — — — — 0000 chip 5270 U1BDTP1 15:0 — — — — — — — — BDTPTRL<7:1> — 0000 T Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ec Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV h Registers” for more information. n o 2: This register does not have associated CLR, SET, and INV registers. log 3: All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported. y In 4: The reset value for this bit is undefined. c .

© TABLE 4-43: USB REGISTERS MAP(1) (CONTINUED) 2 0 s Bits 1 s 1 Microchip Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T e 31:16 — — — — — — — — — — — — — — — — 0000 c 5280 U1FRML(3) hn 15:0 — — — — — — — — FRML<7:0> 0000 o log 5290 U1FRMH(3) 31:16 — — — — — — — — — — — — — — — — 0000 y 15:0 — — — — — — — — — — — — — FRMH<10:8> 0000 Inc 31:16 — — — — — — — — — — — — — — — — 0000 . 52A0 U1TOK 15:0 — — — — — — — — PID<3:0> EP<3:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 52B0 U1SOF 15:0 — — — — — — — — CNT<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 52C0 U1BDTP2 15:0 — — — — — — — — BDTPTRH<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 52D0 U1BDTP3 15:0 — — — — — — — — BDTPTRU<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 52E0 U1CNFG1 15:0 — — — — — — — — UTEYE UOEMON USBFRZ USBSIDL — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 5300 U1EP0 15:0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 5310 U1EP1 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 5320 U1EP2 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 P 31:16 — — — — — — — — — — — — — — — — 0000 5330 U1EP3 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 I C 31:16 — — — — — — — — — — — — — — — — 0000 5340 U1EP4 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 3 31:16 — — — — — — — — — — — — — — — — 0000 2 5350 U1EP5 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 M 31:16 — — — — — — — — — — — — — — — — 0000 5360 U1EP6 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 3 5370 U1EP7 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 X D Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S6 Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV X 1 Registers” for more information. 1 4 2: This register does not have associated CLR, SET, and INV registers. / 3 4 H 3: All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported. -p 4: The reset value for this bit is undefined. X a g e 8 X 3

D TABLE 4-43: USB REGISTERS MAP(1) (CONTINUED) P S 61 ss Bits I 143H-page 8 Virtual Addre(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets C32M 4 31:16 — — — — — — — — — — — — — — — — 0000 5380 U1EP8 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 X 5390 U1EP9 31:16 — — — — — — — — — — — — — — — — 0000 3 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 53A0 U1EP10 X 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 / 53B0 U1EP11 4 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 53C0 U1EP12 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 53D0 U1EP13 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 53E0 U1EP14 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 53F0 U1EP15 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section12.1.1 “CLR, SET and INV Registers” for more information. 2: This register does not have associated CLR, SET, and INV registers. 3: All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported. 4: The reset value for this bit is undefined. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX3XX/4XX 5.0 FLASH PROGRAM MEMORY RTSP is performed by software executing from either Flash or RAM memory. EJTAG is performed using the Note1: This data sheet summarizes the features EJTAG port of the device and a EJTAG capable of the PIC32MX3XX/4XX family of programmer. ICSP is performed using a serial data devices. It is not intended to be a compre- connection to the device and allows much faster pro- hensive reference source. To comple- gramming times than RTSP. RTSP techniques are ment the information in this data sheet, described in this chapter. The ICSP and EJTAG refer to Section 5. “Flash Program methods are described in the “PIC32MX Flash Memory” (DS61121) of the “PIC32 Programming Specification” (DS61145), which can be Family Reference Manual”, which is downloaded from the Microchip web site. available from the Microchip web site Note: Flash LVD Delay (LVDstartup) must be (www.microchip.com/PIC32). taken into account between setting up and 2: Some registers and associated bits executing any Flash command operation. described in this section may not be See Example5-1 for a code example to available on all devices. Refer to set up and execute a Flash command Section4.0 “Memory Organization” in operation. this data sheet for device-specific register and bit information. PIC32MX3XX/4XX devices contain an internal program Flash memory for executing user code. There are three methods by which the user can program this memory: • Run-Time Self Programming (RTSP) • In-Circuit Serial Programming™ (ICSP™) • EJTAG Programming EXAMPLE 5-1: NVMCON = 0x4004; // Enable and configure for erase operation Wait(delay); // Delay for 6 µs for LVDstartup NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; NVMCONSET = 0x8000; // Initiate operation while(NVMCONbits.WR==1); // Wait for current operation to complete © 2011 Microchip Technology Inc. DS61143H-page 85

PIC32MX3XX/4XX NOTES: DS61143H-page 86 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 6.0 RESETS The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The Note1: This data sheet summarizes the features following is a list of device Reset sources: of the PIC32MX3XX/4XX family of • POR: Power-on Reset devices. It is not intended to be a • MCLR: Master Clear Reset Pin comprehensive reference source. To • SWR: Software Reset complement the information in this data sheet, refer to Section 7. “Resets” • WDTR: Watchdog Timer Reset (DS61118) of the “PIC32 Family • BOR: Brown-out Reset Reference Manual”, which is available • CMR: Configuration Mismatch Reset from the Microchip web site A simplified block diagram of the Reset module is (www.microchip.com/PIC32). illustrated in Figure6-1. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM MCLR MCLR Glitch Filter Sleep or Idle WDTR WDT Voltage Time-out Regulator Enabled POR Power-up Timer SYSRST VDD VDD Rise Detect Brown-out BOR Reset Configuration Mismatch Reset CMR SWR Software Reset © 2011 Microchip Technology Inc. DS61143H-page 87

PIC32MX3XX/4XX NOTES: DS61143H-page 88 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 7.0 INTERRUPT CONTROLLER PIC32MX3XX/4XX devices generate interrupt requests in response to interrupt events from peripheral mod- Note1: This data sheet summarizes the features ules. The Interrupt Control module exists externally to of the PIC32MX3XX/4XX family of the CPU logic and prioritizes the interrupt events before devices. It is not intended to be a presenting them to the CPU. comprehensive reference source. To The PIC32MX3XX/4XX interrupts module includes the complement the information in this data following features: sheet, refer to Section 8. “Interrupt • Up to 96 interrupt sources Controller” (DS61108) of the “PIC32 Family Reference Manual”, which is • Up to 64 interrupt vectors available from the Microchip web site • Single and Multi-Vector mode operations (www.microchip.com/PIC32). • Five external interrupts with edge polarity control 2: Some registers and associated bits • Interrupt proximity timer described in this section may not be • Module Freeze in Debug mode available on all devices. Refer to • Seven user-selectable priority levels for each Section4.0 “Memory Organization” in vector this data sheet for device-specific register • Four user-selectable subpriority levels within each and bit information. priority • Dedicated shadow set for highest priority level • Software can generate any interrupt • User-configurable interrupt vector table location • User-configurable interrupt vector spacing FIGURE 7-1: INTERRUPT CONTROLLER MODULE s Vector Number st e u q e R upt Interrupt Controller CPU Core err Priority Level nt I Shadow Set Number Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and bits) are associated with the CPU. Details about them are available in Section3.0 “CPU”. To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this section, and all other sections of this manual, are signified by uppercase letters only. The CPU register names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register. © 2011 Microchip Technology Inc. DS61143H-page 89

PIC32MX3XX/4XX T ABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION Vector Interrupt Source(1) IRQ Interrupt Bit Location Number Highest Natural Order Priority Flag Enable Priority Subpriority CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> T1 – Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> IC1 – Input Capture 1 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> OC1 – Output Compare 1 6 6 IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16> INT1 – External Interrupt 1 7 7 IFS0<7> IEC0<7> IPC1<28:26> IPC1<25:24> T2 – Timer2 8 8 IFS0<8> IEC0<8> IPC2<4:2> IPC2<1:0> IC2 – Input Capture 2 9 9 IFS0<9> IEC0<9> IPC2<12:10> IPC2<9:8> OC2 – Output Compare 2 10 10 IFS0<10> IEC0<10> IPC2<20:18> IPC2<17:16> INT2 – External Interrupt 2 11 11 IFS0<11> IEC0<11> IPC2<28:26> IPC2<25:24> T3 – Timer3 12 12 IFS0<12> IEC0<12> IPC3<4:2> IPC3<1:0> IC3 – Input Capture 3 13 13 IFS0<13> IEC0<13> IPC3<12:10> IPC3<9:8> OC3 – Output Compare 3 14 14 IFS0<14> IEC0<14> IPC3<20:18> IPC3<17:16> INT3 – External Interrupt 3 15 15 IFS0<15> IEC0<15> IPC3<28:26> IPC3<25:24> T4 – Timer4 16 16 IFS0<16> IEC0<16> IPC4<4:2> IPC4<1:0> IC4 – Input Capture 4 17 17 IFS0<17> IEC0<17> IPC4<12:10> IPC4<9:8> OC4 – Output Compare 4 18 18 IFS0<18> IEC0<18> IPC4<20:18> IPC4<17:16> INT4 – External Interrupt 4 19 19 IFS0<19> IEC0<19> IPC4<28:26> IPC4<25:24> T5 – Timer5 20 20 IFS0<20> IEC0<20> IPC5<4:2> IPC5<1:0> IC5 – Input Capture 5 21 21 IFS0<21> IEC0<21> IPC5<12:10> IPC5<9:8> OC5 – Output Compare 5 22 22 IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16> SPI1E – SPI1 Fault 23 23 IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24> SPI1TX – SPI1 Transfer Done 24 23 IFS0<24> IEC0<24> IPC5<28:26> IPC5<25:24> SPI1RX – SPI1 Receive Done 25 23 IFS0<25> IEC0<25> IPC5<28:26> IPC5<25:24> U1E – UART1 Error 26 24 IFS0<26> IEC0<26> IPC6<4:2> IPC6<1:0> U1RX – UART1 Receiver 27 24 IFS0<27> IEC0<27> IPC6<4:2> IPC6<1:0> U1TX – UART1 Transmitter 28 24 IFS0<28> IEC0<28> IPC6<4:2> IPC6<1:0> I2C1B – I2C1 Bus Collision Event 29 25 IFS0<29> IEC0<29> IPC6<12:10> IPC6<9:8> I2C1S – I2C1 Slave Event 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> I2C1M – I2C1 Master Event 31 25 IFS0<31> IEC0<31> IPC6<12:10> IPC6<9:8> CN – Input Change Interrupt 32 26 IFS1<0> IEC1<0> IPC6<20:18> IPC6<17:16> AD1 – ADC1 Convert Done 33 27 IFS1<1> IEC1<1> IPC6<28:26> IPC6<25:24> PMP – Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0> CMP1 – Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8> CMP2 – Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX General Purpose – Features” and TABLE 2: “PIC32MX USB – Features” for available peripherals. DS61143H-page 90 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED) Vector Interrupt Source(1) IRQ Interrupt Bit Location Number Highest Natural Order Priority Flag Enable Priority Subpriority SPI2E – SPI2 Fault 37 31 IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24> SPI2TX – SPI2 Transfer Done 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> SPI2RX – SPI2 Receive Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24> U2E – UART2 Error 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0> U2RX – UART2 Receiver 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> U2TX – UART2 Transmitter 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0> I2C2B – I2C2 Bus Collision Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8> I2C2S – I2C2 Slave Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> I2C2M – I2C2 Master Event 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8> FSCM – Fail-Safe Clock Monitor 46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16> RTCC – Real-Time Clock and 47 35 IFS1<15> IEC1<15> IPC8<28:26> IPC8<25:24> Calendar DMA0 – DMA Channel 0 48 36 IFS1<16> IEC1<16> IPC9<4:2> IPC9<1:0> DMA1 – DMA Channel 1 49 37 IFS1<17> IEC1<17> IPC9<12:10> IPC9<9:8> DMA2 – DMA Channel 2 50 38 IFS1<18> IEC1<18> IPC9<20:18> IPC9<17:16> DMA3 – DMA Channel 3 51 39 IFS1<19> IEC1<19> IPC9<28:26> IPC9<25:24> FCE – Flash Control Event 56 44 IFS1<24> IEC1<24> IPC11<4:2> IPC11<1:0> USB 57 45 IFS1<25> IEC1<25> IPC11<12:10> IPC11<9:8> Lowest Natural Order Priority Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX General Purpose – Features” and TABLE 2: “PIC32MX USB – Features” for available peripherals. © 2011 Microchip Technology Inc. DS61143H-page 91

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PIC32MX3XX/4XX 8.0 OSCILLATOR The PIC32MX oscillator system has the following CONFIGURATION modules and features: • A total of four external and internal oscillator Note1: This data sheet summarizes the features options as clock sources of the PIC32MX3XX/4XX family of • On-chip PLL (phase-locked loop) with user- devices. It is not intended to be a selectable input divider, multiplier and output comprehensive reference source. To divider to boost operating frequency on select complement the information in this data internal and external oscillator sources sheet, refer to the “PIC32 Family • On-chip user-selectable divisor postscaler on Reference Manual” Section 6. select oscillator sources “Oscillator Configuration” (DS61112), • Software-controllable switching between various which is available from the Microchip web site (www.microchip.com/PIC32). clock sources • A Fail-Safe Clock Monitor (FSCM) that detects 2: Some registers and associated bits clock failure and permits safe application recovery described in this section may not be or shut down available on all devices. Refer to Section4.0 “Memory Organization” in • Dedicated on-chip PLL for USB peripheral this data sheet for device-specific register and bit information. FIGURE 8-1: PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM USB PLL UFIN USB Clock (48 MHz) div x PLL x24 div 2 UFRCEN UFIN = 4 MHz UPLLEN Primary Oscillator (POSC) UPLLIDIV<2:0> C1(3) OSC1 XT, HS, EC RF(2) TLoo gInicternal 4 MHz F≤INFIN ≤5 MHz EXCTPPLLLL, ,F HRSCPPLLLL, Postscaler Peripherals XTAL div x PLL div y div x PBCLK Enable RS(1) PLL Input Divider PLL Output Divider C2(3) OSC2(4) FPLLIDIV<2:0> PLLODIV<2:0> PBDIV<1:0> FRC PLL Multiplier Oscillator COSC<2:0> PLLMULT<2:0> FRC 8 MHz typical div 16 FRC/16 TUN<5:0> CPU and Select Peripherals FRCDIV Postscaler SYSCLK FRCDIV<2:0> LPRC LPRC Oscillator 31.25 kHz typical Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSC SOSCEN and FSOSCEN Clock Control Logic FSCM INT Fail-Safe SOSCI Clock FSCM Event Monitor Notes: 1. A series resistor, RS, may be required for AT strip-cut crystals. 2. The internal feedback resistor, RF, is typically in the range of 2 to 10MΩ. NOSC<2:0> 3. Refer to the “PIC32 Family Reference Manual” Section 6. “Oscillator COSC<2:0> Configuration” (DS61112) for help determining the best oscillator FSCMEN<1:0> OSWEN components. WDT, PWRT 4. PBCLK out is available on the OSC2 pin in certain clock modes. Timer1, RTCC © 2011 Microchip Technology Inc. DS61143H-page 93

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PIC32MX3XX/4XX 9.0 PREFETCH CACHE Prefetch cache increases performance for applications executing out of the cacheable program Flash memory Note1: This data sheet summarizes the features regions by implementing instruction caching, constant of the PIC32MX3XX/4XX family of data caching and instruction prefetching. devices. It is not intended to be a comprehensive reference source. To 9.1 Features complement the information in this data sheet, refer to Section 4. “Prefetch • 16 Fully Associative Lockable Cache Lines Cache” (DS61119) of the “PIC32 Family • 16-byte Cache Lines Reference Manual”, which is available • Up to four Cache Lines Allocated to Data from the Microchip web site • Two Cache Lines with Address Mask to hold (www.microchip.com/PIC32). repeated instructions 2: Some registers and associated bits • Pseudo LRU replacement policy described in this section may not be • All Cache Lines are software writable available on all devices. Refer to • 16-byte parallel memory fetch Section4.0 “Memory Organization” in this data sheet for device-specific register • Predictive Instruction Prefetch and bit information. FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM FSM CTRL Tag Logic Cache Line U P CTRL C X/ U M P B C Bus Control X/ M Cache Control B Prefetch Control Cache Hit LRU Line RDATA Address Miss LRU Encode Hit Logic Prefetch Prefetch CTRL RDATA PFM © 2011 Microchip Technology Inc. DS61143H-page 95

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PIC32MX3XX/4XX 10.0 DIRECT MEMORY ACCESS • Automatic Word-Size Detection: (DMA) CONTROLLER - Transfer Granularity, down to byte level - Bytes need not be word-aligned at source Note1: This data sheet summarizes the features and destination of the PIC32MX3XX/4XX family of • Fixed Priority Channel Arbitration devices. It is not intended to be a • Flexible DMA Channel Operating Modes: comprehensive reference source. To - Manual (software) or automatic (interrupt) complement the information in this data DMA requests sheet, refer to Section 31. “Direct - One-Shot or Auto-Repeat Block Transfer Memory Access (DMA) Controller” modes (DS61117) of the “PIC32 Family - Channel-to-channel chaining Reference Manual”, which is available • Flexible DMA Requests: from the Microchip web site (www.microchip.com/PIC32). - A DMA request can be selected from any of the peripheral interrupt sources 2: Some registers and associated bits - Each channel can select any (appropriate) described in this section may not be observable interrupt as its DMA request available on all devices. Refer to source Section4.0 “Memory Organization” in - A DMA transfer abort can be selected from this data sheet for device-specific register any of the peripheral interrupt sources and bit information. - Pattern (data) match transfer termination The PIC32MX Direct Memory Access (DMA) controller • Multiple DMA Channel Status Interrupts: is a bus master module useful for data transfers - DMA channel block transfer complete between different devices without CPU intervention. - Source empty or half empty The source and destination of a DMA transfer can be - Destination full or half-full any of the memory mapped modules existent in the - DMA transfer aborted due to an external PIC32MX (such as Peripheral Bus (PBUS) devices: event SPI, UART, PMP, and so on) or memory itself. - Invalid DMA address generated Following are some of the key features of the DMA • DMA Debug Support Features: controller module: - Most recent address accessed by a DMA • Four Identical Channels, each featuring: channel - Auto-Increment Source and Destination - Most recent DMA channel to transfer data Address Registers • CRC Generation Module: - Source and Destination Pointers - CRC module can be assigned to any of the - Memory to Memory and Memory to available channels Peripheral Transfers - CRC module is highly configurable FIGURE 10-1: DMA BLOCK DIAGRAM INT Controller System IRQ Peripheral Bus ADdedcoredsesr CChaonnntreoll 0 I0SEL CChaonnntreoll 1 I1 Y IntBerufasce Device Bus + Bus Arbitration I2 G(loDbMaAl CCoOnNtr)ol CChaonnntreoll n InS E L Channel Priority Arbitration © 2011 Microchip Technology Inc. DS61143H-page 97

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PIC32MX3XX/4XX 11.0 USB ON-THE-GO (OTG) The PIC32MX USB module includes the following features: Note1: This data sheet summarizes the features • USB Full-Speed Support for Host and Device of the PIC32MX3XX/4XX family of • Low-Speed Host Support devices. It is not intended to be a compre- hensive reference source. To • USB OTG Support complement the information in this data • Integrated Signaling Resistors sheet, refer to Section 27. “USB On- • Integrated Analog Comparators for VBUS The-Go (OTG)” (DS61126) of the “PIC32 Monitoring Family Reference Manual”, which is • Integrated USB Transceiver available from the Microchip web site • Transaction Handshaking Performed by (www.microchip.com/PIC32). Hardware 2: Some registers and associated bits • Endpoint Buffering Anywhere in System RAM described in this section may not be • Integrated DMA to Access System RAM and available on all devices. Refer to Flash Section4.0 “Memory Organization” in this data sheet for device-specific register Note: The implementation and use of the USB and bit information. specifications, as well as other third-party specifications or technologies, may The Universal Serial Bus (USB) module contains ana- require licensing; including, but not limited log and digital components to provide a USB 2.0 full- to, USB Implementers Forum, Inc. (also speed and low-speed embedded host, full-speed referred to as USB-IF). The user is fully device, or OTG implementation with a minimum of responsible for investigating and external components. This module in Host mode is satisfying any applicable licensing intended for use as an embedded host and therefore obligations. does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA control- ler, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32MX USB OTG module is presented in Figure11-1. The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communi- cation. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The inte- grated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. © 2011 Microchip Technology Inc. DS61143H-page 99

PIC32MX3XX/4XX FIGURE 11-1: PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM USBEN FRC USB Suspend Oscillator 8MHzTypical CPU Clock Not POSC Sleep TUN<5:0>(4) Primary Oscillator (POSC) UFIN(5) Divx PLL Div2 UFRCEN(3) OSC1 UPLLIDIV(6) UPLLEN(6) USBSuspend To Clock Generator for Core and Peripherals OSC2 Sleep or Idle (PBout)(1) USB Module USB SRPCharge Voltage VBUS Comparators SRPDischarge 48 MHz USB Clock(7) FullSpeedPull-up D+(2) Registers and Control HostPull-down Interface SIE Transceiver LowSpeedPull-up D-(2) DMA System RAM HostPull-down ID Pull-up ID(8) VBUSON(8) VUSB Transceiver Power 3.3V Note 1: PB clock is only available on this pin for select EC modes. 2: Pins can be used as digital inputs when USB is not enabled. 3: This bit field is contained in the OSCCON register. 4: This bit field is contained in the OSCTRM register. 5: USB PLL UFIN requirements: 4 MHz. 6: This bit field is contained in the DEVCFG2 register. 7: A 48 MHz clock is required for proper USB operation. 8: Pins can be used as GPIO when the USB module is disabled. DS61143H-page 100 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 12.0 I/O PORTS General purpose I/O pins are the simplest of peripher- als. They allow the PIC® MCU to monitor and control Note1: This data sheet summarizes the features other devices. To add flexibility and functionality, some of the PIC32MX3XX/4XX family of pins are multiplexed with alternate function(s). These devices. It is not intended to be a functions depend on which peripheral features are on comprehensive reference source. To the device. In general, when a peripheral is functioning, complement the information in this data that pin may not be used as a general purpose I/O pin. sheet, refer to Section 12. “I/O Ports” Following are some of the key features of this module: (DS61120) of the “PIC32 Family • Individual Output Pin Open-drain Enable/Disable Reference Manual”, which is available from the Microchip web site • Individual Input Pin Weak Pull-up Enable/Disable (www.microchip.com/PIC32). • Monitor Selective Inputs and Generate Interrupt when Change in Pin State is Detected 2: Some registers and associated bits • Operation during CPU Sleep and Idle modes described in this section may not be available on all devices. Refer to • Fast Bit Manipulation using CLR, SET and INV Section4.0 “Memory Organization” in Registers this data sheet for device-specific register Figure12-1 illustrates a block diagram of a typical and bit information. multiplexed I/O port. FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus D Q SYSCLK CK ODC EN Q WR ODC 1 I/O Cell RD TRIS 0 0 1 D Q CK TRIS 1 EN Q 0 WR TRIS Output Multiplexers D Q CK LAT I/O Pin EN Q WR LAT WR PORT RD LAT 1 RD PORT Q D Q D 0 Sleep Q CK Q CK SYSCLK Synchronization Peripheral Input R Peripheral Input Buffer Legend: R = Peripheral input buffer types may vary. Refer to Table1-1 for peripheral details. Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. © 2011 Microchip Technology Inc. DS61143H-page 101

PIC32MX3XX/4XX 12.1 Parallel I/O (PIO) Ports The maximum input voltage allowed on the input pins is the same as the maximum VIH specification. Refer to All port pins have three registers (TRIS, LAT and Section29.0 “Electrical Characteristics” for VIH PORT) that are directly associated with their operation. specification details. TRIS is a data direction or tri-state control register that Note: Analog levels on any pin that is defined as determines whether a digital pin is an input or an out- a digital input (including the ANx pins) put. Setting a TRISx register bit = 1 configures the cor- may cause the input buffer to consume responding I/O pin as an input; setting a TRISx register current that exceeds the device specifica- bit = 0 configures the corresponding I/O pin as an out- tions. put. All port I/O pins are defined as inputs after a device Reset. Certain I/O pins are shared with analog 12.1.3 ANALOG INPUTS peripherals and default to analog inputs after a device Reset. Certain pins can be configured as analog inputs used by the ADC and Comparator modules. Setting the cor- PORT is a register used to read the current state of the responding bits in the AD1PCFG register = 0 enables signal applied to the port I/O pins. Writing to a PORTx the pin as an analog input pin and must have the corre- register performs a write to the port’s latch, LATx sponding TRIS bit set = 1 (input). If the TRIS bit is register, latching the data to the port’s I/O pins. cleared = 0 (output), the digital output level (VOH or LAT is a register used to write data to the port I/O pins. VOL) will be converted. Any time a port I/O pin is config- The LATx latch register holds the data written to either ured as analog, its digital input is disabled and the cor- the LATx or PORTx registers. Reading the LATx latch responding PORTx register bit will read ‘0’. The register reads the last value written to the AD1PCFG Register has a default value of 0x0000; corresponding port or latch register. therefore, all pins that share ANx functions are analog Not all port I/O pins are implemented on some devices, (not digital) by default. therefore, the corresponding PORTx, LATx and TRISx 12.1.4 DIGITAL OUTPUTS register bits will read as zeros. Pins are configured as digital outputs by setting the cor- 12.1.1 CLR, SET AND INV REGISTERS responding TRIS register bits = 0. When configured as Every I/O module register has a corresponding CLR digital outputs, these pins are CMOS drivers or can be (clear), SET (set) and INV (invert) register designed to configured as open drain outputs by setting the corre- provide fast atomic bit manipulations. As the name of sponding bits in the ODCx Open-Drain Configuration the register implies, a value written to a SET, CLR or register. INV register effectively performs the implied operation, The open-drain feature allows the generation of but only on the corresponding base register and only outputs higher than VDD (e.g., 5V) on any desired 5V bits specified as ‘1’ are modified. Bits specified as ‘0’ tolerant pins by using external pull-up resistors. The are not modified. maximum open-drain voltage allowed is the same as Reading SET, CLR and INV registers returns undefined the maximum VIH specification. values. To see the affects of a write operation to a SET, See the “Pin Diagrams” section for the available pins CLR or INV register, the base register must be read. and their functionality. 12.1.5 ANALOG OUTPUTS Note: Using a PORTxINV register to toggle a bit is recommended because the operation is Certain pins can be configured as analog outputs, such performed in hardware atomically, using as the CVREF output voltage used by the comparator fewer instructions as compared to the tra- module. Configuring the Comparator Reference mod- ditional read-modify-write method shown ule to provide this output will present the analog output below: voltage on the pin, independent of the TRIS register PORTC ^= 0x0001; setting for the corresponding pin. 12.1.2 DIGITAL INPUTS 12.1.6 INPUT CHANGE NOTIFICATION Pins are configured as digital inputs by setting the cor- The input change notification function of the I/O ports responding TRIS register bits = 1. When configured as (CNx) allows devices to generate interrupt requests in inputs, they are either TTL buffers or Schmitt Triggers. response to change of state on selected pin. Several digital pins share functionality with analog Each CNx pin also has a weak pull-up, which acts as a inputs and default to the analog inputs at POR. Setting current source connected to the pin. The pull-ups are the corresponding bit in the AD1PCFG register = 1 enabled by setting corresponding bit in CNPUE register. enables the pin as a digital pin. DS61143H-page 102 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 13.0 TIMER1 This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can oper- Note1: This data sheet summarizes the features ate as a free-running interval timer for various timing of the PIC32MX3XX/4XX family of applications and counting external events. This timer devices. It is not intended to be a compre- can also be used with the Secondary Oscillator (SOSC) hensive reference source. To comple- for real-time clock applications. The following modes ment the information in this data sheet, are supported: refer to Section 14. “Timers” (DS61105) • Synchronous Internal Timer of the “PIC32 Family Reference Manual”, • Synchronous Internal Gated Timer which is available from the Microchip web site (www.microchip.com/PIC32). • Synchronous External Timer • Asynchronous External Timer 2: Some registers and associated bits described in this section may not be 13.1 Additional Supported Features available on all devices. Refer to Section4.0 “Memory Organization” in • Selectable clock prescaler this data sheet for device-specific register • Timer operation during CPU Idle and Sleep mode and bit information. • Fast bit manipulation using CLR, SET and INV registers • Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC) FIGURE 13-1: TIMER1 BLOCK DIAGRAM(1) PR1 Equal 16-bit Comparator TSYNC (T1CON<2>) 1 Sync TMR1 Reset 0 0 T1IF Event Flag 1 Q D TGATE (T1CON<7>) Q TCS (T1CON<1>) TGATE (T1CON<7>) ON (T1CON<15>) SOSCO/T1CK x 1 Gate Prescaler SOSCEN Sync 1 0 1, 8, 64, 256 SOSCI PBCLK 0 0 2 TCKPS<1:0> (T1CON<5:4>) Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1. © 2011 Microchip Technology Inc. DS61143H-page 103

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PIC32MX3XX/4XX 14.0 TIMER2/3 AND TIMER4/5 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. Note1: This data sheet summarizes the features The 32-bit timers can operate in three modes: of the PIC32MX3XX/4XX family of • Synchronous Internal 32-bit Timer devices. It is not intended to be a compre- • Synchronous Internal 32-bit Gated Timer hensive reference source. To comple- ment the information in this data sheet, • Synchronous External 32-bit Timer refer to Section 14. “Timers” (DS61105) Note: Throughout this chapter, references to of the “PIC32 Family Reference Manual”, registers TxCON, TMRx and PRx use ‘x’ which is available from the Microchip web to represent Timer2 through 5 in 16-bit site (www.microchip.com/PIC32). modes. In 32-bit modes, ‘x’ represents Timer2 or 4; ‘y’ represents Timer3 or 5. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to 14.1 Additional Supported Features Section4.0 “Memory Organization” in • Selectable clock prescaler this data sheet for device-specific register and bit information. • Timers operational during CPU Idle • Time base for input capture and output compare This family of PIC32MX devices features four modules (Timer2 and Timer3 only) synchronous 16-bit timers (default) that can operate as • ADC event trigger (Timer3 only) a free-running interval timer for various timing applica- tions and counting external events. The following • Fast bit manipulation using CLR, SET and INV modes are supported: registers • Synchronous Internal 16-bit Timer • Synchronous Internal 16-bit Gated Timer • Synchronous External 16-bit Timer FIGURE 14-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT) TMRx Sync ADC Event Trigger(1) Comparator x 16 Equal PRx Reset 0 TxIF Event Flag 1 Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) TGATE (TxCON<7>) ON (TxCON<15>) TxCK(2) x 1 Prescaler Gate 1, 2, 4, 8, 16, Sync 1 0 32, 64, 256 PBCLK 0 0 3 Note 1: ADC event trigger is available on Timer3 only. TCKPS (TxCON<6:4>) 2: TxCK pins not available on 64-pin devices. © 2011 Microchip Technology Inc. DS61143H-page 105

PIC32MX3XX/4XX FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy TMRx Sync MSHalfWord LSHalfWord ADC Event Trigger(3) 32-bit Comparator Equal PRy PRx TyIF Event 0 Flag 1 Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) TGATE (TxCON<7>) ON (TxCON<15>) TxCK(2) x 1 Prescaler Gate 1, 2, 4, 8, 16, Sync 1 0 32, 64, 256 PBCLK 0 0 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of ‘x’ in registers TxCON, TMRx, PRx and TxCK refers to either Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy and TyIF refers to either Timer3 or Timer5. 2: TxCK pins are not available on 64-pin devices. 3: ADC event trigger is available only on Timer2/3 pair. DS61143H-page 106 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 15.0 INPUT CAPTURE 2. Capture timer value on every edge (rising and falling) Note1: This data sheet summarizes the features 3. Capture timer value on every edge (rising and of the PIC32MX3XX/4XX family of falling), specified edge first. devices. It is not intended to be a 4. Prescaler Capture Event modes comprehensive reference source. To - Capture timer value on every 4th rising edge complement the information in this data of input at ICx pin sheet, refer to Section 15. “Input Capture” (DS61122) of the “PIC32 - Capture timer value on every 16th rising Family Reference Manual”, which is edge of input at ICx pin available from the Microchip web site Each input capture channel can select between one of (www.microchip.com/PIC32). two 16-bit timers (Timer2 or Timer3) for the time base, 2: Some registers and associated bits or two 16-bit timers (Timer2 and Timer3) together to described in this section may not be form a 32-bit timer. The selected timer can use either available on all devices. Refer to an internal or external clock. Section4.0 “Memory Organization” in Other operational features include: this data sheet for device-specific register • Device wake-up from capture pin during CPU and bit information. Sleep and Idle modes The Input Capture module is useful in applications • Interrupt on input capture event requiring frequency (period) and pulse measurement. • 4-word FIFO buffer for capture values The PIC32MX3XX/4XX devices support up to five input - Interrupt optionally generated after 1, 2, 3 or capture channels. 4 buffer locations are filled The Input Capture module captures the 16-bit or 32-bit • Input capture can also be used to provide value of the selected Time Base registers when an additional sources of external interrupts event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1. Simple Capture Event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM ICx Input Timer3 Timer2 ICTMR 0 1 C32 FIFO Control ICxBUF<31:16> ICxBUF<15:0> Prescaler Edge Detect 1, 4, 16 ICM<2:0> ICM<2:0> FEDGE ICBNE ICOV Interrupt ICxCON Event ICI<1:0> Generation Data Space Interface Interrupt Peripheral Data Bus © 2011 Microchip Technology Inc. DS61143H-page 107

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PIC32MX3XX/4XX 16.0 OUTPUT COMPARE The Output Compare module (OCMP) is used to gen- erate a single pulse or a train of pulses in response to Note1: This data sheet summarizes the features selected time base events. For all modes of operation, of the PIC32MX3XX/4XX family of the OCMP module compares the values stored in the devices. It is not intended to be a OCxR and/or the OCxRS registers to the value in the comprehensive reference source. To selected timer. When a match occurs, the OCMP mod- complement the information in this data ule generates an event based on the selected mode of sheet, refer to Section 16. “Output operation. Compare” (DS61111) of the “PIC32 The following are some of the key features: Family Reference Manual”, which is available from the Microchip web site • Multiple output compare modules in a device (www.microchip.com/PIC32). • Programmable interrupt generation on compare event 2: Some registers and associated bits described in this section may not be • Single and Dual Compare modes available on all devices. Refer to • Single and continuous output pulse generation Section4.0 “Memory Organization” in • Pulse-Width Modulation (PWM) mode this data sheet for device-specific register • Hardware-based PWM Fault detection and and bit information. automatic output disable • Programmable selection of 16-bit or 32-bit time bases. • Can operate from either of two available 16-bit time bases or a single 32-bit time base FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Output S Q OCx(1) Logic R 3 Output Enable OCM<2:0> Output Logic Mode Select Enable Comparator OCFA or OCFB (see Note 2) 0 1 OCTSEL 0 1 16 16 TMR register inputs Period match signals from time bases from time bases (see Note 3) (see Note 3) Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. © 2011 Microchip Technology Inc. DS61143H-page 109

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PIC32MX3XX/4XX 17.0 SERIAL PERIPHERAL The SPI module is a synchronous serial interface use- INTERFACE (SPI) ful for communicating with external peripherals and other microcontroller devices. These peripheral Note1: This data sheet summarizes the features devices may be Serial EEPROMs, shift registers, dis- of the PIC32MX3XX/4XX family of play drivers, Analog-to-Digital Converters, etc. The devices. It is not intended to be a compre- PIC32MX SPI module is compatible with Motorola® SPI hensive reference source. To comple- and SIOP interfaces. ment the information in this data sheet, Following are some of the key features of this module: refer to Section 23. “Serial Peripheral • Master and Slave Modes Support Interface (SPI)” (DS61106) of the • Four Different Clock Formats “PIC32 Family Reference Manual”, which is available from the Microchip web site • Framed SPI Protocol Support (www.microchip.com/PIC32). • User Configurable 8-bit, 16-bit and 32-bit Data Width 2: Some registers and associated bits described in this section may not be • Separate SPI Data Registers for Receive and available on all devices. Refer to Transmit Section4.0 “Memory Organization” in • Programmable Interrupt Event on every 8-bit, this data sheet for device-specific register 16-bit and 32-bit Data Transfer and bit information. • Operation during CPU Sleep and Idle Mode • Fast Bit Manipulation using CLR, SET and INV Registers FIGURE 17-1: SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read Write Registers share address SPIxBUF SPIxRXB SPIxTXB Transmit Receive SPIxSR SDIx bit 0 SDOx Shift Control Slave Select Clock Edge and Frame Control Select SSx/FSYNC Sync Control Baud Rate PBCLK Generator SCKx Enable Master Clock Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register. © 2011 Microchip Technology Inc. DS61143H-page 111

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PIC32MX3XX/4XX 18.0 INTER-INTEGRATED The PIC32MX3XX/4XX devices have up to two I2C CIRCUIT™ (I2C™) interface modules, denoted as I2C1 and I2C2. Each I2C module has a 2-pin interface: the SCLx pin is clock Note1: This data sheet summarizes the features and the SDAx pin is data. of the PIC32MX3XX/4XX family of Each I2C module, ‘I2Cx’ (x = 1 or 2), offers the following devices. It is not intended to be a compre- key features: hensive reference source. To comple- • I2C Interface Supporting both Master and Slave ment the information in this data sheet, Operation. refer to Section 24. “Inter-Integrated Circuit (I2C™)” (DS61116) of the “PIC32 • I2C Slave Mode Supports 7 and 10-bit Address. Family Reference Manual”, which is • I2C Master Mode Supports 7 and 10-bit Address. available from the Microchip web site • I2C Port allows Bidirectional Transfers between (www.microchip.com/PIC32). Master and Slaves. 2: Some registers and associated bits • Serial Clock Synchronization for I2C Port can be described in this section may not be used as a Handshake Mechanism to Suspend available on all devices. Refer to and Resume Serial Transfer (SCLREL control). Section4.0 “Memory Organization” in • I2C Supports Multi-master Operation; Detects Bus this data sheet for device-specific register Collision and Arbitrates Accordingly. and bit information. • Provides Support for Address Bit Masking. The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure18-1 illustrates the I2C module block diagram. © 2011 Microchip Technology Inc. DS61143H-page 113

PIC32MX3XX/4XX FIGURE 18-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoelltiseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read ShiftClock Reload Control Write BRG Down Counter I2CxBRG Read PBCLK DS61143H-page 114 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 19.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are: RECEIVER TRANSMITTER • Full-duplex, 8-bit or 9-bit data transmission (UART) • Even, odd or no parity options (for 8-bit data) • One or two Stop bits Note 1: This data sheet summarizes the features • Hardware auto-baud feature of the PIC32MX3XX/4XX family of • Hardware flow control option devices. It is not intended to be a comprehensive reference source. To • Fully integrated Baud Rate Generator (BRG) with complement the information in this data 16-bit prescaler sheet, refer to Section 21. “Universal • Baud rates ranging from 76 bps to 20 Mbps at 80 Asynchronous Receiver Transmitter MHz (UART)” (DS61107) of the “PIC32 Family • 4-level-deep First-In-First-Out (FIFO) Transmit Reference Manual”, which is available Data Buffer from the Microchip web site • 4-level-deep FIFO Receive Data Buffer (www.microchip.com/PIC32). • Parity, framing and buffer overrun error detection 2: Some registers and associated bits • Support for interrupt only on address detect (9th described in this section may not be bit=1) available on all devices. Refer to • Separate transmit and receive interrupts Section4.0 “Memory Organization” in • Loopback mode for diagnostic support this data sheet for device-specific register and bit information. • LIN protocol support • IrDA encoder and decoder with 16x baud clock The UART module is one of the serial I/O modules output for external IrDA encoder/decoder support available in PIC32MX3XX/4XX family devices. The UART is a full-duplex, asynchronous communication Figure19-1 illustrates a simplified block diagram of the channel that communicates with peripheral devices UART. and personal computers through protocols such as RS- 232, RS-485, LIN 1.2 and IrDA®. The module also sup- ports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® BCLKx UxRTS Hardware Flow Control UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX © 2011 Microchip Technology Inc. DS61143H-page 115

PIC32MX3XX/4XX FIGURE 19-2: TRANSMISSION (8-BIT OR 9-BIT DATA) Write to UxTXREG Character 1 BCLK/16 (Shift Clock) UxTX Start bit bit 0 bit 1 bit 7/8 Stop bit Character 1 UxTXIF Cleared by User UxTXIF Character 1 to Transmit Shift Register TRMT bit FIGURE 19-3: TWO CONSECUTIVE TRANSMISSIONS Write to UxTXREG Character 1 Character 2 BCLK/16 (Shift Clock) UxTX Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 Character 1 Character 2 UxTXIF (UTXISEL0 = 0) UxTXIF Cleared by User in Software UxTXIF (UTXISEL0 = 1) Character 1 to Character 2 to Transmit Shift Register Transmit Shift Register TRMT bit DS61143H-page 116 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 19-4: UART RECEPTION UxRX Start Start bit bit 0 bit1 bit 7 Stop bit bit 0 bit 7 Stop bit bit UxRXIF (RXISEL = 0x) Character 1 Character 2 to UxRXREG to UxRXREG RIDLE bit Note: This timing diagram shows 2 characters received on the UxRX input. FIGURE 19-5: UART RECEPTION WITH RECEIVE OVERRUN Character 1 Characters 2, 3, 4, 5 Character 6 Start Start Start UxRX bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Character 1, 2, 3, 4 Character 5 Stored in Receive Held in UxRSR FIFO OERR Cleared by User OERR bit RIDLE bit Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character. © 2011 Microchip Technology Inc. DS61143H-page 117

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PIC32MX3XX/4XX 20.0 PARALLEL MASTER PORT Key features of the PMP module include: (PMP) • 8-bit,16-bit interface • Up to 16 programmable address lines Note1: This data sheet summarizes the features • Up to two Chip Select lines of the PIC32MX3XX/4XX family of • Programmable strobe options devices. It is not intended to be a compre- hensive reference source. To comple- - Individual read and write strobes, or ment the information in this data sheet, - Read/write strobe with enable strobe refer to Section 13. “Parallel Master • Address auto-increment/auto-decrement Port (PMP)” (DS61128) of the “PIC32 • Programmable address/data multiplexing Family Reference Manual”, which is • Programmable polarity on control signals available from the Microchip web site (www.microchip.com/PIC32). • Parallel Slave Port support - Legacy addressable 2: Some registers and associated bits described in this section may not be - Address support available on all devices. Refer to - 4-byte deep auto-incrementing buffer Section4.0 “Memory Organization” in • Programmable Wait states this data sheet for device-specific register • Operate during CPU Sleep and Idle modes and bit information. • Fast bit manipulation using CLR, SET and INV The PMP is a parallel 8-bit/16-bit input/output module registers specifically designed to communicate with a wide • Freeze option for in-circuit debugging variety of parallel devices, such as communications peripherals, LCDs, external memory devices and Note: On 64-pin devices, data pins PMD<15:8> microcontrollers. Because the interface to parallel are not available. peripherals varies significantly, the PMP module is highly configurable. FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus Control Lines PIC32MX3XX/4XX PMA<0> PMALL Parallel Master Port PMA<1> PMALH FLASH Up to 16-bit Address EEPROM PMA<13:2> SRAM PMA<14> PMCS1 PMA<15> PMCS2 PMRD PMRD/PMWR FIFO PMWR Microcontroller LCD buffer PMENB PMD<7:0> PMD<15:8>(1) 16/8-bit Data (with or without multiplexed addressing) Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes. © 2011 Microchip Technology Inc. DS61143H-page 119

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PIC32MX3XX/4XX 21.0 REAL-TIME CLOCK AND The following are some of the key features of this CALENDAR (RTCC) module: • Time: Hours, Minutes and Seconds Note1: This data sheet summarizes the features • 24-Hour Format (Military Time) of the PIC32MX3XX/4XX family of • Visibility of One-Half-Second Period devices. It is not intended to be a compre- • Provides Calendar: Weekday, Date, Month and hensive reference source. To comple- Year ment the information in this data sheet, refer to Section 29. “Real-Time Clock • Alarm Intervals are configurable for Half of a and Calendar (RTCC)” (DS61125) of the Second, One Second, 10 Seconds, One Minute, “PIC32 Family Reference Manual”, which 10 Minutes, One Hour, One Day, One Week, One is available from the Microchip web site Month and One Year (www.microchip.com/PIC32). • Alarm Repeat with Decrementing Counter 2: Some registers and associated bits • Alarm with Indefinite Repeat: Chime described in this section may not be • Year Range: 2000 to 2099 available on all devices. Refer to • Leap Year Correction Section4.0 “Memory Organization” in • BCD Format for Smaller Firmware Overhead this data sheet for device-specific register • Optimized for Long-Term Battery Operation and bit information. • Fractional Second Synchronization The PIC32MX RTCC module is intended for applica- • User Calibration of the Clock Crystal Frequency tions in which accurate time must be maintained for with Auto-Adjust extended periods of time with minimal or no CPU inter- • Calibration Range: ±0.66 Seconds Error per vention. Low-power optimization provides extended Month battery lifetime while keeping track of time. • Calibrates up to 260 ppm of Crystal Error • Requirements: External 32.768 kHz Clock Crystal • Alarm Pulse or Seconds Clock Output on RTCC pin FIGURE 21-1: RTCC BLOCK DIAGRAM 32.768 kHz Input from Secondary Oscillator (SOSC) RTCC Prescalers 0.5s YEAR, MTH, DAY RTCC Timer RTCVAL WKDAY Alarm HR, MIN, SEC Event Comparator MTH, DAY Compare Registers ALRMVAL WKDAY with Masks HR, MIN, SEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse Seconds Pulse RTCC Pin RTCOE © 2011 Microchip Technology Inc. DS61143H-page 121

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PIC32MX3XX/4XX 22.0 10-BIT ANALOG-TO-DIGITAL • Automatic Channel Scan mode CONVERTER (ADC) • Selectable conversion trigger source • 16-word conversion result buffer Note1: This data sheet summarizes the features • Selectable Buffer Fill modes of the PIC32MX3XX/4XX family of • Eight conversion result format options devices. It is not intended to be a compre- • Operation during CPU Sleep and Idle modes hensive reference source. Refer to Sec- tion 17. “10-bit Analog-to-Digital A block diagram of the 10-bit ADC is illustrated in Converter (ADC)” (DS61104) of the Figure22-1. The 10-bit ADC has 16 analog input pins, “PIC32 Family Reference Manual”, which designated AN0-AN15. In addition, there are two ana- is available from the Microchip web site log input pins for external voltage reference connec- (www.microchip.com/PIC32). tions. These voltage reference inputs may be shared with other analog input pins and may be common to 2: Some registers and associated bits other analog module references. described in this section may not be available on all devices. Refer to The analog inputs are connected through two multi- Section4.0 “Memory Organization” in plexers (MUXs) to one SHA. The analog input MUXs this data sheet for device-specific register can be switched between two sets of analog inputs and bit information. between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as The PIC32MX3XX/4XX 10-bit Analog-to-Digital the reference, using a reference input pin (see Converter (ADC) includes the following features: Figure22-1). • Successive Approximation Register (SAR) The Analog Input Scan mode sequentially converts conversion user-specified channels. A control register specifies • Up to 1000 kilo samples per second (ksps) which analog input channels will be included in the conversion speed scanning sequence. • Up to 16 analog input pins The 10-bit ADC is connected to a 16-word result buffer. • External voltage reference input pins Each 10-bit result is converted to one of eight, 32-bit • One unipolar, differential Sample-and-Hold output formats when it is read from the result buffer. Amplifier (SHA) FIGURE 22-1: ADC1 MODULE BLOCK DIAGRAM VREF+(1) AVDD VREF-(1) AVSS VCFG<2:0> AN0 ADC1BUF0 ADC1BUF1 AN15 ADC1BUF2 S/H CHANNEL VREFH VREFL SCAN + CH0SB<4:0> CH0SA<4:0> - SAR ADC CSCNA AN1 VREFL ADC1BUFE ADC1BUFF CH0NA CH0NB Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. © 2011 Microchip Technology Inc. DS61143H-page 123

PIC32MX3XX/4XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC ADC Internal RC Clock(1) 1 TAD ADCS<7:0> 0 8 ADC Conversion Clock Multiplier TPB 2,4,..., 512 Note 1: See the ADC electrical characteristics for the exact RC clock value. DS61143H-page 124 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 23.0 COMPARATOR The PIC32MX3XX/4XX Analog Comparator module contains one or more comparator(s) that can be Note1: This data sheet summarizes the features configured in a variety of ways. of the PIC32MX3XX/4XX family of Following are some of the key features of this module: devices. It is not intended to be a compre- hensive reference source. Refer to • Selectable inputs available include: Section 19. “Comparator” (DS61110) of - Analog inputs multiplexed with I/O pins the “PIC32 Family Reference Manual”, - On-chip internal absolute voltage reference which is available from the Microchip web (IVREF) site (www.microchip.com/PIC32). - Comparator voltage reference (CVREF) 2: Some registers and associated bits • Outputs can be inverted described in this section may not be • Selectable interrupt generation available on all devices. Refer to A block diagram of the comparator module is illustrated Section4.0 “Memory Organization” in in Figure23-1. this data sheet for device-specific register and bit information. FIGURE 23-1: COMPARATOR BLOCK DIAGRAM Comparator 1 CREF COUT (CM1CON) ON C1OUT (CMSTAT) CPOL C1IN+(1) CVREF(2) C1OUT CCH<1:0> C1 C1IN- COE C1IN+ C2IN+ IVREF(2) Comparator 2 CREF COUT (CM2CON) ON C2OUT (CMSTAT) CPOL C2IN+ CVREF(2) C2OUT CCH<1:0> C2 C2IN- COE C2IN+ C1IN+ IVREF(2) Note 1: On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not available as a comparator input. 2: Internally connected. © 2011 Microchip Technology Inc. DS61143H-page 125

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PIC32MX3XX/4XX 24.0 COMPARATOR VOLTAGE The CVREF is a 16-tap, resistor ladder network that pro- REFERENCE (CVREF) vides a selectable reference voltage. Although its pri- mary purpose is to provide a reference for the analog Note1: This data sheet summarizes the features comparators, it also may be used independently of of the PIC32MX3XX/4XX family of them. devices. It is not intended to be a compre- A block diagram of the module is illustrated in hensive reference source. Refer to Sec- Figure24-1. The resistor ladder is segmented to tion 20. “Comparator Voltage provide two ranges of voltage reference values and has Reference (CVREF)” (DS61109) of the a power-down function to conserve power when the “PIC32 Family Reference Manual”, which reference is not being used. The module’s supply refer- is available from the Microchip web site ence can be provided from either device VDD/VSS or an (www.microchip.com/PIC32). external voltage reference. The CVREF output is avail- able for the comparators and typically available for pin 2: Some registers and associated bits output. described in this section may not be available on all devices. Refer to The comparator voltage reference has the following Section4.0 “Memory Organization” in features: this data sheet for device-specific register • High and low range selection and bit information. • Sixteen output levels available for each range • Internally connected to comparators to conserve device pins • Output can be connected to a pin FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ AVDD CVRSS = 0 8R CVR3:CVR0 R CVREN R CVREF R R X U M 16 Steps o-1 CVREFOUT 6-t CVRCON<CVROE> 1 R R R CVRR 8R CVRSS = 1 VREF- AVSS CVRSS = 0 © 2011 Microchip Technology Inc. DS61143H-page 127

PIC32MX3XX/4XX NOTES: DS61143H-page 128 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 25.0 POWER-SAVING FEATURES • LPRC Idle Mode: the system clock is derived from the LPRC. Note1: This data sheet summarizes the features Peripherals continue to operate, but can option- of the PIC32MX3XX/4XX family of ally be individually disabled. This is the lowest devices. It is not intended to be a compre- power mode for the device with a clock running. hensive reference source. To comple- • Sleep Mode: the CPU, the system clock source, ment the information in this data sheet, and any peripherals that operate from the system refer to Section 10. “Power-Saving clock source, are halted. Features” (DS61130) of the “PIC32 Some peripherals can operate in Sleep using spe- Family Reference Manual”, which is cific clock sources. This is the lowest power mode available from the Microchip web site for the device. (www.microchip.com/PIC32). 2: Some registers and associated bits 25.3 Power-Saving Operation described in this section may not be available on all devices. Refer to The purpose of all power-saving is to reduce power Section4.0 “Memory Organization” in consumption by reducing the device clock frequency. this data sheet for device-specific register To achieve this, low-frequency clock sources can be and bit information. selected. In addition, the peripherals and CPU can be halted or disabled to further reduce power This section describes power-saving for the consumption. PIC32MX3XX/4XX. The PIC32MX devices offer a total of nine methods and modes that are organized into two 25.3.1 SLEEP MODE categories that allow the user to balance power con- sumption with device performance. In all of the meth- Sleep mode has the lowest power consumption of the ods and modes described in this section, power-saving device Power-Saving operating modes. The CPU and is controlled by software. most peripherals are halted. Select peripherals can continue to operate in Sleep mode and can be used to 25.1 Power-Saving with CPU Running wake the device from Sleep. See the individual periph- eral module sections for descriptions of behavior in When the CPU is running, power consumption can be Sleep mode. controlled by reducing the CPU clock frequency, lower- Sleep mode includes the following characteristics: ing the PBCLK, and by individually disabling modules. These methods are grouped into the following modes: • The CPU is halted. • The system clock source is typically shut down. • FRC Run mode: the CPU is clocked from the FRC See Section25.3.2 “Idle Mode” for specific clock source with or without postscalers. information. • LPRC Run mode: the CPU is clocked from the • There can be a wake-up delay based on the LPRC clock source. oscillator selection. • SOSC Run mode: the CPU is clocked from the • The Fail-Safe Clock Monitor (FSCM) does not SOSC clock source. operate during Sleep mode. • Peripheral Bus Scaling mode: peripherals are • The BOR circuit, if enabled, remains operative clocked at programmable fraction of the CPU during Sleep mode. clock (SYSCLK). • The WDT, if enabled, is not automatically cleared 25.2 CPU Halted Methods prior to entering Sleep mode. • Some peripherals can continue to operate in The device supports two power-saving modes, Sleep Sleep mode. These peripherals include I/O pins and Idle, both of which halt the clock to the CPU. These that detect a change in the input signal, WDT, modes operate with all clock sources, as listed below: ADC, UART and peripherals that use an external • POSC Idle Mode: the system clock is derived from clock input or the internal LPRC oscillator, e.g., the POSC. The system clock source continues to RTCC and Timer 1. operate. • I/O pins continue to sink or source current in the Peripherals continue to operate, but can same manner as they do when the device is not in optionally be individually disabled. Sleep. • FRC Idle Mode: the system clock is derived from • The USB module can override the disabling of the the FRC with or without postscalers. Peripherals POSC or FRC. Refer to Section11.0 “USB On- continue to operate, but can optionally be The-Go (OTG)” for specific details. individually disabled. • Some modules can be individually disabled by • SOSC Idle Mode: the system clock is derived from software prior to entering Sleep in order to further the SOSC. Peripherals continue to operate, but reduce consumption. can optionally be individually disabled. © 2011 Microchip Technology Inc. DS61143H-page 129

PIC32MX3XX/4XX The processor will exit, or ‘wake-up’, from Sleep on one The processor will wake or exit from Idle mode on the of the following events: following events: • On any interrupt from an enabled source that is • On any interrupt event for which the interrupt operating in Sleep. The interrupt priority must be source is enabled. The priority of the interrupt greater than the current CPU priority. event must be greater than the current priority of • On any form of device Reset. CPU. If the priority of the interrupt event is lower than or equal to current priority of CPU, the CPU • On a WDT time-out. See Section26.2 “Watchdog will remain halted and the device will remain in Timer (WDT)”. Idle mode. If the interrupt priority is lower than or equal to current • On any source of device Reset. priority, the CPU will remain halted, but the PBCLK will • On a WDT time-out interrupt. See Section26.2 start running and the device will enter into Idle mode. “Watchdog Timer (WDT)”. Note: There is no FRZ mode for this module. 25.3.3 PERIPHERAL BUS SCALING 25.3.2 IDLE MODE METHOD In the Idle mode, the CPU is halted but the System Most of the peripherals on the device are clocked using clock (SYSCLK) source is still enabled. This allows the PBCLK. The peripheral bus can be scaled relative peripherals to continue operation when the CPU is to the SYSCLK to minimize the dynamic power con- halted. Peripherals can be individually configured to sumed by the peripherals. The PBCLK divisor is con- halt when entering Idle by setting their respective SIDL trolled by PBDIV<1:0> (OSCCON<20:19>), allowing bit. Latency when exiting Idle mode is very low due to SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All the CPU oscillator source remaining active. peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, Interrupt Con- troller, DMA, Bus Matrix and Prefetch Cache are Note: Changing the PBCLK divider ratio clocked directly from SYSCLK, as a result, they are not requires recalculation of peripheral timing. affected by PBCLK divisor changes For example, assume the UART is config- ured for 9600 baud with a PB clock ratio of Changing the PBCLK divisor affects: 1:1 and a POSC of 8 MHz. When the PB • The CPU to peripheral access latency. The CPU clock divisor of 1:2 is used, the input fre- has to wait for next PBCLK edge for a read to quency to the baud clock is cut in half; complete. In 1:8 mode this results in a latency of therefore, the baud rate is reduced to 1/2 one to seven SYSCLKs. its former value. Due to numeric truncation • The power consumption of the peripherals. Power in calculations (such as the baud rate divi- consumption is directly proportional to the fre- sor), the actual baud rate may be a tiny quency at which the peripherals are clocked. The percentage different than expected. For greater the divisor, the lower the power consumed this reason, any timing calculation by the peripherals. required for a peripheral should be per- formed with the new PB clock frequency To minimize dynamic power the PB divisor should be instead of scaling the previous value chosen to run the peripherals at the lowest frequency based on a change in PB divisor ratio. that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock require- Oscillator start-up and PLL lock delays are ments such as baud rate accuracy should be taken into applied when switching to a clock source account. For example, the UART peripheral may not be that was disabled and that uses a crystal able to achieve all baud rate values at some PBCLK and/or the PLL. For example, assume the divider depending on the SYSCLK value. clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator start-up delay would be applied when exiting Idle. How- ever, when switching back to POSC, the appropriate PLL and/or oscillator startup/lock delays would be applied. The device enters Idle mode when the SLPEN (OSCCON<4>) bit is clear and a WAIT instruction is executed. DS61143H-page 130 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 26.0 SPECIAL FEATURES PIC32MX3XX/4XX devices include several features intended to maximize application flexibility and reliabil- Note: This data sheet summarizes the features of ity and minimize cost through elimination of external the PIC32MX3XX/4XX family family of components. These are: devices. It is not intended to be a compre- • Flexible Device Configuration hensive reference source. To complement • Watchdog Timer the information in this data sheet, refer to • JTAG Interface Section 9. “Watchdog Timer and Power-up Timer” (DS61114), Section • In-Circuit Serial Programming™ (ICSP™) 32. “Configuration” (DS61124) and Section 33. “Programming and Diag- 26.1 Configuration Bits nostics” (DS61129) of the “PIC32 Family The Configuration bits can be programmed to select Reference Manual”, which is available from various device configurations. the Microchip web site (www.microchip.com/PIC32). REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P 31:24 — — — CP — — — BWP r-1 r-1 r-1 r-1 R/P R/P R/P R/P 23:16 — — — — PWP<7:4> R/P R/P R/P R/P r-1 r-1 r-1 r-1 15:8 PWP<3:0> — — — — r-1 r-1 r-1 r-1 R/P r-1 R/P R/P 7:0 — — — — ICESEL — DEBUG<1:0> Legend: R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown) bit 31 Reserved: Write ‘0’ bit 30-29 Reserved: Write ‘1’ bit 28 CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection disabled 0 = Protection enabled bit 27-25 Reserved: Write ‘1’ bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-20 Reserved: Write ‘1’ © 2011 Microchip Technology Inc. DS61143H-page 131

PIC32MX3XX/4XX REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 19-12 PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one’s compliment of the number of write protected program Flash memory pages. 11111111 = Disabled 11111110 = 0xBD00_0FFF 11111101 = 0xBD00_1FFF 11111100 = 0xBD00_2FFF 11111011 = 0xBD00_3FFF 11111010 = 0xBD00_4FFF 11111001 = 0xBD00_5FFF 11111000 = 0xBD00_6FFF 11110111 = 0xBD00_7FFF 11110110 = 0xBD00_8FFF 11110101 = 0xBD00_9FFF 11110100 = 0xBD00_AFFF 11110011 = 0xBD00_BFFF 11110010 = 0xBD00_CFFF 11110001 = 0xBD00_DFFF 11110000 = 0xBD00_EFFF 11101111 = 0xBD00_FFFF . . . 01111111 = 0xBD07_FFFF bit 11-4 Reserved: Write ‘1’ bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used bit 2 Reserved: Write ‘1’ bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled) 11 = Debugger disabled 10 = Debugger enabled 01 = Reserved (same as ‘11’ setting) 00 = Reserved (same as ‘11’ setting) DS61143H-page 132 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:24 — — — — — — — — R/P r-1 r-1 R/P R/P R/P R/P R/P 23:16 FWDTEN — — WDTPS<4:0> R/P R/P R/P R/P r-1 R/P R/P R/P 15:8 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0> R/P r-1 R/P r-1 r-1 R/P R/P R/P 7:0 IESO — FSOSCEN — — FNOSC<2:0> Legend: R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown) bit 31-24 Reserved: Write ‘1’ bit 23 FWDTEN: Watchdog Timer Enable bit 1 = The WDT is enabled and cannot be disabled by software 0 = The WDT is not enabled; it can be enabled in software bit 22-21 Reserved: Write ‘1’ bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = ‘10100’ bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled Note 1: Do not disable POSC (POSCMOD = 00) when using this oscillator source. © 2011 Microchip Technology Inc. DS61143H-page 133

PIC32MX3XX/4XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write ‘1’ bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0>=11 OR 00) 0 = CLKO output disabled bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS oscillator mode selected 01 = XT oscillator mode selected 00 = External clock mode selected bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled) bit 6 Reserved: Write ‘1’ bit 5 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 4-3 Reserved: Write ‘1’ bit 2-0 FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Note 1: Do not disable POSC (POSCMOD = 00) when using this oscillator source. DS61143H-page 134 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:24 — — — — — — — — r-1 r-1 r-1 r-1 r-1 R/P R/P R/P 23:16 — — — — — FPLLODIV<2:0> R/P r-1 r-1 r-1 r-1 R/P R/P R/P 15:8 UPLLEN — — — — UPLLIDIV<2:0> r-1 R/P R/P R/P r-1 R/P R/P R/P 7:0 — FPLLMUL<2:0> — FPLLIDIV<2:0> Legend: R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown) bit 31-19 Reserved: Write ‘1’ bit 18-16 FPLLODIV<2:0>: Default Postscaler for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 15 UPLLEN: USB PLL Enable bit 1 = Disable and bypass USB PLL 0 = Enable USB PLL bit 14-11 Reserved: Write ‘1’ bit 10-8 UPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 Reserved: Write ‘1’ bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 Reserved: Write ‘1’ bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider © 2011 Microchip Technology Inc. DS61143H-page 135

PIC32MX3XX/4XX REGISTER 26-4: DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:24 — — — — — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 23:16 — — — — — — — — R/P R/P R/P R/P R/P R/P R/P R/P 15:8 USERID<15:8> R/P R/P R/P R/P R/P R/P R/P R/P 7:0 USERID<7:0> Legend: R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown) bit 31-16 Reserved: Write ‘1’ bit 15-0 USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSP™ and JTAG REGISTER 26-5: DEVID: DEVICE AND REVISION ID REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R R R R R R R R 31:24 VER<3:0>(1) DEVID<27:24>(1) R R R R R R R R 23:16 DEVID<23:16>(1) R R R R R R R R 15:8 DEVID<15:8>(1) R R R R R R R R 7:0 DEVID<7:0>(1) Legend: R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown) bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID(1) Note 1: See the “PIC32MX Flash Programming Specification” (DS61145) for a list of Revision and Device ID values. DS61143H-page 136 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 26.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-Up Timer of the PIC32MX3XX/4XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by reset- ting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. The following are some of the key features of the WDT module: • Configuration or software controlled • User-configurable time-out period • Can wake the device from Sleep or Idle FIGURE 26-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM PWRTEnable LPRC WDTEnable Control PWRTEnable 1:64Output LPRC PWRT Oscillator 1 Clock 25-bitCounter WDTCLR=1 WDTEnable 25 Wake 0 DeviceReset WDTCounterReset WDT Enable 1 NMI(Wake-up) Reset Event PowerSave Decoder FWDTPS<4:0>(DEVCFG1<20:16>) © 2011 Microchip Technology Inc. DS61143H-page 137

PIC32MX3XX/4XX 26.3 On-Chip Voltage Regulator 26.3.1 ON-CHIP REGULATOR AND POR All PIC32MX3XX/4XX device’s core and digital logic When the voltage regulator is enabled, it takes fixed are designed to operate at a nominal 1.8V. To simplify delay for it to generate output. During this time, desig- system designs, most devices in the nated as TPU, code execution is disabled. TPU is applied PIC32MX3XX/4XX incorporate an on-chip regulator every time the device resumes operation after any providing the required core logic voltage from VDD. power-down, including Sleep mode. The internal 1.8V regulator is controlled by the If the regulator is disabled, a separate Power-up Timer ENVREG pin. Tying this pin to VDD enables the regu- (PWRT) is automatically enabled. The PWRT adds a lator, which in turn provides power to the core. A low fixed delay of TPWRT at device start-up. See ESR capacitor (such as tantalum) must be connected Section29.0 “Electrical Characteristics” for more to the VCORE/VCAP pin (Figure26-2). This helps to information on TPU AND TPWRT. maintain the stability of the regulator. The recom- 26.3.2 ON-CHIP REGULATOR AND BOR mended value for the filer capacitor is provided in Section29.1 “DC Characteristics”. When the on-chip regulator is enabled, PIC32MX3XX/4XX devices also have a simple brown- Note: It is important that the low ESR capacitor out capability. If the voltage supplied to the regulator is is placed as close as possible to the inadequate to maintain a regulated level, the regulator VCORE/VCAP pin. Reset circuitry will generate a Brown-out Reset. This Tying the ENVREG pin to VSS disables the regulator. In event is captured by the BOR flag bit (RCON<1>). The this case, separate power for the core logic at a nomi- brown-out voltage levels are specific in Section29.1 nal 1.8V must be supplied to the device on the “DC Characteristics”. VCORE/VCAP pin. 26.3.3 POWER-UP REQUIREMENTS Alternatively, the VCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to The on-chip regulator is designed to meet the power-up Figure26-2 for possible configurations. requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VCORE must never exceed VDD by 0.3 volts. FIGURE 26-2: CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled (ENVREG tied to VDD): Regulator Disabled (ENVREG tied to ground): 3.3V 1.8V(1) 3.3V(1) PIC32MX PIC32MX VDD VDD ENVREG ENVREG VCORE/VCAP VCORE/VCAP CEFC (10μF typ) VSS VSS Note 1: These are typical operating voltages. Refer to Section29.1 “DC Characteristics” for the full operating ranges of VDD and VCORE. DS61143H-page 138 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 26.4 Programming and Diagnostics PIC32MX3XX/4XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: • Simplified field programmability using two-wire In- Circuit Serial Programming™ (ICSP™) interfaces • Debugging using ICSP • Programming and debugging capabilities using the EJTAG extension of JTAG • JTAG boundary scan testing for device and board diagnostics PIC32MX devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. FIGURE 26-3: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS PGEC1 PGED1 ICSP™ Controller PGEC2 PGED2 ICESEL TDI TDO JTAG Controller Core TCK TMS JTAGEN DEBUG<1:0> TRCLK TRD0 Instruction Trace TRD1 Controller TRD2 TRD3 DEBUG<1:0> © 2011 Microchip Technology Inc. DS61143H-page 139

PIC32MX3XX/4XX REGISTER 26-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 r-x r-x r-x r-x r-x r-x r-x r-x 31:24 — — — — — — — — r-x r-x r-x r-x r-x r-x r-x r-x 23:16 — — — — — — — — r-x r-x r-x r-x r-x r-x r-x r-x 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 r-x r-x 7:0 DDPUSB DDPU1 DDPU2 DDPSPI1 JTAGEN TROEN — — Legend: R=Readable bit W=Writable bit P=Programmable bit r=Reserved bit U=Unimplemented bit -n=Bit Value at POR: (‘0’, ‘1’, x=Unknown) bit 31-8 Reserved: Write ‘0’; ignore read bit 7 DDPUSB: Debug Data Port Enable for USB bit 1 = USB peripheral ignores USBFRZ (U1CNFG1<5>) setting 0 = USB peripheral follows USBFRZ setting bit 6 DDPU1: Debug Data Port Enable for UART1 bit 1 = UART1 peripheral ignores FRZ (U1MODE<14>) setting 0 = UART1 peripheral follows FRZ setting bit 5 DDPU2: Debug Data Port Enable for UART2 bit 1 = UART2 peripheral ignores FRZ (U2MODE<14>) setting 0 = UART2 peripheral follows FRZ setting bit 4 DDPSPI1: Debug Data Port Enable for SPI1 bit 1 = SPI1 peripheral ignores FRZ (SPI1CON<14>) setting 0 = SPI1 peripheral follows FRZ setting bit 3 JTAGEN: JTAG Port Enable bit 1 = Enable JTAG Port 0 = Disable JTAG Port bit 2 TROEN: Trace Output Enable bit 1 = Enable Trace Port 0 = Disable Trace Port bit 1-0 Reserved: Write ‘1’; ignore read DS61143H-page 140 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 27.0 INSTRUCTION SET Table27-1 provides a summary of the instructions that are implemented by the PIC32MX3XX/4XX family The PIC32MX3XX/4XX family instruction set complies core. with the MIPS32 Release 2 instruction set architecture. PIC32MX does not support the following features: Note: Refer to “MIPS32® Architecture for Pro- grammers Volume II: The MIPS32® • CoreExtend instructions Instruction Set” at www.mips.com for • Coprocessor 1 instructions more information. • Coprocessor 2 instructions TABLE 27-1: MIPS32® INSTRUCTION SET Instruction Description Function ADD Integer Add Rd = Rs + Rt ADDI Integer Add Immediate Rt = Rs + Immed ADDIU Unsigned Integer Add Immediate Rt = Rs + Immed U ADDU Unsigned Integer Add Rd = Rs + Rt U AND Logical AND Rd = Rs & Rt ANDI Logical AND Immediate Rt = Rs & (0 || Immed) 16 B Unconditional Branch PC += (int)offset (Assembler idiom for: BEQ r0, r0, offset) BAL Branch and Link GPR[31] = PC + 8 (Assembler idiom for: BGEZAL r0, offset) PC += (int)offset BEQ Branch on Equal if Rs == Rt PC += (int)offset BEQL Branch on Equal Likely(1) if Rs == Rt PC += (int)offset else Ignore Next Instruction BGEZ Branch on Greater Than or Equal to Zero if !Rs[31] PC += (int)offset BGEZAL Branch on Greater Than or Equal to Zero and Link GPR[31] = PC + 8 if !Rs[31] PC += (int)offset BGEZALL Branch on Greater Than or Equal to Zero and Link GPR[31] = PC + 8 Likely(1) if !Rs[31] PC += (int)offset else Ignore Next Instruction BGEZL Branch on Greater Than or Equal to Zero Likely(1) if !Rs[31] PC += (int)offset else Ignore Next Instruction BGTZ Branch on Greater Than Zero if !Rs[31] && Rs != 0 PC += (int)offset BGTZL Branch on Greater Than Zero Likely(1) if !Rs[31] && Rs != 0 PC += (int)offset else Ignore Next Instruction BLEZ Branch on Less Than or Equal to Zero if Rs[31] || Rs == 0 PC += (int)offset Note 1: This instruction is deprecated and should not be used. © 2011 Microchip Technology Inc. DS61143H-page 141

PIC32MX3XX/4XX TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED) Instruction Description Function BLEZL Branch on Less Than or Equal to Zero Likely(1) if Rs[31] || Rs == 0 PC += (int)offset else Ignore Next Instruction BLTZ Branch on Less Than Zero if Rs[31] PC += (int)offset BLTZAL Branch on Less Than Zero and Link GPR[31] = PC + 8 if Rs[31] PC += (int)offset BLTZALL Branch on Less Than Zero and Link Likely(1) GPR[31] = PC + 8 if Rs[31] PC += (int)offset else Ignore Next Instruction BLTZL Branch on Less Than Zero Likely(1) if Rs[31] PC += (int)offset else Ignore Next Instruction BNE Branch on Not Equal if Rs != Rt PC += (int)offset BNEL Branch on Not Equal Likely(1) if Rs != Rt PC += (int)offset else Ignore Next Instruction BREAK Breakpoint Break Exception CLO Count Leading Ones Rd = NumLeadingOnes(Rs) CLZ Count Leading Zeroes Rd = NumLeadingZeroes(Rs) DERET Return from Debug Exception PC = DEPC Exit Debug Mode DI Atomically Disable Interrupts Rt = Status; Status = 0 IE DIV Divide LO = (int)Rs / (int)Rt HI = (int)Rs % (int)Rt DIVU Unsigned Divide LO = (uns)Rs / (uns)Rt HI = (uns)Rs % (uns)Rt EHB Execution Hazard Barrier Stop instruction execution until execution hazards are cleared EI Atomically Enable Interrupts Rt = Status; Status = 1 IE ERET Return from Exception if Status ERL PC = ErrorEPC else PC = EPC Status = 0 EXL Status = 0 ERL LL = 0 EXT Extract Bit Field Rt = ExtractField(Rs, pos, size) INS Insert Bit Field Rt = InsertField(Rs, Rt, pos, size) J Unconditional Jump PC = PC[31:28] || offset<<2 Note 1: This instruction is deprecated and should not be used. DS61143H-page 142 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED) Instruction Description Function JAL Jump and Link GPR[31] = PC + 8 PC = PC[31:28] || offset<<2 JALR Jump and Link Register Rd = PC + 8 PC = Rs JALR.HB Jump and Link Register with Hazard Barrier Like JALR, but also clears execution and instruction hazards JR Jump Register PC = Rs JR.HB Jump Register with Hazard Barrier Like JR, but also clears execution and instruction hazards LB Load Byte Rt = (byte)Mem[Rs+offset] LBU Unsigned Load Byte Rt = (ubyte))Mem[Rs+offset] LH Load Halfword Rt = (half)Mem[Rs+offset] LHU Unsigned Load Halfword Rt = (uhalf)Mem[Rs+offset] LL Load Linked Word Rt = Mem[Rs+offset> LL = 1 bit LLAdr = Rs + offset LUI Load Upper Immediate Rt = immediate << 16 LW Load Word Rt = Mem[Rs+offset] LWPC Load Word, PC relative Rt = Mem[PC+offset] LWL Load Word Left Re = Re MERGE Mem[Rs+offset] LWR Load Word Right Re = Re MERGE Mem[Rs+offset] MADD Multiply-Add HI | LO += (int)Rs * (int)Rt MADDU Multiply-Add Unsigned HI | LO += (uns)Rs * (uns)Rt MFC0 Move from Coprocessor 0 Rt = CPR[0, Rd, sel] MFHI Move from HI Rd = HI MFLO Move from LO Rd = LO MOVN Move Conditional on Not Zero if Rt ¼ 0 then Rd = Rs MOVZ Move Conditional on Zero if Rt = 0 then Rd = Rs MSUB Multiply-Subtract HI | LO -= (int)Rs * (int)Rt MSUBU Multiply-Subtract Unsigned HI | LO -= (uns)Rs * (uns)Rt MTC0 Move to Coprocessor 0 CPR[0, n, Sel] = Rt MTHI Move to HI HI = Rs MTLO Move to LO LO = Rs MUL Multiply with register write HI | LO =Unpredictable Rd = ((int)Rs * (int)Rt) 31..0 MULT Integer Multiply HI | LO = (int)Rs * (int)Rd MULTU Unsigned Multiply HI | LO = (uns)Rs * (uns)Rd NOP No Operation (Assembler idiom for: SLL r0, r0, r0) NOR Logical NOR Rd = ~(Rs | Rt) OR Logical OR Rd = Rs | Rt ORI Logical OR Immediate Rt = Rs | Immed RDHWR Read Hardware Register (if enabled by HWREna Re = HWR[Rd] Register) Note 1: This instruction is deprecated and should not be used. © 2011 Microchip Technology Inc. DS61143H-page 143

PIC32MX3XX/4XX TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED) Instruction Description Function RDPGPR Read GPR from Previous Shadow Set Rt = SGPR[SRSCtl , Rd] PSS ROTR Rotate Word Right Rd = Rt || Rt sa-1..0 31..sa ROTRV Rotate Word Right Variable Rd = Rt || Rt Rs-1..0 31..Rs SB Store Byte (byte)Mem[Rs+offset] = Rt SC Store Conditional Word if LL = 1 bit mem[Rs+offset> = Rt Rt = LL bit SDBBP Software Debug Break Point Trap to SW Debug Handler SEB Sign-Extend Byte Rd = SignExtend (Rs-7...0) SEH Sign-Extend Half Rd = SignExtend (Rs-15...0) SH Store Half (half)Mem[Rs+offset> = Rt SLL Shift Left Logical Rd = Rt << sa SLLV Shift Left Logical Variable Rd = Rt << Rs[4:0] SLT Set on Less Than if (int)Rs < (int)Rt Rd = 1 else Rd = 0 SLTI Set on Less Than Immediate if (int)Rs < (int)Immed Rt = 1 else Rt = 0 SLTIU Set on Less Than Immediate Unsigned if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0 SLTU Set on Less Than Unsigned if (uns)Rs < (uns)Immed Rd = 1 else Rd = 0 SRA Shift Right Arithmetic Rd = (int)Rt >> sa SRAV Shift Right Arithmetic Variable Rd = (int)Rt >> Rs[4:0] SRL Shift Right Logical Rd = (uns)Rt >> sa SRLV Shift Right Logical Variable Rd = (uns)Rt >> Rs[4:0] SSNOP Superscalar Inhibit No Operation NOP SUB Integer Subtract Rt = (int)Rs - (int)Rd SUBU Unsigned Subtract Rt = (uns)Rs - (uns)Rd SW Store Word Mem[Rs+offset] = Rt SWL Store Word Left Mem[Rs+offset] = Rt SWR Store Word Right Mem[Rs+offset] = Rt SYNC Synchronize Orders the cached coherent and uncached loads and stores for access to the shared memory SYSCALL System Call SystemCallException TEQ Trap if Equal if Rs == Rt TrapException TEQI Trap if Equal Immediate if Rs == (int)Immed TrapException Note 1: This instruction is deprecated and should not be used. DS61143H-page 144 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 27-1: MIPS32® INSTRUCTION SET (CONTINUED) Instruction Description Function TGE Trap if Greater Than or Equal if (int)Rs >= (int)Rt TrapException TGEI Trap if Greater Than or Equal Immediate if (int)Rs >= (int)Immed TrapException TGEIU Trap if Greater Than or Equal Immediate Unsigned if (uns)Rs >= (uns)Immed TrapException TGEU Trap if Greater Than or Equal Unsigned if (uns)Rs >= (uns)Rt TrapException TLT Trap if Less Than if (int)Rs < (int)Rt TrapException TLTI Trap if Less Than Immediate if (int)Rs < (int)Immed TrapException TLTIU Trap if Less Than Immediate Unsigned if (uns)Rs < (uns)Immed TrapException TLTU Trap if Less Than Unsigned if (uns)Rs < (uns)Rt TrapException TNE Trap if Not Equal if Rs != Rt TrapException TNEI Trap if Not Equal Immediate if Rs != (int)Immed TrapException WAIT Wait for Interrupt Go to a low power mode and stall until interrupt occurs WRPGPR Write to GPR in Previous Shadow Set SGPR[SRSCtl , Rd> = Rt PSS WSBH Word Swap Bytes Within Halfwords Rd = Rt || Rt || Rt 23..16 31..24 7..0 || Rt 15..8 XOR Exclusive OR Rd = Rs ^ Rt XORI Exclusive OR Immediate Rt = Rs ^ (uns)Immed Note 1: This instruction is deprecated and should not be used. © 2011 Microchip Technology Inc. DS61143H-page 145

PIC32MX3XX/4XX NOTES: DS61143H-page 146 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 28.0 DEVELOPMENT SUPPORT 28.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® • Integrated Development Environment operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2011 Microchip Technology Inc. DS61143H-page 147

PIC32MX3XX/4XX 28.2 MPLAB C Compilers for Various 28.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 28.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 28.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 28.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS61143H-page 148 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 28.7 MPLAB SIM Software Simulator 28.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 28.10 PICkit 3 In-Circuit Debugger/ Programmer and 28.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2011 Microchip Technology Inc. DS61143H-page 149

PIC32MX3XX/4XX 28.11 PICkit 2 Development 28.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 28.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS61143H-page 150 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings (Note 1) Ambient temperature under bias.............................................................................................................-40°C to +105°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3).........................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on VCORE with respect to VSS ....................................................................................................... -0.3V to 2.0V Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s).......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table29-2). 3: See the “Pin Diagrams” section for the 5V tolerant pins. © 2011 Microchip Technology Inc. DS61143H-page 151

PIC32MX3XX/4XX 29.1 DC Characteristics TABLE 29-1: OPERATING MIPS VS. VOLTAGE Max. Frequency VDD Range Temp. Range Characteristic (in Volts) (in °C) PIC32MX3XX/4XX DC5 2.3V-3.6V -40°C to +85°C 80 MHz (Note 1) DC5b 2.3V-3.6V -40°C to +105°C 80 MHz (Note 1) Note 1: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. TABLE 29-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max. Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C V-Temp Temperature Devices Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +105 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – S IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W TABLE 29-3: THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical Max. Unit Notes θ Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm) JA 40 — °C/W 1 θ Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) JA 43 — °C/W 1 θ Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) JA 47 — °C/W 1 θ Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) JA 28 — °C/W 1 θ Note 1: Junction to ambient thermal resistance, Theta-JA ( JA) numbers are achieved by package simulations. TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical Max. Units Conditions No. Operating Voltage DC10 VDD Supply Voltage 2.3 — 3.6 V — DC12 VDR RAM Data Retention Voltage 1.75 — — V — (Note 1) DC16 VPOR VDD Start Voltage 1.75 — 1.95 V — to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms — to Ensure Internal Power-on Reset Signal Note 1: This is the limit to which VDD can be lowered without losing RAM data. DS61143H-page 152 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Typical(3) Max. Units Conditions No. Operating Current (IDD)(1,2) -40ºC, 8.5 13 +25ºC, DC20 mA Code executing from Flash +85ºC — 4 MHz 9 15 +105ºC DC20c 4.0 — mA Code executing from SRAM — DC21 23.5 32 mA Code executing from Flash 20 MHz — — DC21c 16.4 — mA Code executing from SRAM (Note 4) DC22 48 61 mA Code executing from Flash 60 MHz — — DC22c 45 — mA Code executing from SRAM (Note 4) -40ºC, 55 75 +25ºC, DC23 mA Code executing from Flash 2.3V +85ºC 80 MHz 60 100 +105ºC DC23c 55 — mA Code executing from SRAM — — DC24 — 100 µA — -40°C DC24a — 130 µA — +25°C 2.3V DC24b — 670 µA — +85°C DC24c — 850 µA — +105ºC DC25 94 — µA — -40°C DC25a 125 — µA — +25°C 3.3V LPRC (31 kHz) DC25b 302 — µA — +85°C (Note 4) DC25d 400 — µA — +105ºC DC25c 71 — µA Code executing from SRAM — — DC26 — 110 µA — -40°C DC26a — 180 µA — +25°C 3.6V DC26b — 700 µA — +85°C DC26c — 900 µA — +105ºC Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type as well as temperature can have an impact on the current consumption. 2: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are dis- abled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. 3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. 4: This parameter is characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. DS61143H-page 153

PIC32MX3XX/4XX TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Parameter Typical(2) Max. Units Conditions No. Idle Current (IIDLE): Core OFF, Clock ON Base Current (Note 1) DC30 — 5 mA -40ºC, +25ºC, +85ºC 2.3V DC30a 1.4 — mA -40ºC, +25ºC, +85ºC — 4 MHz DC30b — 5 mA -40ºC, +25ºC, +85ºC 3.6V DC30c — 8 mA +105ºC DC31 — 15 mA -40ºC, +25ºC, +85ºC 2.3V DC31a 13 — mA -40ºC, +25ºC, +85ºC — 20 MHz DC31b — 17 mA -40ºC, +25ºC, +85ºC (Note 3) 3.6V DC31c — 25 mA +105ºC DC32 — 22 mA -40ºC, +25ºC, +85ºC 2.3V DC32a 20 — mA -40ºC, +25ºC, +85ºC — 60 MHz DC32b — 25 mA -40ºC, +25ºC, +85ºC (Note 3) 3.6V DC32c — 32 mA +105ºC DC33 — 29 mA -40ºC, +25ºC, +85ºC 2.3V DC33a 24 — mA -40ºC, +25ºC, +85ºC — 80 MHz DC33b — 32 mA -40ºC, +25ºC, +85ºC 3.6V DC33c — 40 mA +105ºC DC34 — 36 µA -40°C DC34a — 62 µA +25°C 2.3V DC34b — 392 µA +85°C DC34c — 550 µA +105ºC DC35 35 — µA -40°C DC35a 65 — µA +25°C LPRC (31 kHz) 3.3V DC35b 242 — µA +85°C (Note 3) DC35c 350 — µA +105ºC DC36 — 43 µA -40°C DC36a — 106 µA +25°C 3.6V DC36b — 414 µA +85°C DC36c — 600 µA +105ºC Note 1: The test conditions for base IDLE current measurements are as follows: System clock is enabled and PBCLK divisor = 1:8. CPU in Idle mode (CPU core halted). Only digital peripheral modules are enabled (ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: This parameter is characterized, but not tested in manufacturing. DS61143H-page 154 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Parameter Typical(2) Max. Units Conditions No. Power-Down Current (IPD)(1) DC40 7 30 μA -40°C DC40a 24 30 μA +25°C 2.3V Base Power-Down Current (Note 6) DC40b 205 300 μA +85°C DC40h 450 900 µA +105ºC DC40c 25 — μA +25°C 3.3V Base Power-Down Current DC40d 9 70 μA -40°C DC40e 25 70 μA +25°C DC40g 115 200(5) μA +70°C 3.6V Base Power-Down Current DC40f 200 400 μA +85°C DC40i 470 1200 µA +105ºC Module Differential Current DC41 — 10 μA -40°C DC41a — 10 μA +25°C 2.3V Watchdog Timer Current: ΔIWDT (Notes 3, 6) DC41b — 10 μA +85°C DC41g — 12 µA +105ºC DC41c 5 — μA +25°C 3.3V Watchdog Timer Current: ΔIWDT (Note 3) DC41d — 10 μA -40°C DC41e — 10 μA +25°C 3.6V Watchdog Timer Current: ΔIWDT (Note 3) DC41f — 12 μA +85°C DC41h — 15 µA +105ºC DC42 — 10 μA -40°C DC42a — 17 μA +25°C RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC 2.3V DC42b — 37 μA +85°C (Notes 3, 6) DC42h — 45 µA +105ºC DC42c 23 — μA +25°C 3.3V RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3) DC42e — 10 μA -40°C DC42f — 30 μA +25°C 3.6V RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3) DC42g — 44 μA +85°C DC42i — 44 µA +105ºC Note 1: Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled. 2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: Data is characterized at +70°C and not tested. Parameter is for design guidance only. 6: This parameter is characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. DS61143H-page 155

PIC32MX3XX/4XX TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Parameter Typical(2) Max. Units Conditions No. Module Differential Current (Continued) DC43 — 1100 μA -40°C DC43a — 1100 μA +25°C 2.5V ADC: ΔIADC (Notes 3, 4, 6) DC43b — 1000 μA +85°C DC43h — 1200 µA +105ºC DC43c 880 — μA — — ADC: ΔIADC (Notes 3, 4) DC43e — 1100 μA -40°C DC43f — 1100 μA +25°C 3.6V ADC: ΔIADC (Notes 3, 4) DC43g — 1000 μA +85°C DC43i — 1200 µA +105ºC Note 1: Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled. 2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: Data is characterized at +70°C and not tested. Parameter is for design guidance only. 6: This parameter is characterized, but not tested in manufacturing. DS61143H-page 156 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. VIL Input Low Voltage DI10 I/O pins: with TTL Buffer VSS — 0.15VDD V (Note 4) with Schmitt Trigger Buffer VSS — 0.2VDD V (Note 4) DI15 MCLR VSS — 0.2VDD V (Note 4) DI16 OSC1 (XT mode) VSS — 0.2VDD V (Note 4) DI17 OSC1 (HS mode) VSS — 0.2VDD V (Note 4) DI18 SDAx, SCLx VSS — 0.3VDD V SMBus disabled (Note 4) DI19 SDAx, SCLx VSS — 0.8 V SMBus enabled (Note 4) VIH Input High Voltage DI20 I/O pins: with Analog Functions 0.8VDD — VDD V (Note 4) Digital Only 0.8VDD — V (Note 4) with TTL Buffer 0.25VDD + 0.8V — 5.5 V (Note 4) with Schmitt Trigger Buffer 0.8VDD — 5.5 V (Note 4) DI25 MCLR 0.8VDD — VDD V (Note 4) DI26 OSC1 (XT mode) 0.7VDD — VDD V (Note 4) DI27 OSC1 (HS mode) 0.7VDD — VDD V (Note 4) DI28 SDAx, SCLx 0.7VDD — 5.5 V SMBus disabled (Note 4) DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled, 2.3V ≤ VPIN ≤ 5.5 (Note 4) DI30 ICNPU CNxx Pull up Current 50 250 400 μA VDD = 3.3V, VPIN = VSS IIL Input Leakage Current (Note 3) DI50 I/O Ports — — +1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51 Analog Input Pins — — +1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI55 MCLR — — +1 μA VSS ≤ VPIN ≤ VDD DI56 OSC1 — — +1 μA VSS ≤ VPIN ≤ VDD, XT and HS modes Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. DS61143H-page 157

PIC32MX3XX/4XX TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical Max. Units Conditions No. VOL Output Low Voltage DO10 I/O Ports — — 0.4 V IOL = 7 mA, VDD = 3.6V — — 0.4 V IOL = 6 mA, VDD = 2.3V DO16 OSC2/CLKO — — 0.4 V IOL = 3.5 mA, VDD = 3.6V — — 0.4 V IOL = 2.5 mA, VDD = 2.3V VOH Output High Voltage DO20 I/O Ports 2.4 — — V IOH = -12 mA, VDD = 3.6V 1.4 — — V IOH = -12 mA, VDD = 2.3V DO26 OSC2/CLKO 2.4 — — V IOH = -12 mA, VDD = 3.6V 1.4 — — V IOH = -12 mA, VDD = 2.3V TABLE 29-10: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical Max. Units Conditions No. BO10 VBOR BOR Event on VDD 2.0 — 2.3 V — transition high-to-low DS61143H-page 158 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY(3) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. Program Flash Memory D130 EP Cell Endurance 1000 — — E/W — D131 VPR VDD for Read VMIN — 3.6 V — D132 VPEW VDD for Erase or Write 3.0 — 3.6 V — D134 TRETD Characteristic Retention 20 — — Year — D135 IDDP Supply Current during — 10 — mA — Programming TWW Word Write Cycle Time 20 — 40 μs — D136 TRW Row Write Cycle Time(2) 3 4.5 — ms — (128 words per row) D137 TPE Page Erase Cycle Time 20 — — ms — TCE Chip Erase Cycle Time 80 — — ms — D138 LVDstartup Flash LVD Delay — — 6 μs — Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. 2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). 3: Refer to the “PIC32MX Flash Programming Specification” (DS61145) for operating conditions during programming and erase cycles. TABLE 29-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Required Flash wait states SYSCLK Units Comments 0 Wait State 0 to 30 1 Wait State 31 to 60 MHz — 2 Wait States 61 to 80 Note 1: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. © 2011 Microchip Technology Inc. DS61143H-page 159

PIC32MX3XX/4XX TABLE 29-13: COMPARATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical Max. Units Comments No. D300 VIOFF Input Offset Voltage — ±7.5 ±25 mV AVDD = VDD, AVSS = VSS D301 VICM Input Common Mode Voltage 0 — VDD V AVDD = VDD, AVSS = VSS (Note 2) D302 CMRR Common Mode Rejection Ratio 55 — — dB Max VICM = (VDD - 1)V (Note 2) D303 TRESP Response Time — 150 400 ns AVDD = VDD, AVSS = VSS (Notes 1,2) D304 ON2OV Comparator Enabled to Output — — 10 μs Comparator module is Valid configured before setting the comparator ON bit. (Note 2) D305 IVREF Internal Voltage Reference 0.57 0.6 0.63 V — Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. 2: These parameters are characterized but not tested. TABLE 29-14: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical Max. Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb — D311 VRAA Absolute Accuracy — — 1/2 LSb — D312 TSET Settling Time(1) — — 10 μs — Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. This parameter is characterized, but not tested in manufacturing. TABLE 29-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical Max. Units Comments No. D320 VCORE Regulator Output Voltage 1.62 1.80 1.98 V — D321 CEFC External Filter Capacitor Value 8 10 — μF Capacitor must be low series resistance (< 1 Ohm) D322 TPWRT Power-up Timer Period — 64 — ms ENVREG = 0 DS61143H-page 160 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 29.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX3XX/4XX AC characteristics and timing parameters. FIGURE 29-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS Pin CL RL = 464Ω CL = 50 pF for all pins VSS 50 pF for OSC2 pin (EC mode) TABLE 29-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 OS31 © 2011 Microchip Technology Inc. DS61143H-page 161

PIC32MX3XX/4XX TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. OS10 FOSC External CLKI Frequency DC — 50(3) MHz EC (Note 5) (External clocks allowed only 4 — 50(5) MHz ECPLL (Note 4) in EC and ECPLL modes) OS11 Oscillator Crystal Frequency 3 — 10 MHz XT (Note 5) OS12 4 — 10 MHz XTPLL (Notes 4, 5) OS13 10 — 25 MHz HS (Note 5) OS14 10 — 25 MHz HSPLL (Notes 4, 5) OS15 32 32.768 100 kHz SOSC (Note 5) OS20 TOSC TOSC = 1/FOSC = TCY(2) — — — — See parameter OS10 for FOSC value OS30 TOSL, External Clock In (OSC1) 0.45 x TOSC — — ns EC (Note 5) TOSH High or Low Time OS31 TOSR, External Clock In (OSC1) — — 0.05 x TOSC ns EC (Note 5) TOSF Rise or Fall Time OS40 TOST Oscillator Start-up Timer Period — 1024 — TOSC (Note 5) (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) OS41 TFSCM Primary Clock Fail Safe — 2 — ms (Note 5) Time-out Period OS42 GM External Oscillator — 12 — mA/V VDD = 3.3V Transconductance TA = +25°C (Note 5) Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not tested. 2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. 3: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. 4: PLL input requirements: 4 MHZ ≤ FPLLIN ≤ 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. 5: This parameter is characterized, but not tested in manufacturing. DS61143H-page 162 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical Max. Units Conditions No. OS50 FPLLI PLL Voltage Controlled 4 — 5 MHz ECPLL, HSPLL, XTPLL, Oscillator (VCO) Input FRCPLL modes Frequency Range OS51 FSYS On-Chip VCO System 60 — 120 MHz — Frequency OS52 TLOCK PLL Start-up Time (Lock Time) — — 2 ms — OS53 DCLK CLKO Stability(2) -0.25 — +0.25 % Measured over 100 ms (Period Jitter or Cumulative) period Note 1: These parameters are characterized, but not tested in manufacturing. 2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula: D EffectiveJitter = -----------------------------C----L---K-------------------------- SYSCLK ---------------------------------------------------------- CommunicationClock For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows: D D EffectiveJitter = -----C----L--K--- = -----C----L--K--- 80 2 ------ 20 TABLE 29-19: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Characteristics Min. Typical Max. Units Conditions No. Internal FRC Accuracy @ 8.00 MHz(1) F20 FRC -2 — +2 % — Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 29-20: INTERNAL RC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Characteristics Min. Typical Max. Units Conditions No. LPRC @ 31.25 kHz(1) F21 LPRC -15 — +15 % — Note 1: Change of LPRC frequency as VDD changes. © 2011 Microchip Technology Inc. DS61143H-page 163

PIC32MX3XX/4XX FIGURE 29-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) DO31 DO32 Note: Refer to Figure29-1 for load conditions. TABLE 29-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(2) Min. Typical(1) Max. Units Conditions No. DO31 TIOR Port Output Rise Time — 5 15 ns VDD < 2.5V — 5 10 ns VDD > 2.5V DO32 TIOF Port Output Fall Time — 5 15 ns VDD < 2.5V — 5 10 ns VDD > 2.5V DI35 TINP INTx Pin High or Low Time 10 — — ns — DI40 TRBP CNx High or Low Time (input) 2 — — TSYSCLK — Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. 2: This parameter is characterized, but not tested in manufacturing. DS61143H-page 164 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power Up Sequence (Note 2) CPU starts fetching code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power Up Sequence (Note 2) CPU starts fetching code SY00 SY10 (TPU) (TOST) (Note 1) External VCORE Provided Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VCORE VPOR (TSYSDLY) SY02 Power Up Sequence (Note 3) CPU starts fetching code SY01 (TPWRT) (Note 1) Note1: The Power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). 2: Includes interval voltage regulator stabilization delay. 3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled. © 2011 Microchip Technology Inc. DS61143H-page 165

PIC32MX3XX/4XX FIGURE 29-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (TSYSDLY) (SY30) SY02 Reset Sequence CPU starts fetching code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU starts fetching code TOST (SY10) TABLE 29-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SY00 TPU Power-up Period — 400 600 μs -40°C to +85°C Internal Voltage Regulator Enabled SY01 TPWRT Power-up Period 48 64 80 ms -40°C to +85°C External Vcore Applied (Power-Up-Timer Active) SY02 TSYSDLY System Delay Period: — 1 μs — — -40°C to +85°C Time required to reload Device + Configuration Fuses plus SYSCLK 8 SYSCLK delay before first instruction is cycles fetched. SY20 TMCLR MCLR Pulse Width (low) — 2 — μs -40°C to +85°C SY30 TBOR BOR Pulse Width (low) — 1 — μs -40°C to +85°C Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested. DS61143H-page 166 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure29-1 for load conditions. TABLE 29-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(2) Min. Typical Max. Units Conditions No. TA10 TTXH TxCK Synchronous, [(12.5 ns or 1TPB)/N] — — ns Must also meet High Time with prescaler + 25 ns parameter TA15. Asynchronous, 10 — — ns — with prescaler TA11 TTXL TxCK Synchronous, [(12.5 ns or 1TPB)/N] — — ns Must also meet Low Time with prescaler + 25 ns parameter TA15. Asynchronous, 10 — — ns — with prescaler TA15 TTXP TxCK Synchronous, [(Greater of 25 ns or — — ns VDD > 2.7V Input Period with prescaler 2TPB)/N] + 30 ns [(Greater of 25 ns or — — ns VDD < 2.7V 2TPB)/N] + 50 ns Asynchronous, 20 — — ns VDD > 2.7V with prescaler (Note 3) 50 — — ns VDD < 2.7V (Note 3) OS60 FT1 SOSC1/T1CK Oscillator 32 — 100 kHz — Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>)) TA20 TCKEXTMRL Delay from External TxCK — 1 TPB — Clock Edge to Timer Increment Note 1: Timer1 is a Type A. 2: This parameter is characterized, but not tested in manufacturing. 3: N = prescale value (1, 8, 64, 256) © 2011 Microchip Technology Inc. DS61143H-page 167

PIC32MX3XX/4XX TABLE 29-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Max. Units Conditions No. TB10 TTXH TxCK Synchronous, [(12.5 ns or 1TPB)/N] — ns Must also meet N = prescale High with prescaler + 25 ns parameter value Time TB15. (1, 2, 4, 8, 16, 32, 64, 256) TB11 TTXL TxCK Synchronous, [(12.5 ns or 1TPB)/N] — ns Must also meet Low with prescaler + 25 ns parameter Time TB15. TB15 TTXP TxCK Synchronous, [(Greater of 25 ns or — ns VDD > 2.7V Input with prescaler 2 TPB)/N] + 30 ns Period [(Greater of 25 ns or — ns VDD < 2.7V — 2 TPB)/N] + 50 ns TB20 TCKEXTMRL Delay from External — 1 TPB — TxCK Clock Edge to Timer Increment Note 1: These parameters are characterized, but not tested in manufacturing. DS61143H-page 168 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure29-1 for load conditions. TABLE 29-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Max. Units Conditions No. IC10 TCCL ICx Input Low Time [(12.5 ns or 1TPB)/N] — ns Must also N = prescale + 25 ns meet value (1, 4, 16) parameter IC15. IC11 TCCH ICx Input High Time [(12.5 ns or 1TPB)/N] — ns Must also + 25 ns meet parameter IC15. IC15 TCCP ICx Input Period [(25 ns or 2TPB)/N] — ns — + 50 ns Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 29-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure29-1 for load conditions. TABLE 29-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. OC10 TCCF OCx Output Fall Time — — — ns See parameter DO32. OC11 TCCR OCx Output Rise Time — — — ns See parameter DO31. Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. DS61143H-page 169

PIC32MX3XX/4XX FIGURE 29-9: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx OCx is tri-stated Note: Refer to Figure29-1 for load conditions. TABLE 29-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param Symbol Characteristics(1) Min Typical(2) Max Units Conditions No. OC15 TFD Fault Input to PWM I/O Change — — 25 ns — OC20 TFLT Fault Input Pulse Width 50 — — ns — Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS61143H-page 170 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP31 SP30 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure29-1 for load conditions. TABLE 29-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SP10 TSCL SCKx Output Low Time(3) TSCK/2 — — ns — SP11 TSCH SCKx Output High Time(3) TSCK/2 — — ns — SP20 TSCF SCKx Output Fall Time(4) — — — ns See parameter DO32 SP21 TSCR SCKx Output Rise Time(4) — — — ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns — TDIV2SCL to SCKx Edge SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns — TSCL2DIL to SCKx Edge Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. DS61143H-page 171

PIC32MX3XX/4XX FIGURE 29-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SCKX (CKP = 1) SP35 SP20 SP21 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure29-1 for load conditions. TABLE 29-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SP10 TSCL SCKx Output Low Time(3) TSCK/2 — — ns — SP11 TSCH SCKx Output High Time(3) TSCK/2 — — ns — SP20 TSCF SCKx Output Fall Time(4) — — — ns See parameter DO32 SP21 TSCR SCKx Output Rise Time(4) — — — ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V SP36 TDOV2SC, SDOx Data Output Setup to 15 — — ns — TDOV2SCL First SCKx Edge SP40 TDIV2SCH, Setup Time of SDIx Data Input 15 — — ns VDD > 2.7V TDIV2SCL to SCKx Edge 20 — — ns VDD < 2.7V SP41 TSCH2DIL, Hold Time of SDIx Data Input 15 — — ns VDD > 2.7V TSCL2DIL to SCKx Edge 20 — — ns VDD < 2.7V Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS61143H-page 172 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP35 SP72 SP73 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure29-1 for load conditions. TABLE 29-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — ns — SP71 TSCH SCKx Input High Time(3) TSCK/2 — — ns — SP72 TSCF SCKx Input Fall Time — — — ns See parameter DO32 SP73 TSCR SCKx Input Rise Time — — — ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns — TDIV2SCL to SCKx Edge SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns — TSCL2DIL to SCKx Edge SP50 TSSL2SCH, SSx ↓ to SCKx ↑ or SCKx Input 175 — — ns — TSSL2SCL SP51 TSSH2DOZ SSx ↑ to SDOx Output 5 — 25 ns — High-Impedance(3) SP52 TSCH2SSH SSx after SCKx Edge TSCK + 20 — — ns — TSCL2SSH Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. DS61143H-page 173

PIC32MX3XX/4XX FIGURE 29-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure29-1 for load conditions. TABLE 29-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — ns — SP71 TSCH SCKx Input High Time(3) TSCK/2 — — ns — SP72 TSCF SCKx Input Fall Time — 5 10 ns — SP73 TSCR SCKx Input Rise Time — 5 10 ns — SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after — — 20 ns VDD > 2.7V TSCL2DOV SCKx Edge — — 30 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns — TDIV2SCL to SCKx Edge SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns — TSCL2DIL to SCKx Edge SP50 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ 175 — — ns — TSSL2SCL Input SP51 TSSH2DOZ SSx ↑ to SDOX Output 5 — 25 ns — High-Impedance(4) SP52 TSCH2SSH SSx ↑ after SCKx Edge TSCK + — — ns — TSCL2SSH 20 SP60 TSSL2DOV SDOx Data Output Valid after — — 25 ns — SSx Edge Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins. DS61143H-page 174 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure29-1 for load conditions. FIGURE 29-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure29-1 for load conditions. © 2011 Microchip Technology Inc. DS61143H-page 175

PIC32MX3XX/4XX TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min.(1) Max. Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) — μs 400 kHz mode TPB * (BRG + 2) — μs — 1 MHz mode(2) TPB * (BRG + 2) — μs IM11 THI:SCL Clock High Time 100 kHz mode TPB * (BRG + 2) — μs 400 kHz mode TPB * (BRG + 2) — μs — 1 MHz mode(2) TPB * (BRG + 2) — μs IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF. 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF. 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns — 1 MHz mode(2) 100 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — μs Hold Time 400 kHz mode 0 0.9 μs — 1 MHz mode(2) 0 0.3 μs IM30 TSU:STA Start Condition 100 kHz mode TPB * (BRG + 2) — μs Only relevant for Setup Time 400 kHz mode TPB * (BRG + 2) — μs Repeated Start condition. 1 MHz mode(2) TPB * (BRG + 2) — μs IM31 THD:STA Start Condition 100 kHz mode TPB * (BRG + 2) — μs After this period, the Hold Time 400 kHz mode TPB * (BRG + 2) — μs first clock pulse is generated. 1 MHz mode(2) TPB * (BRG + 2) — μs IM33 TSU:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — μs Setup Time 400 kHz mode TPB * (BRG + 2) — μs — 1 MHz mode(2) TPB * (BRG + 2) — μs IM34 THD:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — ns Hold Time 400 kHz mode TPB * (BRG + 2) — ns — 1 MHz mode(2) TPB * (BRG + 2) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns — 1 MHz mode(2) — 350 ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs The amount of time the 400 kHz mode 1.3 — μs bus must be free 1 MHz mode(2) 0.5 — μs before a new transmission can start. IM50 CB Bus Capacitive Loading — 400 pF — IM51 TPGD Pulse Gobbler Delay(3) 52 312 ns — Note 1: BRG is the value of the I2C™ Baud Rate Generator. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: The typical value for this parameter is 104 ns. DS61143H-page 176 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition Note: Refer to Figure29-1 for load conditions. FIGURE 29-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure29-1 for load conditions. © 2011 Microchip Technology Inc. DS61143H-page 177

PIC32MX3XX/4XX TABLE 29-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Max. Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs PBCLK must operate at a minimum of 800 KHz. 400 kHz mode 1.3 — μs PBCLK must operate at a minimum of 3.2 MHz. 1 MHz mode(1) 0.5 — μs — IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs PBCLK must operate at a minimum of 800 KHz. 400 kHz mode 0.6 — μs PBCLK must operate at a minimum of 3.2 MHz. 1 MHz mode(1) 0.5 — μs — IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF. 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF. 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns — 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 μs — 1 MHz mode(1) 0 0.3 μs IS30 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — ns Start condition. 1 MHz mode(1) 250 — ns IS31 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — ns clock pulse is generated. 1 MHz mode(1) 250 — ns IS33 TSU:STO Stop Condition 100 kHz mode 4000 — ns Setup Time 400 kHz mode 600 — ns — 1 MHz mode(1) 600 — ns IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns — 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid from 100 kHz mode 0 3500 ns Clock 400 kHz mode 0 1000 ns — 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs The amount of time the bus 400 kHz mode 1.3 — μs must be free before a new 1 MHz mode(1) 0.5 — μs transmission can start. IS50 CB Bus Capacitive Loading — 400 pF — Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS61143H-page 178 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 29-34: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V VDD – 0.3 VDD + 0.3 — or 2.5 or 3.6 AD02 AVSS Module VSS Supply VSS — VSS + 0.3 V — Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.0 — AVDD V (Note 1) AD05a 2.5 — 3.6 V VREFH = AVDD (Note 3) AD06 VREFL Reference Voltage Low AVSS — VREFH – V (Note 1) 2.0 AD07 VREF Absolute Reference 2.0 — AVDD V (Note 3) Voltage (VREFH – VREFL) AD08 IREF Current Drain — 250 400 μA ADC operating — 3 μA ADC off Analog Input AD12 VINH-VINL Full-Scale Input Span VREFL — VREFH V — AD13 VINL Absolute VINL Input AVSS – 0.3 — AVDD/2 V — Voltage AD14 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + V — 0.3 AD15 — Leakage Current — ±0.001 ±0.610 μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10KΩ AD17 RIN Recommended — — 5K Ω (Note 1) Impedance of Analog Voltage Source ADC Accuracy – Measurements with External VREF+/VREF- AD20c Nr Resolution 10 data bits bits — AD21c INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD22c DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) AD23c GERR Gain Error — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD24n EOFF Offset Error — — <±1 LSb VINL = AVSS = 0V, AVDD = 3.3V AD25c — Monotonicity — — — — Guaranteed Note 1: These parameters are not characterized or tested in manufacturing. 2: With no missing codes. 3: These parameters are characterized, but not tested in manufacturing. 4: Characterized with 1 kHz sinewave. © 2011 Microchip Technology Inc. DS61143H-page 179

PIC32MX3XX/4XX TABLE 29-34: ADC MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical Max. Units Conditions No. ADC Accuracy – Measurements with Internal VREF+/VREF- AD20d Nr Resolution 10 data bits bits (Note 3) AD21d INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD22d DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2,3) AD23d GERR Gain Error — — <±4 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD24d EOFF Offset Error — — <±2 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD25d — Monotonicity — — — — Guaranteed Dynamic Performance AD31b SINAD Signal to Noise and 55 58.5 — dB (Notes 3, 4) Distortion AD34b ENOB Effective Number of Bits 9.0 9.5 — bits (Notes 3, 4) Note 1: These parameters are not characterized or tested in manufacturing. 2: With no missing codes. 3: These parameters are characterized, but not tested in manufacturing. 4: Characterized with 1 kHz sinewave. DS61143H-page 180 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX TABLE 29-35: 10-BIT ADC CONVERSION RATE PARAMETERS(2) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp TAD Sampling ADC Speed RS Max VDD ADC Channels Configuration Minimum Time Min 1 MIPS to 400 ksps(1) 65 ns 132 ns 500Ω 3.0V to 3.6V VREF- VREF+ ANx CHX SHA ADC Up to 400 ksps 200 ns 200 ns 5.0 kΩ 2.5V to 3.6V VREF- VREF+ or or AVSS AVDD ANx CHX SHA ADC ANx or VREF- Up to 300 ksps 200 ns 200 ns 5.0 kΩ 2.5V to 3.6V VREF- VREF+ or or AVSS AVDD ANx CHX SHA ADC ANx or VREF- Note 1: External VREF- and VREF+ pins must be used for correct operation. 2: These parameters are characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. DS61143H-page 181

PIC32MX3XX/4XX TABLE 29-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. Clock Parameters AD50 TAD Analog-to-Digital Clock Period 65 — — ns See Table29-35 and Note 2 AD51 TRC Analog-to-Digital Internal RC — 250 — ns See Note 3 Oscillator Period Conversion Rate AD55 TCONV Conversion Time — 12 TAD — — — AD56 FCNV Throughput Rate — — 1000 KSPS AVDD = 3.0V to 3.6V (Sampling Speed) — — 400 KSPS AVDD = 2.5V to 3.6V AD57 TSAMP Sample Time 1 TAD — — — TSAMP must be ≥ 132 ns. Timing Parameters AD60 TPCS Conversion Start from Sample — 1.0 TAD — — Auto-Convert Trigger Trigger (SSRC<2:0> = 111) not selected. See Note 3 AD61 TPSS Sample Start from Setting 0.5 TAD — 1.5 TAD — — Sample (SAMP) bit AD62 TCSS Conversion Completion to — 0.5 TAD — — See Note 3 Sample Start (ASAM = 1) AD63 TDPU Time to Stabilize Analog Stage — — 2 μs See Note 3 from Analog-to-Digital OFF to Analog-to-Digital ON Note 1: These parameters are characterized, but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: Characterized by design but not tested. DS61143H-page 182 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0>=01, SIMSAM=0, ASAM=0, SSRC<2:0>=000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP AD55 AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) of the “PIC32 Family Reference Manual”. 3 – Software clears ADxCON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One TAD for end of conversion. © 2011 Microchip Technology Inc. DS61143H-page 183

PIC32MX3XX/4XX FIGURE 29-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0>=01, SIMSAM=0, ASAM=1, SSRC<2:0>=111, SAMC<4:0>=00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 2 – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) of the “PIC32 Family Reference Manual”. 3 – Convert bit 9. 4 – Convert bit 8. 5 – Convert bit 0. 6 – One TAD for end of conversion. 7 – Begin conversion of next channel. 8 – Sample for time specified by SAMC<4:0>. DS61143H-page 184 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-20: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 29-37: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical Max. Units Conditions No. PS1 TdtV2wrH Data In Valid before WR or CS 20 — — ns — Inactive (setup time) PS2 TwrH2dtI WR or CS Inactive to Data – 40 — — ns — In Invalid (hold time) PS3 TrdL2dtV RD and CS Active to Data – — — 60 ns — Out Valid PS4 TrdH2dtI RD Active or CS Inactive to Data – 0 — 10 ns — Out Invalid PS5 Tcs CS Active Time TPB + 40 — — ns — PS6 TWR WR Active Time TPB + 25 — — ns — PS7 TRD RD Active Time TPB + 25 — — ns — Note 1: These parameters are characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. DS61143H-page 185

PIC32MX3XX/4XX FIGURE 29-21: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 PMA<13:18> Address PM6 PMD<7:0> AAdddrdersess<s7<:70:>0> DDaatata PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 29-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical Max. Units Conditions No. PM1 TLAT PMALL/PMALH Pulse Width — 1 TPB — — — PM2 TADSU Address Out Valid to PMALL/PMALH — 2 TPB — — — Invalid (address setup time) PM3 TADHOLD PMALL/PMALH Invalid to Address — 1 TPB — — — Out Invalid (address hold time) PM4 TAHOLD PMRD Inactive to Address Out 5 — — ns — Invalid (address hold time) PM5 TRD PMRD Pulse Width — 1 TPB — — — PM6 TDSU PMRD or PMENB Active to Data In 15 — — ns — Valid (data setup time) PM7 TDHOLD PMRD or PMENB Inactive to Data In — 80 — ns — Invalid (data hold time) Note 1: These parameters are characterized, but not tested in manufacturing. DS61143H-page 186 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PMA<13:18> Address PM2 + PM3 PMD<7:0> Address<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 29-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typical Max. Units Conditions No. PM11 TWR PMWR Pulse Width — 1 TPB — — — PM12 TDVSU Data Out Valid before PMWR or — 2 TPB — — — PMENB goes Inactive (data setup time) PM13 TDVHOLD PMWR or PMEMB Invalid to Data — 1 TPB — — — Out Invalid (data hold time) Note 1: These parameters are characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. DS61143H-page 187

PIC32MX3XX/4XX TABLE 29-40: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Characteristics(1) Min. Typ Max. Units Conditions No. USB313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB must be in this range for proper USB operation. USB315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V — USB316 VIHUSB Input High Voltage for USB Buffer 2.0 — — V — USB318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+ and D- must exceed this value while VCM is met. USB319 VCM Differential Common Mode Range 0.8 — 2.5 V — USB320 ZOUT Driver Output Impedance 28.0 — 44.0 Ω — USB321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kΩ load connected to 3.6V. USB322 VOH Voltage Output High 2.8 — 3.6 V 1.5 kΩ load connected to ground. Note 1: These parameters are characterized, but not tested in manufacturing. DS61143H-page 188 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX FIGURE 29-23: EJTAG TIMING CHARACTERISTICS T TCKeye T T TCKhigh TCKlow T rf TCK T rf TMS TDI TTsetup TThold Trf T rf TDO TRST* T TRST*low TTDOout TTDOzstate Defined Undefined T rf TABLE 29-41: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-Temp Param. Symbol Description(1) Min. Max. Units Conditions No. EJ1 TTCKCYC TCK Cycle Time 25 — ns — EJ2 TTCKHIGH TCK High Time 10 — ns — EJ3 TTCKLOW TCK Low Time 10 — ns — EJ4 TTSETUP TAP Signals Setup Time Before 5 — ns — Rising TCK EJ5 TTHOLD TAP Signals Hold Time After 3 — ns — Rising TCK EJ6 TTDOOUT TDO Output Delay Time from — 5 ns — Falling TCK EJ7 TTDOZSTATE TDO 3-State Delay Time from — 5 ns — Falling TCK EJ8 TTRSTLOW TRST Low Time 25 — ns — EJ9 TRF TAP Signals Rise/Fall Time, All — — ns — Input and Output Note 1: These parameters are characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. DS61143H-page 189

PIC32MX3XX/4XX NOTES: DS61143H-page 190 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX PIC32MX360F XXXXXXXXXX 512H-80I/PT XXXXXXXXXX e3 YYWWNNN 0510017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX PIC32MX360F XXXXXXXXXXXX 256L-80I/PT YYWWNNN e3 0510017 64-Lead QFN (9x9x0.9 mm) Example XXXXXXXXXX PIC32MX360F XXXXXXXXXX 512H-80I/MR XXXXXXXXXX e3 YYWWNNN 0510017 121-Lead XBGA (10x10x1.1 mm) Example XXXXXXXXXX PIC32MX460F XXXXXXXXXX 512L-80I/BG XXXXXXXXXX e3 YYWWNNN 0510017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. DS61143H-page 191

PIC32MX3XX/4XX 30.2 Package Details The following sections give the technical details of the packages. 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(cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)@/1 DS61143H-page 192 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS61143H-page 193

PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 194 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS61143H-page 195

PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 196 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX (cid:27)(cid:28)(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 e E E1 N b NOTE1 123 NOTE2 α c A φ β L A1 L1 A2 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 (cid:15)(cid:4)(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)(cid:5)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! 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DS61143H-page 197

PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 198 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS61143H-page 199

PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 200 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS61143H-page 201

PIC32MX3XX/4XX NOTES: DS61143H-page 202 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX APPENDIX A: REVISION HISTORY Revision F (June 2009) This revision includes minor typographical and Revision E (July 2008) formatting changes throughout the data sheet text. • Updated the PIC32MX340F128H features in Global changes include: Table1 to include 4 programmable DMA • Changed all instances of OSCI to OSC1 and channels. OSCO to OSC2 • Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE • Deleted registers in most sections, refer to the related section of the “PIC32 Family Reference Manual” (DS61132). The other changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, General Added a “Packages” column to Table1 and Table2. Purpose and USB 32-bit Flash Microcontrollers” Corrected all pin diagrams to update the following pin names. • Changed PGC1/EMUC1 to PGEC1 • Changed PGD1/EMUD1 to PGED1 • Changed PGC2/EMUC2 to PGEC2 • Changed PGD2/EMUD2 to PGED2 Shaded appropriate pins in each diagram to indicate which pins are 5V tolerant. Added 64-Lead QFN package pin diagrams, one for General Purpose and one for USB. Section1.0 “Device Overview” Reconstructed Figure1-1 to include Timers, ADC and RTCC in the block diagram. Section2.0 “Guidelines for Added a new section to the data sheet that provides the following information: Getting Started with 32-bit • Basic Connection Requirements Microcontrollers” • Capacitors • Master Clear Pin • ICSP™ Pins • External Oscillator Pins • Configuration of Analog and Digital Pins • Unused I/Os Section4.0 “Memory Updated the memory maps, Figure4-1 through Figure4-6. Organization” All summary peripheral register maps were relocated to Section4.0 “Memory Organization”. Section7.0 “Interrupt Removed the “Address” column from Table7-1. Controller” Section12.0 “I/O Ports” Added a second paragraph in Section12.1.3 “Analog Inputs” to clarify that all pins that share ANx functions are analog by default, because the AD1PCFG register has a default value of 0x0000. © 2011 Microchip Technology Inc. DS61143H-page 203

PIC32MX3XX/4XX TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section26.0 “Special Features” Modified bit names and locations in Register26-5 “DEVID: Device and Revision ID Register”. Replaced “TSTARTUP” with “TPU”, and “64-ms nominal delay” with “TPWRT”, in Section26.3.1 “On-Chip Regulator and POR”. The information that appeared in the Watchdog Timer and the Programming and Diagnostics sections of 61143E version of this data sheet has been incorporated into the Special Features section: • Section26.2 “Watchdog Timer (WDT)” • Section26.4 “Programming and Diagnostics” Section29.0 “Electrical Added the 64-Lead QFN package to Table29-3. Characteristics” Updated data in Table29-5. Updated data in Table29-7. Updated data in Table29-4, Table29-5, Table29-7 and Table29-8. Updated data in Table29-11. Added OS42 parameter to Table29-17. Replaced Table29-23. Replaced Table29-24. Replaced Table29-25. Updated Table29-36. Section30.0 “Packaging Added 64-Lead QFN package marking information to Section30.1 “Package Information” Marking Information”. Added the 64-Lead QFN (MR) package drawing and land pattern to Section30.2 “Package Details”. “Product Identification System” Added the MR package designator for the 64-Lead (9x9x0.9) QFN. DS61143H-page 204 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Revision G (April 2010) This revision also includes minor typographical and formatting changes throughout the data sheet text. The revision includes the following global update: Major updates are referenced by their respective • Added Note 2 to the shaded table that appears at section in the following table. the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, General Purpose Updated the crystal oscillator range to 3 MHz to 25 MHz (see Peripheral and USB 32-bit Flash Features:) Microcontrollers” Added the 121-pin Ball Grid Array (XBGA) pin diagram. Updated Table1: “PIC32MX General Purpose – Features” and Table2: “PIC32MX USB – Features” Added the following tables: - Table3: “Pin Names: PIC32MX320F128L, PIC32MX340F128L, and PIC32MX360F128L, and PIC32MX360F512L Devices”, - Table4: “Pin Names: PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices” Updated the following pins as 5V tolerant: - 64-pin QFN (USB): Pin 34 (VBUS), Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 64-pin TQFP (USB): Pin 34 (Vbus), Pin 36 (D-/RG3), Pin 37 (D+/RG2) and Pin 42 (IC1/RTCC/INT1/RD8) - 100-pin TQFP (USB): Pin 54 (VBUS), Pin 56 (D-/RG3) and Pin 57 (D+/RG2) Section1.0 “Device Overview” Updated the Pinout I/O Descriptions table to include the device pin numbers (see Table1-1) Section2.0 “Guidelines for Getting Updated the Ohm value for the low-ESR capacitor from less than 5 to less Started with 32-bit Microcontrollers” than 1 (see Section2.3.1 “Internal Regulator Mode”). Labeled the capacitor on the VCAP/VDDCORE pin as CEFC in Figure2-1. Changed 10 µF capacitor to CEFC capacitor in Section2.3 “Capacitor on Internal Voltage Regulator (VCAP/VCORE)”. Section4.0 “Memory Organization” Updated all register map tables to include the “All Resets” column. Separated the PORT register maps into individual tables (see Table4-21 through Table4-34). In addition, formatting changes were made to improve readability. Section12.0 “I/O Ports” Updated the second paragraph of Section12.1.2 “Digital Inputs” and removed Table 12-1. Section22.0 “10-bit Analog-to-Digital Updated the ADC Conversion Clock Period Block Diagram (see Figure22- Converter (ADC)” 2). Section26.0 “Special Features” Extensive updates were made to Section26.2 “Watchdog Timer (WDT)” and Section26.3 “On-Chip Voltage Regulator”. © 2011 Microchip Technology Inc. DS61143H-page 205

PIC32MX3XX/4XX TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section29.0 “Electrical Updated the Absolute Maximum Ratings and added Note 3. Characteristics” Added Thermal Packaging Characteristics for the 121-pin XBGA package (see Table29-3). Updated the conditions for parameters DC20, DC21, DC22 and DC23 in Table29-5. Updated the comments for parameter D321 (CEFC) in Table29-15. Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics, changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see Figure29-13). Section30.0 “Packaging Information” Added the 121-pin XBGA package marking information and package details. “Product Identification System” Added the definition for BG (121-lead 10x10x1.1 mm, XBGA). Added the definition for Speed. DS61143H-page 206 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Revision H (May 2011) The revision includes the following global update: • All references to VDDCORE/VCAP have been changed to: VCORE/VCAP • Added references to the new V-Temp temperature range: -40ºC to +105ºC This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in the following table. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description Section1.0 “Device Overview” Updated the VBUS description in Table 1-1: “Pinout I/O Descriptions”. Section4.0 “Memory Organization” Added Note 2 and changed the RIPL<2:0> bits to SRIPL<2:0> in the Interrupt Register Map tables (see Table4-2 through Table4-6. Added Note 2 to the Timer1-5 Register Map (see Table4-7). Updated the All Resets value for I2C1CON<15:0> and I2C2CON<15:0> in the I2C1 and I2C2 Register Map (see Table4-10). Updated the All Resets value for SPI1STAT<15:0> and SPI2STAT<15:0> in the SPI1 and SPI2 Register Map (see Table4-12). Updated the All Resets value for CM1CON<15:0> and CM2CON<15:0> in the Comparator Register Map (see Table4-17). Renamed the RCDIV<2:0> bits to FRCDIV<2:0> and the LOCK bit to SLOCK in the OSCCON register, and added Note 3 and the SYSKEYregister to the System Control Registers Map (see Table4-20). Updated the All Resets value for the PMSTAT register in the Parallel Master Port Register Map (see Table4-37). Updated the All Resets value for CHECON<15:0> and CHETAG<15:0> in the Prefetch Register Map (see Table4-39). Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2 register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively in the Device Configuration Word Summary (see Table4-41). Added Notes 1 through 4 to the USB Register Map (see Table4-43). Section5.0 “Flash Program Memory” Added a note on Flash LVD Delay and Example5-1. Section8.0 “Oscillator Configuration” Updated the PIC32MX3XX/4XX Family Clock Diagram (see Figure8-1). Section11.0 “USB On-The-Go (OTG)” Updated the PIC32MX3XX/4XX Family USB Interface Diagram (see Figure11-1). Section16.0 “Output Compare” Updated the Output Compare Module Block Diagram (see Figure16-1). Section22.0 “10-bit Analog-to-Digital Updated the ADC Conversion Clock Period Block Diagram (see Converter (ADC)” Figure22-2). Section26.0 “Special Features” Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2 register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively (see Register26-3). © 2011 Microchip Technology Inc. DS61143H-page 207

PIC32MX3XX/4XX TABLE A-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section29.0 “Electrical Added the new V-Temp temperature range (-40ºC to +105ºC) to the Characteristics” heading of all specification tables. Updated the Ambient temperature under bias, updated the Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added Voltage on VBUS with respect to Vss in Absolute Maximum Ratings. Added the characteristic, DC5a to Operating MIPS vs. Voltage (see Table29-1). Updated or added the following parameters to the Operating Current (IDD) DC Characteristics: DC20, DC23, DC24c, DC25d, DC26c (see Table29-5). Added the following parameters to the Idle Current (IIDLE) DC Characteristics: DC30c, DC31c, DC32c, DS33c, DC34c, DC35c, and DC36c (see Table29-6). Added the following parameters to the Power-down Current (IPD) DC Characteristics: DC40g, DC40h, DC40i, DC41g, DC41h, DC42g, DC42h, DC42i, DC43h, and DC43i (see Table29-7). Added the Brown-out Reset (BOR) Electrical Characteristics (see Table29-10). Removed all Conditions from the Program Memory DC Characteristics (see Table29-11). Removed the AC Characteristics voltage reference table (Table 29-15). Added Note 2 to the PLL Clock Timing Specifications (see Table29-18). Updated the OC/PWM Module Timing Characteristics (see Figure29-9). Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing Requirements (Master Mode) (see Table29-32). Added parameter numbers (AD13, AD14, and AD15) to the ADC Module Specifications (see Table29-34). Updated the 10-bit ADC Conversion Rate Parameters (see Table29-35). Updated parameter AD57 (TSAMP) in the Analog-to-Digital Conversion Timing Requirements (see Table29-36). Updated the Conditions for parameters USB313, USB318, and USB319 in the OTG Electrical Specifications (see Table29-40). Section30.0 “Packaging Information” Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) – 9x9x0.9 mm Body [QFN] packing diagram. Product Identification System Added the new V-Temp (V) temperature information. DS61143H-page 208 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX INDEX A M AC Characteristics............................................................161 Microchip Internet Web Site..............................................209 Internal RC Accuracy................................................163 MPLAB ASM30 Assembler, Linker, Librarian...................148 AC Electrical Specifications MPLAB Integrated Development Environment Software..147 Parallel Master Port Read Requirements.................186 MPLAB PM3 Device Programmer....................................150 Parallel Master Port Write Requirements..................187 MPLAB REAL ICE In-Circuit Emulator System................149 Parallel Slave Port Requirements.............................185 MPLINK Object Linker/MPLIB Object Librarian................148 Assembler P MPASM Assembler...................................................148 Packaging.........................................................................191 B Details.......................................................................192 Block Diagrams Marking.....................................................................191 ADC Module..............................................................123 PIC32 Family USB Interface Diagram..............................100 Comparator I/O Operating Modes.............................125 Pinout I/O Descriptions (table)............................................22 Comparator Voltage Reference................................127 Power-on Reset (POR) Connections for On-Chip Voltage Regulator.............138 and On-Chip Voltage Regulator...............................138 Input Capture............................................................107 R JTAG Compliant Application Showing Daisy-Chaining of Components........................139 Reader Response.............................................................210 Output Compare Module...........................................109 S Reset System..............................................................87 RTCC........................................................................121 Serial Peripheral Interface (SPI)...87, 97, 111, 119, 121, 130 Type B Timer................................................37, 95, 105 Software Simulator (MPLAB SIM)....................................149 UART........................................................................115 Special Features...............................................................131 WDT..........................................................................137 T Brown-out Reset (BOR) and On-Chip Voltage Regulator................................138 Timer1 Module..............................................89, 95, 103, 105 Timing Diagrams C 10-bit Analog-to-Digital Conversion (CHPS<1:0> = 01, C Compilers SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)..183 MPLAB C18..............................................................148 10-bit Analog-to-Digital Conversion (CHPS<1:0> = 01, Comparator SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, Operation..................................................................126 SAMC<4:0> = 00001).......................................184 Comparator Voltage Reference I2Cx Bus Data (Master Mode)..................................175 Configuring................................................................128 I2Cx Bus Data (Slave Mode)....................................177 CPU Module..................................................................31, 37 I2Cx Bus Start/Stop Bits (Master Mode)...................175 Customer Change Notification Service.............................209 I2Cx Bus Start/Stop Bits (Slave Mode).....................177 Customer Notification Service...........................................209 Input Capture (CAPx)...............................................169 Customer Support.............................................................209 OC/PWM..................................................................170 Output Compare (OCx)............................................169 D Parallel Master Port Write.................................186, 187 DC Characteristics............................................................152 Parallel Slave Port....................................................185 I/O Pin Input Specifications.......................................157 SPIx Master Mode (CKE = 0)...................................171 I/O Pin Output Specifications....................................158 SPIx Master Mode (CKE = 1)...................................172 Idle Current (IIDLE)....................................................154 SPIx Slave Mode (CKE = 0).....................................173 Operating Current (IDD).............................................153 SPIx Slave Mode (CKE = 1).....................................174 Power-Down Current (IPD)........................................155 Timer1, 2, 3, 4, 5 External Clock..............................167 Program Memory......................................................159 Transmission (8-bit or 9-bit Data).............................116 Temperature and Voltage Specifications..................152 UART Reception with Receive Overrun...................117 Development Support.......................................................147 Timing Requirements CLKO and I/O...........................................................164 E Timing Specifications Electrical Characteristics...................................................151 I2Cx Bus Data Requirements (Master Mode)...........175 AC.............................................................................161 I2Cx Bus Data Requirements (Slave Mode).............178 Errata..................................................................................19 Output Compare Requirements................................169 Simple OC/PWM Mode Requirements.....................170 F SPIx Master Mode (CKE = 0) Requirements............171 Flash Program Memory......................................................85 SPIx Master Mode (CKE = 1) Requirements............172 RTSP Operation..........................................................85 SPIx Slave Mode (CKE = 1) Requirements..............174 I V I/O Ports....................................................................101, 115 VCORE/VCAP Pin...............................................................138 Parallel I/O (PIO).......................................................102 Voltage Reference Specifications.....................................160 Internet Address................................................................209 Voltage Regulator (On-Chip)............................................138 © 2011 Microchip Technology Inc. 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PIC32MX3XX/4XX W Watchdog Timer Operation..................................................................137 WWW Address..................................................................209 WWW, On-Line Support......................................................19 DS61143H-page 210 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design • Development Systems Information Line resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQs), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2011 Microchip Technology Inc. DS61143H-page 211

PIC32MX3XX/4XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC32MX3XX/4XX Literature Number: DS61143H Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS61143H-page 212 © 2011 Microchip Technology Inc.

PIC32MX3XX/4XX Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 3XX F 512 H T -80 I/PT-XXX Examples: PIC32MX320F032H-40I/PT: Microchip Brand General purpose PIC32MX, Architecture 32KB program memory, Product Groups 64-pin, Industrial temperature, TQFP package. Flash Memory Family PIC32MX360F256L-80I/PT: Program Memory Size (KB) General purpose PIC32MX, Pin Count 256KB program memory, Tape and Reel Flag (if applicable) 100-pin, Industrial temperature, TQFP package. Speed Temperature Range Package Pattern Flash Memory Family Architecture MX = 32-bit RISC MCU core Product Groups 3XX= General purpose microcontroller family 4XX= USB Flash Memory Family F = Flash program memory Program Memory Size 32 = 32K 64 = 64K 128= 128K 256= 256K 512= 512K Speed 40 = 40 MHz 80 = 80 MHz Pin Count H = 64-pin L = 100-pin Temperature Range I = -40°C to +85°C (Industrial) V = -40°C to +105°C (V-Temp) Package PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) BG = 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample © 2011 Microchip Technology Inc. DS61143H-page 213

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