PIC32MX1XX/2XX 28/36/44-PIN 32-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog Operating Conditions Timers/Output Compare/Input Capture • 2.3V to 3.6V, -40ºC to +105ºC, DC to 40 MHz • Five General Purpose Timers: • 2.3V to 3.6V, -40ºC to +85ºC, DC to 50 MHz - Five 16-bit and up to two 32-bit Timers/Counters Core: 50 MHz/83 DMIPS MIPS32® M4K® • Five Output Compare (OC) modules • Five Input Capture (IC) modules • MIPS16e® mode for up to 40% smaller code size • Peripheral Pin Select (PPS) to allow function remap • Code-efficient (C and Assembly) architecture • Real-Time Clock and Calendar (RTCC) module • Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Communication Interfaces Clock Management • USB 2.0-compliant Full-speed OTG controller • 0.9% internal oscillator • Two UART modules (12.5 Mbps): • Programmable PLLs and oscillator clock sources - Supports LIN 2.0 protocols and IrDA® support • Fail-Safe Clock Monitor (FSCM) • Two 4-wire SPI modules (25 Mbps) • Independent Watchdog Timer • Two I2C modules (up to 1 Mbaud) with SMBus support • Fast wake-up and start-up • PPS to allow function remap Power Management • Parallel Master Port (PMP) • Low-power management modes (Sleep and Idle) Direct Memory Access (DMA) • Integrated Power-on Reset and Brown-out Reset • Four channels of hardware DMA with automatic data • 0.5 mA/MHz dynamic current (typical) size detection • 44 μA IPD current (typical) • Two additional channels dedicated for USB Audio Interface Features • Programmable Cyclic Redundancy Check (CRC) • Data communication: I2S, LJ, RJ, and DSP modes Input/Output • Control interface: SPI and I2C • 10 mA source/sink on all I/O pins and up to 14 mA on • Master clock: non-standard VOH - Generation of fractional clock frequencies • 5V-tolerant pins - Can be synchronized with USB clock • Selectable open drain, pull-ups, and pull-downs - Can be tuned in run-time • External interrupts on all I/O pins Advanced Analog Features Qualification and Class B Support • ADC Module: • AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned - 10-bit 1.1 Msps rate with one S&H • Class B Safety Library, IEC 60730 - Up to 10 analog inputs on 28-pin devices and 13 analog inputs on 44-pin devices Debugger Development Support • Flexible and independent ADC trigger sources • In-circuit and in-application programming • Charge Time Measurement Unit (CTMU): • 4-wire MIPS® Enhanced JTAG interface - Supports mTouch™ capacitive touch sensing • Unlimited program and six complex data breakpoints - Provides high-resolution time measurement (1 ns) • IEEE 1149.2-compatible (JTAG) boundary scan - On-chip temperature measurement capability • Comparators: - Up to three Analog Comparator modules - Programmable references with 32 voltage points Packages Type SOIC SSOP SPDIP QFN VTLA TQFP Pin Count 28 28 28 28 44 36 44 44 I/O Pins (up to) 21 21 21 21 34 25 34 34 Contact/Lead Pitch 1.27 0.65 0.100'' 0.65 0.65 0.50 0.50 0.80 Dimensions 17.90x7.50x2.65 10.2x5.3x2 1.365''x.285''x.135'' 6x6x0.9 8x8x0.9 5x5x0.9 6x6x0.9 10x10x1 Note: All dimensions are in millimeters (mm) unless specified.  2011-2016 Microchip Technology Inc. DS60001168J-page 1

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 1: PIC32MX1XX 28/36/44-PIN GENERAL PURPOSE FAMILY FEATURES Remappable Peripherals s) Device Pins (1)Program Memory (KB) Data Memory (KB) Remappable Pins (2)/Capture/Comparemers UART 2SPI/IS (3)External Interrupts Analog Comparators USB On-The-Go (OTG) 2IC PMP DMA Channels(Programmable/Dedicated) CTMU 0-bit 1 Msps ADC (Channel RTCC I/O Pins JTAG Packages Ti 1 SOIC, SSOP, PIC32MX110F016B 28 16+3 4 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y SPDIP, QFN PIC32MX110F016C 36 16+3 4 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA VTLA, PIC32MX110F016D 44 16+3 4 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP, QFN SOIC, SSOP, PIC32MX120F032B 28 32+3 8 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y SPDIP, QFN PIC32MX120F032C 36 32+3 8 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA VTLA, PIC32MX120F032D 44 32+3 8 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP, QFN SOIC, SSOP, PIC32MX130F064B 28 64+3 16 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y SPDIP, QFN PIC32MX130F064C 36 64+3 16 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA VTLA, PIC32MX130F064D 44 64+3 16 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP, QFN SOIC, SSOP, PIC32MX150F128B 28 128+3 32 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y SPDIP, QFN PIC32MX150F128C 36 128+3 32 24 5/5/5 2 2 5 3 N 2 Y 4/0 Y 12 Y 25 Y VTLA VTLA, PIC32MX150F128D 44 128+3 32 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP, QFN SOIC, SSOP, PIC32MX130F256B 28 256+3 16 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y SPDIP, QFN VTLA, PIC32MX130F256D 44 256+3 16 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP, QFN SOIC, SSOP, PIC32MX170F256B 28 256+3 64 20 5/5/5 2 2 5 3 N 2 Y 4/0 Y 10 Y 21 Y SPDIP, QFN VTLA, PIC32MX170F256D 44 256+3 64 32 5/5/5 2 2 5 3 N 2 Y 4/0 Y 13 Y 35 Y TQFP, QFN Note 1: This device features 3 KB of boot Flash memory. 2: Four out of five timers are remappable. 3: Four out of five external interrupts are remappable. DS60001168J-page 2  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 2: PIC32MX2XX 28/36/44-PIN USB FAMILY FEATURES Remappable Peripherals s) Device Pins (1)Program Memory (KB) Data Memory (KB) Remappable Pins (2)mers/Capture/Compare UART 2SPI/IS (3)External Interrupts Analog Comparators USB On-The-Go (OTG) 2IC PMP DMA Channels(Programmable/Dedicated) CTMU 0-bit 1 Msps ADC (Channel RTCC I/O Pins JTAG Packages Ti 1 SOIC, SSOP, PIC32MX210F016B 28 16+3 4 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y SPDIP, QFN PIC32MX210F016C 36 16+3 4 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 25 Y VTLA VTLA, PIC32MX210F016D 44 16+3 4 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP, QFN SOIC, SSOP, PIC32MX220F032B 28 32+3 8 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y SPDIP, QFN PIC32MX220F032C 36 32+3 8 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA VTLA, PIC32MX220F032D 44 32+3 8 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP, QFN SOIC, SSOP, PIC32MX230F064B 28 64+3 16 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y SPDIP, QFN PIC32MX230F064C 36 64+3 16 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA VTLA, PIC32MX230F064D 44 64+3 16 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP, QFN SOIC, SSOP, PIC32MX250F128B 28 128+3 32 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y SPDIP, QFN PIC32MX250F128C 36 128+3 32 23 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 12 Y 23 Y VTLA VTLA, PIC32MX250F128D 44 128+3 32 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP, QFN SOIC, SSOP, PIC32MX230F256B 28 256+3 16 20 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y SPDIP, QFN VTLA, PIC32MX230F256D 44 256+3 16 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP, QFN SOIC, SSOP, PIC32MX270F256B 28 256+3 64 19 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 9 Y 19 Y SPDIP, QFN VTLA, PIC32MX270F256D 44 256+3 64 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP, QFN VTLA, PIC32MX270F256DB(4) 44 256+3 64 31 5/5/5 2 2 5 3 Y 2 Y 4/2 Y 13 Y 33 Y TQFP, QFN Note 1: This device features 3 KB of boot Flash memory. 2: Four out of five timers are remappable. 3: Four out of five external interrupts are remappable. 4: This PIC32 device is targeted to specific audio software packages that are tracked for licensing royalty purposes. All peripherals and electrical characteristics are identical to their corresponding base part numbers.  2011-2016 Microchip Technology Inc. DS60001168J-page 3

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Pin Diagrams TABLE 3: PIN NAMES FOR 28-PIN GENERAL PURPOSE DEVICES 28-PIN SOIC, SPDIP, SSOP (TOP VIEW)(1,2,3) 1 28 1 28 1 28 SSOP SOIC SPDIP PIC32MX110F016B PIC32MX120F032B PIC32MX130F064B PIC32MX130F256B PIC32MX150F128B PIC32MX170F256B Pin # Full Pin Name Pin # Full Pin Name 1 MCLR 15 PGEC3/RPB6/PMD6/RB6 2 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 16 TDI/RPB7/CTED3/PMD5/INT0/RB7 3 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 17 TCK/RPB8/SCL1/CTED10/PMD4/RB8 4 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 18 TDO/RPB9/SDA1/CTED4/PMD3/RB9 5 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 19 VSS 6 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 20 VCAP 7 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 21 PGED2/RPB10/CTED11/PMD2/RB10 8 VSS 22 PGEC2/TMS/RPB11/PMD1/RB11 9 OSC1/CLKI/RPA2/RA2 23 AN12/PMD0/RB12 10 OSC2/CLKO/RPA3/PMA0/RA3 24 AN11/RPB13/CTPLS/PMRD/RB13 11 SOSCI/RPB4/RB4 25 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 12 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 26 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 13 VDD 27 AVSS 14 PGED3/RPB5/PMD7/RB5 28 AVDD Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: Shaded pins are 5V tolerant. DS60001168J-page 4  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 4: PIN NAMES FOR 28-PIN USB DEVICES 28-PIN SOIC, SPDIP, SSOP (TOP VIEW)(1,2,3) 1 28 1 28 1 28 SSOP SOIC SPDIP PIC32MX210F016B PIC32MX220F032B PIC32MX230F064B PIC32MX230F256B PIC32MX250F128B PIC32MX270F256B Pin # Full Pin Name Pin # Full Pin Name 1 MCLR 15 VBUS 2 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 16 TDI/RPB7/CTED3/PMD5/INT0/RB7 3 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 17 TCK/RPB8/SCL1/CTED10/PMD4/RB8 4 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 18 TDO/RPB9/SDA1/CTED4/PMD3/RB9 5 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 19 VSS 6 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 20 VCAP 7 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 21 PGED2/RPB10/D+/CTED11/RB10 8 VSS 22 PGEC2/RPB11/D-/RB11 9 OSC1/CLKI/RPA2/RA2 23 VUSB3V3 10 OSC2/CLKO/RPA3/PMA0/RA3 24 AN11/RPB13/CTPLS/PMRD/RB13 11 SOSCI/RPB4/RB4 25 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 12 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 26 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 13 VDD 27 AVSS 14 TMS/RPB5/USBID/RB5 28 AVDD Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more informa- tion. 3: Shaded pins are 5V tolerant.  2011-2016 Microchip Technology Inc. DS60001168J-page 5

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 5: PIN NAMES FOR 28-PIN GENERAL PURPOSE DEVICES 28-PIN QFN (TOP VIEW)(1,2,3.4) PIC32MX110F016B PIC32MX120F032B PIC32MX130F064B PIC32MX130F256B PIC32MX150F128B 28 1 PIC32MX170F256B Pin # Full Pin Name Pin # Full Pin Name 1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 15 TDO/RPB9/SDA1/CTED4/PMD3/RB9 2 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 16 VSS 3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 17 VCAP 4 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 18 PGED2/RPB10/CTED11/PMD2/RB10 5 VSS 19 PGEC2/TMS/RPB11/PMD1/RB11 6 OSC1/CLKI/RPA2/RA2 20 AN12/PMD0/RB12 7 OSC2/CLKO/RPA3/PMA0/RA3 21 AN11/RPB13/CTPLS/PMRD/RB13 8 SOSCI/RPB4/RB4 22 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 9 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 23 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 10 VDD 24 AVSS 11 PGED3/RPB5/PMD7/RB5 25 AVDD 12 PGEC3/RPB6/PMD6/RB6 26 MCLR 13 TDI/RPB7/CTED3/PMD5/INT0/RB7 27 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 14 TCK/RPB8/SCL1/CTED10/PMD4/RB8 28 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: Shaded pins are 5V tolerant. DS60001168J-page 6  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 6: PIN NAMES FOR 28-PIN USB DEVICES 28-PIN QFN (TOP VIEW)(1,2,3,4) PIC32MX210F016B PIC32MX220F032B PIC32MX230F064B PIC32MX230F256B PIC32MX250F128B 28 PIC32MX270F256B 1 Pin # Full Pin Name Pin # Full Pin Name 1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 15 TDO/RPB9/SDA1/CTED4/PMD3/RB9 2 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 16 VSS 3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 17 VCAP 4 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 18 PGED2/RPB10/D+/CTED11/RB10 5 VSS 19 PGEC2/RPB11/D-/RB11 6 OSC1/CLKI/RPA2/RA2 20 VUSB3V3 7 OSC2/CLKO/RPA3/PMA0/RA3 21 AN11/RPB13/CTPLS/PMRD/RB13 8 SOSCI/RPB4/RB4 22 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 9 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 23 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 10 VDD 24 AVSS 11 TMS/RPB5/USBID/RB5 25 AVDD 12 VBUS 26 MCLR 13 TDI/RPB7/CTED3/PMD5/INT0/RB7 27 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 14 TCK/RPB8/SCL1/CTED10/PMD4/RB8 28 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: Shaded pins are 5V tolerant.  2011-2016 Microchip Technology Inc. DS60001168J-page 7

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 7: PIN NAMES FOR 36-PIN GENERAL PURPOSE DEVICES 36-PIN VTLA (TOP VIEW)(1,2,3,5) PIC32MX110F016C PIC32MX120F032C PIC32MX130F064C PIC32MX150F128C 36 1 Pin # Full Pin Name Pin # Full Pin Name 1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 19 TDO/RPB9/SDA1/CTED4/PMD3/RB9 2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 20 RPC9/CTED7/RC9 3 PGED4(4)/AN6/RPC0/RC0 21 VSS 4 PGEC4(4)/AN7/RPC1/RC1 22 VCAP 5 VDD 23 VDD 6 VSS 24 PGED2/RPB10/CTED11/PMD2/RB10 7 OSC1/CLKI/RPA2/RA2 25 PGEC2/TMS/RPB11/PMD1/RB11 8 OSC2/CLKO/RPA3/PMA0/RA3 26 AN12/PMD0/RB12 9 SOSCI/RPB4/RB4 27 AN11/RPB13/CTPLS/PMRD/RB13 10 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 28 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 11 RPC3/RC3 29 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 12 VSS 30 AVSS 13 VDD 31 AVDD 14 VDD 32 MCLR 15 PGED3/RPB5/PMD7/RB5 33 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 16 PGEC3/RPB6/PMD6/RB6 34 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 17 TDI/RPB7/CTED3/PMD5/INT0/RB7 35 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 18 TCK/RPB8/SCL1/CTED10/PMD4/RB8 36 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: This pin function is not available on PIC32MX110F016C and PIC32MX120F032C devices. 5: Shaded pins are 5V tolerant. DS60001168J-page 8  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 8: PIN NAMES FOR 36-PIN USB DEVICES 36-PIN VTLA (TOP VIEW)(1,2,3,5) PIC32MX210F016C PIC32MX220F032C PIC32MX230F064C PIC32MX250F128C 36 1 Pin # Full Pin Name Pin # Full Pin Name 1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 19 TDO/RPB9/SDA1/CTED4/PMD3/RB9 2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 20 RPC9/CTED7/RC9 3 PGED4(4)/AN6/RPC0/RC0 21 VSS 4 PGEC4(4)/AN7/RPC1/RC1 22 VCAP 5 VDD 23 VDD 6 VSS 24 PGED2/RPB10/D+/CTED11/RB10 7 OSC1/CLKI/RPA2/RA2 25 PGEC2/RPB11/D-/RB11 8 OSC2/CLKO/RPA3/PMA0/RA3 26 VUSB3V3 9 SOSCI/RPB4/RB4 27 AN11/RPB13/CTPLS/PMRD/RB13 10 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 28 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 11 AN12/RPC3/RC3 29 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 12 VSS 30 AVSS 13 VDD 31 AVDD 14 VDD 32 MCLR 15 TMS/RPB5/USBID/RB5 33 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 16 VBUS 34 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 17 TDI/RPB7/CTED3/PMD5/INT0/RB7 35 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 18 TCK/RPB8/SCL1/CTED10/PMD4/RB8 36 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: This pin function is not available on PIC32MX210F016C and PIC32MX120F032C devices. 5: Shaded pins are 5V tolerant.  2011-2016 Microchip Technology Inc. DS60001168J-page 9

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 9: PIN NAMES FOR 44-PIN GENERAL PURPOSE DEVICES 44-PIN QFN (TOP VIEW)(1,2,3,5) PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX130F256D PIC32MX150F128D PIC32MX170F256D 44 1 Pin # Full Pin Name Pin # Full Pin Name 1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0 4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1 5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2 6 VSS 28 VDD 7 VCAP 29 VSS 8 PGED2/RPB10/CTED11/PMD2/RB10 30 OSC1/CLKI/RPA2/RA2 9 PGEC2/RPB11/PMD1/RB11 31 OSC2/CLKO/RPA3/RA3 10 AN12/PMD0/RB12 32 TDO/RPA8/PMA8/RA8 11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4 12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4 13 PGEC4(4)/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9 14 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 36 RPC3/RC3 15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4 16 AVSS 38 RPC5/PMA3/RC5 17 AVDD 39 VSS 18 MCLR 40 VDD 19 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 41 PGED3/RPB5/PMD7/RB5 20 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 42 PGEC3/RPB6/PMD6/RB6 21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices. 5: Shaded pins are 5V tolerant. DS60001168J-page 10  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 10: PIN NAMES FOR 44-PIN USB DEVICES 44-PIN QFN (TOP VIEW)(1,2,3,5) PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX230F256D PIC32MX250F128D PIC32MX270F256D 44 1 Pin # Full Pin Name Pin # Full Pin Name 1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0 4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1 5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2 6 VSS 28 VDD 7 VCAP 29 VSS 8 PGED2/RPB10/D+/CTED11/RB10 30 OSC1/CLKI/RPA2/RA2 9 PGEC2/RPB11/D-/RB11 31 OSC2/CLKO/RPA3/RA3 10 VUSB3V3 32 TDO/RPA8/PMA8/RA8 11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4 12 PGED4/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4 13 PGEC4/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9 14 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 36 AN12/RPC3/RC3 15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4 16 AVSS 38 RPC5/PMA3/RC5 17 AVDD 39 VSS 18 MCLR 40 VDD 19 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 41 RPB5/USBID/RB5 20 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 42 VBUS 21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices. 5: Shaded pins are 5V tolerant.  2011-2016 Microchip Technology Inc. DS60001168J-page 11

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 11: PIN NAMES FOR 44-PIN GENERAL PURPOSE DEVICES 44-PIN TQFP (TOP VIEW)(1,2,3,5) PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX130F256D PIC32MX150F128D PIC32MX170F256D 44 1 Pin # Full Pin Name Pin # Full Pin Name 1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0 4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1 5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2 6 VSS 28 VDD 7 VCAP 29 VSS 8 PGED2/RPB10/CTED11/PMD2/RB10 30 OSC1/CLKI/RPA2/RA2 9 PGEC2/RPB11/PMD1/RB11 31 OSC2/CLKO/RPA3/RA3 10 AN12/PMD0/RB12 32 TDO/RPA8/PMA8/RA8 11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4 12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4 13 PGEC4(4)/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9 14 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 36 RPC3/RC3 15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4 16 AVSS 38 RPC5/PMA3/RC5 17 AVDD 39 VSS 18 MCLR 40 VDD 19 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 41 PGED3/RPB5/PMD7/RB5 20 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 42 PGEC3/RPB6/PMD6/RB6 21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices. 5: Shaded pins are 5V tolerant. DS60001168J-page 12  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 12: PIN NAMES FOR 44-PIN USB DEVICES 44-PIN TQFP (TOP VIEW)(1,2,3,5) PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX230F256D PIC32MX250F128D PIC32MX270F256D 44 1 Pin # Full Pin Name Pin # Full Pin Name 1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0 4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1 5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2 6 VSS 28 VDD 7 VCAP 29 VSS 8 PGED2/RPB10/D+/CTED11/RB10 30 OSC1/CLKI/RPA2/RA2 9 PGEC2/RPB11/D-/RB11 31 OSC2/CLKO/RPA3/RA3 10 VUSB3V3 32 TDO/RPA8/PMA8/RA8 11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4 12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4 13 PGEC4(4)/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9 14 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 36 AN12/RPC3/RC3 15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4 16 AVSS 38 RPC5/PMA3/RC5 17 AVDD 39 VSS 18 MCLR 40 VDD 19 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 41 RPB5/USBID/RB5 20 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 42 VBUS 21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: This pin function is not available on PIC32MX210F016D and PIC32MX220F032D devices. 5: Shaded pins are 5V tolerant.  2011-2016 Microchip Technology Inc. DS60001168J-page 13

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 13: PIN NAMES FOR 44-PIN GENERAL PURPOSE DEVICES 44-PIN VTLA (TOP VIEW)(1,2,3,5) PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX130F256D PIC32MX150F128D PIC32MX170F256D 44 1 Pin # Full Pin Name Pin # Full Pin Name 1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0 4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1 5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2 6 VSS 28 VDD 7 VCAP 29 VSS 8 PGED2/RPB10/CTED11/PMD2/RB10 30 OSC1/CLKI/RPA2/RA2 9 PGEC2/RPB11/PMD1/RB11 31 OSC2/CLKO/RPA3/RA3 10 AN12/PMD0/RB12 32 TDO/RPA8/PMA8/RA8 11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4 12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4 13 PGEC4(4)/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9 14 CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 36 RPC3/RC3 15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4 16 AVSS 38 RPC5/PMA3/RC5 17 AVDD 39 VSS 18 MCLR 40 VDD 19 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 41 PGED3/RPB5/PMD7/RB5 20 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 42 PGEC3/RPB6/PMD6/RB6 21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: This pin function is not available on PIC32MX110F016D and PIC32MX120F032D devices. 5: Shaded pins are 5V tolerant. DS60001168J-page 14  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 14: PIN NAMES FOR 44-PIN USB DEVICES 44-PIN VTLA (TOP VIEW)(1,2,3,5) PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX230F256D PIC32MX250F128D PIC32MX270F256D 44 1 Pin # Full Pin Name Pin # Full Pin Name 1 RPB9/SDA1/CTED4/PMD3/RB9 23 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 2 RPC6/PMA1/RC6 24 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 3 RPC7/PMA0/RC7 25 AN6/RPC0/RC0 4 RPC8/PMA5/RC8 26 AN7/RPC1/RC1 5 RPC9/CTED7/PMA6/RC9 27 AN8/RPC2/PMA2/RC2 6 VSS 28 VDD 7 VCAP 29 VSS 8 PGED2/RPB10/D+/CTED11/RB10 30 OSC1/CLKI/RPA2/RA2 9 PGEC2/RPB11/D-/RB11 31 OSC2/CLKO/RPA3/RA3 10 VUSB3V3 32 TDO/RPA8/PMA8/RA8 11 AN11/RPB13/CTPLS/PMRD/RB13 33 SOSCI/RPB4/RB4 12 PGED4(4)/TMS/PMA10/RA10 34 SOSCO/RPA4/T1CK/CTED9/RA4 13 PGEC4(4)/TCK/CTED8/PMA7/RA7 35 TDI/RPA9/PMA9/RA9 14 CVREFOUT/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 36 AN12/RPC3/RC3 15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 37 RPC4/PMA4/RC4 16 AVSS 38 RPC5/PMA3/RC5 17 AVDD 39 VSS 18 MCLR 40 VDD 19 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 41 RPB5/USBID/RB5 20 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 42 VBUS 21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 43 RPB7/CTED3/PMD5/INT0/RB7 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 44 RPB8/SCL1/CTED10/PMD4/RB8 Note 1: The RPn pins can be used by remappable peripherals. See Table1 for the available peripherals and Section11.3 “Peripheral Pin Select” for restrictions. 2: Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section11.0 “I/O Ports” for more information. 3: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: This pin function is not available on PIC32MX210F016D and PIC32MX220F032D devices. 5: Shaded pins are 5V tolerant.  2011-2016 Microchip Technology Inc. DS60001168J-page 15

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Table of Contents 1.0 Device Overview........................................................................................................................................................................19 2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................27 3.0 CPU............................................................................................................................................................................................33 4.0 Memory Organization.................................................................................................................................................................37 5.0 Flash Program Memory..............................................................................................................................................................53 6.0 Resets........................................................................................................................................................................................59 7.0 Interrupt Controller.....................................................................................................................................................................63 8.0 Oscillator Configuration..............................................................................................................................................................73 9.0 Direct Memory Access (DMA) Controller...................................................................................................................................83 10.0 USB On-The-Go (OTG)............................................................................................................................................................103 11.0 I/O Ports...................................................................................................................................................................................127 12.0 Timer1......................................................................................................................................................................................143 13.0 Timer2/3, Timer4/5...................................................................................................................................................................147 14.0 Watchdog Timer (WDT)...........................................................................................................................................................153 15.0 Input Capture............................................................................................................................................................................157 16.0 Output Compare.......................................................................................................................................................................161 17.0 Serial Peripheral Interface (SPI)...............................................................................................................................................165 18.0 Inter-Integrated Circuit (I2C).....................................................................................................................................................173 19.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................181 20.0 Parallel Master Port (PMP).......................................................................................................................................................189 21.0 Real-Time Clock and Calendar (RTCC)...................................................................................................................................199 22.0 10-bit Analog-to-Digital Converter (ADC).................................................................................................................................209 23.0 Comparator..............................................................................................................................................................................219 24.0 Comparator Voltage Reference (CVREF)..................................................................................................................................223 25.0 Charge Time Measurement Unit (CTMU) ...............................................................................................................................227 26.0 Power-Saving Features ...........................................................................................................................................................233 27.0 Special Features......................................................................................................................................................................239 28.0 Instruction Set..........................................................................................................................................................................251 29.0 Development Support...............................................................................................................................................................253 30.0 Electrical Characteristics..........................................................................................................................................................257 31.0 50 MHz Electrical Characteristics.............................................................................................................................................301 32.0 DC and AC Device Characteristics Graphs..............................................................................................................................307 33.0 Packaging Information..............................................................................................................................................................311 The Microchip Web Site.....................................................................................................................................................................341 Customer Change Notification Service..............................................................................................................................................341 Customer Support..............................................................................................................................................................................341 Product Identification System.............................................................................................................................................................342 DS60001168J-page 16  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011-2016 Microchip Technology Inc. DS60001168J-page 17

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: To access the following documents, refer to the Documentation > Reference Manuals section of the Microchip PIC32 website: http://www.microchip.com/pic32 • Section 1. “Introduction” (DS60001127) • Section 2. “CPU” (DS60001113) • Section 3. “Memory Organization” (DS60001115) • Section 5. “Flash Program Memory” (DS60001121) • Section 6. “Oscillator Configuration” (DS60001112) • Section 7. “Resets” (DS60001118) • Section 8. “Interrupt Controller” (DS60001108) • Section 9. “Watchdog Timer and Power-up Timer” (DS60001114) • Section 10. “Power-Saving Features” (DS60001130) • Section 12. “I/O Ports” (DS60001120) • Section 13. “Parallel Master Port (PMP)” (DS60001128) • Section 14. “Timers” (DS60001105) • Section 15. “Input Capture” (DS60001122) • Section 16. “Output Compare” (DS60001111) • Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104) • Section 19. “Comparator” (DS60001110) • Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109) • Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107) • Section 23. “Serial Peripheral Interface (SPI)” (DS60001106) • Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116) • Section 27. “USB On-The-Go (OTG)” (DS60001126) • Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125) • Section 31. “Direct Memory Access (DMA) Controller” (DS60001117) • Section 32. “Configuration” (DS60001124) • Section 33. “Programming and Diagnostics” (DS60001129) • Section 37. “Charge Time Measurement Unit (CTMU)” (DS60001167) DS60001168J-page 18  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX1XX/2XX 28/36/44-pin Family devices. Note: This data sheet summarizes the features Figure1-1 illustrates a general block diagram of the of the PIC32MX1XX/2XX 28/36/44-pin core and peripheral modules in the PIC32MX1XX/2XX Family of devices. It is not intended to be 28/36/44-pin Family of devices. a comprehensive reference source. To complement the information in this data Table1-1 lists the functions of the various pins shown sheet, refer to documents listed in the in the pinout diagrams. Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). FIGURE 1-1: BLOCK DIAGRAM VCAP OSC2/CLKO OSC/SOSC OSC1/CLKI Oscillators Power-up VDD, VSS Timer FRC/LPRC MCLR Oscillators Voltage Oscillator Regulator Start-up Timer PLL Power-on Precision Dividers Band Gap Reset Reference PLL-USB Watchdog USBCLK Timer SYSCLK Brown-out Timing Generation PBCLK Reset Peripheral Bus Clocked by SYSCLK CTMU PORTA Timer1-Timer5 Priority JTAG Interrupt BSCAN Controller PWM PORTB LK OC1-OC5 C C EJTAG INT USB DMA ICD 32 y PB b MIPS32® M4K® ed IC1-IC5 PORTC CPU Core ck o 32 IS 32 DS 32 32 32 32 al Bus Cl SPI1-SPI2 Remappable er Pins Bus Matrix eriph P 32 32 I2C1-I2C2 32 32 Peripheral Bridge Data RAM PMP 10-bit ADC UART1-UART2 er Progra3m2- Fbilta Wshi dMeemory Flashontroll RTCC C Comparators 1-3 Note: Some features are not available on all devices. Refer to the family features tables (Table1 and Table2) for availability.  2011-2016 Microchip Technology Inc. DS60001168J-page 19

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) 28-pin 44-pin Pin Buffer Pin Name 28-pin SSOP/ 36-pin QFN/ Type Type Description QFN SPDIP/ VTLA TQFP/ SOIC VTLA AN0 27 2 33 19 I Analog Analog input channels. AN1 28 3 34 20 I Analog AN2 1 4 35 21 I Analog AN3 2 5 36 22 I Analog AN4 3 6 1 23 I Analog AN5 4 7 2 24 I Analog AN6 — — 3 25 I Analog AN7 — — 4 26 I Analog AN8 — — — 27 I Analog AN9 23 26 29 15 I Analog AN10 22 25 28 14 I Analog AN11 21 24 27 11 I Analog 26(2) 10(2) AN12 20(2) 23(2) I Analog 11(3) 36(3) CLKI 6 9 7 30 I ST/CMOS External clock source input. Always associated with OSC1 pin function. CLKO 7 10 8 31 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 6 9 7 30 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 7 10 8 31 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI 8 11 9 33 I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. SOSCO 9 12 10 34 O — 32.768 kHz low-power oscillator crystal output. REFCLKI PPS PPS PPS PPS I ST Reference Input Clock REFCLKO PPS PPS PPS PPS O — Reference Output Clock IC1 PPS PPS PPS PPS I ST Capture Inputs 1-5 IC2 PPS PPS PPS PPS I ST IC3 PPS PPS PPS PPS I ST IC4 PPS PPS PPS PPS I ST IC5 PPS PPS PPS PPS I ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS60001168J-page 20  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin 44-pin Pin Buffer Pin Name 28-pin SSOP/ 36-pin QFN/ Type Type Description QFN SPDIP/ VTLA TQFP/ SOIC VTLA OC1 PPS PPS PPS PPS O — Output Compare Output 1 OC2 PPS PPS PPS PPS O — Output Compare Output 2 OC3 PPS PPS PPS PPS O — Output Compare Output 3 OC4 PPS PPS PPS PPS O — Output Compare Output 4 OC5 PPS PPS PPS PPS O — Output Compare Output 5 OCFA PPS PPS PPS PPS I ST Output Compare Fault A Input OCFB PPS PPS PPS PPS I ST Output Compare Fault B Input INT0 13 16 17 43 I ST External Interrupt 0 INT1 PPS PPS PPS PPS I ST External Interrupt 1 INT2 PPS PPS PPS PPS I ST External Interrupt 2 INT3 PPS PPS PPS PPS I ST External Interrupt 3 INT4 PPS PPS PPS PPS I ST External Interrupt 4 RA0 27 2 33 19 I/O ST PORTA is a bidirectional I/O port RA1 28 3 34 20 I/O ST RA2 6 9 7 30 I/O ST RA3 7 10 8 31 I/O ST RA4 9 12 10 34 I/O ST RA7 — — — 13 I/O ST RA8 — — — 32 I/O ST RA9 — — — 35 I/O ST RA10 — — — 12 I/O ST RB0 1 4 35 21 I/O ST PORTB is a bidirectional I/O port RB1 2 5 36 22 I/O ST RB2 3 6 1 23 I/O ST RB3 4 7 2 24 I/O ST RB4 8 11 9 33 I/O ST RB5 11 14 15 41 I/O ST RB6 12(2) 15(2) 16(2) 42(2) I/O ST RB7 13 16 17 43 I/O ST RB8 14 17 18 44 I/O ST RB9 15 18 19 1 I/O ST RB10 18 21 24 8 I/O ST RB11 19 22 25 9 I/O ST RB12 20(2) 23(2) 26(2) 10(2) I/O ST RB13 21 24 27 11 I/O ST RB14 22 25 28 14 I/O ST RB15 23 26 29 15 I/O ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only.  2011-2016 Microchip Technology Inc. DS60001168J-page 21

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin 44-pin Pin Buffer Pin Name 28-pin SSOP/ 36-pin QFN/ Type Type Description QFN SPDIP/ VTLA TQFP/ SOIC VTLA RC0 — — 3 25 I/O ST PORTC is a bidirectional I/O port RC1 — — 4 26 I/O ST RC2 — — — 27 I/O ST RC3 — — 11 36 I/O ST RC4 — — — 37 I/O ST RC5 — — — 38 I/O ST RC6 — — — 2 I/O ST RC7 — — — 3 I/O ST RC8 — — — 4 I/O ST RC9 — — 20 5 I/O ST T1CK 9 12 10 34 I ST Timer1 external clock input T2CK PPS PPS PPS PPS I ST Timer2 external clock input T3CK PPS PPS PPS PPS I ST Timer3 external clock input T4CK PPS PPS PPS PPS I ST Timer4 external clock input T5CK PPS PPS PPS PPS I ST Timer5 external clock input U1CTS PPS PPS PPS PPS I ST UART1 clear to send U1RTS PPS PPS PPS PPS O — UART1 ready to send U1RX PPS PPS PPS PPS I ST UART1 receive U1TX PPS PPS PPS PPS O — UART1 transmit U2CTS PPS PPS PPS PPS I ST UART2 clear to send U2RTS PPS PPS PPS PPS O — UART2 ready to send U2RX PPS PPS PPS PPS I ST UART2 receive U2TX PPS PPS PPS PPS O — UART2 transmit SCK1 22 25 28 14 I/O ST Synchronous serial clock input/output for SPI1 SDI1 PPS PPS PPS PPS I ST SPI1 data in SDO1 PPS PPS PPS PPS O — SPI1 data out SS1 PPS PPS PPS PPS I/O ST SPI1 slave synchronization or frame pulse I/O SCK2 23 26 29 15 I/O ST Synchronous serial clock input/output for SPI2 SDI2 PPS PPS PPS PPS I ST SPI2 data in SDO2 PPS PPS PPS PPS O — SPI2 data out SS2 PPS PPS PPS PPS I/O ST SPI2 slave synchronization or frame pulse I/O SCL1 14 17 18 44 I/O ST Synchronous serial clock input/output for I2C1 Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS60001168J-page 22  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin 44-pin Pin Buffer Pin Name 28-pin SSOP/ 36-pin QFN/ Type Type Description QFN SPDIP/ VTLA TQFP/ SOIC VTLA SDA1 15 18 19 1 I/O ST Synchronous serial data input/output for I2C1 SCL2 4 7 2 24 I/O ST Synchronous serial clock input/output for I2C2 SDA2 3 6 1 23 I/O ST Synchronous serial data input/output for I2C2 19(2) 22(2) 25(2) TMS 12 I ST JTAG Test mode select pin 11(3) 14(3) 15(3) TCK 14 17 18 13 I ST JTAG test clock input pin TDI 13 16 17 35 O — JTAG test data input pin TDO 15 18 19 32 O — JTAG test data output pin RTCC 4 7 2 24 O ST Real-Time Clock alarm output CVREF- 28 3 34 20 I Analog Comparator Voltage Reference (low) CVREF+ 27 2 33 19 I Analog Comparator Voltage Reference (high) CVREFOUT 22 25 28 14 O Analog Comparator Voltage Reference output C1INA 4 7 2 24 I Analog Comparator Inputs C1INB 3 6 1 23 I Analog C1INC 2 5 36 22 I Analog C1IND 1 4 35 21 I Analog C2INA 2 5 36 22 I Analog C2INB 1 4 35 21 I Analog C2INC 4 7 2 24 I Analog C2IND 3 6 1 23 I Analog C3INA 23 26 29 15 I Analog C3INB 22 25 28 14 I Analog C3INC 27 2 33 19 I Analog C3IND 1 4 35 21 I Analog C1OUT PPS PPS PPS PPS O — Comparator Outputs C2OUT PPS PPS PPS PPS O — C3OUT PPS PPS PPS PPS O — Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only.  2011-2016 Microchip Technology Inc. DS60001168J-page 23

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin 44-pin Pin Buffer Pin Name 28-pin SSOP/ 36-pin QFN/ Type Type Description QFN SPDIP/ VTLA TQFP/ SOIC VTLA PMA0 7 10 8 3 I/O TTL/ST Parallel Master Port Address bit 0 input (Buffered Slave modes) and output (Master modes) PMA1 9 12 10 2 I/O TTL/ST Parallel Master Port Address bit 1 input (Buffered Slave modes) and output (Master modes) PMA2 — — 27 O — Parallel Master Port address PMA3 — — 38 O — (Demultiplexed Master modes) PMA4 — — 37 O — PMA5 — — 4 O — PMA6 — — 5 O — PMA7 — — 13 O — PMA8 — — 32 O — PMA9 — — 35 O — PMA10 — — 12 O — PMCS1 23 26 29 15 O — Parallel Master Port Chip Select 1 strobe 20(2) 23(2) 26(2) 10(2) Parallel Master Port data (Demultiplexed PMD0 I/O TTL/ST 1(3) 4(3) 35(3) 21(3) Master mode) or address/data 19(2) 22(2) 25(2) 9(2) (Multiplexed Master modes) PMD1 I/O TTL/ST 2(3) 5(3) 36(3) 22(3) 18(2) 21(2) 24(2) 8(2) PMD2 I/O TTL/ST 3(3) 6(3) 1(3) 23(3) PMD3 15 18 19 1 I/O TTL/ST PMD4 14 17 18 44 I/O TTL/ST PMD5 13 16 17 43 I/O TTL/ST PMD6 12(2) 15(2) 16(2) 42(2) I/O TTL/ST 28(3) 3(3) 34(3) 20(3) PMD7 11(2) 14(2) 15(2) 41(2) I/O TTL/ST 27(3) 2(3) 33(3) 19(3) PMRD 21 24 27 11 O — Parallel Master Port read strobe 22(2) 25(2) 28(2) 14(2) PMWR O — Parallel Master Port write strobe 4(3) 7(3) 2(3) 24(3) VBUS 12(3) 15(3) 16(3) 42(3) I Analog USB bus power monitor VUSB3V3 20(3) 23(3) 26(3) 10(3) P — USB internal transceiver supply. This pin must be connected to VDD. VBUSON 22(3) 25(3) 28(3) 14(3) O — USB Host and OTG bus power control output D+ 18(3) 21(3) 24(3) 8(3) I/O Analog USB D+ D- 19(3) 22(3) 25(3) 9(3) I/O Analog USB D- Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS60001168J-page 24  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin 44-pin Pin Buffer Pin Name 28-pin SSOP/ 36-pin QFN/ Type Type Description QFN SPDIP/ VTLA TQFP/ SOIC VTLA USBID 11(3) 14(3) 15(3) 41(3) I ST USB OTG ID detect CTED1 27 2 33 19 I ST CTMU External Edge Input CTED2 28 3 34 20 I ST CTED3 13 16 17 43 I ST CTED4 15 18 19 1 I ST CTED5 22 25 28 14 I ST CTED6 23 26 29 15 I ST CTED7 — — 20 5 I ST CTED8 — — — 13 I ST CTED9 9 12 10 34 I ST CTED10 14 17 18 44 I ST CTED11 18 21 24 8 I ST CTED12 2 5 36 22 I ST CTED13 3 6 1 23 I ST CTPLS 21 24 27 11 O — CTMU Pulse Output PGED1 1 4 35 21 I/O ST Data I/O pin for Programming/Debugging Communication Channel 1 PGEC1 2 5 36 22 I ST Clock input pin for Programming/Debugging Communication Channel 1 PGED2 18 21 24 8 I/O ST Data I/O pin for Programming/Debugging Communication Channel 2 PGEC2 19 22 25 9 I ST Clock input pin for Programming/Debugging Communication Channel 2 11(2) 14(2) 15(2) 41(2) Data I/O pin for Programming/Debugging PGED3 I/O ST 27(3) 2(3) 33(3) 19(3) Communication Channel 3 12(2) 15(2) 16(2) 42(2) Clock input pin for Programming/ PGEC3 I ST 28(3) 3(3) 34(3) 20(3) Debugging Communication Channel 3 PGED4 — — 3 12 Data I/O pin for Programming/Debugging I/O ST Communication Channel 4 PGEC4 — — 4 13 Clock input pin for Programming/ I ST Debugging Communication Channel 4 Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only.  2011-2016 Microchip Technology Inc. DS60001168J-page 25

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 28-pin 44-pin Pin Buffer Pin Name 28-pin SSOP/ 36-pin QFN/ Type Type Description QFN SPDIP/ VTLA TQFP/ SOIC VTLA MCLR 26 1 32 18 I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD 25 28 31 17 P — Positive supply for analog modules. This pin must be connected at all times. AVSS 24 27 30 16 P — Ground reference for analog modules VDD 10 13 5, 13, 14, 28, 40 P — Positive supply for peripheral logic and 23 I/O pins VCAP 17 20 22 7 P — CPU logic filter capacitor connection VSS 5, 16 8, 19 6, 12, 21 6, 29, 39 P — Ground reference for logic and I/O pins. This pin must be connected at all times. VREF+ 27 2 33 19 I Analog Analog voltage reference (high) input VREF- 28 3 34 20 I Analog Analog voltage reference (low) input Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS60001168J-page 26  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 32-BIT MCUs The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. Note: This data sheet summarizes the features See Figure2-1. of the PIC32MX1XX/2XX 28/36/44-pin Consider the following criteria when using decoupling Family of devices. It is not intended to be capacitors: a comprehensive reference source. To complement the information in this data • Value and type of capacitor: A value of 0.1 µF sheet, refer to the documents listed in the (100 nF), 10-20V is recommended. The capacitor Documentation > Reference Manual should be a low Equivalent Series Resistance section of the Microchip PIC32 web site (low-ESR) capacitor and have resonance fre- (www.microchip.com/pic32). quency in the range of 20MHz and higher. It is further recommended that ceramic capacitors be 2.1 Basic Connection Requirements used. • Placement on the printed circuit board: The Getting started with the PIC32MX1XX/2XX 28/36/44- decoupling capacitors should be placed as close pin Family of 32-bit Microcontrollers (MCUs) requires to the pins as possible. It is recommended that attention to a minimal set of device pin connections the capacitors be placed on the same side of the before proceeding with development. The following is a board as the device. If space is constricted, the list of pin names, which must always be connected: capacitor can be placed on another layer on the • All VDD and VSS pins (see 2.2“Decoupling PCB using a via; however, ensure that the trace Capacitors”) length from the pin to the capacitor is within one- • All AVDD and AVSS pins, even if the ADC module quarter inch (6mm) in length. is not used (see 2.2“Decoupling Capacitors”) • Handling high frequency noise: If the board is • VCAP pin (see 2.3“Capacitor on Internal experiencing high frequency noise, upward of Voltage Regulator (VCAP)”) tens of MHz, add a second ceramic-type capacitor • MCLR pin (see 2.4“Master Clear (MCLR) Pin”) in parallel to the above described decoupling capacitor. The value of the second capacitor can • PGECx/PGEDx pins, used for In-Circuit Serial be in the range of 0.01µF to 0.001µF. Place this Programming™ (ICSP™) and debugging pur- second capacitor next to the primary decoupling poses (see 2.5“ICSP Pins”) capacitor. In high-speed circuit designs, consider • OSC1 and OSC2 pins, when external oscillator implementing a decade pair of capacitances as source is used (see 2.7“External Oscillator close to the power and ground pins as possible. Pins”) For example, 0.1 µF in parallel with 0.001 µF. The following pins may be required: • Maximizing performance: On the board layout • VREF+/VREF- pins – used when external voltage from the power supply circuit, run the power and reference for the ADC module is implemented return traces to the decoupling capacitors first, and then to the device pins. This ensures that the Note: The AVDD and AVSS pins must be con- decoupling capacitors are first in the power chain. nected, regardless of ADC use and the Equally important is to keep the trace length ADC voltage reference source. between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.  2011-2016 Microchip Technology Inc. DS60001168J-page 27

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 2-1: RECOMMENDED 2.4 Master Clear (MCLR) Pin MINIMUM CONNECTION The MCLR pin provides two specific device functions: Tantalum or 0.1 µF VDD ceramic 10 µF Ceramic • Device Reset ESR  3(3) • Device programming and debugging 10K R1 CAP VDD VSS Pulling The MCLR pin low generates a device Reset. MCLR V Figure2-2 illustrates a typical MCLR circuit. During 1K device programming and debugging, the resistance C VUSB3V3(1) and capacitance that can be added to the pin must 0.1 µF be considered. Device programmers and debuggers PIC32 VDD drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must VSS VSS not be adversely affected. Therefore, specific values 0.1 µF of R and C will need to be adjusted based on the Ceramic 0.1 µF VDD D S application and PCB requirements. Ceramic VD VS DD SS A A V V For example, as illustrated in Figure2-2, it is Connect(2) recommended that the capacitor C, be isolated from 0.1 µF 0.1 µF the MCLR pin during programming and debugging Ceramic Ceramic operations. L1(2) Place the components illustrated in Figure2-2 within one-quarter inch (6mm) from the MCLR pin. Note 1: If the USB module is not used, this pin must be connected to VDD. 2: As an option, instead of a hard-wired connection, an FIGURE 2-2: EXAMPLE OF MCLR PIN inductor (L1) can be substituted between VDD and CONNECTIONS AVDD to improve ADC noise rejection. The inductor impedance should be less than 3 and the inductor VDD capacity greater than 10 mA. Where: R 10k R1(1) MCLR f = F-----C---N----V-- (i.e., ADC conversion rate/2) 0.1 µF(2) C 1 k 2 PIC32 1 f = ----------------------- 1 2 LC 5 PGECx(3) ™ 4 L = ----------1------------2 SP 2 VDD PGEDx(3)   C 3 2f C I 6 VSS NC 1: Aluminum or electrolytic capacitors should not be used. ESR  3 from -40ºC to 125ºC @ SYSCLK Note 1: 470R11 will limit any current flowing into frequency (i.e., MIPS). MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge 2.2.1 BULK CAPACITORS (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met without The use of a bulk capacitor is recommended to improve interfering with the Debug/Programmer tools. power supply stability. Typical values range from 4.7 µF 2: The capacitor can be sized to prevent unintentional to 47µF. This capacitor should be located as close to Resets from brief glitches or to extend the device the device as possible. Reset period during POR. 3: No pull-ups or bypass capacitors are allowed on active debug/program PGECx/PGEDx pins. 2.3 Capacitor on Internal Voltage Regulator (VCAP) 2.5 ICSP Pins 2.3.1 INTERNAL REGULATOR MODE The PGECx and PGEDx pins are used for ICSP and A low-ESR (3 ohm) capacitor is required on the VCAP debugging purposes. It is recommended to keep the pin, which is used to stabilize the internal voltage trace length between the ICSP connector and the ICSP regulator output. The VCAP pin must not be connected pins on the device as short as possible. If the ICSP con- to VDD, and must have a CEFC capacitor, with at least a nector is expected to experience an ESD event, a 6V rating, connected to ground. The type can be series resistor is recommended, with the value in the ceramic or tantalum. Refer to 30.0“Electrical range of a few tens of Ohms, not to exceed 100 Ohms. Characteristics” for additional information on CEFC specifications. DS60001168J-page 28  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Pull-up resistors, series diodes and capacitors on the The oscillator circuit should be placed on the same side PGECx and PGEDx pins are not recommended as they of the board as the device. Also, place the oscillator cir- will interfere with the programmer/debugger communi- cuit close to the respective oscillator pins, not exceed- cations to the device. If such discrete components are ing one-half inch (12mm) distance between them. The an application requirement, they should be removed load capacitors should be placed next to the oscillator from the circuit during programming and debugging. itself, on the same side of the board. Use a grounded Alternatively, refer to the AC/DC characteristics and copper pour around the oscillator circuit to isolate them timing requirements information in the respective from surrounding circuits. The grounded copper pour device Flash programming specification for information should be routed directly to the MCU ground. Do not on capacitive loading limits and pin input voltage high run any signal traces or power traces inside the ground (VIH) and input low (VIL) requirements. pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is Ensure that the “Communication Channel Select” (i.e., placed. A suggested layout is illustrated in Figure2-3. PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™. FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web Oscillator Secondary site: • “Using MPLAB® ICD 3” (poster) (DS50001765) Guard Trace • “MPLAB® ICD 3 Design Advisory” (DS50001764) • “MPLAB® REAL ICE™ In-Circuit Debugger Guard Ring User’s Guide” (DS50001616) • “Using MPLAB® REAL ICE™ Emulator” (poster) Main Oscillator (DS50001749) 2.6 JTAG 2.8 Unused I/Os The TMS, TDO, TDI and TCK pins are used for testing Unused I/O pins should not be allowed to float as and debugging according to the Joint Test Action inputs. They can be configured as outputs and driven Group (JTAG) standard. It is recommended to keep the to a logic-low state. trace length between the JTAG connector and the Alternatively, inputs can be reserved by connecting the JTAG pins on the device as short as possible. If the pin to VSS through a 1k to 10k resistor and configuring JTAG connector is expected to experience an ESD the pin as an input. event, a series resistor is recommended with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete compo- nents are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC character- istics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2.7 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section8.0 “Oscillator Configuration” for details).  2011-2016 Microchip Technology Inc. DS60001168J-page 29

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 2.8.1 CRYSTAL OSCILLATOR DESIGN FIGURE 2-4: PRIMARY CRYSTAL CONSIDERATION OSCILLATOR CIRCUIT RECOMMENDATIONS The following example assumptions are used to calculate the Primary Oscillator loading capacitor Circuit A values: Typical XT • CIN = PIC32_OSC2_Pin Capacitance = ~4-5 pF (4-10 MHz) • COUT = PIC32_OSC1_Pin Capacitance = ~4-5 pF • C1 and C2 = XTAL manufacturing recommended 1 2 C C loading capacitance 1M • Estimated PCB stray capacitance, (i.e.,12 mm length) = 2.5 pF OSC2 OSC1 EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR CALCULATION Circuit B Typical HS Crystal manufacturer recommended: C1 = C2 = 15 pF (10-25 MHz) Therefore: CLOAD = {([CIN + C1] * [COUT + C2]) / [CIN + C1 + C2 + COUT]} + estimated oscillator PCB stray capacitance 1 2 = {([5 + 15][5 + 15]) / [5 + 15 + 15 + 5]} + 2.5 pF C C = {([20][20]) / [40]} + 2.5 = 10 + 2.5 = 12.5 pF Rounded to the nearest standard value or 12 pF in this example for OSC2 OSC1 Primary Oscillator crystals “C1” and “C2”. Circuit C The following tips are used to increase oscillator gain, (i.e., to increase peak-to-peak oscillator signal): Typical XT/HS (4-25 MHz) • Select a crystal with a lower “minimum” power drive rating • Select an crystal oscillator with a lower XTAL 1 2 C Rs C manufacturing “ESR” rating. • Add a parallel resistor across the crystal. The smaller the resistor value the greater the gain. It is recom- 1M mended to stay in the range of 600k to 1M OSC2 OSC1 • C1 and C2 values also affect the gain of the oscillator. The lower the values, the higher the gain. • C2/C1 ratio also affects gain. To increase the gain, Circuit D make C1 slightly smaller than C2, which will also help Not Recommended start-up performance. Note: Do not add excessive gain such that the oscillator signal is clipped, flat on top of the sine wave. If so, you need to reduce the gain or add a series resistor, RS, as 1M shown in circuit “C” in Figure2-4. Failure Rs to do so will stress and age the crystal, which can result in an early failure. Adjust the gain to trim the max peak-to-peak to OSC2 OSC1 ~VDD-0.6V. When measuring the oscilla- tor signal you must use a FET scope Circuit E probe or a probe with  1.5 pF or the Not Recommended scope probe itself will unduly change the gain and peak-to-peak levels. 2.8.1.1 Additional Microchip References • AN588 “PICmicro® Microcontroller Oscillator Rs Design Guide” • AN826 “Crystal Oscillator Basics and Crystal 1M Selection for rfPIC™ and PICmicro® Devices” OSC2 OSC1 • AN849 “Basic PICmicro® Oscillator Design” DS60001168J-page 30  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 2.9 Typical Application Connection Examples Examples of typical application connections are shown in Figure2-5 and Figure2-6. FIGURE 2-5: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION PIC32MX120F032D Current Source To AN6 To AN7 To AN8 To AN9 To AN11 To AN0 CTMU AN0 R1 R1 R1 R1 R1 C1 C2 C3 C4 C5 AN1 To AN1 ADC R2 R2 R2 R2 R2 Read the Touch Sensors C1 C2 C3 C4 C5 Microchip mTouch™ Library AN9 Process Samples To AN5 AN11 R3 R3 R3 R3 R3 User C1 C2 C3 C4 C5 Application Display Data LCD Controller PMPD<7:0> Microchip Parallel Frame Display LCD Graphics Master PMPWR Buffer Controller Panel Library Port FIGURE 2-6: AUDIO PLAYBACK APPLICATION PMPD<7:0> USB USB PMP Host Display PMPWR PIC32MX220F032D Stereo Headphones I2S 3 Audio Codec 3 SPI Speaker 3 MMC SD SDI  2011-2016 Microchip Technology Inc. DS60001168J-page 31

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 32  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 3.0 CPU • MIPS16e® code compression - 16-bit encoding of 32-bit instructions to Note: This data sheet summarizes the features improve code density of the PIC32MX1XX/2XX 28/36/44-pin - Special PC-relative instructions for efficient Family of devices. It is not intended to be loading of addresses and constants a comprehensive reference source. To - SAVE and RESTORE macro instructions for complement the information in this data setting up and tearing down stack frames sheet, refer to Section 2. “CPU” within subroutines (DS60001113), which is available from the Documentation > Reference Manual - Improved support for handling 8 and 16-bit section of the Microchip PIC32 web site data types (www.microchip.com/pic32). Resources • Simple Fixed Mapping Translation (FMT) for the MIPS32® M4K® Processor Core mechanism are available at: www.imgtec.com. • Simple dual bus interface The MIPS32® M4K® Processor Core is the heart of the - Independent 32-bit address and data buses PIC32MX1XX/2XX family processor. The CPU fetches - Transactions can be aborted to improve instructions, decodes each instruction, fetches source interrupt latency operands, executes each instruction and writes the • Autonomous multiply/divide unit results of instruction execution to the destinations. - Maximum issue rate of one 32x16 multiply 3.1 Features per clock - Maximum issue rate of one 32x32 multiply • 5-stage pipeline every other clock • 32-bit address and data paths - Early-in iterative divide. Minimum 11 and • MIPS32 Enhanced Architecture (Release 2) maximum 33 clock latency (dividend (rs) sign - Multiply-accumulate and multiply-subtract extension-dependent) instructions • Power control - Targeted multiply instruction - Minimum frequency: 0 MHz - Zero/One detect instructions - Low-Power mode (triggered by WAIT - WAIT instruction instruction) - Conditional move instructions (MOVN, MOVZ) - Extensive use of local gated clocks - Vectored interrupts • EJTAG debug and instruction trace - Programmable exception vector base - Support for single stepping - Atomic interrupt enable/disable - Virtual instruction and data address/value - Bit field manipulation instructions - Breakpoints FIGURE 3-1: MIPS32® M4K® PROCESSOR CORE BLOCK DIAGRAM CPU EJTAG MDU TAP Off-chip Debug Interface Execution Core (RF/ALU/Shift) FMT Bus Interface Dual Bus Interface Bus Matrix System Power Co-processor Management  2011-2016 Microchip Technology Inc. DS60001168J-page 33

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 3.2 Architecture Overview 3.2.2 MULTIPLY/DIVIDE UNIT (MDU) The MIPS32 M4K processor core contains several The MIPS32 M4K processor core includes a Multi- logic blocks working together in parallel, providing an ply/Divide Unit (MDU) that contains a separate pipeline efficient high-performance computing engine. The for multiply and divide operations. This pipeline oper- following blocks are included with the core: ates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows • Execution Unit MDU operations to be partially masked by system stalls • Multiply/Divide Unit (MDU) and/or other integer unit instructions. • System Control Coprocessor (CP0) • Fixed Mapping Translation (FMT) The high-performance MDU consists of a 32x16 booth • Dual Internal Bus interfaces recoded multiplier, result/accumulation registers (HI • Power Management and LO), a divide state machine, and the necessary • MIPS16e® Support multiplexers and control logic. The first number shown • Enhanced JTAG (EJTAG) Controller (‘32’ of 32x16) represents the rs operand. The second number (‘16’ of 32x16) represents the rt operand. The 3.2.1 EXECUTION UNIT PIC32 core only checks the value of the latter (rt) oper- and to determine how many times the operation must The MIPS32 M4K processor core execution unit imple- pass through the multiplier. The 16x16 and 32x16 ments a load/store architecture with single-cycle ALU operations pass through the multiplier once. A 32x32 operations (logical, shift, add, subtract) and an autono- operation passes through the multiplier twice. mous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for The MDU supports execution of one 16x16 or 32x16 integer operations and address calculation. The regis- multiply operation every clock cycle; 32x32 multiply ter file consists of two read ports and one write port and operations can be issued every other clock cycle. is fully bypassed to minimize operation latency in the Appropriate interlocks are implemented to stall the pipeline. issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined The execution unit includes: by logic built into the MDU. • 32-bit adder used for calculating the data address Divide operations are implemented with a simple 1 bit • Address unit for calculating the next instruction per clock iterative algorithm. An early-in detection address checks the sign extension of the dividend (rs) operand. • Logic for branch determination and branch target If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit address calculation wide rs, 15 iterations are skipped and for a 24-bit wide • Load aligner rs, 7 iterations are skipped. Any attempt to issue a sub- • Bypass multiplexers used to avoid stalls when sequent MDU instruction while a divide is still active executing instruction streams where data causes an IU pipeline stall until the divide operation is producing instructions are followed closely by completed. consumers of their results • Leading Zero/One detect unit for implementing Table3-1 lists the repeat rate (peak issue rate of cycles the CLZ and CLO instructions until the operation can be reissued) and latency (num- • Arithmetic Logic Unit (ALU) for performing bitwise ber of cycles until a result is available) for the PIC32 logical operations core multiply and divide instructions. The approximate • Shifter and store aligner latency and repeat rates are listed in terms of pipeline clocks. TABLE 3-1: MIPS32® M4K® PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate MULT/MULTU, MADD/MADDU, 16 bits 1 1 MSUB/MSUBU 32 bits 2 2 MUL 16 bits 2 1 32 bits 3 2 DIV/DIVU 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32 DS60001168J-page 34  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY The MIPS architecture defines that the result of a adds the product to the current contents of the HI and multiply or divide operation be placed in the HI and LO LO registers. Similarly, the MSUB instruction multiplies registers. Using the Move-From-HI (MFHI) and Move- two operands and then subtracts the product from the From-LO (MFLO) instructions, these values can be HI and LO registers. The MADD and MSUB operations transferred to the General Purpose Register file. are commonly used in DSP algorithms. In addition to the HI/LO targeted operations, the 3.2.3 SYSTEM CONTROL MIPS32® architecture also defines a multiply instruc- COPROCESSOR (CP0) tion, MUL, which places the least significant results in the primary register file instead of the HI/LO register In the MIPS architecture, CP0 is responsible for the pair. By avoiding the explicit MFLO instruction virtual-to-physical address translation, the exception required when using the LO register, and by support- control system, the processor’s diagnostics capability, ing multiple destination registers, the throughput of the operating modes (Kernel, User and Debug) and multiply-intensive operations is increased. whether interrupts are enabled or disabled. Configura- tion information, such as presence of options like Two other instructions, Multiply-Add (MADD) and MIPS16e, is also available by accessing the CP0 Multiply-Subtract (MSUB), are used to perform the registers, listed in Table3-2. multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then TABLE 3-2: COPROCESSOR 0 REGISTERS Register Register Function Number Name 0-6 Reserved Reserved in the PIC32MX1XX/2XX family core. 7 HWREna Enables access via the RDHWR instruction to selected hardware registers. 8 BadVAddr(1) Reports the address for the most recent address-related exception. 9 Count(1) Processor cycle count. 10 Reserved Reserved in the PIC32MX1XX/2XX family core. 11 Compare(1) Timer interrupt control. 12 Status(1) Processor status and control. 12 IntCtl(1) Interrupt system status and control. 12 SRSCtl(1) Shadow register set status and control. 12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set. 13 Cause(1) Cause of last general exception. 14 EPC(1) Program counter at last exception. 15 PRId Processor identification and revision. 15 EBASE Exception vector base register. 16 Config Configuration register. 16 Config1 Configuration Register 1. 16 Config2 Configuration Register 2. 16 Config3 Configuration Register 3. 17-22 Reserved Reserved in the PIC32MX1XX/2XX family core. 23 Debug(2) Debug control and exception status. 24 DEPC(2) Program counter at last debug exception. 25-29 Reserved Reserved in the PIC32MX1XX/2XX family core. 30 ErrorEPC(1) Program counter at last error. 31 DESAVE(2) Debug handler scratchpad register. Note 1: Registers used in exception processing. 2: Registers used during debug.  2011-2016 Microchip Technology Inc. DS60001168J-page 35

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table3-3 lists the exception types in order of priority. TABLE 3-3: MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS EJTAG debug single step. DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. NMI Assertion of NMI signal. Interrupt Assertion of unmasked hardware or software interrupt signal. DIB EJTAG debug hardware instruction break matched. AdEL Fetch address alignment error. Fetch reference to protected address. IBE Instruction fetch bus error. DBp EJTAG breakpoint (execution of SDBBP instruction). Sys Execution of SYSCALL instruction. Bp Execution of BREAK instruction. RI Execution of a reserved instruction. CpU Execution of a coprocessor instruction for a coprocessor that is not enabled. CEU Execution of a CorExtend instruction when CorExtend is not enabled. Ov Execution of an arithmetic instruction that overflowed. Tr Execution of a trap (when trap condition is true). DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). AdEL Load address alignment error. Load reference to protected address. AdES Store address alignment error. Store to protected address. DBE Load or store bus error. DDBL EJTAG data hardware breakpoint matched in load data compare. 3.3 Power Management 3.4 EJTAG Debug Support The MIPS M4K processor core offers many power man- The MIPS M4K processor core provides an Enhanced agement features, including low-power design, active JTAG (EJTAG) interface for use in the software debug power management and power-down modes of opera- of application and kernel code. In addition to standard tion. The core is a static design that supports slowing or User mode and Kernel modes of operation, the M4K Halting the clocks, which reduces system power con- core provides a Debug mode that is entered after a sumption during Idle periods. debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until 3.3.1 INSTRUCTION-CONTROLLED a Debug Exception Return (DERET) instruction is POWER MANAGEMENT executed. During this time, the processor executes the debug exception handler routine. The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more The EJTAG interface operates through the Test Access information on power management, see Section26.0 Port (TAP), a serial communication port used for trans- “Power-Saving Features”. ferring test data in and out of the core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. DS60001168J-page 36  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 4.0 MEMORY ORGANIZATION 4.1 PIC32MX1XX/2XX 28/36/44-pin Family Memory Layout Note: This data sheet summarizes the features of the PIC32MX1XX/2XX 28/36/44-pin PIC32MX1XX/2XX 28/36/44-pin Family microcontrol- Family of devices. It is not intended to be lers implement two address schemes: virtual and phys- a comprehensive reference source.For ical. All hardware resources, such as program memory, detailed information, refer to Section 3. data memory and peripherals, are located at their “Memory Organization” (DS60001115), respective physical addresses. Virtual addresses are which is available from the exclusively used by the CPU to fetch and execute Documentation > Reference Manual instructions as well as access peripherals. Physical section of the Microchip PIC32 web site addresses are used by bus master peripherals, such as (www.microchip.com/pic32). DMA and the Flash controller, that access memory independently of the CPU. PIC32MX1XX/2XX 28/36/44-pin Family microcontrol- The memory maps for the PIC32MX1XX/2XX lers provide 4 GB unified virtual memory address 28/36/44-pin Family devices are illustrated in space. All memory regions, including program, data Figure4-1 through Figure4-6. memory, Special Function Registers (SFRs), and Con- figuration registers, reside in this address space at their Table4-1 provides SFR memory map details. respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX1XX/2XX 28/36/44-pin Family devices to execute from data memory. Key features include: • 32-bit native data width • Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode address space • Flexible program Flash memory partitioning • Flexible data RAM partitioning for data and program space • Separate boot Flash memory for protected code • Robust bus exception handling to intercept runaway code • Simple memory mapping with Fixed Mapping Translation (FMT) unit • Cacheable (KSEG0) and non-cacheable (KSEG1) address regions  2011-2016 Microchip Technology Inc. DS60001168J-page 37

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX110/210 DEVICES (4 KB RAM, 16 KB FLASH) Virtual Physical Memory Map(1) Memory Map(1) 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC00C00 0xBFC00BFF Device Configuration 0xBFC00BF0 Registers 0xBFC00BEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs 1 Reserved G 0xBF800000 E S K Reserved 0xBD004000 0xBD003FFF Program Flash(2) 0xBD000000 Reserved 0xA0001000 0xA0000FFF RAM(2) 0xA0000000 0x1FC00C00 Device 0x1FC00BFF Reserved 0x9FC00C00 Configuration 0x9FC00BFF Device Registers 0x1FC00BF0 Configuration 0x1FC00BEF Registers 0x9FC00BF0 Boot Flash 0x9FC00BEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved 0 SFRs G 0x9D004000 E 0x1F800000 S 0x9D003FFF K Program Flash(2) Reserved 0x9D000000 0x1D004000 0x1D003FFF Reserved 0x80001000 Program Flash(2) 0x80000FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00001000 0x00000FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa- tion code provided by end-user development tools (refer to the specific development tool documentation for information). DS60001168J-page 38  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX120/220 DEVICES (8 KB RAM, 32 KB FLASH) Virtual Physical Memory Map(1) Memory Map(1) 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC00C00 0xBFC00BFF Device Configuration 0xBFC00BF0 Registers 0xBFC00BEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs Reserved 1 0xBF800000 G E S Reserved K 0xBD008000 0xBD007FFF Program Flash(2) 0xBD000000 Reserved 0xA0002000 0xA0001FFF RAM(2) 0xA0000000 0x1FC00C00 Device 0x1FC00BFF Reserved 0x9FC00C00 Configuration 0x9FC00BFF Device Registers 0x1FC00BF0 Configuration 0x1FC00BEF Registers 0x9FC00BF0 Boot Flash 0x9FC00BEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0x9D008000 0 0x1F800000 G 0x9D007FFF E S Program Flash(2) K Reserved 0x9D000000 0x1D008000 0x1D007FFF Reserved 0x80002000 Program Flash(2) 0x80001FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00002000 0x00001FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa- tion code provided by end-user development tools (refer to the specific development tool documentation for information).  2011-2016 Microchip Technology Inc. DS60001168J-page 39

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX130/230 DEVICES (16 KB RAM, 64 KB FLASH) Virtual Physical Memory Map(1) Memory Map(1) 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC00C00 0xBFC00BFF Device Configuration 0xBFC00BF0 Registers 0xBFC00BEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs 1 Reserved G 0xBF800000 E S K Reserved 0xBD010000 0xBD00FFFF Program Flash(2) 0xBD000000 Reserved 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x1FC00C00 Device 0x1FC00BFF Reserved 0x9FC00C00 Configuration 0x9FC00BFF Device Registers 0x1FC00BF0 Configuration 0x1FC00BEF Registers 0x9FC00BF0 Boot Flash 0x9FC00BEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 G 0x9D010000 E 0x1F800000 S 0x9D00FFFF K Program Flash(2) Reserved 0x9D000000 0x1D010000 0x1D00FFFF Reserved 0x80004000 Program Flash(2) 0x80003FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00004000 0x00003FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa- tion code provided by end-user development tools (refer to the specific development tool documentation for information). DS60001168J-page 40  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX150/250 DEVICES (32 KB RAM, 128 KB FLASH) Virtual Physical Memory Map(1) Memory Map(1) 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC00C00 0xBFC00BFF Device Configuration 0xBFC00BF0 Registers 0xBFC00BEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs Reserved 1 G 0xBF800000 E S K Reserved 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 Reserved 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x1FC00C00 Device 0x1FC00BFF Reserved 0x9FC00C00 Configuration 0x9FC00BFF Device Registers 0x1FC00BF0 Configuration 0x1FC00BEF Registers 0x9FC00BF0 Boot Flash 0x9FC00BEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 G 0x9D020000 E 0x1F800000 S 0x9D01FFFF K Program Flash(2) Reserved 0x9D000000 0x1D020000 0x1D01FFFF Reserved 0x80008000 Program Flash(2) 0x80007FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00008000 0x00007FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa- tion code provided by end-user development tools (refer to the specific development tool documentation for information).  2011-2016 Microchip Technology Inc. DS60001168J-page 41

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX170/270 DEVICES (64 KB RAM, 256 KB FLASH) Virtual Physical Memory Map(1) Memory Map(1) 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC00C00 0xBFC00BFF Device Configuration 0xBFC00BF0 Registers 0xBFC00BEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs 1 Reserved G 0xBF800000 E S K Reserved 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 Reserved 0xA0010000 0xA000FFFF RAM(2) 0xA0000000 0x1FC00C00 Device 0x1FC00BFF Reserved 0x9FC00C00 Configuration 0x9FC00BFF Device Registers 0x1FC00BF0 Configuration 0x1FC00BEF Registers 0x9FC00BF0 Boot Flash 0x9FC00BEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 G 0x9D040000 E 0x1F800000 S 0x9D03FFFF K Program Flash(2) Reserved 0x9D000000 0x1D040000 0x1D03FFFF Reserved 0x80010000 Program Flash(2) 0x8000FFFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00010000 0x0000FFFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa- tion code provided by end-user development tools (refer to the specific development tool documentation for information). DS60001168J-page 42  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX130/230 DEVICES (16 KB RAM, 256 KB FLASH) Virtual Physical Memory Map(1) Memory Map(1) 0xFFFFFFFF 0xFFFFFFFF Reserved 0xBFC00C00 0xBFC00BFF Device Configuration 0xBFC00BF0 Registers 0xBFC00BEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs 1 Reserved G 0xBF800000 E S K Reserved 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 Reserved 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x1FC00C00 Device 0x1FC00BFF Reserved 0x9FC00C00 Configuration 0x9FC00BFF Device Registers 0x1FC00BF0 Configuration 0x1FC00BEF Registers 0x9FC00BF0 Boot Flash 0x9FC00BEF 0x1FC00000 Boot Flash Reserved 0x9FC00000 0x1F900000 0x1F8FFFFF Reserved SFRs 0 G 0x9D040000 E 0x1F800000 S 0x9D03FFFF K Program Flash(2) Reserved 0x9D000000 0x1D040000 0x1D03FFFF Reserved 0x80004000 Program Flash(2) 0x80003FFF 0x1D000000 RAM(2) Reserved 0x80000000 0x00004000 0x00003FFF Reserved RAM(2) 0x00000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”) and can be changed by initializa- tion code provided by end-user development tools (refer to the specific development tool documentation for information).  2011-2016 Microchip Technology Inc. DS60001168J-page 43

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 4-1: SFR MEMORY MAP Virtual Address Peripheral Offset Base Start Watchdog Timer 0x0000 RTCC 0x0200 Timer1-5 0x0600 Input Capture 1-5 0x2000 Output Compare 1-5 0x3000 IC1 and IC2 0x5000 SPI1 and SPI2 0x5800 UART1 and UART2 0x6000 PMP 0x7000 ADC 0xBF80 0x9000 CVREF 0x9800 Comparator 0xA000 CTMU 0xA200 Oscillator 0xF000 Device and Revision ID 0xF220 Peripheral Module Disable 0xF240 Flash Controller 0xF400 Reset 0xF600 PPS 0xFA04 Interrupts 0x1000 Bus Matrix 0x2000 DMA 0xBF88 0x3000 USB 0x5050 PORTA-PORTC 0x6000 Configuration 0xBFC0 0x0BF0 DS60001168J-page 44  2011-2016 Microchip Technology Inc.

 4.2 Bus Matrix Control Registers 2 0 1 1 TABLE 4-2: BUS MATRIX REGISTER MAP -2 0 16 Microchip T Virtual Address(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 B2it2s/6 21/5 20/4 19/3 18/2 17/1 16/0 AllResets e c 31:16 — — — — — — — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F hn 2000 BMXCON(1) P o 15:0 — — — — — — — — — BMXWSDRM — — — BMXARB<2:0> 0041 lo I gy In 2010 BMXDKPBA(1) 3115:1:06 — — — — — — — — —BMXDKPB—A<15:0> — — — — — — 00000000 C3 c . 31:16 — — — — — — — — — — — — — — — — 0000 2 2020 BMXDUDBA(1) 15:0 BMXDUDBA<15:0> 0000 M 2030 BMXDUPBA(1) 31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 BMXDUPBA<15:0> 0000 1 31:16 xxxx X 2040 BMXDRMSZ BMXDRMSZ<31:0> 15:0 xxxx X 31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000 2050 BMXPUPBA(1) / 15:0 BMXPUPBA<15:0> 0000 2 31:16 xxxx X 2060 BMXPFMSZ BMXPFMSZ<31:0> 15:0 xxxx X 31:16 0000 2070 BMXBOOTSZ BMXBOOTSZ<31:0> 2 15:0 0C00 8 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more information. 3 6 / 4 4 - P I N D S6 F 0 0 A 0 1 16 M 8 J -p I a L g e 4 Y 5

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 4-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 23:16 BMX BMX BMX BMX BMX — — — ERRIXI ERRICD ERRDMA ERRDS ERRIS U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 7:0 BMX — — — — BMXARB<2:0> WSDRM Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-21 Unimplemented: Read as ‘0’ bit 20 BMXERRIXI: Enable Bus Error from IXI bit 1=Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus 0=Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit 1=Enable bus error exceptions for unmapped address accesses initiated from ICD 0=Disable bus error exceptions for unmapped address accesses initiated from ICD bit 18 BMXERRDMA: Bus Error from DMA bit 1=Enable bus error exceptions for unmapped address accesses initiated from DMA 0=Disable bus error exceptions for unmapped address accesses initiated from DMA bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode) 1=Enable bus error exceptions for unmapped address accesses initiated from CPU data access 0=Disable bus error exceptions for unmapped address accesses initiated from CPU data access bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode) 1=Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access 0=Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access bit 15-7 Unimplemented: Read as ‘0’ bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit 1=Data RAM accesses from CPU have one wait state for address setup 0=Data RAM accesses from CPU have zero wait states for address setup bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits 111 = Reserved (using these Configuration modes will produce undefined behavior) • • • 011 = Reserved (using these Configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 (default) 000 = Arbitration Mode 0 DS60001168J-page 46  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 4-2: BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 15:8 BMXDKPBA<15:8> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 BMXDKPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits When non-zero, this value selects the relative base address for kernel program space in RAM bit 9-0 BMXDKPBA<9:0>: Read-Only bits This value is always ‘0’, which forces 1KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. 2: The value in this register must be less than or equal to BMXDRMSZ.  2011-2016 Microchip Technology Inc. DS60001168J-page 47

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 4-3: BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 15:8 BMXDUDBA<15:8> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 BMXDUDBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits When non-zero, the value selects the relative base address for User mode data space in RAM, the value must be greater than BMXDKPBA. bit 9-0 BMXDUDBA<9:0>: Read-Only bits This value is always ‘0’, which forces 1KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. 2: The value in this register must be less than or equal to BMXDRMSZ. DS60001168J-page 48  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 4-4: BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 15:8 BMXDUPBA<15:8> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 BMXDUPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits When non-zero, the value selects the relative base address for User mode program space in RAM, BMXDUPBA must be greater than BMXDUDBA. bit 9-0 BMXDUPBA<9:0>: Read-Only bits This value is always ‘0’, which forces 1KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. 2: The value in this register must be less than or equal to BMXDRMSZ.  2011-2016 Microchip Technology Inc. DS60001168J-page 49

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 4-5: BMXDRMSZ: DATA RAM SIZE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R R R R R R R R 31:24 BMXDRMSZ<31:24> R R R R R R R R 23:16 BMXDRMSZ<23:16> R R R R R R R R 15:8 BMXDRMSZ<15:8> R R R R R R R R 7:0 BMXDRMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes: 0x00001000 = Device has 4KB RAM 0x00002000 = Device has 8KB RAM 0x00004000 = Device has 16 KB RAM 0x00008000 = Device has 32 KB RAM 0x00010000 = Device has 64 KB RAM REGISTER 4-6: BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 — — — — BMXPUPBA<19:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 15:8 BMXPUPBA<15:8> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 BMXPUPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as ‘0’ bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits bit 10-0 BMXPUPBA<10:0>: Read-Only bits This value is always ‘0’, which forces 2KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. 2: The value in this register must be less than or equal to BMXPFMSZ. DS60001168J-page 50  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 4-7: BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R R R R R R R R 31:24 BMXPFMSZ<31:24> R R R R R R R R 23:16 BMXPFMSZ<23:16> R R R R R R R R 15:8 BMXPFMSZ<15:8> R R R R R R R R 7:0 BMXPFMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits Static value that indicates the size of the PFM in bytes: 0x00004000 = Device has 16KB Flash 0x00008000 = Device has 32KB Flash 0x00010000 = Device has 64 KB Flash 0x00020000 = Device has 128 KB Flash 0x00040000 = Device has 256 KB Flash REGISTER 4-8: BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R R R R R R R R 31:24 BMXBOOTSZ<31:24> R R R R R R R R 23:16 BMXBOOTSZ<23:16> R R R R R R R R 15:8 BMXBOOTSZ<15:8> R R R R R R R R 7:0 BMXBOOTSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes: 0x00000C00 = Device has 3KB boot Flash  2011-2016 Microchip Technology Inc. DS60001168J-page 51

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 52  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 5.0 FLASH PROGRAM MEMORY RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP Note: This data sheet summarizes the features techniques is available in Section 5. “Flash Program of the PIC32MX1XX/2XX 28/36/44-pin Memory” (DS60001121) in the “PIC32 Family Family of devices. It is not intended to be Reference Manual”. a comprehensive reference source. To EJTAG is performed using the EJTAG port of the complement the information in this data device and an EJTAG capable programmer. sheet, refer to Section 5. “Flash ICSP is performed using a serial data connection to the Program Memory” (DS60001121), which device and allows much faster programming times than is available from the Documentation > RTSP. Reference Manual section of the Microchip PIC32 web site The EJTAG and ICSP methods are described in the (www.microchip.com/pic32). “PIC32 Flash Programming Specification” (DS60001145), which can be downloaded from the PIC32MX1XX/2XX 28/36/44-pin Family devices con- Microchip web site. tain an internal Flash program memory for executing user code. There are three methods by which the user Note: The Flash page size on PIC32MX- can program this memory: 1XX/2XX 28/36/44-pin Family devices is 1 KB and the row size is 128 bytes (256 IW • Run-Time Self-Programming (RTSP) and 32 IW, respectively). • EJTAG Programming • In-Circuit Serial Programming™ (ICSP™)  2011-2016 Microchip Technology Inc. DS60001168J-page 53

D 5.1 Flash Controller Control Registers P S 600 TABLE 5-1: FLASH CONTROLLER REGISTER MAP IC 0 1168J-page 54 Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 1 31:16 — — — — — — — — — — — — — — — — 0000 F400 NVMCON(1) X 15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — NVMOP<3:0> 0000 31:16 0000 X F410 NVMKEY NVMKEY<31:0> 15:0 0000 / 31:16 0000 2 F420 NVMADDR(1) NVMADDR<31:0> 15:0 0000 X 31:16 0000 X F430 NVMDATA NVMDATA<31:0> 15:0 0000 31:16 0000 2 F440 NVMSRCADDR NVMSRCADDR<31:0> 15:0 0000 8 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 3 Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more information. 6 / 4 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R-0 R-0 R-0 U-0 U-0 U-0 15:8 WR WREN WRERR(1) LVDERR(1) LVDSTAT(1) — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — — — NVMOP<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 WR: Write Control bit This bit is writable when WREN = 1 and the unlock sequence is followed. 1 = Initiate a Flash operation. Hardware clears this bit when the operation completes 0 = Flash operation is complete or inactive bit 14 WREN: Write Enable bit This is the only bit in this register reset by a device Reset. 1 = Enable writes to WR bit and enables LVD circuit 0 = Disable writes to WR bit and disables LVD circuit bit 13 WRERR: Write Error bit(1) This bit is read-only and is automatically set by hardware. 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set by hardware. 1 = Low-voltage detected (possible data corruption, if WRERR is set) 0 = Voltage level is acceptable for programming bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set and cleared by the hardware. 1 = Low-voltage event is active 0 = Low-voltage event is not active bit 10-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation bits These bits are writable when WREN = 0. 1111 =Reserved • • • 0111 = Reserved 0110 =No operation 0101 =Program Flash Memory (PFM) erase operation: erases PFM, if all pages are not write-protected 0100 =Page erase operation: erases page selected by NVMADDR, if it is not write-protected 0011 =Row program operation: programs row selected by NVMADDR, if it is not write-protected 0010 =No operation 0001 =Word program operation: programs word selected by NVMADDR, if it is not write-protected 0000 = No operation Note 1: This bit is cleared by setting NVMOP == ‘b0000, and initiating a Flash operation (i.e., WR).  2011-2016 Microchip Technology Inc. DS60001168J-page 55

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 5-2: NVMKEY: PROGRAMMING UNLOCK REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 31:24 NVMKEY<31:24> W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 23:16 NVMKEY<23:16> W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 15:8 NVMKEY<15:8> W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 7:0 NVMKEY<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 NVMKEY<31:0>: Unlock Register bits These bits are write-only, and read as ‘0’ on any read Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM. REGISTER 5-3: NVMADDR: FLASH ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 NVMADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 NVMADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 NVMADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 NVMADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 NVMADDR<31:0>: Flash Address bits Bulk/Chip/PFM Erase: Address is ignored. Page Erase: Address identifies the page to erase. Row Program: Address identifies the row to program. Word Program: Address identifies the word to program. DS60001168J-page 56  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 5-4: NVMDATA: FLASH PROGRAM DATA REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 NVMDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 NVMDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 NVMDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 NVMDATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 NVMDATA<31:0>: Flash Programming Data bits Note: The bits in this register are only reset by a Power-on Reset (POR). REGISTER 5-5: NVMSRCADDR: SOURCE DATA ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 NVMSRCADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 NVMSRCADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 NVMSRCADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 NVMSRCADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits (NVMCON<3:0>) are set to perform row programming.  2011-2016 Microchip Technology Inc. DS60001168J-page 57

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 58  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 6.0 RESETS The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The Note: This data sheet summarizes the features following is a list of device Reset sources: of the PIC32MX1XX/2XX 28/36/44-pin • Power-on Reset (POR) Family of devices. It is not intended to be • Master Clear Reset pin (MCLR) a comprehensive reference source. To • Software Reset (SWR) complement the information in this data sheet, refer to Section 7. “Resets” • Watchdog Timer Reset (WDTR) (DS60001118), which is available from the • Brown-out Reset (BOR) Documentation > Reference Manual • Configuration Mismatch Reset (CMR) section of the Microchip PIC32 web site A simplified block diagram of the Reset module is (www.microchip.com/pic32). illustrated in Figure6-1. FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM MCLR MCLR Glitch Filter Sleep or Idle WDTR WDT Voltage Time-out Regulator Enabled POR Power-up Timer SYSRST VDD VDD Rise Detect Brown-out BOR Reset Configuration Mismatch CMR Reset SWR Software Reset  2011-2016 Microchip Technology Inc. DS60001168J-page 59

D 6.1 Reset Control Registers P S 600 TABLE 6-1: RESET CONTROL REGISTER MAP IC 0 1 168J-page 60 Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bi2ts3/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 1 31:16 — — — — — — — — — — — — — — — — 0000 F600 RCON 15:0 — — — — — — CMR VREGS EXTR SWR — WDTO SLEEP IDLE BOR POR xxxx(2) X 31:16 — — — — — — — — — — — — — — — — 0000 X F610 RSWRST 15:0 — — — — — — — — — — — — — — — SWRST 0000 / Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for X more information. X 2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. 2 8 / 3 6 / 4 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0 15:8 — — — — — — CMR VREGS R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS 7:0 EXTR SWR — WDTO SLEEP IDLE BOR(1) POR(1) Legend: HS = Set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-10 Unimplemented: Read as ‘0’ bit 9 CMR: Configuration Mismatch Reset Flag bit 1 = Configuration mismatch Reset has occurred 0 = Configuration mismatch Reset has not occurred bit 8 VREGS: Voltage Regulator Standby Enable bit 1 = Regulator is enabled and is on during Sleep mode 0 = Regulator is disabled and is off during Sleep mode bit 7 EXTR: External Reset (MCLR) Pin Flag bit 1 = Master Clear (pin) Reset has occurred 0 = Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset Flag bit 1 = Software Reset was executed 0 = Software Reset as not executed bit 5 Unimplemented: Read as ‘0’ bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred 0 = WDT Time-out has not occurred bit 3 SLEEP: Wake From Sleep Flag bit 1 = Device was in Sleep mode 0 = Device was not in Sleep mode bit 2 IDLE: Wake From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit(1) 1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit(1) 1 = Power-on Reset has occurred 0 = Power-on Reset has not occurred Note 1: User software must clear this bit to view next detection.  2011-2016 Microchip Technology Inc. DS60001168J-page 61

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 6-2: RSWRST: SOFTWARE RESET REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC 7:0 — — — — — — — SWRST(1) Legend: HC = Cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-1 Unimplemented: Read as ‘0’ bit 0 SWRST: Software Reset Trigger bit(1) 1 = Enable Software Reset event 0 = No effect Note 1: The system unlock sequence must be performed before the SWRST bit is written. Refer to Section 6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details. DS60001168J-page 62  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 7.0 INTERRUPT CONTROLLER • Up to 64 interrupt sources • Up to 44 interrupt vectors Note: This data sheet summarizes the features • Single and multi-vector mode operations of the PIC32MX1XX/2XX 28/36/44-pin • Five external interrupts with edge polarity control Family of devices. It is not intended to be a comprehensive reference source. To • Interrupt proximity timer complement the information in this data • Seven user-selectable priority levels for each sheet, refer to Section 8. “Interrupt Con- vector troller” (DS60001108), which is available • Four user-selectable subpriority levels within each from the Documentation > Reference priority Manual section of the Microchip PIC32 • Software can generate any interrupt web site (www.microchip.com/pic32). • User-configurable Interrupt Vector Table (IVT) PIC32MX1XX/2XX 28/36/44-pin Family devices gener- location ate interrupt requests in response to interrupt events • User-configurable interrupt vector spacing from peripheral modules. The interrupt control module Note: The dedicated shadow register set is not exists externally to the CPU logic and prioritizes the present on PIC32MX1XX/2XX 28/36/44- interrupt events before presenting them to the CPU. pin Family devices. The PIC32MX1XX/2XX 28/36/44-pin Family interrupt A simplified block diagram of the Interrupt Controller module includes the following features: module is illustrated in Figure7-1. FIGURE 7-1: INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM s est Vector Number u q e R pt Interrupt Controller CPU Core u err nt Priority Level I  2011-2016 Microchip Technology Inc. DS60001168J-page 63

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Bit Location IRQ Vector Persistent Interrupt Source(1) # # Interrupt Flag Enable Priority Sub-priority Highest Natural Order Priority CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No INT0 – External Interrupt 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No T1 – Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No IC1E – Input Capture 1 Error 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> Yes IC1 – Input Capture 1 6 5 IFS0<6> IEC0<6> IPC1<12:10> IPC1<9:8> Yes OC1 – Output Compare 1 7 6 IFS0<7> IEC0<7> IPC1<20:18> IPC1<17:16> No INT1 – External Interrupt 1 8 7 IFS0<8> IEC0<8> IPC1<28:26> IPC1<25:24> No T2 – Timer2 9 8 IFS0<9> IEC0<9> IPC2<4:2> IPC2<1:0> No IC2E – Input Capture 2 10 9 IFS0<10> IEC0<10> IPC2<12:10> IPC2<9:8> Yes IC2 – Input Capture 2 11 9 IFS0<11> IEC0<11> IPC2<12:10> IPC2<9:8> Yes OC2 – Output Compare 2 12 10 IFS0<12> IEC0<12> IPC2<20:18> IPC2<17:16> No INT2 – External Interrupt 2 13 11 IFS0<13> IEC0<13> IPC2<28:26> IPC2<25:24> No T3 – Timer3 14 12 IFS0<14> IEC0<14> IPC3<4:2> IPC3<1:0> No IC3E – Input Capture 3 15 13 IFS0<15> IEC0<15> IPC3<12:10> IPC3<9:8> Yes IC3 – Input Capture 3 16 13 IFS0<16> IEC0<16> IPC3<12:10> IPC3<9:8> Yes OC3 – Output Compare 3 17 14 IFS0<17> IEC0<17> IPC3<20:18> IPC3<17:16> No INT3 – External Interrupt 3 18 15 IFS0<18> IEC0<18> IPC3<28:26> IPC3<25:24> No T4 – Timer4 19 16 IFS0<19> IEC0<19> IPC4<4:2> IPC4<1:0> No IC4E – Input Capture 4 Error 20 17 IFS0<20> IEC0<20> IPC4<12:10> IPC4<9:8> Yes IC4 – Input Capture 4 21 17 IFS0<21> IEC0<21> IPC4<12:10> IPC4<9:8> Yes OC4 – Output Compare 4 22 18 IFS0<22> IEC0<22> IPC4<20:18> IPC4<17:16> No INT4 – External Interrupt 4 23 19 IFS0<23> IEC0<23> IPC4<28:26> IPC4<25:24> No T5 – Timer5 24 20 IFS0<24> IEC0<24> IPC5<4:2> IPC5<1:0> No IC5E – Input Capture 5 Error 25 21 IFS0<25> IEC0<25> IPC5<12:10> IPC5<9:8> Yes IC5 – Input Capture 5 26 21 IFS0<26> IEC0<26> IPC5<12:10> IPC5<9:8> Yes OC5 – Output Compare 5 27 22 IFS0<27> IEC0<27> IPC5<20:18> IPC5<17:16> No AD1 – ADC1 Convert done 28 23 IFS0<28> IEC0<28> IPC5<28:26> IPC5<25:24> Yes FSCM – Fail-Safe Clock Monitor 29 24 IFS0<29> IEC0<29> IPC6<4:2> IPC6<1:0> No RTCC – Real-Time Clock and 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> No Calendar FCE – Flash Control Event 31 26 IFS0<31> IEC0<31> IPC6<20:18> IPC6<17:16> No CMP1 – Comparator Interrupt 32 27 IFS1<0> IEC1<0> IPC6<28:26> IPC6<25:24> No CMP2 – Comparator Interrupt 33 28 IFS1<1> IEC1<1> IPC7<4:2> IPC7<1:0> No CMP3 – Comparator Interrupt 34 29 IFS1<2> IEC1<2> IPC7<12:10> IPC7<9:8> No USB – USB Interrupts 35 30 IFS1<3> IEC1<3> IPC7<20:18> IPC7<17:16> Yes SPI1E – SPI1 Fault 36 31 IFS1<4> IEC1<4> IPC7<28:26> IPC7<25:24> Yes SPI1RX – SPI1 Receive Done 37 31 IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24> Yes SPI1TX – SPI1 Transfer Done 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> Yes Note 1: Not all interrupt sources are available on all devices. See TABLE 1:“PIC32MX1XX 28/36/44-Pin General Purpose Family Features” and TABLE 2:“PIC32MX2XX 28/36/44-pin USB Family Features” for the lists of available peripherals. DS60001168J-page 64  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Bit Location IRQ Vector Persistent Interrupt Source(1) # # Interrupt Flag Enable Priority Sub-priority U1E – UART1 Fault 39 32 IFS1<7> IEC1<7> IPC8<4:2> IPC8<1:0> Yes U1RX – UART1 Receive Done 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0> Yes U1TX – UART1 Transfer Done 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> Yes I2C1B – I2C1 Bus Collision Event 42 33 IFS1<10> IEC1<10> IPC8<12:10> IPC8<9:8> Yes I2C1S – I2C1 Slave Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8> Yes I2C1M – I2C1 Master Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> Yes CNA – PORTA Input Change 45 34 IFS1<13> IEC1<13> IPC8<20:18> IPC8<17:16> Yes Interrupt CNB – PORTB Input Change 46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16> Yes Interrupt CNC – PORTC Input Change 47 34 IFS1<15> IEC1<15> IPC8<20:18> IPC8<17:16> Yes Interrupt PMP – Parallel Master Port 48 35 IFS1<16> IEC1<16> IPC8<28:26> IPC8<25:24> Yes PMPE – Parallel Master Port Error 49 35 IFS1<17> IEC1<17> IPC8<28:26> IPC8<25:24> Yes SPI2E – SPI2 Fault 50 36 IFS1<18> IEC1<18> IPC9<4:2> IPC9<1:0> Yes SPI2RX – SPI2 Receive Done 51 36 IFS1<19> IEC1<19> IPC9<4:2> IPC9<1:0> Yes SPI2TX – SPI2 Transfer Done 52 36 IFS1<20> IEC1<20> IPC9<4:2> IPC9<1:0> Yes U2E – UART2 Error 53 37 IFS1<21> IEC1<21> IPC9<12:10> IPC9<9:8> Yes U2RX – UART2 Receiver 54 37 IFS1<22> IEC1<22> IPC9<12:10> IPC9<9:8> Yes U2TX – UART2 Transmitter 55 37 IFS1<23> IEC1<23> IPC9<12:10> IPC9<9:8> Yes I2C2B – I2C2 Bus Collision Event 56 38 IFS1<24> IEC1<24> IPC9<20:18> IPC9<17:16> Yes I2C2S – I2C2 Slave Event 57 38 IFS1<25> IEC1<25> IPC9<20:18> IPC9<17:16> Yes I2C2M – I2C2 Master Event 58 38 IFS1<26> IEC1<26> IPC9<20:18> IPC9<17:16> Yes CTMU – CTMU Event 59 39 IFS1<27> IEC1<27> IPC9<28:26> IPC9<25:24> Yes DMA0 – DMA Channel 0 60 40 IFS1<28> IEC1<28> IPC10<4:2> IPC10<1:0> No DMA1 – DMA Channel 1 61 41 IFS1<29> IEC1<29> IPC10<12:10> IPC10<9:8> No DMA2 – DMA Channel 2 62 42 IFS1<30> IEC1<30> IPC10<20:18> IPC10<17:16> No DMA3 – DMA Channel 3 63 43 IFS1<31> IEC1<31> IPC10<28:26> IPC10<25:24> No Lowest Natural Order Priority Note 1: Not all interrupt sources are available on all devices. See TABLE 1:“PIC32MX1XX 28/36/44-Pin General Purpose Family Features” and TABLE 2:“PIC32MX2XX 28/36/44-pin USB Family Features” for the lists of available peripherals.  2011-2016 Microchip Technology Inc. DS60001168J-page 65

D 7.1 Interrupt Control Registers P S 60 I 0 TABLE 7-2: INTERRUPT REGISTER MAP C 0 1 16 ss Bits 3 8J-page 66 Virtual Addre(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 AllResets 2MX 1 31:16 — — — — — — — — — — — — — — — — 0000 1000 INTCON X 15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 1010 INTSTAT(3) 15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000 /2 31:16 0000 X 1020 IPTMR IPTMR<31:0> 15:0 0000 X 31:16 FCEIF RTCCIF FSCMIF AD1IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000 1030 IFS0 15:0 IC3EIF T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000 2 31:16 DMA3IF DMA2IF DMA1IF DMA0IF CTMUIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF 0000 8 1040 IFS1 15:0 CNCIF CNBIF CNAIF I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF USBIF(2) CMP3IF CMP2IF CMP1IF 0000 / 3 31:16 FCEIE RTCCIE FSCMIE AD1IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000 1060 IEC0 6 15:0 IC3EIE T3IE INT2IE OC2IE IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000 / 31:16 DMA3IE DMA2IE DMA1IE DMA0IE CTMUIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE 0000 4 1070 IEC1 15:0 CNCIE CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE USBIE(2) CMP3IE CMP2IE CMP1IE 0000 4 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000 - 1090 IPC0 P 15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000 I 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000 N 10A0 IPC1 15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000 F 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000 10B0 IPC2 A 15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000  10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000 M 2 15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000 0 I 11 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 L -20 10D0 IPC4 15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000 Y 1 6 31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000 M 10E0 IPC5 ic 15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000 roch 10F0 IPC6 31:16 — — — CMP1IP<2:0> CMP1IS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000 ip 15:0 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000 T e Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c h Note 1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section11.2 “CLR, n o SET and INV Registers” for more information. lo g 2: These bits are not available on PIC32MX1XX devices. y In 3: This register does not have associated CLR, SET, INV registers. c .

 TABLE 7-2: INTERRUPT REGISTER MAP (CONTINUED) 2 01 ss Bits 1-2016 Micro Virtual Addre(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 AllResets chip T 1100 IPC7 3115::106 —— —— —— CSMPPI13IPIP<<22:0:0>> CSMPPI13ISIS<<11:0:0>> —— —— —— UCSMBPIP2I<P2<:02>:0(2>) UCSMBPIS2I<S1<:01>:0(>2) 00000000 ec 31:16 — — — PMPIP<2:0> PMPIS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000 h 1110 IPC8 P no 15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0> 0000 log 31:16 — — — CTMUIP<2:0> CTMUIS<1:0> — — — I2C2IP<2:0> I2C2IS<1:0> 0000 IC y 1120 IPC9 In 15:0 — — — U2IP<2:0> U2IS<1:0> — — — SPI2IP<2:0> SPI2IS<1:0> 0000 3 c . 1130 IPC10 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000 2 15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000 M Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section11.2 “CLR, X SET and INV Registers” for more information. 1 2: These bits are not available on PIC32MX1XX devices. X 3: This register does not have associated CLR, SET, INV registers. X / 2 X X 2 8 / 3 6 / 4 4 - P I N D S6 F 0 0 A 0 1 16 M 8 J -p I a L g e 6 Y 7

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 15:8 — — — MVEC — TPC<2:0> U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-13 Unimplemented: Read as ‘0’ bit 12 MVEC: Multi Vector Configuration bit 1 = Interrupt controller configured for Multi-vectored mode 0 = Interrupt controller configured for Single-vectored mode bit 11 Unimplemented: Read as ‘0’ bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits 111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer 110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer 101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer 100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer 011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer 010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer 001 = Interrupts of group priority 1 start the Interrupt Proximity timer 000 = Disables Interrupt Proximity timer bit 7-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge DS60001168J-page 68  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 7-2: INTSTAT: INTERRUPT STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 15:8 — — — — — SRIPL<2:0>(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — VEC<5:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as ‘0’ bit 10-8 SRIPL<2:0>: Requested Priority Level bits(1) 111-000 = The priority level of the latest interrupt presented to the CPU bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 VEC<5:0>: Interrupt Vector bits(1) 11111-00000 = The interrupt vector that is presented to the CPU Note 1: This value should only be used when the interrupt controller is configured for Single Vectormode. REGISTER 7-3: IPTMR: INTERRUPT PROXIMITY TIMER REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 IPTMR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 IPTMR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 IPTMR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 IPTMR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by an interrupt event.  2011-2016 Microchip Technology Inc. DS60001168J-page 69

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 7-4: IFSx: INTERRUPT FLAG STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS09 IFS08 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 IFS07 IFS06 IFS05 IFS04 IFS03 IFS02 IFS01 IFS00 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 IFS31-IFS00: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = No interrupt request has occurred Note: This register represents a generic definition of the IFSx register. Refer to Table7-1 for the exact bit definitions. REGISTER 7-5: IECx: INTERRUPT ENABLE CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC09 IEC08 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 IEC07 IEC06 IEC05 IEC04 IEC03 IEC02 IEC01 IEC00 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 IEC31-IEC00: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled Note: This register represents a generic definition of the IECx register. Refer to Table7-1 for the exact bit definitions. DS60001168J-page 70  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 — — — IP03<2:0> IS03<1:0> U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 — — — IP02<2:0> IS02<1:0> U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 — — — IP01<2:0> IS01<1:0> U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — — IP00<2:0> IS00<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-26 IP03<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 25-24 IS03<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 23-21 Unimplemented: Read as ‘0’ bit 20-18 IP02<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 IS02<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 15-13 Unimplemented: Read as ‘0’ bit 12-10 IP01<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled Note: This register represents a generic definition of the IPCx register. Refer to Table7-1 for the exact bit definitions.  2011-2016 Microchip Technology Inc. DS60001168J-page 71

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) bit 9-8 IS01<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 IP00<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 1-0 IS00<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note: This register represents a generic definition of the IPCx register. Refer to Table7-1 for the exact bit definitions. DS60001168J-page 72  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 8.0 OSCILLATOR The PIC32MX1XX/2XX 28/36/44-pin Family oscillator system has the following modules and features: CONFIGURATION • Four external and internal oscillator options as Note: This data sheet summarizes the features clock sources of the PIC32MX1XX/2XX 28/36/44-pin • On-Chip PLL with user-selectable input divider, Family of devices. It is not intended to be multiplier and output divider to boost operating a comprehensive reference source. To frequency on select internal and external complement the information in this data oscillator sources sheet, refer to Section 6. “Oscillator • On-Chip user-selectable divisor postscaler on Configuration” (DS60001112), which is select oscillator sources available from the Documentation > • Software-controllable switching between Reference Manual section of the various clock sources Microchip PIC32 web site • A Fail-Safe Clock Monitor (FSCM) that detects (www.microchip.com/pic32). clock failure and permits safe application recovery or shutdown • Dedicated On-Chip PLL for USB peripheral A block diagram of the oscillator system is provided in Figure8-1.  2011-2016 Microchip Technology Inc. DS60001168J-page 73

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 8-1: OSCILLATOR DIAGRAM USB PLL(4) USB Clock (48 MHz) UFIN div x PLL x24 div 2 UFRCEN UFIN 4 MHz UPLLEN UPLLIDIV<2:0> ROTRIM<8:0> REFCLKI (M) OE POSC FRC LPRC REFCLKO System PLL SOSC 2N+5---M-1---2--- PBCLK 4 MHz FIN 5 MHz SYSCLK FIN div x PLL To SPI RODIV<14:0> (N) FPLLIDIV<2:0> ROSEL<3:0> COSC<2:0> PLLMULT<2:0> div y XTPLL, HSPLL, ECPLL, FRCPLL PLLODIV<2:0> Primary Oscillator (POSC) C1(2) OSC1 Postscaler Peripherals XTAL TLoo gInicternal POSC (XT, HS, EC) div x PBCLK (TPB) RP(1) 3x 1x HS XT FRC PBDIV<1:0> C2(2) RS(1) OSC2(3) div 16 div 2 FRC/16 To ADC CPU and Select Peripherals FRC Oscillator Postscaler SYSCLK 8 MHz typical FRCDIV TUN<5:0> FRCDIV<2:0> Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSC SOSCEN and FSOSCEN LPRC SOSCI Oscillator 31.25 kHz typical LPRC Clock Control Logic FSCM INT Fail-Safe Clock FSCM Event Monitor NOSC<2:0> COSC<2:0> FSCMEN<1:0> OSWEN WDT, PWRT Timer1, RTCC Notes: 1. A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain, add a parallel resistor, RP, with a value of 1 M 2. Refer to Section 6. “Oscillator Configuration” (DS60001112) in the “PIC32 Family Reference Manual” for help in determining the best oscillator components. 3. The PBCLK out is only available on the OSC2 pin in certain clock modes. 4. The USB PLL is only available on PIC32MX2XX devices. DS60001168J-page 74  2011-2016 Microchip Technology Inc.

 8.1 Oscillator Control Regiters 2 0 1 TABLE 8-1: OSCILLATOR CONTROL REGISTER MAP 1 -2016 Microchip Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bi2ts3/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T e 31:16 — — PLLODIV<2:0> FRCDIV<2:0> — SOSCRDYPBDIVRDY PBDIV<1:0> PLLMULT<2:0> x1xx(2) chn F000 OSCCON 15:0 — COSC<2:0> — NOSC<2:0> CLKLOCK ULOCK(3) SLOCK SLPEN CF UFRCEN(3) SOSCEN OSWEN xxxx(2) P o log F010 OSCTUN 31:16 — — — — — — — — — — — — — — — — 0000 IC y 15:0 — — — — — — — — — — TUN<5:0> 0000 Inc. F020 REFOCON 3115:1:06 O—N — SIDL OE RSLP — DIVSWEN ACTIVE RO—DIV<14:0>— — — ROSEL<3:0> 00000000 32 31:16 ROTRIM<8:0> — — — — — — — 0000 M F030 REFOTRIM 15:0 — — — — — — — — — — — — — — — — 0000 X Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more information. X 2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. X 3: This bit is only available on PIC32MX2XX devices. / 2 X X 2 8 / 3 6 / 4 4 - P I N D S6 F 0 0 A 0 1 16 M 8 J -p I a L g e 7 Y 5

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 R/W-y R/W-y R/W-y R/W-0 R/W-0 R/W-1 31:24 — — PLLODIV<2:0> FRCDIV<2:0> U-0 R-0 R-1 R/W-y R/W-y R/W-y R/W-y R/W-y 23:16 — SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0> U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y 15:8 — COSC<2:0> — NOSC<2:0> R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0 7:0 CLKLOCK ULOCK(1) SLOCK SLPEN CF UFRCEN(1) SOSCEN OSWEN Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29-27 PLLODIV<2:0>: Output Divider for PLL 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 bit 23 Unimplemented: Read as ‘0’ bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit 1 = The Secondary Oscillator is running and is stable 0 = The Secondary Oscillator is still warming up or is turned off bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit 1 = PBDIV<1:0> bits can be written 0 = PBDIV<1:0> bits cannot be written bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits 11 = PBCLK is SYSCLK divided by 8 (default) 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note 1: This bit is only available on PIC32MX2XX devices. Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details. DS60001168J-page 76  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (OSCCON<26:24>) 110 = Internal Fast RC (FRC) Oscillator divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (POSC) (XT, HS or EC) 001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast RC (FRC) Oscillator bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits 111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC Oscillator (FRC) divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast Internal RC Oscillator (FRC) On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). bit 7 CLKLOCK: Clock Selection Lock Enable bit If clock switching and monitoring is disabled (FCKSM<1:0> = 1x): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified If clock switching and monitoring is enabled (FCKSM<1:0> = 0x): Clock and PLL selections are never locked and may be modified. bit 6 ULOCK: USB PLL Lock Status bit(1) 1 = The USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 =The USB PLL module is out of lock or USB PLL module start-up timer is in progress or the USB PLL is disabled bit 5 SLOCK: PLL Lock Status bit 1 = The PLL module is in lock or PLL module start-up timer is satisfied 0 = The PLL module is out of lock, the PLL start-up timer is running, or the PLL is disabled bit 4 SLPEN: Sleep Mode Enable bit 1 = The device will enter Sleep mode when a WAIT instruction is executed 0 = The device will enter Idle mode when a WAIT instruction is executed Note 1: This bit is only available on PIC32MX2XX devices. Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.  2011-2016 Microchip Technology Inc. DS60001168J-page 77

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 UFRCEN: USB FRC Clock Enable bit(1) 1 = Enable the FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable the Secondary Oscillator 0 = Disable the Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: This bit is only available on PIC32MX2XX devices. Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details. DS60001168J-page 78  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 8-2: OSCTUN: FRC TUNING REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — TUN<5:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 100000 = Center frequency -12.5% 100001 = • • • 111111 = 000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz) 000001 = • • • 011110 = 011111 = Center frequency +12.5% Note1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized, nor tested. Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.  2011-2016 Microchip Technology Inc. DS60001168J-page 79

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 8-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 — RODIV<14:8>(1,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 RODIV<7:0>(1,3) R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC 15:8 ON — SIDL OE RSLP(2) — DIVSWEN ACTIVE U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — — — ROSEL<3:0>(1) Legend: HC = Hardware Clearable HS = Hardware Settable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 Unimplemented: Read as ‘0’ bit 30-16 RODIV<14:0> Reference Clock Divider bits(1,3) The value selects the reference clock divider bits. See Figure8-1 for information. bit 15 ON: Output Enable bit 1 = Reference Oscillator module is enabled 0 = Reference Oscillator module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Peripheral Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12 OE: Reference Clock Output Enable bit 1 = Reference clock is driven out on REFCLKO pin 0 = Reference clock is not driven out on REFCLKO pin bit 11 RSLP: Reference Oscillator Module Run in Sleep bit(2) 1 = Reference Oscillator module output continues to run in Sleep 0 = Reference Oscillator module output is disabled in Sleep bit 10 Unimplemented: Read as ‘0’ bit 9 DIVSWEN: Divider Switch Enable bit 1 = Divider switch is in progress 0 = Divider switch is complete bit 8 ACTIVE: Reference Clock Request Status bit 1 = Reference clock request is active 0 = Reference clock request is not active bit 7-4 Unimplemented: Read as ‘0’ Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result. 2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001. 3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to’1’. DS60001168J-page 80  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 8-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits(1) 1111 = Reserved; do not use • • • 1001 = Reserved; do not use 1000 =REFCLKI 0111 =System PLL output 0110 =USB PLL output 0101 =SOSC 0100 =LPRC 0011 =FRC 0010 =POSC 0001 =PBCLK 0000 =SYSCLK Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result. 2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001. 3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to’1’.  2011-2016 Microchip Technology Inc. DS60001168J-page 81

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 8-4: REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 ROTRIM<8:1> R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 ROTRIM<0> — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 7:0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits 111111111 = 511/512 divisor added to RODIV value 111111110 = 510/512 divisor added to RODIV value • • • 100000000 = 256/512 divisor added to RODIV value • • • 000000010 = 2/512 divisor added to RODIV value 000000001 = 1/512 divisor added to RODIV value 000000000 = 0/512 divisor added to RODIV value bit 22-0 Unimplemented: Read as ‘0’ Note: While the ON (REFOCON<15>) bit is ‘1’, writes to this register do not take effect until the DIVSWEN bit is also set to ‘1’. DS60001168J-page 82  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 9.0 DIRECT MEMORY ACCESS • Fixed priority channel arbitration (DMA) CONTROLLER • Flexible DMA channel operating modes: - Manual (software) or automatic (interrupt) Note: This data sheet summarizes the features DMA requests of the PIC32MX1XX/2XX 28/36/44-pin - One-Shot or Auto-Repeat Block Transfer Family of devices. It is not intended to be modes a comprehensive reference source. To - Channel-to-channel chaining complement the information in this data • Flexible DMA requests: sheet, refer to Section 31. “Direct Mem- - A DMA request can be selected from any of ory Access (DMA) Controller” the peripheral interrupt sources (DS60001117), which is available from the - Each channel can select any (appropriate) Documentation > Reference Manual observable interrupt as its DMA request section of the Microchip PIC32 web site source (www.microchip.com/pic32). - A DMA transfer abort can be selected from The PIC32 Direct Memory Access (DMA) controller is a any of the peripheral interrupt sources bus master module useful for data transfers between - Pattern (data) match transfer termination different devices without CPU intervention. The source • Multiple DMA channel status interrupts: and destination of a DMA transfer can be any of the - DMA channel block transfer complete memory mapped modules existent in the PIC32, such - Source empty or half empty as Peripheral Bus devices: SPI, UART, PMP, etc., or - Destination full or half full memory itself. Figure9-1 show a block diagram of the - DMA transfer aborted due to an external DMA Controller module. event The DMA Controller module has the following key - Invalid DMA address generated features: • DMA debug support features: • Four identical channels, each featuring: - Most recent address accessed by a DMA - Auto-increment source and destination channel address registers - Most recent DMA channel to transfer data - Source and destination pointers • CRC Generation module: - Memory to memory and memory to - CRC module can be assigned to any of the peripheral transfers available channels • Automatic word-size detection: - CRC module is highly configurable - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination FIGURE 9-1: DMA BLOCK DIAGRAM Interrupt System IRQ Controller Peripheral Bus DAedcdoredsesr CChaonnntreoll 0 I0SEL CChaonnntreoll 1 I1 Y IntBerufasce DBeuvsi cAer bBitursa taionnd I2 Global Control Channel n In (DMACON) Control S E L Channel Priority Arbitration  2011-2016 Microchip Technology Inc. DS60001168J-page 83

D 9.1 DMA Control Registers P S 600 TABLE 9-1: DMA GLOBAL REGISTER MAP IC 0 1168J-page 84 Virtual Address(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 1 31:16 — — — — — — — — — — — — — — — — 0000 3000 DMACON X 15:0 ON — — SUSPENDDMABUSY — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 3010 DMASTAT 15:0 — — — — — — — — — — — — RDWR DMACH<2:0>(2) 0000 / 31:16 0000 2 3020 DMAADDR DMAADDR<31:0> 15:0 0000 X Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more information. 2 8 / TABLE 9-2: DMA CRC REGISTER MAP 3 6 s Bits Virtual Addres(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets /44-P I 31:16 — — BYTO<1:0> WBO — — BITO — — — — — — — — 0000 N 3030 DCRCCON 15:0 — — — PLEN<4:0> CRCEN CRCAPP CRCTYP — — CRCCH<2:0> 0000 31:16 0000 F 3040 DCRCDATA DCRCDATA<31:0> 15:0 0000 A 31:16 0000 3050 DCRCXOR DCRCXOR<31:0> M  15:0 0000 20 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I 1 L 1 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for -20 more information. Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 9-3: DMA CHANNELS 0-3 REGISTER MAP 2 01 ss Bits 1-2016 Micro Virtual Addre(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets chip T 3060 DCH0CON 3115::106 CHB—USY —— —— —— —— —— —— CHC—HNS CH—EN CH—AED CH—CHN CH—AEN —— CHE—DET —CHPRI<1:0—> 00000000 echn 3070 DCH0ECON3115:1:06 — — — C—HSIRQ<7:—0> — — — CFORCE CABORT PATEN SIRCQHEANIRQA<7IR:0Q>EN — — — 0F0FF0F0 P o lo 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 I g 3080 DCH0INT C y 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 Inc. 3090 DCH0SSA 3115:1:06 CHSSA<31:0> 00000000 32 31:16 0000 M 30A0 DCH0DSA CHDSA<31:0> 15:0 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 30B0 DCH0SSIZ 15:0 CHSSIZ<15:0> 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 X 30C0 DCH0DSIZ 15:0 CHDSIZ<15:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 30D0 DCH0SPTR / 15:0 CHSPTR<15:0> 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 X 30E0 DCH0DPTR 15:0 CHDPTR<15:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 30F0 DCH0CSIZ 15:0 CHCSIZ<15:0> 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 8 3100 DCH0CPTR 15:0 CHCPTR<15:0> 0000 / 3 31:16 — — — — — — — — — — — — — — — — 0000 3110 DCH0DAT 15:0 — — — — — — — — CHPDAT<7:0> 0000 6 3120 DCH1CON 31:16 — — — — — — — — — — — — — — — — 0000 /4 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000 4 31:16 — — — — — — — — CHAIRQ<7:0> 00FF 3130 DCH1ECON - 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00 P 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 3140 DCH1INT I 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 N DS6 3150 DCH1SSA 3115:1:06 CHSSA<31:0> 00000000 F 0 00116 3160 DCH1DSA 3115:1:06 CHDSA<31:0> 00000000 AM 8 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. J -p Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for I ag more information. L e 8 Y 5

D TABLE 9-3: DMA CHANNELS 0-3 REGISTER MAP (CONTINUED) P S 60001168J-pag Virtual Address(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets IC32M e 8 3170 DCH1SSIZ 31:16 — — — — — — — — — — — — — — — — 0000 X 6 15:0 CHSSIZ<15:0> 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 3180 DCH1DSIZ X 15:0 CHDSIZ<15:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 3190 DCH1SPTR 15:0 CHSPTR<15:0> 0000 / 2 31:16 — — — — — — — — — — — — — — — — 0000 31A0 DCH1DPTR X 15:0 CHDPTR<15:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 31B0 DCH1CSIZ 15:0 CHCSIZ<15:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 2 31C0 DCH1CPTR 15:0 CHCPTR<15:0> 0000 8 31:16 — — — — — — — — — — — — — — — — 0000 / 31D0 DCH1DAT 3 15:0 — — — — — — — — CHPDAT<7:0> 0000 6 31:16 — — — — — — — — — — — — — — — — 0000 31E0 DCH2CON / 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000 4 31:16 — — — — — — — — CHAIRQ<7:0> 00FF 4 31F0DCH2ECON 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00 - 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 P 3200 DCH2INT 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 I N 31:16 0000 3210 DCH2SSA CHSSA<31:0> 15:0 0000 F 31:16 0000 3220 DCH2DSA CHDSA<31:0> A 15:0 0000 31:16 — — — — — — — — — — — — — — — — 0000 M  3230 DCH2SSIZ 2 15:0 CHSSIZ<15:0> 0000 0 I 1 31:16 — — — — — — — — — — — — — — — — 0000 L 1 3240 DCH2DSIZ -20 15:0 CHDSIZ<15:0> 0000 Y 1 31:16 — — — — — — — — — — — — — — — — 0000 6 3250 DCH2SPTR M 15:0 CHSPTR<15:0> 0000 icro 3260 DCH2DPTR 31:16 — — — — — — — — — — — — — — — — 0000 ch 15:0 CHDPTR<15:0> 0000 ip T 3270 DCH2CSIZ 31:16 — — — — — — — — — — — — — — — — 0000 e 15:0 CHCSIZ<15:0> 0000 c hn Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. o lo Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for g more information. y In c .

 TABLE 9-3: DMA CHANNELS 0-3 REGISTER MAP (CONTINUED) 2 01 ss Bits 1-2016 Micro Virtual Addre(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets ch 31:16 — — — — — — — — — — — — — — — — 0000 ip 3280 DCH2CPTR T 15:0 CHCPTR<15:0> 0000 e chn 3290 DCH2DAT 31:16 — — — — — — — — — — — — — — — — 0000 P o 15:0 — — — — — — — — CHPDAT<7:0> 0000 lo I g 31:16 — — — — — — — — — — — — — — — — 0000 C y 32A0 DCH3CON In 15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000 3 c . 32B0DCH3ECON31:16 — — — — — — — — CHAIRQ<7:0> 00FF 2 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00 M 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 32C0 DCH3INT 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 X 32D0 DCH3SSA 31:16 CHSSA<31:0> 0000 1 15:0 0000 X 31:16 0000 32E0 DCH3DSA CHDSA<31:0> X 15:0 0000 31:16 — — — — — — — — — — — — — — — — 0000 / 32F0 DCH3SSIZ 2 15:0 CHSSIZ<15:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 3300 DCH3DSIZ X 15:0 CHDSIZ<15:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 3310 DCH3SPTR 2 15:0 CHSPTR<15:0> 0000 8 31:16 — — — — — — — — — — — — — — — — 0000 3320 DCH3DPTR / 15:0 CHDPTR<15:0> 0000 3 31:16 — — — — — — — — — — — — — — — — 0000 6 3330 DCH3CSIZ 15:0 CHCSIZ<15:0> 0000 / 31:16 — — — — — — — — — — — — — — — — 0000 4 3340 DCH3CPTR 15:0 CHCPTR<15:0> 0000 4 31:16 — — — — — — — — — — — — — — — — 0000 - 3350 DCH3DAT P 15:0 — — — — — — — — CHPDAT<7:0> 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IN Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for DS6 more information. F 0 0 A 0 1 16 M 8 J -p I a L g e 8 Y 7

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-1: DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 15:8 ON(1) — — SUSPEND DMABUSY — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 7:0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: DMA On bit(1) 1 = DMA module is enabled 0 = DMA module is disabled bit 14-13 Unimplemented: Read as ‘0’ bit 12 SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally bit 11 DMABUSY: DMA Module Busy bit 1 = DMA module is active 0 = DMA module is disabled and not actively transferring data bit 10-0 Unimplemented: Read as ‘0’ Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. DS60001168J-page 88  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-2: DMASTAT: DMA STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 7:0 — — — — RDWR DMACH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3 RDWR: Read/Write Status bit 1 = Last DMA bus access was a read 0 = Last DMA bus access was a write bit 2-0 DMACH<2:0>: DMA Channel bits These bits contain the value of the most recent active DMA channel. REGISTER 9-3: DMAADDR: DMA ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 31:24 DMAADDR<31:24> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 23:16 DMAADDR<23:16> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 15:8 DMAADDR<15:8> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 DMAADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DMAADDR<31:0>: DMA Module Address bits These bits contain the address of the most recent DMA access.  2011-2016 Microchip Technology Inc. DS60001168J-page 89

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-4: DCRCCON: DMA CRC CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 31:24 — — BYTO<1:0> WBO(1) — — BITO U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 — — — PLEN<4:0> R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 7:0 CRCEN CRCAPP(1) CRCTYP — — CRCCH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits 11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order per half-word) 10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per half-word) 01 = Endian byte swap on word boundaries (i.e., reverse source byte order) 00 = No swapping (i.e., source byte order) bit 27 WBO: CRC Write Byte Order Selection bit(1) 1 = Source data is written to the destination re-ordered as defined by BYTO<1:0> 0 = Source data is written to the destination unaltered bit 26-25 Unimplemented: Read as ‘0’ bit 24 BITO: CRC Bit Order Selection bit When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): 1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected) 0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected) When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): 1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected) 0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected) bit 23-13 Unimplemented: Read as ‘0’ bit 12-8 PLEN<4:0>: Polynomial Length bits When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): These bits are unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): Denotes the length of the polynomial – 1. bit 7 CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. DS60001168J-page 90  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA 0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination bit 5 CRCTYP: CRC Type Selection bit 1 = The CRC module will calculate an IP header checksum 0 = The CRC module will calculate a LFSR CRC bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 CRCCH<2:0>: CRC Channel Select bits 111 = CRC is assigned to Channel 7 110 = CRC is assigned to Channel 6 101 = CRC is assigned to Channel 5 100 = CRC is assigned to Channel 4 011 = CRC is assigned to Channel 3 010 = CRC is assigned to Channel 2 001 = CRC is assigned to Channel 1 000 = CRC is assigned to Channel 0 Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.  2011-2016 Microchip Technology Inc. DS60001168J-page 91

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-5: DCRCDATA: DMA CRC DATA REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 DCRCDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 DCRCDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 DCRCDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 DCRCDATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DCRCDATA<31:0>: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return ‘0’ on any read. When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value). When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): Bits greater than PLEN will return ‘0’ on any read. REGISTER 9-6: DCRCXOR: DMA CRCXOR ENABLE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 DCRCXOR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 DCRCXOR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 DCRCXOR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 DCRCXOR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): This register is unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): 1 = Enable the XOR input to the Shift register 0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in theregister DS60001168J-page 92  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-7: DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 15:8 CHBUSY — — — — — — CHCHNS(1) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0 7:0 CHEN(2) CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 CHBUSY: Channel Busy bit 1 = Channel is active or has been enabled 0 = Channel is inactive or has been disabled bit 14-9 Unimplemented: Read as ‘0’ bit 8 CHCHNS: Chain Channel Selection bit(1) 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) bit 7 CHEN: Channel Enable bit(2) 1 = Channel is enabled 0 = Channel is disabled bit 6 CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled bit CHCHN: Channel Chain Enable bit 1 = Allow channel to be chained 0 = Do not allow channel to be chained bit 4 CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete bit 3 Unimplemented: Read as ‘0’ bit 2 CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected bit 1-0 CHPRI<1:0>: Channel Priority bits 11 = Channel has priority 3 (highest) 10 = Channel has priority 2 01 = Channel has priority 1 00 = Channel has priority 0 Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1). 2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended.  2011-2016 Microchip Technology Inc. DS60001168J-page 93

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-8: DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 23:16 CHAIRQ<7:0>(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 15:8 CHSIRQ<7:0>(1) S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 7:0 CFORCE CABORT PATEN SIRQEN AIRQEN — — — Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1) 11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag • • • 00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1) 11111111 = Interrupt 255 will initiate a DMA transfer • • • 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer bit 7 CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a ‘1’ 0 = This bit always reads ‘0’ bit 6 CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a ‘1’ 0 = This bit always reads ‘0’ bit 5 PATEN: Channel Pattern Match Abort Enable bit 1 = Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled bit 4 SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs 0 = Interrupt number CHSIRQ is ignored and does not start a transfer bit 3 AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer bit 2-0 Unimplemented: Read as ‘0’ Note 1: See Table 7-1:“Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources. DS60001168J-page 94  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23 CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 16 CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 15-8 Unimplemented: Read as ‘0’ bit 7 CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTR=CHSSIZ) 0 = No interrupt is pending bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTR=CHSSIZ/2) 0 = No interrupt is pending bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR=CHDSIZ) 0 = No interrupt is pending  2011-2016 Microchip Technology Inc. DS60001168J-page 95

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED) bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR=CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs 0 = No interrupt is pending bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending bit 0 CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected (either the source or the destination address is invalid) 0 = No interrupt is pending DS60001168J-page 96  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 CHSSA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 CHSSA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 CHSSA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CHSSA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 CHSSA<31:0> Channel Source Start Address bits Channel source start address. Note: This must be the physical address of the source. REGISTER 9-11: DCHxDSA: DMA CHANNEL ‘x’ DESTINATION START ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 CHDSA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 CHDSA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 CHDSA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CHDSA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits Channel destination start address. Note:This must be the physical address of the destination.  2011-2016 Microchip Technology Inc. DS60001168J-page 97

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 CHSSIZ<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CHSSIZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHSSIZ<15:0>: Channel Source Size bits 1111111111111111 = 65,535 byte source size • • • 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size REGISTER 9-13: DCHxDSIZ: DMA CHANNEL ‘x’ DESTINATION SIZE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 CHDSIZ<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CHDSIZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits 1111111111111111 = 65,535 byte destination size • • • 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size DS60001168J-page 98  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 15:8 CHSPTR<15:8> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 CHSPTR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits 1111111111111111 = Points to byte 65,535 of the source • • • 0000000000000001 = Points to byte 1 of the source 0000000000000000 = Points to byte 0 of the source Note: When in Pattern Detect mode, this register is reset on a pattern detect. REGISTER 9-15: DCHxDPTR: DMA CHANNEL ‘x’ DESTINATION POINTER REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 15:8 CHDPTR<15:8> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 CHDPTR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits 1111111111111111 = Points to byte 65,535 of the destination • • • 0000000000000001 = Points to byte 1 of the destination 0000000000000000 = Points to byte 0 of the destination  2011-2016 Microchip Technology Inc. DS60001168J-page 99

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 CHCSIZ<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CHCSIZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHCSIZ<15:0>: Channel Cell Size bits 1111111111111111 = 65,535 bytes transferred on an event • • • 0000000000000010 = 2 bytes transferred on an event 0000000000000001= 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event REGISTER 9-17: DCHxCPTR: DMA CHANNEL ‘x’ CELL POINTER REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 15:8 CHCPTR<15:8> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 CHCPTR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHCPTR<15:0>: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event • • • 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event Note: When in Pattern Detect mode, this register is reset on a pattern detect. DS60001168J-page 100  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 9-18: DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CHPDAT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 CHPDAT<7:0>: Channel Data Register bits Pattern Terminate mode: Data to be matched must be stored in this register to allow a “terminate on match”. All other modes: Unused.  2011-2016 Microchip Technology Inc. DS60001168J-page 101

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 102  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 10.0 USB ON-THE-GO (OTG) The PIC32 USB module includes the following features: Note: This data sheet summarizes the features • USB Full-Speed support for Host and Device of the PIC32MX1XX/2XX 28/36/44-pin • Low-Speed Host support Family of devices. It is not intended to be a comprehensive reference source. To • USB OTG support complement the information in this data • Integrated signaling resistors sheet, refer to Section 27. “USB On-The- • Integrated analog comparators for VBUS Go (OTG)” (DS60001126), which is avail- monitoring able from the Documentation > Reference • Integrated USB transceiver Manual section of the Microchip PIC32 • Transaction handshaking performed by hardware web site (www.microchip.com/pic32). • Endpoint buffering anywhere in system RAM The Universal Serial Bus (USB) module contains • Integrated DMA to access system RAM and Flash analog and digital components to provide a USB 2.0 Note: The implementation and use of the USB Full-Speed and Low-Speed embedded host, Full- specifications, as well as other third party Speed device or OTG implementation with a minimum specifications or technologies, may of external components. This module in Host mode is require licensing; including, but not limited intended for use as an embedded host and therefore to, USB Implementers Forum, Inc., also does not implement a UHCI or OHCI controller. referred to as USB-IF (www.usb.org). The The USB module consists of the clock generator, the user is fully responsible for investigating USB voltage comparators, the transceiver, the Serial and satisfying any applicable licensing Interface Engine (SIE), a dedicated USB DMA control- obligations. ler, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure10-1. The clock generator provides the 48 MHz clock required for USB Full-Speed and Low-Speed communi- cation. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The inte- grated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module.  2011-2016 Microchip Technology Inc. DS60001168J-page 103

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 10-1: PIC32MX1XX/2XX 28/36/44-PIN FAMILY FAMILY USB INTERFACE DIAGRAM FRC Oscillator 8MHzTypical TUN<5:0>(3) Primary Oscillator (POSC) UFIN(4) Divx PLL Div2 UFRCEN(2) OSC1 UPLLIDIV(5) UPLLEN(5) OSC2 USB Module USB SRPCharge Voltage Bus Comparators SRPDischarge 48 MHz USB Clock(6) FullSpeedPull-up D+(1) Registers and Control HostPull-down Interface SIE Transceiver LowSpeedPull-up D-(1) DMA System RAM HostPull-down ID Pull-up ID(1) VBUSON(1) VUSB3V3 Transceiver Power 3.3V Note 1: Pins can be used as digital input/output when USB is not enabled. 2: This bit field is contained in the OSCCON register. 3: This bit field is contained in the OSCTRM register. 4: USB PLL UFIN requirements: 4 MHz. 5: This bit field is contained in the DEVCFG2 register. 6: A 48 MHz clock is required for proper USB operation. DS60001168J-page 104  2011-2016 Microchip Technology Inc.

 10.1 USB Control Registers 2 0 1 TABLE 10-1: USB REGISTER MAP 1 -2016 Microchip Virtual Address(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 Bits 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T ec 5040 U1OTGIR(2) 31:16 — — — — — — — — — — — — — — — — 0000 hn 15:0 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000 P ology 5050 U1OTGIE 3115::106 —— —— —— —— —— —— —— —— ID—IE T1M—SECIE LSTA—TEIE AC—TVIE SES—VDIE SESE—NDIE —— VBU—SVDIE 00000000 IC In 31:16 — — — — — — — — — — — — — — — — 0000 3 c 5060 U1OTGSTAT(3) . 15:0 — — — — — — — — ID — LSTATE — SESVD SESEND — VBUSVD 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 M 5070 U1OTGCON 15:0 — — — — — — — — DPPULUP DMPULUPDPPULDWNDMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 5080 U1PWRC 15:0 — — — — — — — — UACTPND(4) — — USLPGRD USBBUSY — USUSPEND USBPWR 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 X 5200 U1IR(2) 15:0 — — — — — — — — STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF 0000 X DETACHIF 0000 / 31:16 — — — — — — — — — — — — — — — — 0000 2 5210 U1IE URSTIE 0000 X 15:0 — — — — — — — — STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE DETACHIE 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 5220 U1EIR(2) 15:0 — — — — — — — — BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0000 2 EOFEF 0000 8 31:16 — — — — — — — — — — — — — — — — 0000 / 5230 U1EIE CRC5EE 0000 3 15:0 — — — — — — — — BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE PIDEE EOFEE 0000 6 31:16 — — — — — — — — — — — — — — — — 0000 / 5240 U1STAT(3) 4 15:0 — — — — — — — — ENDPT<3:0> DIR PPBI — — 0000 4 31:16 — — — — — — — — — — — — — — — — 0000 - 5250 U1CON 15:0 — — — — — — — — JSTATE SE0 PKTDIS USBRST HOSTEN RESUME PPBRST USBEN 0000 P TOKBUSY SOFEN 0000 I 31:16 — — — — — — — — — — — — — — — — 0000 N DS 5260 U1ADDR 15:0 — — — — — — — — LSPDEN DEVADDR<6:0> 0000 600 5270 U1BDTP1 31:16 — — — — — — — — — — — — — — — — 0000 F 0 15:0 — — — — — — — — BDTPTRL<15:9> — 0000 A 1 1 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 68 Note 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8, and 0xC respectively. M J -pag 2: STheies Sreegcitsitoenr d11o.e2s “ nCoLt Rh,a SveE Ta sasnodc iIaNteVd R SeEgTis atenrds ”IN foVr rmegoirset einrsfo.rmation. IL e 1 3: This register does not have associated CLR, SET and INV registers. Y 0 4: Reset value for this bit is undefined. 5

D TABLE 10-1: USB REGISTER MAP (CONTINUED) P S 60001168J-pag Virtual Address(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 Bits 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets IC32M e 1 5280 U1FRML(3) 31:16 — — — — — — — — — — — — — — — — 0000 X 06 15:0 — — — — — — — — FRML<7:0> 0000 1 5290 U1FRMH(3) 31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 — — — — — — — — — — — — — FRMH<2:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 52A0 U1TOK 15:0 — — — — — — — — PID<3:0> EP<3:0> 0000 / 2 31:16 — — — — — — — — — — — — — — — — 0000 52B0 U1SOF X 15:0 — — — — — — — — CNT<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 52C0 U1BDTP2 15:0 — — — — — — — — BDTPTRH<7:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 2 52D0 U1BDTP3 15:0 — — — — — — — — BDTPTRU<7:0> 0000 8 31:16 — — — — — — — — — — — — — — — — 0000 / 52E0 U1CNFG1 3 15:0 — — — — — — — — UTEYE UOEMON — USBSIDL — — — UASUSPND 0001 6 31:16 — — — — — — — — — — — — — — — — 0000 5300 U1EP0 / 15:0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 4 31:16 — — — — — — — — — — — — — — — — 0000 4 5310 U1EP1 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 - 31:16 — — — — — — — — — — — — — — — — 0000 P 5320 U1EP2 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 I N 31:16 — — — — — — — — — — — — — — — — 0000 5330 U1EP3 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 F 31:16 — — — — — — — — — — — — — — — — 0000 5340 U1EP4 A 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 31:16 — — — — — — — — — — — — — — — — 0000 M  5350 U1EP5 2 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 0 I 1 31:16 — — — — — — — — — — — — — — — — 0000 L 1 5360 U1EP6 -20 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 Y 1 31:16 — — — — — — — — — — — — — — — — 0000 6 5370 U1EP7 M 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 icro 5380 U1EP8 31:16 — — — — — — — — — — — — — — — — 0000 ch 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 ip T Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. e Note 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8, and 0xC respectively. ch See Section11.2 “CLR, SET and INV Registers” for more information. no 2: This register does not have associated SET and INV registers. lo 3: This register does not have associated CLR, SET and INV registers. g y In 4: Reset value for this bit is undefined. c .

 TABLE 10-1: USB REGISTER MAP (CONTINUED) 2 01 ss Bits 1-2016 Micro Virtual Addre(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets chip T 5390 U1EP9 3115::106 —— —— —— —— —— —— —— —— —— —— —— EPCO—NDIS EPR—XEN EPT—XEN EPS—TALL EPH—SHK 00000000 e 31:16 — — — — — — — — — — — — — — — — 0000 chn 53A0 U1EP10 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 P o log 53B0 U1EP11 31:16 — — — — — — — — — — — — — — — — 0000 IC y 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 Inc. 53C0 U1EP12 3115::106 —— —— —— —— —— —— —— —— —— —— —— EPCO—NDIS EPR—XEN EPT—XEN EPS—TALL EPH—SHK 00000000 32 31:16 — — — — — — — — — — — — — — — — 0000 M 53D0 U1EP13 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 53E0 U1EP14 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 X 53F0 U1EP15 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 X Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / Note 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8, and 0xC respectively. 2 See Section11.2 “CLR, SET and INV Registers” for more information. X 2: This register does not have associated SET and INV registers. 3: This register does not have associated CLR, SET and INV registers. X 4: Reset value for this bit is undefined. 2 8 / 3 6 / 4 4 - P I N D S 60 F 0 0 A 1 1 68 M J -pa I g L e 1 Y 0 7

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-1: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS 7:0 IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 IDIF: ID State Change Indicator bit 1 = A change in the ID state was detected 0 = No change in the ID state was detected bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state has been stable for 1ms, but different from last time 0 = USB line state has not been stable for 1ms bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up 0 = Activity has not been detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS voltage has dropped below the session end level 0 = VBUS voltage has not dropped below the session end level bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = A change on the session end input was detected 0 = No change on the session end input was detected bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = A change on the session valid input was detected 0 = No change on the session valid input was detected DS60001168J-page 108  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-2: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 7:0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interrupt Enable bit 1 = ID interrupt is enabled 0 = ID interrupt is disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = 1 millisecond timer interrupt is enabled 0 = 1 millisecond timer interrupt is disabled bit 5 LSTATEIE: Line State Interrupt Enable bit 1 = Line state interrupt is enabled 0 = Line state interrupt is disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = Activity interrupt is enabled 0 = Activity interrupt is disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Session valid interrupt is enabled 0 = Session valid interrupt is disabled bit 2 SESENDIE: B-Device Session End Interrupt Enable bit 1 = B-Device session end interrupt is enabled 0 = B-Device session end interrupt is disabled bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = A-Device VBUS valid interrupt is enabled 0 = A-Device VBUS valid interrupt is disabled  2011-2016 Microchip Technology Inc. DS60001168J-page 109

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-3: U1OTGSTAT: USB OTG STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 7:0 ID — LSTATE — SESVD SESEND — VBUSVD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 ID: ID Pin State Indicator bit 1 = No cable is attached or a “type B” cable has been inserted into the USB receptacle 0 = A “type A” OTG cable has been inserted into the USB receptacle bit 6 Unimplemented: Read as ‘0’ bit 5 LSTATE: Line State Stable Indicator bit 1 = USB line state (SE0 (U1CON<6>) bit and JSTATE (U1CON<7>)) bit has been stable for previous 1ms 0 = USB line state (SE0 and JSTATE) has not been stable for previous 1ms bit 4 Unimplemented: Read as ‘0’ bit 3 SESVD: Session Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A or B device 0 = VBUS voltage is below Session Valid on the A or B device bit 2 SESEND: B-Device Session End Indicator bit 1 = VBUS voltage is below Session Valid on the B device 0 = VBUS voltage is above Session Valid on the B device bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVD: A-Device VBUS Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A device 0 = VBUS voltage is below Session Valid on the A device DS60001168J-page 110  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-4: U1OTGCON: USB OTG CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled bit 4 DMPULDWN: D- Pull-Down Enable bit 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled bit 3 VBUSON: VBUS Power-on bit 1 = VBUS line is powered 0 = VBUS line is not powered bit 2 OTGEN: OTG Functionality Enable bit 1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control 0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control bit 1 VBUSCHG: VBUS Charge Enable bit 1 = VBUS line is charged through a pull-up resistor 0 = VBUS line is not charged through a resistor bit 0 VBUSDIS: VBUS Discharge Enable bit 1 = VBUS line is discharged through a pull-down resistor 0 = VBUS line is not discharged through a resistor  2011-2016 Microchip Technology Inc. DS60001168J-page 111

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-5: U1PWRC: USB POWER CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 7:0 UACTPND — — USLPGRD USBBUSY(1) — USUSPEND USBPWR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 UACTPND: USB Activity Pending bit 1 = USB bus activity has been detected; however, an interrupt is pending, which has yet to be generated 0 = An interrupt is not pending bit 6-5 Unimplemented: Read as ‘0’ bit 4 USLPGRD: USB Sleep Entry Guard bit 1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending 0 = USB module does not block Sleep entry bit 3 USBBUSY: USB Module Busy bit(1) 1 = USB module is active or disabled, but not ready to be enabled 0 = USB module is not active and is ready to be enabled bit 2 Unimplemented: Read as ‘0’ bit 1 USUSPEND: USB Suspend Mode bit 1 = USB module is placed in Suspend mode (The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.) 0 = USB module operates normally bit 0 USBPWR: USB Operation Enable bit 1 = USB module is turned on 0 = USB module is disabled (Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption.) Note 1: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB module registers produce undefined results. DS60001168J-page 112  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-6: U1IR: USB INTERRUPT REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 R/WC-0, HS 7:0 STALLIF ATTACHIF(1) RESUMEIF(2) IDLEIF TRNIF(3) SOFIF UERRIF(4) URSTIF(5) DETACHIF(6) Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = In Host mode a STALL handshake was received during the handshake phase of the transaction In Device mode a STALL handshake was transmitted during the handshake phase of the transaction 0 = STALL handshake has not been sent bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1) 1 = Peripheral attachment was detected by the USB module 0 = Peripheral attachment was not detected bit 5 RESUMEIF: Resume Interrupt bit(2) 1 = K-State is observed on the D+ or D- pin for 2.5 µs 0 = K-State is not observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3ms or more) 0 = No Idle condition detected bit 3 TRNIF: Token Processing Complete Interrupt bit(3) 1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information 0 = Processing of current token not complete bit 2 SOFIF: SOF Token Interrupt bit 1 = SOF token received by the peripheral or the SOF threshold reached by thehost 0 = SOF token was not received nor threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit(4) 1 = Unmasked error condition has occurred 0 = Unmasked error condition has not occurred bit 0 URSTIF: USB Reset Interrupt bit (Device mode)(5) 1 = Valid USB Reset has occurred 0 = No USB Reset has occurred DETACHIF: USB Detach Interrupt bit (Host mode)(6) 1 = Peripheral detachment was detected by the USB module 0 = Peripheral detachment was not detected Note 1: This bit is valid only if the HOSTEN bit is set (see Register10-11), there is no activity on the USB for 2.5µs, and the current bus state is not SE0. 2: When not in Suspend mode, this interrupt should be disabled. 3: Clearing this bit will cause the STAT FIFO to advance. 4: Only error conditions enabled through the U1EIE register will set this bit. 5: Device mode. 6: Host mode.  2011-2016 Microchip Technology Inc. DS60001168J-page 113

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-7: U1IE: USB INTERRUPT ENABLE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE(1) URSTIE(2) DETACHIE(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt is enabled 0 = STALL interrupt is disabled bit 6 ATTACHIE: ATTACH Interrupt Enable bit 1 = ATTACH interrupt is enabled 0 = ATTACH interrupt is disabled bit 5 RESUMEIE: RESUME Interrupt Enable bit 1 = RESUME interrupt is enabled 0 = RESUME interrupt is disabled bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle interrupt is enabled 0 = Idle interrupt is disabled bit 3 TRNIE: Token Processing Complete Interrupt Enable bit 1 = TRNIF interrupt is enabled 0 = TRNIF interrupt is disabled bit 2 SOFIE: SOF Token Interrupt Enable bit 1 = SOFIF interrupt is enabled 0 = SOFIF interrupt is disabled bit 1 UERRIE: USB Error Interrupt Enable bit(1) 1 = USB Error interrupt is enabled 0 = USB Error interrupt is disabled bit 0 URSTIE: USB Reset Interrupt Enable bit(2) 1 = URSTIF interrupt is enabled 0 = URSTIF interrupt is disabled DETACHIE: USB Detach Interrupt Enable bit(3) 1 = DATTCHIF interrupt is enabled 0 = DATTCHIF interrupt is disabled Note 1: For an interrupt to propagate USBIF, the UERRIE (U1IE<1>) bit must be set. 2: Device mode. 3: Host mode. DS60001168J-page 114  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS 7:0 CRC5EF(4) BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF PIDEF EOFEF(3,5) Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Packet rejected due to bit stuff error 0 = Packet accepted bit 6 BMXEF: Bus Matrix Error Flag bit 1 = The base address, of the Buffer Descriptor Table, or the address of an individual buffer pointed to by a Buffer Descriptor Table entry, isinvalid. 0 = No address error bit 5 DMAEF: DMA Error Flag bit(1) 1 = USB DMA error condition detected 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2) 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field received is not an integral number of bytes 0 = Data field received is an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = Data packet rejected due to CRC16 error 0 = Data packet accepted Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to betruncated. 2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) haselapsed. 3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. 4: Device mode. 5: Host mode.  2011-2016 Microchip Technology Inc. DS60001168J-page 115

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED) bit 1 CRC5EF: CRC5 Host Error Flag bit(4) 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted EOFEF: EOF Error Flag bit(3,5) 1 = An EOF error condition was detected 0 = No EOF error condition was detected bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to betruncated. 2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) haselapsed. 3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. 4: Device mode. 5: Host mode. DS60001168J-page 116  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CRC5EE(1) BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE PIDEE EOFEE(2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = BTSEF interrupt is enabled 0 = BTSEF interrupt is disabled bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit 1 = BMXEF interrupt is enabled 0 = BMXEF interrupt is disabled bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = DMAEF interrupt is enabled 0 = DMAEF interrupt is disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = BTOEF interrupt is enabled 0 = BTOEF interrupt is disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = DFN8EF interrupt is enabled 0 = DFN8EF interrupt is disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16EF interrupt is enabled 0 = CRC16EF interrupt is disabled bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit(1) 1 = CRC5EF interrupt is enabled 0 = CRC5EF interrupt is disabled EOFEE: EOF Error Interrupt Enable bit(2) 1 = EOF interrupt is enabled 0 = EOF interrupt is disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = PIDEF interrupt is enabled 0 = PIDEF interrupt is disabled Note 1: Device mode. 2: Host mode. Note: For an interrupt to propagate the USBIF register, the UERRIE (U1IE<1>) bit must be set.  2011-2016 Microchip Technology Inc. DS60001168J-page 117

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-10: U1STAT: USB STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R-x R-x R-x R-x R-x R-x U-0 U-0 7:0 ENDPT<3:0> DIR PPBI — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits (Represents the number of the Buffer Descriptor Table, updated by the last USB transfer.) 1111= Endpoint 15 1110= Endpoint 14 • • • 0001= Endpoint 1 0000= Endpoint 0 bit 3 DIR: Last Buffer Descriptor Direction Indicator bit 1 = Last transaction was a transmit (TX) transfer 0 = Last transaction was a receive (RX) transfer bit 2 PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit 1 = The last transaction was to the ODD Buffer Descriptor bank 0 = The last transaction was to the EVEN Buffer Descriptor bank bit 1-0 Unimplemented: Read as ‘0’ Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only valid when the TRNIF (U1IR<3>) bit is active. Clearing the TRNIF bit advances the FIFO. Data in register is invalid when the TRNIF bit=0. DS60001168J-page 118  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 PKTDIS(4) USBEN(4) JSTATE SE0 USBRST HOSTEN(2) RESUME(3) PPBRST TOKBUSY(1,5) SOFEN(5) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 JSTATE: Live Differential Receiver JSTATE flag bit 1 = JSTATE was detected on the USB 0 = No JSTATE was detected bit 6 SE0: Live Single-Ended Zero flag bit 1 = Single-Ended Zero was detected on the USB 0 = No Single-Ended Zero was detected bit 5 PKTDIS: Packet Transfer Disable bit(4) 1 = Token and packet processing is disabled (set upon SETUP token received) 0 = Token and packet processing is enabled TOKBUSY: Token Busy Indicator bit(1,5) 1 = Token is being executed by the USB module 0 = No token is being executed bit 4 USBRST: Module Reset bit(5) 1 = USB reset generated 0 = USB reset terminated bit 3 HOSTEN: Host Mode Enable bit(2) 1 = USB host capability is enabled 0 = USB host capability is disabled bit 2 RESUME: RESUME Signaling Enable bit(3) 1 = RESUME signaling is activated 0 = RESUME signaling is disabled Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see Register10-15). 2: All host control logic is reset any time that the value of this bit is toggled. 3: Software must set RESUME for 10ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a Low-Speed EOP to the RESUME signaling when this bit is cleared. 4: Device mode. 5: Host mode.  2011-2016 Microchip Technology Inc. DS60001168J-page 119

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the EVEN Buffer Descriptor banks 0 = Even/Odd buffer pointers are not Reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry is enabled 0 = USB module and supporting circuitry is disabled SOFEN: SOF Enable bit(5) 1 = SOF token is sent every 1 ms 0 = SOF token is disabled Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see Register10-15). 2: All host control logic is reset any time that the value of this bit is toggled. 3: Software must set RESUME for 10ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a Low-Speed EOP to the RESUME signaling when this bit is cleared. 4: Device mode. 5: Host mode. DS60001168J-page 120  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-12: U1ADDR: USB ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 LSPDEN DEVADDR<6:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: Low-Speed Enable Indicator bit 1 = Next token command to be executed at Low-Speed 0 = Next token command to be executed at Full-Speed bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits REGISTER 10-13: U1FRML: USB FRAME NUMBER LOW REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 7:0 FRML<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits The register bits are updated with the current frame number whenever a SOF TOKEN is received.  2011-2016 Microchip Technology Inc. DS60001168J-page 121

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 7:0 — — — — — FRMH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as ‘0’ bit 2-0 FRMH<2:0>: The Upper 3 bits of the Frame Numbers bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. REGISTER 10-15: U1TOK: USB TOKEN REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 PID<3:0>(1) EP<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-4 PID<3:0>: Token Type Indicator bits(1) 1101= SETUP (TX) token type transaction 1001 = IN (RX) token type transaction 0001 = OUT (TX) token type transaction Note: All other values are reserved and must not be used. bit 3-0 EP<3:0>: Token Command Endpoint Address bits The four bit value must specify a valid endpoint. Note 1: All other values are reserved and must not be used. DS60001168J-page 122  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 CNT<7:0>: SOF Threshold Value bits Typical values of the threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet REGISTER 10-17: U1BDTP1: USB BUFFER DESCRIPTOR TABLE PAGE 1 REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 7:0 BDTPTRL<15:9> — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-1 BDTPTRL<15:9>: Buffer Descriptor Table Base Address bits This 7-bit value provides address bits 15 through 9 of the Buffer Descriptor Table base address, which defines the starting location of the Buffer Descriptor Table in system memory. The 32-bit Buffer Descriptor Table base address is 512-byte aligned. bit 0 Unimplemented: Read as ‘0’  2011-2016 Microchip Technology Inc. DS60001168J-page 123

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 BDTPTRH<23:16> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 BDTPTRH<23:16>: Buffer Descriptor Table Base Address bits This 8-bit value provides address bits 23 through 16 of the Buffer Descriptor Table base address, which defines the starting location of the Buffer Descriptor Table in system memory. The 32-bit Buffer Descriptor Table base address is 512-byte aligned. REGISTER 10-19: U1BDTP3: USB BUFFER DESCRIPTOR TABLE PAGE 3 REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 BDTPTRU<31:24> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 BDTPTRU<31:24>: Buffer Descriptor Table Base Address bits This 8-bit value provides address bits 31 through 24 of the Buffer Descriptor Table base address, defines the starting location of the Buffer Descriptor Table in system memory. The 32-bit Buffer Descriptor Table base address is 512-byte aligned. DS60001168J-page 124  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 7:0 UTEYE UOEMON — USBSIDL — — — UASUSPND Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 UTEYE: USB Eye-Pattern Test Enable bit 1 = Eye-Pattern Test is enabled 0 = Eye-Pattern Test is disabled bit 6 UOEMON: USB OE Monitor Enable bit 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive bit 5 Unimplemented: Read as ‘0’ bit 4 USBSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 3-1 Unimplemented: Read as ‘0’ bit 0 UASUSPND: Automatic Suspend Enable bit 1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit (U1PWRC<1>) in Register10-5. 0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock.  2011-2016 Microchip Technology Inc. DS60001168J-page 125

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only) 1 = Direct connection to a Low-Speed device enabled 0 = Direct connection to a Low-Speed device disabled; hub required with PRE_PID bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only) 1 = Retry NAKed transactions disabled 0 = Retry NAKed transactions enabled; retry done in hardware bit 5 Unimplemented: Read as ‘0’ bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN=1 and EPRXEN=1: 1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed 0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed Otherwise, this bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint Handshake is enabled 0 = Endpoint Handshake is disabled (typically used for isochronous endpoints) DS60001168J-page 126  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 11.0 I/O PORTS These functions depend on which peripheral features are on the device. In general, when a peripheral is func- Note: This data sheet summarizes the features tioning, that pin may not be used as a general purpose of the PIC32MX1XX/2XX 28/36/44-pin I/O pin. Family of devices. It is not intended to be Key features of this module include: a comprehensive reference source. To • Individual output pin open-drain enable/disable complement the information in this data • Individual input pin weak pull-up and pull-down sheet, refer to Section 12. “I/O Ports” (DS60001120), which is available from the • Monitor selective inputs and generate interrupt when change in pin state is detected Documentation > Reference Manual section of the Microchip PIC32 web site • Operation during Sleep and Idle modes (www.microchip.com/pic32). • Fast bit manipulation using CLR, SET, and INV registers General purpose I/O pins are the simplest of peripher- Figure11-1 illustrates a block diagram of a typical als. They allow the PIC® MCU to monitor and control multiplexed I/O port. other devices. To add flexibility and functionality, some pins are multiplexed with alternate functions. FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus D Q SYSCLK CK ODC EN Q WR ODC 1 I/O Cell RD TRIS 0 0 1 D Q CK TRIS 1 EN Q 0 WR TRIS Output Multiplexers D Q CK LAT I/O Pin EN Q WR LAT WR PORT RD LAT 1 RD PORT Q D Q D 0 Sleep Q CK Q CK PBCLK Synchronization Peripheral Input R Peripheral Input Buffer Legend: R = Peripheral input buffer types may vary. Refer to Table1-1 for peripheral details. Note: This block diagram is a general representation of a shared port/peripheral structure and is only provided for illustration purposes. The actual structure for any specific port/peripheral combination may be different than it is shown here.  2011-2016 Microchip Technology Inc. DS60001168J-page 127

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 11.1 Parallel I/O (PIO) Ports 11.1.4 INPUT CHANGE NOTIFICATION All port pins have 10 registers directly associated with The input change notification function of the I/O ports their operation as digital I/O. The data direction register allows the PIC32MX1XX/2XX 28/36/44-pin Family (TRISx) determines whether the pin is an input or an devices to generate interrupt requests to the processor output. If the data direction bit is a ‘1’, then the pin is an in response to a change-of-state on selected input pins. input. All port pins are defined as inputs after a Reset. This feature can detect input change-of-states even in Reads from the latch (LATx) read the latch. Writes to Sleep mode, when the clocks are disabled. Every I/O the latch write the latch. Reads from the port (PORTx) port pin can be selected (enabled) for generating an read the port pins, while writes to the port pins write the interrupt request on a change-of-state. latch. Five control registers are associated with the CN func- tionality of each I/O port. The CNENx registers contain 11.1.1 OPEN-DRAIN CONFIGURATION the CN interrupt enable control bits for each of the input In addition to the PORTx, LATx, and TRISx registers for pins. Setting any of these bits enables a CN interrupt data control, some port pins can also be individually for the corresponding pins. configured for either digital or open-drain output. This is The CNSTATx register indicates whether a change controlled by the Open-Drain Control register, ODCx, occurred on the corresponding pin since the last read associated with each port. Setting any of the bits con- of the PORTx bit. figures the corresponding pin to act as an open-drain Each I/O pin also has a weak pull-up and a weak output. pull-down connected to it. The pull-ups act as a The open-drain feature allows the generation of current source or sink source connected to the pin, outputs higher than VDD (e.g., 5V) on any desired 5V- and eliminate the need for external resistors when tolerant pins by using external pull-up resistors. The push-button or keypad devices are connected. The maximum open-drain voltage allowed is the same as pull-ups and pull-downs are enabled separately using the maximum VIH specification. the CNPUx and the CNPDx registers, which contain See the “Pin Diagrams” section for the available pins the control bits for each of the pins. Setting any of and their functionality. the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. 11.1.2 CONFIGURING ANALOG AND Note: Pull-ups and pull-downs on change notifi- DIGITAL PORT PINS cation pins should always be disabled The ANSELx register controls the operation of the when the port pin is configured as a digital analog port pins. The port pins that are to function as output. analog inputs must have their corresponding ANSEL An additional control register (CNCONx) is shown in and TRIS bits set. In order to use port pins for I/O Register11-3. functionality with digital modules, such as Timers, UARTs, etc., the corresponding ANSELx bit must be 11.2 CLR, SET and INV Registers cleared. The ANSELx register has a default value of 0xFFFF; Every I/O module register has a corresponding CLR therefore, all pins that share analog functions are (clear), SET (set) and INV (invert) register designed to analog (not digital) by default. provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or If the TRIS bit is cleared (output) while the ANSELx bit INV register effectively performs the implied operation, is set, the digital output level (VOH or VOL) is converted but only on the corresponding base register and only by an analog peripheral, such as the ADC module or bits specified as ‘1’ are modified. Bits specified as ‘0’ Comparator module. are not modified. When the PORT register is read, all pins configured as Reading SET, CLR and INV registers returns undefined analog input channels are read as cleared (a low level). values. To see the affects of a write operation to a SET, Pins configured as digital inputs do not convert an CLR, or INV register, the base register must be read. analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. 11.1.3 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be a NOP. DS60001168J-page 128  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 11.3 Peripheral Pin Select Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority A major challenge in general purpose devices is provid- over any analog functions associated with the pin. ing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The chal- 11.3.3 CONTROLLING PERIPHERAL PIN lenge is even greater on low pin-count devices. In an SELECT application where more than one peripheral needs to PPS features are controlled through two sets of SFRs: be assigned to a single pin, inconvenient workarounds one to map peripheral inputs, and one to map outputs. in application code or a complete redesign may be the Because they are separately controlled, a particular only option. peripheral’s input and output (if the peripheral has both) The Peripheral Pin Select (PPS) configuration provides can be placed on any selectable function pin without an alternative to these choices by enabling peripheral constraint. set selection and their placement on a wide range of The association of a peripheral to a peripheral-select- I/O pins. By increasing the pinout options available on able pin is handled in two different ways, depending on a particular device, users can better tailor the device to whether an input or output is being mapped. their entire application, rather than trimming the application to fit the device. 11.3.4 INPUT MAPPING The PPS configuration feature operates over a fixed The inputs of the PPS options are mapped on the basis subset of digital I/O pins. Users may independently of the peripheral. That is, a control register associated map the input and/or output of most digital peripherals with a peripheral dictates the pin it will be mapped to. to these I/O pins. PPS is performed in software and The [pin name]R registers, where [pin name] refers to the generally does not require the device to be repro- peripheral pins listed in Table11-1, are used to config- grammed. Hardware safeguards are included that pre- ure peripheral input mapping (see Register11-1). Each vent accidental or spurious changes to the peripheral register contains sets of 4 bit fields. Programming these mapping once it has been established. bit fields with an appropriate value maps the RPn pin 11.3.1 AVAILABLE PINS with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field is The number of available pins is dependent on the shown in Table11-1. particular device and its pin count. Pins that support the For example, Figure11-2 illustrates the remappable PPS feature include the designation “RPn” in their full pin selection for the U1RX input. pin designation, where “RP” designates a remappable peripheral and “n” is the remappable port number. FIGURE 11-2: REMAPPABLE INPUT 11.3.2 AVAILABLE PERIPHERALS EXAMPLE FOR U1RX The peripherals managed by the PPS are all digital- U1RXR<3:0> only peripherals. These include general serial commu- nications (UART and SPI), general purpose timer clock 0 inputs, timer-related peripherals (input capture and out- RPA2 put compare) and interrupt-on-change inputs. 1 In comparison, some digital-only peripheral modules RPB6 are never included in the PPS feature. This is because 2 U1RX input the peripheral’s function requires special I/O circuitry to peripheral RPA4 on a specific port and cannot be easily connected to multiple pins. These modules include I2C among oth- ers. A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). n A key difference between remappable and non-remap- RPn pable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral Note: For input only, PPS functionality does not have must always be assigned to a specific I/O pin before it priority over TRISx settings. Therefore, when can be used. In contrast, non-remappable peripherals configuring RPn pin for input, the corresponding are always available on a default pin, assuming that the bit in the TRISx register must also be configured peripheral is active and not conflicting with another for input (set to ‘1’). peripheral. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin.  2011-2016 Microchip Technology Inc. DS60001168J-page 129

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 11-1: INPUT PIN SELECTION [pin name]R Value to Peripheral Pin [pin name]R SFR [pin name]R bits RPn Pin Selection 0000 = RPA0 INT4 INT4R INT4R<3:0> 0001 = RPB3 0010 = RPB4 T2CK T2CKR T2CKR<3:0> 0011 = RPB15 0100 = RPB7 0101 = RPC7(2) IC4 IC4R IC4R<3:0> 0110 = RPC0(1) 0111 = RPC5(2) 1000 = Reserved SS1 SS1R SS1R<3:0> • • REFCLKI REFCLKIR REFCLKIR<3:0> • 1111 = Reserved 0000 = RPA1 INT3 INT3R INT3R<3:0> 0001 = RPB5 0010 = RPB1 T3CK T3CKR T3CKR<3:0> 0011 = RPB11 0100 = RPB8 IC3 IC3R IC3R<3:0> 0101 = RPA8(2) 0110 = RPC8(2) U1CTS U1CTSR U1CTSR<3:0> 0111 = RPA9(2) 1000 = Reserved U2RX U2RXR U2RXR<3:0> • • • SDI1 SDI1R SDI1R<3:0> 1111 = Reserved INT2 INT2R INT2R<3:0> 0000 = RPA2 0001 = RPB6 T4CK T4CKR T4CKR<3:0> 0010 = RPA4 0011 = RPB13 IC1 IC1R IC1R<3:0> 0100 = RPB2 IC5 IC5R IC5R<3:0> 0101 = RPC6(2) 0110 = RPC1(1) U1RX U1RXR U1RXR<3:0> 0111 = RPC3(1) 1000 = Reserved U2CTS U2CTSR U2CTSR<3:0> • SDI2 SDI2R SDI2R<3:0> • • OCFB OCFBR OCFBR<3:0> 1111 = Reserved 0000 = RPA3 INT1 INT1R INT1R<3:0> 0001 = RPB14 0010 = RPB0 T5CK T5CKR T5CKR<3:0> 0011 = RPB10 0100 = RPB9 0101 = RPC9(1) IC2 IC2R IC2R<3:0> 0110 = RPC2(2) 0111 = RPC4(2) 1000 = Reserved SS2 SS2R SS2R<3:0> • • OCFA OCFAR OCFAR<3:0> • 1111 = Reserved Note 1: This pin is not available on 28-pin devices. 2: This pin is only available on 44-pin devices. DS60001168J-page 130  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 11.3.5 OUTPUT MAPPING 11.3.6.1 Control Register Lock Sequence In contrast to inputs, the outputs of the PPS options Under normal operation, writes to the RPnR and [pin are mapped on the basis of the pin. In this case, a name]R registers are not allowed. Attempted writes control register associated with a particular pin appear to execute normally, but the contents of the dictates the peripheral output to be mapped. The registers remain unchanged. To change these regis- RPnR registers (Register11-2) are used to control ters, they must be unlocked in hardware. The regis- output mapping. Like the [pin name]R registers, each ter lock is controlled by the Configuration bit, register contains sets of 4 bit fields. The value of the IOLOCK (CFGCON<13>). Setting IOLOCK prevents bit field corresponds to one of the peripherals, and writes to the control registers; clearing IOLOCK that peripheral’s output is mapped to the pin (see allows writes. Table11-2 and Figure11-3). To set or clear the IOLOCK bit, an unlock sequence A null output is associated with the output register reset must be executed. Refer to Section 6. “Oscillator” value of ‘0’. This is done to ensure that remappable (DS60001112) in the “PIC32 Family Reference outputs remain disconnected from all output pins by Manual” for details. default. 11.3.6.2 Configuration Bit Select Lock FIGURE 11-3: EXAMPLE OF As an additional level of safety, the device can be MULTIPLEXING OF configured to prevent more than one write session to REMAPPABLE OUTPUT the RPnR and [pin name]R registers. The Configuration FOR RPA0 bit, IOL1WAY (DEVCFG3<29>), blocks the IOLOCK bit from being cleared after it has been set once. If RPA0R<3:0> IOLOCK remains set, the register unlock procedure does not execute, and the PPS control registers cannot Default be written to. The only way to clear the bit and re- 0 enable peripheral remapping is to perform a device U1TX Output 1 Reset. U1RTS Output 2 In the default (unprogrammed) state, IOL1WAY is set, RPA0 restricting users to one write session. Output Data 14 15 11.3.6 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to the peripheral map: • Control register lock sequence • Configuration bit select lock  2011-2016 Microchip Technology Inc. DS60001168J-page 131

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 11-2: OUTPUT PIN SELECTION RPnR Value to Peripheral RPn Port Pin RPnR SFR RPnR bits Selection RPA0 RPA0R RPA0R<3:0> 0000 = No Connect 0001 = U1TX RPB3 RPB3R RPB3R<3:0> 0010 = U2RTS RPB4 RPB4R RPB4R<3:0> 0011 = SS1 0100 = Reserved RPB15 RPB15R RPB15R<3:0> 0101 = OC1 RPB7 RPB7R RPB7R<3:0> 0110 = Reserved 0111 = C2OUT RPC7 RPC7R RPC7R<3:0> 1000 = Reserved • RPC0 RPC0R RPC0R<3:0> • • RPC5 RPC5R RPC5R<3:0> 1111 = Reserved RPA1 RPA1R RPA1R<3:0> 0000 = No Connect 0001 = Reserved RPB5 RPB5R RPB5R<3:0> 0010 = Reserved RPB1 RPB1R RPB1R<3:0> 0011 = SDO1 0100 = SDO2 RPB11 RPB11R RPB11R<3:0> 0101 = OC2 RPB8 RPB8R RPB8R<3:0> 0110 = Reserved 0111 = C3OUT RPA8 RPA8R RPA8R<3:0> • • RPC8 RPC8R RPC8R<3:0> • RPA9 RPA9R RPA9R<3:0> 1111 = Reserved RPA2 RPA2R RPA2R<3:0> 0000 = No Connect 0001 = Reserved RPB6 RPB6R RPB6R<3:0> 0010 = Reserved 0011 = SDO1 RPA4 RPA4R RPA4R<3:0> 0100 = SDO2 RPB13 RPB13R RPB13R<3:0> 0101 = OC4 0110 = OC5 RPB2 RPB2R RPB2R<3:0> 0111 = REFCLKO 1000 = Reserved RPC6 RPC6R RPC6R<3:0> • RPC1 RPC1R RPC1R<3:0> • • RPC3 RPC3R RPC3R<3:0> 1111 = Reserved RPA3 RPA3R RPA3R<3:0> 0000 = No Connect 0001 = U1RTS RPB14 RPB14R RPB14R<3:0> 0010 = U2TX 0011 = Reserved RPB0 RPB0R RPB0R<3:0> 0100 = SS2 RPB10 RPB10R RPB10R<3:0> 0101 = OC3 0110 = Reserved RPB9 RPB9R RPB9R<3:0> 0111 = C1OUT 1000 = Reserved RPC9 RPC9R RPC9R<3:0> • RPC2 RPC2R RPC2R<3:0> • • RPC4 RPC4R RPC4R<3:0> 1111 = Reserved DS60001168J-page 132  2011-2016 Microchip Technology Inc.

 11.4 Ports Control Registers 2 0 1 TABLE 11-3: PORTA REGISTER MAP 1 -2016 Microchip Virtual Address(BF88_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T e 31:16 — — — — — — — — — — — — — — — — 0000 c 6000 ANSELA hn 15:0 — — — — — — — — — — — — — — ANSA1 ANSA0 0003 P ology 6010 TRISA 3115:1:06 —— —— —— —— —— TRIS—A10(2) TRIS—A9(2) TRIS—A8(2) TRIS—A7(2) —— —— TR—ISA4 TR—ISA3 TR—ISA2 TR—ISA1 TR—ISA0 0070900F IC In 31:16 — — — — — — — — — — — 0000 3 c 6020 PORTA . 15:0 — — — — — RA10(2) RA9(2) RA8(2) RA7(2) — — RA4 RA3 RA2 RA1 RA0 xxxx 2 31:16 — — — — — — — — — — — — — — — — 0000 M 6030 LATA 15:0 — — — — — LATA10(2) LATA9(2) LATA8(2) LATA7(2) — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 X 6040 ODCA 15:0 — — — — — ODCA10(2) ODCA9(2) ODCA8(2) ODCA7(2) — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 X 6050 CNPUA 15:0 — — — — — CNPUA10(2) CNPUA9(2) CNPUA8(2) CNPUA7(2) — — CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 6060 CNPDA 15:0 — — — — — CNPDA10(2) CNPDA9(2) CNPDA8(2) CNPDA7(2) — — CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000 /2 31:16 — — — — — — — — — — — — — — — — 0000 X 6070 CNCONA 15:0 ON — SIDL — — — — — — — — — — — — — 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 6080 CNENA 15:0 — — — — — CNIEA10(2) CNIEA9(2) CNIEA8(2) CNIEA7(2) — — CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000 2 6090 CNSTATA3115:1:06 —— —— —— —— —— CNSTA—TA10(2)CNST—ATA9(2)CNST—ATA8(2)CNST—ATA7(2) —— —— CNS—TATA4CNS—TATA3CNS—TATA2CNS—TATA1CNS—TATA000000000 8 / Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for 6 more information. / 2: This bit is only available on 44-pin devices. 4 4 - P I N D S 60 F 0 0 A 1 1 68 M J -pa I g L e 1 Y 3 3

D TABLE 11-4: PORTB REGISTER MAP P S 60001168J-pag Virtual Address(BF88_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24B/8its 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets IC32M e 1 31:16 — — — — — — — — — — — — — — — — 0000 X 34 6100 ANSELB 15:0 ANSB15 ANSB14 ANSB13 ANSB12(2) — — — — — — — — ANSB3 ANSB2 ANSB1 ANSB0 E00F 1 6110 TRISB 31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 TRISB15 TRISB14 TRISB13 TRISB12(2) TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6(2) TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF X 31:16 — — — — — — — — — — — 0000 6120 PORTB 15:0 RB15 RB14 RB13 RB12(2) RB11 RB10 RB9 RB8 RB7 RC6(2) RB5 RB4 RB3 RB2 RB1 RB0 xxxx / 2 31:16 — — — — — — — — — — — — — — — — 0000 6130 LATB X 15:0 LATB15 LATB14 LATB13 LATB12(2) LATB11 LATB10 LATB9 LATB8 LATB7 LATB6(2) LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 X 6140 ODCB 15:0 ODCB15 ODCB14 ODCB13 ODCB12(2) ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 6150 CNPUB 15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12(2) CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6(2) CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 8 / 31:16 — — — — — — — — — — — — — — — — 0000 3 6160 CNPDB 15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12(2) CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6(2) CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 6 6170 CNCONB3115:1:06 O—N —— S—IDL —— —— —— —— —— —— —— —— —— —— —— —— —— 00000000 /4 31:16 — — — — — — — — — — — — — — — — 0000 4 6180 CNENB 15:0 CNIEB15 CNIEB14 CNIEB13 CNIEB11(2) CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6(2) CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000 - P 31:16 — — — — — — — — — — — — — — — — 0000 6190 CNSTATB CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN I 15:0 STATB15 STATB14 STATB13 STATB12(2) STATB11 STATB10 STATB9 STATB8 STATB7 STATB6(2) STATB5 STATB4 STATB3 STATB2 STATB1 STATB0 0000 N Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more information. A 2: This bit is not available on PIC32MX2XX devices. The reset value for the TRISB register when this bit is not available is 0x0000EFBF. M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 11-5: PORTC REGISTER MAP 2 01 ss Bits 1-2016 Micro Virtual Addre(BF88_#) Register(1,2)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets c h 31:16 — — — — — — — — — — — — — — — — 0000 ip T 6200 ANSELC 15:0 — — — — — — — — — — — — ANSC3(4) ANSC2(3) ANSC1 ANSC0 000F ec 31:16 — — — — — — — — — — — — — — — — 0000 h 6210 TRISC P n 15:0 — — — — — — TRISC9 TRISC8(3) TRISC7(3) TRISC6(3) TRISC5(3) TRISC4(3) TRISC3 TRISC2(3) TRISC1 TRISC0 03FF o log 6220 PORTC 31:16 — — — — — — — — — — — 0000 IC y In 15:0 — — — — — — RC9 RC8(3) RC7(3) RC6(3) RC5(3) RC4(3) RC3 RC2(3) RC1 RC0 xxxx 3 c 31:16 — — — — — — — — — — — — — — — — 0000 . 6230 LATC 15:0 — — — — — — LATC9 LATC8(3) LATC7(3) LATC6(3) LATC5(3) LATC4(3) LATC3 LATC2(3) LATC1 LATC0 xxxx 2 31:16 — — — — — — — — — — — — — — — — 0000 M 6240 ODCC 15:0 — — — — — — ODCC9 ODCC8(3) ODCC7(3) ODCC6(3) ODCC5(3) ODCC4(3) ODCC3 ODCC2(3) ODCC1 ODCC0 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 6250 CNPUC 15:0 — — — — — — CNPUC9 CNPUC8(3) CNPUC7(3) CNPUC6(3) CNPUC5(3) CNPUC4(3) CNPUC3 CNPUC2(3) CNPUC1 CNPUC0 0000 1 X 31:16 — — — — — — — — — — — — — — — — 0000 6260 CNPDC 15:0 — — — — — — CNPDC9 CNPDC8(3) CNPDC7(3) CNPDC6(3) CNPDC5(3) CNPDC4(3) CNPDC3 CNPDC2(3) CNPDC1 CNPDC0 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 / 6270 CNCONC 15:0 ON — SIDL — — — — — — — — — — — — — 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 X 6280 CNENC 15:0 — — — — — — CNIEC9 CNIEC8(3) CNIEC7(3) CNIEC6(3) CNIEC5(3) CNIEC4(3) CNIEC3 CNIEC2(3) CNIEC1 CNIEC0 0000 X 6290 CNSTATC3115:1:06 —— —— —— —— —— —— CNS—TATC9 CNST—ATC8(3)CNST—ATC7(3)CNST—ATC6(3)CNST—ATC5(3)CNST—ATC4(3)CNS—TATC3CNST—ATC2(3)CNS—TATC1CNS—TATC000000000 2 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 8 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for / more information. 3 2: PORTC is not available on 28-pin devices. 6 3: This bit is only available on 44-pin devices. / 4: This bit is only available on USB-enabled devices with 36 or 44 pins. 4 4 - P I N D S 60 F 0 0 A 1 1 68 M J -pa I g L e 1 Y 3 5

D TABLE 11-6: PERIPHERAL PIN SELECT INPUT REGISTER MAP P S 60001168J-page Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets IC32M 1 X 3 31:16 — — — — — — — — — — — — — — — — 0000 6 FA04 INT1R 1 15:0 — — — — — — — — — — — — INT1R<3:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 FA08 INT2R X 15:0 — — — — — — — — — — — — INT2R<3:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 /2 FA0C INT3R 15:0 — — — — — — — — — — — — INT3R<3:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 X FA10 INT4R 15:0 — — — — — — — — — — — — INT4R<3:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 2 FA18 T2CKR 15:0 — — — — — — — — — — — — T2CKR<3:0> 0000 8 / 31:16 — — — — — — — — — — — — — — — — 0000 3 FA1C T3CKR 15:0 — — — — — — — — — — — — T3CKR<3:0> 0000 6 31:16 — — — — — — — — — — — — — — — — 0000 / FA20 T4CKR 4 15:0 — — — — — — — — — — — — T4CKR<3:0> 0000 4 31:16 — — — — — — — — — — — — — — — — 0000 FA24 T5CKR - 15:0 — — — — — — — — — — — — T5CKR<3:0> 0000 P 31:16 — — — — — — — — — — — — — — — — 0000 I FA28 IC1R N 15:0 — — — — — — — — — — — — IC1R<3:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 F FA2C IC2R 15:0 — — — — — — — — — — — — IC2R<3:0> 0000 A 31:16 — — — — — — — — — — — — — — — — 0000  FA30 IC3R M 2 15:0 — — — — — — — — — — — — IC3R<3:0> 0000 0 I 1 31:16 — — — — — — — — — — — — — — — — 0000 L 1 FA34 IC4R -20 15:0 — — — — — — — — — — — — IC4R<3:0> 0000 Y 16 31:16 — — — — — — — — — — — — — — — — 0000 M FA38 IC5R ic 15:0 — — — — — — — — — — — — IC5R<3:0> 0000 ro 31:16 — — — — — — — — — — — — — — — — 0000 ch FA48 OCFAR ip 15:0 — — — — — — — — — — — — OCFAR<3:0> 0000 Te 31:16 — — — — — — — — — — — — — — — — 0000 c FA4C OCFBR hn 15:0 — — — — — — — — — — — — OCFBR<3:0> 0000 o lo 31:16 — — — — — — — — — — — — — — — — 0000 g FA50 U1RXR y In 15:0 — — — — — — — — — — — — U1RXR<3:0> 0000 c .

 TABLE 11-6: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) 2 0 11-2016 Micro Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets c h ip 31:16 — — — — — — — — — — — — — — — — 0000 Te FA54 U1CTSR 15:0 — — — — — — — — — — — — U1CTSR<3:0> 0000 c hn 31:16 — — — — — — — — — — — — — — — — 0000 P o FA58 U2RXR lo 15:0 — — — — — — — — — — — — U2RXR<3:0> 0000 I g C y In FA5C U2CTSR 31:16 — — — — — — — — — — — — — — — — 0000 3 c. 15:0 — — — — — — — — — — — — U2CTSR<3:0> 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 FA84 SDI1R M 15:0 — — — — — — — — — — — — SDI1R<3:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 X FA88 SS1R 15:0 — — — — — — — — — — — — SS1R<3:0> 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 X FA90 SDI2R 15:0 — — — — — — — — — — — — SDI2R<3:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 / FA94 SS2R 2 15:0 — — — — — — — — — — — — SS2R<3:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 FAB8 REFCLKIR X 15:0 — — — — — — — — — — — — REFCLKIR<3:0> 0000 2 8 / 3 6 / 4 4 - P I N D S 60 F 0 0 A 1 1 68 M J -pa I g L e 1 Y 3 7

D TABLE 11-7: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP P S 60001168J-page Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets IC32M 1 X 3 31:16 — — — — — — — — — — — — — — — — 0000 8 FB00 RPA0R 15:0 — — — — — — — — — — — — RPA0<3:0> 0000 1 X 31:16 — — — — — — — — — — — — — — — — 0000 FB04 RPA1R 15:0 — — — — — — — — — — — — RPA1<3:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 / FB08 RPA2R 2 15:0 — — — — — — — — — — — — RPA2<3:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 FB0C RPA3R 15:0 — — — — — — — — — — — — RPA3<3:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 FB10 RPA4R 2 15:0 — — — — — — — — — — — — RPA4<3:0> 0000 8 31:16 — — — — — — — — — — — — — — — — 0000 FB20 RPA8R(1) / 15:0 — — — — — — — — — — — — RPA8<3:0> 0000 3 31:16 — — — — — — — — — — — — — — — — 0000 6 FB24 RPA9R(1) 15:0 — — — — — — — — — — — — RPA9<3:0> 0000 / 4 31:16 — — — — — — — — — — — — — — — — 0000 FB2C RPB0R 4 15:0 — — — — — — — — — — — — RPB0<3:0> 0000 - 31:16 — — — — — — — — — — — — — — — — 0000 P FB30 RPB1R 15:0 — — — — — — — — — — — — RPB1<3:0> 0000 I N 31:16 — — — — — — — — — — — — — — — — 0000 FB34 RPB2R 15:0 — — — — — — — — — — — — RPB2<3:0> 0000 F 31:16 — — — — — — — — — — — — — — — — 0000 FB38 RPB3R A 15:0 — — — — — — — — — — — — RPB3<3:0> 0000  31:16 — — — — — — — — — — — — — — — — 0000 M 20 FB3C RPB4R 15:0 — — — — — — — — — — — — RPB4<3:0> 0000 I 11 31:16 — — — — — — — — — — — — — — — — 0000 L -20 FB40 RPB5R 15:0 — — — — — — — — — — — — RPB5<3:0> 0000 Y 1 6 M FB44 RPB6R(2) 31:16 — — — — — — — — — — — — — — — — 0000 ic 15:0 — — — — — — — — — — — — RPB6<3:0> 0000 roc 31:16 — — — — — — — — — — — — — — — — 0000 h FB48 RPB7R ip 15:0 — — — — — — — — — — — — RPB7<3:0> 0000 T e Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ch Note 1: This register is only available on 44-pin devices. no 2: This register is only available on PIC32MX1XX devices. lo 3: This register is only available on 36-pin and 44-pin devices. g y In c .

 TABLE 11-7: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) 2 011-2016 Micro Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets c hip T FB4C RPB8R 3115:1:06 —— —— —— —— —— —— —— —— —— —— —— —— — —RPB8<3:0—> — 00000000 e ch 31:16 — — — — — — — — — — — — — — — — 0000 P n FB50 RPB9R olo 15:0 — — — — — — — — — — — — RPB9<3:0> 0000 I gy 31:16 — — — — — — — — — — — — — — — — 0000 C In FB54 RPB10R 15:0 — — — — — — — — — — — — RPB10<3:0> 0000 3 c . 31:16 — — — — — — — — — — — — — — — — 0000 2 FB58 RPB11R 15:0 — — — — — — — — — — — — RPB11<3:0> 0000 M 31:16 — — — — — — — — — — — — — — — — 0000 FB60 RPB13R X 15:0 — — — — — — — — — — — — RPB13<3:0> 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 FB64 RPB14R X 15:0 — — — — — — — — — — — — RPB14<3:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 X FB68 RPB15R 15:0 — — — — — — — — — — — — RPB15<3:0> 0000 / 2 31:16 — — — — — — — — — — — — — — — — 0000 FB6C RPC0R(3) X 15:0 — — — — — — — — — — — — RPC0<3:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 FB70 RPC1R(3) 15:0 — — — — — — — — — — — — RPC1<3:0> 0000 2 FB74 RPC2R(1) 31:16 — — — — — — — — — — — — — — — — 0000 8 15:0 — — — — — — — — — — — — RPC2<3:0> 0000 / 31:16 — — — — — — — — — — — — — — — — 0000 3 FB78 RPC3R(3) 15:0 — — — — — — — — — — — — RPC3<3:0> 0000 6 FB7C RPC4R(1) 31:16 — — — — — — — — — — — — — — — — 0000 /4 15:0 — — — — — — — — — — — — RPC4<3:0> 0000 4 FB80 RPC5R(1) 31:16 — — — — — — — — — — — — — — — — 0000 - 15:0 — — — — — — — — — — — — RPC5<3:0> 0000 P 31:16 — — — — — — — — — — — — — — — — 0000 I FB84 RPC6R(1) N D 15:0 — — — — — — — — — — — — RPC6<3:0> 0000 S60 FB88 RPC7R(1) 31:16 — — — — — — — — — — — — — — — — 0000 F 00 15:0 — — — — — — — — — — — — RPC7<3:0> 0000 A 1 1 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 68 Note 1: This register is only available on 44-pin devices. M J-pa 23:: TThhiiss rreeggiisstteerr iiss oonnllyy aavvaaiillaabbllee oonn 3P6IC-p3in2 ManXd1 X4X4- dpeinv idceevsi.ces. I g L e 1 Y 3 9

D TABLE 11-7: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) P S 600 ss Bits IC 01168J-pag Virtual Addre(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32M e 140 FB8C RPC8R(1) 3115:1:06 —— —— —— —— —— —— —— —— —— —— —— —— — —RPC8<3:0—> — 00000000 X1 31:16 — — — — — — — — — — — — — — — — 0000 X FB90 RPC9R(3) 15:0 — — — — — — — — — — — — RPC9<3:0> 0000 X Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / Note 1: This register is only available on 44-pin devices. 2 2: This register is only available on PIC32MX1XX devices. X 3: This register is only available on 36-pin and 44-pin devices. X 2 8 / 3 6 / 4 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 11-1: [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — — — [pin name]R<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3-0 [pin name]R<3:0>: Peripheral Pin Select Input bits Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table11-1 for input pin selection values. Note: Register values can only be changed if the Configuration bit, IOLOCK (CFGCON<13>), = 0. REGISTER 11-2: RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — — — RPnR<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits See Table11-2 for output pin selection values. Note: Register values can only be changed if the Configuration bit, IOLOCK (CFGCON<13>), = 0.  2011-2016 Microchip Technology Inc. DS60001168J-page 141

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 11-3: CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A, B, C) Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 15:8 ON — SIDL — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 7:0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Change Notice (CN) Control ON bit 1 = CN is enabled 0 = CN is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Control bit 1 = Idle mode halts CN operation 0 = Idle does not affect CN operation bit 12-0 Unimplemented: Read as ‘0’ DS60001168J-page 142  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 12.0 TIMER1 The following modes are supported: • Synchronous Internal Timer Note: This data sheet summarizes the features • Synchronous Internal Gated Timer of the PIC32MX1XX/2XX 28/36/44-pin • Synchronous External Timer Family of devices. It is not intended to be a comprehensive reference source. To • Asynchronous External Timer complement the information in this data sheet, refer to Section 14. “Timers” 12.1 Additional Supported Features (DS60001105), which is available from the • Selectable clock prescaler Documentation > Reference Manual section of the Microchip PIC32 web site • Timer operation during CPU Idle and Sleep mode (www.microchip.com/pic32). • Fast bit manipulation using CLR, SET and INV registers This family of PIC32 devices features one • Asynchronous mode can be used with the SOSC synchronous/asynchronous 16-bit timer that can operate to function as a Real-Time Clock (RTC) as a free-running interval timer for various timing applica- tions and counting external events. This timer can also Figure12-1 illustrates a general block diagram of be used with the Low-Power Secondary Oscillator Timer1. (SOSC) for Real-Time Clock (RTC) applications. FIGURE 12-1: TIMER1 BLOCK DIAGRAM Data Bus<31:0> <15:0> <15:0> TSYNC 1 Sync Reset TMR1 0 16-bit Comparator Equal PR1 0 T1IF Event Flag 1 Q D TGATE Q TCS TGATE ON SOSCO/T1CK x 1 SOSCEN Gate Prescaler Sync 1 0 1, 8, 64, 256 SOSCI PBCLK 0 0 2 TCKPS<1:0> Note: The default state of the SOSCEN (OSCCON<1>) bit during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1.  2011-2016 Microchip Technology Inc. DS60001168J-page 143

D 12.2 Timer1 Control Registers P S 600 TABLE 12-1: TIMER1 REGISTER MAP IC 0 1168J-page 14 Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 4 1 31:16 — — — — — — — — — — — — — — — — 0000 0600 T1CON X 15:0 ON — SIDL TWDIS TWIP — — — TGATE — TCKPS<1:0> — TSYNC TCS — 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 0610 TMR1 15:0 TMR1<15:0> 0000 / 31:16 — — — — — — — — — — — — — — — — 0000 2 0620 PR1 15:0 PR1<15:0> FFFF X Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more information. 2 8 / 3 6 / 4 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 12-1: T1CON: TYPE A TIMER CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0 15:8 ON(1) — SIDL TWDIS TWIP — — — R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 7:0 TGATE — TCKPS<1:0> — TSYNC TCS — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Timer On bit(1) 1 = Timer is enabled 0 = Timer is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12 TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to Timer1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality) bit 11 TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to the Timer1 register in progress 0 = Asynchronous write to Timer1 register is complete In Synchronous Timer mode: This bit is read as ‘0’. bit 10-8 Unimplemented: Read as ‘0’ bit 7 TGATE: Timer Gated Time Accumulation Enable bit When TCS=1: This bit is ignored. When TCS=0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value Note 1: When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.  2011-2016 Microchip Technology Inc. DS60001168J-page 145

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 12-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS=1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS=0: This bit is ignored. bit 1 TCS: Timer Clock Source Select bit 1 = External clock from TxCKI pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. DS60001168J-page 146  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 13.0 TIMER2/3, TIMER4/5 • Synchronous internal 32-bit timer • Synchronous internal 32-bit gated timer Note: This data sheet summarizes the features • Synchronous external 32-bit timer of the PIC32MX1XX/2XX 28/36/44-pin Note: In this chapter, references to registers, Family of devices. It is not intended to be TxCON, TMRx and PRx, use ‘x’ to a comprehensive reference source. To represent Timer2 through Timer5 in 16-bit complement the information in this data sheet, refer to Section 14. “Timers” modes. In 32-bit modes, ‘x’ represents (DS60001105), which is available from the Timer2 or Timer4 and ‘y’ represents Documentation > Reference Manual Timer3 or Timer5. section of the Microchip PIC32 web site (www.microchip.com/pic32). 13.1 Additional Supported Features This family of PIC32 devices features four synchronous • Selectable clock prescaler 16-bit timers (default) that can operate as a free- • Timers operational during CPU idle running interval timer for various timing applications • Time base for Input Capture and Output Compare and counting external events. The following modes are modules (Timer2 and Timer3 only) supported: • ADC event trigger (Timer3 in 16-bit mode, • Synchronous internal 16-bit timer Timer2/3 in 32-bit mode) • Synchronous internal 16-bit gated timer • Fast bit manipulation using CLR, SET and INV • Synchronous external 16-bit timer registers Two 32-bit synchronous timers are available by Figure13-1 and Figure13-2 illustrate block diagrams combining Timer2 with Timer3 and Timer4 with Timer5. of Timer2/3 and Timer4/5. The 32-bit timers can operate in three modes: FIGURE 13-1: TIMER2-TIMER5 BLOCK DIAGRAM (16-BIT) Data Bus<31:0> <15:0> <15:0> Reset TMRx Sync ADC Event Trigger(1) Comparator x 16 Equal PRx 0 TxIF Event Flag 1 Q D TGATE Q TCS TGATE ON TxCK x 1 Prescaler Gate 1, 2, 4, 8, 16, Sync 1 0 32, 64, 256 PBCLK 0 0 3 Note 1: ADC event trigger is available on Timer3 only. TCKPS  2011-2016 Microchip Technology Inc. DS60001168J-page 147

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 13-2: TIMER2/3, TIMER4/5 BLOCK DIAGRAM (32-BIT) Data Bus<31:0> <31:0> Reset TMRy(1) TMRx(1) Sync MS Half Word LS Half Word ADC Event Trigger(2) 32-bit Comparator Equal PRy PRx TyIF Event 0 Flag 1 Q D TGATE Q TCS TGATE ON TxCK x 1 Prescaler Gate 1, 2, 4, 8, 16, Sync 1 0 32, 64, 256 PBCLK 0 0 3 TCKPS Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5. 2: ADC event trigger is available only on the Timer2/3 pair. DS60001168J-page 148  2011-2016 Microchip Technology Inc.

 13.2 Timer Control Registers 2 0 1 TABLE 13-1: TIMER2-TIMER5 REGISTER MAP 1 -2016 Microchip Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Te 31:16 — — — — — — — — — — — — — — — — 0000 c 0800 T2CON h 15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS — 0000 P n ology 0810 TMR2 3115::106 — — — — — — — —TMR2<15:0—> — — — — — — — 00000000 IC In 31:16 — — — — — — — — — — — — — — — — 0000 3 c 0820 PR2 . 15:0 PR2<15:0> FFFF 2 0A00 T3CON31:16 — — — — — — — — — — — — — — — — 0000 M 15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> — — TCS — 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 0A10 TMR3 15:0 TMR3<15:0> 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 X 0A20 PR3 15:0 PR3<15:0> FFFF X 31:16 — — — — — — — — — — — — — — — — 0000 0C00 T4CON / 15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS — 0000 2 0C10 TMR4 31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 TMR4<15:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 0C20 PR4 15:0 PR4<15:0> FFFF 2 31:16 — — — — — — — — — — — — — — — — 0000 0E00 T5CON 8 15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> — — TCS — 0000 / 31:16 — — — — — — — — — — — — — — — — 0000 3 0E10 TMR5 15:0 TMR5<15:0> 0000 6 31:16 — — — — — — — — — — — — — — — — 0000 / 0E20 PR5 4 15:0 PR5<15:0> FFFF 4 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for - P more information. I N D S 60 F 0 0 A 1 1 68 M J -pa I g L e 1 Y 4 9

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 13-1: TXCON: TYPE B TIMER CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 15:8 ON(1,3) — SIDL(4) — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 7:0 TGATE(3) TCKPS<2:0>(3) T32(2) — TCS(3) — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Timer On bit(1,3) 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit(4) 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 TGATE: Timer Gated Time Accumulation Enable bit(3) When TCS=1: This bit is ignored and is read as ‘0’. When TCS=0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits(3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: This bit is available only on even numbered timers (Timer2 and Timer4). 3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3, and Timer5). All timer functions are set through the even numbered timers. 4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. DS60001168J-page 150  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 13-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) bit 3 T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: This bit is available only on even numbered timers (Timer2 and Timer4). 3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3, and Timer5). All timer functions are set through the even numbered timers. 4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode.  2011-2016 Microchip Technology Inc. DS60001168J-page 151

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 152  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 14.0 WATCHDOG TIMER (WDT) The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be Note: This data sheet summarizes the features used to detect system software malfunctions by reset- of the PIC32MX1XX/2XX 28/36/44-pin ting the device if the WDT is not cleared periodically in Family of devices. It is not intended to be software. Various WDT time-out periods can be a comprehensive reference source. To selected using the WDT postscaler. The WDT can also complement the information in this data be used to wake the device from Sleep or Idle mode. sheet, refer to Section 9. “Watchdog, The following are some of the key features of the WDT Deadman, and Power-up Timers” module: (DS60001114), which are available from the Documentation > Reference Manual • Configuration or software controlled section of the Microchip PIC32 web site • User-configurable time-out period (www.microchip.com/pic32). • Can wake the device from Sleep or Idle mode Figure14-1 illustrates a block diagram of the WDT and Power-up timer. FIGURE 14-1: WATCHDOG TIMER AND POWER-UP TIMER BLOCK DIAGRAM PWRTEnable LPRC WDTEnable Control PWRTEnable 1:64Output LPRC PWRT Oscillator 1 Clock 25-bitCounter WDTCLR=1 WDTEnable 25 Wake 0 DeviceReset WDTCounterReset WDT Enable 1 NMI(Wake-up) Reset Event PowerSave Decoder FWDTPS<4:0> (DEVCFG1<20:16>)  2011-2016 Microchip Technology Inc. DS60001168J-page 153

D 14.1 Watchdog Timer Control Registers P S 60 TABLE 14-1: WATCHDOG TIMER CONTROL REGISTER MAP I 0 C 0 11 ss Bits 3 68J-page 15 Virtual Addre(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 2MX 4 31:16 — — — — — — — — — — — — — — — — 0000 1 0000 WDTCON 15:0 ON — — — — — — — — SWDTPS<4:0> WDTWINENWDTCLR 0000 X Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for / more information. 2 X X 2 8 / 3 6 / 4 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 14-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 ON(1,2) — — — — — — — U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0 7:0 — SWDTPS<4:0> WDTWINEN WDTCLR Legend: y = Values set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Watchdog Timer Enable bit(1,2) 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software bit 14-7 Unimplemented: Read as ‘0’ bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits On reset, these bits are set to the values of the WDTPS <4:0> of Configuration bits. bit 1 WDTWINEN: Watchdog Timer Window Enable bit 1 = Enable windowed Watchdog Timer 0 = Disable windowed Watchdog Timer bit 0 WDTCLR: Watchdog Timer Reset bit 1 = Writing a ‘1’ will clear the WDT 0 = Software cannot force this bit to a ‘0’ Note 1: A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software. 2: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.  2011-2016 Microchip Technology Inc. DS60001168J-page 155

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 156  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 15.0 INPUT CAPTURE • Prescaler capture event modes: - Capture timer value on every 4th rising edge of Note: This data sheet summarizes the features input at ICx pin of the PIC32MX1XX/2XX 28/36/44-pin - Capture timer value on every 16th rising edge of Family of devices. It is not intended to be input at ICx pin a comprehensive reference source. To complement the information in this data Each input capture channel can select between one of sheet, refer to Section 15. “Input Cap- two 16-bit timers (Timer2 or Timer3) for the time base, ture” (DS60001122), which is available or two 16-bit timers (Timer2 and Timer3) together to from the Documentation > Reference form a 32-bit timer. The selected timer can use either Manual section of the Microchip PIC32 an internal or external clock. web site (www.microchip.com/pic32). Other operational features include: The Input Capture module is useful in applications • Device wake-up from capture pin during Sleep requiring frequency (period) and pulse measurement. and Idle modes • Interrupt on input capture event The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an • 4-word FIFO buffer for capture values (interrupt event occurs at the ICx pin. The following events cause optionally generated after 1, 2, 3, or 4 buffer capture events: locations are filled) • Input capture can also be used to provide • Simple capture event modes: additional sources of external interrupts - Capture timer value on every rising and falling edge of input at ICx pin Figure15-1 illustrates a general block diagram of the Input Capture module. - Capture timer value on every edge (rising and falling) - Capture timer value on every edge (rising and falling), specified edge first. FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM FEDGE ICM<2:0> Specified/Every Edge Mode 110 Prescaler Mode 101 TMR2 TMR3 (16th Rising Edge) C32 || ICTMR Prescaler Mode 100 (4th Rising Edge) Capture Event To CPU FIFO CONTROL Rising Edge Mode 011 ICx pin ICxBUF FallingEdgeMode 010 FIFO ICI<1:0> ICM<2:0> Edge Detection 001 Mode /N Set Flag ICxIF (In IFSx Register) Sleep/Idle Wake-up Mode 001 111 Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.  2011-2016 Microchip Technology Inc. DS60001168J-page 157

D 15.1 Input Capture Control Registers P S 600 TABLE 15-1: INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP IC 0 1168J-page 15 Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 8 1 31:16 — — — — — — — — — — — — — — — — 0000 2000 IC1CON(1) X 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 31:16 xxxx X 2010 IC1BUF IC1BUF<31:0> 15:0 xxxx / 2 2200 IC2CON(1) 31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 31:16 xxxx X 2210 IC2BUF IC2BUF<31:0> 15:0 xxxx 2400 IC3CON(1) 31:16 — — — — — — — — — — — — — — — — 0000 2 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 8 31:16 xxxx / 2410 IC3BUF IC3BUF<31:0> 3 15:0 xxxx 6 2600 IC4CON(1) 31:16 — — — — — — — — — — — — — — — — 0000 / 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 4 31:16 xxxx 4 2610 IC4BUF IC4BUF<31:0> 15:0 xxxx - 2800 IC5CON(1) 31:16 — — — — — — — — — — — — — — — — 0000 P 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 I N 31:16 xxxx 2810 IC5BUF IC5BUF<31:0> 15:0 xxxx F Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more information. M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 15-1: ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 15:8 ON(1) — SIDL — — — FEDGE C32 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 7:0 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = unknown) P = Programmable bit r = Reserved bit bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Input Capture Module Enable bit(1) 1=Module is enabled 0=Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Control bit 1=Halt in Idle mode 0=Continue to operate in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110) 1=Capture rising edge first 0=Capture falling edge first bit 8 C32: 32-bit Capture Select bit 1=32-bit timer resource capture 0=16-bit timer resource capture bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’) 0=Timer3 is the counter source for capture 1=Timer2 is the counter source for capture bit 6-5 ICI<1:0>: Interrupt Control bits 11= Interrupt on every fourth capture event 10= Interrupt on every third capture event 01= Interrupt on every second capture event 00= Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1=Input capture overflow has occurred 0=No input capture overflow has occurred bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1=Input capture buffer is not empty; at least one more capture value can be read 0=Input capture buffer is empty Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.  2011-2016 Microchip Technology Inc. DS60001168J-page 159

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 15-1: ICXCON: INPUT CAPTURE ‘x’ CONTROL REGISTER (CONTINUED) bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111= Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110= Simple Capture Event mode – every edge, specified edge first and every edge thereafter 101= Prescaled Capture Event mode – every sixteenth rising edge 100= Prescaled Capture Event mode – every fourth rising edge 011= Simple Capture Event mode – every rising edge 010= Simple Capture Event mode – every falling edge 001= Edge Detect mode – every edge (rising and falling) 000= Input Capture module is disabled Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. DS60001168J-page 160  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 16.0 OUTPUT COMPARE The following are some of the key features: • Multiple Output Compare Modules in a device Note: This data sheet summarizes the features • Programmable interrupt generation on compare of the PIC32MX1XX/2XX 28/36/44-pin event Family of devices. It is not intended to be a comprehensive reference source. To • Single and Dual Compare modes complement the information in this data • Single and continuous output pulse generation sheet, refer to Section 16. “Output Com- • Pulse-Width Modulation (PWM) mode pare” (DS60001111), which is available • Hardware-based PWM Fault detection and from the Documentation > Reference automatic output disable Manual section of the Microchip PIC32 • Can operate from either of two available 16-bit web site (www.microchip.com/pic32). time bases or a single 32-bit time base The Output Compare module is used to generate a sin- gle pulse or a train of pulses in response to selected time base events. For all modes of operation, the Out- put Compare module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the Output Compare module generates an event based on the selected mode of operation. FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Output S Q OCx(1) Logic R Output Output Enable 3 Enable Logic OCM<2:0> Mode Select OCFA or OCFB(2) Comparator 0 1 OCTSEL 0 1 16 16 Timer2 Timer3 Timer2 Timer3 Rollover Rollover Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.  2011-2016 Microchip Technology Inc. DS60001168J-page 161

D 16.1 Output Compare Control Registers P S 60 TABLE 16-1: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP I 0 C 0 11 ss Bits 3 68J-page 16 Virtual Addre(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 2MX 2 31:16 — — — — — — — — — — — — — — — — 0000 1 3000 OC1CON 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 X 31:16 xxxx X 3010 OC1R OC1R<31:0> 15:0 xxxx / 31:16 xxxx 2 3020 OC1RS OC1RS<31:0> 15:0 xxxx X 3200 OC2CON31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 31:16 xxxx 2 3210 OC2R OC2R<31:0> 15:0 xxxx 8 3220 OC2RS 3115:1:06 OC2RS<31:0> xxxxxxxx /3 31:16 — — — — — — — — — — — — — — — — 0000 6 3400 OC3CON 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 / 4 31:16 xxxx 3410 OC3R OC3R<31:0> 4 15:0 xxxx - 31:16 xxxx P 3420 OC3RS OC3RS<31:0> 15:0 xxxx I 31:16 — — — — — — — — — — — — — — — — 0000 N 3600 OC4CON 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000 31:16 xxxx F 3610 OC4R OC4R<31:0> 15:0 xxxx A  3620 OC4RS 3115:1:06 OC4RS<31:0> xxxxxxxx M 2 0 31:16 — — — — — — — — — — — — — — — — 0000 I 1 3800 OC5CON L 1-20 3115:1:06 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0x0x0x0x Y 16 M 3810 OC5R 15:0 OC5R<31:0> xxxx icroc 3820 OC5RS 3115:1:06 OC5RS<31:0> xxxxxxxx h ip Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. T Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for e c more information. h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 16-1: OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 15:8 ON(1) — SIDL — — — — — U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — — OC32 OCFLT(2) OCTSEL OCM<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Output Compare Peripheral On bit(1) 1 = Output Compare peripheral is enabled 0 = Output Compare peripheral is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12-6 Unimplemented: Read as ‘0’ bit 5 OC32: 32-bit Compare Mode bit 1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisons to the 32-bit timer source 0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source bit 4 OCFLT: PWM Fault Condition Status bit(2) 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for this Output Compare module 0 = Timer2 is the clock source for this Output Compare module bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx; Fault pin enabled 110 = PWM mode on OCx; Fault pin disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: This bit is only used when OCM<2:0> = ‘111’. It is read as ‘0’ in all other modes.  2011-2016 Microchip Technology Inc. DS60001168J-page 163

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 164  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 17.0 SERIAL PERIPHERAL Some of the key features of the SPI module are: INTERFACE (SPI) • Master mode and Slave mode support • Four clock formats Note: This data sheet summarizes the features • Enhanced Framed SPI protocol support of the PIC32MX1XX/2XX 28/36/44-pin • User-configurable 8-bit, 16-bit and 32-bit data width Family of devices. It is not intended to be • Separate SPI FIFO buffers for receive and transmit a comprehensive reference source. To - FIFO buffers act as 4/8/16-level deep FIFOs complement the information in this data based on 32/16/8-bit data width sheet, refer to Section 23. “Serial • Programmable interrupt event on every 8-bit, Peripheral Interface (SPI)” 16-bit and 32-bit data transfer (DS60001106), which is available from the • Operation during Sleep and Idle modes Documentation > Reference Manual • Audio Codec Support: section of the Microchip PIC32 web site - I2S protocol (www.microchip.com/pic32). - Left-justified The SPI module is a synchronous serial interface that - Right-justified is useful for communicating with external peripherals - PCM and other microcontrollers. These peripheral devices may be Serial EEPROMs, Shift registers, display driv- ers, Analog-to-Digital Converters (ADC), etc. The PIC32 SPI module is compatible with Motorola® SPI and SIOP interfaces. FIGURE 17-1: SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read Write FIFOs Share Address SPIxBUF SPIxRXB FIFO SPIxTXB FIFO Transmit Receive SPIxSR SDIx bit 0 SDOx Shift MCLKSEL Control Slave Select Clock Edge and Frame Control Select SSx/FSYNC Sync Control 1 REFCLK Baud Rate Generator SCKx 0 PBCLK Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. MSTEN  2011-2016 Microchip Technology Inc. DS60001168J-page 165

D 17.1 SPI Control Registers P S 600 TABLE 17-1: SPI1 AND SPI2 REGISTER MAP IC 0 1168J-page 16 Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 6 1 31:16 FRMEN FRMSYNCFRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF 0000 5800 SPI1CON X 15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000 31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000 X 5810 SPI1STAT 15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008 / 31:16 0000 2 5820 SPI1BUF 15:0 DATA<31:0> 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 X 5830 SPI1BRG 15:0 — — — BRG<12:0> 0000 31:16 — — — — — — — — — — — — — — — — 0000 2 5840SPI1CON2 SPI FRM SPI SPI AUD 8 15:0 — — IGNROV IGNTUR AUDEN — — — — AUDMOD<1:0> 0000 SGNEXT ERREN ROVEN TUREN MONO / 31:16 FRMEN FRMSYNCFRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL — — — — — SPIFE ENHBUF 0000 3 5A00 SPI2CON 15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000 6 31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000 / 5A10 SPI2STAT 4 15:0 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008 4 31:16 0000 5A20 SPI2BUF DATA<31:0> - 15:0 0000 P 31:16 — — — — — — — — — — — — — — — — 0000 5A30 SPI2BRG I 15:0 — — — BRG<12:0> 0000 N 31:16 — — — — — — — — — — — — — — — — 0000 5A40SPI2CON2 SPI FRM SPI SPI AUD F 15:0 — — IGNROV IGNTUR AUDEN — — — — AUDMOD<1:0> 0000 SGNEXT ERREN ROVEN TUREN MONO A Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M  Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV 2 Registers” for more information. 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 23:16 MCLKSEL(2) — — — — — SPIFE ENHBUF(2) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 ON(1) — SIDL DISSDO MODE32 MODE16 SMP CKE(3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 SSEN CKP(4) MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output) 0 = Framed SPI support is disabled bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Slave mode) 0 = Frame sync pulse output (Master mode) bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only) 1 = Frame pulse is active-high 0 = Frame pulse is active-low bit 28 MSSEN: Master Mode Slave Select Enable bit 1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit. 0 = Slave select SPI support is disabled. bit 27 FRMSYPW: Frame Sync Pulse Width bit 1 = Frame sync pulse is one character wide 0 = Frame sync pulse is one clock wide bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in FRAMED_SYNC mode. 111 = Reserved; do not use 110 = Reserved; do not use 101 = Generate a frame sync pulse on every 32 data characters 100 = Generate a frame sync pulse on every 16 data characters 011 = Generate a frame sync pulse on every 8 data characters 010 = Generate a frame sync pulse on every 4 data characters 001 = Generate a frame sync pulse on every 2 data characters 000 = Generate a frame sync pulse on every data character bit 23 MCLKSEL: Master Clock Enable bit(2) 1 = REFCLK is used by the Baud Rate Generator 0 = PBCLK is used by the Baud Rate Generator bit 22-18 Unimplemented: Read as ‘0’ Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: This bit can only be written when the ON bit = 0. 3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN=1). 4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of CKP.  2011-2016 Microchip Technology Inc. DS60001168J-page 167

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 16 ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register 0 = SDOx pin is controlled by the module bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits When AUDEN = 1: MODE32 MODE16 Communication 1 1 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 1 0 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 0 1 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame 0 0 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame When AUDEN = 0: MODE32 MODE16 Communication 1 x 32-bit 0 1 16-bit 0 0 8-bit bit 9 SMP: SPI Data Input Sample Phase bit Master mode (MSTEN=1): 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode (MSTEN=0): SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0. To write a '1' to this bit, the MSTEN value = 1 must first be written. bit 8 CKE: SPI Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see the CKP bit) 0 = Serial output data changes on transition from Idle clock state to active clock state (see the CKP bit) bit 7 SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin used for Slave mode 0 = SSx pin not used for Slave mode, pin controlled by port function. bit 6 CKP: Clock Polarity Select bit(4) 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: This bit can only be written when the ON bit = 0. 3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN=1). 4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of CKP. DS60001168J-page 168  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode bit 4 DISSDI: Disable SDI bit 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits 11 = Interrupt is generated when the buffer is full 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: This bit can only be written when the ON bit = 0. 3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN=1). 4: When AUDEN = 1, the SPI module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of CKP.  2011-2016 Microchip Technology Inc. DS60001168J-page 169

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 17-2: SPIxCON2: SPI CONTROL REGISTER 2 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 SPISGNEXT — — FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 7:0 AUDEN(1) — — — AUDMONO(1,2) — AUDMOD<1:0>(1,2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit 1 = Data from RX FIFO is sign extended 0 = Data from RX FIFO is not sign extended bit 14-13 Unimplemented: Read as ‘0’ bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame Error overflow generates error events 0 = Frame Error does not generate error events bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = Receive overflow generates error events 0 = Receive overflow does not generate error events bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit underrun generates error events 0 = Transmit underrun does not generate error events bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions) 1 = A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data 0 = A ROV is a critical error that stops SPI operation bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions) 1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error that stops SPI operation bit 7 AUDEN: Enable Audio CODEC Support bit(1) 1 = Audio protocol enabled 0 = Audio protocol disabled bit 6-5 Unimplemented: Read as ‘0’ bit 3 AUDMONO: Transmit Audio Data Format bit(1,2) 1 = Audio data is mono (Each data word is transmitted on both left and right channels) 0 = Audio data is stereo bit 2 Unimplemented: Read as ‘0’ bit 1-0 AUDMOD<1:0>: Audio Protocol Mode bit(1,2) 11 = PCM/DSP mode 10 = Right-Justified mode 01 = Left-Justified mode 00 = I2S mode Note 1: This bit can only be written when the ON bit = 0. 2: This bit is only valid for AUDEN=1. DS60001168J-page 170  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 17-3: SPIxSTAT: SPI STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 31:24 — — — RXBUFELM<4:0> U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 23:16 — — — TXBUFELM<4:0> U-0 U-0 U-0 R/C-0, HS R-0 U-0 U-0 R-0 15:8 — — — FRMERR SPIBUSY — — SPITUR R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 7:0 SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF Legend: C = Clearable bit HS = Set in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1) bit 23-21 Unimplemented: Read as ‘0’ bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1) bit 15-13 Unimplemented: Read as ‘0’ bit 12 FRMERR: SPI Frame Error status bit 1 = Frame error detected 0 = No Frame error detected This bit is only valid when FRMEN=1. bit 11 SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle bit 10-9 Unimplemented: Read as ‘0’ bit 8 SPITUR: Transmit Under Run bit 1 = Transmit buffer has encountered an underrun condition 0 = Transmit buffer has no underrun condition This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling (ON bit =0) and re-enabling (ON bit = 1) the module, or writing a ‘0’ to SPITUR. bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1) 1 = When SPI module shift register is empty 0 = When SPI module shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred This bit is set in hardware; can bit only be cleared by disabling (ON bit =0) and re-enabling (ON bit = 1) the module, or by writing a ‘0’ to SPIROV. bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1) 1 = RX FIFO is empty (CRPTR = SWPTR) 0 = RX FIFO is not empty (CRPTR SWPTR) bit 4 Unimplemented: Read as ‘0’  2011-2016 Microchip Technology Inc. DS60001168J-page 171

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 17-3: SPIxSTAT: SPI STATUS REGISTER bit 3 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. bit 2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR. Enhanced Buffer Mode: Set when CWPTR + 1 = SRPTR; cleared otherwise bit 0 SPIRBF: SPI Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB is full 0 = Receive buffer, SPIxRXB is not full Standard Buffer Mode: Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode: Set when SWPTR + 1 = CRPTR; cleared otherwise DS60001168J-page 172  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 18.0 INTER-INTEGRATED CIRCUIT The I2C module provides complete hardware support (I2C) for both Slave and Multi-Master modes of the I2C serial communication standard. Figure18-1 illustrates the I2C module block diagram. Note: This data sheet summarizes the features of the PIC32MX1XX/2XX 28/36/44-pin Each I2C module has a 2-pin interface: the SCLx pin is Family of devices. It is not intended to be clock and the SDAx pin is data. a comprehensive reference source. To Each I2C module offers the following key features: complement the information in this data sheet, refer to Section 24. “Inter- • I2C interface supporting both master and slave Integrated Circuit (I2C)” (DS60001116), operation which is available from the Documentation • I2C Slave mode supports 7-bit and 10-bit addressing > Reference Manual section of the Micro- • I2C Master mode supports 7-bit and 10-bit chip PIC32 web site addressing (www.microchip.com/pic32). • I2C port allows bidirectional transfers between master and slaves • Serial clock synchronization for the I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) • I2C supports multi-master operation; detects bus collision and arbitrates accordingly • Provides support for address bit masking  2011-2016 Microchip Technology Inc. DS60001168J-page 173

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 18-1: I2C BLOCK DIAGRAM Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop bit Detect Write Start and Stop bit Generation I2CxSTAT c gi Read o CDoellitseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB ShiftClock Read Reload Control Write BRG Down Counter I2CxBRG Read PBCLK DS60001168J-page 174  2011-2016 Microchip Technology Inc.

 18.1 I2C Control Registers 2 0 1 TABLE 18-1: I2C1 AND I2C2 REGISTER MAP 1 -2016 Microchip Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T e 31:16 — — — — — — — — — — — — — — — — 0000 c 5000 I2C1CON hn 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 P ology 5010 I2C1STAT 3115::106 ACK—STAT TRS—TAT —— —— —— B—CL GC—STAT AD—D10 IW—COL I2C—OV D—_A —P —S R—_W R—BF T—BF 00000000 IC In 31:16 — — — — — — — — — — — — — — — — 0000 3 c 5020 I2C1ADD . 15:0 — — — — — — Address Register 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 M 5030 I2C1MSK 15:0 — — — — — — Address Mask Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 5040 I2C1BRG 15:0 — — — — Baud Rate Generator Register 0000 1 31:16 — — — — — — — — — — — — — — — — 0000 X 5050 I2C1TRN 15:0 — — — — — — — — Transmit Register 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 5060 I2C1RCV / 15:0 — — — — — — — — Receive Register 0000 2 31:16 — — — — — — — — — — — — — — — — 0000 X 5100 I2C2CON 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 X 31:16 — — — — — — — — — — — — — — — — 0000 5110 I2C2STAT 15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 2 5120 I2C2ADD 31:16 — — — — — — — — — — — — — — — — 0000 8 15:0 — — — — — — Address Register 0000 / 31:16 — — — — — — — — — — — — — — — — 0000 3 5130 I2C2MSK 15:0 — — — — — — Address Mask Register 0000 6 31:16 — — — — — — — — — — — — — — — — 0000 / 5140 I2C2BRG 4 15:0 — — — — Baud Rate Generator Register 0000 4 31:16 — — — — — — — — — — — — — — — — 0000 5150 I2C2TRN - 15:0 — — — — — — — — Transmit Register 0000 P 31:16 — — — — — — — — — — — — — — — — 0000 5160 I2C2RCV I 15:0 — — — — — — — — Receive Register 0000 N DS Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 60 Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV F 0 Registers” for more information. 0 A 1 1 68 M J -pa I g L e 1 Y 7 5

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 2 REGISTER 18-1: I2CXCON: I C CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 15:8 ON(1) — SIDL SCLREL STRICT A10M DISSLW SMEN R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC 7:0 GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN Legend: HC = Cleared in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: I2C Enable bit(1) 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables the I2C module; all I2C pins are controlled by PORT functions bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space. 0 = Strict I2C Reserved Address Rule not enabled bit 10 A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. DS60001168J-page 176  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 2 REGISTER 18-1: I2CXCON: I C CONTROL REGISTER (CONTINUED) bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send a NACK during an Acknowledge sequence 0 = Send an ACK during an Acknowledge sequence bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.  2011-2016 Microchip Technology Inc. DS60001168J-page 177

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 2 REGISTER 18-2: I2CXSTAT: I C STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC 15:8 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC 7:0 IWCOL I2COV D_A P S R_W RBF TBF Legend: HS = Set in hardware HSC = Hardware set/cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit bit 31-16 Unimplemented: Read as ‘0’ bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave Hardware set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. This condition can only be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the module. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. DS60001168J-page 178  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 2 REGISTER 18-2: I2CXSTAT: I C STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware set or clear after reception of I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.  2011-2016 Microchip Technology Inc. DS60001168J-page 179

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 180  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 19.0 UNIVERSAL ASYNCHRONOUS Key features of the UART module include: RECEIVER TRANSMITTER • Full-duplex, 8-bit or 9-bit data transmission (UART) • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits Note: This data sheet summarizes the features • Hardware auto-baud feature of the PIC32MX1XX/2XX 28/36/44-pin • Hardware flow control option Family of devices. It is not intended to be • Fully integrated Baud Rate Generator (BRG) with a comprehensive reference source. To 16-bit prescaler complement the information in this data sheet, refer to Section 21. “Universal • Baud rates ranging from 38 bps to 12.5 Mbps at Asynchronous Receiver Transmitter 50 MHz (UART)” (DS60001107), which is avail- • 8-level deep First In First Out (FIFO) transmit data able from the Documentation > Reference buffer Manual section of the Microchip PIC32 • 8-level deep FIFO receive data buffer web site (www.microchip.com/pic32). • Parity, framing and buffer overrun error detection The UART module is one of the serial I/O modules • Support for interrupt-only on address detect available in PIC32MX1XX/2XX 28/36/44-pin Family (9th bit=1) devices. The UART is a full-duplex, asynchronous • Separate transmit and receive interrupts communication channel that communicates with • Loopback mode for diagnostic support peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN, and IrDA®. • LIN protocol support The UART module also supports the hardware flow • IrDA encoder and decoder with 16x baud clock control option, with UxCTS and UxRTS pins, and also output for external IrDA encoder/decoder support includes an IrDA encoder and decoder. Figure19-1 illustrates a simplified block diagram of the UART module. FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® UxRTS/BCLKx Hardware Flow Control UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.  2011-2016 Microchip Technology Inc. DS60001168J-page 181

D 19.1 UART Control Registers P S 600 TABLE 19-1: UART1 AND UART2 REGISTER MAP IC 0 1168J-page 18 Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 2 1 31:16 — — — — — — — — — — — — — — — — 0000 6000 U1MODE(1) X 15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000 X 6010 U1STA(1) 15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 / 31:16 — — — — — — — — — — — — — — — — 0000 2 6020 U1TXREG 15:0 — — — — — — — Transmit Register 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 X 6030 U1RXREG 15:0 — — — — — — — Receive Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 2 6040 U1BRG(1) 15:0 Baud Rate Generator Prescaler 0000 8 6200 U2MODE(1) 31:16 — — — — — — — — — — — — — — — — 0000 /3 15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000 6 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000 6210 U2STA(1) / 15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 4 6220 U2TXREG 31:16 — — — — — — — — — — — — — — — — 0000 4 15:0 — — — — — — — Transmit Register 0000 - 31:16 — — — — — — — — — — — — — — — — 0000 P 6230 U2RXREG 15:0 — — — — — — — Receive Register 0000 I 31:16 — — — — — — — — — — — — — — — — 0000 N 6240 U2BRG(1) 15:0 Baud Rate Generator Prescaler 0000 F Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more information. A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 19-1: UxMODE: UARTx MODE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 15:8 ON(1) — SIDL IREN RTSMD — UEN<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: UARTx Enable bit(1) 1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by the UEN<1:0> and UTXEN control bits. 0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal. bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12 IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = Wake-up enabled 0 = Wake-up disabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Loopback mode is enabled 0 = Loopback mode is disabled Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.  2011-2016 Microchip Technology Inc. DS60001168J-page 183

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x baud clock enabled 0 = Standard Speed mode – 16x baud clock enabled bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. DS60001168J-page 184  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 31:24 — — — — — — — ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 ADDR<7:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 15:8 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/W-0 R-0 7:0 URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Read as ‘0’ bit 24 ADM_EN: Automatic Address Detect Mode Enable bit 1 = Automatic Address Detect mode is enabled 0 = Automatic Address Detect mode is disabled bit 23-16 ADDR<7:0>: Automatic Address Mask bits When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address detection. bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated and asserted while the transmit buffer is empty 01 = Interrupt is generated and asserted when all characters have been transmitted 00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 UTXINV: Transmit Polarity Inversion bit If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is ‘0’): 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’): 1 = IrDA encoded UxTX Idle state is ‘1’ 0 = IrDA encoded UxTX Idle state is ‘0’ bit 12 URXEN: Receiver Enable bit 1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON=1) 0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port. bit 11 UTXBRK: Transmit Break bit 1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Break transmission is disabled or completed bit 10 UTXEN: Transmit Enable bit 1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON=1). 0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is controlled by port. bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer  2011-2016 Microchip Technology Inc. DS60001168J-page 185

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved; do not use 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters) 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters) 00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) bit 5 ADDEN: Address Character Detect bit(bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect. 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Data is being received bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit. This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and the RSR to an empty state. 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty DS60001168J-page 186  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Figure19-2 and Figure19-3 illustrate typical receive and transmit timing for the UART module. FIGURE 19-2: UART RECEPTION Char 1 Char 2-4 Char 5-10 Char 11-13 Read to UxRXREG Start 1 Stop Start 2 Stop 4 Start 5 Stop 10Start 11 Stop 13 UxRX RIDLE Cleared by Software OERR Cleared by Software UxRXIF URXISEL = 00 Cleared by Software UxRXIF URXISEL = 01 UxRXIF URXISEL = 10 FIGURE 19-3: TRANSMISSION (8-BIT OR 9-BIT DATA) 8 into TxBUF Write to UxTXREG TSR BCLK/16 Pull from Buffer (Shift Clock) UxTX Start Bit 0 Bit 1 Stop Start Bit 1 UxTXIF UTXISEL = 00 UxTXIF UTXISEL = 01 UxTXIF UTXISEL = 10  2011-2016 Microchip Technology Inc. DS60001168J-page 187

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 188  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 20.0 PARALLEL MASTER PORT Key features of the PMP module include: (PMP) • Fully multiplexed address/data mode • Demultiplexed or partially multiplexed address/ Note: This data sheet summarizes the features data mode of the PIC32MX1XX/2XX 28/36/44-pin - up to 11 address lines with single Chip Select Family of devices. It is not intended to be - up to 12 address lines without Chip Select a comprehensive reference source. To complement the information in this data • One Chip Select line sheet, refer to Section 13. “Parallel • Programmable strobe options Master Port (PMP)” (DS60001128), - Individual read and write strobes or; which is available from the Documentation - Read/write strobe with enable strobe > Reference Manual section of the • Address auto-increment/auto-decrement Microchip PIC32 web site • Programmable address/data multiplexing (www.microchip.com/pic32). • Programmable polarity on control signals The PMP is a parallel 8-bit input/output module • Legacy parallel slave port support specifically designed to communicate with a wide • Enhanced parallel slave support variety of parallel devices, such as communications - Address support peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel - 4-byte deep auto-incrementing buffer peripherals varies significantly, the PMP module is • Programmable Wait states highly configurable. • Selectable input voltage levels Figure20-1 illustrates the PMP module block diagram. FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus Control Lines PIC32MX1XX/2XX Parallel PMA<0> Master Port PMALL PMA<1> PMALH Up to 12-bit Address Flash EEPROM SRAM PMA<10:2> PMA<14> PMCS1 PMRD PMRD/PMWR FIFO PMWR Microcontroller LCD Buffer PMENB PMD<7:0> 8-bit Data (with or without multiplexed addressing)  2011-2016 Microchip Technology Inc. DS60001168J-page 189

D 20.1 PMP Control Registers P S 600 TABLE 20-1: PARALLEL MASTER PORT REGISTER MAP IC 0 1168J-page 19 Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 0 1 31:16 — — — — — — — — — — — — — — — — 0000 7000 PMCON X 15:0 ON — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP — CS1P — WRSP RDSP 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 7010 PMMODE 15:0 BUSY IRQM<1:0> INCM<1:0> — MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000 / 31:16 — — — — — — — — — — — — — — — — 0000 2 7020 PMADDR CS1 0000 X 15:0 — — — — ADDR<10:0> ADDR14 X 31:16 0000 7030 PMDOUT DATAOUT<31:0> 15:0 0000 2 31:16 0000 8 7040 PMDIN DATAIN<31:0> 15:0 0000 / 3 31:16 — — — — — — — — — — — — — — — — 0000 7050 PMAEN 6 15:0 — PTEN14 — — — PTEN<10:0> 0000 / 31:16 — — — — — — — — — — — — — — — — 0000 4 7060 PMSTAT 15:0 IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F 4 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. - Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for P more information. I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 ON(1) — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 7:0 CSF<1:0>(2) ALP(2) — CS1P(2) — WRSP RDSP Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Parallel Master Port Enable bit(1) 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 8 bits are not used 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and PMA<14> 00 = Address and data appear on separate pins bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffer bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled bit 7-6 CSF<1:0>: Chip Select Function bits(2) 11 = Reserved 10 = PMCS1 functions as Chip Select 01 = PMCS1 functions as PMA<14> 00 = PMCS1 functions as PMA<14> bit 5 ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) Note1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines.  2011-2016 Microchip Technology Inc. DS60001168J-page 191

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 4 Unimplemented: Read as ‘0’ bit 3 CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) bit 2 Unimplemented: Read as ‘0’ bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (MODE<1:0>=00,01,10): 1=Write strobe active-high (PMWR) 0=Write strobe active-low (PMWR) For Master mode 1 (MODE<1:0>=11): 1=Enable strobe active-high (PMENB) 0=Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (MODE<1:0>=00,01,10): 1=Read Strobe active-high (PMRD) 0=Read Strobe active-low (PMRD) For Master mode 1 (MODE<1:0>=11): 1=Read/write strobe active-high (PMRD/PMWR) 0=Read/write strobe active-low (PMRD/PMWR) Note1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. DS60001168J-page 192  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 15:8 BUSY IRQM<1:0> INCM<1:0> — MODE<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 WAITB<1:0>(1) WAITM<3:0>(1) WAITE<1:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Reserved, do not use 10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only) 01 = Interrupt generated at the end of the read/write cycle 00 = No Interrupt generated bit 12-11 INCM<1:0>: Increment Mode bits 11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only) 10 = Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2) 01 = Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2) 00 = No increment or decrement of address bit 10 Unimplemented: Read as ‘0’ bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<7:0>) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<7:0>) 01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>) bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1) 11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB 10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB 01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB 00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB • • • 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) Note1: Whenever WAITM<3:0>=0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB=1 TPBCLK cycle, WAITE=0 TPBCLK cycles for a read operation. 2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.  2011-2016 Microchip Technology Inc. DS60001168J-page 193

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) Note1: Whenever WAITM<3:0>=0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB=1 TPBCLK cycle, WAITE=0 TPBCLK cycles for a read operation. 2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1. DS60001168J-page 194  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 20-3: PMADDR: PARALLEL PORT ADDRESS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 15:8 CS1(1) — — — — ADDR<10:8> ADDR14(2) 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as ‘0’ bit 14 CS1: Chip Select 1 bit(1) 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive bit 14 ADDR<14>: Destination Address bit 14(2) bit 13-11 Unimplemented: Read as ‘0’ bit 10-0 ADDR<10:0>: Destination Address bits Note 1: When the CSF<1:0> bits (PMCON<7:6>) = 10. 2: When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.  2011-2016 Microchip Technology Inc. DS60001168J-page 195

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 20-4: PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 15:8 — PTEN14 — — — PTEN<10:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 PTEN<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as ‘0’ bit 15-14 PTEN14: PMCS1 Address Port Enable bits 1 = PMA14 functions as either PMA14 or PMCS1(1) 0 = PMA14 functions as port I/O bit 13-11 Unimplemented: Read as ‘0’ bit 10-2 PTEN<10:2>: PMP Address Port Enable bits 1 = PMA<10:2> function as PMP address lines 0 = PMA<10:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Address Port Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads functions as port I/O Note1: The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register. 2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by bits ADRMUX<1:0> in the PMCON register. DS60001168J-page 196  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 20-5: PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY) Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0 15:8 IBF IBOV — — IB3F IB2F IB1F IB0F R-1 R/W-0, HSC U-0 U-0 R-1 R-1 R-1 R-1 7:0 OBE OBUF — — OB3E OB2E OB1E OB0E Legend: HSC = Set by Hardware; Cleared by Software R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte buffer occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IBxF: Input Buffer ‘x’ Status Full bits 1 = Input Buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input Buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte buffer (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OBxE: Output Buffer ‘x’ Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted  2011-2016 Microchip Technology Inc. DS60001168J-page 197

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 198  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 21.0 REAL-TIME CLOCK AND Following are some of the key features of this module: CALENDAR (RTCC) • Time: hours, minutes and seconds • 24-hour format (military time) Note: This data sheet summarizes the features • Visibility of one-half second period of the PIC32MX1XX/2XX 28/36/44-pin • Provides calendar: day, date, month and year Family of devices. It is not intended to be a comprehensive reference source. To • Alarm intervals are configurable for half of a complement the information in this data second, one second, 10 seconds, one minute, 10 sheet, refer to Section 29. “Real-Time minutes, one hour, one day, one week, one month Clock and Calendar (RTCC)” and one year (DS60001125), which is available from the • Alarm repeat with decrementing counter Documentation > Reference Manual • Alarm with indefinite repeat: Chime section of the Microchip PIC32 web site • Year range: 2000 to 2099 (www.microchip.com/pic32). • Leap year correction The PIC32 RTCC module is intended for applications in • BCD format for smaller firmware overhead which accurate time must be maintained for extended • Optimized for long-term battery operation periods of time with minimal or no CPU intervention. • Fractional second synchronization Low-power optimization provides extended battery • User calibration of the clock crystal frequency with lifetime while keeping track of time. auto-adjust • Calibration range: 0.66 seconds error per month • Calibrates up to 260 ppm of crystal error • Requirements: External 32.768 kHz clock crystal • Alarm pulse or seconds clock output on RTCC pin FIGURE 21-1: RTCC BLOCK DIAGRAM CAL<9:0> 32.768 kHz Input from Secondary Oscillator (SOSC) RTCC Prescalers RTCTIME 0.5s HR, MIN, SEC RTCC Timer RTCVAL RTCDATE Alarm YEAR, MONTH, DAY, WDAY Event Comparator ALRMTIME HR, MIN, SEC Compare Registers ALRMVAL with Masks ALRMDATE MONTH, DAY, WDAY Repeat Counter Set RTCC Flag 0 RTCC Interrupt Logic Alarm Pulse 1 Seconds Pulse RTCC RTSECSEL RTCOE  2011-2016 Microchip Technology Inc. DS60001168J-page 199

D 21.1 RTCC Control Registers P S 600 TABLE 21-1: RTCC REGISTER MAP IC 0 1168J-page 20 Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 0 1 31:16 — — — — — — CAL<9:0> 0000 0200 RTCCON X 15:0 ON — SIDL — — — — — RTSECSELRTCCLKON — — RTCWRENRTCSYNCHALFSEC RTCOE 0000 31:16 — — — — — — — — — — — — — — — — 0000 X 0210 RTCALRM 15:0 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000 / 31:16 — — HR10<1:0> HR01<3:0> — MIN10<2:0> MIN01<3:0> xxxx 2 0220 RTCTIME 15:0 — SEC10<2:0> SEC01<3:0> — — — — — — — — xx00 X 31:16 YEAR10<3:0> YEAR01<3:0> — — — MONTH10 MONTH01<3:0> xxxx X 0230 RTCDATE 15:0 — — DAY10<1:0> DAY01<3:0> — — — — — WDAY01<2:0> xx00 31:16 — — HR10<1:0> HR01<3:0> — MIN10<2:0> MIN01<3:0> xxxx 2 0240 ALRMTIME 15:0 — SEC10<2:0> SEC01<3:0> — — — — — — — — xx00 8 31:16 — — — — — — — — — — — MONTH10 MONTH01<3:0> 00xx / 0250 ALRMDATE 3 15:0 DAY10<3:0> DAY01<3:0> — — — — — WDAY01<2:0> xx0x 6 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for more 4 information. 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 21-1: RTCCON: RTC CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 31:24 — — — — — — CAL<9:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 CAL<7:0> R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 15:8 ON(1,2) — SIDL — — — — — R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0 7:0 RTSECSEL(3) RTCCLKON — — RTCWREN(4) RTCSYNC HALFSEC(5) RTCOE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as ‘0’ bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value 0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute • • • 0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute 0000000000 = No adjustment 1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute • • • 1000000000 = Maximum negative adjustment, subtracts 512 clock pulses every one minute bit 15 ON: RTCC On bit(1,2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Disables the PBCLK to the RTCC when the device enters Idle mode 0 = Continue normal operation when the device enters Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 RTSECSEL: RTCC Seconds Clock Output Select bit(3) 1 = RTCC Seconds Clock is selected for the RTCC pin 0 = RTCC Alarm Pulse is selected for the RTCC pin bit 6 RTCCLKON: RTCC Clock Enable Status bit 1 = RTCC Clock is actively running 0 = RTCC Clock is not running Note 1: The ON bit is only writable when RTCWREN = 1. 2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active. 4: The RTCWREN bit can be set only when the write sequence is enabled. 5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>). Note: This register is reset only on a Power-on Reset (POR).  2011-2016 Microchip Technology Inc. DS60001168J-page 201

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 21-1: RTCCON: RTC CONTROL REGISTER (CONTINUED) bit 5-4 Unimplemented: Read as ‘0’ bit 3 RTCWREN: RTC Value Registers Write Enable bit(4) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read If the register is read twice and results in the same data, the data can be assumed to be valid 0 = RTC Value registers can be read without concern about a rollover ripple bit 1 HALFSEC: Half-Second Status bit(5) 1 = Second half period of a second 0 = First half period of a second bit 0 RTCOE: RTCC Output Enable bit 1 = RTCC clock output enabled – clock presented onto an I/O 0 = RTCC clock output disabled Note 1: The ON bit is only writable when RTCWREN = 1. 2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active. 4: The RTCWREN bit can be set only when the write sequence is enabled. 5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>). Note: This register is reset only on a Power-on Reset (POR). DS60001168J-page 202  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 ALRMEN(1,2) CHIME(2) PIV(2) ALRMSYNC(3) AMASK<3:0>(2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 ARPT<7:0>(2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ALRMEN: Alarm Enable bit(1,2) 1 = Alarm is enabled 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit(2) 1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF 0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00 bit 13 PIV: Alarm Pulse Initial Value bit(2) When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse. When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse. bit 12 ALRMSYNC: Alarm Sync bit(3) 1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing, which are then synchronized to the PB clock domain 0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC clocks away from a half-second rollover bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(2) 0000 = Every half-second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29, once every four years) 1010 = Reserved; do not use 1011 = Reserved; do not use 11xx = Reserved; do not use Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0>=00 and CHIME=0. 2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC=1. 3: This assumes a CPU read will execute in less than 32 PBCLKs. Note: This register is reset only on a Power-on Reset (POR).  2011-2016 Microchip Technology Inc. DS60001168J-page 203

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED) bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits(2) 11111111 = Alarm will trigger 256 times • • • 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME=1. Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0>=00 and CHIME=0. 2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC=1. 3: This assumes a CPU read will execute in less than 32 PBCLKs. Note: This register is reset only on a Power-on Reset (POR). DS60001168J-page 204  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 21-3: RTCTIME: RTC TIME VALUE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 31:24 — — HR10<1:0> HR01<3:0> U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 23:16 — MIN10<2:0> MIN01<3:0> U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 15:8 — SEC10<2:0> SEC01<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 7:0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29-28 HR10<1:0>: Binary-Coded Decimal Value of Hours bits, 10s place digit; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1s place digit; contains a value from 0 to 9 bit 23 Unimplemented: Read as ‘0’ bit 22-20 MIN10<2:0>: Binary-Coded Decimal Value of Minutes bits, 10s place digit; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1s place digit; contains a value from 0 to 9 bit 15 Unimplemented: Read as ‘0’ bit 14-12 SEC10<2:0>: Binary-Coded Decimal Value of Seconds bits, 10s place digit; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1s place digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as ‘0’ Note: This register is only writable when RTCWREN=1 (RTCCON<3>).  2011-2016 Microchip Technology Inc. DS60001168J-page 205

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 21-4: RTCDATE: RTC DATE VALUE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 31:24 YEAR10<3:0> YEAR01<3:0> U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x 23:16 — — — MONTH10 MONTH01<3:0> U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 15:8 — — DAY10<1:0> DAY01<3:0> U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x 7:0 — — — — — WDAY01<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10s place digit; contains a value from 0 to 9 bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1s place digit; contains a value from 0 to 9 bit 23-21 Unimplemented: Read as ‘0’ bit 20 MONTH10: Binary-Coded Decimal Value of Months bits, 10s place digit; contains a value of 0 or 1 bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1s place digit; contains a value from 0 to 9 bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 DAY10<1:0>: Binary-Coded Decimal Value of Days bits, 10s place digit; contains a value of 0 to 3 bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1s place digit; contains a value from 0 to 9 bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY01<2:0>: Binary-Coded Decimal Value of Weekdays bits; contains a value from 0 to 6 Note: This register is only writable when RTCWREN=1 (RTCCON<3>). DS60001168J-page 206  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 21-5: ALRMTIME: ALARM TIME VALUE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 31:24 — — HR10<1:0> HR01<3:0> U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 23:16 — MIN10<2:0> MIN01<3:0> U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 15:8 — SEC10<2:0> SEC01<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 7:0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29-28 HR10<1:0>: Binary Coded Decimal value of hours bits, 10s place digit; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1s place digit; contains a value from 0 to 9 bit 23 Unimplemented: Read as ‘0’ bit 22-20 MIN10<2:0>: Binary Coded Decimal value of minutes bits, 10s place digit; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1s place digit; contains a value from 0 to 9 bit 15 Unimplemented: Read as ‘0’ bit 14-12 SEC10<2:0>: Binary Coded Decimal value of seconds bits, 10s place digit; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1s place digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as ‘0’  2011-2016 Microchip Technology Inc. DS60001168J-page 207

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 21-6: ALRMDATE: ALARM DATE VALUE REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x 23:16 — — — MONTH10 MONTH01<3:0> U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 15:8 — — DAY10<1:0> DAY01<3:0> U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x 7:0 — — — — — WDAY01<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-21 Unimplemented: Read as ‘0’ bit 20 MONTH10: Binary Coded Decimal value of months bits, 10s place digit; contains a value of 0 or 1 bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1s place digit; contains a value from 0 to 9 bit 15-14 Unimplemented: Read as ‘0’ bit 13-12 DAY10<1:0>: Binary Coded Decimal value of days bits, 10s place digit; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1s place digit; contains a value from 0 to 9 bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY01<2:0>: Binary Coded Decimal value of weekdays bits; contains a value from 0 to 6 DS60001168J-page 208  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 22.0 10-BIT ANALOG-TO-DIGITAL • Up to 13 analog input pins CONVERTER (ADC) • External voltage reference input pins • One unipolar, differential Sample and Hold Note: This data sheet summarizes the features Amplifier (SHA) of the PIC32MX1XX/2XX 28/36/44-pin • Automatic Channel Scan mode Family of devices. It is not intended to be • Selectable conversion trigger source a comprehensive reference source. To • 16-word conversion result buffer complement the information in this data • Selectable buffer fill modes sheet, refer to Section 17. “10-bit Ana- log-to-Digital Converter (ADC)” • Eight conversion result format options (DS60001104), which is available from the • Operation during Sleep and Idle modes Documentation > Reference Manual A block diagram of the 10-bit ADC is illustrated in section of the Microchip PIC32 web site Figure22-1. Figure22-2 illustrates a block diagram of (www.microchip.com/pic32). the ADC conversion clock period. The 10-bit ADC has up to 13 analog input pins, designated AN0-AN12. In The 10-bit Analog-to-Digital Converter (ADC) includes addition, there are two analog input pins for external the following features: voltage reference connections. These voltage • Successive Approximation Register (SAR) reference inputs may be shared with other analog input conversion pins and may be common to other analog module • Up to 1 Msps conversion speed references. FIGURE 22-1: ADC1 MODULE BLOCK DIAGRAM CTMUI(3) VREF+(1) AVDD VREF-(1) AVSS AN0 AN12(2) VCFG<2:0> CTMUT(3) ADC1BUF0 IVREF(4) ADC1BUF1 Open(5) ADC1BUF2 S&H VREFH VREFL Channel Scan + CH0SA<4:0> CH0SB<4:0> - SAR ADC CSCNA AN1 ADC1BUFE VREFL ADC1BUFF CH0NA CH0NB Alternate Input Selection Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs. 2: AN8 is only available on 44-pin devices. AN6, AN7, and AN12 are not available on 28-pin devices. 3: Connected to the CTMU module. See Section25.0 “Charge Time Measurement Unit (CTMU)” for more information. 4: Internal precision voltage reference (1.2V). 5: This selection is only used with CTMU capacitive and time measurement.  2011-2016 Microchip Technology Inc. DS60001168J-page 209

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC(1) Div 2 1 TAD ADCS<7:0> 0 8 ADC Conversion Clock Multiplier TPB(2) 2, 4,..., 512 Note 1: See Section30.0 “Electrical Characteristics” for the exact FRC clock value. 2: Refer to Figure8-1 in Section8.0 “Oscillator Configuration” for more information. DS60001168J-page 210  2011-2016 Microchip Technology Inc.

 22.1 ADC Control Registers 2 0 1 TABLE 22-1: ADC REGISTER MAP 1 -2016 Microchip Virtual Address(BF80_#) RNegaimsteer Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets T ec 9000AD1CON1(1)31:16 — — — — — — — — — — — — — — — — 0000 hn 15:0 ON — SIDL — — FORM<2:0> SSRC<2:0> CLRASAM — ASAM SAMP DONE 0000 P o log 9010AD1CON2(1)31:16 — — — — — — — — — — — — — — — — 0000 IC y 15:0 VCFG<2:0> OFFCAL — CSCNA — — BUFS — SMPI<3:0> BUFM ALTS 0000 Inc. 9020AD1CON3(1)3115:1:06 AD—RC —— —— — — SAMC—<4:0> — — — — — —ADCS<7:0—> — — — 00000000 32 31:16 CH0NB — — — CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000 M 9040 AD1CHS(1) 15:0 — — — — — — — — — — — — — — — — 0000 X 31:16 — — — — — — — — — — — — — — — — 0000 9050 AD1CSSL(1) 1 15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 X 31:16 0000 9070 ADC1BUF0 ADC Result Word 0 (ADC1BUF0<31:0>) 15:0 0000 X 31:16 0000 / 9080 ADC1BUF1 ADC Result Word 1 (ADC1BUF1<31:0>) 2 15:0 0000 X 31:16 0000 9090 ADC1BUF2 15:0 ADC Result Word 2 (ADC1BUF2<31:0>) 0000 X 31:16 0000 90A0 ADC1BUF3 ADC Result Word 3 (ADC1BUF3<31:0>) 2 15:0 0000 8 31:16 0000 90B0 ADC1BUF4 ADC Result Word 4 (ADC1BUF4<31:0>) / 15:0 0000 3 31:16 0000 6 90C0 ADC1BUF5 ADC Result Word 5 (ADC1BUF5<31:0>) 15:0 0000 / 4 31:16 0000 90D0 ADC1BUF6 ADC Result Word 6 (ADC1BUF6<31:0>) 4 15:0 0000 - 31:16 0000 P 90E0 ADC1BUF7 ADC Result Word 7 (ADC1BUF7<31:0>) 15:0 0000 I 31:16 0000 N D 90F0 ADC1BUF8 ADC Result Word 8 (ADC1BUF8<31:0>) S 15:0 0000 60001 9100 ADC1BUF9 3115:1:06 ADC Result Word 9 (ADC1BUF9<31:0>) 00000000 FA 1 68J-pag L9e1g1e0ndA:DC1BxU =FA un3k11n5:o1:0w6n value on Reset; — = unimplemented, read as ‘0’. Reset values are shAoDwCn Rine hseuxlta Wdeocridm Aa l.(ADC1BUFA<31:0>) 00000000 MIL e 2 Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for details. Y 1 1

D TABLE 22-1: ADC REGISTER MAP (CONTINUED) P S 60001168J-pag Virtual Address(BF80_#) RNegaimsteer Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets IC32M e 2 9120 ADC1BUFB 31:16 ADC Result Word B (ADC1BUFB<31:0>) 0000 X 12 15:0 0000 1 31:16 0000 9130 ADC1BUFC ADC Result Word C (ADC1BUFC<31:0>) X 15:0 0000 X 31:16 0000 9140 ADC1BUFD ADC Result Word D (ADC1BUFD<31:0>) 15:0 0000 / 2 31:16 0000 9150 ADC1BUFE ADC Result Word E (ADC1BUFE<31:0>) X 15:0 0000 X 31:16 0000 9160 ADC1BUFF 15:0 ADC Result Word F (ADC1BUFF<31:0>) 0000 2 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 8 Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for details. / 3 6 / 4 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 15:8 ON(1) — SIDL — — FORM<2:0> R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC 7:0 SSRC<2:0> CLRASAM — ASAM SAMP(2) DONE(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: ADC Operating Mode bit(1) 1 = ADC module is operating 0 = ADC module is not operating bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 FORM<2:0>: Data Output Format bits 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 =Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = CTMU ends sampling and starts conversion 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if ASAM=1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ‘0’, this bit is automatically cleared by hardware to end sampling and start conversion. 3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion.  2011-2016 Microchip Technology Inc. DS60001168J-page 213

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated. 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence bit 3 Unimplemented: Read as ‘0’ bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set. 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit(2) 1 = The ADC sample and hold amplifier is sampling 0 = The ADC sample/hold amplifier is holding When ASAM=0, writing ‘1’ to this bit starts sampling. When SSRC=000, writing ‘0’ to this bit will end sampling and start conversion. bit 0 DONE: Analog-to-Digital Conversion Status bit(3) 1 = Analog-to-digital conversion is done 0 = Analog-to-digital conversion is not done or has not started Clearing this bit will not affect any operation in progress. Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if ASAM=1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ‘0’, this bit is automatically cleared by hardware to end sampling and start conversion. 3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. DS60001168J-page 214  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 22-2: AD1CON2: ADC CONTROL REGISTER 2 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 15:8 VCFG<2:0> OFFCAL — CSCNA — — R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 BUFS — SMPI<3:0> BUFM ALTS Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits VREFH VREFL 000 AVDD AVss 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin 1xx AVDD AVSS bit 12 OFFCAL: Input Offset Calibration Mode Select bit 1 = Enable Offset Calibration mode Positive and negative inputs of the sample and hold amplifier are connected to VREFL 0 = Disable Offset Calibration mode The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL bit 11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Input Scan Select bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit Only valid when BUFM=1. 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 =Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 =Interrupts at the completion of conversion for each 15th sample/convert sequence • • • 0001 =Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 =Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8 0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0 bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples 0 = Always use Sample A input multiplexer settings  2011-2016 Microchip Technology Inc. DS60001168J-page 215

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 22-3: AD1CON3: ADC CONTROL REGISTER 3 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 ADRC — — SAMC<4:0>(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W R/W-0 7:0 ADCS<7:0>(2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ADRC: ADC Conversion Clock Source bit 1 = Clock derived from FRC 0 = Clock derived from Peripheral Bus Clock (PBCLK) bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1) 11111 =31 TAD • • • 00001 =1 TAD 00000 =0 TAD (Not allowed) bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 =TPB • 2 • (ADCS<7:0> + 1) = 512 • TPB = TAD • • • 00000001 =TPB • 2 • (ADCS<7:0> + 1) = 4 • TPB = TAD 00000000 =TPB • 2 • (ADCS<7:0> + 1) = 2 • TPB = TAD Note 1: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111. 2: This bit is not used if the ADRC (AD1CON3<15>) bit = 1. DS60001168J-page 216  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 22-4: AD1CHS: ADC INPUT SELECT REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 CH0NB — — — CH0SB<3:0> R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 23:16 CH0NA — — — CH0SA<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 7:0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 CH0NB: Negative Input Select bit for Sample B 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 30-28 Unimplemented: Read as ‘0’ bit 27-24 CH0SB<3:0>: Positive Input Select bits for Sample B 1111 =Channel 0 positive input is Open(1) 1110 =Channel 0 positive input is IVREF(2) 1101 =Channel 0 positive input is CTMU temperature sensor (CTMUT)(3) 1100 = Channel 0 positive input is AN12(4) • • • 0001 =Channel 0 positive input is AN1 0000 =Channel 0 positive input is AN0 bit 23 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting(2) 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 22-20 Unimplemented: Read as ‘0’ bit 19-16 CH0SA<3:0>: Positive Input Select bits for Sample A Multiplexer Setting 1111 =Channel 0 positive input is Open(1) 1110 =Channel 0 positive input is IVREF(2) 1101 =Channel 0 positive input is CTMU temperature (CTMUT)(3) 1100 = Channel 0 positive input is AN12(4) • • • 0001 =Channel 0 positive input is AN1 0000 =Channel 0 positive input is AN0 bit 15-0 Unimplemented: Read as ‘0’ Note 1: This selection is only used with CTMU capacitive and time measurement. 2: See Section24.0 “Comparator Voltage Reference (CVREF)” for more information. 3: See Section25.0 “Charge Time Measurement Unit (CTMU)” for more information. 4: AN12 is only available on 44-pin devices. AN6-AN8 are not available on 28-pin devices.  2011-2016 Microchip Technology Inc. DS60001168J-page 217

PIC32MX1XX/2XX 28/36/44-PIN FAMILY R EGISTER 22-5: AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CSSL<15:0>: ADC Input Pin Scan Selection bits(1,2) 1 = Select ANx for input scan 0 = Skip ANx for input scan Note 1: CSSL = ANx, where ‘x’ = 0-12; CSSL13 selects CTMU input for scan; CSSL14 selects IVREF for scan; CSSL15 selects VSS for scan. 2: On devices with less than 13 analog inputs, all CSSLx bits can be selected; however, inputs selected for scan without a corresponding input on the device will convert to VREFL. DS60001168J-page 218  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 23.0 COMPARATOR Following are some of the key features of this module: • Selectable inputs available include: Note: This data sheet summarizes the features - Analog inputs multiplexed with I/O pins of the PIC32MX1XX/2XX 28/36/44-pin - On-chip internal absolute voltage reference Family of devices. It is not intended to be (IVREF) a comprehensive reference source. To complement the information in this data - Comparator voltage reference (CVREF) sheet, refer to Section 19. • Outputs can be Inverted “Comparator” (DS60001110), which is • Selectable interrupt generation available from the Documentation > A block diagram of the comparator module is provided Reference Manual section of the in Figure23-1. Microchip PIC32 web site (www.microchip.com/pic32). The Analog Comparator module contains three comparators that can be configured in a variety of ways. FIGURE 23-1: COMPARATOR BLOCK DIAGRAM C1INB CCH<1:0> C1INC COE C1IND CMP1 C1OUT CREF CPOL CMSTAT<C1OUT> C1INA CM1CON<COUT> C2INB CCH<1:0> To CTMU module (Pulse Generator) C2INC COE C2IND CMP2 C2OUT CREF CPOL CMSTAT<C2OUT> C2INA CM2CON<COUT> CCH<1:0> C3INB C3INC COE C3IND CMP3 C3OUT CREF C3INA CPOL CMSTAT<C3OUT> CM3CON<COUT> CVREF(1) Note 1: Internally connected. See Section24.0 “Comparator Voltage Reference (CVREF)” for more information. IVREF(2) 2: Internal precision voltage reference (1.2V).  2011-2016 Microchip Technology Inc. DS60001168J-page 219

D 23.1 Comparator Control Registers P S 600 TABLE 23-1: COMPARATOR REGISTER MAP IC 0 1168J-page 22 Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 0 1 31:16 — — — — — — — — — — — — — — — — 0000 A000 CM1CON X 15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3 31:16 — — — — — — — — — — — — — — — — 0000 X A010 CM2CON 15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3 / 31:16 — — — — — — — — — — — — — — — — 0000 2 A020 CM3CON 15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3 X 31:16 — — — — — — — — — — — — — — — — 0000 X A060 CMSTAT 15:0 — — SIDL — — — — — — — — — — C3OUT C2OUT C1OUT 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for 8 more information. / 3 6 / 4 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 23-1: CMXCON: COMPARATOR CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R-0 15:8 ON(1) COE CPOL(2) — — — — COUT R/W-1 R/W-1 U-0 R/W-0 U-0 U-0 R/W-1 R/W-1 7:0 EVPOL<1:0> — CREF — — CCH<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Comparator ON bit(1) 1 = Module is enabled. Setting this bit does not affect the other bits in this register 0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register bit 14 COE: Comparator Output Enable bit 1 = Comparator output is driven on the output CxOUT pin 0 = Comparator output is not driven on the output CxOUT pin bit 13 CPOL: Comparator Output Inversion bit(2) 1 = Output is inverted 0 = Output is not inverted bit 12-9 Unimplemented: Read as ‘0’ bit 8 COUT: Comparator Output bit 1 = Output of the Comparator is a ‘1’ 0 = Output of the Comparator is a ‘0’ bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits 11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = Comparator interrupt is generated on a high-to-low transition of the comparator output 01 = Comparator interrupt is generated on a low-to-high transition of the comparator output 00 = Comparator interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Positive Input Configure bit 1 = Comparator non-inverting input is connected to the internal CVREF 0 = Comparator non-inverting input is connected to the CXINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator 11 = Comparator inverting input is connected to the IVREF 10 = Comparator inverting input is connected to the CxIND pin 01 = Comparator inverting input is connected to the CxINC pin 00 = Comparator inverting input is connected to the CxINB pin Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. 2: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.  2011-2016 Microchip Technology Inc. DS60001168J-page 221

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 23-2: CMSTAT: COMPARATOR STATUS REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 15:8 — — SIDL — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 7:0 — — — — — C3OUT C2OUT C1OUT Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Control bit 1 = All Comparator modules are disabled when the device enters Idle mode 0 = All Comparator modules continue to operate when the device enters Idle mode bit 12-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator Output bit 1 = Output of Comparator 3 is a ‘1’ 0 = Output of Comparator 3 is a ‘0’ bit 1 C2OUT: Comparator Output bit 1 = Output of Comparator 2 is a ‘1’ 0 = Output of Comparator 2 is a ‘0’ bit 0 C1OUT: Comparator Output bit 1 = Output of Comparator 1 is a ‘1’ 0 = Output of Comparator 1 is a ‘0’ DS60001168J-page 222  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 24.0 COMPARATOR VOLTAGE The resistor ladder is segmented to provide two ranges REFERENCE (CVREF) of voltage reference values and has a power-down function to conserve power when the reference is not Note: This data sheet summarizes the features being used. The module’s supply reference can be pro- of the PIC32MX1XX/2XX 28/36/44-pin vided from either device VDD/VSS or an external Family of devices. It is not intended to be voltage reference. The CVREF output is available for a comprehensive reference source. To the comparators and typically available for pin output. complement the information in this data The comparator voltage reference has the following sheet, refer to Section 20. “Comparator features: Voltage Reference (CVREF)” • High and low range selection (DS60001109), which is available from the • Sixteen output levels available for each range Documentation > Reference Manual section of the Microchip PIC32 web site • Internally connected to comparators to conserve (www.microchip.com/pic32). device pins • Output can be connected to a pin The CVREF module is a 16-tap, resistor ladder network A block diagram of the module is shown in Figure24-1. that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ CVRSRC AVDD CVRSS = 0 8R CVR<3:0> CVREF R CVREN R R R X U M 16 Steps 1 CVREFOUT o- 6-t CVRCON<CVROE> 1 R R R CVRR 8R CVRSS = 1 VREF- AVSS CVRSS = 0  2011-2016 Microchip Technology Inc. DS60001168J-page 223

D 24.1 Comparator Voltage Reference Control Register P S 60 I 00 TABLE 24-1: COMPARATOR VOLTAGE REFERENCE REGISTER MAP C 1 1 3 68J-page 224 Virtual Address(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 2MX1 9800 CVRCON 31:16 — — — — — — — — — — — — — — — — 0000 X 15:0 ON — — — — — — — — CVROE CVRR CVRSS CVR<3:0> 0000 X Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for / 2 more information. X X 2 8 / 3 6 / 4 4 - P I N F A M  2 0 I 1 L 1 -20 Y 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 15:8 ON(1) — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 — CVROE CVRR CVRSS CVR<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Comparator Voltage Reference On bit(1) 1=Module is enabled Setting this bit does not affect other bits in the register. 0=Module is disabled and does not consume current. Clearing this bit does not affect the other bits in the register. bit 14-7 Unimplemented: Read as ‘0’ bit 6 CVROE: CVREFOUT Enable bit 1=Voltage level is output on CVREFOUT pin 0=Voltage level is disconnected from CVREFOUT pin bit 5 CVRR: CVREF Range Selection bit 1=0 to 0.67 CVRSRC, with CVRSRC/24 step size 0=0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size bit 4 CVRSS: CVREF Source Selection bit 1=Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-) 0=Comparator voltage reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0>: CVREF Value Selection 0  CVR<3:0>  15 bits When CVRR=1: CVREF=(CVR<3:0>/24)  (CVRSRC) When CVRR=0: CVREF=1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC) Note1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.  2011-2016 Microchip Technology Inc. DS60001168J-page 225

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 226  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 25.0 CHARGE TIME The CTMU module includes the following key features: MEASUREMENT UNIT (CTMU) • Up to 13 channels available for capacitive or time measurement input Note: This data sheet summarizes the features • On-chip precision current source of the PIC32MX1XX/2XX 28/36/44-pin • 16-edge input trigger sources Family of devices. It is not intended to be • Selection of edge or level-sensitive inputs a comprehensive reference source. To complement the information in this data • Polarity control for each edge source sheet, refer to Section 37. “Charge Time • Control of edge sequence Measurement Unit (CTMU)” • Control of response to edges (DS60001167), which is available from the • High precision time measurement Documentation > Reference Manual • Time delay of external or internal signal asynchro- section of the Microchip PIC32 web site nous to system clock (www.microchip.com/pic32). • Integrated temperature sensing diode The Charge Time Measurement Unit (CTMU) is a flex- • Control of current source during auto-sampling ible analog module that has a configurable current • Four current source ranges source with a digital configuration circuit built around it. • Time measurement resolution of one nanosecond The CTMU can be used for differential time measure- ment between pulse sources and can be used for gen- A block diagram of the CTMU is shown in Figure25-1. erating an asynchronous pulse. By working with other on-chip analog modules, the CTMU can be used for high resolution time measurement, measure capaci- tance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. FIGURE 25-1: CTMU BLOCK DIAGRAM CTMUCON1 or CTMUCON2 CTMUCON ITRIM<5:0> IRNG<1:0> Current Source CTED1 • Edge • Control CTMU ADC • Logic EEDDGG12SSTTAATT TGEN Control Trigger CTED13 Current Logic Control Timer1 OC1 IC1-IC3 CTMUP Pulse CTPLS Generator CMP1-CMP3 CTMUI PBCLK (To ADC S&H capacitor) CTMUT (To ADC) C2INB Temperature Sensor CDelay Comparator 2 External capacitor for pulse generation Current Control Selection TGEN EDG1STAT, EDG2STAT CTMUT 0 EDG1STAT = EDG2STAT CTMUI 0 EDG1STAT  EDG2STAT CTMUP 1 EDG1STAT  EDG2STAT No Connect 1 EDG1STAT = EDG2STAT  2011-2016 Microchip Technology Inc. DS60001168J-page 227

D 25.1 CTMU Control Registers P S 6 I 0 C 0 0 TABLE 25-1: CTMU REGISTER MAP 1 3 1 68 ss Bits 2 J-page 228 Virtual Addre(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets MX1X A200CTMUCON31:16EDG1MODEDG1POL EDG1SEL<3:0> EDG2STATEDG1STATEDG2MODEDG2POL EDG2SEL<3:0> — — 0000 X 15:0 ON — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG ITRIM<5:0> IRNG<1:0> 0000 / Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for X more information. X 2 8 / 3 6 / 4 4 - P I N F A M I L Y  2 0 1 1 -2 0 1 6 M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 23:16 EDG2MOD EDG2POL EDG2SEL<3:0> — — R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15:8 ON — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN(2) CTTRIG R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 ITRIM<5:0> IRNG<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 EDG1MOD: Edge1 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 30 EDG1POL: Edge 1 Polarity Select bit 1 = Edge1 programmed for a positive edge response 0 = Edge1 programmed for a negative edge response bit 29-26 EDG1SEL<3:0>: Edge 1 Source Select bits 1111 = C3OUT pin is selected 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = IC3 Capture Event is selected 1011 = IC2 Capture Event is selected 1010 = IC1 Capture Event is selected 1001 = CTED8 pin is selected 1000 = CTED7 pin is selected 0111 = CTED6 pin is selected 0110 = CTED5 pin is selected 0101 = CTED4 pin is selected 0100 = CTED3 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 25 EDG2STAT: Edge2 Status bit Indicates the status of Edge2 and can be written to control edge source 1 = Edge2 has occurred 0 = Edge2 has not occurred Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select C2OUT. 2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. 3: Refer to the CTMU Current Source Specifications (Table30-41) in Section30.0 “Electrical Characteristics” for current values. 4: This bit setting is not available for the CTMU temperature diode.  2011-2016 Microchip Technology Inc. DS60001168J-page 229

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 24 EDG1STAT: Edge1 Status bit Indicates the status of Edge1 and can be written to control edge source 1 = Edge1 has occurred 0 = Edge1 has not occurred bit 23 EDG2MOD: Edge2 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 22 EDG2POL: Edge 2 Polarity Select bit 1 = Edge2 programmed for a positive edge response 0 = Edge2 programmed for a negative edge response bit 21-18 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = C3OUT pin is selected 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = PBCLK clock is selected 1011 = IC3 Capture Event is selected 1010 = IC2 Capture Event is selected 1001 = IC1 Capture Event is selected 1000 = CTED13 pin is selected 0111 = CTED12 pin is selected 0110 = CTED11 pin is selected 0101 = CTED10 pin is selected 0100 = CTED9 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 17-16 Unimplemented: Read as ‘0’ bit 15 ON: ON Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation when the device enters Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select C2OUT. 2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. 3: Refer to the CTMU Current Source Specifications (Table30-41) in Section30.0 “Electrical Characteristics” for current values. 4: This bit setting is not available for the CTMU temperature diode. DS60001168J-page 230  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge1 must occur before Edge2 can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit(2) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 • • • 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current • • • 100010 100001 = Maximum negative change from nominal current bit 1-0 IRNG<1:0>: Current Range Select bits(3) 11 = 100 times base current 10 = 10 times base current 01 = Base current level 00 = 1000 times base current(4) Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to ‘1110’ to select C2OUT. 2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. 3: Refer to the CTMU Current Source Specifications (Table30-41) in Section30.0 “Electrical Characteristics” for current values. 4: This bit setting is not available for the CTMU temperature diode.  2011-2016 Microchip Technology Inc. DS60001168J-page 231

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 232  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 26.0 POWER-SAVING FEATURES • LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but Note: This data sheet summarizes the features can optionally be individually disabled. This is the of the PIC32MX1XX/2XX 28/36/44-pin lowest power mode for the device with a clock Family of devices. It is not intended to be running. a comprehensive reference source. To • Sleep mode: the CPU, the system clock source complement the information in this data and any peripherals that operate from the system sheet, refer to Section 10. “Power- clock source are Halted. Some peripherals can Saving Features” (DS60001130), which operate in Sleep using specific clock sources. is available from the Documentation > This is the lowest power mode for the device. Reference Manual section of the Microchip PIC32 web site 26.3 Power-Saving Operation (www.microchip.com/pic32). Peripherals and the CPU can be Halted or disabled to This section describes power-saving features for the further reduce power consumption. PIC32MX1XX/2XX 28/36/44-pin Family. The PIC32 devices offer a total of nine methods and modes, 26.3.1 SLEEP MODE organized into two categories, that allow the user to Sleep mode has the lowest power consumption of the balance power consumption with device performance. In device power-saving operating modes. The CPU and all of the methods and modes described in this section, most peripherals are Halted. Select peripherals can power-saving is controlled by software. continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual 26.1 Power Saving with CPU Running peripheral module sections for descriptions of behavior in Sleep. When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, Sleep mode includes the following characteristics: lowering the PBCLK and by individually disabling • The CPU is halted modules. These methods are grouped into the • The system clock source is typically shutdown. following categories: See Section26.3.3 “Peripheral Bus Scaling • FRC Run mode: the CPU is clocked from the FRC Method” for specific information. clock source with or without postscalers • There can be a wake-up delay based on the • LPRC Run mode: the CPU is clocked from the oscillator selection LPRC clock source • The Fail-Safe Clock Monitor (FSCM) does not • SOSC Run mode: the CPU is clocked from the operate during Sleep mode SOSC clock source • The BOR circuit remains operative during Sleep In addition, the Peripheral Bus Scaling mode is available mode where peripherals are clocked at the programmable • The WDT, if enabled, is not automatically cleared fraction of the CPU clock (SYSCLK). prior to entering Sleep mode • Some peripherals can continue to operate at 26.2 CPU Halted Methods limited functionality in Sleep mode. These peripherals include I/O pins that detect a change The device supports two power-saving modes, Sleep in the input signal, WDT, ADC, UART and and Idle, both of which Halt the clock to the CPU. These peripherals that use an external clock input or the modes operate with all clock sources, as follows: internal LPRC oscillator (e.g., RTCC, Timer1 and • POSC Idle mode: the system clock is derived from Input Capture). the POSC. The system clock source continues to • I/O pins continue to sink or source current in the operate. Peripherals continue to operate, but can same manner as they do when the device is not in optionally be individually disabled. Sleep • FRC Idle mode: the system clock is derived from • The USB module can override the disabling of the the FRC with or without postscalers. Peripherals Posc or FRC. Refer to the USB section for continue to operate, but can optionally be specific details. individually disabled. • Modules can be individually disabled by software • SOSC Idle mode: the system clock is derived from prior to entering Sleep in order to further reduce the SOSC. Peripherals continue to operate, but consumption can optionally be individually disabled.  2011-2016 Microchip Technology Inc. DS60001168J-page 233

PIC32MX1XX/2XX 28/36/44-PIN FAMILY The processor will exit, or ‘wake-up’, from Sleep on one The device enters Idle mode when the SLPEN of the following events: (OSCCON<4>) bit is clear and a WAIT instruction is executed. • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be The processor will wake or exit from Idle mode on the greater than the current CPU priority. following events: • On any form of device Reset • On any interrupt event for which the interrupt • On a WDT time-out source is enabled. The priority of the interrupt event must be greater than the current priority of If the interrupt priority is lower than or equal to the the CPU. If the priority of the interrupt event is current priority, the CPU will remain Halted, but the lower than or equal to current priority of the CPU, PBCLK will start running and the device will enter into the CPU will remain Halted and the device will Idle mode. remain in Idle mode. 26.3.2 IDLE MODE • On any form of device Reset In Idle mode, the CPU is Halted but the System Clock • On a WDT time-out interrupt (SYSCLK) source is still enabled. This allows peripher- 26.3.3 PERIPHERAL BUS SCALING als to continue operation when the CPU is Halted. METHOD Peripherals can be individually configured to Halt when entering Idle by setting their respective SIDL bit. Most of the peripherals on the device are clocked using Latency, when exiting Idle mode, is very low due to the the PBCLK. The Peripheral Bus can be scaled relative to CPU oscillator source remaining active. the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by Note1: Changing the PBCLK divider ratio PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to requires recalculation of peripheral tim- PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals ing. For example, assume the UART is using PBCLK are affected when the divisor is changed. configured for 9600 baud with a PB clock Peripherals such as the USB, Interrupt Controller, DMA, ratio of 1:1 and a POSC of 8 MHz. When and the bus matrix are clocked directly from SYSCLK. the PB clock divisor of 1:2 is used, the As a result, they are not affected by PBCLK divisor input frequency to the baud clock is cut in changes. half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric Changing the PBCLK divisor affects: truncation in calculations (such as the • The CPU to peripheral access latency. The CPU baud rate divisor), the actual baud rate has to wait for next PBCLK edge for a read to may be a tiny percentage different than complete. In 1:8 mode, this results in a latency of expected. For this reason, any timing cal- one to seven SYSCLKs. culation required for a peripheral should • The power consumption of the peripherals. Power be performed with the new PB clock fre- consumption is directly proportional to the fre- quency instead of scaling the previous quency at which the peripherals are clocked. The value based on a change in the PB divisor greater the divisor, the lower the power consumed ratio. by the peripherals. 2: Oscillator start-up and PLL lock delays To minimize dynamic power, the PB divisor should be are applied when switching to a clock chosen to run the peripherals at the lowest frequency source that was disabled and that uses a that provides acceptable system performance. When crystal and/or the PLL. For example, selecting a PBCLK divider, peripheral clock require- assume the clock source is switched from ments, such as baud rate accuracy, should be taken POSC to LPRC just prior to entering Sleep into account. For example, the UART peripheral may in order to save power. No oscillator start- not be able to achieve all baud rate values at some up delay would be applied when exiting PBCLK divider depending on the SYSCLK value. Idle. However, when switching back to POSC, the appropriate PLL and/or oscillator start-up/lock delays would be applied. DS60001168J-page 234  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 26.4 Peripheral Module Disable To disable a peripheral, the associated PMDx bit must be set to ‘1’. To enable a peripheral, the associated The Peripheral Module Disable (PMD) registers PMDx bit must be cleared (default). See Table26-1 for provide a method to disable a peripheral module by more information. stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate Note: Disabling a peripheral module while it’s PMD control bit, the peripheral is in a minimum power ON bit is set, may result in undefined consumption state. The control and status registers behavior. The ON bit for the associated associated with the peripheral are also disabled, so peripheral module must be cleared prior to writes to those registers do not have effect and read disable a module via the PMDx bits. values are invalid. TABLE 26-1: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS Peripheral(1) PMDx bit Name(1) Register Name and Bit Location ADC1 AD1MD PMD1<0> CTMU CTMUMD PMD1<8> Comparator Voltage Reference CVRMD PMD1<12> Comparator 1 CMP1MD PMD2<0> Comparator 2 CMP2MD PMD2<1> Comparator 3 CMP3MD PMD2<2> Input Capture 1 IC1MD PMD3<0> Input Capture 2 IC2MD PMD3<1> Input Capture 3 IC3MD PMD3<2> Input Capture 4 IC4MD PMD3<3> Input Capture 5 IC5MD PMD3<4> Output Compare 1 OC1MD PMD3<16> Output Compare 2 OC2MD PMD3<17> Output Compare 3 OC3MD PMD3<18> Output Compare 4 OC4MD PMD3<19> Output Compare 5 OC5MD PMD3<20> Timer1 T1MD PMD4<0> Timer2 T2MD PMD4<1> Timer3 T3MD PMD4<2> Timer4 T4MD PMD4<3> Timer5 T5MD PMD4<4> UART1 U1MD PMD5<0> UART2 U2MD PMD5<1> SPI1 SPI1MD PMD5<8> SPI2 SPI2MD PMD5<9> I2C1 I2C1MD PMD5<16> I2C2 I2C2MD PMD5<17> USB(2) USBMD PMD5<24> RTCC RTCCMD PMD6<0> Reference Clock Output REFOMD PMD6<1> PMP PMPMD PMD6<16> Note 1: Not all modules and associated PMDx bits are available on all devices. See TABLE 1:“PIC32MX1XX 28/36/44-Pin General Purpose Family Features” and TABLE 2:“PIC32MX2XX 28/36/44-pin USB Family Features” for the lists of available peripherals. 2: The module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit.  2011-2016 Microchip Technology Inc. DS60001168J-page 235

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 26.4.1 CONTROLLING CONFIGURATION CHANGES Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to enabled or disabled peripherals: • Control register lock sequence • Configuration bit select lock 26.4.1.1 Control Register Lock Under normal operation, writes to the PMDx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the Configuration bit, PMDLOCK (CFGCON<12>). Setting PMDLOCK prevents writes to the control registers; clearing PMDLOCK allows writes. To set or clear PMDLOCK, an unlock sequence must be executed. Refer to Section 6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details. 26.4.1.2 Configuration Bit Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the PMDx registers. The Configuration bit, PMDL1WAY (DEVCFG3<28>), blocks the PMDLOCK bit from being cleared after it has been set once. If PMDLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable PMD functionality is to perform a device Reset. DS60001168J-page 236  2011-2016 Microchip Technology Inc.

 TABLE 26-2: PERIPHERAL MODULE DISABLE REGISTER MAP 2 01 ss Bits 1-2016 Micro Virtual Addre(BF80_#) Register(1)Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets c h 31:16 — — — — — — — — — — — — — — — — 0000 ip F240 PMD1 T 15:0 — — — CVRMD — — — CTMUMD — — — — — — — AD1MD 0000 ec 31:16 — — — — — — — — — — — — — — — — 0000 h F250 PMD2 P n 15:0 — — — — — — — — — — — — — CMP3MD CMP2MD CMP1MD 0000 o logy In F260 PMD3 3115:1:06 —— —— —— —— —— —— —— —— —— —— —— OICC55MMDD OICC44MMDD OICC33MMDD OICC22MMDD OICC11MMDD 00000000 IC3 c 31:16 — — — — — — — — — — — — — — — — 0000 . F270 PMD4 2 15:0 — — — — — — — — — — — T5MD T4MD T3MD T2MD T1MD 0000 31:16 — — — — — — — USB1MD — — — — — — I2C1MD I2C1MD 0000 M F280 PMD5 15:0 — — — — — — SPI2MD SPI1MD — — — — — — U2MD U1MD 0000 X 31:16 — — — — — — — — — — — — — — — PMPMD 0000 F290 PMD6 1 15:0 — — — — — — — — — — — — — — REFOMD RTCCMD 0000 X Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section11.2 “CLR, SET and INV Registers” for X more information. / 2 X X 2 8 / 3 6 / 4 4 - P I N D S 60 F 0 0 A 1 1 68 M J -pa I g L e 2 Y 3 7

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 238  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 27.0 SPECIAL FEATURES 27.1 Configuration Bits The Configuration bits can be programmed using the Note: This data sheet summarizes the features following registers to select various device of the PIC32MX1XX/2XX 28/36/44-pin configurations. Family of devices. However, it is not intended to be a comprehensive • DEVCFG0: Device Configuration Word 0 reference source. To complement the • DEVCFG1: Device Configuration Word 1 information in this data sheet, refer to • DEVCFG2: Device Configuration Word 2 Section 32. “Configuration” • DEVCFG3: Device Configuration Word 3 (DS60001124) and Section 33. “Programming and Diagnostics” • CFGCON: Configuration Control Register (DS60001129), which are available from In addition, the DEVID register (Register27-6) the Documentation > Reference Manual provides device and revision information. section of the Microchip PIC32 web site (www.microchip.com/pic32). PIC32MX1XX/2XX 28/36/44-pin Family devices include the following features intended to maximize application flexibility, reliability and minimize cost through elimination of external components. • Flexible device configuration • Joint Test Action Group (JTAG) interface • In-Circuit Serial Programming™ (ICSP™)  2011-2016 Microchip Technology Inc. DS60001168J-page 239

D 27.2 Configuration Registers P S 600 TABLE 27-1: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY IC 0 1168J-page 24 Virtual Address(BFC0_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/B8its 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 32MX 0 1 31:16FVBUSONIOFUSBIDIO IOL1WAY PMDL1WAY — — — — — — — — — — — — xxxx 0BF0DEVCFG3 X 15:0 USERID<15:0> xxxx 31:16 — — — — — — — — — — — — — FPLLODIV<2:0> xxxx X 0BF4DEVCFG2 15:0 UPLLEN(1) — — — — UPLLIDIV<2:0>(1) — FPLLMUL<2:0> — FPLLIDIV<2:0> xxxx / 31:16 — — — — — — FWDTWINSZ<1:0> FWDTEN WINDIS — WDTPS<4:0> xxxx 2 0BF8DEVCFG1 15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0> IESO — FSOSCEN — — FNOSC<2:0> xxxx X 31:16 — — — CP — — — BWP — — — — — PWP<8:6>(2) xxxx X 0BFCDEVCFG0 15:0 PWP<5:0> — — — — — ICESEL<1:0> JTAGEN DEBUG<1:0> xxxx Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 Note 1: This bit is only available on PIC32MX2XX devices. 8 2: PWP<8:7> are only available on devices with 256 KB of Flash. / 3 6 TABLE 27-2: DEVICE ID, REVISION, AND CONFIGURATION SUMMARY / 4 Virtual Address(BF80_#) RegisterName Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 Bits 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 (1)All Resets 4-PIN 31:16 VER<3:0> DEVID<27:16> xxxx(1) F F220 DEVID 15:0 DEVID<15:0> xxxx(1) A 31:16 — — — — — — — — — — — — — — — — 0000 F200 CFGCON M  15:0 — — IOLOCK PMDLOCK — — — — — — — — JTAGEN — — TDOEN 000B 201 F230 SYSKEY(3) 31:16 SYSKEY<31:0> 0000 IL 1 15:0 0000 -20 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Y 1 6 Note 1: Reset values are dependent on the device variant. M ic ro c h ip T e c h n o lo g y In c .

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P 31:24 — — — CP — — — BWP r-1 r-1 r-1 r-1 r-1 R/P R/P R/P 23:16 — — — — — PWP<8:6>(3) R/P R/P R/P R/P R/P R/P r-1 r-1 15:8 PWP<5:0> — — r-1 r-1 r-1 R/P R/P R/P R/P R/P 7:0 — — — ICESEL<1:0>(2) JTAGEN(1) DEBUG<1:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 Reserved: Write ‘0’ bit 30-29 Reserved: Write ‘1’ bit 28 CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection is disabled 0 = Protection is enabled bit 27-25 Reserved: Write ‘1’ bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-19 Reserved: Write ‘1’ Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register. 2: The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for availability. 3: The PWP<8:7> bits are only available on devices with 256 KB Flash.  2011-2016 Microchip Technology Inc. DS60001168J-page 241

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 18-10 PWP<8:0>: Program Flash Write-Protect bits(3) Prevents selected program Flash memory pages from being modified during code execution. 111111111 = Disabled 111111110 = Memory below 0x0400 address is write-protected 111111101 = Memory below 0x0800 address is write-protected 111111100 = Memory below 0x0C00 address is write-protected 111111011 = Memory below 0x1000 (4K) address is write-protected 111111010 = Memory below 0x1400 address is write-protected 111111001 = Memory below 0x1800 address is write-protected 111111000 = Memory below 0x1C00 address is write-protected 111110111 = Memory below 0x2000 (8K) address is write-protected 111110110 = Memory below 0x2400 address is write-protected 111110101 = Memory below 0x2800 address is write-protected 111110100 = Memory below 0x2C00 address is write-protected 111110011 = Memory below 0x3000 address is write-protected 111110010 = Memory below 0x3400 address is write-protected 111110001 = Memory below 0x3800 address is write-protected 111110000 = Memory below 0x3C00 address is write-protected 111101111 = Memory below 0x4000 (16K) address is write-protected • • • 110111111 = Memory below 0x10000 (64K) address is write-protected • • • 101111111 = Memory below 0x20000 (128K) address is write-protected • • • 011111111 = Memory below 0x40000 (256K) address is write-protected • • • 000000000 = All possible memory is write-protected bit 9-5 Reserved: Write ‘1’ bit 4-3 ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits(2) 11 = PGEC1/PGED1 pair is used 10 = PGEC2/PGED2 pair is used 01 = PGEC3/PGED3 pair is used 00 = PGEC4/PGED4 pair is used(2) bit 2 JTAGEN: JTAG Enable bit(1) 1 = JTAG is enabled 0 = JTAG is disabled bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled) 1x = Debugger is disabled 0x = Debugger is enabled Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register. 2: The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for availability. 3: The PWP<8:7> bits are only available on devices with 256 KB Flash. DS60001168J-page 242  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 R/P R/P 31:24 — — — — — — FWDTWINSZ<1:0> R/P R/P r-1 R/P R/P R/P R/P R/P 23:16 FWDTEN WINDIS — WDTPS<4:0> R/P R/P R/P R/P r-1 R/P R/P R/P 15:8 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0> R/P r-1 R/P r-1 r-1 R/P R/P R/P 7:0 IESO — FSOSCEN — — FNOSC<2:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-26 Reserved: Write ‘1’ bit 25-24 FWDTWINSZ<1:0>: Watchdog Timer Window Size bits 11 = Window size is 25% 10 = Window size is 37.5% 01 = Window size is 50% 00 = Window size is 75% bit 23 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled and cannot be disabled by software 0 = Watchdog Timer is not enabled; it can be enabled in software bit 22 WINDIS: Watchdog Timer Window Enable bit 1 = Watchdog Timer is in non-Window mode 0 = Watchdog Timer is in Window mode bit 21 Reserved: Write ‘1’ bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = 10100 Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source.  2011-2016 Microchip Technology Inc. DS60001168J-page 243

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write ‘1’ bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output disabled 0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0>=11 or 00) bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = External Clock mode is selected bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) bit 6 Reserved: Write ‘1’ bit 5 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 4-3 Reserved: Write ‘1’ bit 2-0 FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. DS60001168J-page 244  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 31:24 — — — — — — — — r-1 r-1 r-1 r-1 r-1 R/P R/P R/P 23:16 — — — — — FPLLODIV<2:0> R/P r-1 r-1 r-1 r-1 R/P R/P R/P 15:8 UPLLEN(1) — — — — UPLLIDIV<2:0>(1) r-1 R/P-1 R/P R/P-1 r-1 R/P R/P R/P 7:0 — FPLLMUL<2:0> — FPLLIDIV<2:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-19 Reserved: Write ‘1’ bit 18-16 FPLLODIV<2:0>: Default PLL Output Divisor bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 15 UPLLEN: USB PLL Enable bit(1) 1 = Disable and bypass USB PLL 0 = Enable USB PLL bit 14-11 Reserved: Write ‘1’ bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits(1) 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 Reserved: Write ‘1’ bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 Reserved: Write ‘1’ Note 1: This bit is only available on PIC32MX2XX devices.  2011-2016 Microchip Technology Inc. DS60001168J-page 245

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Note 1: This bit is only available on PIC32MX2XX devices. DS60001168J-page 246  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-4: DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R/P R/P R/P R/P r-1 r-1 r-1 r-1 31:24 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY — — — — r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 23:16 — — — — — — — — R/P R/P R/P R/P R/P R/P R/P R/P 15:8 USERID<15:8> R/P R/P R/P R/P R/P R/P R/P R/P 7:0 USERID<7:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 FVBUSONIO: USB VBUSON Selection bit 1 = VBUSON pin is controlled by the USB module 0 = VBUSON pin is controlled by the port function bit 30 FUSBIDIO: USB USBID Selection bit 1 = USBID pin is controlled by the USB module 0 = USBID pin is controlled by the port function bit 29 IOL1WAY: Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 28 PMDl1WAY: Peripheral Module Disable Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 27-16 Reserved: Write ‘1’ bit 15-0 USERID<15:0>: User ID bits This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG.  2011-2016 Microchip Technology Inc. DS60001168J-page 247

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-5: CFGCON: CONFIGURATION CONTROL REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 23:16 — — — — — — — — U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 15:8 — — IOLOCK(1) PMDLOCK(1) — — — — U-0 U-0 U-0 U-0 R/W-1 U-0 U-1 R/W-1 7:0 — — — — JTAGEN — — TDOEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as ‘0’ bit 13 IOLOCK: Peripheral Pin Select Lock bit(1) 1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed. 0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed. bit 12 PMDLOCK: Peripheral Module Disable bit(1) 1 = Peripheral module is locked. Writes to PMD registers is not allowed. 0 = Peripheral module is not locked. Writes to PMD registers is allowed. bit 11-4 Unimplemented: Read as ‘0’ bit 3 JTAGEN: JTAG Port Enable bit 1 = Enable the JTAG port 0 = Disable the JTAG port bit 2-1 Unimplemented: Read as ‘1’ bit 0 TDOEN: TDO Enable for 2-Wire JTAG bit 1 = 2-wire JTAG protocol uses TDO 0 = 2-wire JTAG protocol does not use TDO Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details. DS60001168J-page 248  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY REGISTER 27-6: DEVID: DEVICE AND REVISION ID REGISTER Bit Bit Bit Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 R R R R R R R R 31:24 VER<3:0>(1) DEVID<27:24>(1) R R R R R R R R 23:16 DEVID<23:16>(1) R R R R R R R R 15:8 DEVID<15:8>(1) R R R R R R R R 7:0 DEVID<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID bits(1) Note 1: See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID values.  2011-2016 Microchip Technology Inc. DS60001168J-page 249

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 27.3 On-Chip Voltage Regulator 27.4 Programming and Diagnostics All PIC32MX1XX/2XX 28/36/44-pin Family devices’ PIC32MX1XX/2XX 28/36/44-pin Family devices pro- core and digital logic are designed to operate at a nom- vide a complete range of programming and diagnostic inal 1.8V. To simplify system designs, most devices in features that can increase the flexibility of any applica- the PIC32MX1XX/2XX 28/36/44-pin Family family tion using them. These features allow system design- incorporate an on-chip regulator providing the required ers to include: core logic voltage from VDD. • Simplified field programmability using two-wire A low-ESR capacitor (such as tantalum) must be In-Circuit Serial Programming™ (ICSP™) connected to the VCAP pin (see Figure27-1). This interfaces helps to maintain the stability of the regulator. The • Debugging using ICSP recommended value for the filter capacitor is provided • Programming and debugging capabilities using in Section30.1 “DC Characteristics”. the EJTAG extension of JTAG Note: It is important that the low-ESR capacitor • JTAG boundary scan testing for device and board is placed as close as possible to the VCAP diagnostics pin. PIC32 devices incorporate two programming and diag- nostic modules, and a trace controller, that provide a 27.3.1 ON-CHIP REGULATOR AND POR range of functions to the application developer. It takes a fixed delay for the on-chip regulator to gener- Figure27-2 illustrates a block diagram of the ate an output. During this time, designated as TPU, programming, debugging, and trace ports. code execution is disabled. TPU is applied every time the device resumes operation after any power-down, FIGURE 27-2: BLOCK DIAGRAM OF including Sleep mode. PROGRAMMING, 27.3.2 ON-CHIP REGULATOR AND BOR DEBUGGING AND TRACE PORTS PIC32MX1XX/2XX 28/36/44-pin Family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a PGEC1 regulated level, the regulator Reset circuitry will PGED1 generate a Brown-out Reset. This event is captured by ICSP™ the BOR flag bit (RCON<1>). The brown-out voltage Controller levels are specific in Section30.1 “DC PGEC4 Characteristics”. PGED4 Core FIGURE 27-1: CONNECTIONS FOR THE ICESEL ON-CHIP REGULATOR TDI 3.3V(1) TDO JTAG PIC32 Controller TCK VDD TMS VCAP JTAGEN DEBUG<1:0> CEFC(2,3) (10F typ) VSS Note 1: These are typical operating voltages. Refer to Section30.1 “DC Characteristics” for the full operating ranges of VDD. 2: It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. 3: The typical voltage on the VCAP pin is 1.8V. DS60001168J-page 250  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 28.0 INSTRUCTION SET The PIC32MX1XX/2XX family instruction set complies with the MIPS32® Release 2 instruction set architecture. The PIC32 device family does not support the following features: • Core extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.imgtec.com for more information.  2011-2016 Microchip Technology Inc. DS60001168J-page 251

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 252  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 29.0 DEVELOPMENT SUPPORT 29.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and hardware development tool that runs on Windows®, • Integrated Development Environment Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2011-2016 Microchip Technology Inc. DS60001168J-page 253

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 29.2 MPLAB XC Compilers 29.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 29.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 29.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS60001168J-page 254  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 29.6 MPLAB X SIM Software Simulator 29.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 29.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 29.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 29.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2011-2016 Microchip Technology Inc. DS60001168J-page 255

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 29.11 Demonstration/Development 29.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS60001168J-page 256  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX1XX/2XX 28/36/44-pin Family electrical characteristics for devices that operate at 40MHz. Refer to Section31.0 “50 MHz Electrical Characteristics” for additional specifications for operations at higher frequency. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX1XX/2XX 28/36/44-pin Family devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings (See Note 1) Ambient temperature under bias.............................................................................................................-40°C to +105°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3).........................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD  2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on D+ or D- pin with respect to VUSB3V3..................................................................... -0.3V to (VUSB3V3 + 0.3V) Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s).......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................15 mA Maximum output current sourced by any I/O pin....................................................................................................15 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table30-2). 3: See the “Pin Diagrams” section for the 5V tolerant pins.  2011-2016 Microchip Technology Inc. DS60001168J-page 257

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 30.1 DC Characteristics TABLE 30-1: OPERATING MIPS VS. VOLTAGE Max. Frequency VDD Range Temp. Range Characteristic (in Volts)(1) (in °C) PIC32MX1XX/2XX 28/36/44-pin Family DC5 2.3-3.6V -40°C to +85°C 40 MHz DC5b 2.3-3.6V -40°C to +105°C 40 MHz Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table30-11 for BOR values. TABLE 30-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max. Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C V-temp Temperature Devices Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +105 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – S IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical Max. Unit Notes Package Thermal Resistance, 28-pin SSOP JA 71 — °C/W 1 Package Thermal Resistance, 28-pin SOIC JA 50 — °C/W 1 Package Thermal Resistance, 28-pin SPDIP JA 42 — °C/W 1 Package Thermal Resistance, 28-pin QFN JA 35 — °C/W 1 Package Thermal Resistance, 36-pin VTLA JA 31 — °C/W 1 Package Thermal Resistance, 44-pin QFN JA 32 — °C/W 1 Package Thermal Resistance, 44-pin TQFP JA 45 — °C/W 1 Package Thermal Resistance, 44-pin VTLA JA 30 — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS60001168J-page 258  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typ. Max. Units Conditions No. Operating Voltage DC10 VDD Supply Voltage (Note 2) 2.3 — 3.6 V — DC12 VDR RAM Data Retention Voltage 1.75 — — V — (Note 1) DC16 VPOR VDD Start Voltage 1.75 — 2.1 V — to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.00005 — 0.115 V/s — to Ensure Internal Power-on Reset Signal Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table30-11 for BOR values.  2011-2016 Microchip Technology Inc. DS60001168J-page 259

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Parameter Typical(3) Max. Units Conditions No. Operating Current (IDD) (Notes 1, 2, 5) DC20 2 3 mA 4 MHz (Note 4) DC21 7 10.5 mA 10 MHz DC22 10 15 mA 20 MHz (Note 4) DC23 15 23 mA 30 MHz (Note 4) DC24 20 30 mA 40 MHz DC25 100 150 µA +25ºC, 3.3V LPRC (31 kHz) (Note 4) Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. 2: The test conditions for IDD measurements are as follows: • Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) • OSC2/CLKO is configured as an I/O input pin • USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 • CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1 • No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared • WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD • CPU executing while(1) statement from Flash • RTCC and JTAG are disabled 3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. 4: This parameter is characterized, but not tested in manufacturing. 5: IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information. DS60001168J-page 260  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Parameter Typical(2) Max. Units Conditions No. Idle Current (IIDLE): Core Off, Clock on Base Current (Notes 1, 4) DC30a 1 1.5 mA 4 MHz (Note 3) DC31a 2 3 mA 10 MHz DC32a 4 6 mA 20 MHz (Note 3) DC33a 5.5 8 mA 30 MHz (Note 3) DC34a 7.5 11 mA 40 MHz DC37a 100 — µA -40°C LPRC (31 kHz) DC37b 250 — µA +25°C 3.3V (Note 3) DC37c 380 — µA +85°C Note 1: The test conditions for IIDLE current measurements are as follows: • Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) • OSC2/CLKO is configured as an I/O input pin • USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 • CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1 • No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared • WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD • RTCC and JTAG are disabled 2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: This parameter is characterized, but not tested in manufacturing. 4: IIDLE electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information.  2011-2016 Microchip Technology Inc. DS60001168J-page 261

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Typical(2) Max. Units Conditions No. Power-Down Current (IPD) (Notes 1, 5) DC40k 44 70 A -40°C DC40l 44 70 A +25°C Base Power-Down Current DC40n 168 259 A +85°C DC40m 335 536 µA +105ºC Module Differential Current DC41e 5 20 A 3.6V Watchdog Timer Current: IWDT (Note 3) DC42e 23 50 A 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) DC43d 1000 1100 A 3.6V ADC: IADC (Notes 3,4) Note 1: The test conditions for IPD current measurements are as follows: • Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) • OSC2/CLKO is configured as an I/O input pin • USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 • CPU is in Sleep mode, and SRAM data memory Wait states = 1 • No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set • WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD • RTCC and JTAG are disabled 2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: IPD electrical characteristics for devices with 256 KB Flash are only provided as Preliminary information. DS60001168J-page 262  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. VIL Input Low Voltage DI10 I/O Pins with PMP VSS — 0.15VDD V I/O Pins VSS — 0.2VDD V DI18 SDAx, SCLx VSS — 0.3VDD V SMBus disabled (Note 4) DI19 SDAx, SCLx VSS — 0.8 V SMBus enabled (Note 4) VIH Input High Voltage DI20 I/O Pins not 5V-tolerant(5) 0.65VDD — VDD V (Note 4,6) I/O Pins 5V-tolerant with 0.25 VDD + 0.8V — 5.5 V (Note 4,6) PMP(5) I/O Pins 5V-tolerant(5) 0.65VDD — 5.5 V DI28 SDAx, SCLx 0.65VDD — 5.5 V SMBus disabled (Note 4,6) DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled, 2.3V  VPIN  5.5 (Note 4,6) DI30 ICNPU Change Notification — — -50 A VDD = 3.3V, VPIN = VSS Pull-up Current (Note 3,6) DI31 ICNPD Change Notification — — -50 µA VDD = 3.3V, VPIN = VDD Pull-down Current(4) IIL Input Leakage Current (Note 3) DI50 I/O Ports — — +1 A VSS  VPIN  VDD, Pin at high-impedance DI51 Analog Input Pins — — +1 A VSS  VPIN  VDD, Pin at high-impedance DI55 MCLR(2) — — +1 A VSS VPIN VDD DI56 OSC1 — — +1 A VSS VPIN VDD, XT and HS modes Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. 5: See the “Pin Diagrams” section for the 5V-tolerant pins. 6: The VIH specifications are only in relation to externally applied inputs, and not with respect to the user- selectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32 device are guaranteed to be recognized only as a logic “high” internally to the PIC32 device, provided that the external load does not exceed the minimum value of ICNPU. For External “input” logic inputs that require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the PIC32 device.  2011-2016 Microchip Technology Inc. DS60001168J-page 263

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT INJECTION CURRENT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typ.(1) Max. Units Conditions No. DI60a IICL Input Low Injection 0 — -5(2,5) mA This parameter applies to all pins, Current with the exception of the power pins. DI60b IICH Input High Injection 0 — +5(3,4,5) mA This parameter applies to all pins, Current with the exception of all 5V tolerant pins, and the SOSCI, SOSCO, OSC1, D+, and D- pins. DI60c IICT Total Input Injection -20(6) — +20(6) mA Absolute instantaneous sum of all ± Current (sum of all I/O input injection currents from all I/O and Control pins) pins (| IICL + | IICH |)  IICT ) Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: VIL source < (VSS - 0.3). Characterized but not tested. 3: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 4: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any “positive” input injection current. 5: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD + 0.3) or VIL source < (VSS - 0.3)). 6: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the spec- ified limit. If Note 2, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 3, IICH = ((IICH source - (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3)  VSOURCE  (VDD + 0.3), injection current = 0. DS60001168J-page 264  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristic Min. Typ. Max. Units Conditions Output Low Voltage DO10 VOL — — 0.4 V IOL  10 mA, VDD = 3.3V I/O Pins Output High Voltage 1.5(1) — — IOH  -14 mA, VDD = 3.3V I/O Pins 2.0(1) — — IOH  -12 mA, VDD = 3.3V DO20 VOH V 2.4 — — IOH  -10 mA, VDD = 3.3V 3.0(1) — — IOH  -7 mA, VDD = 3.3V Note 1: Parameters are characterized, but not tested. TABLE 30-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min.(1) Typical Max. Units Conditions No. BO10 VBOR BOR Event on VDD transition 2.0 — 2.3 V — high-to-low(2) Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.  2011-2016 Microchip Technology Inc. DS60001168J-page 265

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. Program Flash Memory(3) D130 EP Cell Endurance 20,000 — — E/W — D131 VPR VDD for Read 2.3 — 3.6 V — D132 VPEW VDD for Erase or Write 2.3 — 3.6 V — D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA — Programming TWW Word Write Cycle Time — 411 — s See Note 4 e D136 TRW Row Write Cycle Time — 6675 — ycl See Note 2,4 C D137 TPE Page Erase Cycle Time — 20011 — C See Note 4 R TCE Chip Erase Cycle Time — 80180 — F See Note 4 Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. 2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). 3: Refer to the “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during programming and erase cycles. 4: This parameter depends on FRC accuracy (See Table30-19) and FRC tuning values (See Register8-2). DS60001168J-page 266  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-13: COMPARATOR SPECIFICATIONS Standard Operating Conditions (see Note 4): 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical Max. Units Comments No. D300 VIOFF Input Offset Voltage — ±7.5 ±25 mV AVDD = VDD, AVSS = VSS D301 VICM Input Common Mode Voltage 0 — VDD V AVDD = VDD, AVSS = VSS (Note 2) D302 CMRR Common Mode Rejection Ratio 55 — — dB Max VICM = (VDD - 1)V (Note 2) D303A TRESP Large Signal Response Time — 150 400 ns AVDD = VDD, AVSS = VSS (Note 1,2) D303B TSRESP Small Signal Response Time — 1 — s This is defined as an input step of 50 mV with 15 mV of overdrive (Note 2) D304 ON2OV Comparator Enabled to Output — — 10 s Comparator module is Valid configured before setting the comparator ON bit (Note 2) D305 IVREF Internal Voltage Reference 1.14 1.2 1.26 V — D312 TSET Internal Comparator Voltage — — 10 µs (Note 3) DRC Reference Setting time Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. 2: These parameters are characterized but not tested. 3: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter is characterized, but not tested in manufacturing. 4: The Comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.  2011-2016 Microchip Technology Inc. DS60001168J-page 267

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-14: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typ. Max. Units Comments No. D312 TSET Internal 4-bit DAC — — 10 µs See Note 1 Comparator Reference Settling time D313 DACREFH CVREF Input Voltage AVSS — AVDD V CVRSRC with CVRSS = 0 Reference Range VREF- — VREF+ V CVRSRC with CVRSS = 1 D314 DVREF CVREF Programmable 0 — 0.625 x V 0 to 0.625 DACREFH with Output Range DACREFH DACREFH/24 step size 0.25 x — 0.719 x V 0.25 x DACREFH to 0.719 DACREFH DACREFH DACREFH with DACREFH/32 step size D315 DACRES Resolution — — DACREFH/24 — CVRCON<CVRR> = 1 — — DACREFH/32 — CVRCON<CVRR> = 0 D316 DACACC Absolute Accuracy(2) — — 1/4 LSB DACREFH/24, CVRCON<CVRR> = 1 — — 1/2 LSB DACREFH/32, CVRCON<CVRR> = 0 Note 1: Settling time was measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter is characterized, but is not tested in manufacturing. 2: These parameters are characterized but not tested. TABLE 30-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical Max. Units Comments No. D321 CEFC External Filter Capacitor Value 8 10 — F Capacitor must be low series resistance (1 ohm). Typical voltage on the VCAP pin is 1.8V. DS60001168J-page 268  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 30.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX1XX/2XX 28/36/44-pin Family AC character- istics and timing parameters. FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins VSS 50 pF for OSC2 pin (EC mode) TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C mode Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 30-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 OS31  2011-2016 Microchip Technology Inc. DS60001168J-page 269

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. OS10 FOSC External CLKI Frequency DC — 40 MHz EC (Note 4) (External clocks allowed only 4 — 40 MHz ECPLL (Note 3) in EC and ECPLL modes) OS11 Oscillator Crystal Frequency 3 — 10 MHz XT (Note 4) OS12 4 — 10 MHz XTPLL (Notes 3,4) OS13 10 — 25 MHz HS (Note 5) OS14 10 — 25 MHz HSPLL (Notes 3,4) OS15 32 32.768 100 kHz SOSC (Note 4) OS20 TOSC TOSC = 1/FOSC = TCY (Note 2) — — — — See parameter OS10 for FOSC value OS30 TOSL, External Clock In (OSC1) 0.45 x TOSC — — ns EC (Note 4) TOSH High or Low Time OS31 TOSR, External Clock In (OSC1) — — 0.05 x TOSC ns EC (Note 4) TOSF Rise or Fall Time OS40 TOST Oscillator Start-up Timer Period — 1024 — TOSC (Note 4) (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) OS41 TFSCM Primary Clock Fail Safe — 2 — ms (Note 4) Time-out Period OS42 GM External Oscillator — 12 — mA/V VDD = 3.3V, Transconductance (Primary TA = +25°C Oscillator only) (Note 4) Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not tested. 2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. 3: PLL input requirements: 4 MHZ  FPLLIN  5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. 4: This parameter is characterized, but not tested in manufacturing. DS60001168J-page 270  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typical Max. Units Conditions No. OS50 FPLLI PLL Voltage Controlled 3.92 — 5 MHz ECPLL, HSPLL, XTPLL, Oscillator (VCO) Input FRCPLL modes Frequency Range OS51 FSYS On-Chip VCO System 60 — 120 MHz — Frequency OS52 TLOCK PLL Start-up Time (Lock Time) — — 2 ms — OS53 DCLK CLKO Stability(2) -0.25 — +0.25 % Measured over 100 ms (Period Jitter or Cumulative) period Note 1: These parameters are characterized, but not tested in manufacturing. 2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula: D EffectiveJitter = -----------------------------C----L---K-------------------------- SYSCLK ---------------------------------------------------------- CommunicationClock For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows: D D EffectiveJitter = -----C----L--K--- = -----C----L---K-- 40 1.41 ------ 20 TABLE 30-19: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Characteristics Min. Typical Max. Units Conditions No. Internal FRC Accuracy @ 8.00 MHz(1) F20b FRC -0.9 — +0.9 % — Note 1: Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift. TABLE 30-20: INTERNAL LPRC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Characteristics Min. Typical Max. Units Conditions No. LPRC @ 31.25 kHz(1) F21 LPRC -15 — +15 % — Note 1: Change of LPRC frequency as VDD changes.  2011-2016 Microchip Technology Inc. DS60001168J-page 271

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) DO31 DO32 Note: Refer to Figure30-1 for load conditions. TABLE 30-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(2) Min. Typical(1) Max. Units Conditions No. DO31 TIOR Port Output Rise Time — 5 15 ns VDD < 2.5V — 5 10 ns VDD > 2.5V DO32 TIOF Port Output Fall Time — 5 15 ns VDD < 2.5V — 5 10 ns VDD > 2.5V DI35 TINP INTx Pin High or Low Time 10 — — ns — DI40 TRBP CNx High or Low Time (input) 2 — — TSYSCLK — Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. 2: This parameter is characterized, but not tested in manufacturing. DS60001168J-page 272  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 SY10 (TPU) (TOST) (Note 1) Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). 2: Includes interval voltage regulator stabilization delay.  2011-2016 Microchip Technology Inc. DS60001168J-page 273

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (TSYSDLY) (SY30) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 30-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SY00 TPU Power-up Period — 400 600 s — Internal Voltage Regulator Enabled SY02 TSYSDLY System Delay Period: — s + — — — Time Required to Reload Device 8 SYSCLK Configuration Fuses plus SYSCLK cycles Delay before First instruction is Fetched. SY20 TMCLR MCLR Pulse Width (low) 2 — — s — SY30 TBOR BOR Pulse Width (low) — 1 — s — Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested. DS60001168J-page 274  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure30-1 for load conditions. TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS(1) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(2) Min. Typical Max. Units Conditions No. TA10 TTXH TxCK Synchronous, [(12.5ns or 1 TPB)/N] — — ns Must also meet High Time with prescaler + 25ns parameter TA15 Asynchronous, 10 — — ns — with prescaler TA11 TTXL TxCK Synchronous, [(12.5ns or 1 TPB)/N] — — ns Must also meet Low Time with prescaler + 25ns parameter TA15 Asynchronous, 10 — — ns — with prescaler TA15 TTXP TxCK Synchronous, [(Greater of 25ns or — — ns VDD > 2.7V Input Period with prescaler 2 TPB)/N] + 30ns [(Greater of 25ns or — — ns VDD < 2.7V 2 TPB)/N] + 50ns Asynchronous, 20 — — ns VDD > 2.7V with prescaler (Note 3) 50 — — ns VDD < 2.7V (Note 3) OS60 FT1 SOSC1/T1CK Oscillator 32 — 100 kHz — Input Frequency Range (oscillator enabled by setting the TCS (T1CON<1>) bit) TA20 TCKEXTMRL Delay from External TxCK — — 1 TPB — Clock Edge to Timer Increment Note 1: Timer1 is a Type A timer. 2: This parameter is characterized, but not tested in manufacturing. 3: N = Prescale Value (1, 8, 64, 256).  2011-2016 Microchip Technology Inc. DS60001168J-page 275

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Max. Units Conditions No. TB10 TTXH TxCK Synchronous, with [(12.5ns or 1 TPB)/N] — ns Must also meet N = prescale High Time prescaler + 25ns parameter value TB15 (1, 2, 4, 8, TB11 TTXL TxCK Synchronous, with [(12.5ns or 1 TPB)/N] — ns Must also meet 16, 32, 64, Low Time prescaler + 25ns parameter 256) TB15 TB15 TTXP TxCK Synchronous, with [(Greater of [(25ns or — ns VDD > 2.7V Input prescaler 2 TPB)/N] + 30ns Period [(Greater of [(25ns or — ns VDD < 2.7V 2 TPB)/N] + 50ns TB20 TCKEXTMRL Delay from External TxCK — 1 TPB — Clock Edge to Timer Increment Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 30-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure30-1 for load conditions. TABLE 30-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Max. Units Conditions No. IC10 TCCL ICx Input Low Time [(12.5ns or 1 TPB)/N] — ns Must also N = prescale + 25ns meet value (1, 4, 16) parameter IC15. IC11 TCCH ICx Input High Time [(12.5ns or 1 TPB)/N] — ns Must also + 25ns meet parameter IC15. IC15 TCCP ICx Input Period [(25ns or 2 TPB)/N] — ns — + 50ns Note 1: These parameters are characterized, but not tested in manufacturing. DS60001168J-page 276  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC11 OC10 Note: Refer to Figure30-1 for load conditions. TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. OC10 TCCF OCx Output Fall Time — — — ns See parameter DO32 OC11 TCCR OCx Output Rise Time — — — ns See parameter DO31 Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 30-9: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx OCx is tri-stated Note: Refer to Figure30-1 for load conditions. TABLE 30-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param Symbol Characteristics(1) Min Typical(2) Max Units Conditions No. OC15 TFD Fault Input to PWM I/O Change — — 50 ns — OC20 TFLT Fault Input Pulse Width 50 — — ns — Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2011-2016 Microchip Technology Inc. DS60001168J-page 277

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP31 SP30 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SP10 TSCL SCKx Output Low Time TSCK/2 — — ns — (Note 3) SP11 TSCH SCKx Output High Time TSCK/2 — — ns — (Note 3) SP20 TSCF SCKx Output Fall Time — — — ns See parameter DO32 (Note 4) SP21 TSCR SCKx Output Rise Time — — — ns See parameter DO31 (Note 4) SP30 TDOF SDOx Data Output Fall Time — — — ns See parameter DO32 (Note 4) SP31 TDOR SDOx Data Output Rise Time — — — ns See parameter DO31 (Note 4) SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns — TDIV2SCL to SCKx Edge SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns — TSCL2DIL to SCKx Edge Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS60001168J-page 278  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SCKX (CKP = 1) SP35 SP20 SP21 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions No. SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 — — ns — SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 — — ns — SP20 TSCF SCKx Output Fall Time (Note 4) — — — ns See parameter DO32 SP21 TSCR SCKx Output Rise Time (Note 4) — — — ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time — — — ns See parameter DO32 (Note 4) SP31 TDOR SDOx Data Output Rise Time — — — ns See parameter DO31 (Note 4) SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V SP36 TDOV2SC, SDOx Data Output Setup to 15 — — ns — TDOV2SCL First SCKx Edge SP40 TDIV2SCH, Setup Time of SDIx Data Input to 15 — — ns VDD > 2.7V TDIV2SCL SCKx Edge 20 — — ns VDD < 2.7V SP41 TSCH2DIL, Hold Time of SDIx Data Input 15 — — ns VDD > 2.7V TSCL2DIL to SCKx Edge 20 — — ns VDD < 2.7V Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2016 Microchip Technology Inc. DS60001168J-page 279

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions No. SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 — — ns — SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 — — ns — SP72 TSCF SCKx Input Fall Time — — — ns See parameter DO32 SP73 TSCR SCKx Input Rise Time — — — ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time (Note 4) — — — ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time (Note 4) — — — ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns — TDIV2SCL to SCKx Edge SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns — TSCL2DIL to SCKx Edge SP50 TSSL2SCH, SSx  to SCKx  or SCKx Input 175 — — ns — TSSL2SCL SP51 TSSH2DOZ SSx  to SDOx Output 5 — 25 ns — High-Impedance (Note 3) SP52 TSCH2SSH SSx after SCKx Edge TSCK + 20 — — ns — TSCL2SSH Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 50 ns. 4: Assumes 50 pF load on all SPIx pins. DS60001168J-page 280  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 — — ns — SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 — — ns — SP72 TSCF SCKx Input Fall Time — 5 10 ns — SP73 TSCR SCKx Input Rise Time — 5 10 ns — SP30 TDOF SDOx Data Output Fall Time — — — ns See parameter DO32 (Note 4) SP31 TDOR SDOx Data Output Rise Time — — — ns See parameter DO31 (Note 4) SP35 TSCH2DOV, SDOx Data Output Valid after — — 20 ns VDD > 2.7V TSCL2DOV SCKx Edge — — 30 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns — TDIV2SCL to SCKx Edge SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns — TSCL2DIL to SCKx Edge SP50 TSSL2SCH, SSx  to SCKx  or SCKx  Input 175 — — ns — TSSL2SCL Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 50 ns. 4: Assumes 50 pF load on all SPIx pins.  2011-2016 Microchip Technology Inc. DS60001168J-page 281

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions No. SP51 TSSH2DOZ SSx  to SDOX Output 5 — 25 ns — High-Impedance (Note 4) SP52 TSCH2SSH SSx  after SCKx Edge TSCK + — — ns — TSCL2SSH 20 SP60 TSSL2DOV SDOx Data Output Valid after — — 25 ns — SSx Edge Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 50 ns. 4: Assumes 50 pF load on all SPIx pins. DS60001168J-page 282  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure30-1 for load conditions. FIGURE 30-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure30-1 for load conditions.  2011-2016 Microchip Technology Inc. DS60001168J-page 283

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min.(1) Max. Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) — s — 400 kHz mode TPB * (BRG + 2) — s — 1 MHz mode TPB * (BRG + 2) — s — (Note 2) IM11 THI:SCL Clock High Time 100 kHz mode TPB * (BRG + 2) — s — 400 kHz mode TPB * (BRG + 2) — s — 1 MHz mode TPB * (BRG + 2) — s — (Note 2) IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode — 100 ns (Note 2) IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode — 300 ns (Note 2) IM25 TSU:DAT Data Input 100 kHz mode 250 — ns — Setup Time 400 kHz mode 100 — ns 1 MHz mode 100 — ns (Note 2) IM26 THD:DAT Data Input 100 kHz mode 0 — s — Hold Time 400 kHz mode 0 0.9 s 1 MHz mode 0 0.3 s (Note 2) IM30 TSU:STA Start Condition 100 kHz mode TPB * (BRG + 2) — s Only relevant for Setup Time 400 kHz mode TPB * (BRG + 2) — s Repeated Start condition 1 MHz mode TPB * (BRG + 2) — s (Note 2) IM31 THD:STA Start Condition 100 kHz mode TPB * (BRG + 2) — s After this period, the Hold Time 400 kHz mode TPB * (BRG + 2) — s first clock pulse is generated 1 MHz mode TPB * (BRG + 2) — s (Note 2) IM33 TSU:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — s — Setup Time 400 kHz mode TPB * (BRG + 2) — s 1 MHz mode TPB * (BRG + 2) — s (Note 2) IM34 THD:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — ns — Hold Time 400 kHz mode TPB * (BRG + 2) — ns 1 MHz mode TPB * (BRG + 2) — ns (Note 2) Note 1: BRG is the value of the I2C Baud Rate Generator. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: The typical value for this parameter is 104 ns. DS60001168J-page 284  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min.(1) Max. Units Conditions No. IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns — from Clock 400 kHz mode — 1000 ns — 1 MHz mode — 350 ns — (Note 2) IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s The amount of time the bus must be free 400 kHz mode 1.3 — s before a new 1 MHz mode 0.5 — s transmission can start (Note 2) IM50 CB Bus Capacitive Loading — 400 pF — IM51 TPGD Pulse Gobbler Delay 52 312 ns See Note 3 Note 1: BRG is the value of the I2C Baud Rate Generator. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: The typical value for this parameter is 104 ns.  2011-2016 Microchip Technology Inc. DS60001168J-page 285

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition Note: Refer to Figure30-1 for load conditions. FIGURE 30-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure30-1 for load conditions. DS60001168J-page 286  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Max. Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 1.3 — s PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode 0.5 — s — (Note 1) IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 0.6 — s PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode 0.5 — s — (Note 1) IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode — 100 ns (Note 1) IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode — 300 ns (Note 1) IS25 TSU:DAT Data Input 100 kHz mode 250 — ns — Setup Time 400 kHz mode 100 — ns 1 MHz mode 100 — ns (Note 1) IS26 THD:DAT Data Input 100 kHz mode 0 — ns — Hold Time 400 kHz mode 0 0.9 s 1 MHz mode 0 0.3 s (Note 1) IS30 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — ns Start condition 1 MHz mode 250 — ns (Note 1) IS31 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — ns clock pulse is generated 1 MHz mode 250 — ns (Note 1) IS33 TSU:STO Stop Condition 100 kHz mode 4000 — ns — Setup Time 400 kHz mode 600 — ns 1 MHz mode 600 — ns (Note 1) Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  2011-2016 Microchip Technology Inc. DS60001168J-page 287

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Max. Units Conditions No. IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns — Hold Time 400 kHz mode 600 — ns 1 MHz mode 250 ns (Note 1) IS40 TAA:SCL Output Valid from 100 kHz mode 0 3500 ns — Clock 400 kHz mode 0 1000 ns 1 MHz mode 0 350 ns (Note 1) IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s The amount of time the bus 400 kHz mode 1.3 — s must be free before a new transmission can start 1 MHz mode 0.5 — s (Note 1) IS50 CB Bus Capacitive Loading — 400 pF — Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS60001168J-page 288  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-34: ADC MODULE SPECIFICATIONS Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V — VDD – 0.3 VDD + 0.3 or or 2.5 3.6 AD02 AVSS Module VSS Supply VSS — AVDD V (Note 1) Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.0 — AVDD V (Note 1) AD05a 2.5 — 3.6 V VREFH = AVDD (Note 3) AD06 VREFL Reference Voltage Low AVSS — VREFH – 2.0 V (Note 1) AD07 VREF Absolute Reference 2.0 — AVDD V (Note 3) Voltage (VREFH – VREFL) AD08 IREF Current Drain — 250 400 µA ADC operating AD08a — — 3 µA ADC off Analog Input AD12 VINH-VINL Full-Scale Input Span VREFL — VREFH V — AD13 VINL Absolute VINL Input AVSS – 0.3 — AVDD/2 V — Voltage AD14 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V — AD15 — Leakage Current — ±0.001 ±0.610 µA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10 k AD17 RIN Recommended — — 5k  (Note 1) Impedance of Analog Voltage Source ADC Accuracy – Measurements with External VREF+/VREF- AD20c Nr Resolution 10 data bits bits — AD21c INL Integral Non-linearity > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD22c DNL Differential Non-linearity > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) AD23c GERR Gain Error > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD24c EOFF Offset Error > -1 — < 1 Lsb VINL = AVSS = 0V, AVDD = 3.3V AD25c — Monotonicity — — — — Guaranteed Note 1: These parameters are not characterized or tested in manufacturing. 2: With no missing codes. 3: These parameters are characterized, but not tested in manufacturing. 4: Characterized with a 1 kHz sine wave. 5: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.  2011-2016 Microchip Technology Inc. DS60001168J-page 289

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-34: ADC MODULE SPECIFICATIONS Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical Max. Units Conditions No. ADC Accuracy – Measurements with Internal VREF+/VREF- AD20d Nr Resolution 10 data bits bits (Note 3) AD21d INL Integral Non-linearity > -1 — < 1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD22d DNL Differential Non-linearity > -1 — < 1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2,3) AD23d GERR Gain Error > -4 — < 4 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD24d EOFF Offset Error > -2 — < 2 Lsb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD25d — Monotonicity — — — — Guaranteed Dynamic Performance AD32b SINAD Signal to Noise and 55 58.5 — dB (Notes 3,4) Distortion AD34b ENOB Effective Number of bits 9.0 9.5 — bits (Notes 3,4) Note 1: These parameters are not characterized or tested in manufacturing. 2: With no missing codes. 3: These parameters are characterized, but not tested in manufacturing. 4: Characterized with a 1 kHz sine wave. 5: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. DS60001168J-page 290  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-35: 10-BIT CONVERSION RATE PARAMETERS Standard Operating Conditions (see Note 3): 2.5V to 3.6V (unless otherwise stated) AC CHARACTERISTICS(2) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Sampling ADC Speed TAD Min. RS Max. VDD ADC Channels Configuration Time Min. 1 Msps to 400 ksps(1) 65 ns 132 ns 500 3.0V to 3.6V VREF- VREF+ ANx CHX SHA ADC Up to 400 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V VREF- VREF+ or or AVSS AVDD ANx CHX SHA ADC ANx or VREF- Note 1: External VREF- and VREF+ pins must be used for correct operation. 2: These parameters are characterized, but not tested in manufacturing. 3: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.  2011-2016 Microchip Technology Inc. DS60001168J-page 291

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions (see Note 4): 2.5V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typical(1) Max. Units Conditions No. Clock Parameters AD50 TAD ADC Clock Period(2) 65 — — ns See Table30-35 Conversion Rate AD55 TCONV Conversion Time — 12 TAD — — — AD56 FCNV Throughput Rate — — 1000 ksps AVDD = 3.0V to 3.6V (Sampling Speed) — — 400 ksps AVDD = 2.5V to 3.6V AD57 TSAMP Sample Time 1 TAD — — — TSAMP must be  132 ns Timing Parameters AD60 TPCS Conversion Start from Sample — 1.0 TAD — — Auto-Convert Trigger Trigger(3) (SSRC<2:0> = 111) not selected AD61 TPSS Sample Start from Setting 0.5 TAD — 1.5 TAD — — Sample (SAMP) bit AD62 TCSS Conversion Completion to — 0.5 TAD — — — Sample Start (ASAM = 1)(3) AD63 TDPU Time to Stabilize Analog Stage — — 2 s — from ADC Off to ADC On(3) Note 1: These parameters are characterized, but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: Characterized by design but not tested. 4: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized. DS60001168J-page 292  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM=0, SSRC<2:0>=000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104) in the “PIC32 Family Reference Manual”. 3 – Software clears ADxCON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One TAD for end of conversion.  2011-2016 Microchip Technology Inc. DS60001168J-page 293

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM=1, SSRC<2:0>=111, SAMC<4:0>=00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP TSAMP AD55 AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. 6 – One TAD for end of conversion. TSAMP is described in Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104). 7 – Begin conversion of next channel. 3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>. 4 – Convert bit 8. DS60001168J-page 294  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-20: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2  2011-2016 Microchip Technology Inc. DS60001168J-page 295

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-37: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Para Symbol Characteristics(1) Min. Typ. Max. Units Conditions m.No. PS1 TdtV2wr Data In Valid before WR or CS 20 — — ns — H Inactive (setup time) PS2 TwrH2dt WR or CS Inactive to Data-In 40 — — ns — I Invalid (hold time) PS3 TrdL2dt RD and CS Active to Data-Out — — 60 ns — V Valid PS4 TrdH2dtI RD Activeor CS Inactive to 0 — 10 ns — Data-Out Invalid PS5 Tcs CS Active Time TPB + 40 — — ns — PS6 TWR WR Active Time TPB + 25 — — ns — PS7 TRD RD Active Time TPB + 25 — — ns — Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 30-21: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 PMA<13:18> Address PM6 PMD<7:0> AAdddrdersess<s7<:70:>0> DDaatata PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> DS60001168J-page 296  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY T ABLE 30-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typ. Max. Units Conditions No. PM1 TLAT PMALL/PMALH Pulse Width — 1 TPB — — — PM2 TADSU Address Out Valid to — 2 TPB — — — PMALL/PMALH Invalid (address setup time) PM3 TADHOLD PMALL/PMALH Invalid to — 1 TPB — — — Address Out Invalid (address hold time) PM4 TAHOLD PMRD Inactive to Address Out 5 — — ns — Invalid (address hold time) PM5 TRD PMRD Pulse Width — 1 TPB — — — PM6 TDSU PMRD or PMENB Active to Data 15 — — ns — In Valid (data setup time) PM7 TDHOLD PMRD or PMENB Inactive to — 80 — ns — Data In Invalid (data hold time) Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 30-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PMA<13:18> Address PM2 + PM3 PMD<7:0> Address<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1>  2011-2016 Microchip Technology Inc. DS60001168J-page 297

PIC32MX1XX/2XX 28/36/44-PIN FAMILY T ABLE 30-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typ. Max. Units Conditions No. PM11 TWR PMWR Pulse Width — 1 TPB — — — PM12 TDVSU Data Out Valid before PMWR or — 2 TPB — — — PMENB goes Inactive (data setup time) PM13 TDVHOLD PMWR or PMEMB Invalid to Data — 1 TPB — — — Out Invalid (data hold time) Note 1: These parameters are characterized, but not tested in manufacturing. TABLE 30-40: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics(1) Min. Typ. Max. Units Conditions No. USB313 VUSB3V3 USB Voltage 3.0 — 3.6 V Voltage on VUSB3V3 must be in this range for proper USB operation USB315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V — USB316 VIHUSB Input High Voltage for USB Buffer 2.0 — — V — USB318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+ and D- must exceed this value while VCM is met USB319 VCM Differential Common Mode Range 0.8 — 2.5 V — USB320 ZOUT Driver Output Impedance 28.0 — 44.0  — USB321 VOL Voltage Output Low 0.0 — 0.3 V 1.425 k load connected to VUSB3V3 USB322 VOH Voltage Output High 2.8 — 3.6 V 1.425 k load connected to ground Note 1: These parameters are characterized, but not tested in manufacturing. DS60001168J-page 298  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 30-41: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions (see Note 3):2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA  +85°C for Industrial -40°CTA +105°C for V-temp Param Symbol Characteristic Min. Typ. Max. Units Conditions No. CTMU CURRENT SOURCE CTMUI1 IOUT1 Base Range(1) — 0.55 — µA CTMUCON<9:8> = 01 CTMUI2 IOUT2 10x Range(1) — 5.5 — µA CTMUCON<9:8> = 10 CTMUI3 IOUT3 100x Range(1) — 55 — µA CTMUCON<9:8> = 11 CTMUI4 IOUT4 1000x Range(1) — 550 — µA CTMUCON<9:8> = 00 CTMUFV1 VF Temperature Diode Forward — 0.598 — V TA = +25ºC, Voltage(1,2) CTMUCON<9:8> = 01 — 0.658 — V TA = +25ºC, CTMUCON<9:8> = 10 — 0.721 — V TA = +25ºC, CTMUCON<9:8> = 11 CTMUFV2 VFVR Temperature Diode Rate of — -1.92 — mV/ºC CTMUCON<9:8> = 01 Change(1,2) — -1.74 — mV/ºC CTMUCON<9:8> = 10 — -1.56 — mV/ºC CTMUCON<9:8> = 11 Note 1: Nominal value at center point of current trim range (CTMUCON<15:10> = 000000). 2: Parameters are characterized but not tested in manufacturing. Measurements taken with the following conditions: • VREF+ = AVDD = 3.3V • ADC module configured for conversion speed of 500 ksps • All PMD bits are cleared (PMDx = 0) • Executing a while(1) statement • Device operating from the FRC with no PLL 3: The CTMU module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is tested, but not characterized.  2011-2016 Microchip Technology Inc. DS60001168J-page 299

PIC32MX1XX/2XX 28/36/44-PIN FAMILY FIGURE 30-23: EJTAG TIMING CHARACTERISTICS T TCKcyc T T TCKhigh TCKlow T rf TCK T rf TMS TDI TTsetup TThold Trf T rf TDO T TRST*low TTDOout TTDOzstate TRST* Defined Undefined T rf TABLE 30-42: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Description(1) Min. Max. Units Conditions No. EJ1 TTCKCYC TCK Cycle Time 25 — ns — EJ2 TTCKHIGH TCK High Time 10 — ns — EJ3 TTCKLOW TCK Low Time 10 — ns — EJ4 TTSETUP TAP Signals Setup Time Before 5 — ns — Rising TCK EJ5 TTHOLD TAP Signals Hold Time After 3 — ns — Rising TCK EJ6 TTDOOUT TDO Output Delay Time from — 5 ns — Falling TCK EJ7 TTDOZSTATE TDO 3-State Delay Time from — 5 ns — Falling TCK EJ8 TTRSTLOW TRST Low Time 25 — ns — EJ9 TRF TAP Signals Rise/Fall Time, All — — ns — Input and Output Note 1: These parameters are characterized, but not tested in manufacturing. DS60001168J-page 300  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 31.0 50 MHz ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX1XX/2XX 28/36/44-pin Family electrical characteristics for devices operating at 50 MHz. The specifications for 50 MHz are identical to those shown in Section30.0 “Electrical Characteristics”, with the exception of the parameters listed in this chapter. Parameters in this chapter begin with the letter “M”, which denotes 50 MHz operation. For example, parameter DC29a in Section30.0 “Electrical Characteristics”, is the up to 40 MHz operation equivalent for MDC29a. Absolute maximum ratings for the PIC32MX1XX/2XX 28/36/44-pin Family 50 MHz devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings (See Note 1) Ambient temperature under bias...............................................................................................................-40°C to +85°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3).........................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD  2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on D+ or D- pin with respect to VUSB3V3..................................................................... -0.3V to (VUSB3V3 + 0.3V) Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s).......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................15 mA Maximum output current sourced by any I/O pin....................................................................................................15 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table30-2). 3: See the “Pin Diagrams” section for the 5V tolerant pins.  2011-2016 Microchip Technology Inc. DS60001168J-page 301

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 31.1 DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE Max. Frequency VDD Range Temp. Range Characteristic (in Volts)(1) (in °C) PIC32MX1XX/2XX 28/36/44-pin Family MDC5 2.3-3.6V -40°C to +85°C 50 MHz Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table30-11 for BOR values. TABLE 31-2: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical(3) Max. Units Conditions No. Operating Current (IDD) (Note 1, 2) MDC24 25 37 mA 50 MHz Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. 2: The test conditions for IDD measurements are as follows: • Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) • OSC2/CLKO is configured as an I/O input pin • USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 • CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1 • No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared • WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD • CPU executing while(1) statement from Flash 3: RTCC and JTAG are disabled 4: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. DS60001168J-page 302  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 31-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical(2) Max. Units Conditions No. Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1) MDC34a 8 13 mA 50 MHz Note 1: The test conditions for IIDLE current measurements are as follows: • Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) • OSC2/CLKO is configured as an I/O input pin • USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 • CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1 • No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared • WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD • RTCC and JTAG are disabled 2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param. Typical(2) Max. Units Conditions No. Power-Down Current (IPD) (Note 1) MDC40k 10 25 A -40°C Base Power-Down Current MDC40n 250 500 A +85°C Module Differential Current MDC41e 10 55 A 3.6V Watchdog Timer Current: IWDT (Note 3) MDC42e 23 55 A 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) MDC43d 1100 1300 A 3.6V ADC: IADC (Notes 3,4) Note 1: The test conditions for IPD current measurements are as follows: • Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) • OSC2/CLKO is configured as an I/O input pin • USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 • CPU is in Sleep mode, and SRAM data memory Wait states = 1 • No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set • WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD • RTCC and JTAG are disabled 2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.  2011-2016 Microchip Technology Inc. DS60001168J-page 303

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 31-5: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param. Symbol Characteristics Min. Typical Max. Units Conditions No. MOS10 FOSC External CLKI Frequency DC — 50 MHz EC (Note 2) (External clocks allowed only 4 — 50 MHz ECPLL (Note 1) in EC and ECPLL modes) Note 1: PLL input requirements: 4 MHz  FPLLIN  5 MHz (use PLL prescaler to reduce Fosc). This parameter is characterized, but tested at 10 MHz only at manufacturing. 2: This parameter is characterized, but not tested in manufacturing. TABLE 31-6: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param. Symbol Characteristics Min. Typical Max. Units Conditions No. MSP10 TSCL SCKx Output Low Time TSCK/2 — — ns — (Note 1,2) MSP11 TSCH SCKx Output High Time TSCK/2 — — ns — (Note 1,2) Note 1: These parameters are characterized, but not tested in manufacturing. 2: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. TABLE 31-7: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param. Symbol Characteristics(1) Min. Typ. Max. Units Conditions No. MSP10 TSCL SCKx Output Low Time TSCK/2 — — ns — (Note 1,2) MSP11 TSCH SCKx Output High Time TSCK/2 — — ns — (Note 1,2) Note 1: These parameters are characterized, but not tested in manufacturing. 2: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. DS60001168J-page 304  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE 31-8: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +105°C for V-temp Param. Symbol Characteristics Min. Typ. Max. Units Conditions No. MSP70 TSCL SCKx Input Low Time (Note 1,2) TSCK/2 — — ns — MSP71 TSCH SCKx Input High Time (Note 1,2) TSCK/2 — — ns — MSP51 TSSH2DOZ SSx  to SDOx Output 5 — 25 ns — High-Impedance (Note 2) Note 1: These parameters are characterized, but not tested in manufacturing. 2: The minimum clock period for SCKx is 40 ns. TABLE 31-9: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param. Symbol Characteristics Min. Typical Max. Units Conditions No. SP70 TSCL SCKx Input Low Time (Note 1,2) TSCK/2 — — ns — SP71 TSCH SCKx Input High Time (Note 1,2) TSCK/2 — — ns — Note 1: These parameters are characterized, but not tested in manufacturing. 2: The minimum clock period for SCKx is 40 ns.  2011-2016 Microchip Technology Inc. DS60001168J-page 305

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 306  2011-2016 Microchip Technology Inc.

 32.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS 2 0 1 1 Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes -20 only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating 1 6 range (e.g., outside specified power supply range) and therefore, outside the warranted range. M ic ro P c FIGURE 32-1: I/O OUTPUT VOLTAGE HIGH (VOH) FIGURE 32-2: I/O OUTPUT VOLTAGE LOW (VOL) h ip I T C e chn --00..005500 VVOOHH ((VV)) VVOOLL(cid:3)(cid:3)((VV)) 3 olog --00..004455 3.6V 00..005500 2 y In --00..004400 00..004455 3.6V M c. 3.3V 00..004400 3.3V X --00..003355 00..003355 --00..003300 3V 3V 1 IOH(A)IOH(A) ----0000....000022225050 IOH(A)IOH(A) 000000......000000223223050050 XX / -0.015 Absolute Maximum 00..001155 Absolute Maximum 2 -0.010 0.010 X -0.005 0.005 X 0.000 0.000 2 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 8 / 3 6 / 4 4 - P I N D S F 6 0 0 A 0 1 16 M 8 J -p I ag L e 3 Y 0 7

D FIGURE 32-3: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 32-5: TYPICAL IIDLE CURRENT @ VDD = 3.3V P S 6 0 I 0 C 01 8 1 6 440000 3 8 J-p 335500 7 2 a g M e 3 330000 6 0 X 8 225500 A) 5 m (µA)(µA)PDPD 220000 urrent ( 4 1X II 115500 CLE 3 X DD 100 II / 2 2 50 X 0 1 X -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 0 2 Temperature (Celsius) 0 10 20 30 40 8 MIPS / 3 6 FIGURE 32-4: TYPICAL IDD CURRENT @ VDD = 3.3V / 4 4 2255 - P I 2200 N  1155 F 2 A)A) 0 mm A 11-2 ((DDDD 1100 M 0 II 1 6 M I ic 5 L roc Y h ip T 0 e ch 0 10 20 30 40 n o lo MIPS g y In c .

 FIGURE 32-6: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 32-8: TYPICAL CTMU TEMPERATURE DIODE 20 FORWARD VOLTAGE 1 1 -2 88000000 0 1 6 M 77999900 00..885500 icro 77998800 00..880000 P chip Technology Inc. FRC Frequency (kHz)FRC Frequency (kHz) 77777777777999999999993456723456700000000000 Forward Voltage (V)Forward Voltage (V) 0000000000000............556677455667705050550505050000000000000 VVVFFF === 000...576925818 55 µA,5 V.5F VµRA ,= V 0-F1.5V.55R6 µ= mA -,1V V./7ºFC4V Rm =V /-º1C.92 mV/ºC IC32MX 1 7910 0.400 X 7900 0.350 X -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 / Temperature (Celsius) Temperature (Celsius) 2 X X FIGURE 32-7: TYPICAL LPRC FREQUENCY @ VDD = 3.3V 2 3333 8 / 3 6 / z)z) 4 HH 3322 kk y (y ( 4 cc nn - ee uu P qq ee FrFr I C C N RR 3311 PP D LL S F 6 0 0 A 0 1 16 M 8 30 J -p -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 I ag L e 3 Temperature (Celsius) Y 0 9

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 310  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC32MX220F XXXXXXXXXXXXXXXXXXXX 032B-I/SO e3 XXXXXXXXXXXXXXXXXXXX 1130235 YYWWNNN 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC32MX220F XXXXXXXXXXXXXXXXX 032B-I/SP e3 YYWWNNN 1130235 28-Lead SSOP Example XXXXXXXXXXXX PIC32MX220F XXXXXXXXXXXX 032B-I/SSe3 YYWWNNN 1130235 28-Lead QFN Example XXXXXXXX 32MX220F XXXXXXXX 032BE/MLe3 YYWWNNN 1130235 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2016 Microchip Technology Inc. DS60001168J-page 311

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 33.1 Package Marking Information (Continued) 36-Lead VTLA Example XXXXXXXX 32MX220F XXXXXXXX 032CE/TLe3 YYWWNNN 1130235 44-Lead VTLA Example XXXXXXXXXX PIC32 XXXXXXXXXX MX120F0 XXXXXXXXXX 32DI/TL e3 YYWWNNN 1130235 44-Lead QFN Example XXXXXXXXXX 32MX220F XXXXXXXXXX 032D-E/ML e3 XXXXXXXXXX 1130235 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX 32MX220F XXXXXXXXXX 032D-I/PT XXXXXXXXXX e3 YYWWNNN 1130235 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. DS60001168J-page 312  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 33.2 Package Details This section provides the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:18)(cid:14)(cid:19)(cid:20)(cid:9)(cid:16)(cid:21)(cid:7)(cid:11)(cid:11)(cid:9)(cid:22)(cid:23)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:24)(cid:16)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:30)(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"(cid:16)(cid:16)(cid:22)(cid:10)# $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:17): (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)(cid:16).(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) < < (cid:17)(cid:30)(cid:4)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:15)(cid:30)(cid:16). (cid:15)(cid:30)(cid:18). (cid:15)(cid:30):. (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4). < < 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + (cid:18)(cid:30)(cid:5)(cid:4) (cid:18)(cid:30):(cid:4) :(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:20)#&(cid:24) +(cid:15) .(cid:30)(cid:4)(cid:4) .(cid:30),(cid:4) .(cid:30)(cid:16)(cid:4) 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:6)(cid:30)(cid:6)(cid:4) (cid:15)(cid:4)(cid:30)(cid:17)(cid:4) (cid:15)(cid:4)(cid:30).(cid:4) 2(cid:23)(cid:23)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30).. (cid:4)(cid:30)(cid:18). (cid:4)(cid:30)(cid:6). 2(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 6(cid:15) (cid:15)(cid:30)(cid:17).(cid:14)(cid:8)+2 6(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) < (cid:4)(cid:30)(cid:17). 2(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:5)> :> 6(cid:13)(cid:11)#(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:17)(cid:17) < (cid:4)(cid:30),: $ (cid:13)(cid:6)(cid:12)% (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:26)#(cid:14)+(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)(cid:4)(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) ,(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14)-(cid:15)(cid:5)(cid:30).(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8)+21 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:18),/  2011-2016 Microchip Technology Inc. DS60001168J-page 313

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001168J-page 314  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:16)(cid:20)(cid:14)(cid:19)(cid:19)!(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)&(cid:23)(cid:7)(cid:11)(cid:9)’(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:24)(cid:16)(cid:10)(cid:25)(cid:9)(cid:26)(cid:9)(cid:29)(cid:30)(cid:30)(cid:9)(cid:21)(cid:14)(cid:11)(cid:9)(cid:31) (cid:8)!(cid:9)"(cid:16)(cid:10)&’(cid:10)# $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 5(cid:26)(cid:20)&! (cid:29)70;+(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:17): (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:30)(cid:15)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:25)(cid:23)(cid:10)(cid:14)&(cid:23)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:20)(cid:26)(cid:12)(cid:14)(cid:31)(cid:27)(cid:11)(cid:26)(cid:13) (cid:7) < < (cid:30)(cid:17)(cid:4)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:30)(cid:15)(cid:17)(cid:4) (cid:30)(cid:15),. (cid:30)(cid:15).(cid:4) /(cid:11)!(cid:13)(cid:14)&(cid:23)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:20)(cid:26)(cid:12)(cid:14)(cid:31)(cid:27)(cid:11)(cid:26)(cid:13) (cid:7)(cid:15) (cid:30)(cid:4)(cid:15). < < (cid:3)(cid:24)(cid:23)"(cid:27)#(cid:13)(cid:22)(cid:14)&(cid:23)(cid:14)(cid:3)(cid:24)(cid:23)"(cid:27)#(cid:13)(cid:22)(cid:14)=(cid:20)#&(cid:24) + (cid:30)(cid:17)(cid:6)(cid:4) (cid:30),(cid:15)(cid:4) (cid:30),,. (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:20)#&(cid:24) +(cid:15) (cid:30)(cid:17)(cid:5)(cid:4) (cid:30)(cid:17):. (cid:30)(cid:17)(cid:6). 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:30),(cid:5). (cid:15)(cid:30),(cid:16). (cid:15)(cid:30)(cid:5)(cid:4)(cid:4) (cid:25)(cid:20)(cid:10)(cid:14)&(cid:23)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:20)(cid:26)(cid:12)(cid:14)(cid:31)(cid:27)(cid:11)(cid:26)(cid:13) 6 (cid:30)(cid:15)(cid:15)(cid:4) (cid:30)(cid:15),(cid:4) (cid:30)(cid:15).(cid:4) 6(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:21) (cid:30)(cid:4)(cid:4): (cid:30)(cid:4)(cid:15)(cid:4) (cid:30)(cid:4)(cid:15). 5(cid:10)(cid:10)(cid:13)(cid:22)(cid:14)6(cid:13)(cid:11)#(cid:14)=(cid:20)#&(cid:24) )(cid:15) (cid:30)(cid:4)(cid:5)(cid:4) (cid:30)(cid:4).(cid:4) (cid:30)(cid:4)(cid:18)(cid:4) 6(cid:23)*(cid:13)(cid:22)(cid:14)6(cid:13)(cid:11)#(cid:14)=(cid:20)#&(cid:24) ) (cid:30)(cid:4)(cid:15)(cid:5) (cid:30)(cid:4)(cid:15): (cid:30)(cid:4)(cid:17)(cid:17) 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)(cid:8)(cid:23)*(cid:14)(cid:3)(cid:10)(cid:11)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:14)? (cid:13)/ < < (cid:30)(cid:5),(cid:4) $ (cid:13)(cid:6)(cid:12)% (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) ?(cid:14)(cid:3)(cid:20)(cid:12)(cid:26)(cid:20)%(cid:20)(cid:21)(cid:11)(cid:26)&(cid:14)0(cid:24)(cid:11)(cid:22)(cid:11)(cid:21)&(cid:13)(cid:22)(cid:20)!&(cid:20)(cid:21)(cid:30) ,(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:26)#(cid:14)+(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:30)(cid:4)(cid:15)(cid:4)@(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14)-(cid:15)(cid:5)(cid:30).(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:18)(cid:4)/  2011-2016 Microchip Technology Inc. DS60001168J-page 315

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001168J-page 316  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2016 Microchip Technology Inc. DS60001168J-page 317

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001168J-page 318  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)((cid:23)(cid:7)(cid:8)(cid:9))(cid:11)(cid:7)(cid:13)*(cid:9)$ (cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:20)(cid:7)+(cid:6)(cid:9)(cid:24),(cid:5)(cid:25)(cid:9)(cid:26)(cid:9)-.-(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"()$# /(cid:14)(cid:13)(cid:17)(cid:9)(cid:30)(cid:28)(cid:27)(cid:27)(cid:9)(cid:21)(cid:21)(cid:9)0 (cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19)+(cid:13)(cid:17) $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:17): (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)(cid:16).(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) (cid:4)(cid:30):(cid:4) (cid:4)(cid:30)(cid:6)(cid:4) (cid:15)(cid:30)(cid:4)(cid:4) (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)(cid:4) (cid:4)(cid:30)(cid:4)(cid:17) (cid:4)(cid:30)(cid:4). 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7), (cid:4)(cid:30)(cid:17)(cid:4)(cid:14)(cid:8)+2 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + (cid:16)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 +$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)=(cid:20)#&(cid:24) +(cid:17) ,(cid:30)(cid:16). ,(cid:30)(cid:18)(cid:4) (cid:5)(cid:30)(cid:17)(cid:4) 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:16)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 +$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:17) ,(cid:30)(cid:16). ,(cid:30)(cid:18)(cid:4) (cid:5)(cid:30)(cid:17)(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:17), (cid:4)(cid:30),(cid:4) (cid:4)(cid:30),. 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30).(cid:4) (cid:4)(cid:30).. (cid:4)(cid:30)(cid:18)(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:9)&(cid:23)(cid:9)+$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)# A (cid:4)(cid:30)(cid:17)(cid:4) < < $ (cid:13)(cid:6)(cid:12)% (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) (cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:20)!(cid:14)!(cid:11)*(cid:14)!(cid:20)(cid:26)(cid:12)"(cid:27)(cid:11)&(cid:13)#(cid:30) ,(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14)-(cid:15)(cid:5)(cid:30).(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8)+21 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:15)(cid:4)./  2011-2016 Microchip Technology Inc. DS60001168J-page 319

PIC32MX1XX/2XX 28/36/44-PIN FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)((cid:23)(cid:7)(cid:8)(cid:9))(cid:11)(cid:7)(cid:13)*(cid:9)$ (cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:20)(cid:7)+(cid:6)(cid:9)(cid:24),(cid:5)(cid:25)(cid:9)(cid:26)(cid:9)-.-(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"()$# /(cid:14)(cid:13)(cid:17)(cid:9)(cid:30)(cid:28)(cid:27)(cid:27)(cid:9)(cid:21)(cid:21)(cid:9)0 (cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19)+(cid:13)(cid:17) $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) DS60001168J-page 320  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY  2011-2016 Microchip Technology Inc. DS60001168J-page 321

PIC32MX1XX/2XX 28/36/44-PIN FAMILY DS60001168J-page 322  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY  2011-2016 Microchip Technology Inc. DS60001168J-page 323

PIC32MX1XX/2XX 28/36/44-PIN FAMILY DS60001168J-page 324  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 11(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)((cid:23)(cid:7)(cid:8)(cid:9))(cid:11)(cid:7)(cid:13)*(cid:9)$ (cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:20)(cid:7)+(cid:6)(cid:9)(cid:24),(cid:5)(cid:25)(cid:9)(cid:26)(cid:9)(cid:3).(cid:3)(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"()$# $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:5)(cid:5) (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)(cid:16).(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) (cid:4)(cid:30):(cid:4) (cid:4)(cid:30)(cid:6)(cid:4) (cid:15)(cid:30)(cid:4)(cid:4) (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)(cid:4) (cid:4)(cid:30)(cid:4)(cid:17) (cid:4)(cid:30)(cid:4). 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7), (cid:4)(cid:30)(cid:17)(cid:4)(cid:14)(cid:8)+2 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + :(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 +$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)=(cid:20)#&(cid:24) +(cid:17) (cid:16)(cid:30),(cid:4) (cid:16)(cid:30)(cid:5). (cid:16)(cid:30):(cid:4) 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) :(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 +$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:17) (cid:16)(cid:30),(cid:4) (cid:16)(cid:30)(cid:5). (cid:16)(cid:30):(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:17). (cid:4)(cid:30),(cid:4) (cid:4)(cid:30),: 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30),(cid:4) (cid:4)(cid:30)(cid:5)(cid:4) (cid:4)(cid:30).(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:9)&(cid:23)(cid:9)+$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)# A (cid:4)(cid:30)(cid:17)(cid:4) < < $ (cid:13)(cid:6)(cid:12)% (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) (cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:20)!(cid:14)!(cid:11)*(cid:14)!(cid:20)(cid:26)(cid:12)"(cid:27)(cid:11)&(cid:13)#(cid:30) ,(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14)-(cid:15)(cid:5)(cid:30).(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8)+21 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:15)(cid:4),/  2011-2016 Microchip Technology Inc. DS60001168J-page 325

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 11(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)((cid:23)(cid:7)(cid:8)(cid:9))(cid:11)(cid:7)(cid:13)*(cid:9)$ (cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:20)(cid:7)+(cid:6)(cid:9)(cid:24),(cid:5)(cid:25)(cid:9)(cid:26)(cid:9)(cid:3).(cid:3)(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"()$# $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) DS60001168J-page 326  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY 11(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)2(cid:17)(cid:14)(cid:19)(cid:9)((cid:23)(cid:7)(cid:8)(cid:9))(cid:11)(cid:7)(cid:13)3(cid:7)(cid:15)(cid:20)(cid:9)(cid:24)(cid:10)2(cid:25)(cid:9)(cid:26)(cid:9)4(cid:30).4(cid:30).4(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!*(cid:9)(cid:2)(cid:28)(cid:30)(cid:30)(cid:9)(cid:21)(cid:21)(cid:9)"2()(cid:10)# $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)6(cid:13)(cid:11)#! 7 (cid:5)(cid:5) 6(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30):(cid:4)(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) < < (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6). (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4). (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4). < (cid:4)(cid:30)(cid:15). 2(cid:23)(cid:23)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30)(cid:5). (cid:4)(cid:30)(cid:16)(cid:4) (cid:4)(cid:30)(cid:18). 2(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 6(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8)+2 2(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> ,(cid:30).> (cid:18)> 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:20)#&(cid:24) +(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 6(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) < (cid:4)(cid:30)(cid:17)(cid:4) 6(cid:13)(cid:11)#(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30),(cid:4) (cid:4)(cid:30),(cid:18) (cid:4)(cid:30)(cid:5). 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DS60001168J-page 327

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001168J-page 328  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY APPENDIX A: REVISION HISTORY This revision includes the addition of the following devices: Revision A (May 2011) • PIC32MX130F064B • PIC32MX230F064B This is the initial released version of this document. • PIC32MX130F064C • PIC32MX230F064C • PIC32MX130F064D • PIC32MX230F064D Revision B (October 2011) • PIC32MX150F128B • PIC32MX250F128B The following two global changes are included in this • PIC32MX150F128C • PIC32MX250F128C revision: • PIC32MX150F128D • PIC32MX250F128D • All packaging references to VLAP have been Text and formatting changes were incorporated changed to VTLA throughout the document throughout the document. • All references to VCORE have been removed All other major changes are referenced by their • All occurrences of the ASCL1, ASCL2, ASDA1, and respective section in TableA-1. ASDA2 pins have been removed • V-temp temperature range (-40ºC to +105ºC) was added to all electrical specification tables TABLE A-1: MAJOR SECTION UPDATES Section Update Description “32-bit Microcontrollers (up to 128 KB Split the existing Features table into two: PIC32MX1XX General Purpose Flash and 32 KB SRAM) with Audio Family Features (Table1) and PIC32MX2XX USB Family Features (Table2). and Graphics Interfaces, USB, and Added the SPDIP package reference (see Table1, Table2, and “Pin Advanced Analog” Diagrams”). Added the new devices to the applicable pin diagrams. Changed PGED2 to PGED1 on pin 35 of the 36-pin VTLA diagram for PIC32MX220F032C, PIC32MX220F016C, PIC32MX230F064C, and PIC32MX250F128C devices. 1.0“Device Overview” Added the SPDIP package reference and updated the pin number for AN12 for 44-pin QFN devices in the Pinout I/O Descriptions (see Table1-1). Added the PGEC4/PGED4 pin pair and updated the C1INA-C1IND and C2INA-C2IND pin numbers for 28-pin SSOP/SPDIP/SOIC devices in the Pinout I/O Descriptions (see Table1-1). 2.0“Guidelines for Getting Started Updated the Recommended Minimum Connection diagram (see Figure2-1). with 32-bit Microcontrollers”  2011-2016 Microchip Technology Inc. DS60001168J-page 329

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Update Description 4.0“Memory Organization” Added Memory Maps for the new devices (see Figure4-3 and Figure4-4). Removed the BMXCHEDMA bit from the Bus Matrix Register map (see Table4-1). Added the REFOTRIM register, added the DIVSWEN bit to the REFOCON registers, added Note 4 to the ULOCK and SOSCEN bits and added the PBDIVRDY bit in the OSCCON register in the in the System Control Register map (see Table4-16). Removed the ALTI2C1 and ALTI2C2 bits from the DEVCFG3 register and added Note 1 to the UPLLEN and UPLLIDIV<2:0> bits of the DEVCFG2 register in the Device Configuration Word Summary (see Table4-17). Updated Note 1 in the Device and Revision ID Summary (see Table4-18). Added Note 2 to the PORTA Register map (see Table4-19). Added the ANSB6 and ANSB12 bits to the ANSELB register in the PORTB Register map (see Table4-20). Added Notes 2 and 3 to the PORTC Register map (see Table4-21). Updated all register names in the Peripheral Pin Select Register map (see Table4-23). Added values in support of new devices (16 KB RAM and 32 KB RAM) in the Data RAM Size register (see Register4-5). Added values in support of new devices (64 KB Flash and 128 KB Flash) in the Data RAM Size register (see Register4-5). 8.0“Oscillator Configuration” Added Note 5 to the PIC32MX1XX/2XX Family Clock Diagram (see Figure8-1). Added the PBDIVRDY bit and Note 2 to the Oscillator Control register (see Register8-1). Added the DIVSWEN bit and Note 3 to the Reference Oscillator Control register (see Register8-3). Added the REFOTRIM register (see Register8-4). 21.0“10-bit Analog-to-Digital Updated the ADC1 Module Block Diagram (see Figure21-1). Converter (ADC)” Updated the Notes in the ADC Input Select register (see Register21-4). 24.0“Charge Time Measurement Updated the CTMU Block Diagram (see Figure24-1). Unit (CTMU)” Added Note 3 to the CTMU Control register (see Register24-1) 26.0“Special Features” Added Note 1 and the PGEC4/PGED4 pin pair to the ICESEL<1:0> bits in DEVCFG0: Device Configuration Word 0 (see Register26-1). Removed the ALTI2C1 and ALTI2C2 bits from the Device Configuration Word 3 register (see Register26-4). Removed 26.3.3 “Power-up Requirements”. Added Note 3 to the Connections for the On-Chip Regulator diagram (see Figure26-2). Updated the Block Diagram of Programming, Debugging and Trace Ports diagram (see Figure26-3). DS60001168J-page 330  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Update Description 29.0“Electrical Characteristics” Updated the Absolute Maximum Ratings (removed Voltage on VCORE with respect to VSS). Added the SPDIP specification to the Thermal Packaging Characteristics (see Table29-2). Updated the Typical values for parameters DC20-DC24 in the Operating Current (IDD) specification (see Table29-5). Updated the Typical values for parameters DC30a-DC34a in the Idle Current (IIDLE) specification (see Table29-6). Updated the Typical values for parameters DC40i and DC40n and removed parameter DC40m in the Power-down Current (IPD) specification (see Table29-7). Removed parameter D320 (VCORE) from the Internal Voltage Regulator Specifications and updated the Comments (see Table29-13). Updated the Minimum, Typical, and Maximum values for parameter F20b in the Internal FRC Accuracy specification (see Table29-17). Removed parameter SY01 (TPWRT) and removed all Conditions from Resets Timing (see Table29-20). Updated all parameters in the CTMU Specifications (see Table29-39). 31.0“Packaging Information” Added the 28-lead SPDIP package diagram information (see 31.1“Package Marking Information” and 31.2“Package Details”). “Product Identification System” Added the SPDIP (SP) package definition. Revision C (November 2011) All major changes are referenced by their respective section in TableA-2. TABLE A-2: MAJOR SECTION UPDATES Section Update Description “32-bit Microcontrollers (up to 128 KB Revised the source/sink on I/O pins (see “Input/Output” on page 1). Flash and 32 KB SRAM) with Audio Added the SPDIP package to the PIC32MX220F032B device in the and Graphics Interfaces, USB, and PIC32MX2XX USB Family Features (see Table2). Advanced Analog” 4.0“Memory Organization” Removed ANSB6 from the ANSELB register and added the ODCB6, ODCB10, and ODCB11 bits in the PORTB Register Map (see Table4-20). 29.0“Electrical Characteristics” Updated the minimum value for parameter OS50 in the PLL Clock Timing Specifications (see Table29-16).  2011-2016 Microchip Technology Inc. DS60001168J-page 331

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Revision D (February 2012) All occurrences of VUSB were changed to: VUSB3V3. In addition, text and formatting changes were incorporated throughout the document. All other major changes are referenced by their respective section in TableA-3. TABLE A-3: MAJOR SECTION UPDATES Section Update Description “32-bit Microcontrollers (up to 128 Corrected a part number error in all pin diagrams. KB Flash and 32 KB SRAM) with Updated the DMA Channels (Programmable/Dedicated) column in the Audio and Graphics Interfaces, USB, PIC32MX1XX General Purpose Family Features (see Table1). and Advanced Analog” 1.0“Device Overview” Added the TQFP and VTLA packages to the 44-pin column heading and updated the pin numbers for the SCL1, SCL2, SDA1, and SDA2 pins in the Pinout I/O Descriptions (see Table1-1). 7.0“Interrupt Controller” Updated the Note that follows the features. Updated the Interrupt Controller Block Diagram (see Figure7-1). 29.0“Electrical Characteristics” Updated the Maximum values for parameters DC20-DC24, and the Minimum value for parameter DC21 in the Operating Current (IDD) DC Characteristics (see Table29-5). Updated all Minimum and Maximum values for the Idle Current (IIDLE) DC Characteristics (see Table29-6). Updated the Maximum values for parameters DC40k, DC40l, DC40n, and DC40m in the Power-down Current (IPD) DC Characteristics (see Table29-7). Changed the minimum clock period for SCKx from 40 ns to 50 ns in Note 3 of the SPIx Master and Slave Mode Timing Requirements (see Table29-26 through Table29-29). 30.0“DC and AC Device Updated the Typical IIDLE Current @ VDD = 3.3V graph (see Figure30-5). Characteristics Graphs” DS60001168J-page 332  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Revision E (October 2012) All singular pin diagram occurrences of CVREF were changed to: CVREFOUT. In addition, minor text and for- matting changes were incorporated throughout the document. All major changes are referenced by their respective section in TableA-4. TABLE A-4: MAJOR SECTION UPDATES Section Update Description “32-bit Microcontrollers (up to Updated the following feature sections: 128 KB Flash and 32 KB SRAM) • “Operating Conditions” with Audio and Graphics • “Communication Interfaces” Interfaces, USB, and Advanced Analog” 2.0“Guidelines for Getting Removed Section 2.8 “Configuration of Analog and Digital Pins During ICSP Started with 32-bit MCUs” Operations”. 3.0“CPU” Removed references to GPR shadow registers in 3.1“Features” and 3.2.1“Execution Unit”. 4.0“Memory Organization” Updated the BRG bit range in the SPI1 and SPI2 Register Map (see Table4-8). Added the PWP<6> bit to the Device Configuration Word Summary (see Table4-17). 5.0“Flash Program Memory” Added a note with Flash page size and row size information. 7.0“Interrupt Controller” Updated the TPC<2:0> bit definitions (see Register7-1). Updated the IPTMR<31:0> bit definition (see Register7-3). 8.0“Oscillator Configuration” Updated the PIC32MX1XX/2XX Family Clock Diagram (see Figure8-1). Updated the RODIV<14:0> bit definitions (see Register8-3). 10.0“USB On-The-Go (OTG)” Updated the Notes in the USB Interface Diagram (see Figure10-1). 18.0“Universal Asynchronous Updated the baud rate range in the list of primary features. Receiver Transmitter (UART)” 26.0“Special Features” Added the PWP<6> bit to the Device Configuration Word 0 (see Register26-1). 29.0“Electrical Characteristics” Added Note 1 to Operating MIPS vs. Voltage (see Table29-1). Added Note 2 to DC Temperature and Voltage Specifications (see Table29-4). Updated the Conditions for parameter DC25 in DC Characteristics: Operating Current (IDD) (see Table29-5). Added Note 2 to Electrical Characteristics: BOR (see Table29-10). Added Note 4 to Comparator Specifications (see Table29-12). Added Note 5 to ADC Module Specifications (see Table29-32). Updated the 10-bit Conversion Rate Parameters and added Note 3 (see Table29-33). Added Note 4 to the Analog-to-Digital Conversion Timing Requirements (see Table29-34). Added Note 3 to CTMU Current Source Specifications (see Table29-39). 30.0“50 MHz Electrical New chapter with electrical characteristics for 50 MHz devices. Characteristics” 31.0“Packaging Information” The 36-pin and 44-pin VTLA packages have been updated.  2011-2016 Microchip Technology Inc. DS60001168J-page 333

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Revision F (February 2014) In addition, this revision includes the following major changes as described in TableA-5, as well as minor This revision includes the addition of the following updates to text and formatting, which were devices: incorporated throughout the document. • PIC32MX170F256B • PIC32MX270F256B • PIC32MX170F256D • PIC32MX270F256D TABLE A-5: MAJOR SECTION UPDATES Section Update Description 32-bit Microcontrollers (up to 256 Added new devices to the family features (see Table1 and Table2). KB Flash and 64 KB SRAM) with Updated pin diagrams to include new devices (see “Pin Diagrams”). Audio and Graphics Interfaces, USB, and Advanced Analog 1.0“Device Overview” Added Note 3 reference to the following pin names: VBUS, VUSB3V3, VBUSON, D+, D-, and USBID. 2.0“Guidelines for Getting Replaced Figure2-1: Recommended Minimum Connection. Started with 32-bit MCUs” Updated Figure2-2: MCLR Pin Connections. Added 2.9“SOSC Design Recommendation”. 4.0“Memory Organization” Added memory tables for devices with 64 KB RAM (see Table4-4 through Table4-5). Changed the Virtual Addresses for all registers and updated the PWP bits in the DEVCFG: Device Configuration Word Summary (see Table4-17). Updated the ODCA, ODCB, and ODCC port registers (see Table4-19, Table4- 20, and Table4-21). The RTCTIME, RTCDATE, ALRMTIME, and ALRMDATE registers were updated (see Table4-25). Added Data Ram Size value for 64 KB RAM devices (see Register4-5). Added Program Flash Size value for 256 KB Flash devices (see Register4-5). 12.0“Timer1” The Timer1 block diagram was updated to include the 16-bit data bus (see Figure12-1). 13.0“Timer2/3, Timer4/5” The Timer2-Timer5 block diagram (16-bit) was updated to include the 16-bit data bus (see Figure13-1). The Timer2/3, Timer4/5 block diagram (32-bit) was updated to include the 32- bit data bus (see Figure13-1). 19.0“Parallel Master Port (PMP)” The CSF<1:0> bit value definitions for ‘00’ and ‘01’ were updated (see Register19-1). Bit 14 in the Parallel Port Address register (PMADDR) was updated (see Register19-3). 20.0“Real-Time Clock and The following registers were updated: Calendar (RTCC)” RTCTIME (see Register20-3) RTCDATE (see Register20-4) ALRMTIME (see Register20-5) ALRMDATE (see Register20-6) 26.0“Special Features” Updated the PWP bits (see Register26-1). 29.0“Electrical Characteristics” Added parameters DO50 and DO50a to the Capacitive Loading Requirements on Output Pins (see Table29-14). Added Note 5 to the IDD DC Characteristics (see Table29-5). Added Note 4 to the IIDLE DC Characteristics (see Table29-6). Added Note 5 to the IPD DC Characteristics (see Table29-7). Updated the conditions for parameters USB321 (VOL) and USB322 (VOH) in the OTG Electrical Specifications (see Table29-38). Product Identification System Added 40 MHz speed information. DS60001168J-page 334  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Revision G (April 2015) All peripheral SFR maps have been relocated from the Memory chapter to their respective peripheral This revision includes the addition of the following chapters. devices: In addition, this revision includes the following major • PIC32MX130F256B • PIC32MX230F256B changes as described in TableA-6, as well as minor • PIC32MX130F256D • PIC32MX230F256D updates to text and formatting, which were incorporated throughout the document. The title of the document was updated to avoid confusion with the PIC32MX1XX/2XX/5XX 64/100-pin Family data sheet. TABLE A-6: MAJOR SECTION UPDATES Section Update Description 32-bit Microcontrollers (up to 256 Added new devices to the family features (see Table1 and Table2). KB Flash and 64 KB SRAM) with Updated pin diagrams to include new devices (see Pin Diagrams). Audio and Graphics Interfaces, USB, and Advanced Analog 2.0“Guidelines for Getting Updated these sections: 2.2“Decoupling Capacitors”, 2.3“Capacitor on Started with 32-bit MCUs” Internal Voltage Regulator (VCAP)”, 2.4“Master Clear (MCLR) Pin”, 2.8.1“Crystal Oscillator Design Consideration” 4.0“Memory Organization” Added Memory Map for new devices (see Figure4-6). 14.0“Watchdog Timer (WDT)” New chapter created from content previously located in the Special Features chapter. 30.0“Electrical Characteristics” Removed parameter D312 (TSET) from the Comparator Specifications (see Table30-12). Added the Comparator Voltage Reference Specifications (see Table30-13). Updated Table30-12. Revision H (July 2015) This revision includes the following major changes as described in TableA-7, as well as minor updates to text and formatting, which were incorporated throughout the document. TABLE A-7: MAJOR SECTION UPDATES Section Update Description 2.0“Guidelines for Getting Section 2.9 “Sosc Design Recommendation” was removed. Started with 32-bit MCUs” 8.0“Oscillator Configuration” The Primary Oscillator (POSC) logic in the Oscillator diagram was updated (see Figure8-1). 30.0“Electrical Characteristics” The Power-Down Current (IPD) DC Characteristics parameter DC40k was updated (see Table30-7). Table 30-9:“DC Characteristics: I/O Pin Input Injection current Specifications” was added.  2011-2016 Microchip Technology Inc. DS60001168J-page 335

PIC32MX1XX/2XX 28/36/44-PIN FAMILY Revision J (April 2016) This revision includes the following major changes as described in TableA-8, as well as minor updates to text and formatting, which were incorporated throughout the document. TABLE A-8: MAJOR SECTION UPDATES Section Update Description “32-bit Microcontrollers (up to The PIC32MX270FDB device and Note 4 were added to TABLE 2:“PIC32MX2XX 256 KB Flash and 64 KB 28/36/44-pin USB Family Features”. SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog” 2.0“Guidelines for Getting EXAMPLE 2-1:“Crystal Load Capacitor Calculation” was updated. Started with 32-bit MCUs” 30.0“Electrical Parameter DO50a (CSOSC) was removed from the Capacitive Loading Characteristics” Requirements on Output Pins AC Characteristics (see Table30-16). “Product Identification The device mapping was updated to include type B for Software Targeting. System” DS60001168J-page 336  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY INDEX Numerics Core Exception Types................................................36 EJTAG Debug Support...............................................36 50 MHz Electrical Characteristics.....................................301 Power Management...................................................36 A CPU Module.................................................................27, 33 AC Characteristics............................................................269 Customer Change Notification Service.............................341 10-Bit Conversion Rate Parameters.........................291 Customer Notification Service..........................................341 ADC Specifications...................................................289 Customer Support.............................................................341 Analog-to-Digital Conversion Requirements.............292 D EJTAG Timing Requirements...................................300 DC and AC Characteristics Internal FRC Accuracy..............................................271 Graphs and Tables...................................................307 Internal RC Accuracy................................................271 DC Characteristics............................................................258 OTG Electrical Specifications...................................298 I/O Pin Input Specifications..............................263, 264 Parallel Master Port Read Requirements.................297 I/O Pin Output Specifications....................................265 Parallel Master Port Write.........................................298 Parallel Master Port Write Requirements..................298 Idle Current (IIDLE)....................................................261 Parallel Slave Port Requirements.............................296 Power-Down Current (IPD)........................................262 Program Memory......................................................266 PLL Clock Timing......................................................271 Temperature and Voltage Specifications..................259 Analog-to-Digital Converter (ADC)....................................209 DC Characteristics (50 MHz)............................................302 Assembler MPASM Assembler...................................................254 Idle Current (IIDLE)....................................................303 Power-Down Current (IPD)........................................303 B Development Support.......................................................253 Block Diagrams Direct Memory Access (DMA) Controller............................83 ADC Module..............................................................209 E Comparator I/O Operating Modes.............................219 Electrical Characteristics..................................................257 Comparator Voltage Reference................................223 AC.............................................................................269 Connections for On-Chip Voltage Regulator.............250 Errata..................................................................................16 Core and Peripheral Modules.....................................19 External Clock CPU............................................................................33 Timer1 Timing Requirements...................................275 CTMU Configurations Timer2, 3, 4, 5 Timing Requirements.......................276 Time Measurement...........................................227 Timing Requirements...............................................270 DMA............................................................................83 External Clock (50 MHz) I2C Circuit.................................................................174 Timing Requirements...............................................304 Input Capture............................................................157 Interrupt Controller......................................................63 F JTAG Programming, Debugging and Trace Ports....250 Flash Program Memory......................................................53 Output Compare Module...........................................161 RTSP Operation.........................................................53 PMP Pinout and Connections to External Devices...189 Reset System..............................................................59 I RTCC........................................................................199 I/O Ports...........................................................................127 SPI Module...............................................................165 Parallel I/O (PIO)......................................................128 Timer1.......................................................................143 Write/Read Timing....................................................128 Timer2/3/4/5 (16-Bit).................................................147 Input Change Notification.................................................128 Typical Multiplexed Port Structure............................127 Instruction Set...................................................................251 UART........................................................................181 Inter-Integrated Circuit (I2C..............................................173 WDT and Power-up Timer........................................153 Internal Voltage Reference Specifications........................268 Brown-out Reset (BOR) Internet Address...............................................................341 and On-Chip Voltage Regulator................................250 Interrupt Controller..............................................................63 C IRG, Vector and Bit Location......................................64 C Compilers M MPLAB C18..............................................................254 Memory Maps Charge Time Measurement Unit. See CTMU. PIC32MX110/210 Devices Clock Diagram....................................................................74 (4 KB RAM, 16 KB Flash)...................................38 Comparator PIC32MX120/220 Devices Specifications....................................................267, 268 (8 KB RAM, 32 KB Flash)...................................39 Comparator Module..........................................................219 PIC32MX130/230 Comparator Voltage Reference (CVref.............................223 (16 KB RAM, 256 KB Flash)...............................43 Configuration Bit...............................................................239 PIC32MX130/230 Devices Configuring Analog Port Pins............................................128 (16 KB RAM, 64 KB Flash).................................40 CPU PIC32MX150/250 Devices Architecture Overview.................................................34 (32 KB RAM, 128 KB Flash)...............................41 Coprocessor 0 Registers............................................35 PIC32MX170/270  2011-2016 Microchip Technology Inc. DS60001168J-page 337

PIC32MX1XX/2XX 28/36/44-PIN FAMILY (64 KB RAM, 256 KB Flash)...............................42 DCHxSPTR (DMA Channel ’x’ Source Pointer)..........99 Memory Organization..........................................................37 DCHxSSA (DMA Channel ’x’ Source Start Address)..97 Microchip Internet Web Site..............................................341 DCHxSSIZ (DMA Channel ’x’ Source Size)................98 MPLAB ASM30 Assembler, Linker, Librarian...................254 DCRCCON (DMA CRC Control).................................90 MPLAB Integrated Development Environment Software..253 DCRCDATA (DMA CRC Data)...................................92 MPLAB PM3 Device Programmer.....................................255 DCRCXOR (DMA CRCXOR Enable).........................92 MPLAB REAL ICE In-Circuit Emulator System.................255 DEVCFG0 (Device Configuration Word 0)...............241 MPLINK Object Linker/MPLIB Object Librarian................254 DEVCFG1 (Device Configuration Word 1)...............243 DEVCFG2 (Device Configuration Word 2)...............245 O DEVCFG3 (Device Configuration Word 3)...............247 Oscillator Configuration.......................................................73 DEVID (Device and Revision ID)..............................249 Output Compare................................................................161 DMAADDR (DMA Address)........................................89 DMACON (DMA Controller Control)...........................88 P DMASTAT (DMA Status)............................................89 Packaging.........................................................................311 I2CxCON (I2C Control).............................................176 Details.......................................................................313 I2CxSTAT (I2C Status).............................................178 Marking.....................................................................311 ICxCON (Input Capture ’x’ Control)..........................159 Parallel Master Port (PMP)...............................................189 IECx (Interrupt Enable Control)..................................70 PIC32 Family USB Interface Diagram...............................104 IFSx (Interrupt Flag Status)........................................70 Pinout I/O Descriptions (table)............................................20 INTCON (Interrupt Control).........................................68 Power-on Reset (POR) INTSTAT (Interrupt Status).........................................69 and On-Chip Voltage Regulator................................250 IPCx (Interrupt Priority Control)..................................71 Power-Saving Features.....................................................233 IPTMR (Interrupt Proximity Timer)..............................69 CPU Halted Methods................................................233 NVMADDR (Flash Address).......................................56 Operation..................................................................233 NVMCON (Programming Control)..............................55 with CPU Running.....................................................233 NVMDATA (Flash Program Data)...............................57 R NVMKEY (Programming Unlock)................................56 NVMSRCADDR (Source Data Address)....................57 Real-Time Clock and Calendar (RTCC)............................199 OCxCON (Output Compare ’x’ Control)....................163 Register Maps...............................................................45–?? OSCCON (Oscillator Control).....................................76 Registers OSCTUN (FRC Tuning)..............................................79 [pin name]R (Peripheral Pin Select Input).................141 PMADDR (Parallel Port Address).............................195 AD1CHS (ADC Input Select)....................................217 PMAEN (Parallel Port Pin Enable)............................196 AD1CON1 (ADC Control 1)......................................213 PMCON (Parallel Port Control).................................191 AD1CON2 (ADC Control 2)......................................215 PMMODE (Parallel Port Mode).................................193 AD1CON3 (ADC Control 3)......................................216 PMSTAT (Parallel Port Status (Slave Modes Only)..197 AD1CSSL (ADC Input Scan Select).........................218 REFOCON (Reference Oscillator Control).................80 ALRMDATE (Alarm Date Value)...............................208 REFOTRIM (Reference Oscillator Trim).....................82 ALRMTIME (Alarm Time Value)...............................207 RPnR (Peripheral Pin Select Output).......................141 BMXBOOTSZ (Boot Flash (IFM) Size........................51 RSWRST (Software Reset)........................................62 BMXCON (Bus Matrix Configuration).........................46 RTCALRM (RTC Alarm Control)...............................203 BMXDKPBA (Data RAM Kernel Program RTCCON (RTC Control)...........................................201 Base Address)....................................................47 RTCDATE (RTC Date Value)...................................206 BMXDRMSZ (Data RAM Size Register).....................50 RTCTIME (RTC Time Value)....................................205 BMXDUDBA (Data RAM User Data Base Address)...48 SPIxCON (SPI Control)............................................167 BMXDUPBA (Data RAM User Program SPIxCON2 (SPI Control 2).......................................170 Base Address)....................................................49 SPIxSTAT (SPI Status).............................................171 BMXPFMSZ (Program Flash (PFM) Size)..................51 T1CON (Type A Timer Control)................................145 BMXPUPBA (Program Flash (PFM) User Program TxCON (Type B Timer Control)................................150 Base Address)....................................................50 U1ADDR (USB Address)..........................................121 CFGCON (Configuration Control).............................248 U1BDTP1 (USB BDT Page 1)..................................123 CM1CON (Comparator 1 Control)............................221 U1BDTP2 (USB BDT Page 2)..................................124 CMSTAT (Comparator Status Register)...................222 U1BDTP3 (USB BDT Page 3)..................................124 CNCONx (Change Notice Control for PORTx).........142 U1CNFG1 (USB Configuration 1).............................125 CTMUCON (CTMU Control).....................................229 U1CON (USB Control)..............................................119 CVRCON (Comparator Voltage Reference Control).225 U1EIE (USB Error Interrupt Enable).........................117 DCHxCON (DMA Channel ’x’ Control)........................93 U1EIR (USB Error Interrupt Status)..........................115 DCHxCPTR (DMA Channel ’x’ Cell Pointer).............100 U1EP0-U1EP15 (USB Endpoint Control).................126 DCHxCSIZ (DMA Channel ’x’ Cell-Size)...................100 U1FRMH (USB Frame Number High)......................122 DCHxDAT (DMA Channel ’x’ Pattern Data)..............101 U1FRML (USB Frame Number Low)........................121 DCHxDPTR (Channel ’x’ Destination Pointer)............99 U1IE (USB Interrupt Enable)....................................114 DCHxDSA (DMA Channel ’x’ Destination U1IR (USB Interrupt)................................................113 Start Address).....................................................97 U1OTGCON (USB OTG Control).............................111 DCHxDSIZ (DMA Channel ’x’ Destination Size).........98 U1OTGIE (USB OTG Interrupt Enable)....................109 DCHxECON (DMA Channel ’x’ Event Control)...........94 U1OTGIR (USB OTG Interrupt Status).....................108 DCHxINT (DMA Channel ’x’ Interrupt Control)............95 DS60001168J-page 338  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY U1OTGSTAT (USB OTG Status)..............................110 Parallel Slave Port....................................................295 U1PWRC (USB Power Control)................................112 SPIx Master Mode (CKE = 0)...................................278 U1SOF (USB SOF Threshold)..................................123 SPIx Master Mode (CKE = 1)...................................279 U1STAT (USB Status)..............................................118 SPIx Slave Mode (CKE = 0).....................................280 U1TOK (USB Token)................................................122 SPIx Slave Mode (CKE = 1).....................................281 UxMODE (UARTx Mode)..........................................183 Timer1, 2, 3, 4, 5 External Clock..............................275 UxSTA (UARTx Status and Control).........................185 UART Reception.......................................................187 WDTCON (Watchdog Timer Control).......................155 UART Transmission (8-bit or 9-bit Data)..................187 Resets.................................................................................59 Timing Requirements Revision History................................................................329 CLKO and I/O...........................................................272 RTCALRM (RTC ALARM Control)....................................203 Timing Specifications I2Cx Bus Data Requirements (Master Mode)...........284 S I2Cx Bus Data Requirements (Slave Mode).............287 Serial Peripheral Interface (SPI).......................................165 Input Capture Requirements....................................276 Software Simulator (MPLAB SIM).....................................255 Output Compare Requirements................................277 Special Features...............................................................239 Simple OCx/PWM Mode Requirements...................277 SPIx Master Mode (CKE = 0) Requirements............278 T SPIx Master Mode (CKE = 1) Requirements............279 Timer1 Module..................................................................143 SPIx Slave Mode (CKE = 1) Requirements..............281 Timer2/3, Timer4/5 Modules.............................................147 SPIx Slave Mode Requirements (CKE = 0)..............280 Timing Diagrams Timing Specifications (50 MHz) 10-Bit Analog-to-Digital Conversion SPIx Master Mode (CKE = 0) Requirements............304 (ASAM = 0, SSRC<2:0> = 000)........................293 SPIx Master Mode (CKE = 1) Requirements............304 10-Bit Analog-to-Digital Conversion (ASAM = 1, SPIx Slave Mode (CKE = 1) Requirements..............305 SSRC<2:0> = 111, SAMC<4:0> = 00001)........294 SPIx Slave Mode Requirements (CKE = 0)..............305 EJTAG......................................................................300 U External Clock...........................................................269 I/O Characteristics....................................................272 UART................................................................................181 I2Cx Bus Data (Master Mode)..................................283 USB On-The-Go (OTG)....................................................103 I2Cx Bus Data (Slave Mode)....................................286 V I2Cx Bus Start/Stop Bits (Master Mode)...................283 I2Cx Bus Start/Stop Bits (Slave Mode).....................286 VCAP pin............................................................................250 Input Capture (CAPx)................................................276 Voltage Regulator (On-Chip)............................................250 OCx/PWM.................................................................277 W Output Compare (OCx).............................................277 Parallel Master Port Read.........................................296 WWW Address.................................................................341 Parallel Master Port Write.........................................297 WWW, On-Line Support.....................................................16  2011-2016 Microchip Technology Inc. DS60001168J-page 339

PIC32MX1XX/2XX 28/36/44-PIN FAMILY NOTES: DS60001168J-page 340  2011-2016 Microchip Technology Inc.

PIC32MX1XX/2XX 28/36/44-PIN FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011-2016 Microchip Technology Inc. DS60001168J-page 341

PIC32MX1XX/2XX 28/36/44-PIN FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 1XX F 032 D B T - 50 I / PT - XXX Example: PIC32MX110F032DT-I/PT: Microchip Brand General purpose PIC32, 32-bit RISC MCU with M4K® core, Architecture 32KB program memory, 44-pin, Product Groups Industrial temperature, TQFP package. Flash Memory Family Program Memory Size (KB) Pin Count Software Targeting Tape and Reel Flag (if applicable) Speed (if applicable) Temperature Range Package Pattern Flash Memory Family Architecture MX = M4K® MCU core Product Groups 1XX = General purpose microcontroller family 2XX = General purpose microcontroller family Flash Memory Family F = Flash program memory Program Memory Size 016 = 16K 032 = 32K 064 = 64K 128 = 128K 256 = 256K Pin Count B = 28-pin C = 36-pin D = 44-pin Software Targeting B = Targeted for Bluetooth® Audio Break-in devices Speed () = 40 MHz – ()indicates a blank field; package markings for 40 MHz devices do not include the Speed 50 = 50 MHz Temperature Range I = -40°C to +85°C (Industrial) V = -40°C to +105°C (V-temp) Package ML = 28-Lead (6x6 mm) QFN (Plastic Quad Flatpack) ML = 44-Lead (8x8 mm) QFN (Plastic Quad Flatpack) PT = 44-Lead (10x10x1 mm) TQFP (Plastic Thin Quad Flatpack) SO = 28-Lead (7.50 mm) SOIC (Plastic Small Outline) SP = 28-Lead (300 mil) SPDIP (Skinny Plastic Dual In-line) SS = 28-Lead (5.30 mm) SSOP (Plastic Shrink Small Outline) TL = 36-Lead (5x5 mm) VTLA (Very Thin Leadless Array) TL = 44-Lead (6x6 mm) VTLA (Very Thin Leadless Array) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2011-2016 Microchip Technology Inc. DS60001168J-page 342

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, and may be superseded by updates. It is your responsibility to dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, ensure that your application meets with your specifications. KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MICROCHIP MAKES NO REPRESENTATIONS OR MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, WARRANTIES OF ANY KIND WHETHER EXPRESS OR RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company, FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load, arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A. hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademarks of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2011-2016, Microchip Technology Incorporated, Printed in CERTIFIED BY DNV the U.S.A., All Rights Reserved. ISBN:978-1-5224-0471-2 == ISO/TS 16949 ==  2011-2016 Microchip Technology Inc. DS60001168J-page 343

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