PIC24FJ256DA210 Family Data Sheet 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)  2010 Microchip Technology Inc. DS39969B

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-235-9 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39969B-page 2  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG) Graphics Controller Features: Peripheral Features: • Three Graphics Hardware Accelerators to Facilitate • Enhanced Parallel Master Port/Parallel Slave Port Rendering of Block Copying, Text and Unpacking of (EPMP/PSP), 100-pin devices only: Compressed Data - Direct access from CPU with an Extended Data • Color Look-up Table (CLUT) with Maximum of 256 Entries Space (EDS) interface • 1/2/4/8/16 bits-per-pixel (bpp) Color Depth Set at - 4, 8 and 16-bit wide data bus Run Time - Up to 23 programmable address lines • Display Resolution Programmable According to - Up to 2 chip select lines Frame Buffer: - Up to 2 Acknowledgement lines (one per chip - Supports direct access to external memory on select) devices with EPMP - Programmable address/data multiplexing - Resolution supported is up to 480x272 @ 60Hz, - Programmable address and data Wait states 16bpp; 640x480 @ 30 Hz, 16bpp or - Programmable polarity on control signals 640x480 @ 60 Hz, 8bpp • Peripheral Pin Select: • Supports Various Display Interfaces: - Up to 44 available pins (100-pin devices) - 4/8/16-bit Monochrome STN • Three 3-Wire/4-Wire SPI modules (supports 4 Frame - 4/8/16-bit Color STN modes) - 9/12/18/24-bit Color TFT (18 and 24-bit displays • Three I2C™ modules Supporting Multi-Master/Slave are connected as 16-bit, 5-6-5 RGB color format) modes and 7-Bit/10-Bit Addressing • Four UART modules: Universal Serial Bus Features: - Supports RS-485, RS-232, LIN/J2602 protocols • USB v2.0 On-The-Go (OTG) Compliant and IrDA® • Dual Role Capable – Can act as either Host or Peripheral • Five 16-Bit Timers/Counters with Programmable • Low-Speed (1.5 Mbps) and Full-Speed (12 Mbps) Prescaler USB Operation in Host mode • Nine 16-Bit Capture Inputs, each with a Dedicated Time • Full-Speed USB Operation in Device mode Base • High-Precision PLL for USB • Nine 16-Bit Compare/PWM Outputs, each with a Dedi- • Supports up to 32 Endpoints (16 bidirectional): cated Time Base - USB module can use the internal RAM location • Hardware Real-Time Clock and Calendar (RTCC) from 0x800 to 0xFFFF as USB endpoint buffers • Enhanced Programmable Cyclic Redundancy Check • On-Chip USB Transceiver with Interface for Off-Chip (CRC) Generator Transceiver • Up to 5 External Interrupt Sources • Supports Control, Interrupt, Isochronous and Bulk Transfers • On-Chip Pull-up and Pull-Down Resistors Remappable Peripherals PIC24FJ Device Pins Program Memory (bytes) SRAM (bytes) Remappable Pins 16-Bit Timers IC/OC PWM ®UART w/IrDA SPI 2IC™ 10-Bit A/D (ch) Comparators CTMU EPMP/PSP RTCC Graphics Controller USB OTG PIC24FJ128DA106 64 128K 24K 29 5 9/9 4 3 3 16 3 Y N Y Y Y PIC24FJ256DA106 64 256K 24K 29 5 9/9 4 3 3 16 3 Y N Y Y Y PIC24FJ128DA110 100/121 128K 24K 44 5 9/9 4 3 3 24 3 Y Y Y Y Y PIC24FJ256DA110 100/121 256K 24K 44 5 9/9 4 3 3 24 3 Y Y Y Y Y PIC24FJ128DA206 64 128K 96K 29 5 9/9 4 3 3 16 3 Y N Y Y Y PIC24FJ256DA206 64 256K 96K 29 5 9/9 4 3 3 16 3 Y N Y Y Y PIC24FJ128DA210 100/121 128K 96K 44 5 9/9 4 3 3 24 3 Y Y Y Y Y PIC24FJ256DA210 100/121 256K 96K 44 5 9/9 4 3 3 24 3 Y Y Y Y Y  2010 Microchip Technology Inc. DS39969B-page 3

PIC24FJ256DA210 FAMILY High-Performance CPU Analog Features: • Modified Harvard Architecture • 10-Bit, up to 24-Channel Analog-to-Digital (A/D) • Up to 16 MIPS Operation at 32 MHz Converter at 500 ksps: • 8 MHz Internal Oscillator - Operation is possible in Sleep mode • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier - Band gap reference input feature • 32-Bit by 16-Bit Hardware Divider • Three Analog Comparators with Programmable • 16 x 16-Bit Working Register Array Input/Output Configuration • C Compiler Optimized Instruction Set Architecture • Charge Time Measurement Unit (CTMU): with Flexible Addressing modes - Supports capacitive touch sensing for touch • Linear Program Memory Addressing, up to screens and capacitive switches 12 Mbytes - Minimum time measurement setting at 100 ps • Data Memory Addressing, up to 16 Mbytes: • Available LVD Interrupt VLVD Level - 2K SFR space - 30K linear data memory Special Microcontroller Features: - 66K extended data memory - Remaining (from 16 Mbytes) memory (external) • Operating Voltage Range of 2.2V to 3.6V can be accessed using extended data Memory • 5.5V Tolerant Input (digital pins only) (EDS) and EPMP (EDS is divided into 32-Kbyte • Configurable Open-Drain Outputs on Digital I/O pages) Ports • Two Address Generation Units for Separate Read • High-Current Sink/Source (18 mA/18 mA) on all and Write Addressing of Data Memory I/O Ports • Selectable Power Management modes: Power Management: - Sleep, Idle and Doze modes with fast wake-up • Fail-Safe Clock Monitor (FSCM) Operation: • On-Chip Voltage Regulator of 1.8V - Detects clock failure and switches to on-chip, • Switch between Clock Sources in Real Time FRC oscillator • Idle, Sleep and Doze modes with Fast Wake-up and • On-Chip LDO Regulator Two-Speed Start-up • Power-on Reset (POR) and • Run Mode: 800 A/MIPS, 3.3V Typical Oscillator Start-up Timer (OST) • Sleep mode Current Down to 20 A, 3.3V Typical • Brown-out Reset (BOR) • Standby Current with 32 kHz Oscillator: 22 A, • Flexible Watchdog Timer (WDT) with On-Chip 3.3V Typical Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan Support • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Self-reprogrammable under software control - Write protection option for Configuration Words DS39969B-page 4  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY Pin Diagram (64-Pin TQFP/QFN) 0 F 8/R D1 9/RF1/CN6D N50/R HSYNC/CN62/RE4GD3/CN61/RE3GD2/CN60/RE2GD1/CN59/RE1GD0/CN58/RE0GD11/V2/SESSVLD/CN6CMPSTGD10/V/V1/VBUSSTCMPSTBUSVL ENVREGVCAPC3INA/SESSEND/CN16/RD7C3INB/CN15/RD6RP20/GPWR/CN14/RD5RP25/GCLK/CN13/RD4RP22/GEN/CN52/RD3DPH/RP23/CN51/RD2V/RP24/GD9/V/CCPCONBUSCHG 4321098765432109 VSYNC/CN63/RE5 1 6666655555555554 48 SROCS1C4O/SCLKI/T1CK/C3INC/RPI37/CN0/ GD12/SCL3/CN64/RE6 2 47 SOSCI/C3IND/CN1/RC13 GD13/SDA3/CN65/RE7 3 46 DMH/RP11/INT0/CN49/RD0 C1IND/RP21/CN8/RG6 4 45 RP12/GD7/CN56/RD11 C1INC/RP26/CN9/RG7 5 44 SCL1/RP3/GD6/CN55/RD10 C2IND/RP19/GD14/CN10/RG8 6 43 DPLN/SDA1/RP4/GD8/CN54/RD9 MCLR 7 42 RTCC/DMLN/RP2/CN53/RD8 PIC24FJXXXDAX06 C2INC/RP27/GD15/CN11/RG9 8 41 VSS(1) VSS(1) 9 40 OSCO/CLKO/CN22/RC15 VDD 10 39 OSCI/CLKI/CN23/RC12 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 11 38 VDD PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 12 37 D+/CN83/RG2 AN3/C2INA/VPIO/CN5/RB3 13 36 D-/CN84/RG3 AN2/C2INB/VMIO/RP13/CN4/RB2 14 35 VUSB PGEC1/AN1/VREF-/RP1/CN3/RB1 15 34 VBUS/RF7 PGED1/AN0/VREF+/RP0/CN2/RB0 16 33 RP16/USBID/CN71/RF3 17181920212223242526272829303132 24/RB625/RB7AVDD AVSS 26/RB827/RB98/RB109/RB11(1)VSS VDD 0/RB121/RB132/RB142/RB15D4/RF418/RF5 PGEC2/AN6/RP6/CNPGED2/AN7/RP7/RCV/CN AN8/RP8/CNAN9/RP9/CNTMS/CV/AN10/CN2REF TDO/AN11/CN2 TCK/AN12/CTEDG2/CN3TDI/AN13CTEDG1/CN3AN14/CTPLS/RP14/CN3AN15/RP29/REFO/CN1SDA2/RP10/GD4/CN17/GSCL2/RP17/GD5/CN Note 1: The back pad on QFN devices should be connected to VSS. Legend: RPn and RPIn represents remappable peripheral pins. Shaded pins indicate pins that are tolerant to up to +5.5V.  2010 Microchip Technology Inc. DS39969B-page 5

PIC24FJ256DA210 FAMILY TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN DEVICES Pin Function Pin Function 1 VSYNC/CN63/RE5 33 RP16/USBID/CN71/RF3 2 GD12/SCL3/CN64/RE6 34 VBUS/RF7 3 GD13/SDA3/CN65/RE7 35 VUSB 4 C1IND/RP21/CN8/RG6 36 D-/CN84/RG3 5 C1INC/RP26/CN9/RG7 37 D+/CN83/RG2 6 C2IND/RP19/GD14/CN10/RG8 38 VDD 7 MCLR 39 OSCI/CLKI/CN23/RC12 8 C2INC/RP27/GD15/CN11/RG9 40 OSCO/CLKO/CN22/RC15 9 VSS 41 VSS 10 VDD 42 RTCC/DMLN/RP2/CN53/RD8 11 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 43 DPLN/SDA1/RP4/GD8/CN54/RD9 12 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 44 SCL1/RP3/GD6/CN55/RD10 13 AN3/C2INA/VPIO/CN5/RB3 45 RP12/GD7/CN56/RD11 14 AN2/C2INB/VMIO/RP13/CN4/RB2 46 DMH/RP11/INT0/CN49/RD0 15 PGEC1/AN1/VREF-/RP1/CN3/RB1 47 SOSCI/C3IND/CN1/RC13 16 PGED1/AN0/VREF+/RP0/CN2/RB0 48 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 17 PGEC2/AN6/RP6/CN24/RB6 49 VCPCON/RP24/GD9/VBUSCHG/CN50/RD1 18 PGED2/AN7/RP7/RCV/CN25/RB7 50 DPH/RP23/CN51/RD2 19 AVDD 51 RP22/GEN/CN52/RD3 20 AVSS 52 RP25/GCLK/CN13/RD4 21 AN8/RP8/CN26/RB8 53 RP20/GPWR/CN14/RD5 22 AN9/RP9/CN27/RB9 54 C3INB/CN15/RD6 23 TMS/CVREF/AN10/CN28/RB10 55 C3INA/SESSEND/CN16/RD7 24 TDO/AN11/CN29/RB11 56 VCAP 25 VSS 57 ENVREG 26 VDD 58 GD10/VBUSST/VCMPST1/VBUSVLD/CN68/RF0 27 TCK/AN12/CTEDG2/CN30/RB12 59 GD11/VCMPST2/SESSVLD/CN69/RF1 28 TDI/AN13/CTEDG1/CN31/RB13 60 GD0/CN58/RE0 29 AN14/CTPLS/RP14/CN32/RB14 61 GD1/CN59/RE1 30 AN15/RP29/REFO/CN12/RB15 62 GD2/CN60/RE2 31 SDA2/RP10/GD4/CN17/RF4 63 GD3/CN61/RE3 32 SCL2/RP17/GD5/CN18/RF5 64 HSYNC/CN62/RE4 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. DS39969B-page 6  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY Pin Diagram (100-Pin TQFP) 0 F R PMD4/CN62/RE4PMD3/CN61/RE3PMD2/CN60/RE2HSYNC/CN80/RG13V/CN79/RG12SYNCPMA16/CN81/RG14PMD1/CN59/RE1PMD0/CN58/RE0AN22/PMA17/CN40/RA7AN23/GEN/CN39/RA6PMD8/CN77/RG0PMD9/CN78/RG1V2/SESSVLD/PMD10/CN69/RF1CMPSTV/V1/V/PMD11/CN68/BUSSTCMPSTBUSVLD ENVREGVCAPC3INA/SESSEND/PMD15/CN16/RD7C3INB/PMD14/CN15/RD6RP20/PMRD/CN14/RD5RP25/PMWR/CN13/RD4PMD13/CN19/RD13RPI42/PMD12/CN57/RD12RP22/PMBE0/CN52/RD3DPH/RP23/GD11/PMACK1/CN51/RD2V/RP24/GD7/V/CN50/RD1CPCONBUSCHG GCLK/CN82/RG15 1 100999897969594939291908988878685848382818079787776 75 VSS SOSCO/SCLKI/TICK/C3INC/ VDD 2 74 RPI37/CN0/RC14 PMD5/CN63/RE5 3 73 SOSCI/C3IND/CN1/RC13 SCL3/PMD6/CN64/RE6 4 72 DMH/RP11/INT0/CN49/RD0 SDA3/PMD7/CN65/RE7 5 71 RP12/PMA14/PMCS1/CN56/RD11 RP3/PMA15/PMCS2/CN55/ RPI38/GD0/CN45/RC1 6 70 RD10 RPI39/GD8/CN46/RC2 7 69 DRPDL9N/RP4/GD10/PMACK2/CN54/ RPI40/GD1/CN47/RC3 8 68 DMLN/RTCC/RP2/CN53/RD8 AN16/RPI41/PMCS2/PMA22/CN48/RC4 9 67 SDA1/RPI35/PMBE1/CN44/RA15 AN17/C1IND/RP21/PMA5/PMA18/CN8/RG6 10 66 SCCNL413//RRPAI1346/PMA22/PMCS2/ AN18/C1INC/RP26/PMA4/PMA20/CN9/RG7 11 65 VSS AN19/C2IND/RP19/PMA3/PMA21/CN10/RG8 12 PIC24FJXXXDAX10 64 OSCO/CLKO/CN22/RC15 MCLR 13 63 OSCI/CLKI/CN23/RC12 AN20/C2INC/RP27/PMA2/CN11/RG9 14 62 VDD VSS 15 61 TDO/CN38/RA5 VDD 16 60 TDI/PMA21/PMA3/CN37/RA4 TMS/CN33/RA0 17 59 SDA2/PMA20/PMA4/CN36/RA3 RPI33/PMCS1/CN66/RE8 18 58 SCL2/CN35/RA2 AN21/RPI34/PMA19/CN67/RE9 19 57 D+/CN83/RG2 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 20 56 D-/CN84/RG3 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 21 55 VUSB AN3/C2INA/GD5/VPIO/CN5/RB3 22 54 VBUS/CN73/RF7 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 23 53 RP15/GD9/CN74/RF8 PGEC1/AN1/VREF-/RP1/CN3/RB1 24 52 RP30/GD3/CN70/RF2 PGED1/AN0/VREF+/RP0/CN2/RB0 25 51 RP16/USBID/CN71/RF3 26272829303132333435363738394041424344454647484950 PGEC2/AN6/RP6/CN24/RB6GED2/AN7/RP7/RCV/GPWR/CN25/RB7V-/PMA7/CN41/RA9REFV+/PMA6/CN42/RA10REF AVDD AVSS AN8/RP8/GD12/CN26/RB8GD13/AN9/RP9/GD13/CN27/RB9AN10/CV/PMA13/CN28/RB10REF AN11/PMA12/CN29/RB11VSS VDDTCK/CN34/RA1RP31/GD2/CN76/RF13RPI32/PMA18/PMA5/CN75/RF12AN12/PMA11/CTEDG2/CN30/RB12AN13/PMA10/CTEDG1/CN31/RB13AN14/CTPLS/RP14/PMA1/CN32/RB14AN15/REFO/RP29/PMA0/CN12/RB15 VSS VDD RPI43/GD14/CN20/RD14RP5/GD15/CN21/RD15RP10/PMA9/CN17/RF4RP17/PMA8/CN18/RF5 P Legend: RPn and RPIn represent remappable peripheral pins. Shaded pins indicate pins that are tolerant to up to +5.5V.  2010 Microchip Technology Inc. DS39969B-page 7

PIC24FJ256DA210 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Pin Function Pin Function 1 GCLK/CN82/RG15 41 AN12/PMA11/CTEDG2/CN30/RB12 2 VDD 42 AN13/PMA10/CTEDG1/CN31/RB13 3 PMD5/CN63/RE5 43 AN14/CTPLS/RP14/PMA1/CN32/RB14 4 SCL3/PMD6/CN64/RE6 44 AN15/REFO/RP29/PMA0/CN12/RB15 5 SDA3/PMD7/CN65/RE7 45 VSS 6 RPI38/GD0/CN45/RC1 46 VDD 7 RPI39/GD8/CN46/RC2 47 RPI43/GD14/CN20/RD14 8 RPI40/GD1/CN47/RC3 48 RP5/GD15/CN21/RD15 9 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 49 RP10/PMA9/CN17/RF4 10 AN17/C1IND/RP21/PMA5/PMA18(2)/CN8/RG6 50 RP17/PMA8/CN18/RF5 11 AN18/C1INC/RP26/PMA4/PMA20(2)/CN9/RG7 51 RP16/USBID/CN71/RF3 12 AN19/C2IND/RP19/PMA3/PMA21(2)/CN10/RG8 52 RP30/GD3/CN70/RF2 13 MCLR 53 RP15/GD9/CN74/RF8 14 AN20/C2INC/RP27/PMA2/CN11/RG9 54 VBUS/CN73/RF7 15 VSS 55 VUSB 16 VDD 56 D-/CN84/RG3 17 TMS/CN33/RA0 57 D+/CN83/RG2 18 RPI33/PMCS1/CN66/RE8 58 SCL2/CN35/RA2 19 AN21/RPI34/PMA19/CN67/RE9 59 SDA2/PMA20/PMA4(2)/CN36/RA3 20 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 60 TDI/PMA21/PMA3(2)/CN37/RA4 21 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 61 TDO/CN38/RA5 22 AN3/C2INA/GD5/VPIO/CN5/RB3 62 VDD 23 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 63 OSCI/CLKI/CN23/RC12 24 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 64 OSCO/CLKO/CN22/RC15 25 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 65 VSS 26 PGEC2/AN6/RP6/CN24/RB6 66 SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 27 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 67 SDA1/RPI35/PMBE1/CN44/RA15 28 VREF-/PMA7/CN41/RA9 68 DMLN/RTCC/RP2/CN53/RD8 29 VREF+/PMA6/CN42/RA10 69 DPLN/RP4/GD10/PMACK2/CN54/RD9 30 AVDD 70 RP3/PMA15/PMCS2(3)/CN55/RD10 31 AVSS 71 RP12/PMA14/PMCS1(3)/CN56/RD11 32 AN8/RP8/GD12/CN26/RB8 72 DMH/RP11/INT0/CN49/RD0 33 AN9/RP9/GD13/CN27/RB9 73 SOSCI/C3IND/CN1/RC13 34 AN10/CVREF/PMA13/CN28/RB10 74 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 35 AN11/PMA12/CN29/RB11 75 VSS 36 VSS 76 VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 37 VDD 77 DPH/RP23/GD11/PMACK1/CN51/RD2 38 TCK/CN34/RA1 78 RP22/PMBE0/CN52/RD3 39 RP31/GD2/CN76/RF13 79 RPI42/PMD12/CN57/RD12 40 RPI32/PMA18/PMA5(2)/CN75/RF12 80 PMD13/CN19/RD13 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Note 1: Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. 3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’. DS39969B-page 8  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Pin Function Pin Function 81 RP25/PMWR/CN13/RD4 91 AN23/GEN/CN39/RA6 82 RP20/PMRD/CN14/RD5 92 AN22/PMA17/CN40/RA7 83 C3INB/PMD14/CN15/RD6 93 PMD0/CN58/RE0 84 C3INA/SESSEND/PMD15/CN16/RD7 94 PMD1/CN59/RE1 85 VCAP 95 PMA16/CN81/RG14 86 ENVREG 96 VSYNC/CN79/RG12 87 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 97 HSYNC/CN80/RG13 88 VCMPST2/SESSVLD/PMD10/CN69/RF1 98 PMD2/CN60/RE2 89 PMD9/CN78/RG1 99 PMD3/CN61/RE3 90 PMD8/CN77/RG0 100 PMD4/CN62/RE4 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Note 1: Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. 3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.  2010 Microchip Technology Inc. DS39969B-page 9

PIC24FJ256DA210 FAMILY Pin Diagram – Top View (121-Pin BGA)(1) 1 2 3 4 5 6 7 8 9 10 11 A RE4 RE3 HSYNC/ RE0 RG0 RF1 ENVREG N/C RD12 GD11/ GD7/ RG13 RD2 RD1 B N/C GCLK/ RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14 RG15 C RE6 VDD VSYNC/ RG14 GEN/ N/C RD7 RD4 VDD RC13 RD11 RG12 RA6 D GD0/ RE7 RE5 VSS VSS N/C RD6 RD13 RD0 n/c RD10 RC1 E RC4 GD1/ RG6 GD8/ VDD RG1 N/C RA15 RD8 GD10/ RA14 RC3 RC2 RD9 F MCLR RG8 RG9 RG7 VSS n/c N/C VDD OSCI/ VSS OSCO/ RC12 RC15 G RE8 RE9 RA0 N/C VDD VSS VSS N/C RA5 RA3 RA4 H PGEC3/ PGED3/ VSS VDD N/C VDD n/c VBUS/ VUSB D+/RG2 RA2 RB5 GD4/RB4 RF7 J GD5/ GD6/ PGED2/RB7AVDD RB11 RA1 RB12 N/C N/C GD9/RF8 D-/RG3 RB3 RB2 GPWR K PGEC1/ PGED1/ RA10 GD12/ N/C RF12 RB14 VDD GD15/ USBID/ GD3/ RB1 RB0 RB8 RD15 RF3 RF2 L PGEC2/ RA9 AVSS GD13/ RB10 GD2/ RB13 RB15 GD14/ RF4 RF5 RB6 RB9 RF13 RD14 Note 1: See Table3 for complete functional pinout descriptions. Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Shaded pins indicate pins tolerant to up to +5.5V. DS39969B-page 10  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES Pin Function Pin Function A1 PMD4/CN62/RE4 E5 VDD A2 PMD3/CN61/RE3 E6 PMD9/CN78/RG1 A3 HSYNC/CN80/RG13 E7 N/C A4 PMD0/CN58/RE0 E8 SDA1/RPI35/PMBE1/CN44/RA15 A5 PMD8/CN77/RG0 E9 DMLN/RTCC/RP2/CN53/RD8 A6 VCMPST2/SESSVLD/PMD10/CN69/RF1 E10 DPLN/RP4/GD10/PMACK2/CN54/RD9 A7 ENVREG E11 SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 A8 N/C F1 MCLR A9 RPI42/PMD12/CN57/RD12 F2 AN19/C2IND/RP19/PMA3/PMA21(2)/CN10/RG8 A10 DPH/RP23/GD11/PMACK1/CN51/RD2 F3 AN20/C2INC/RP27/PMA2/CN11/RG9 A11 VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 F4 AN18/C1INC/RP26/PMA4/PMA20(2)/CN9/RG7 B1 N/C F5 VSS B2 GCLK/CN82/RG15 F6 N/C B3 PMD2/CN60/RE2 F7 N/C B4 PMD1/CN59/RE1 F8 VDD B5 AN22/PMA17/CN40/RA7 F9 OSCI/CLKI/CN23/RC12 B6 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 F10 VSS B7 VCAP F11 OSCO/CLKO/CN22/RC15 B8 RP20/PMRD/CN14/RD5 G1 RPI33/PMCS1/CN66/RE8 B9 RP22/PMBE0/CN52/RD3 G2 AN21/RPI34/PMA19/CN67/RE9 B10 VSS G3 TMS/CN33/RA0 B11 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 G4 N/C C1 SCL3/PMD6/CN64/RE6 G5 VDD C2 VDD G6 VSS C3 VSYNC/CN79/RG12 G7 VSS C4 PMA16/CN81/RG14 G8 N/C C5 AN23/GEN/CN39/RA6 G9 TDO/CN38/RA5 C6 N/C G10 SDA2/PMA20/PMA4(2)/CN36/RA3 C7 C3INA/SESSEND/PMD15/CN16/RD7 G11 TDI/PMA21/PMA3(2)/CN37/RA4 C8 RP25/PMWR/CN13/RD4 H1 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 C9 VDD H2 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 C10 SOSCI/C3IND/CN1/RC13 H3 VSS C11 RP12/PMA14/PMCS1(3)/CN56/RD11 H4 VDD D1 RPI38/GD0/CN45/RC1 H5 N/C D2 SDA3/PMD7/CN65/RE7 H6 VDD D3 PMD5/CN63/RE5 H7 N/C D4 VSS H8 VBUS/CN73/RF7 D5 VSS H9 VUSB D6 N/C H10 D+/CN83/RG2 D7 C3INB/PMD14/CN15/RD6 H11 SCL2/CN35/RA2 D8 PMD13/CN19/RD13 J1 AN3/C2INA/GD5/VPIO/CN5/RB3 D9 DMH/RP11/INT0/CN49/RD0 J2 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 D10 N/C J3 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 D11 RP3/PMA15/PMCS2(3)/CN55/RD10 J4 AVDD E1 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 J5 AN11/PMA12/CN29/RB11 E2 RPI40/GD1/CN47/RC3 J6 TCK/CN34/RA1 E3 AN17/C1IND/RP21/PMA5/PMA18(2)/CN8/RG6 J7 AN12/PMA11/CTEDG2/CN30/RB12 E4 RPI39/GD8/CN46/RC2 J8 N/C Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Note 1: Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. 3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’.  2010 Microchip Technology Inc. DS39969B-page 11

PIC24FJ256DA210 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES Pin Function Pin Function J9 N/C L1 PGEC2/AN6/RP6/CN24/RB6 J10 RP15/GD9/CN74/RF8 L2 VREF-(1)/PMA7/CN41/RA9 J11 D-/CN84/RG3 L3 AVSS K1 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 L4 AN9/RP9/GD13/CN27/RB9 K2 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 L5 AN10/CVREF/PMA13/CN28/RB10 K3 VREF+(1)/PMA6/CN42/RA10 L6 RP31/GD2/CN76/RF13 K4 AN8/RP8/GD12/CN26/RB8 L7 AN13/PMA10/CTEDG1/CN31/RB13 K5 N/C L8 AN15/REFO/RP29/PMA0/CN12/RB15 K6 RPI32/PMA18/PMA5(2)/CN75/RF12 L9 RPI43/GD14/CN20/RD14 K7 AN14/CTPLS/RP14/PMA1/CN32/RB14 L10 RP10/PMA9/CN17/RF4 K8 VDD L11 RP17/GD5/PMA8/SCL2/CN18/RF5 K9 RP5/GD15/CN21/RD15 — — K10 RP16/USBID/CN71/RF3 — — K11 RP30/GD3/CN70/RF2 — — Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Note 1: Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. 2: Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. 3: Pin assignment for PMCSx when CSF<1:0> is not equal to ‘00’. DS39969B-page 12  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY Table of Contents 1.0 Device Overview........................................................................................................................................................................15 2.0 Guidelines for Getting Started with 16-bit Microcontrollers........................................................................................................33 3.0 CPU ...........................................................................................................................................................................................39 4.0 Memory Organization.................................................................................................................................................................45 5.0 Flash Program Memory..............................................................................................................................................................81 6.0 Resets........................................................................................................................................................................................87 7.0 Interrupt Controller.....................................................................................................................................................................93 8.0 Oscillator Configuration............................................................................................................................................................141 9.0 Power-Saving Features............................................................................................................................................................155 10.0 I/O Ports...................................................................................................................................................................................157 11.0 Timer1......................................................................................................................................................................................189 12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................191 13.0 Input Capture with Dedicated Timers.......................................................................................................................................197 14.0 Output Compare with Dedicated Timers..................................................................................................................................201 15.0 Serial Peripheral Interface (SPI)...............................................................................................................................................211 16.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................223 17.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................231 18.0 Universal Serial Bus with On-The-Go Support (USB OTG).....................................................................................................239 19.0 Enhanced Parallel Master Port (EPMP)...................................................................................................................................273 20.0 Real-Time Clock and Calendar (RTCC) ..................................................................................................................................285 21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator........................................................................................297 22.0 Graphics Controller Module (GFX)...........................................................................................................................................305 23.0 10-Bit High-Speed A/D Converter............................................................................................................................................325 24.0 Triple Comparator Module........................................................................................................................................................335 25.0 Comparator Voltage Reference................................................................................................................................................341 26.0 Charge Time Measurement Unit (CTMU)................................................................................................................................343 27.0 Special Features......................................................................................................................................................................347 28.0 Development Support...............................................................................................................................................................359 29.0 Instruction Set Summary..........................................................................................................................................................363 30.0 Electrical Characteristics..........................................................................................................................................................371 31.0 Packaging Information..............................................................................................................................................................387 Appendix A: Revision History.............................................................................................................................................................397 Index................................................................................................................................................................................................. 399 The Microchip Web Site.....................................................................................................................................................................405 Customer Change Notification Service..............................................................................................................................................405 Customer Support..............................................................................................................................................................................405 Reader Response..............................................................................................................................................................................406 Product Identification System............................................................................................................................................................407  2010 Microchip Technology Inc. DS39969B-page 13

PIC24FJ256DA210 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39969B-page 14  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 1.0 DEVICE OVERVIEW • Doze Mode Operation: When timing-sensitive applications, such as serial communications, This document contains device-specific information for require the uninterrupted operation of peripherals, the following devices: the CPU clock speed can be selectively reduced, allowing incremental power savings without • PIC24FJ128DA106 • PIC24FJ128DA206 missing a beat. • PIC24FJ256DA106 • PIC24FJ256DA206 • Instruction-Based Power-Saving Modes: The • PIC24FJ128DA110 • PIC24FJ128DA210 microcontroller can suspend all operations, or • PIC24FJ256DA110 • PIC24FJ256DA210 selectively shut down its core while leaving its peripherals active with a single instruction in The PIC24FJ256DA210 family enhances on the exist- software. ing line of Microchip‘s 16-bit microcontrollers, adding a new Graphics Controller (GFX) module to interface 1.1.3 OSCILLATOR OPTIONS AND with a graphical LCD display and also adds large data FEATURES RAM, up to 96 Kbytes. The PIC24FJ256DA210 family allows the CPU to fetch data directly from an external All of the devices in the PIC24FJ256DA210 family offer memory device using the EPMP module. five different oscillator options, allowing users a range of choices in developing application hardware. These 1.1 Core Features include: • Two Crystal modes using crystals or ceramic 1.1.1 16-BIT ARCHITECTURE resonators. Central to all PIC24F devices is the 16-bit modified • Two External Clock modes offering the option of a Harvard architecture, first introduced with Microchip’s divide-by-2 clock output. dsPIC® Digital Signal Controllers (DSCs). The PIC24F • A Fast Internal Oscillator (FRC) with a nominal CPU core offers a wide range of enhancements, such 8MHz output, which can also be divided under as: software control to provide clock speeds as low as • 16-bit data and 24-bit address paths with the 31kHz. ability to move information between data and • A Phase Lock Loop (PLL) frequency multiplier, memory spaces available to the external oscillator modes and the • Linear addressing of up to 12 Mbytes (program FRC oscillator, which allows clock speeds of up to space) and 32 Kbytes (data) 32MHz. • A 16-element working register array with built-in • A separate Low-Power Internal RC Oscillator software stack support (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive • A 17 x 17 hardware multiplier with support for applications. integer math • Hardware support for 32 by 16-bit division The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor • An instruction set that supports multiple (FSCM). This option constantly monitors the main clock addressing modes and is optimized for high-level source against a reference signal provided by the inter- languages, such as ‘C’ nal oscillator and enables the controller to switch to the • Operational performance up to 16 MIPS internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256DA210 family 1.1.4 EASY MIGRATION incorporate a range of features that can significantly Regardless of the memory size, all devices share the reduce power consumption during operation. Key same rich set of peripherals, allowing for a smooth items include: migration path as applications grow and evolve. The • On-the-Fly Clock Switching: The device clock consistent pinout scheme used throughout the entire can be changed under software control to the family also aids in migrating from one device to the next Timer1 source or the internal, low-power RC larger, or even in jumping from 64-pin to 100-pin oscillator during operation, allowing the user to devices. incorporate power-saving ideas into their software The PIC24F family is pin compatible with devices in the designs. dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.  2010 Microchip Technology Inc. DS39969B-page 15

PIC24FJ256DA210 FAMILY 1.2 Graphics Controller 1.4 Other Special Features With the PIC24FJ256DA210 family of devices, • Peripheral Pin Select: The Peripheral Pin Select Microchip introduces the Graphics Controller module, (PPS) feature allows most digital peripherals to be which acts as an interface between the CPU (mainly mapped over a fixed set of digital I/O pins. Users through SFRs) and a display. On-board RAM is pro- may independently map the input and/or output of vided for display buffer, scratch areas, images and any one of the many digital peripherals to any one fonts. In some cases, the RAM requirements for the of the I/O pins. display used exceeds the on-board RAM; external • Communications: The PIC24FJ256DA210 family memory connected through EPMP can be used. incorporates a range of serial communication This module provides acceleration for drawing points, peripherals to handle a range of application vertical and horizontal lines, rectangles, copying rect- requirements. There are three independent I2C™ angles between different locations on screen, drawing modules that support both Master and Slave text and decompressing compressed data. modes of operation. Devices also have, through the PPS feature, four independent UARTs with 1.3 USB On-The-Go built-in IrDA® encoders/decoders and three SPI modules. The USB On-The-Go (USB OTG) module provides • Analog Features: All members of the on-chip functionality as a target device compatible with PIC24FJ256DA210 family include a 10-bit A/D the USB 2.0 standard, as well as limited stand-alone Converter (ADC) module and a triple comparator functionality as a USB embedded host. By implement- module. The ADC module incorporates program- ing USB Host Negotiation Protocol (HNP), the module mable acquisition time, allowing for a channel to can also dynamically switch between device and host be selected and a conversion to be initiated operation, allowing for a much wider range of versatile without waiting for a sampling period, and faster USB enabled applications on a microcontroller sampling speeds. The comparator module platform. includes three analog comparators that are In addition to USB host functionality, configurable for a wide range of operations. PIC24FJ256DA210 family devices provide a true • CTMU Interface: In addition to their other analog single chip USB solution, including an on-chip features, members of the PIC24FJ256DA210 transceiver and voltage regulator, and a voltage boost family include the CTMU interface module. This generator for sourcing bus power during host provides a convenient method for precision time operations. measurement and pulse generation, and can serve as an interface for capacitive sensors. • Enhanced Parallel Master/Parallel Slave Port: There are general purpose I/O ports, which can be configured for parallel data communications. In this mode, the device can be master or slave on the communication bus. 4-bit, 8-bit and 16-bit data transfers, with up to 23 external address lines are supported in Master modes. • Real-Time Clock and Calendar: (RTCC) This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. DS39969B-page 16  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 1.5 Details on Individual Family 5. Available remappable pins (29 pins on Members PIC24FJXXXDAX06 devices and 44 pins on PIC24FJXXXDAX10 devices). Devices in the PIC24FJ256DA210 family are available 6. Analog channels for ADC (16 channels for in 64-pin and 100-pin packages. The general block PIC24FJXXXDAX06 devices and 24 channels diagram for all devices is shown in Figure1-1. for PIC24FJxxxDAx10 devices). The devices are differentiated from each other in seven 7. EPMP module (available in PIC24FJXXXDAX10 ways: devices and not in PIC24FJXXXDAX06 devices). 1. Flash program memory (128 Kbytes for All other features for devices in this family are identical. PIC24FJ128DAXXX devices and 256 Kbytes These are summarized in Table1-1 and Table1-2. for PIC24FJ256DAXXX devices). A list of the pin features available on the 2. Data memory (24 Kbytes for PIC24FJXXXDA1XX PIC24FJ256DA210 family devices, sorted by function, devices, and 96 Kbytes for PIC24FJXXXDA2XX is shown in Table1-1. Note that this table shows the pin devices). location of individual peripheral features and not how 3. Available I/O pins and ports (52 pins on 6 ports they are multiplexed on the same pin. This information for PIC24FJXXXDAX06 devices and 84 pins on is provided in the pinout diagrams in the beginning of 7 ports for PIC24FJXXXDAX10 devices). the data sheet. Multiplexed features are sorted by the 4. Available Interrupt-on-Change Notification (ICN) priority given to a feature, with the highest priority inputs (52 on PIC24FJXXXDAx06 devices and peripheral being listed first. 84 on PIC24FJXXXDAX10 devices).  2010 Microchip Technology Inc. DS39969B-page 17

PIC24FJ256DA210 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256DA210 FAMILY: 64-PIN Features PIC24FJ128DA106 PIC24FJ256DA106 PIC24FJ128DA206 PIC24FJ256DA206 Operating Frequency DC – 32 MHz Program Memory (bytes) 128K 256K 128K 256K Program Memory (instructions) 44,032 87,552 44,032 87,552 Data Memory (bytes) 24K 96K Interrupt Sources (soft vectors/ 65 (61/4) NMI traps) I/O Ports Ports B, C, D, E, F, G Total I/O Pins 52 Remappable Pins 29 (28 I/O, 1 Input only) Timers: Total Number (16-bit) 5(1) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 52 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 3 Parallel Communications No (EPMP/PSP) JTAG Boundary Scan Yes 10-Bit Analog-to-Digital Converter 16 (ADC) Module (input channels) Analog Comparators 3 CTMU Interface Yes USB OTG Yes Graphics Controller Yes Resets (and Delays) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 64-Pin TQFP and QFN Note 1: Peripherals are accessible through remappable pins. DS39969B-page 18  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256DA210 FAMILY: 100-PIN DEVICES Features PIC24FJ128DA110 PIC24FJ256DA110 PIC24FJ128DA210 PIC24FJ256DA210 Operating Frequency DC – 32 MHz Program Memory (bytes) 128K 256K 128K 256K Program Memory (instructions) 44,032 87,552 44,032 87,552 Data Memory (bytes) 24K 96K Interrupt Sources (soft vectors/NMI 66 (62/4) traps) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 84 Remappable Pins 44 (32 I/O, 12 input only) Timers: Total Number (16-bit) 5(1) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 84 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 3 Parallel Communications (EPMP/PSP) Yes JTAG Boundary Scan Yes 10-Bit Analog-to-Digital Converter 24 (ADC) Module (input channels) Analog Comparators 3 CTMU Interface Yes USB OTG Yes Graphics Controller Yes Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 100-Pin TQFP and 121-Pin BGA Note 1: Peripherals are accessible through remappable pins.  2010 Microchip Technology Inc. DS39969B-page 19

PIC24FJ256DA210 FAMILY FIGURE 1-1: PIC24FJ256DA210 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 8 16 16 (12 I/O) EDS and Table Data Latch Data Access DataRAM Control Block PCH PCL Up to 0x7FFF 23 Program Counter Address PORTB Stack Repeat Latch Control Control Logic Logic (16 I/O) 16 23 16 Address Latch Read AGU Write AGU Program Memory/ PORTC(1) Extended Data Space (8 I/O) Data Latch Address Bus EA MUX 16 a 24 Dat 16 16 PORTD(1) al Inst Latch Liter (16 I/O) Inst Register Instruction Decode and PORTE(1) Control Divide OSCO/CLKO Control Signals Support 16 x 16 (10 I/O) OSCI/CLKI 17x17 W Reg Array Timing Power-up Multiplier Generation Timer Oscillator REFO FRC/LPRC Start-up Timer PORTF(1) Oscillators Power-on 16-Bit ALU Reset (10 I/O) 16 Precision Band Gap Watchdog Reference Timer ENVREG LVD & BOR Voltage Regulator PORTG(1) (12 I/O) VCAP VDD,VSS MCLR 10-Bit Timer1 Timer2/3(2) Timer4/5(2) RTCC Comparators(2) USB OTG ADC EPMP/PSP(3) 1-I9C(2) OC1-/P9(W2)M ICNs(1) 1/S2/P3I(2) 1I/22C/3™ 1/U2A/3R/4T(2) CTMU(2) GCoranptrhoilclesr Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table1-1 for specific implementations by pin count. 2: These peripheral I/Os are only accessible through remappable pins. 3: Not available on 64-pin devices (PIC24FJxxxDAx06). DS39969B-page 20  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA AN0 16 25 K2 I ANA AN1 15 24 K1 I ANA AN2 14 23 J2 I ANA AN3 13 22 J1 I ANA AN4 12 21 H2 I ANA AN5 11 20 H1 I ANA AN6 17 26 L1 I ANA AN7 18 27 J3 I ANA AN8 21 32 K4 I ANA AN9 22 33 L4 I ANA AN10 23 34 L5 I ANA AN11 24 35 J5 I ANA A/D Analog Inputs. AN12 27 41 J7 I ANA AN13 28 42 L7 I ANA AN14 29 43 K7 I ANA AN15 30 44 L8 I ANA AN16 — 9 E1 I ANA AN17 — 10 E3 I ANA AN18 — 11 F4 I ANA AN19 — 12 F2 I ANA AN20 — 14 F3 I ANA AN21 — 19 G2 I ANA AN22 — 92 B5 I ANA AN23 — 91 C5 I ANA AVDD 19 30 J4 P — Positive Supply for Analog modules. AVSS 20 31 L3 P — Ground Reference for Analog modules. C1INA 11 20 H1 I ANA Comparator 1 Input A. C1INB 12 21 H2 I ANA Comparator 1 Input B. C1INC 5 11 F4 I ANA Comparator 1 Input C. C1IND 4 10 E3 I ANA Comparator 1 Input D. C2INA 13 22 J1 I ANA Comparator 2 Input A. C2INB 14 23 J2 I ANA Comparator 2 Input B. C2INC 8 14 F3 I ANA Comparator 2 Input C. C2IND 6 12 F2 I ANA Comparator 2 Input D. C3INA 55 84 C7 I ANA Comparator 3 Input A. C3INB 54 83 D7 I ANA Comparator 3 Input B. C3INC 48 74 B11 I ANA Comparator 3 Input C. C3IND 47 73 C10 I ANA Comparator 3 Input D. CLKI 39 63 F9 I ST Main Clock Input Connection. CLKO 40 64 F11 O — System Clock Output. Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 21

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA CN0 48 74 B11 I ST CN1 47 73 C10 I ST CN2 16 25 K2 I ST CN3 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST CN9 5 11 F4 I ST CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST CN14 53 82 B8 I ST CN15 54 83 D7 I ST CN16 55 84 C7 I ST CN17 31 49 L10 I ST CN18 32 50 L11 I ST CN19 — 80 D8 I ST Interrupt-on-Change Inputs. CN20 — 47 L9 I ST CN21 — 48 K9 I ST CN22 40 64 F11 I ST CN23 39 63 F9 I ST CN24 17 26 L1 I ST CN25 18 27 J3 I ST CN26 21 32 K4 I ST CN27 22 33 L4 I ST CN28 23 34 L5 I ST CN29 24 35 J5 I ST CN30 27 41 J7 I ST CN31 28 42 L7 I ST CN32 29 43 K7 I ST CN33 — 17 G3 I ST CN34 — 38 J6 I ST CN35 — 58 H11 I ST CN36 — 59 G10 I ST CN37 — 60 G11 I ST CN38 — 61 G9 I ST CN39 — 91 C5 I ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. DS39969B-page 22  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA CN40 — 92 B5 I ST CN41 — 28 L2 I ST CN42 — 29 K3 I ST CN43 — 66 E11 I ST CN44 — 67 E8 I ST CN45 — 6 D1 I ST CN46 — 7 E4 I ST CN47 — 8 E2 I ST CN48 — 9 E1 I ST CN49 46 72 D9 I ST CN50 49 76 A11 I ST CN51 50 77 A10 I ST CN52 51 78 B9 I ST CN53 42 68 E9 I ST CN54 43 69 E10 I ST CN55 44 70 D11 I ST CN56 45 71 C11 I ST CN57 — 79 A9 I ST CN58 60 93 A4 I ST CN59 61 94 B4 I ST Interrupt-on-Change Inputs. CN60 62 98 B3 I ST CN61 63 99 A2 I ST CN62 64 100 A1 I ST CN63 1 3 D3 I ST CN64 2 4 C1 I ST CN65 3 5 D2 I ST CN66 — 18 G1 I ST CN67 — 19 G2 I ST CN68 58 87 B6 I ST CN69 59 88 A6 I ST CN70 — 52 K11 I ST CN71 33 51 K10 I ST CN73 — 54 H8 I ST CN74 — 53 J10 I ST CN75 — 40 K6 I ST CN76 — 39 L6 I ST CN77 — 90 A5 I ST CN78 — 89 E6 I ST CN79 — 96 C3 I ST CN80 — 97 A3 I ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 23

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA CN81 — 95 C4 I ST CN82 — 1 B2 I ST Interrupt-on-Change Inputs. CN83 37 57 H10 I ST CN84 36 56 J11 I ST CTEDG1 28 42 L7 I ANA CTMU External Edge Input 1. CTEDG2 27 41 J7 I ANA CTMU External Edge Input 2. CTPLS 29 43 K7 O — CTMU Pulse Output. CVREF 23 34 L5 O — Comparator Voltage Reference Output. D+ 37 57 H10 I/O — USB Differential Plus Line (internal transceiver). D- 36 56 J11 I/O — USB Differential Minus Line (internal transceiver). DMH 46 72 D9 O — D- External Pull-up Control Output. DMLN 42 68 E9 O — D- External Pull-down Control Output. DPH 50 77 A10 O — D+ External Pull-up Control Output. DPLN 43 69 E10 O — D+ External Pull-down Control Output. ENVREG 57 86 J7 I ST Voltage Regulator Enable. GCLK 52 1 B2 O — Graphics Display Pixel Clock. GD0 60 6 D1 O — GD1 61 8 E2 O — GD2 62 39 L6 O — GD3 63 52 K11 O — GD4 31 21 H2 O — GD5 32 22 J1 O — GD6 44 23 J2 O — GD7 45 76 A11 O — Graphics Controller Data Output. GD8 43 7 E4 O — GD9 49 53 J10 O — GD10 58 69 E10 O — GD11 59 77 A10 O — GD12 2 32 K4 O — GD13 3 33 L4 O — GD14 6 47 L9 O — GD15 8 48 K9 O — GEN 51 91 C5 O — Graphics Display Enable Output. GPWR 53 27 J3 O — Graphics Display Power System Enable. HSYNC 64 97 A3 O — Graphics Display Horizontal Sync Pulse. INT0 46 72 D9 I ST External Interrupt Input. MCLR 7 13 F1 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 39 63 F9 I ANA Main Oscillator Input Connection. OSCO 40 64 F11 O ANA Main Oscillator Output Connection. Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. DS39969B-page 24  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA PGEC1 15 24 K1 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1. PGED1 16 25 K2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 1. PGEC2 17 26 L1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 2. PGED2 18 27 J3 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 2. PGEC3 11 20 H1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 3. PGED3 12 21 H2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 3. PMA0 — 44 L8 I/O ST Parallel Master Port Address bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 — 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 — 14 F3 O — PMA3 — 12, 60(1) F2, G11(1) O — PMA4 — 11,59(1) F4,G10(1) O — PMA5 — 10,40(1) E3,K6(1) O — PMA6 — 29 K3 O — PMA7 — 28 L2 O — PMA8 — 50 L11 O — PMA9 — 49 L10 O — PMA10 — 42 L7 O — PMA11 — 41 J7 O — PMA12 — 35 J5 O — Parallel Master Port Address bits<22:2>. PMA13 — 34 L5 O — PMA14 — 71 C11 O — PMA15 — 70 D11 O — PMA16 — 95 C4 O — PMA17 — 92 B5 O — PMA18 — 40,10(1) K6,E3(1) O — PMA19 — 19 G2 O — PMA20 — 59, 11(1) G10, F4(1) O — PMA21 — 60,12(1) G11,F2(1) O — PMA22 — 66,9(1) E11,E1(1) O — PMACK1 — 77 A10 I ST/TTL Parallel Master Port Acknowledge Input 1. PMACK2 — 69 E10 I ST/TTL Parallel Master Port Acknowledge Input 2. PMALL — 44 L8 O — Parallel Master Port Lower Address Latch Strobe. PMALH — 43 K7 O — Parallel Master Port Higher Address Latch Strobe. PMALU — 14 F3 O — Parallel Master Port Upper Address Latch Strobe. PMBE0 — 78 B9 O — Parallel Master Port Byte Enable Strobe 0. PMBE1 — 67 E8 O — Parallel Master Port Byte Enable Strobe 1. PMCS1 — 71(3),18 C11(3),G1 I/O ST/TTL Parallel Master Port Chip Select Strobe 1. PMCS2 — 70(2),9, D11(2),E1, O — Parallel Master Port Chip Select Strobe 2. 66(1) E11(1) Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 25

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA PMD0 — 93 A4 I/O ST/TTL PMD1 — 94 B4 I/O ST/TTL PMD2 — 98 B3 I/O ST/TTL PMD3 — 99 A2 I/O ST/TTL PMD4 — 100 A1 I/O ST/TTL PMD5 — 3 D3 I/O ST/TTL PMD6 — 4 C1 I/O ST/TTL PMD7 — 5 D2 I/O ST/TTL Parallel Master Port Data bits<15:0>. PMD8 — 90 A5 I/O ST/TTL PMD9 — 89 E6 I/O ST/TTL PMD10 — 88 A6 I/O ST/TTL PMD11 — 87 B6 I/O ST/TTL PMD12 — 79 A9 I/O ST/TTL PMD13 — 80 D8 I/O ST/TTL PMD14 — 83 D7 I/O ST/TTL PMD15 — 84 C7 I/O ST/TTL PMRD — 82 B8 I/O ST/TTL Parallel Master Port Read Strobe. PMWR — 81 C8 I/O ST/TTL Parallel Master Port Write Strobe. RA0 — 17 G3 I/O ST RA1 — 38 J6 I/O ST RA2 — 58 H11 I/O ST RA3 — 59 G10 I/O ST RA4 — 60 G11 I/O ST RA5 — 61 G9 I/O ST PORTA Digital I/O. RA6 — 91 C5 I/O ST RA7 — 92 B5 I/O ST RA9 — 28 L2 I/O ST RA10 — 29 K3 I/O ST RA14 — 66 E11 I/O ST RA15 — 67 E8 I/O ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. DS39969B-page 26  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA RB0 16 25 K2 I/O ST RB1 15 24 K1 I/O ST RB2 14 23 J2 I/O ST RB3 13 22 J1 I/O ST RB4 12 21 H2 I/O ST RB5 11 20 H1 I/O ST RB6 17 26 L1 I/O ST RB7 18 27 J3 I/O ST PORTB Digital I/O. RB8 21 32 K4 I/O ST RB9 22 33 L4 I/O ST RB10 23 34 L5 I/O ST RB11 24 35 J5 I/O ST RB12 27 41 J7 I/O ST RB13 28 42 L7 I/O ST RB14 29 43 K7 I/O ST RB15 30 44 L8 I/O ST RC1 — 6 D1 I/O ST RC2 — 7 E4 I/O ST RC3 — 8 E2 I/O ST RC4 — 9 E1 I/O ST PORTC Digital I/O. RC12 39 63 F9 I/O ST RC13 47 73 C10 I/O ST RC14 48 74 B11 I/O ST RC15 40 64 F11 I/O ST RCV 18 27 J3 I ST USB Receive Input (from external transceiver). Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 27

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA RD0 46 72 D9 I/O ST RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST PORTD Digital I/O. RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 — 80 D8 I/O ST RD14 — 47 L9 I/O ST RD15 — 48 K9 I/O ST RE0 60 93 A4 I/O ST RE1 61 94 B4 I/O ST RE2 62 98 B3 I/O ST RE3 63 99 A2 I/O ST RE4 64 100 A1 I/O ST PORTE Digital I/O. RE5 1 3 D3 I/O ST RE6 2 4 C1 I/O ST RE7 3 5 D2 I/O ST RE8 — 18 G1 I/O ST RE9 — 19 G2 I/O ST REFO 30 44 L8 O — Reference Clock Output. RF0 58 87 B6 I/O ST RF1 59 88 A6 I/O ST RF2 — 52 K11 I/O ST RF3 33 51 K10 I/O ST RF4 31 49 L10 I/O ST PORTF Digital I/O. RF5 32 50 L11 I/O ST RF7 34 54 H8 I/O ST RF8 — 53 J10 I/O ST RF12 — 40 K6 I/O ST RF13 — 39 L6 I/O ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. DS39969B-page 28  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA RG0 — 90 A5 I/O ST RG1 — 89 E6 I/O ST RG2 37 57 H10 I/O ST RG3 36 56 J11 I/O ST RG6 4 10 E3 I/O ST RG7 5 11 F4 I/O ST PORTG Digital I/O. RG8 6 12 F2 I/O ST RG9 8 14 F3 I/O ST RG12 — 96 C3 I/O ST RG13 — 97 A3 I/O ST RG14 — 95 C4 I/O ST RG15 — 1 B2 I/O ST RP0 16 25 K2 I/O ST RP1 15 24 K1 I/O ST RP2 42 68 E9 I/O ST RP3 44 70 D11 I/O ST RP4 43 69 E10 I/O ST RP5 — 48 K9 I/O ST RP6 17 26 L1 I/O ST RP7 18 27 J3 I/O ST RP8 21 32 K4 I/O ST RP9 22 33 L4 I/O ST Remappable Peripheral (input or output). RP10 31 49 L10 I/O ST RP11 46 72 D9 I/O ST RP12 45 71 C11 I/O ST RP13 14 23 J2 I/O ST RP14 29 43 K7 I/O ST RP15 — 53 J10 I/O ST RP16 33 51 K10 I/O ST RP17 32 50 L11 I/O ST RP18 11 20 H1 I/O ST RP19 6 12 F2 I/O ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 29

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA RP20 53 82 B8 I/O ST RP21 4 10 E3 I/O ST RP22 51 78 B9 I/O ST RP23 50 77 A10 I/O ST RP24 49 76 A11 I/O ST RP25 52 81 C8 I/O ST Remappable Peripheral (input or output). RP26 5 11 F4 I/O ST RP27 8 14 F3 I/O ST RP28 12 21 H2 I/O ST RP29 30 44 L8 I/O ST RP30 — 52 K11 I/O ST RP31 — 39 L6 I/O ST RPI32 — 40 K6 I ST RPI33 — 18 G1 I ST RPI34 — 19 G2 I ST RPI35 — 67 E8 I ST RPI36 — 66 E11 I ST RPI37 48 74 B11 I ST Remappable Peripheral (input only). RPI38 — 6 D1 I ST RPI39 — 7 E4 I ST RPI40 — 8 E2 I ST RPI41 — 9 E1 I ST RPI42 — 79 A9 I ST RPI43 — 47 L9 I ST RTCC 42 68 E9 O — Real-Time Clock Alarm/Seconds Pulse Output. SCL1 44 66 E11 I/O I2C™ I2C1 Synchronous Serial Clock Input/Output. SCL2 32 58 H11 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SCL3 2 4 C1 I/O I2C I2C3 Synchronous Serial Clock Input/Output. SCLKI 48 74 B11 O ANA Secondary Clock Input. SDA1 43 67 E8 I/O I2C I2C1 Data Input/Output. SDA2 31 59 G10 I/O I2C I2C2 Data Input/Output. SDA3 3 5 D2 I/O I2C I2C3 Data Input/Output. SESSEND 55 84 C7 I ST USB VBUS Boost Generator, Comparator Input 3. SESSVLD 59 88 A6 I ST USB VBUS Boost Generator, Comparator Input 2. SOSCI 47 73 C10 I ANA Secondary Oscillator/Timer1 Clock Input. SOSCO 48 74 B11 O ANA Secondary Oscillator/Timer1 Clock Output. T1CK 48 74 B11 I ST Timer1 Clock. Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’. DS39969B-page 30  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 1-3: PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function I/O Description 64-Pin 100-Pin 121-Pin Buffer TQFP/QFN TQFP BGA TCK 27 38 J6 I ST JTAG Test Clock Input. TDI 28 60 G11 I ST JTAG Test Data Input. TDO 24 61 G9 O — JTAG Test Data Output. TMS 23 17 G3 I ST JTAG Test Mode Select Input. USBID 33 51 K10 I ST USB OTG ID (OTG mode only). USBOEN 12 21 H2 O — USB Output Enable Control (for external transceiver). VBUS 34 54 H8 I ANA USB Voltage, Host mode (5V). VBUSCHG 49 76 A11 O — External USB VBUS Charge Output. VBUSON 11 20 H1 O — USB OTG External Charge Pump Control. VBUSST 58 87 B6 I ANA USB OTG Internal Charge Pump Feedback Control. VBUSVLD 58 87 B6 I ST USB VBUS Boost Generator, Comparator Input 1. VCAP 56 85 B7 P — External Filter Capacitor Connection (regulator enabled). VCMPST1 58 87 B6 I ST USB VBUS Boost Generator, Comparator Input 1. VCMPST2 59 88 A6 I ST USB VBUS Boost Generator, Comparator Input 2. VCPCON 49 76 A11 O — USB OTG VBUS PWM/Charge Output. VDD 10, 26, 38 2, 16, 37, C2, C9, F8, P — Positive Supply for Peripheral Digital Logic and I/O Pins. 46, 62 G5, H6, K8, H4, E5 VMIO 14 23 J2 I ST USB Differential Minus Input/Output (external transceiver). VPIO 13 22 J1 I ST USB Differential Plus Input/Output (external transceiver). VREF- 15 28, 24(4) L2, K1(4) I ANA A/D and Comparator Reference Voltage (low) Input. VREF+ 16 29, 25(4) K3, K2(4) I ANA A/D and Comparator Reference Voltage (high) Input. VSS 9, 25, 41 15, 36, 45, B10, F5, P — Ground Reference for Logic and I/O Pins. 65, 75 F10, G6, G7, H3, D4, D5 VSYNC 1 96 C3 O — Graphics Display Vertical Sync Pulse. VUSB 35 55 H9 P — USB Voltage (3.3V). Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Note 1: The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to ‘0’. 2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. 3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. 4: The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 31

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 32  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH 16-BIT MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC24FJ256DA210 family of R1 DD SS (1) (1) 16-bit microcontrollers requires attention to a minimal V V R2 set of device pin connections before proceeding with MCLR (EN/DIS)VREG development. VCAP/VDDCORE C1 The following pins must always be connected: C7 PIC24FXXXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24FJ devices only) (see Section2.4 “Voltage Regulator Pins Key (all values are recommendations): (ENVREG/DISVREG and VCAP/VDDCORE)”) C1 through C6: 0.1 F, 20V ceramic These pins must also be connected if they are being C7: 10 F, 6.3V or greater, tantalum or ceramic used in the end application: R1: 10 kΩ • PGECx/PGEDx pins used for In-Circuit Serial R2: 100Ω to 470Ω Programming™ (ICSP™) and debugging purposes Note 1: See Section2.4 “Voltage Regulator Pins (see Section2.5 “ICSP Pins”) (ENVREG/DISVREG and VCAP/VDDCORE)” • OSCI and OSCO pins when an external oscillator for explanation of ENVREG/DISVREG pin source is used connections. (see Section2.6 “External Oscillator Pins”) 2: The example shown is for a PIC24F device Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; • VREF+/VREF- pins used when external voltage adjust the number of decoupling capacitors reference for analog modules is implemented appropriately. Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2010 Microchip Technology Inc. DS39969B-page 33

PIC24FJ256DA210 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: device Reset, and device programming The use of decoupling capacitors on every pair of and debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 F (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented, depending on the should be a low-ESR device with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1F in parallel with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC24FXXXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1 10k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10k. Ensure that the On boards with power traces running longer than six MCLR pin VIH and VIL specifications are met. inches in length, it is suggested to use a tank capacitor 2: R2 470 will limit any current flowing into for integrated circuits including microcontrollers to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS39969B-page 34  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 2.4 Voltage Regulator Pins FIGURE 2-3: FREQUENCY vs. ESR (ENVREG/DISVREG and PERFORMANCE FOR VCAP/VDDCORE) SUGGESTED VCAP 10 Note: This section applies only to PIC24FJ devices with an on-chip voltage regulator. 1 The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device ) family) must always be connected directly to either a R ( 0.1 S supply voltage or to ground. The particular connection E is determined by whether or not the regulator is to be 0.01 used: • For ENVREG, tie to VDD to enable the regulator, 0.001 or to ground to disable the regulator 0.01 0.1 1 10 100 1000 10,000 • For DISVREG, tie to ground to enable the Frequency (MHz) regulator or to VDD to disable the regulator Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25°C, 0V DC bias. Refer to Section27.2 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. 2.5 ICSP Pins When the regulator is enabled, a low-ESR (<5Ω) The PGECx and PGEDx pins are used for In-Circuit capacitor is required on the VCAP/VDDCORE pin to Serial Programming (ICSP) and debugging purposes. stabilize the voltage regulator output voltage. The It is recommended to keep the trace length between VCAP/VDDCORE pin must not be connected to VDD, and the ICSP connector and the ICSP pins on the device as must use a capacitor of 10 F connected to ground. The short as possible. If the ICSP connector is expected to type can be ceramic or tantalum. A suitable example is experience an ESD event, a series resistor is recom- the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or mended, with the value in the range of a few tens of equivalent. Designers may use Figure2-3 to evaluate ohms, not to exceed 100Ω. ESR equivalence of candidate devices. Pull-up resistors, series diodes and capacitors on the The placement of this capacitor should be close to PGECx and PGEDx pins are not recommended as they VCAP/VDDCORE. It is recommended that the trace will interfere with the programmer/debugger communi- length not exceed 0.25inch (6mm). Refer to cations to the device. If such discrete components are Section30.0 “Electrical Characteristics” for an application requirement, they should be removed additional information. from the circuit during programming and debugging. When the regulator is disabled, the VCAP/VDDCORE pin Alternatively, refer to the AC/DC characteristics and must be tied to a voltage supply at the VDDCORE level. timing requirements information in the respective Refer to Section30.0 “Electrical Characteristics” for device Flash programming specification for information information on VDD and VDDCORE. on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section28.0 “Development Support”.  2010 Microchip Technology Inc. DS39969B-page 35

PIC24FJ256DA210 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: SUGGESTED PLACEMENT OF THE OSCILLATOR Many microcontrollers have options for at least two CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-line Layouts: Section8.0 “Oscillator Configuration” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSCI Oscillator of the board. C1 ` OSCO Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power SOSCO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board Secondary SOSC I where the crystal is placed. Oscillator Crystal ` Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With Sec Oscillator: C1 Sec Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins and other signals Bottom Layer in close proximity to the oscillator are benign (i.e., free Copper Pour of high frequencies, short rise and fall times and other (tied to ground) similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” DEVICE PINS DS39969B-page 36  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 2.7 Configuration of Analog and If your application needs to use certain A/D pins as Digital Pins During ICSP analog input pins during the debug session, the user application must modify the appropriate bits during Operations initialization of the ADC module, as follows: If an ICSP compliant emulator is selected as a debug- • For devices with an ADnPCFG register, clear the ger, it automatically initializes all of the A/D input pins bits corresponding to the pin(s) to be configured (ANx) as “digital” pins. Depending on the particular as analog. Do not change any other bits, particu- device, this is done by setting all bits in the ADnPCFG larly those corresponding to the PGECx/PGEDx register(s), or clearing all bit in the ANSx registers. pair, at any time. All PIC24F devices will have either one or more • For devices with ANSx registers, set the bits ADnPCFG registers or several ANSx registers (one for corresponding to the pin(s) to be configured as each port); no device will have both. Refer to analog. Do not change any other bits, particularly (Section23.0 “10-Bit High-Speed A/D Converter”) those corresponding to the PGECx/PGEDx pair, for more specific information. at any time. The bits in these registers that correspond to the A/D When a Microchip debugger/emulator is used as a pins that initialized the emulator must not be changed programmer, the user application firmware must by the user application firmware; otherwise, correctly configure the ADnPCFG or ANSx registers. communication errors will result between the debugger Automatic initialization of this register is only done and the device. during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic '0', which may affect user application functionality. 2.8 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low.  2010 Microchip Technology Inc. DS39969B-page 37

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 38  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 3.0 CPU The core supports Inherent (no operand), Relative, Literal, Memory Direct Addressing modes along with Note: This data sheet summarizes the features three groups of addressing modes. All modes support of this group of PIC24F devices. It is not Register Direct and various Register Indirect modes. intended to be a comprehensive reference Each group offers up to seven addressing modes. source. For more information, refer to the Instructions are associated with predefined addressing “PIC24F Family Reference Manual”, modes depending upon their functional requirements. Section 44. “CPU with Extended Data For most instructions, the core is capable of executing Space (EDS)” (DS39732). The informa- a data (or program data) memory read, a working reg- tion in this data sheet supersedes the ister (data) read, a data memory write and a program information in the FRM. (instruction) memory read per instruction cycle. As a The PIC24F CPU has a 16-bit (data) modified Harvard result, three parameter instructions can be supported, architecture with an enhanced instruction set and a allowing trinary operations (that is, A + B = C) to be 24-bit instruction word with a variable length opcode executed in a single cycle. field. The Program Counter (PC) is 23 bits wide and A high-speed, 17-bit x 17-bit multiplier has been addresses up to 4M instructions of user program included to significantly enhance the core arithmetic memory space. A single-cycle instruction prefetch capability and throughput. The multiplier supports mechanism is used to help maintain throughput and Signed, Unsigned and Mixed mode, 16-bit x 16-bit or provides predictable execution. All instructions execute 8-bit x 8-bit, integer multiplication. All multiply in a single cycle, with the exception of instructions that instructions execute in a single cycle. change the program flow, the double-word move The 16-bit ALU has been enhanced with integer divide (MOV.D) instruction and the table instructions. assist hardware that supports an iterative non-restoring Overhead-free program loop constructs are supported divide algorithm. It operates in conjunction with the using the REPEAT instructions, which are interruptible REPEAT instruction looping mechanism and a selection at any point. of iterative divide instructions to support 32-bit (or PIC24F devices have sixteen, 16-bit working registers 16-bit), divided by 16-bit, integer signed and unsigned in the programmer’s model. Each of the working division. All divide operations require 19 cycles to registers can act as a data, address or address offset complete but are interruptible at any cycle boundary. register. The 16th working register (W15) operates as a The PIC24F has a vectored exception scheme with up Software Stack Pointer for interrupts and calls. to 8 sources of non-maskable traps and up to 118 inter- The lower 32 Kbytes of the data space can be rupt sources. Each interrupt source can be assigned to accessed linearly. The upper 32Kbytes of the data one of seven priority levels. space are referred to as extended data space to which A block diagram of the CPU is shown in Figure3-1. the extended data RAM, EPMP memory space or program memory can be mapped. 3.1 Programmer’s Model The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but The programmer’s model for the PIC24F is shown in maintains an acceptable level of backward compatibil- Figure3-2. All registers in the programmer’s model are ity. All PIC18 instructions and addressing modes are memory mapped and can be manipulated directly by supported, either directly, or through simple macros. instructions. A description of each register is provided Many of the ISA enhancements have been driven by in Table3-1. All registers associated with the compiler efficiency needs. programmer’s model are memory mapped.  2010 Microchip Technology Inc. DS39969B-page 39

PIC24FJ256DA210 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM EDS and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 Data RAM PCH PCL 16 23 Up to 0x7FFF Program Counter Stack Loop Address Control Control Latch Logic Logic 23 16 RAGU Address Latch WAGU Program Memory/ Extended Data Space Address Bus EA MUX Data Latch ROM Latch 24 16 16 Instruction a Decode and Dat Control Instruction Reg al er Lit Control Signals to Various Blocks Hardware Multiplier 16 x 16 W Register Array Divide Support 16 16-Bit ALU 16 To Peripheral Modules TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register DISICNT Disable Interrupt Count Register DSRPAG Data Space Read Page Register DSWPAG Data Space Write Page Register DS39969B-page 40  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 0 W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address W8 Registers W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 Stack Pointer Limit Value Register 22 0 PC 0 Program Counter 7 0 Table Memory Page TBLPAG Address Register 9 0 DSRPAG Data Space Read Page Register 8 0 DSWPAG Data Space Write Page Register 15 0 Repeat Loop Counter RCOUNT Register 15 SRH SRL 0 ———————DC2IP1L0RA N OVZ C ALU STATUS Register (SR) 15 0 ———————————— IPL3 ——— CPU Control Register (CORCON) 13 0 DISICNT Disable Interrupt Count Register Registers or bits are shadowed for PUSH.S and POP.S instructions.  2010 Microchip Technology Inc. DS39969B-page 41

PIC24FJ256DA210 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HSC — — — — — — — DC bit 15 bit 8 R/W-0, HSC(1) R/W-0, HSC(1) R/W-0, HSC(1) R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts are disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was not negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation, which affects the Z bit, has set it at some time in the past 0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit of the result occurred 0 = No carry out from the Most Significant bit of the result occurred Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. 2: The IPL Status bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39969B-page 42  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R-1 U-0 U-0 — — — — IPL3(1) r — — bit 7 bit 0 Legend: C = Clearable bit r = Reserved bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 Reserved: Read as ‘1’ bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level; see Register3-1 for bit description. 3.3 Arithmetic Logic Unit (ALU) The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a The PIC24F ALU is 16 bits wide and is capable of addi- dedicated hardware multiplier and support hardware tion, subtraction, bit shifts and logic operations. Unless for 16-bit divisor division. otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the 3.3.1 MULTIPLIER ALU may affect the values of the Carry (C), Zero (Z), The ALU contains a high-speed, 17-bit x 17-bit Negative (N), Overflow (OV) and Digit Carry (DC) multiplier. It supports unsigned, signed or mixed sign Status bits in the SR register. The C and DC Status bits operation in several multiplication modes: operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. 1. 16-bit x 16-bit signed The ALU can perform 8-bit or 16-bit operations, 2. 16-bit x 16-bit unsigned depending on the mode of the instruction that is used. 3. 16-bit signed x 5-bit (literal) unsigned Data for the ALU operation can come from the W 4. 16-bit unsigned x 16-bit unsigned register array, or data memory, depending on the 5. 16-bit unsigned x 5-bit (literal) unsigned addressing mode of the instruction. Likewise, output 6. 16-bit unsigned x 16-bit signed data from the ALU can be written to the W register array 7. 8-bit unsigned x 8-bit unsigned or a data memory location.  2010 Microchip Technology Inc. DS39969B-page 43

PIC24FJ256DA210 FAMILY 3.3.2 DIVIDER 3.3.3 MULTI-BIT SHIFT SUPPORT The divide block supports signed and unsigned integer The PIC24F ALU supports both single bit and divide operations with the following data sizes: single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, 1. 32-bit signed/16-bit signed divide capable of performing up to a 15-bit arithmetic right 2. 32-bit unsigned/16-bit unsigned divide shift, or up to a 15-bit left shift, in a single cycle. All 3. 16-bit signed/16-bit signed divide multi-bit shift instructions only support Register Direct 4. 16-bit unsigned/16-bit unsigned divide Addressing for both the operand source and result The quotient for all divide instructions ends up in W0 destination. and the remainder in W1. 16-bit signed and unsigned A full summary of instructions that use the shift DIV instructions can specify any W register for both the operation is provided in Table3-2. 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algo- rithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE BIT AND MULTI-BIT SHIFT OPERATION Instruction Description ASR Arithmetic shift right source register by one or more bits. SL Shift left source register by one or more bits. LSR Logical shift right source register by one or more bits. DS39969B-page 44  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 4.0 MEMORY ORGANIZATION from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space As Harvard architecture devices, PIC24F micro- remapping, as described in Section4.3 “Interfacing controllers feature separate program and data memory Program and Data Memory Spaces”. spaces and busses. This architecture also allows direct User access to the program memory space is restricted access of program memory from the data space during to the lower half of the address range (000000h to code execution. 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to 4.1 Program Memory Space the Configuration bits and Device ID sections of the The program address memory space of the configuration memory space. PIC24FJ256DA210 family devices is 4M instructions. Memory maps for the PIC24FJ256DA210 family of The space is addressable by a 24-bit value derived devices are shown in Figure4-1. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256DA210 FAMILY DEVICES PIC24FJ128DAXXX PIC24FJ256DAXXX GOTO Instruction GOTO Instruction 000000h 000002h Reset Address Reset Address 000004h Interrupt Vector Table Interrupt Vector Table 0000FEh Reserved Reserved 000100h 000104h Alternate Vector Table Alternate Vector Table 0001FEh 000200h User Flash Program Memory (44K instructions) User Flash Program Memory e ac Flash Config Words (87K instructions) 0157FEh p S 015800h y or m e M er s U Flash Config Words 02ABFEh Unimplemented 02AC00h Read ‘0’ Unimplemented Read ‘0’ 7FFFFEh 800000h Reserved Reserved e c a p S y F7FFFEh or F80000h m Device Config Registers Device Config Registers e F8000Eh M n F80010h o ati ur nfig Reserved Reserved o C FEFFFEh FF0000h DEVID (2) DEVID (2) FFFFFEh Note: Memory areas are not shown to scale.  2010 Microchip Technology Inc. DS39969B-page 45

PIC24FJ256DA210 FAMILY 4.1.1 PROGRAM MEMORY 4.1.3 FLASH CONFIGURATION WORDS ORGANIZATION In PIC24FJ256DA210 family devices, the top four The program memory space is organized in words of on-chip program memory are reserved for word-addressable blocks. Although it is treated as configuration information. On device Reset, the config- 24bits wide, it is more appropriate to think of each uration information is copied into the appropriate address of the program memory as a lower and upper Configuration register. The addresses of the Flash word, with the upper byte of the upper word being Configuration Word for devices in the unimplemented. The lower word always has an even PIC24FJ256DA210 family are shown in Table4-1. address, while the upper word has an odd address Their location in the memory map is shown with the (Figure4-2). other memory vectors in Figure4-1. Program memory addresses are always word-aligned The Configuration Words in program memory are a on the lower word and addresses are incremented or compact format. The actual Configuration bits are decremented by two during code execution. This mapped in several different registers in the configuration arrangement also provides compatibility with data memory space. Their order in the Flash Configuration memory space addressing and makes it possible to Words does not reflect a corresponding arrangement in access data in the program memory space. the configuration space. Additional details on the device Configuration Words are provided in Section27.1 4.1.2 HARD MEMORY VECTORS “Configuration Bits”. All PIC24F devices reserve the addresses between TABLE 4-1: FLASH CONFIGURATION 0x00000 and 0x000200 for hard coded program execu- tion vectors. A hardware Reset vector is provided to WORDS FOR redirect code execution from the default value of the PIC24FJ256DA210 FAMILY PC on device Reset to the actual start of code. A GOTO DEVICES instruction is programmed by the user at 0x000000 with Program the actual address for the start of code at 0x000002. Configuration Device Memory Word Addresses PIC24F devices also have two interrupt vector tables, (Words) located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many PIC24FJ128DAXXX 44,032 0x0157F8:0x0157FE device interrupt sources to be handled by separate PIC24FJ256DAXXX 87,552 0x02ABF8:0x02ABFE ISRs. A more detailed discussion of the interrupt vector tables is provided in Section7.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS39969B-page 46  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 4.2 Data Memory Space The EDS includes any additional internal data memory not accessible by the lower 32-Kbyte data address Note: This data sheet summarizes the features space and any external memory through EPMP. For of this group of PIC24F devices. It is not more details on accessing internal extended data intended to be a comprehensive reference memory, refer to the “PIC24F Family Reference source. For more information, refer to the Manual”, Section 45. “Data Memory with Extended “PIC24F Family Reference Manual”, Data Space (EDS)” (DS39733). For more details on Section 45. “Data Memory with accessing external memory using EPMP, refer to the Extended Data Space” (DS39733). The “PIC24F Family Reference Manual”, Section 42. information in this data sheet supersedes “Enhanced Parallel Master Port (EPMP)” the information in the FRM. (DS39730). In PIC24F microcontrollers with EDS, the program memory can also be read from EDS. This is The PIC24F core has a 16-bit wide data memory space, called Program Space Visibility (PSV). Table4-2 lists the addressable as a single linear range. total memory accessible by each of the devices in this The data space is accessed using two Address Genera- family. tion Units (AGUs), one each for read and write opera- The EDS is organized as pages, with a single page called tions. The data space memory map is shown in an EDS page that equals the EDS window (32 Kbytes). Figure4-3. A particular EDS page is selected through the Data The 16-bit wide data addresses in the data memory Space Read register (DSRPAG) or Data Space Write space point to bytes within the Data Space (DS). This register (DSWPAG). For PSV, only the DSRPAG register gives a DS address range of 64 Kbytes or 32K words. is used. The combination of the DSRPAG register value The lower 32 Kbytes (0x0000 to 0x7FFF) of DS is com- and the 16-bit wide data address forms a 24-bit Effective patible with the PIC24F microcontrollers without EDS. Address (EA). For more information on EDS, refer to The upper 32 Kbytes of data memory address space Section4.3.3 “Reading Data from Program Memory (0x8000 - 0xFFFF) are used as an EDS window. Using EDS”. The EDS window is used to access all memory region implemented in EDS, as shown in Figure4-4. TABLE 4-2: TOTAL MEMORY ACCESSIBLE BY THE DEVICE External RAM Access Program Memory Access Devices Internal RAM Using EPMP Using EDS PIC24FJXXXDA210 96 Kbytes (30K + 66K(1)) Yes (up to 16 MB) Yes PIC24FJXXXDA206 96 Kbytes (30K + 66K(1)) No Yes PIC24FJXXXDA110 24 Kbytes Yes (up to 16 MB) Yes PIC24FJXXXDA106 24 Kbytes No Yes Note 1: The internal RAM above 30 Kbytes can be accessed through EDS window.  2010 Microchip Technology Inc. DS39969B-page 47

PIC24FJ256DA210 FAMILY 4.2.1 DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ256DA210 FAMILY DEVICES(4) MSB LSB Address MSB LSB Address 0001h 0000h SFR SFR Space 07FFh 07FEh Space Near 0801h 0800h Data Space 1FFFh 1FFEh 2001h 2000h Lower 32 Kbytes Data Space 30 Kbytes Data RAM 67FFh(1) 67FEh(1) 7FFFh 7FFEh 8001h 8000h EDS Page 0x1 (32 KB) Internal Extended EDS Page 0x2 Data RAM(66 Kbytes)(2) (32 KB) Upper 32 Kbytes EDS Page 0x3 (2 KB) Data Space EDS Window EDS Page 0x4 EPMP Memory Space(3) EDS Page 0x1FF EDS Page 0x200 Program Space Visibility Area toAccess Lower Word of Program Memory EDS Page 0x2FF FFFFh FFFEh EDS Page 0x300 Program Space Visibility Area to Access Upper EDS Page 0x3FF Word of Program Memory Note 1: 24-Kbyte RAM variants (PIC24FJXXXDA1XX devices have implemented RAM only up to 0x67FF). 2: Valid only for 96-Kbyte RAM variants (PIC24FJXXXDA2XX). 3: Valid only for variants with the EPMP module (PIC24FJXXXDAX10). 4: Data memory areas are not shown to scale. DS39969B-page 48  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 4.2.2 DATA MEMORY ORGANIZATION can clear the MSB of any W register by executing a AND ALIGNMENT zero-extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® MCUs and improve data space memory usage efficiency, the Although most instructions are capable of operating on PIC24F instruction set supports both word and byte word or byte data sizes, it should be noted that some operations. As a consequence of byte accessibility, all instructions operate only on words. EA calculations are internally scaled to step through 4.2.3 NEAR DATA SPACE word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode The 8-Kbyte area between 0000h and 1FFFh is [Ws++] will result in a value of Ws + 1 for byte operations referred to as the near data space. Locations in this and Ws + 2 for word operations. space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The Data byte reads will read the complete word, which remainder of the data space is addressable indirectly. contains the byte, using the LSB of any EA to deter- Additionally, the whole data space is addressable using mine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory MOV instructions, which support Memory Direct Addressing with a 16-bit address field. and registers are organized as two parallel, byte-wide entities with shared (word) address decode but 4.2.4 SPECIAL FUNCTION REGISTER separate write lines. Data byte writes only write to the (SFR) SPACE corresponding side of the array or register which matches the byte address. The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function All word accesses must be aligned to an even address. Registers (SFRs). These are used by the PIC24F core Misaligned word data fetches are not supported, so and peripheral modules for controlling the operation of care must be taken when mixing byte and word the device. operations or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error SFRs are distributed among the modules that they con- trap will be generated. If the error occurred on a read, trol and are generally grouped together by module. the instruction underway is completed; if it occurred on Much of the SFR space contains unused addresses; a write, the instruction will be executed but the write will these are read as ‘0’. A diagram of the SFR space, not occur. In either case, a trap is then executed, allow- showing where the SFRs are actually implemented, is ing the system and/or user to examine the machine shown in Table4-3. Each implemented area indicates state prior to execution of the address Fault. a 32-byte region where at least one address is imple- mented as an SFR. A complete list of implemented All byte loads into any W register are loaded into the SFRs, including their addresses, is shown in Tables4-4 LSB. The Most Significant Byte (MSB) is not modified. throughTable4-34. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users TABLE 4-3: IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0 000h Core ICN Interrupts 100h Timers Capture Compare 200h I2C™ UART SPI/UART SPI/I2C SPI UART I/O 300h ADC/CTMU — — — — — 400h — — — — USB ANSEL 500h — — — — — — — — 600h EPMP RTC/Comp CRC — PPS — 700h GFX Controller System NVM/PMD — — — — Legend: — = No implemented SFRs in this block  2010 Microchip Technology Inc. DS39969B-page 49

D P S TABLE 4-4: CPU CORE REGISTERS MAP 3 9 I 9 File All C 6 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Name Resets B -pa WREG0 0000 Working Register 0 0000 2 g 4 e 5 WREG1 0002 Working Register 1 0000 F 0 WREG2 0004 Working Register 2 0000 J WREG3 0006 Working Register 3 0000 2 WREG4 0008 Working Register 4 0000 5 WREG5 000A Working Register 5 0000 6 WREG6 000C Working Register 6 0000 D WREG7 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 A WREG9 0012 Working Register 9 0000 2 WREG10 0014 Working Register 10 0000 1 WREG11 0016 Working Register 11 0000 0 WREG12 0018 Working Register 12 0000 WREG13 001A Working Register 13 0000 F WREG14 001C Working Register 14 0000 A WREG15 001E Working Register 15 0800 M SPLIM 0020 Stack Pointer Limit Value Register xxxx PCL 002E Program Counter Low Word Register 0000 IL PCH 0030 — — — — — — — — Program Counter Register High Byte 0000 Y DSRPAG 0032 — — — — — — Extended Data Space Read Page Address Register 0001 DSWPAG(1) 0034 — — — — — — — Extended Data Space Write Page Address Register 0001 RCOUNT 0036 Repeat Loop Counter Register xxxx SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000 CORCON 0044 — — — — — — — — — — — — IPL3 r — — 0004 DISICNT 0052 — — Disable Interrupts Counter Register xxxx  TBLPAG 0054 — — — — — — — — Table Memory Page Address Register 0000 20 Legend: — = unimplemented, read as ‘0’; r = Reserved bit. Reset values are shown in hexadecimal. 1 Note 1: Reserved in PIC24FJXXXDA106 devices; do not use. 0 M ic ro ch ip T e c h n o lo g y In c .

 TABLE 4-5: ICN REGISTER MAP 2 0 1 0 M File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All ic Name Resets ro c CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CN11PDE CN10PDE CN9PDE CN8PDE CN7PDE CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE 0000 h ip CNPD2 0058 CN31PDE CN30PDE CN29PDE CN28PDE CN27PDE CN26PDE CN25PDE CN24PDE CN23PDE CN22PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) CN18PDE CN17PDE CN16PDE 0000 T e CNPD3 005A CN47PDE(1) CN46PDE(1) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(1) CN39PDE(1) CN38PDE(1) CN37PDE(1) CN36PDE(1) CN35PDE(1) CN34PDE(1) CN33PDE(1) CN32PDE 0000 c hn CNPD4 005C CN63PDE CN62PDE CN61PDE CN60PDE CN59PDE CN58PDE CN57PDE(1) CN56PDE CN55PDE CN54PDE CN53PDE CN52PDE CN51PDE CN50PDE CN49PDE CN48PDE(1) 0000 o lo CNPD5 005E CN79PDE(1) CN78PDE(1) CN77PDE(1) CN76PDE(1) CN75PDE(1) CN74PDE(1) CN73PDE(1) — CN71PDE CN70PDE(1) CN69PDE CN68PDE CN67PDE(1) CN66PDE(1) CN65PDE CN64PDE 0000 g y In CNPD6 0060 — — — — — — — — — — — CN84PDE CN83PDE CN82PDE(1) CN81PDE(1) CN80PDE(1) 0000 c. CNEN1 0062 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CNEN2 0064 CN31IE CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE(1) CN20IE(1) CN19IE(1) CN18IE CN17IE CN16IE 0000 CNEN3 0066 CN47IE(1) CN46IE(1) CN45IE(1) CN44IE(1) CN43IE(1) CN42IE(1) CN41IE(1) CN40IE(1) CN39IE(1) CN38IE(1) CN37IE(1) CN36IE(1) CN35IE(1) CN34IE(1) CN33IE(1) CN32IE 0000 CNEN4 0068 CN63IE CN62IE CN61IE CN60IE CN59IE CN58IE CN57IE(1) CN56IE CN55IE CN54IE CN53IE CN52IE CN51IE CN50IE CN49IE CN48IE(1) 0000 CNEN5 006A CN79IE(1) CN78IE(1) CN77IE(1) CN76IE(1) CN75IE(1) CN74IE(1) CN73IE(1) — CN71IE CN70IE(1) CN69IE CN68IE CN67IE(1) CN66IE(1) CN65IE CN64IE 0000 CNEN6 006C — — — — — — — — — — — CN84IE CN83IE CN82IE(1) CN81IE(1) CN80IE(1) 0000 CNPU1 006E CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 P CNPU2 0070 CN31PUE CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE(1) CN20PUE(1) CN19PUE(1) CN18PUE CN17PUE CN16PUE 0000 I CNPU3 0072 CN47PUE(1) CN46PUE(1) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(1) CN39PUE(1) CN38PUE(1) CN37PUE(1) CN36PUE(1) CN35PUE(1) CN34PUE(1) CN33PUE(1) CN32PUE 0000 C CNPU4 0074 CN63PUE CN62PUE CN61PUE CN60PUE CN59PUE CN58PUE CN57PUE(1) CN56PUE CN55PUE CN54PUE CN53PUE CN52PUE CN51PUE CN50PUE CN49PUE CN48PUE(1) 0000 2 CNPU5 0076 CN79PUE(1) CN78PUE(1) CN77PUE(1) CN76PUE(1) CN75PUE(1) CN74PUE(1) CN73PUE(1) — CN71PUE CN70PUE(1) CN69PUE CN68PUE CN67PUE(1) CN66PUE(1) CN65PUE CN64PUE 0000 4 CNPU6 0078 — — — — — — — — — — — CN84PUE CN83PUE CN82PUE(1) CN81PUE(1) CN80PUE(1) 0000 F Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Unimplemented in 64-pin devices; read as ‘0’. J 2 5 6 D A 2 1 0 F D A S 3 99 M 6 9 B -p IL a g e 5 Y 1

D P S TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP 3 9 I 969 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts C B -pa INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 2 g 4 e 5 INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 F 2 IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 J IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — IC8IF IC7IF — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 IFS2 0088 — — PMPIF(1) OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF 0000 2 IFS3 008A — RTCIF — — — — — — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 5 IFS4 008C — — CTMUIF — — — — LVDIF — — — — CRCIF U2ERIF U1ERIF — 0000 6 IFS5 008E — — IC9IF OC9IF SPI3IF SPF3IF U4TXIF U4RXIF U4ERIF USB1IF MI2C3IF SI2C3IF U3TXIF U3RXIF U3ERIF — 0000 D IFS6 0090 — — — — — — — — — — — GFX1IF — — — — 0000 A IEC0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 2 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — IC8IE IC7IE — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 IEC2 0098 — — PMPIE(1) OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE 0000 1 IEC3 009A — RTCIE — — — — — — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 0 IEC4 009C — — CTMUIE — — — — LVDIE — — — — CRCIE U2ERIE U1ERIE — 0000 F IEC5 009E — — IC9IE OC9IE SPI3IE SPF3IE U4TXIE U4RXIE U4ERIE USB1IE MI2C3IE SI2C3IE U3TXIE U3RXIE U3ERIE — 0000 A IEC6 00A0 — — — — — — — — — — — GFX1IE — — — — 0000 IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 M IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440 I IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444 L IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 Y IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 IPC5 00AE — IC8IP2 IC8IP1 IC8IP0 — IC7IP2 IC7IP1 IC7IP0 — — — — — INT1IP2 INT1IP1 INT1IP0 4404 IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 0044 IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 4440  IPC10 00B8 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 4444 2 IPC11 00BA — — — — — — — — — PMPIP2(1) PMPIP1(1) PMPIP0(1) — OC8IP2 OC8IP1 OC8IP0 0044(2) 0 10 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 M IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 ic ro IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 0400 c hip Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. T Note 1: Unimplemented in 64-pin devices, read as ‘0’. e 2: The Reset value in 64-pin devices are ‘0004’. c h n o lo g y In c .

 TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) 2 010 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts M ic IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440 ro ch IPC18 00C8 — — — — — — — — — — — — — LVDIP2 LVDIP1 LVDIP0 0004 ip T IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040 ec IPC20 00CC — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — 4440 h n IPC21 00CE — U4ERIP2 U4ERIP1 U4ERIP0 — USB1IP2 USB1IP1 USB1IP0 — MI2C3IP2 MI2C3IP1 MI2C3IP0 — SI2C3IP2 SI2C3IP1 SI2C3IP0 4444 o log IPC22 00D0 — SPI3IP2 SPI3IP1 SPI3IP0 — SPF3IP2 SPF3IP1 SPF3IP0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 4444 y In IPC23 00D2 — — — — — — — — — IC9IP2 IC9IP1 IC9IP0 — OC9IP2 OC9IP1 OC9IP0 0044 c. IPC25 00D6 — — — — — — — — — — — — — GFX1IP2 GFX1IP1 GFX1IP0 0004 INTTREG 00E0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Unimplemented in 64-pin devices, read as ‘0’. 2: The Reset value in 64-pin devices are ‘0004’. TABLE 4-7: TIMER REGISTER MAP P I File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All C Name Resets 2 TMR1 0100 Timer1 Register 0000 PR1 0102 Timer1 Period Register FFFF 4 T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 F TMR2 0106 Timer2 Register 0000 J TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) 0000 2 TMR3 010A Timer3 Register 0000 5 PR2 010C Timer2 Period Register FFFF 6 PR3 010E Timer3 Period Register FFFF D T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 A T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 TMR4 0114 Timer4 Register 0000 2 TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) 0000 1 TMR5 0118 Timer5 Register 0000 0 PR4 011A Timer4 Period Register FFFF F PR5 011C Timer5 Period Register FFFF DS T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T45 — TCS — 0000 A 3 99 T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 M 69 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. B -p IL a g e 5 Y 3

D P S TABLE 4-8: INPUT CAPTURE REGISTER MAP 3 9 I 969B File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts C -p 2 a IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 g 4 e 5 IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D F 4 IC1BUF 0144 Input Capture 1 Buffer Register 0000 J IC1TMR 0146 Input Capture 1 Timer Value Register xxxx 2 IC2CON1 0148 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 5 IC2CON2 014A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D IC2BUF 014C Input Capture 2 Buffer Register 0000 6 IC2TMR 014E Input Capture 2 Timer Value Register xxxx D IC3CON1 0150 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 A IC3CON2 0152 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 2 IC3BUF 0154 Input Capture 3 Buffer Register 0000 1 IC3TMR 0156 Input Capture 3 Timer Value Register xxxx 0 IC4CON1 0158 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 IC4CON2 015A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D F IC4BUF 015C Input Capture 4 Buffer Register 0000 A IC4TMR 015E Input Capture 4 Timer Value Register xxxx IC5CON1 0160 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 M IC5CON2 0162 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D I IC5BUF 0164 Input Capture 5 Buffer Register 0000 L IC5TMR 0166 Input Capture 5 Timer Value Register xxxx Y IC6CON1 0168 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 IC6CON2 016A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D IC6BUF 016C Input Capture 6 Buffer Register 0000 IC6TMR 016E Input Capture 6 Timer Value Register xxxx IC7CON1 0170 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 IC7CON2 0172 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D  IC7BUF 0174 Input Capture 7 Buffer Register 0000 2 IC7TMR 0176 Input Capture 7 Timer Value Register xxxx 0 1 0 IC8CON1 0178 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 M ic IC8CON2 017A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D ro IC8BUF 017C Input Capture 8 Buffer Register 0000 c h ip IC8TMR 017E Input Capture 8 Timer Value Register xxxx Te IC9CON1 0180 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 c h IC9CON2 0182 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D n olo IC9BUF 0184 Input Capture 9 Buffer Register 0000 g y IC9TMR 0186 Input Capture 9 Timer Value Register xxxx Inc Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. .

 2 TABLE 4-9: OUTPUT COMPARE REGISTER MAP 0 1 0 All M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ic roc OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 h ip OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C T e OC1RS 0194 Output Compare 1 Secondary Register 0000 c hn OC1R 0196 Output Compare 1 Register 0000 o lo OC1TMR 0198 Output Compare 1 Timer Value Register xxxx g y In OC2CON1 019A — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 c OC2CON2 019C FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C . OC2RS 019E Output Compare 2 Secondary Register 0000 OC2R 01A0 Output Compare 2 Register 0000 OC2TMR 01A2 Output Compare 2 Timer Value Register xxxx OC3CON1 01A4 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OC3CON2 01A6 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC3RS 01A8 Output Compare 3 Secondary Register 0000 P OC3R 01AA Output Compare 3 Register 0000 I OC3TMR 01AC Output Compare 3 Timer Value Register xxxx C OC4CON1 01AE — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 2 OC4CON2 01B0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 4 OC4RS 01B2 Output Compare 4 Secondary Register 0000 OC4R 01B4 Output Compare 4 Register 0000 F OC4TMR 01B6 Output Compare 4 Timer Value Register xxxx J OC5CON1 01B8 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT1 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 2 OC5CON2 01BA FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 5 OC5RS 01BC Output Compare 5 Secondary Register 0000 6 OC5R 01BE Output Compare 5 Register 0000 D OC5TMR 01C0 Output Compare 5 Timer Value Register xxxx A OC6CON1 01C2 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OC6CON2 01C4 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 2 OC6RS 01C6 Output Compare 6 Secondary Register 0000 1 OC6R 01C8 Output Compare 6 Register 0000 0 OC6TMR 01CA Output Compare 6 Timer Value Register xxxx F OC7CON1 01CC — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 DS OC7CON2 01CE FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C A 3 99 OC7RS 01D0 Output Compare 7 Secondary Register 0000 M 6 9 OC7R 01D2 Output Compare 7 Register 0000 B -p OC7TMR 01D4 Output Compare 7 Timer Value Register xxxx IL a g Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. e 5 Y 5

TABLE 4-9: OUTPUT COMPARE REGISTER MAP (CONTINUED) D P S 39 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All I 9 Resets C 6 9 B-p OC8CON1 01D6 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 2 ag OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 4 e 5 OC8RS 01DA Output Compare 8 Secondary Register 0000 F 6 OC8R 01DC Output Compare 8 Register 0000 J OC8TMR 01DE Output Compare 8 Timer Value Register xxxx 2 OC9CON1 01E0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 5 OC9CON2 01E2 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 6 OC9RS 01E4 Output Compare 9 Secondary Register 0000 OC9R 01E6 Output Compare 9 Register 0000 D OC9TMR 01E8 Output Compare 9 Timer Value Register xxxx A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 TABLE 4-10: I2C™ REGISTER MAP 1 0 File All Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets F I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 A I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF M I2C1BRG 0204 — — — — — — — I2C1 Baud Rate Generator Register 0000 I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I L I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 I2C1ADD 020A — — — — — — I2C1 Address Register 0000 Y I2C1MSK 020C — — — — — — I2C1 Address Mask Register 0000 I2C2RCV 0210 — — — — — — — — I2C2 Receive Register 0000 I2C2TRN 0212 — — — — — — — — I2C2 Transmit Register 00FF I2C2BRG 0214 — — — — — — — I2C2 Baud Rate Generator Register 0000 I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000  I2C2ADD 021A — — — — — — I2C2 Address Register 0000 2 0 I2C2MSK 021C — — — — — — I2C2 Address Mask Register 0000 1 0 M I2C3RCV 0270 — — — — — — — — I2C3 Receive Register 0000 ic I2C3TRN 0272 — — — — — — — — I2C3 Transmit Register 00FF ro c I2C3BRG 0274 — — — — — — — I2C3 Baud Rate Generator Register 0000 h ip I2C3CON 0276 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 T ec I2C3STAT 0278 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 h n I2C3ADD 027A — — — — — — I2C3 Address Register 0000 o lo I2C3MSK 027C — — — — — — I2C3 Address Mask Register 0000 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-11: UART REGISTER MAPS 2 0 1 0 File All M Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ic ro U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 c hip U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 T U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx e c h U1RXREG 0226 — — — — — — — UART1 Receive Register 0000 n olo U1BRG 0228 UART1 Baud Rate Generator Prescaler Register 0000 gy U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 Inc U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 . U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx U2RXREG 0236 — — — — — — — UART2 Receive Register 0000 U2BRG 0238 UART2 Baud Rate Generator Prescaler Register 0000 U3MODE 0250 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 U3STA 0252 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 U3TXREG 0254 — — — — — — — UART3 Transmit Register xxxx P U3RXREG 0256 — — — — — — — UART3 Receive Register 0000 U3BRG 0258 UART3 Baud Rate Generator Prescaler Register 0000 I C U4MODE 02B0 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 U4STA 02B2 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 2 U4TXREG 02B4 — — — — — — — UART4 Transmit Register xxxx 4 U4RXREG 02B6 — — — — — — — UART4 Receive Register 0000 F U4BRG 02B8 UART4 Baud Rate Generator Prescaler Register 0000 J Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 5 6 D A 2 1 0 F D A S 3 99 M 6 9 B -p IL a g e 5 Y 7

D T ABLE 4-12: SPI REGISTER MAPS P S 3 9 I 9 C 6 File All 9B Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets -p 2 ag SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000 4 e 5 SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 F 8 SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 J SPI1BUF 0248 SPI1 Transmit and Receive Buffer 0000 2 SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000 5 SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 6 SPI2CON2 0264 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 D SPI2BUF 0268 SPI2 Transmit and Receive Buffer 0000 SPI3STAT 0280 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000 A SPI3CON1 0282 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 2 SPI3CON2 0284 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 1 SPI3BUF 0288 SPI3 Transmit and Receive Buffer 0000 0 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F TABLE 4-13: PORTA REGISTER MAP(1) A File All M Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit 1 Bit 0 Name Resets I TRISA 02C0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF L PORTA 02C2 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx Y LATA 02C4 LATA15 LATA14 — — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx ODCA 02C6 ODA15 ODA14 — — — ODA10 ODA9 — ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Note 1: PORTA and all associated bits are unimplemented on 64-pin devices and read as ‘0’. Bits are available on 100-pin devices only, unless otherwise noted. TABLE 4-14: PORTB REGISTER MAP  File All 2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 0 TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF M ic PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx roc LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx h ip ODCB 02CE ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 T e Legend: Reset values are shown in hexadecimal. c h n o lo g y In c .

 TABLE 4-15: PORTC REGISTER MAP 2 0 1 0 M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4(1) Bit 3(1) Bit 2(1) Bit 1(1) Bit 0 ReAslel ts ic roc TRISC 02D0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F01E h ip PORTC 02D2 RC15(2,3) RC14 RC13 RC12(2) — — — — — — — RC4 RC3 RC2 RC1 — xxxx T e LATC 02D4 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 — xxxx c hn ODCC 02D6 ODC15 ODC14 ODC13 ODC12 — — — — — — — ODC4 ODC3 ODC2 ODC1 — 0000 o lo Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. gy Note 1: Bits are unimplemented in 64-pin devices; read as ‘0’. Inc 23:: RRCC1125 aisn odn RlyC a1v5a ialareb leo nwlyh eanva tihlaeb PleO wShCeMn Dth<e1 p:0r>im Caoryn foigsucrilalatitoonr ibsi tdsis=a b1le1d oorr w0h0e ann Ed Cth me oOdSeC isIO sFeNle cCteodn f(iPguOrSatCioMn Db<it 1=:0 1>. Configuration bits= 11 or 00); otherwise read as ‘0’. . TABLE 4-16: PORTD REGISTER MAP File Addr Bit 15(1) Bit 14(1) Bit 13(1) Bit 12(1) Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Name Resets TRISD 02D8 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF PORTD 02DA RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx P LATD 02DC LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx I C ODCD 02DE ODD15 ODD14 ODD13 ODD12 ODD11 ODD10 ODD9 ODD8 ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. 2 Note 1: Bits are unimplemented in 64-pin devices; read as ‘0’. 4 TABLE 4-17: PORTE REGISTER MAP F J File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9(1) Bit 8(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 2 Name Resets 5 TRISE 02E0 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF 6 PORTE 02E2 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx D LATE 02E4 — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx ODCE 02E6 — — — — — — ODE9 ODE8 ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 ODE0 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. 2 Note 1: Bits are unimplemented in 64-pin devices; read as ‘0’. 1 0 F D A S 3 99 M 6 9 B -p IL a g e 5 Y 9

D P S TABLE 4-18: PORTF REGISTER MAP 3 9 I 9 C 69 File Addr Bit 15 Bit 14 Bit 13(1) Bit 12(1) Bit 11 Bit 10 Bit 9 Bit 8(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2(1) Bit 1 Bit 0 All B-p Name Resets 2 ag TRISF 02E8 — — TRISF13 TRISF12 — — — TRISF8 TRISF7 — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31BF 4 e 6 PORTF 02EA — — RF13 RF12 — — — RF8 RF7 — RF5 RF4 RF3 RF2 RF1 RF0 xxxx F 0 LATF 02EC — — LATF13 LATF12 — — — LATF8 LATF7 — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx J ODCF 02EE — — ODF13 ODF12 — — — ODF8 ODF7 — ODF5 ODF4 ODF3 ODF2 ODF1 ODF0 0000 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Note 1: Bits are unimplemented in 64-pin devices; read as ‘0’. 5 6 TABLE 4-19: PORTG REGISTER MAP D A File Addr Bit 15(1) Bit 14(1) Bit 13(1) Bit 12(1) Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1(1) Bit 0(1) All Name Resets 2 TRISG 02F0 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF 1 PORTG 02F2 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx 0 LATG 02F4 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx F ODCG 02F6 ODG15 ODG14 ODG13 ODG12 — — ODG9 ODG8 ODG7 ODG6 — — ODG3 ODG2 ODG1 ODG0 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Note 1: Bits are unimplemented in 64-pin devices; read as ‘0’. M TABLE 4-20: PAD CONFIGURATION REGISTER MAP I L File All Y Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets PADCFG1 02FC — — — — — — — — — — — — — — RTSECSEL PMPTTL(1) 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Bits are unimplemented in 64-pin devices; read as ‘0’.  2 0 1 0 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-21: ADC REGISTER MAP 2 0 1 0 M File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All ic Name Resets ro c ADC1BUF0 0300 ADC Data Buffer 0 xxxx h ip ADC1BUF1 0302 ADC Data Buffer 1 xxxx T e ADC1BUF2 0304 ADC Data Buffer 2 xxxx c h n ADC1BUF3 0306 ADC Data Buffer 3 xxxx o lo ADC1BUF4 0308 ADC Data Buffer 4 xxxx g y In ADC1BUF5 030A ADC Data Buffer 5 xxxx c. ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC Data Buffer 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8 xxxx ADC1BUF9 0312 ADC Data Buffer 9 xxxx ADC1BUFA 0314 ADC Data Buffer 10 xxxx ADC1BUFB 0316 ADC Data Buffer 11 xxxx ADC1BUFC 0318 ADC Data Buffer 12 xxxx P ADC1BUFD 031A ADC Data Buffer 13 xxxx I ADC1BUFE 031C ADC Data Buffer 14 xxxx C ADC1BUFF 031E ADC Data Buffer 15 xxxx 2 ADC1BUF10 0340 ADC Data Buffer 16 xxxx 4 ADC1BUF11 0342 ADC Data Buffer 17 xxxx F ADC1BUF12 0344 ADC Data Buffer 18 xxxx J ADC1BUF13 0346 ADC Data Buffer 19 xxxx ADC1BUF14 0348 ADC Data Buffer 20 xxxx 2 ADC1BUF15 034A ADC Data Buffer21 xxxx 5 ADC1BUF16 034C ADC Data Buffer 22 xxxx 6 ADC1BUF17 034E ADC Data Buffer 23 xxxx D ADC1BUF18 0350 ADC Data Buffer 24 xxxx A ADC1BUF19 0352 ADC Data Buffer 25 xxxx ADC1BUF1A 0354 ADC Data Buffer 26 xxxx 2 ADC1BUF1B 0356 ADC Data Buffer 27 xxxx 1 ADC1BUF1C 0358 ADC Data Buffer 28 xxxx 0 ADC1BUF1D 035A ADC Data Buffer 29 xxxx F ADC1BUF1E 035C ADC Data Buffer 30 xxxx D A S ADC1BUF1F 035E ADC Data Buffer 31 xxxx 3 99 Legend: — = unimplemented, read as ‘0’, r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal. M 69 Note 1: Unimplemented in 64-pin devices, read as ‘0’ B -p IL a g e 6 Y 1

D TABLE 4-21: ADC REGISTER MAP (CONTINUED) P S 3 9 I 9 File All C 6 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Name Resets B -pa AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000 2 g 4 e AD1CON2 0322 VCFG2 VCFG1 VCFG0 r — CSCNA — — BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 6 F 2 AD1CON3 0324 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 J AD1CHS 0328 CH0NB — — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 AD1CSSH 032E — — — — CSSL27 CSSL26 CSSL25 CSSL24 CSSL23(1) CSSL22(1) CSSL21(1) CSSL20(1) CSSL19(1) CSSL18(1) CSSL17(1) CSSL16(1) 0000 2 AD1CSSL 0330 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 5 Legend: — = unimplemented, read as ‘0’, r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal. 6 Note 1: Unimplemented in 64-pin devices, read as ‘0’ D A TABLE 4-22: CTMU REGISTER MAP 2 File All 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 0 CTMUCON 033C CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 F CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M I L Y  2 0 1 0 M ic ro c h ip T e c h n o lo g y In c .

 T ABLE 4-23: USB OTG REGISTER MAP 2 0 1 0 File All M Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ic roc U1OTGIR(2) 0480 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000 h ip U1OTGIE(2) 0482 — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE 0000 Te U1OTGSTAT2) 0484 — — — — — — — — ID — LSTATE — SESVD SESEND — VBUSVD 0000 c hn U1OTGCON(2) 0486 — — — — — — — — DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000 o lo U1PWRC 0488 — — — — — — — — UACTPND — — USLPGRD — — USUSPND USBPWR 0000 g y Inc U1IR 048A(1) —— —— —— —— —— —— —— —— SSTTAALLLLIIFF ATTA—CHIF(1) RREESSUUMMEEIIFF IIDDLLEEIIFF TTRRNNIIFF SSOOFFIIFF UUEERRRRIIFF DEUTRASCTHIIFF(1) 00000000 . U1IE 048C(1) — — — — — — — — STALLIE — RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE 0000 — — — — — — — — STALLIE ATTACHIE(1) RESUMEIE IDLEIE TRNIE SOFIE UERRIE DETACHIE(1) 0000 U1EIR 048E(1) — — — — — — — — BTSEF — DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0000 — — — — — — — — BTSEF — DMAEF BTOEF DFN8EF CRC16EF EOFEF(1) PIDEF 0000 U1EIE 0490(1) — — — — — — — — BTSEE — DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0000 — — — — — — — — BTSEE — DMAEE BTOEE DFN8EE CRC16EE EOFEE(1) PIDEE 0000 P U1STAT 0492 — — — — — — — — ENDPT3 ENDPT2 ENDPT1 ENDPT0 DIR PPBI — — 0000 U1CON 0494(1) — — — — — — — — — SE0 PKTDIS — HOSTEN RESUME PPBRST USBEN 0000 IC — — — — — — — — JSTATE(1) SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN(1) 0000 U1ADDR 0496 — — — — — — — — LSPDEN(1) USB Device Address (DEVADDR) Register 0000 2 4 U1BDTP1 0498 — — — — — — — — Buffer Descriptor Table Base Address Register — 0000 U1FRML 049A — — — — — — — — Frame Count Register Low Byte 0000 F U1FRMH 049C — — — — — — — — — — — — — Frame Count Register High Byte 0000 J U1TOK(2) 049E — — — — — — — — PID3 PID2 PID1 PID0 EP3 EP2 EP1 EP0 0000 2 U1SOF(2) 04A0 — — — — — — — — Start-Of-Frame Count Register 0000 5 U1CNFG1 04A6 — — — — — — — — UTEYE UOEMON — USBSIDL — — PPB1 PPB0 0000 6 U1CNFG2 04A8 — — — — — — — — — — UVCMPSEL PUVBUS EXTI2CEN UVBUSDIS UVCMPDIS UTRDIS 0000 D U1EP0 04AA — — — — — — — — LSPD(1) RETRYDIS(1) — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 A U1EP1 04AC — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 U1EP2 04AE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 2 U1EP3 04B0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 1 U1EP4 04B2 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 0 U1EP5 04B4 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 F U1EP6 04B6 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 DS U1EP7 04B8 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 A 3 99 U1EP8 04BA — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 M 6 9 U1EP9 04BC — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 B -p Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IL a Note 1: Alternate register or bit definitions when the module is operating in Host mode. g e 6 2: This register is available in Host mode only. Y 3

D TABLE 4-23: USB OTG REGISTER MAP (CONTINUED) P S 3 9 I 9 File All C 6 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Name Resets B -pa U1EP10 04BE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 2 g 4 e U1EP11 04C0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 6 F 4 U1EP12 04C2 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 J U1EP13 04C4 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 U1EP14 04C6 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 2 U1EP15 04C8 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 5 U1PWMRRS 04CC USB Power Supply PWM Duty Cycle Register USB Power Supply PWM Period Register 0000 6 U1PWMCON 04CE PWMEN — — — — — PWMPOL CNTEN — — — — — — — — 0000 D Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A Note 1: Alternate register or bit definitions when the module is operating in Host mode. 2: This register is available in Host mode only. 2 1 TABLE 4-24: ANCFG REGISTER MAP 0 File All F Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets A ANCFG 04DE — — — — — — — — — — — — — VBG6EN VBG2EN VBGEN 0000 M Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I L TABLE 4-25: ANSEL REGISTER MAP Y File All Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets(2) ANSA(1) 04E0 — — — — — ANSA10(1) ANSA9(1) — ANSA7(1) ANSA6(1) — — — — — — 06C0 ANSB 04E2 ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9 ANSB8 ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 FFFF ANSC 04E4 — ANSC14 ANSC13 — — — — — — — — ANSC4(1) — — — — 6010 ANSD 04E6 — — — — — — — — ANSD7 ANSD6 — — — — — — 00C0  2 ANSE(1) 04E8 — — — — — — ANSE9(1) — — — — — — — — — 0200 01 ANSF 04EA — — — — — — — — — — — — — — — ANSF0 0001 0 M ANSG 04EC — — — — — — ANSG9 ANSG8 ANSG7 ANSG6 — — — — — — 03C0 icroc LNeogteend:1: —Un i=m upnleimmpelnetmede ninte 6d4, -rpeiand d aesv i‘c0e’.s R, reesaedt avas lu‘0e’.s are shown in hexadecimal. hip 2: Reset values are valid for 100-pin devices only. T e c h n o lo g y In c .

 TABLE 4-26: ENHANCED PARALLEL MASTER/SLAVE PORT REGISTER MAP(1) 2 0 1 0 File All M Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ic roc PMCON1 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 — MODE1 MODE0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0 0000 h ip PMCON2 0602 BUSY — ERROR TIMEOUT AMREQ CURMST MSTSEL1 MSTSEL0 RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16 0000 T e PMCON3 0604 PTWREN PTRDEN PTBE1EN PTBE0EN — AWAITM1 AWAITM0 AWAITE — PTEN22 PTEN21 PTEN20 PTEN19 PTEN18 PTEN17 PTEN16 0000 c hn PMCON4 0606 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 o lo PMCS1CF 0608 CSDIS CSP CSPTEN BEP — WRSP RDSP SM ACKP PTSZ1 PTSZ0 — — — — — 0000 g y In PMCS1BS 060A BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 BASE15 — — — BASE11 — — — 0200 c PMCS1MD 060C ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000 . PMCS2CF 060E CSDIS CSP CSPTEN BEP — WRSP RDSP SM ACKP PTSZ1 PTSZ0 — — — — — 0000 PMCS2BS 0610 BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 BASE15 — — — BASE11 — — — 0600 PMCS2MD 0612 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000 PMDOUT1 0614 EPMP Data Out Register 1<15:8> EPMP Data Out Register 1<7:0> xxxx PMDOUT2 0616 EPMP Data Out Register 2<15:8> EPMP Data Out Register 2<7:0> xxxx PMDIN1 0618 EPMP Data In Register 1<15:8> EPMP Data In Register 1<7:0> xxxx P PMDIN2 061A EPMP Data In Register 2<15:8> EPMP Data In Register 2<7:0> xxxx I PMSTAT 061C IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F C Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Unimplemented in 64-pin devices, read as ‘0’. 2 4 F TABLE 4-27: REAL-TIME CLOCK AND CALENDAR REGISTER MAP J File All 2 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 5 ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<1:0> xxxx 6 ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 D RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<1:0> xxxx A RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 (Note 1) Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 Note 1: The status of the RCFGCAL register on POR is ‘0000’ and on other Resets is unchanged. 1 0 F D A S 3 99 M 6 9 B -p IL a g e 6 Y 5

D T ABLE 4-28: COMPARATORS REGISTER MAP P S 3 9 I 9 C 6 File All 9B Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets -p 2 ag CMSTAT 0630 CMIDL — — — C3EVT C2EVT C1EVT — — — — — C3OUT C2OUT C1OUT 0000 4 e 6 CVRCON 0632 — — — — — CVREFP CVREFM1 CVREFM0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 F 6 CM1CON 0634 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 J CM2CON 0636 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 2 CM3CON 0638 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 5 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 TABLE 4-29: CRC REGISTER MAP D A File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 2 CRCCON1 0640 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0040 1 CRCCON2 0642 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 0000 0 CRCXORL 0644 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 — 0000 F CRCXORH 0646 X31 X30 X29 X28 X27 X26 X25 X24 X23 X22 X21 X20 X19 X18 X17 X16 0000 CRCDATL 0648 CRC Data Input Register Low 0000 A CRCDATH 064A CRC Data Input Register High 0000 M CRCWDATL 064C CRC Result Register Low 0000 I CRCWDATH 064E CRC Result Register High 0000 L Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Y  2 0 1 0 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP 2 0 1 0 File All M Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ic roc RPINR0 0680 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — — — 3F00 h ip RPINR1 0682 — — INT3R5 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 3F3F T e RPINR2 0684 — — — — — — — — — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 003F c hn RPINR3 0686 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 3F3F o lo RPINR4 0688 — — T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 3F3F g y In RPINR7 068E — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 3F3F c RPINR8 0690 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 3F3F . RPINR9 0692 — — IC6R5 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 — — IC5R5 IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 3F3F RPINR10 0694 — — IC8R5 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 — — IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 3F3F RPINR11 0696 — — OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 3F3F RPINR15 069E — — IC9R5 IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 — — — — — — — — 3F00 RPINR17 06A2 — — U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 — — — — — — — — 3F00 RPINR18 06A4 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 3F3F P RPINR19 06A6 — — U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 — — U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 3F3F I RPINR20 06A8 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 3F3F C RPINR21 06AA — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 3F3F 2 RPINR22 06AC — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 3F3F 4 RPINR23 06AE — — — — — — — — — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 003F RPINR27 06B6 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 3F3F F RPINR28 06B8 — — SCK3R5 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 — — SDI3R5 SDI3R4 SDI3R3 SDI3R2 SDI3R1 SDI3R0 3F3F J RPINR29 06BA — — — — — — — — — — SS3R5 SS3R4 SS3R3 SS3R2 SS3R1 SS3R0 003F 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 5 Note 1: Bits are unimplemented in 64-pin devices; read as ‘0’. 6 D A 2 1 0 F D A S 3 99 M 6 9 B -p IL a g e 6 Y 7

D TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) P S 3 9 I 9 File All C 6 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Name Resets B -pa RPOR0 06C0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 2 g 4 e RPOR1 06C2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 68 RPOR2 06C4 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000 F J RPOR3 06C6 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000 RPOR4 06C8 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 0000 2 RPOR5 06CA — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000 5 RPOR6 06CC — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000 6 RPOR7 06CE — — RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000 D RPOR8 06D0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 0000 A RPOR9 06D2 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 0000 2 RPOR10 06D4 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000 RPOR11 06D6 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 0000 1 RPOR12 06D8 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 0000 0 RPOR13 06DA — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 0000 F RPOR14 06DC — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 0000 RPOR15(1) 06DE — — RP31R5(1) RP31R4(1) RP31R3(1) RP31R2(1) RP31R1(1) RP31R0(1) — — RP30R5(1) RP30R4(1) RP30R3(1) RP30R2(1) RP30R1(1) RP30R0(1) 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M Note 1: Bits are unimplemented in 64-pin devices; read as ‘0’. I L Y  2 0 1 0 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-31: GRAPHICS REGISTER MAP 2 0 1 0 M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ic roc G1CMDL 0700 Graphics Command Register<15:0> 0000 h ip G1CMDH 0702 Graphics Command Register<31:16> 0000 T e G1CON1 0704 G1EN — G1SIDL GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0 PUBPP2 PUBPP1 PUBPP0 GCMDCNT4 GCMDCNT3 GCMDCNT2 GCMDCNT1 GCMDCNT0 0000 c hn G1STAT 0706 PUBUSY — — — — — — — IPUBUSY RCCBUSY CHRBUSY VMRGN HMRGN CMDLV CMDFUL CMDMPT 0000 o lo G1IE 0708 PUIE — — — — — — — IPUIE RCCIE CHRIE VMRGNIE HMRGNIE CMDLVIE CMDFULIE CMDMPTIE 0000 g y In G1IR 070A PUIF — — — — — — — IPUIF RCCIF CHRIF VMRGNIF HMRGNIF CMDLVIF CMDFULIF CMDMPTIF 0000 c G1W1ADRL 070C GPU Work Area 1 Start Address Register<15:0> 0000 . G1W1ADRH 070E — — — — — — — — GPU Work Area 1 Start Address Register<23:16> 0000 G1W2ADRL 0710 GPU Work Area 2 Start Address Register<15:0> 0000 G1W2ADRH 0712 — — — — — — — — GPU Work Area 2 Start Address Register<23:16> 0000 G1PUW 0714 — — — — — GPU Work Area Width Register 0000 G1PUH 0716 — — — — — GPU Work Area Height Register 0000 G1DPADRL 0718 Display Buffer Start Address Register<15:0> 0000 P G1DPADRH 071A — — — — — — — — Display Buffer Start Address Register<23:16> 0000 I G1DPW 071C — — — — — Display Frame Width Register 0000 C G1DPH 071E — — — — — Display Frame Height Register 0000 2 G1DPWT 0720 — — — — — Display Total Width Register 0000 4 G1DPHT 0722 — — — — — Display Total Height Register 0000 F G1CON2 0724 DPGWDTH1 DPGWDTH0 DPSTGER1 DPSTGER0 — — DPTEST1 DPTEST0 DPBPP2 DPBPP1 DPBPP0 — — DPMODE2 DPMODE1 DPMODE0 0000 G1CON3 0726 — — — — — — DPPINOE DPPOWER DPCLKPOL DPENPOL DPVSPOL DPHSPOL DPPWROE DPENOE DPVSOE DPHSOE 0000 J G1ACTDA 0728 Number of Lines Before the First Active Line Register Number of Pixels Before the First Active PIxel Register 0000 2 G1HSYNC 072A HSYNC Pulse-Width Configuration Register HSYNC Start Delay Configuration Register 0000 5 G1VSYNC 072C VSYNC Pulse-Width Configuration Register VSYNC Start Delay Configuration Register 0000 6 G1DBLCON 072E Vertical Blanking Start to First Displayed Line Configuration Regsiter Horizontal Blanking Start to First Displayed Line Configuration Regsiter 0000 D G1CLUT 0730 CLUTEN CLUTBUSY — — — — CLUTTRD CLUTRWEN Color Look-Up Table Memory Address Register 0000 A G1CLUTWR 0732 Color Look-up Table Memory Write Data Register 0000 G1CLUTRD 0734 Color Look-up Table Memory Read Data Register 0000 2 G1MRGN 0736 Vertical Blanking Advance Register Horizontal Blanking Advance Register 0000 1 G1CHRX 0738 — — — — — Current Character X-Coordinate Position Register 0000 0 G1CHRY 073A — — — — — Current Character Y-Coordinate Position Register 0000 F D G1IPU 073C — — — — — — — — — — HUFFERR BLCKERR LENERR WRAPERR IPUDONE BFINAL 0000 A S 3 G1DBEN 073E GDBEN15 GDBEN14 GDBEN13 GDBEN12 GDBEN11 GDBEN10 GDBEN9 GDBEN8 GDBEN7 GDBEN6 GDBEN5 GDBEN4 GDBEN3 GDBEN2 GDBEN1 GDBEN0 0000 99 M 6 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 9 B -p IL a g e 6 Y 9

D T ABLE 4-32: SYSTEM REGISTER MAP P S 3 9 I 9 C 6 File All 9B Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets -p 2 ag RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1 4 e 7 OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCEN OSWEN Note 2 F 0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 CPDIV1 CPDIV0 PLLEN G1CLKSEL — — — — 0100 J CLKDIV2 0746 GCLKDIV6 GCLKDIV5 GCLKDIV4 GCLKDIV3 GCLKDIV2 GCLKDIV1 GCLKDIV0 — — — — — — — — — 0000 2 OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 5 REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000 6 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: The Reset value of the RCON register is dependent on the type of Reset event. See Section6.0 “Resets” for more information. D 2: The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section8.0 “Oscillator Configuration” for more information. A TABLE 4-33: NVM REGISTER MAP 2 1 File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 0 NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) F NVMKEY 0766 — — — — — — — — NVMKEY Register<7:0> 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. M I TABLE 4-34: PMD REGISTER MAP L Y File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD 0000 PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 PMD3 0774 — — — — — CMPMD RTCCMD PMPMD(1) CRCMD — — — U3MD I2C3MD I2C2MD — 0000 PMD4 0776 — — — — — — — — — UPWMMD U4MD — REFOMD CTMUMD LVDMD USB1MD 0000  PMD5 0778 — — — — — — — IC9MD — — — — — — — OC9MD 0000 2 PMD6 077A — — — — — — — — — GFX1MD — — — — — SPI3MD 0000 0 10 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M Note 1: Unimplemented in 64-pin devices, read as ‘0’. ic ro c h ip T e c h n o lo g y In c .

PIC24FJ256DA210 FAMILY 4.2.5 EXTENDED DATA SPACE (EDS) pages, each having 32 Kbytes of data. Mapping of the EDS page into the EDS window is done using the Data The enhancement of the data space in Space Read register (DSRPAG<9:0>) for read opera- PIC24FJ256DA210 family devices has been tions and Data Space Write register (DSWPAG<8:0>) accomplished by a new technique, called the Extended for write operations. Figure4-4 displays the entire EDS Data Space (EDS). space. The EDS includes any additional internal extended Note: Accessing Page 0 in the EDS window will data memory not accessible by the lower 32 Kbytes generate an address error trap as Page 0 data address space, any external memory through is the base data memory (data locations, EPMP and the Program Space Visibility (PSV). 0x0800 to 0x7FFF, in the lower data The extended data space is always accessed through space). the EDS window, the upper half of data space. The entire extended data space is organized into EDS FIGURE 4-4: EXTENDED DATA SPACE Special 0x0000 Function Registers 0x0800 30 KB Data Memory EDS Space 0x8000 0x008000 0x018000 0xFF8000 0x000000 0x7F8000 0x000001 0x7F8001 Internal Extended Memory(1) 0x0187FE 0x018800 32W KinBd EowDS MEInexttmeernondraye(l d1) EAMxcectemersnosaryl EAMxctecemernsoasrly PASrcopcgaercasems PASrcopcgaercasems PASrcopcgaercasems PASrcopcgaercasems using using EPMP(2) EPMP(2) 0xFFFE 0x00FFFE 0x01FFFE 0xFFFFFE 0x007FFE 0x7FFFFE 0x007FFF 0x7FFFFF DSxPAG DSxPAG DSx PAG DSRPAG DSRPAG DSRPAG DSRPAG = 0x001 = 0x003 = 0x1FF = 0x200 = 0x2FF = 0x300 = 0x3FF Extended SRAM(1) (66 KB) EPMP Memory Space(2) Program Memory Note 1: Available only in PIC24FJXXXDA2XX devices. In the PIC24FJXXXDA110 devices, this space can be used to access external memory using EPMP. 2: Available only in PIC24FJXXXDAX10 devices (100-pin).  2010 Microchip Technology Inc. DS39969B-page 71

PIC24FJ256DA210 FAMILY 4.2.5.1 Data Read from EDS Space by setting bit 15 of the working register, assigned with the offset address; then, the contents of the pointed In order to read the data from the EDS space, first, an EDS location can be read. Address Pointer is set up by loading the required EDS page number into the DSRPAG register and assigning Figure4-5 illustrates how the EDS space address is the offset address to one of the W registers. Once the generated for read operations. above assignment is done, the EDS window is enabled FIGURE 4-5: EDS ADDRESS GENERATION FOR READ OPERATIONS Select 1 Wn 9 8 0 DSRPAG Reg 9 Bits 15 Bits 24-Bit EA 0 = Extended SRAM and EPMP Wn<0> is Byte Select When the Most Significant bit (MSBs) of EA is ‘1’ and Note: All read operations from EDS space have DSRPAG<9> = 0, the lower 9 bits of DSRPAG are con- an overhead of one instruction cycle. catenated to the lower 15 bits of EA to form a 24-bit Therefore, a minimum of two instruction EDS space address for read operations. cycles is required to complete an EDS Example4-1 shows how to read a byte, word and read. EDS reads under the REPEAT double-word from EDS. instruction; the first two accesses take three cycles and the subsequent accesses take one cycle. EXAMPLE 4-1: EDS READ CODE IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0002 , w0 mov w0 , DSRPAG ;page 2 is selected for read mov #0x0800 , w1 ;select the location (0x800) to be read bset w1 , #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++] , w2 ;read Low byte mov.b [w1++] , w3 ;read High byte ;Read a word from the selected location mov [w1] , w2 ; ;Read Double - word from the selected location mov.d [w1] , w2 ;two word read, stored in w2 and w3 DS39969B-page 72  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 4.2.5.2 Data Write into EDS Space EDS window is enabled by setting bit 15 of the working register, assigned with the offset address, and the In order to write data to EDS space, such as in EDS accessed location can be written. reads, an Address Pointer is set up by loading the required EDS page number into the DSWPAG register, Figure4-2 illustrates how the EDS space address is and assigning the offset address to one of the W regis- generated for write operations. ters. Once the above assignment is done, then the FIGURE 4-6: EDS ADDRESS GENERATION FOR WRITE OPERATIONS Select 1 Wn 8 0 DSWPAG Reg 9 Bits 15 Bits 24-Bit EA Wn<0> is Byte Select When the MSBs of EA is ‘1’, the lower 9 bits of DSWPAG are concatenated to the lower 15 bits of EA to form a 24-bit EDS address for write operations. Example4-2 shows how to write a byte, word and dou- ble-word to EDS. EXAMPLE 4-2: EDS WRITE CODE IN ASSEMBLY ; Set the EDS page where the data to be written mov #0x0002 , w0 mov w0 , DSWPAG ;page 2 is selected for write mov #0x0800 , w1 ;select the location (0x800) to be written bset w1 , #15 ;set the MSB of the base address, enable EDS mode ;Write a byte to the selected location mov #0x00A5 , w2 mov #0x003C , w3 mov.b w2 , [w1++] ;write Low byte mov.b w3 , [w1++] ;write High byte ;Write a word to the selected location mov #0x1234 , w2 ; mov w2 , [w1] ; ;Write a Double - word to the selected location mov #0x1122 , w2 mov #0x4455 , w3 mov.d w2 , [w1] ;2 EDS writes  2010 Microchip Technology Inc. DS39969B-page 73

PIC24FJ256DA210 FAMILY The page registers (DSRPAG/DSWPAG) do not Note1: All write operations to EDS are executed update automatically while crossing a page boundary, in a single cycle. when the rollover happens from 0xFFFF to 0x8000. While developing code in assembly, care must be taken 2: Use of Read/Modify/Write operation on to update the page registers when an Address Pointer any EDS location under a REPEAT crosses the page boundary. The ‘C’ compiler keeps instruction is not supported. For example, track of the addressing, and increments or decrements BCLR, BSW, BTG, RLC f, RLNC f, the page registers accordingly while accessing RRC f, RRNC f, ADD f, SUB f, contiguous data memory locations. SUBR f, AND f, IOR f, XOR f, ASR f, ASL f. 3: Use the DSRPAG register while performing Read/Modify/Write operation. TABLE 4-35: EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES DSWPAG Source/Destination 24-Bit EA DSRPAG (Data Space Write Address while Pointing to Comment (Data Space Read Register) Register) Indirect Addressing EDS x(1) x(1) 0x0000 to 0x1FFF 0x000000 to Near data 0x001FFF space(2) 0x2000 to 0x7FFF 0x002000 to 0x007FFF 0x001 0x001 0x008000 to 0x00FFFE 0x002 0x002 0x010000 to 32 Kbytes on 0x017FFE each page 0x003 0x003 0x018000 to Only 2 Kbytes 0x8000 to 0xFFFF 0x0187FE of extended SRAM on this page 0x004 0x004 0x018800 to 0x027FFE • • • EPMP • • • memory • • • space(4) 0x1FF 0x1FF 0xFF8000 to 0xFFFFFE 0x000 0x000 Invalid Address Address error trap(3) Note 1: If the source/destination address is below 0x8000, the DSRPAG and DSWPAG registers are not considered. 2: This data space can also be accessed by Direct Addressing. 3: When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is ‘0’, an address error trap will occur. 4: EPMP memory space can start from location, 0x008000, in the parts with 24 Kbytes of data memory (PIC24FJXXXDA1XX) DS39969B-page 74  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 4.2.6 SOFTWARE STACK 4.3 Interfacing Program and Data Memory Spaces Apart from its use as a working register, the W15 register in PIC24F devices is also used as a Software The PIC24F architecture uses a 24-bit wide program Stack Pointer (SSP). The pointer always points to the space and 16-bit wide data space. The architecture is first available free word and grows from lower to higher also a modified Harvard scheme, meaning that data addresses. It pre-decrements for stack pops and can also be present in the program space. To use this post-increments for stack pushes, as shown in data successfully, it must be accessed in a way that Figure4-7. Note that for a PC push during any CALL preserves the alignment of information in both spaces. instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be Note: A PC push during exception processing accessed during operation: will concatenate the SRL register to the • Using table instructions to access individual bytes MSB of the PC prior to the push. or words anywhere in the program space The Stack Pointer Limit Value register (SPLIM), associ- • Remapping a portion of the program space into ated with the Stack Pointer, sets an upper address the data space (program space visibility) boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is Table instructions allow an application to read or write forced to ‘0’ as all stack operations must be to small areas of the program memory. This makes the word-aligned. Whenever an EA is generated using method ideal for accessing data tables that need to be W15 as a source or destination pointer, the resulting updated from time to time. It also allows access to all address is compared with the value in SPLIM. If the bytes of the program word. The remapping method contents of the Stack Pointer (W15) and the SPLIM reg- allows an application to access a large block of data on ister are equal, and a push operation is performed, a a read-only basis, which is ideal for look ups from a stack error trap will not occur. The stack error trap will large table of static data. It can only access the least occur on a subsequent push operation. Thus, for significant word of the program word. example, if it is desirable to cause a stack error trap 4.3.1 ADDRESSING PROGRAM SPACE when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is Similarly, a Stack Pointer underflow (stack error) trap is needed to create a 23-bit or 24-bit program address generated when the Stack Pointer address is found to from 16-bit data registers. The solution depends on the be less than 0800h. This prevents the stack from interface method to be used. interfering with the SFR space. For table operations, the 8-bit Table Memory Page A write to the SPLIM register should not be immediately Address register (TBLPAG) is used to define a 32Kword followed by an indirect read operation using W15. region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space FIGURE 4-7: CALL STACK FRAME address. In this format, the MSBs of TBLPAG is used to 0000h 15 0 determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). ds For remapping operations, the 10-bit Extended Data arss we Space Read register (DSRPAG) is used to define a ows Toer Addr PC<15:0> W15 (before CALL) 1S6igKniwficoardn tp baitg (eM iSn bth) eo f pthroeg EraAm is s ‘1pa’, caen.d W thhee Mn Sthbe ( bMito9s)t ck GrHigh 00000<0F0re0e0 WPoCrd<>22:16> W15 (after CALL) of DSRPAG is ‘1’, the lower 8 bits of DSRPAG are con- a catenated with the lower 15 bits of the EA to form a St 23-bit program space address. The DSRPAG<8> bit POP : [--W15] PUSH: [W15++] decides whether the lower word (when bit is ‘0’) or the higher word (when bit is ‘1’) of program memory is mapped. Unlike table operations, this strictly limits remapping operations to the user memory area. Table4-36 and Figure4-8 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word.  2010 Microchip Technology Inc. DS39969B-page 75

PIC24FJ256DA210 FAMILY TABLE 4-36: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 DSRPAG<7:0>(2) Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is DSRPAG<0>. 2: DSRPAG<9> is always ‘1’ in this case. DSRPAG<8> decides whether the lower word or higher word of program memory is read. When DSRPAG<8> is ‘0’, the lower word is read and when it is ‘1’, the higher word is read. FIGURE 4-8: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select 1 EA 1/0 Program Space Visibility(1) 0 DSRPAG<7:0> (Remapping) 1-Bit 8 Bits 15 Bits 23 Bits User/Configuration Byte Select Space Select Note 1: DSRPAG<8> acts as word select. DSRPAG<9> should always be ‘1’ to map program memory to data memory. 2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the lower word. Table read operations are permitted in the configuration memory space. DS39969B-page 76  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM 2. TBLRDH (Table Read High): In Word mode, it MEMORY USING TABLE maps the entire upper word of a program address INSTRUCTIONS (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. The TBLRDL and TBLWTL instructions offer a direct In Byte mode, it maps the upper or lower byte of method of reading or writing the lower word of any the program word to D<7:0> of the data address within the program space without going through address, as above. Note that the data will data space. The TBLRDH and TBLWTH instructions are always be ‘0’ when the upper ‘phantom’ byte is the only method to read or write the upper 8 bits of a selected (byte select = 1). program space word as data. In a similar fashion, two table instructions, TBLWTH The PC is incremented by two for each successive and TBLWTL, are used to write individual bytes or 24-bit program word. This allows program memory words to a program space address. The details of addresses to directly map to data space addresses. their operation are described in Section5.0 “Flash Program memory can thus be regarded as two, 16-bit Program Memory”. word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL For all table operations, the area of program memory access the space which contains the least significant space to be accessed is determined by the Table data word, and TBLRDH and TBLWTH access the space Memory Page Address register (TBLPAG). TBLPAG which contains the upper data byte. covers the entire program memory space of the device, including user and configuration spaces. When Two table instructions are provided to move byte or TBLPAG<7> = 0, the table page is located in the user word-sized (16-bit) data to and from program space. memory space. When TBLPAG<7> = 1, the page is Both function as either byte or word operations. located in configuration space. 1. TBLRDL (Table Read Low): In Word mode, it Note: Only table read operations will execute in maps the lower word of the program space the configuration memory space, where location (P<15:0>) to a data address (D<15:0>). Device IDs are located. Table write In Byte mode, either the upper or lower byte of operations are not allowed. the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. FIGURE 4-9: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG Data EA<15:0> 02 23 15 0 000000h 23 16 8 0 00000000 00000000 020000h 00000000 030000h 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 800000h Only read operations are shown; write operations are also valid in the user memory area.  2010 Microchip Technology Inc. DS39969B-page 77

PIC24FJ256DA210 FAMILY 4.3.3 READING DATA FROM PROGRAM Table4-37 provides the corresponding 23-bit EDS MEMORY USING EDS address for program memory with EDS page and source addresses. The upper 32Kbytes of data space may optionally be mapped into any 16Kword page of the program space. For operations that use PSV and are executed outside This provides transparent access of stored constant a REPEAT loop, the MOV and MOV.D instructions will data from the data space without the need to use require one instruction cycle in addition to the specified special instructions (i.e., TBLRDL/H). execution time. All other instructions will require two instruction cycles in addition to the specified execution Program space access through the data space occurs time. when the MSb of EA is ‘1’ and the DSRPAG<9> is also ‘1’. The lower 8 bits of DSRPAG are concatenated to the For operations that use PSV, which are executed inside Wn<14:0> bits to form a 23-bit EA to access program a REPEAT loop, there will be some instances that memory. The DSRPAG<8> decides which word should require two instruction cycles in addition to the be addressed; when the bit is ‘0’, the lower word and specified execution time of the instruction: when ‘1’, the upper word of the program memory is • Execution in the first iteration accessed. • Execution in the last iteration The entire program memory is divided into 512 EDS • Execution prior to exiting the loop due to an pages, from 0x200 to 0x3FF, each consisting of 16K interrupt words of data. Pages, 0x200 to 0x2FF, correspond to • Execution upon re-entering the loop after an the lower words of the program memory, while 0x300 to interrupt is serviced 0x3FF correspond to the upper words of the program memory. Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a Using this EDS technique, the entire program memory single cycle. can be accessed. Previously, the access to the upper word of the program memory was not supported. TABLE 4-37: EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES Source Address DSRPAG while Indirect 23-Bit EA Pointing to EDS Comment (Data Space Read Register) Addressing 0x200 0x000000 to 0x007FFE Lower words of 4M • • program instructions; • • (8 Mbytes) for read • • operations only. 0x2FF 0x8000 to 0xFFFF 0x7F8000 to 0x7FFFFE 0x300 0x000001 to 0x007FFF Upper words of 4M • • program instructions (4 Mbytes remaining, • • 4 Mbytes are phantom • • bytes) for read 0x3FF 0x7F8001 to 0x7FFFFF operations only. 0x000 Invalid Address Address error trap(1) Note 1: When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is ‘0’, an address error trap will occur. DS39969B-page 78  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD When DSRPAG<9:8> = 10 and EA<15> = 1 Program Space Data Space DSRPAG 23 15 0 202h 000000h 0000h Data EA<14:0> 010000h 017FFEh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... 8000h EDS Window ...while the lower 15bits of the EA specify an exact FFFFh address within the EDS area. This corre- sponds exactly to the same lower 15 bits of the actual program 7FFFFEh space address. FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS HIGHER WORD When DSRPAG<9:8> = 11 and EA<15> = 1 Program Space Data Space DSRPAG 23 15 0 302h 000000h 0000h Data EA<14:0> 010001h 017FFFh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... 8000h EDS Window ...while the lower 15bits of the EA specify an exact FFFFh address within the EDS area. This corre- sponds exactly to the same lower 15 bits of the actual program 7FFFFEh space address.  2010 Microchip Technology Inc. DS39969B-page 79

PIC24FJ256DA210 FAMILY EXAMPLE 4-3: EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0202 , w0 mov w0 , DSRPAG ;page 0x202, consisting lower words, is selected for read mov #0x000A , w1 ;select the location (0x0A) to be read bset w1 , #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++] , w2 ;read Low byte mov.b [w1++] , w3 ;read High byte ;Read a word from the selected location mov [w1] , w2 ; ;Read Double - word from the selected location mov.d [w1] , w2 ;two word read, stored in w2 and w3 DS39969B-page 80  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 5.0 FLASH PROGRAM MEMORY microcontroller just before shipping the product. This also allows the most recent firmware or a custom Note: This data sheet summarizes the features firmware to be programmed. of this group of PIC24F devices. It is not RTSP is accomplished using TBLRD (table read) and intended to be a comprehensive reference TBLWT (table write) instructions. With RTSP, the user source. For more information, refer to the may write program memory data in blocks of 64 instruc- “PIC24F Family Reference Manual”, tions (192 bytes) at a time and erase program memory Section 4. “Program Memory” in blocks of 512 instructions (1536 bytes) at a time. (DS39715). The information in this data sheet supersedes the information in the 5.1 Table Instructions and Flash FRM. Programming The PIC24FJ256DA210 family of devices contains internal Flash program memory for storing and execut- Regardless of the method used, all programming of ing application code. The program memory is readable, Flash memory is done with the table read and write writable and erasable. The Flash can be programmed instructions. These allow direct read and write access to in four ways: the program memory space from the data memory while the device is in normal operating mode. The 24-bit target • In-Circuit Serial Programming™ (ICSP™) address in the program memory is formed using the • Run-Time Self-Programming (RTSP) TBLPAG<7:0> bits and the Effective Address (EA) from • JTAG a W register, specified in the table instruction, as shown • Enhanced In-Circuit Serial Programming in Figure5-1. (Enhanced ICSP) The TBLRDL and the TBLWTL instructions are used to ICSP allows a PIC24FJ256DA210 family device to be read or write to bits<15:0> of program memory. serially programmed while in the end application circuit. TBLRDL and TBLWTL can access program memory in This is simply done with two lines for the programming both Word and Byte modes. clock and programming data (named PGECx and The TBLRDH and TBLWTH instructions are used to read PGEDx, respectively), and three other lines for power or write to bits<23:16> of program memory. TBLRDH (VDD), ground (VSS) and Master Clear (MCLR). This and TBLWTH can also access program memory in Word allows customers to manufacture boards with or Byte mode. unprogrammed devices and then program the FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program 0 Program Counter 0 Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2010 Microchip Technology Inc. DS39969B-page 81

PIC24FJ256DA210 FAMILY 5.2 RTSP Operation 5.3 JTAG Operation The PIC24F Flash program memory array is organized The PIC24F family supports JTAG boundary scan. into rows of 64 instructions or 192 bytes. RTSP allows Boundary scan can improve the manufacturing the user to erase blocks of eight rows (512 instructions) process by verifying pin to PCB connectivity. at a time and to program one row at a time. It is also possible to program single words. 5.4 Enhanced In-Circuit Serial The 8-row erase blocks and single row write blocks are Programming edge-aligned, from the beginning of program memory, on Enhanced In-Circuit Serial Programming uses an boundaries of 1536 bytes and 192 bytes, respectively. on-board bootloader, known as the program executive, When data is written to program memory using TBLWT to manage the programming process. Using an SPI instructions, the data is not written directly to memory. data frame format, the program executive can erase, Instead, data written using table writes is stored in program and verify program memory. For more holding latches until the programming sequence is information on Enhanced ICSP, see the device executed. programming specification. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 5.5 Control Registers 64TBLWT instructions are required to write the full row There are two SFRs used to read and write the of memory. program Flash memory: NVMCON and NVMKEY. To ensure that no data is corrupted during a write, any The NVMCON register (Register5-1) controls which unused address should be programmed with blocks are to be erased, which memory type is to be FFFFFFh. This is because the holding latches reset to programmed and when the programming cycle starts. an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows NVMKEY is a write-only register that is used for write which were not rewritten. protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the The basic sequence for RTSP programming is to set up NVMKEY register. Refer to Section5.6 “Programming a Table Pointer, then do a series of TBLWT instructions Operations” for further details. to load the buffers. Programming is performed by setting the control bits in the NVMCON register. 5.6 Programming Operations Data can be loaded in any order and the holding regis- ters can be written to multiple times before performing A complete programming sequence is necessary for a write operation. Subsequent writes, however, will programming or erasing the internal Flash in RTSP wipe out any previous writes. mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Note: Writing to a location multiple times without Setting the WR bit (NVMCON<15>) starts the opera- erasing is not recommended. tion and the WR bit is automatically cleared when the All of the table write operations are single-word writes operation is finished. (2 instruction cycles), because only the buffers are writ- ten. A programming cycle is required for programming each row. DS39969B-page 82  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/S-0, HC(1) R/W-0(1) R-0, HSC(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: S = Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HC = Hardware Clearable bit bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit(1) 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only; refer to the device programming specification.  2010 Microchip Technology Inc. DS39969B-page 83

PIC24FJ256DA210 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example5-3). 5. Write the program block to Flash memory: The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row a) Set the NVMOP bits to ‘0001’ to configure erase block containing the desired row. The general for row programming. Clear the ERASE bit process is: and set the WREN bit. b) Write 55h to NVMKEY. 1. Read eight rows of program memory (512instructions) and store in data RAM. c) Write AAh to NVMKEY. 2. Update the program data in RAM with the d) Set the WR bit. The programming cycle desired new data. begins and the CPU stalls for the duration of the write cycle. When the write to Flash 3. Erase the block (see Example5-1): memory is done, the WR bit is cleared a) Set the NVMOP bits (NVMCON<3:0>) to automatically. ‘0010’ to configure for block erase. Set the 6. Repeat steps 4 and 5, using the next available ERASE (NVMCON<6>) and WREN 64instructions from the block in data RAM by (NVMCON<14>) bits. incrementing the value in TBLPAG, until all b) Write the starting address of the block to be 512instructions are written back to Flash erased into the TBLPAG and W registers. memory. c) Write 55h to NVMKEY. For protection against accidental operations, the write d) Write AAh to NVMKEY. initiate sequence for NVMKEY must be used to allow e) Set the WR bit (NVMCON<15>). The erase any erase or program operation to proceed. After the cycle begins and the CPU stalls for the dura- programming command has been executed, the user tion of the erase cycle. When the erase is must wait for the programming time until programming done, the WR bit is cleared automatically. is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example5-4. EXAMPLE 5-1: ERASING A PROGRAM MEMORY BLOCK (ASSEMBLY LANGUAGE CODE) ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize Program Memory (PM) Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA<15:0> pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV.B #0x55, W0 MOV W0, NVMKEY ; Write the 0x55 key MOV.B #0xAA, W1 ; MOV W1, NVMKEY ; Write the 0xAA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS39969B-page 84  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE) // C example using MPLAB C30 unsigned long progAddr = 0xXXXXXX; // Address of row to write unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVMCON asm("DISI #5"); // Block all interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // check function to perform unlock // sequence and set WR EXAMPLE 5-3: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 63rd_program_word MOV #LOW_WORD_63, W2 ; MOV #HIGH_BYTE_63, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0] ; Write PM high byte into program latch EXAMPLE 5-4: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV.B #0x55, W0 MOV W0, NVMKEY ; Write the 0x55 key MOV.B #0xAA, W1 ; MOV W1, NVMKEY ; Write the 0xAA key BSET NVMCON, #WR ; Start the programming sequence NOP ; Required delays NOP BTSC NVMCON, #15 ; and wait for it to be BRA $-2 ; completed  2010 Microchip Technology Inc. DS39969B-page 85

PIC24FJ256DA210 FAMILY 5.6.2 PROGRAMMING A SINGLE WORD write latches and specify the lower 16 bits of the pro- OF FLASH PROGRAM MEMORY gram memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits If a Flash location has been erased, it can be pro- (NVMCON<3:0>) to ‘0011’. The write is performed by grammed using table write instructions to write an executing the unlock sequence and setting the WR bit instruction word (24-bit) into the write latch. The (see Example5-5). An equivalent procedure in ‘C’ TBLPAG register is loaded with the 8 Most Significant compiler, using the MPLAB C30 compiler and built-in Bytes (MSB) of the Flash address. The TBLWTL and hardware functions is shown in Example5-6. TBLWTH instructions write the desired data into the EXAMPLE 5-5: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY ; Setup a pointer to data Program Memory MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ;Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address MOV #LOW_WORD_N, W2 ; MOV #HIGH_BYTE_N, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; Setup NVMCON for programming one word to data Program Memory MOV #0x4003, W0 ; MOV W0, NVMCON ; Set NVMOP bits to 0011 DISI #5 ; Disable interrupts while the KEY sequence is written MOV.B #0x55, W0 ; Write the key sequence MOV W0, NVMKEY MOV.B #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR ; Start the write cycle NOP ; Required delays NOP EXAMPLE 5-6: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY (‘C’ LANGUAGE CODE) // C example using MPLAB C30 unsigned int offset; unsigned long progAddr = 0xXXXXXX; // Address of word to program unsigned int progDataL = 0xXXXX; // Data to program lower word unsigned char progDataH = 0xXX; // Data to program upper byte //Set up NVMCON for word programming NVMCON = 0x4003; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); // Write to address low word __builtin_tblwth(offset, progDataH); // Write to upper byte asm(“DISI #5”); // Block interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // C30 function to perform unlock // sequence and set WR DS39969B-page 86  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 6.0 RESETS Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU Note: This data sheet summarizes the features and peripherals are forced to a known Reset state. of this group of PIC24F devices. It is not Most registers are unaffected by a Reset; their status is intended to be a comprehensive reference unknown on POR and unchanged by all other Resets. source. For more information, refer to the “PIC24F Family Reference Manual”, Note: Refer to the specific peripheral or CPU section of this manual for register Reset Section 7. “Reset” (DS39712). The infor- mation in this data sheet supersedes the states. information in the FRM. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset The Reset module combines all Reset sources and (see Register6-1). A POR will clear all bits, except for controls the device Master Reset Signal, SYSRST. The the BOR and POR (RCON<1:0>) bits, which are set. following is a list of device Reset sources: The user may set or clear any bit at any time during • POR: Power-on Reset code execution. The RCON bits only serve as status • MCLR: Pin Reset bits. Setting a particular Reset status bit in software will • SWR: RESET Instruction not cause a device Reset to occur. • WDT: Watchdog Timer Reset The RCON register also has other bits associated with • BOR: Brown-out Reset the Watchdog Timer and device power-saving states. • CM: Configuration Mismatch Reset The function of these bits is discussed in other sections of this data sheet. • TRAPR: Trap Conflict Reset • IOPUWR: Illegal Opcode Reset Note: The status bits in the RCON register • UWR: Uninitialized W Register Reset should be cleared after they are read so that the next RCON register value after a A simplified block diagram of the Reset module is device Reset will be meaningful. shown in Figure6-1. FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise POR Detect SYSRST VDD Brown-out BOR Reset Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2010 Microchip Technology Inc. DS39969B-page 87

PIC24FJ256DA210 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0, HS R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS R/W-0 TRAPR IOPUWR — — — — CM VREGS(3) bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register is used as an Address Pointer and caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred bit 8 VREGS: Voltage Regulator Standby Enable bit(3) 1 = Program memory and regulator remain active during Sleep/Idle 0 = Program memory power is removed and regulator goes to standby during Seep/Idle bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. DS39969B-page 88  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 2 IDLE: Wake-up From Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. TABLE 6-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap Conflict Event POR IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR CM (RCON<9>) Configuration Mismatch Reset POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR WDTO (RCON<4>) WDT Time-out CLRWDT, PWRSAV Instruction, POR SLEEP (RCON<3>) PWRSAV #0 Instruction POR IDLE (RCON<2>) PWRSAV #1 Instruction POR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits may be set or cleared by the user software.  2010 Microchip Technology Inc. DS39969B-page 89

PIC24FJ256DA210 FAMILY 6.1 Special Function Register Reset 6.3 Clock Source Selection at Reset States If clock switching is enabled, the system clock source Most of the Special Function Registers (SFRs) associ- at device Reset is chosen, as shown in Table6-2. If ated with the PIC24F CPU and peripherals are reset to a clock switching is disabled, the system clock source is particular value at a device Reset. The SFRs are always selected according to the oscillator Configura- grouped by their peripheral or CPU function and their tion bits. Refer to the “PIC24F Family Reference Reset values are specified in each section of this manual. Manual”, Section8.0 “Oscillator Configuration” for further details. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers. The TABLE 6-2: OSCILLATOR SELECTION vs. Reset value for the Reset Control register, RCON, will TYPE OF RESET (CLOCK depend on the type of device Reset. The Reset value SWITCHING ENABLED) for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed Reset Type Clock Source Determinant values of the FNOSC bits in Flash Configuration Word2 (CW2) (see Table6-2). The RCFGCAL and POR FNOSC Configuration bits NVMCON registers are only affected by a POR. BOR (CW2<10:8>) MCLR 6.2 Device Reset Times COSC Control bits WDTO (OSCCON<14:12>) The Reset times for various types of device Reset are SWR summarized in Table6-3. Note that the system Reset signal, SYSRST, is released after the POR delay time expires. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The Fail-Safe Clock Monitor (FSCM) delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. DS39969B-page 90  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS System Clock Reset Type Clock Source SYSRST Delay Notes Delay POR(7) EC TPOR + TSTARTUP + TRST — 1, 2, 3 ECPLL TPOR + TSTARTUP + TRST TLOCK 1, 2, 3, 5 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST 1, 2, 3, 4 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK 1, 2, 3, 4, 5 FRC, FRCDIV TPOR + TSTARTUP + TRST TFRC 1, 2, 3, 6, 7 FRCPLL TPOR + TSTARTUP + TRST TFRC + TLOCK 1, 2, 3, 5, 6 LPRC TPOR + TSTARTUP + TRST TLPRC 1, 2, 3, 6 BOR EC TSTARTUP + TRST — 2, 3 ECPLL TSTARTUP + TRST TLOCK 2, 3, 5 XT, HS, SOSC TSTARTUP + TRST TOST 2, 3, 4 XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK 2, 3, 4, 5 FRC, FRCDIV TSTARTUP + TRST TFRC 2, 3, 6, 7 FRCPLL TSTARTUP + TRST TFRC + TLOCK 2, 3, 5, 6 LPRC TSTARTUP + TRST TLPRC 2, 3, 6 MCLR Any Clock TRST — 3 WDT Any Clock TRST — 3 Software Any clock TRST — 3 Illegal Opcode Any Clock TRST — 3 Uninitialized W Any Clock TRST — 3 Trap Conflict Any Clock TRST — 3 Note 1: TPOR = Power-on Reset delay (10 s nominal). 2: TSTARTUP = TVREG (10 s nominal when VREGS = 1 and when VREGS = 0; depends upon WUTSEL<1:0> bits setting). 3: TRST = Internal State Reset time (32s nominal). 4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: TLOCK = PLL lock time. 6: TFRC and TLPRC = RC Oscillator start-up times. 7: If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid. It switches to the primary oscillator after its respective clock delay. 6.3.1 POR AND LONG OSCILLATOR 6.3.2 FAIL-SAFE CLOCK MONITOR START-UP TIMES (FSCM) AND DEVICE RESETS The oscillator start-up circuitry and its associated delay If the FSCM is enabled, it will begin to monitor the timers are not linked to the device Reset delays that system clock source when SYSRST is released. If a occur at power-up. Some crystal circuits (especially valid clock source is not available at this time, the low-frequency crystals) will have a relatively long device will automatically switch to the FRC oscillator start-up time. Therefore, one or more of the following and the user can switch to the desired crystal oscillator conditions is possible after SYSRST is released: in the Trap Service Routine (TSR). • The oscillator circuit has not begun to oscillate. • The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). • The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. There- fore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known.  2010 Microchip Technology Inc. DS39969B-page 91

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 92  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 7.0 INTERRUPT CONTROLLER 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE Note: This data sheet summarizes the features The Alternate Interrupt Vector Table (AIVT) is located of this group of PIC24F devices. It is not after the IVT, as shown in Figure7-1. The ALTIVT intended to be a comprehensive reference (INTCON2<15>) control bit provides access to the source. For more information, refer to the AIVT. If the ALTIVT bit is set, all interrupt and exception “PIC24F Family Reference Manual”, Sec- processes will use the alternate vectors instead of the tion 8. “Interrupts” (DS39707). The infor- default vectors. The alternate vectors are organized in mation in this data sheet supersedes the the same manner as the default vectors. information in the FRM. The AIVT supports emulation and debugging efforts by The PIC24F interrupt controller reduces the numerous providing a means to switch between an application peripheral interrupt request signals to a single interrupt and a support environment without requiring the inter- request signal to the PIC24F CPU. It has the following rupt vectors to be reprogrammed. This feature also features: enables switching between applications for evaluation • Up to 8 processor exceptions and software traps of different software algorithms at run time. If the AIVT • Seven user-selectable priority levels is not needed, the AIVT should be programmed with the same addresses used in the IVT. • Interrupt Vector Table (IVT) with up to 118 vectors • Unique vector for each interrupt or exception 7.2 Reset Sequence source • Fixed priority within a specified user priority level A device Reset is not a true exception because the • Alternate Interrupt Vector Table (AIVT) for debug interrupt controller is not involved in the Reset process. support The PIC24F devices clear their registers in response to a Reset, which forces the PC to zero. The micro- • Fixed interrupt entry and return latencies controller then begins program execution at location, 000000h. The user programs a GOTO instruction at the 7.1 Interrupt Vector Table Reset address, which redirects program execution to The Interrupt Vector Table (IVT) is shown in Figure7-1. the appropriate start-up routine. The IVT resides in program memory, starting at location Note: Any unimplemented or unused vector 000004h. The IVT contains 126 vectors, consisting of locations in the IVT and AIVT should be 8non-maskable trap vectors, plus up to 118 sources of programmed with the address of a default interrupt. In general, each interrupt source has its own interrupt handler routine that contains a vector. Each interrupt vector contains a 24-bit wide RESET instruction. address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt asso- ciated with Vector 0 will take priority over interrupts at any other vector address. PIC24FJ256DA210 family devices implement non-maskable traps and unique interrupts. These are summarized in Table7-1 and Table7-2.  2010 Microchip Technology Inc. DS39969B-page 93

PIC24FJ256DA210 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction 000000h Reset – GOTO Address 000002h Reserved 000004h Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000014h Interrupt Vector 1 — — — Interrupt Vector 52 00007Ch y orit Interrupt Vector 53 00007Eh Interrupt Vector Table (IVT)(1) Pri Interrupt Vector 54 000080h er — d — Or — ural Interrupt Vector 116 0000FCh at Interrupt Vector 117 0000FEh N g Reserved 000100h n Reserved 000102h si a Reserved e cr Oscillator Fail Trap Vector e D Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000114h Interrupt Vector 1 — — — Interrupt Vector 52 00017Ch Interrupt Vector 53 00017Eh Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 54 000180h — — — Interrupt Vector 116 Interrupt Vector 117 0001FEh Start of Code 000200h Note 1: See Table7-2 for the interrupt vector list. TABLE 7-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h Reserved 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved DS39969B-page 94  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector IVT AIVT Interrupt Source Number Address Address Flag Enable Priority ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> CTMU Event 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4> External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0> External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0> External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4> External Interrupt 3 53 00007Eh 00017Eh IFS3<5> IEC3<5> IPC13<6:4> External Interrupt 4 54 000080h 000180h IFS3<6> IEC3<6> IPC13<10:8> Graphics Controller 100 0000DCh 0001DCh IFS6<4> IEC6<4> IPC25<2:0> I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4> I2C1 Slave Event 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0> I2C2 Master Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8> I2C2 Slave Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4> I2C3 Master Event 85 0000BEh 0001BEh IFS5<5> IEC5<5> IPC21<6:4> I2C3 Slave Event 84 0000BCh 0001BCh IFS5<4> IEC5<4> IPC21<2:0> Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4> Input Capture 2 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4> Input Capture 3 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4> Input Capture 4 38 000060h 000160h IFS2<6> IEC2<6> IPC9<10:8> Input Capture 5 39 000062h 000162h IFS2<7> IEC2<7> IPC9<14:12> Input Capture 6 40 000064h 000164h IFS2<8> IEC2<8> IPC10<2:0> Input Capture 7 22 000040h 000140h IFS1<6> IEC1<6> IPC5<10:8> Input Capture 8 23 000042h 000142h IFS1<7> IEC1<7> IPC5<14:12> Input Capture 9 93 0000CEh 0001CEh IFS5<13> IEC5<13> IPC23<6:4> Input Change Notification (ICN) 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12> Low-Voltage Detect (LVD) 72 0000A4h 0001A4h IFS4<8> IEC4<8> IPC18<2:0> Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8> Output Compare 2 6 000020h 000120h IFS0<6> IEC0<6> IPC1<10:8> Output Compare 3 25 000046h 000146h IFS1<9> IEC1<9> IPC6<6:4> Output Compare 4 26 000048h 000148h IFS1<10> IEC1<10> IPC6<10:8> Output Compare 5 41 000066h 000166h IFS2<9> IEC2<9> IPC10<6:4> Output Compare 6 42 000068h 000168h IFS2<10> IEC2<10> IPC10<10:8> Output Compare 7 43 00006Ah 00016Ah IFS2<11> IEC2<11> IPC10<14:12> Output Compare 8 44 00006Ch 00016Ch IFS2<12> IEC2<12> IPC11<2:0> Output Compare 9 92 0000CCh 0001CCh IFS5<12> IEC5<12> IPC23<2:0> Enhanced Parallel Master Port (EPMP)(1) 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4> Real-Time Clock and Calendar (RTCC) 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8> SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4> SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8> SPI2 Error 32 000054h 000154h IFS2<0> IEC2<0> IPC8<2:0> SPI2 Event 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4> SPI3 Error 90 0000C8h 0001C8h IFS5<10> IEC5<10> IPC22<10:8> SPI3 Event 91 0000CAh 0001CAh IFS5<11> IEC5<11> IPC22<14:12> Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06).  2010 Microchip Technology Inc. DS39969B-page 95

PIC24FJ256DA210 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Interrupt Bit Locations Vector IVT AIVT Interrupt Source Number Address Address Flag Enable Priority Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12> Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12> Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0> Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12> Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0> UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4> UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12> UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0> UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8> UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8> UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12> UART3 Error 81 0000B6h 0001B6h IFS5<1> IEC5<1> IPC20<6:4> UART3 Receiver 82 0000B8h 0001B8h IFS5<2> IEC5<2> IPC20<10:8> UART3 Transmitter 83 0000BAh 0001BAh IFS5<3> IEC5<3> IPC20<14:12> UART4 Error 87 0000C2h 0001C2h IFS5<7> IEC5<7> IPC21<14:12> UART4 Receiver 88 0000C4h 0001C4h IFS5<8> IEC5<8> IPC22<2:0> UART4 Transmitter 89 0000C6h 0001C6h IFS5<9> IEC5<9> IPC22<6:4> USB Interrupt 86 0000C0h 0001C0h IFS5<6> IEC5<6> IPC21<10:8> Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06). 7.3 Interrupt Control and Status The IPCx registers are used to set the interrupt priority Registers level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. The PIC24FJ256DA210 family of devices implements The INTTREG register contains the associated a total of 40 registers for the interrupt controller: interrupt vector number and the new CPU interrupt • INTCON1 priority level, which are latched into the Vector • INTCON2 Number (VECNUM<6:0>) and the Interrupt Level • IFS0 through IFS6 (ILR<3:0>) bit fields in the INTTREG register. The new interrupt priority level is the priority of the • IEC0 through IEC6 pending interrupt. • IPC0 through IPC25 (except IPC14, IPC17 and IPC24) The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the order of their vector numbers, • INTTREG as shown in Table7-2. For example, the INT0 (External Global interrupt control functions are controlled from Interrupt 0) is shown as having a vector number and a INTCON1 and INTCON2. INTCON1 contains the Inter- natural order priority of 0. Thus, the INT0IF status bit is rupt Nesting Disable (NSTDIS) bit, as well as the found in IFS0<0>, the INT0IE enable bit in IEC0<0> control and status flags for the processor trap sources. and the INT0IP<2:0> priority bits in the first position of The INTCON2 register controls the external interrupt IPC0 (IPC0<2:0>). request signal behavior and the use of the Alternate Although they are not specifically part of the interrupt Interrupt Vector Table (AIVT). control hardware, two of the CPU Control registers con- The IFSx registers maintain all of the interrupt request tain bits that control interrupt functionality. The ALU flags. Each source of interrupt has a status bit, which is STATUS register (SR) contains the IPL<2:0> bits set by the respective peripherals or an external signal (SR<7:5>). These indicate the current CPU interrupt and is cleared via software. priority level. The user can change the current CPU The IECx registers maintain all of the interrupt enable priority level by writing to the IPL bits. bits. These control bits are used to individually enable interrupts from the peripherals or external signals. DS39969B-page 96  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY The CORCON register contains the IPL3 bit, which, a generic ISR is used for multiple vectors (such as together with IPL<2:0>, indicates the current CPU when ISR remapping is used in bootloader applica- priority level. IPL3 is a read-only bit so that trap events tions) or to check if another interrupt is pending while in cannot be masked by the user software. an ISR. The interrupt controller has the Interrupt Controller Test All interrupt registers are described in Register7-1 register, INTTREG, which displays the status of the through Register7-40 in the succeeding pages. interrupt controller. When an interrupt request occurs, it’s associated vector number and the new interrupt pri- ority level are latched into INTTREG. This information can be used to determine a specific interrupt source if REGISTER 7-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — DC(1) bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15); user interrupts are disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) Note 1: See Register3-1 for the description of the remaining bits (bit 8, 4, 3, 2, 1 and 0) that are not dedicated to interrupt control functions. 2: The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. 3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.  2010 Microchip Technology Inc. DS39969B-page 97

PIC24FJ256DA210 FAMILY REGISTER 7-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC r-1 U-0 U-0 — — — — IPL3(1) r — — bit 7 bit 0 Legend: r = Reserved bit C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 Reserved: Read as ‘1’ bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level; see Register3-2 for bit description. DS39969B-page 98  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 99

PIC24FJ256DA210 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS39969B-page 100  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. DS39969B-page 101

PIC24FJ256DA210 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — bit 15 bit 8 R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS IC8IF IC7IF — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 Unimplemented: Read as ‘0’ bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39969B-page 102  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS — — PMPIF(1) OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0 U-0 R/W-0, HS R/W-0, HS IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 OC8IF: Output Compare Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Not available in PIC24FJXXXDAX06 devices.  2010 Microchip Technology Inc. DS39969B-page 103

PIC24FJ256DA210 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-2 Unimplemented: Read as ‘0’ bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Not available in PIC24FJXXXDAX06 devices. DS39969B-page 104  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 R/W-0, HS R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS U-0 — INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-7 Unimplemented: Read as ‘0’ bit 6 INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 105

PIC24FJ256DA210 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS — — CTMUIF — — — — LVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-9 Unimplemented: Read as ‘0’ bit 8 LVDIF: Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS39969B-page 106  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS — — IC9IF OC9IF SPI3IF SPF3IF U4TXIF U4RXIF bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 U4ERIF USB1IF MI2C3IF SI2C3IF U3TXIF U3RXIF U3ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 IC9IF: Input Capture Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 OC9IF: Output Compare Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 SPI3IF: SPI3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPF3IF: SPI3 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 U4TXIF: UART4 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 U4RXIF: UART4 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 U4ERIF: UART4 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 USB1IF: USB1 (USB OTG) Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 MI2C3IF: Master I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 SI2C3IF: Slave I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010 Microchip Technology Inc. DS39969B-page 107

PIC24FJ256DA210 FAMILY REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 (CONTINUED) bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ REGISTER 7-11: IFS6: INTERRUPT FLAG STATUS REGISTER 6 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 — — — GFX1IF — — — — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 GFX1IF: Graphics 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3-0 Unimplemented: Read as ‘0’ DS39969B-page 108  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2010 Microchip Technology Inc. DS39969B-page 109

PIC24FJ256DA210 FAMILY REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U2TXIE U2RXIE INT2IE(1) T5IE T4IE OC4IE OC3IE — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8IE IC7IE — INT1IE(1) CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 Unimplemented: Read as ‘0’ bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. DS39969B-page 110  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 111

PIC24FJ256DA210 FAMILY REGISTER 7-14: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PMPIE(1) OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIE: Parallel Master Port Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 OC8IE: Output Compare Channel 8 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-2 Unimplemented: Read as ‘0’ bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06). DS39969B-page 112  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-15: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IE(1) INT3IE(1) — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-7 Unimplemented: Read as ‘0’ bit 6 INT4IE: External Interrupt 4 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 INT3IE: External Interrupt 3 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 113

PIC24FJ256DA210 FAMILY REGISTER 7-16: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — LVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-9 Unimplemented: Read as ‘0’ bit 8 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ DS39969B-page 114  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-17: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC9IE OC9IE SPI3IE SPF3IE U4TXIE U4RXIE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U4ERIE USB1IE MI2C3IE SI2C3IE U3TXIE U3RXIE U3ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 IC9IE: Input Capture Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 OC9IE: Output Compare Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 SPI3IE: SPI3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 SPF3IE: SPI3 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 U4TXIE: UART4 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 U4RXIE: UART4 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 U4ERIE: UART4 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 USB1IE: USB1 (USB OTG) Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 MI2C3IE: Master I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 SI2C3IE: Slave I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 U3TXIE: UART3 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 U3RXIE: UART3 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2010 Microchip Technology Inc. DS39969B-page 115

PIC24FJ256DA210 FAMILY REGISTER 7-17: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 (CONTINUED) bit 1 U3ERIE: UART3 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ REGISTER 7-18: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — GFX1IE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 GFX1IE: Graphics 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3-0 Unimplemented: Read as ‘0’ DS39969B-page 116  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-19: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. DS39969B-page 117

PIC24FJ256DA210 FAMILY REGISTER 7-20: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39969B-page 118  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-21: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. DS39969B-page 119

PIC24FJ256DA210 FAMILY REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 120  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-23: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. DS39969B-page 121

PIC24FJ256DA210 FAMILY REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC8IP2 IC8IP1 IC8IP0 — IC7IP2 IC7IP1 IC7IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 122  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-25: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 123

PIC24FJ256DA210 FAMILY REGISTER 7-26: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 124  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-27: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. DS39969B-page 125

PIC24FJ256DA210 FAMILY REGISTER 7-28: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39969B-page 126  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-29: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. DS39969B-page 127

PIC24FJ256DA210 FAMILY REGISTER 7-30: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PMPIP2(1) PMPIP1(1) PMPIP0(1) — OC8IP2 OC8IP1 OC8IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06). DS39969B-page 128  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-31: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 129

PIC24FJ256DA210 FAMILY REGISTER 7-32: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39969B-page 130  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-33: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 131

PIC24FJ256DA210 FAMILY REGISTER 7-34: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39969B-page 132  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-35: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — LVDIP2 LVDIP1 LVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled REGISTER 7-36: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 133

PIC24FJ256DA210 FAMILY REGISTER 7-37: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U3TXIP<2:0>: UART3 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U3RXIP<2:0>: UART3 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U3ERIP<2:0>: UART3 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39969B-page 134  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-38: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4ERIP2 U4ERIP1 U4ERIP0 — USB1IP2 USB1IP1 USB1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C3IP2 MI2C3IP1 MI2C3IP0 — SI2C3IP2 SI2C3IP1 SI2C3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U4ERIP<2:0>: UART4 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 USB1IP<2:0>: USB1 (USB OTG) Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C3IP<2:0>: Master I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C3IP<2:0>: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. DS39969B-page 135

PIC24FJ256DA210 FAMILY REGISTER 7-39: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI3IP2 SPI3IP1 SPI3IP0 — SPF3IP2 SPF3IP1 SPF3IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 SPI3IP<2:0>: SPI3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPF3IP<2:0>: SPI3 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U4TXIP<2:0>: UART4 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U4RXIP<2:0>: UART4 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 136  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-40: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC9IP2 IC9IP1 IC9IP0 — OC9IP2 OC9IP1 OC9IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC9IP<2:0>: Input Capture Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 OC9IP<2:0>: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. DS39969B-page 137

PIC24FJ256DA210 FAMILY REGISTER 7-41: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — GFX1IP2 GFX1IP1 GFX1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 GFX1IP<2:0>: Graphics 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 138  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 7-42: INTTREG: INTERRUPT CONTROLLER TEST REGISTER R-0, HSC U-0 R/W-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens when the CPU priority is higher than the interrupt priority 0 = No interrupt request is unacknowledged bit 14 Unimplemented: Read as ‘0’ bit 13 VHOLD: Vector Number Capture Configuration bit 1 = The VECNUM bits contain the value of the highest priority pending interrupt 0 = The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<5:0>: Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits VHOLD = 1: The VECNUM bits indicate the vector number (from 0 to 118) of the last interrupt to occur VHOLD = 0: The VECNUM bits indicate the vector number (from 0 to 118) of the interrupt request currently being handled  2010 Microchip Technology Inc. DS39969B-page 139

PIC24FJ256DA210 FAMILY 7.4 Interrupt Setup Procedures 7.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, 7.4.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS (INTCON1<15>) control bit if nested interrupts are not desired. 7.4.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the All user interrupts can be disabled using the following appropriate IPCx register. The priority level will procedure: depend on the specific application and type of 1. Push the current SR value onto the software interrupt source. If multiple priority levels are not stack using the PUSH instruction. desired, the IPCx register control bits for all 2. Force the CPU to priority level 7 by inclusive enabled interrupt sources may be programmed ORing the value 0Eh with SRL. to the same non-zero value. To enable user interrupts, the POP instruction may be Note: At a device Reset, the IPCx registers are used to restore the previous SR value. initialized, such that all user interrupt Note that only user interrupts with a priority level of 7 or sources are assigned to priority level 4. less can be disabled. Trap sources (Level8-15) cannot 3. Clear the interrupt flag status bit associated with be disabled. the peripheral in the associated IFSx register. The DISI instruction provides a convenient way to 4. Enable the interrupt source by setting the disable interrupts of priority levels, 1-6, for a fixed interrupt enable control bit associated with the period of time. Level 7 interrupt sources are not source in the appropriate IECx register. disabled by the DISI instruction. 7.4.2 INTERRUPT SERVICE ROUTINE (ISR) The method that is used to declare an Interrupt Service Routine (ISR) and initialize the IVT with the correct vec- tor address will depend on the programming language (i.e., ‘C’ or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be termi- nated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS39969B-page 140  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 8.0 OSCILLATOR • An on-chip PLL block to boost internal operating CONFIGURATION frequency on select internal and external oscillator sources, and to provide a precise clock source for Note: This data sheet summarizes the features peripherals, such as USB and graphics of this group of PIC24F devices. It is not • Software controllable switching between various intended to be a comprehensive reference clock sources source. For more information, refer to the • Software controllable postscaler for selective “PIC24F Family Reference Manual”, clocking of CPU for system power savings Section 6. “Oscillator” (DS39700). The • A Fail-Safe Clock Monitor (FSCM) that detects information in this data sheet supersedes clock failure and permits safe application recovery the information in the FRM. or shutdown The oscillator system for PIC24FJ256DA210 family • A separate and independently configurable system devices has the following features: clock output for synchronizing external hardware • A total of four external and internal oscillator options A simplified diagram of the oscillator system is shown as clock sources, providing 11 different clock modes in Figure8-1. FIGURE 8-1: PIC24FJ256DA210 FAMILY CLOCK DIAGRAM PIC24FJ256DA210 Family Clock for Display Interface 48/96 MHz Clock for Graphics Controller Module 48 MHz USB Clock Primary Oscillator XT, HS, EC OSCO 96 MHz PLL(1) REFOCON<15:8> CPDIV<1:0> OSCI Reference Clock XTPLL, HSPLL Generator ECPLL,FRCPLL PLL and REFO DIV PLLDIV<2:0> GCLKDIV<6:0> Peripherals er 8 MHz/ FRC al 4 MHz FRCDIV Oscillator 8 MHz stsc CLKO (nominal) o P er CLKDIV<10:8> FRC cal CPU s st LPFRC o 1/16 P LPRC LPRC CLKDIV<14:12> Oscillator 31 kHz (nominal) SOSC Secondary Oscillator Clock Control Logic Fail-Safe SOSCO Clock SOSCEN Monitor Enable SOSCI Oscillator WDT Clock Source Option for Other Modules Note 1: Refer to Figure8-2 for more information on the 96 MHz PLL block.  2010 Microchip Technology Inc. DS39969B-page 141

PIC24FJ256DA210 FAMILY 8.1 CPU Clocking Scheme 8.2 Initial Configuration on POR The system clock source can be provided by one of The oscillator source (and operating mode) that is used four sources: at a device Power-on Reset (POR) event is selected using Configuration bit settings. The oscillator Configu- • Primary Oscillator (POSC) on the OSCI and ration bit settings are located in the Configuration OSCO pins registers in the program memory (refer to Section27.1 • Secondary Oscillator (SOSC) on the SOSCI and “Configuration Bits” for further details). The Primary SOSCO pins Oscillator Configuration bits, POSCMD<1:0> (Configu- • Fast Internal RC (FRC) Oscillator ration Word 2<1:0>) and the Initial Oscillator Select • Low-Power Internal RC (LPRC) Oscillator Configuration bits, FNOSC<2:0> (Configuration The primary oscillator and FRC sources have the Word2<10:8>), select the oscillator source that is used option of using the internal 24x PLL block, which at a POR. The FRC primary oscillator with postscaler generates the USB module clock, the Graphics module (FRCDIV) is the default (unprogrammed) selection. The clock and a separate system clock through the 96 MHZ secondary oscillator, or one of the internal oscillators, PLL. Refer to Section8.5 “96 MHz PLL Block” for may be chosen by programming these bit locations. additional information. The Configuration bits allow users to choose between The internal FRC provides an 8 MHz clock source. It the various clock modes, shown in Table8-1. can optionally be reduced by the programmable clock 8.2.1 CLOCK SWITCHING MODE divider to provide a range of system clock frequencies. CONFIGURATION BITS The selected clock source generates the processor The FCKSM Configuration bits (Configuration and peripheral clock sources. The processor clock Word2<7:6>) are used to jointly configure device clock source is divided by two to produce the internal instruc- tion cycle clock, FCY. In this document, the instruction switching and the Fail-Safe Clock Monitor (FSCM). cycle clock is also denoted by FOSC/2. The internal Clock switching is enabled only when FCKSM1 is instruction cycle clock, FOSC/2, can be provided on the programmed (‘0’). The FSCM is enabled only when OSCO I/O pin for some operating modes of the primary FCKSM<1:0> are both programmed (‘00’). oscillator. TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Notes Fast RC Oscillator with Postscaler Internal 11 111 1, 2 (FRCDIV) FRC Oscillator/16 (500 KHz) Internal 11 110 1 Low-Power RC Oscillator (LPRC) Internal 11 101 1 Secondary (Timer1) Oscillator Secondary 11 100 1 (SOSC) Primary Oscillator (XT) with PLL Primary 01 011 — Module (XTPLL) Primary Oscillator (EC) with PLL Primary 00 011 1 Module (ECPLL) Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL Module Internal 11 001 1 (FRCPLL) Fast RC Oscillator (FRC) Internal 11 000 1 Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. DS39969B-page 142  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 8.3 Control Registers The OSCCON register (Register8-1) is the main con- trol register for the oscillator. It controls clock source The following five Special Function Registers control switching and allows the monitoring of clock sources. the operation of the oscillator: The CLKDIV register (Register8-2) controls the • OSCCON features associated with Doze mode, as well as the • CLKDIV postscaler for the FRC oscillator. • OSCTUN The OSCTUN register (Register8-3) allows the user to • CLKDIV2 fine tune the FRC oscillator over a range of • REFOCON approximately ±1.5%. The CLKDIV2 register (Register8-4) controls the clock to the display glass, with the frequency ranging from 750 kHz to 96 MHz. The REFOCON register (Register 8-5) controls the frequency of the reference clock out. REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-x, HSC(1) R-x, HSC(1) R-x, HSC(1) U-0 R/W-x(1) R/W-x(1) R/W-x(1) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/S-0 R/W-0 R-0, HSC(3) U-0 R/C-0, HS R/W-0 R/W-0 R/W-0 CLKLOCK IOLOCK(2) LOCK — CF POSCEN SOSCEN OSWEN bit 7 bit 0 Legend: C = Clearable bit S = Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Fast RC/16 Oscillator 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ Note 1: Reset values for these bits are determined by the FNOSC Configuration bits. 2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL Clock mode is selected.  2010 Microchip Technology Inc. DS39969B-page 143

PIC24FJ256DA210 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Fast RC/16 Oscillator 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active bit 5 LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary Oscillator continues to operate during Sleep mode 0 = Primary Oscillator is disabled during Sleep mode bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable the Secondary Oscillator 0 = Disable the Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to the clock source specified by the NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Reset values for these bits are determined by the FNOSC Configuration bits. 2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL Clock mode is selected. DS39969B-page 144  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 8-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 CPDIV1 CPDIV0 PLLEN G1CLKSEL — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: DOZE Enable bit(1) 1 = DOZE<2:0> bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio is set to 1:1 bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits 111 = 31.25 kHz (divide by 256) 110 = 125 kHz (divide by 64) 101 = 250 kHz (divide by 32) 100 = 500 kHz (divide by 16) 011 = 1 MHz (divide by 8) 010 = 2 MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) bit 7-6 CPDIV<1:0>: System Clock Select bits (postscaler select from 32 MHz clock branch) 11 = 4 MHz (divide by 8)(2) 10 = 8 MHz (divide by 4)(2) 01 = 16 MHz (divide by 2) 00 = 32 MHz (divide by 1) Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled.  2010 Microchip Technology Inc. DS39969B-page 145

PIC24FJ256DA210 FAMILY REGISTER 8-2: CLKDIV: CLOCK DIVIDER REGISTER (CONTINUED) bit 5 PLLEN: 96 MHz PLL Enable bit The 96 MHz PLL must be enabled when the USB or graphics controller module is enabled. This control bit can be overridden by the PLL96MHZ (Configuration Word 2 <11>) Configuration bit. 1 = Enable the 96 MHz PLL for USB, graphics controller or HSPLL/ECPLL/FRCPLL operation 0 = Disable the 96 MHz PLL bit 4 G1CLKSEL: Display Controller Module Clock Select bit 1 = Use the 96 MHz clock as a graphics controller module clock 0 = Use the 48 MHz clock as a graphics controller module clock bit 3-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled. REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 = · · · 000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 = · · · 100001 = 100000 = Minimum frequency deviation Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. DS39969B-page 146  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 8-4: CLKDIV2: CLOCK DIVIDER REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 GCLKDIV6(1) GCLKDIV5(1) GCLKDIV4(1) GCLKDIV3(1) GCLKDIV2(1) GCLKDIV1(1) GCLKDIV0(1) — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at all Resets ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 GCLKDIV<6:0>: Display Module Interface Clock Divider Selection bits(1) (Values are based on a 96 MHz clock source set by G1CLKSEL (CLKDIV<4>) = 1. When the 48 MHz clock source is selected, G1CLKSEL (CLKDIV<4>) = 0; all values are divided by 2.)(1) 1111111 = (127) 1.50 MHz (divide by 64) 1111110 = (126) 1.52 MHz (divide by 63) · · · 1100001 = (97) 2.82 MHz (divide by 34) 1100000 = (96) 2.91 MHz (divide by 33); from here, increment the divisor by 1.00 1011111 = (95) 2.95 MHz (divide by 32.50) · · · 1000000 = (65) 5.49 MHz (divide by 17.50) 1000000 = (64) 5.65 MHz (divide by 17.00); from here, increment the divisor by 0.50 0111111 = (63) 5.73 MHz (divide by 16.75) · · · 0000011 = (3) 54.86 MHz (divide by 1.75) 0000010 = (2) 64.00 MHz (divide by 1.5) 0000001 = (1) 76.80 MHz (divide by 1.25); from here, increment the divisor by 0.25 0000000 = (0) 96.00 MHz (divide by 1) bit 8-0 Unimplemented: Read as ‘0’ Note 1: These bits take effect only when the 96 MHz PLL is enabled.  2010 Microchip Technology Inc. DS39969B-page 147

PIC24FJ256DA210 FAMILY 8.4 Clock Switching Operation Once the basic sequence is completed, the system clock hardware responds automatically as follows: With few limitations, applications are free to switch 1. The clock switching hardware compares the between any of the four clock sources (POSC, SOSC, COSCx bits with the new value of the NOSCx FRC and LPRC) under software control and at any bits. If they are the same, then the clock switch time. To limit the possible side effects that could result is a redundant operation. In this case, the from this flexibility, PIC24F devices have a safeguard OSWEN bit is cleared automatically and the lock built into the switching process. clock switch is aborted. Note: The Primary Oscillator mode has three 2. If a valid clock switch has been initiated, the different submodes (XT, HS and EC) LOCK (OSCCON<5>) and CF (OSCCON<3>) which are determined by the POSCMDx bits are cleared. Configuration bits. While an application 3. The new oscillator is turned on by the hardware can switch to and from Primary Oscillator if it is not currently running. If a crystal oscillator mode in software, it cannot switch must be turned on, the hardware will wait until between the different primary submodes the OST expires. If the new source is using the without reprogramming the device. PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). 8.4.1 ENABLING CLOCK SWITCHING 4. The hardware waits for 10 clock cycles from the new clock source and then performs the clock To enable clock switching, the FCKSM1 Configuration switch. bit in CW2 must be programmed to ‘0’. (Refer to 5. The hardware clears the OSWEN bit to indicate a Section27.1 “Configuration Bits” for further details.) successful clock transition. In addition, the If the FCKSM1 Configuration bit is unprogrammed (‘1’), NOSCx bit values are transferred to the COSCx the clock switching function and Fail-Safe Clock Monitor bits. function are disabled. This is the default setting. 6. The old clock source is turned off at this time, The NOSCx (OSCCON<10:8>) control bits do not with the exception of LPRC (if WDT or FSCM control the clock selection when clock switching is are enabled) or SOSC (if SOSCEN remains disabled. However, the COSCx (OSCCON<14:12>) set). control bits will reflect the clock source selected by the FNOSCx Configuration bits. Note1: The processor will continue to execute code throughout the clock switching The OSWEN (OSCCON<0>) control bit has no effect sequence. Timing-sensitive code should when clock switching is disabled; It is held at ‘0’ at all not be executed during this time. times. 2: Direct clock switches between any 8.4.2 OSCILLATOR SWITCHING Primary Oscillator mode with PLL and SEQUENCE FRCPLL modes are not permitted. This applies to clock switches in either direc- At a minimum, performing a clock switch requires this tion. In these instances, the application basic sequence: must switch to FRC mode as a transition 1. If desired, read the COSCx (OSCCON<14:12>) clock source between the two PLL control bits to determine the current oscillator modes. source. 2. Perform the unlock sequence to allow a write to the OSCCON register high byte. 3. Write the appropriate value to the NOSCx (OSCCON<10:8>) control bits for the new oscillator source. 4. Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. DS39969B-page 148  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY A recommended code sequence for a clock switch 8.5 96 MHz PLL Block includes the following: The 96 MHz PLL block is implemented to generate the 1. Disable interrupts during the OSCCON register stable 48 MHz clock required for full-speed USB unlock and write sequence. operation, a programmable clock output for the 2. Execute the unlock sequence for the OSCCON graphics controller module and the system clock from high byte by writing 78h and 9Ah to the same oscillator source. The 96 MHz PLL block is OSCCON<15:8> in two back-to-back shown in Figure8-2. instructions. The 96 MHz PLL block requires a 4 MHz input signal; it 3. Write new oscillator source to the NOSCx bits in uses this to generate a 96 MHz signal from a fixed, 24x the instruction immediately following the unlock PLL. This is, in turn, divided into three branches. The first sequence. branch generates the USB clock, the second branch 4. Execute the unlock sequence for the OSCCON generates the system clock and the third branch gener- low byte by writing 46h and 57h to ates the graphics clock. The 96 MHz PLL block can be OSCCON<7:0> in two back-to-back instructions. enabled and disabled using the PLL96MHZ Configura- 5. Set the OSWEN bit in the instruction immediately tion bit (Configuration Word<11>) or through the PLLEN following the unlock sequence. (CLKDIV<5>) control bit when the PLL96MHZ 6. Continue to execute code that is not Configuration bit is not set. Note that the PLL96MHZ clock-sensitive (optional). Configuration bit and PLLEN register bit are available only for PIC24F devices with USB and graphics 7. Invoke an appropriate amount of software delay controller modules. (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. The 96 MHz PLL prescaler does not automatically 8. Check to see if OSWEN is ‘0’. If it is, the switch sense the incoming oscillator frequency. The user must was successful. If OSWEN is still set, then manually configure the PLL divider to generate the check the LOCK bit to determine the cause of required 4 MHz output, using the PLLDIV<2:0> Config- failure. uration bits (Configuration Word 2<14:12> in most devices). The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example8-1. EXAMPLE 8-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING IN ASSEMBLY ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0  2010 Microchip Technology Inc. DS39969B-page 149

PIC24FJ256DA210 FAMILY FIGURE 8-2: 96 MHz PLL BLOCK USB Clock 48 MHz Clock for USB Module ÷ 2 96 MHz PLL System Clock FNOSC<2:0> PLLDIV<2:0> caler ÷÷÷ 842 1110 ÷ 3 PSLysLt eOmu tCpulot cfkor ÷12 sts ÷ 1 01 IPInnOppuuSttC ffrroomm escaler ÷÷÷ 586 111111001010 Po CPDI0V0<1:0> FRC L Pr ÷÷ 43 001110 Graphics Clock 48 MMHHzz or PL ÷÷ 21 000010 ÷ 2 Graphics Clock 48 MHz Branch Option 2 4 MHz Branch ÷ 64 ÷ 63 127 Clock Output for 96 MHz 96 MHz Branch 126 Display Interface PLL er ... ... (DISPCLK) G1CLKSEL ostscal .÷÷.. 1177..5000 66..54. P ÷ 1.25 1 0 ÷ 1 0 Graphics Clock . Option 1 1 . Clock Output for Graphics . GCLKDIV<6:0> Controller Module (G1CLK) 8.5.1 SYSTEM CLOCK GENERATION as the system clock. Figure8-2 shows this logic in the system clock sub-block. Since the source is a 96 MHz The system clock is generated from the 96 MHz branch signal, the possible system clock frequencies are listed using a configurable postscaler/divider to generate a in Table8-2. The available system clock options are range of frequencies for the system clock multiplexer. always the same, regardless of the setting of the The output of the multiplexer is further passed through PLLDIV Configuration bits. a fixed divide-by-3 divider and the final output is used TABLE 8-2: SYSTEM CLOCK OPTIONS FOR 96 MHz PLL BLOCK MCU Clock Division System Clock Frequency (CPDIV<1:0>) (Instruction Rate in MIPS) None (00) 32MHz (16) 2 (01) 16MHz (8) 4 (10) 8MHz (4)(1) 8 (11) 4MHz (2)(1) Note 1: These options are not compatible with USB operation. They may be used whenever the PLL branch is selected and the USB module is disabled. DS39969B-page 150  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 8.5.2 USB CLOCK GENERATION clock signal from 96 MHz PLL. Due to the requirement that a 4 MHz input must be provided to generate the In the USB-On-The-Go module in PIC24FJ256DA210 96MHz signal, the oscillator operation is limited to a family of devices, the primary oscillator with the PLL range of possible values. Table8-3 shows the valid block can be used as a valid clock source for USB oper- oscillator configurations (i.e., ECPLL, HSPLL, XTPLL ation. The FRC oscillator (implemented with ±0.25% and FRCPLL) for USB operation. This sets the correct accuracy) can be combined with a PLL block, providing PLLDIV configuration for the specified oscillator another option for a valid USB clock source. There is frequency and the output frequency of the USB clock no provision to provide a separate external 48 MHz branch is always 48 MHz. clock to the USB module. The USB module sources its TABLE 8-3: VALID OSCILLATOR CONFIGURATIONS FOR USB OPERATIONS PLL Division Input Oscillator Frequency Clock Mode (PLLDIV<2:0>) 48MHz ECPLL 12 (111) 32MHz HSPLL, ECPLL 8 (110) 24MHz HSPLL, ECPLL 6 (101) 20MHz HSPLL, ECPLL 5 (100) 16MHz HSPLL, ECPLL 4 (011) 12MHz HSPLL, ECPLL 3 (010) 8MHz ECPLL, HSPLL, XTPLL, FRCPLL 2 (001) 4MHz ECPLL, HSPLL, XTPLL, FRCPLL 1 (000) Note: For USB devices, the use of a primary oscillator or external clock source, with a frequency above 32MHz, does not imply that the device’s system clock can be run at the same speed when the USB module is not used. The maximum system clock for all PIC24F devices is 32MHz. 8.5.3 CONSIDERATIONS FOR USB 8.5.4 GRAPHICS CLOCK GENERATION OPERATION Two stable clock signals are generated for the graphics When using the USB On-The-Go module in controller in the PIC24FJ256DA210 family of devices. PIC24FJ256DA210 family devices, users must always The first clock is for the graphics controller module logic observe these rules in configuring the system clock: and the second clock is for the display module interface logic that generates the signals for the display glass. • For USB operation, the selected clock source Figure8-2 shows this logic in the graphics clock (EC, HS or XT) must meet the USB clock sub-block. Both clock signals are generated either from tolerance requirements. the Graphics Clock Option 1 (96 MHz branch) or the • The Primary Oscillator/PLL modes are the only Graphics Clock Option 2 (48 MHz branch). Selection is oscillator configurations that permit USB opera- set in the multiplexer using the G1CLKSEL tion. There is no provision to provide a separate (CLKDIV<4>) control bit. Graphics controller module external clock source to the USB module. logic directly uses the output of that multiplexer while • While the FRCPLL Oscillator mode is used for the display module interface clock is further condi- USB applications, users must always ensure that tioned through a postscaler to generate 128 possible the FRC source is configured to provide a frequencies. The final clock output signal is selected frequency of 4MHz or 8MHz (RCDIV<2:0> = 001 through a multiplexer using the GCLKDIV<6:0> or 000) and that the USB PLL prescaler is (CLKDIV2<15:9>) control bits. The 128 selections vary configured appropriately. in increments of 0.25, 0.5, and 1.0. Refer to Table8-4 All other oscillator modes are available; however, USB for details. Note that for applications that use the operation is not possible when these modes are graphics controller (GFX) module, the 96 MHz PLL selected. They may still be useful in cases where other must be enabled. power levels of operation are desirable and the USB module is not needed (e.g., the application is sleeping and waiting for a bus attachment).  2010 Microchip Technology Inc. DS39969B-page 151

PIC24FJ256DA210 FAMILY TABLE 8-4: DISPLAY MODULE CLOCK FREQUENCY DIVISION Display Module Clock Frequency GCLKDIV<6:0> Frequency Divisor 96 MHz Input (48 MHz Input) 0000000 1 96 MHz (48 MHz) 0000001 1.25 (start incrementing by 0.25) 76.80 MHz (38.4 MHz) 0000010 1.5 64 MHz (32 MHz) … … … 0111111 16.75 5.73 MHz (2.86 MHz) 1000000 17 5.65 MHz (2.82 MHz) 1000001 17.5 (start incrementing by 0.5) 5.49 MHz (2.74 MHz) 1000010 18 5.33 MHz (2.66 MHz) … … … 1011111 32.5 2.95 MHz (1.47 MHz) 1100000 33 2.91 MHz (1.45 MHz) 1100001 34 (start incrementing by 1) 2.82 MHz (1.41 MHz) 1100010 35 2.74 MHz (1.37 MHz) … … … 1111110 63 1.52 MHz (762 kHz) 1111111 64 1.50 MHz (750 kHz) 8.6 Reference Clock Output The ROSSLP and ROSEL bits (REFOCON<13:12>) control the availability of the reference output during In addition to the CLKO output (FOSC/2) available in Sleep mode. The ROSEL bit determines if the oscillator certain oscillator modes, the device clock in the on OSCI and OSCO, or the current system clock PIC24FJ256DA210 family devices can also be config- source, is used for the reference clock output. The ured to provide a reference clock output signal to a port ROSSLP bit determines if the reference source is pin. This feature is available in all oscillator configura- available on REFO when the device is in Sleep mode. tions and allows the user to select a greater range of To use the reference clock output in Sleep mode, both clock submultiples to drive external devices in the the ROSSLP and ROSEL bits must be set. The device application. clock must also be configured for one of the primary This reference clock output is controlled by the modes (EC, HS or XT); otherwise, if the POSCEN bit is REFOCON register (Register8-5). Setting the ROEN not also set, the oscillator on OSCI and OSCO will be bit (REFOCON<15>) makes the clock signal available powered down when the device enters Sleep mode. on the REFO pin. The RODIV bits (REFOCON<11:8>) Clearing the ROSEL bit allows the reference output enable the selection of 16 different clock divider frequency to change as the system clock changes options. during any clock switches. DS39969B-page 152  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 8-5: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL(1) RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit(1) 1 = Primary oscillator used as the base clock 0 = System clock used as the base clock; base clock reflects any clock switching of the device bit 11-8 RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ Note 1: Note that the crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.  2010 Microchip Technology Inc. DS39969B-page 153

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 154  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 9.0 POWER-SAVING FEATURES 9.2.1 SLEEP MODE Sleep mode has these features: Note: This data sheet summarizes the features of this group of PIC24F devices. It is not • The system clock source is shut down. If an intended to be a comprehensive reference on-chip oscillator is used, it is turned off. source. For more information, refer to the • The device current consumption will be reduced “PIC24F Family Reference Manual”, to a minimum, provided that no I/O pin is sourcing Section 10. “Power-Saving Features” current. (DS39698). The information in this data • The Fail-Safe Clock Monitor (FSCM) does not sheet supersedes the information in the operate during Sleep mode since the system FRM. clock source is disabled. The PIC24FJ256DA210 family of devices provides the • The LPRC clock will continue to run in Sleep ability to manage power consumption by selectively mode if the WDT is enabled. managing clocking to the CPU and the peripherals. In • The WDT, if enabled, is automatically cleared general, a lower clock frequency and a reduction in the prior to entering Sleep mode. number of circuits being clocked constitutes lower • Some device features or peripherals may consumed power. All PIC24F devices manage power continue to operate in Sleep mode. This includes consumption in four different ways: items such as the input change notification on the I/O ports or peripherals that use an external clock • Clock Frequency input. Any peripheral that requires the system • Instruction-Based Sleep and Idle modes clock source for its operation will be disabled in • Software Controlled Doze mode Sleep mode. Users can opt to make the voltage • Selective Peripheral Control in Software regulator enter standby mode on entering Sleep Combinations of these methods can be used to mode by clearing the VREGS bit (RCON<8>). selectively tailor an application’s power consumption, This will decrease current consumption but will while still maintaining critical application features, such add a delay, TVREG, to the wake-up time. For this as timing-sensitive communications. reason, applications that do not use the voltage regulator should set this bit. 9.1 Clock Frequency and Clock The device will wake-up from Sleep mode on any of the Switching these events: • On any interrupt source that is individually PIC24F devices allow for a wide range of clock enabled frequencies to be selected under application control. If the system clock configuration is not locked, users can • On any form of device Reset choose low-power or high-precision oscillators by simply • On a WDT time-out changing the NOSC bits. The process of changing a On wake-up from sleep, the processor will restart with system clock during operation, as well as limitations to the same clock source that was active when Sleep the process, are discussed in more detail in Section8.0 mode was entered. “Oscillator Configuration”. EXAMPLE 9-1: PWRSAV INSTRUCTION 9.2 Instruction-Based Power-Saving SYNTAX Modes PWRSAV #0 ; Put the device into SLEEP mode PIC24F devices have two special power-saving modes PWRSAV #1 ; Put the device into IDLE mode that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example9-1. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”.  2010 Microchip Technology Inc. DS39969B-page 155

PIC24FJ256DA210 FAMILY 9.2.2 IDLE MODE It is also possible to use Doze mode to selectively reduce power consumption in event driven applica- Idle mode has these features: tions. This allows clock-sensitive functions, such as • The CPU will stop executing instructions. synchronous communications, to continue without • The WDT is automatically cleared. interruption while the CPU idles, waiting for something • The system clock source remains active. By to invoke an interrupt routine. Enabling the automatic default, all peripheral modules continue to operate return to full-speed CPU operation on interrupts is normally from the system clock source, but can enabled by setting the ROI bit (CLKDIV<15>). By also be selectively disabled (see Section9.4 default, interrupt events have no effect on Doze mode “Selective Peripheral Module Control”). operation. • If the WDT or FSCM is enabled, the LPRC will 9.4 Selective Peripheral Module also remain active. Control The device will wake from Idle mode on any of these events: Idle and Doze modes allow users to substantially • Any interrupt that is individually enabled. reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain • Any device Reset. clocked, and thus, consume power. There may be • A WDT time-out. cases where the application needs what these modes On wake-up from Idle, the clock is reapplied to the CPU do not provide: the allocation of power resources to and instruction execution begins immediately, starting CPU processing with minimal power consumption from with the instruction following the PWRSAV instruction or the peripherals. the first instruction in the ISR. PIC24F devices address this requirement by allowing 9.2.3 INTERRUPTS COINCIDENT WITH peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be POWER SAVE INSTRUCTIONS done with two control bits: Any interrupt that coincides with the execution of a • The Peripheral Enable bit, generically named, PWRSAV instruction will be held off until entry into Sleep “XXXEN”, located in the module’s main control or Idle mode has completed. The device will then SFR. wake-up from Sleep or Idle mode. • The Peripheral Module Disable (PMD) bit, generically named, “XXXMD”, located in one of 9.3 Doze Mode the PMD control registers. Generally, changing clock speed and invoking one of Both bits have similar functions in enabling or disabling the power-saving modes are the preferred strategies its associated module. Setting the PMD bit for a module for reducing power consumption. There may be cir- disables all clock sources to that module, reducing its cumstances, however, where this is not practical. For power consumption to an absolute minimum. In this example, it may be necessary for an application to state, the control and status registers associated with maintain uninterrupted synchronous communication, the peripheral will also be disabled, so writes to those even while it is doing nothing else. Reducing system registers will have no effect and read values will be clock speed may introduce communication errors, invalid. Many peripheral modules have a corresponding while using a power-saving mode may stop PMD bit. communications completely. In contrast, disabling a module by clearing its XXXEN Doze mode is a simple and effective alternative method bit disables its functionality, but leaves its registers to reduce power consumption while the device is still available to be read and written to. This reduces power executing code. In this mode, the system clock contin- consumption, but not by as much as setting the PMD ues to operate from the same source and at the same bit does. Most peripheral modules have an enable bit; speed. Peripheral modules continue to be clocked at exceptions include input capture, output compare and the same speed while the CPU clock speed is reduced. RTCC. Synchronization between the two clock domains is To achieve more selective power savings, peripheral maintained, allowing the peripherals to access the modules can also be selectively disabled when the SFRs while the CPU executes code at a slower rate. device enters Idle mode. This is done through the Doze mode is enabled by setting the DOZEN bit control bit of the generic name format, “XXXIDL”. By (CLKDIV<11>). The ratio between peripheral and core default, all modules that can operate during Idle mode clock speed is determined by the DOZE<2:0> bits will do so. Using the disable on Idle feature allows (CLKDIV<14:12>). There are eight possible further reduction of power consumption during Idle configurations, from 1:1 to 1:128, with 1:1 being the mode, enhancing power savings for extremely critical default. power applications. DS39969B-page 156  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 10.0 I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as Note: This data sheet summarizes the features a general purpose output pin is disabled. The I/O pin of this group of PIC24F devices. It is not may be read, but the output driver for the parallel port intended to be a comprehensive reference bit will be disabled. If a peripheral is enabled, but the source. For more information, refer to the peripheral is not actively driving a pin, that pin may be “PIC24F Family Reference Manual”, driven by a port. Section 12. “I/O Ports with Peripheral All port pins have three registers directly associated Pin Select (PPS)” (DS39711). The infor- with their operation as digital I/O and one register asso- mation in this data sheet supersedes the ciated with their operation as analog input. The Data information in the FRM. Direction register (TRISx) determines whether the pin All of the device pins (except VDD, VSS, MCLR and is an input or an output. If the data direction bit is a ‘1’, OSCI/CLKI) are shared between the peripherals and then the pin is an input. All port pins are defined as the parallel I/O ports. All I/O input ports feature Schmitt inputs after a Reset. Reads from the Output Latch reg- Trigger (ST) inputs for improved noise immunity. ister (LATx), read the latch; writes to the latch, write the latch. Reads from the port (PORTx), read the port pins; writes to the port pins, write the latch. 10.1 Parallel I/O (PIO) Ports Any bit and its associated data and control registers A parallel I/O port that shares a pin with a peripheral is, that are not valid for a particular device will be in general, subservient to the peripheral. The periph- disabled. That means the corresponding LATx and eral’s output buffer data and control signals are TRISx registers, and the port pin will read as zeros. provided to a pair of multiplexers. The multiplexers When a pin is shared with another peripheral or func- select whether the peripheral or the associated port tion that is defined as an input only, it is regarded as a has ownership of the output data and control signals of dedicated port because there is no other competing the I/O pin. The logic also prevents “loop through”, in source of inputs. which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + CK WR PORT Data Latch Read LAT Input Data Read PORT  2010 Microchip Technology Inc. DS39969B-page 157

PIC24FJ256DA210 FAMILY 10.1.1 I/O PORT WRITE/READ TIMING 10.2 Configuring Analog Port Pins (ANSEL) One instruction cycle is required between a port direction change or port write operation and a read operation of The ANSx and TRISx registers control the operation of the same port. Typically, this instruction would be a NOP. the pins with analog function. Each port pin with analog function is associated with one of the ANS bits (see 10.1.2 OPEN-DRAIN CONFIGURATION Register10-1 through Register10-7), which decides if In addition to the PORT, LAT and TRIS registers for data the pin function should be analog or digital. Refer to control, each port pin can also be individually configured Table10-1 for detailed behavior of the pin for different for either a digital or open-drain output. This is controlled ANSx and TRISx bit settings. by the Open-Drain Control register, ODCx, associated When reading the PORT register, all pins configured as with each port. Setting any of the bits configures the analog input channels will read as cleared (a low level). corresponding pin to act as an open-drain output. The open-drain feature allows the generation of 10.2.1 ANALOG INPUT PINS AND outputs higher than VDD (e.g., 5V) on any desired VOLTAGE CONSIDERATIONS digital only pins by using external pull-up resistors. The The voltage tolerance of pins used as device inputs is maximum open-drain voltage allowed is the same as dependent on the pin’s input function. Pins that are used the maximum VIH specification. as digital only inputs are able to handle DC voltages of up 10.1.3 CONFIGURING D+ AND D- PINS to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can (RG2 AND RG3) only tolerate voltages up to VDD. Voltage excursions The input buffers of the RG2 and RG3 pins are by beyond VDD on these pins should always be avoided. default, tri-stated. To use these pins as input pins, the Table10-2 summarizes the input capabilities. Refer to UTRDIS bit (U1CNFG2<0>) should be set which Section30.1 “DC Characteristics” for more details. enables the input buffers on these pins. TABLE 10-1: CONFIGURING ANALOG/DIGITAL FUNCTION OF AN I/O PIN Pin Function ANSx Setting TRISx Setting Comments Analog Input 1 1 It is recommended to keep ANSx = 1. Analog Output 1 1 It is recommended to keep ANSx = 1. Digital Input 0 1 Firmware must wait at least one instruction cycle after configuring a pin as a digital input before a valid input value can be read. Digital Output 0 0 Make sure to disable the analog output function on the pin if any is present. TABLE 10-2: INPUT VOLTAGE LEVELS FOR PORT OR PIN TOLERATED DESCRIPTION INPUT Port or Pin Tolerated Input Description PORTA(1)<10:9, 7:6> PORTB<15:0> PORTC(1)<15:12, 4> PORTD<7:6> VDD Only VDD input levels are tolerated. PORTE(1)<9> PORTF<0> PORTG<9:6, 3:2> PORTA(1)<15:14, 5:0> PORTC(1)<3:1> PORTD(1)<15:8, 5:0> Tolerates input levels above VDD, useful 5.5V PORTE(1)<8:0> for most standard logic. PORTF(1)<13:12, 8:7, 5:1> PORTG(1)<15:12, 1:0> Note 1: Not all of the pins of these PORTS are implemented in 64-pin devices (PIC24FJXXXDAX06); refer to the device pinout diagrams for the details. DS39969B-page 158  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-1: ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 U-0 — — — — — ANSA10 ANSA9 — bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSA7 ANSA6 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 ANSA<10:9>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 8 Unimplemented: Read as ‘0’ bit 7-6 ANSA<7:6>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as ‘0’ Note 1: This register is not available on 64-pin devices (PIC24FJXXXDAX06).  2010 Microchip Technology Inc. DS39969B-page 159

PIC24FJ256DA210 FAMILY REGISTER 10-2: ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9 ANSB8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 ANSB<15:0>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled REGISTER 10-3: ANSC: PORTC ANALOG FUNCTION SELECTION REGISTER U-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 — ANSC14 ANSC13 — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 U-0 U-0 U-0 U-0 — — — ANSC4(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-13 ANSC<14:13>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 12-5 Unimplemented: Read as ‘0’ bit 4 ANSC4: Analog Function Selection bit(1) 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: This bit is not available on 64-pin devices (PIC24FJXXXDAX06). DS39969B-page 160  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-4: ANSD: PORTD ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSD7 ANSD6 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 ANSD<7:6>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as ‘0’ REGISTER 10-5: ANSE: PORTE ANALOG FUNCTION SELECTION REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 U-0 — — — — — — ANSE9 — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 ANSE9: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 8-0 Unimplemented: Read as ‘0’ Note 1: This register is not available in 64-pin devices (PIC24FJXXXDAX06).  2010 Microchip Technology Inc. DS39969B-page 161

PIC24FJ256DA210 FAMILY REGISTER 10-6: ANSF: PORTF ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 — — — — — — — ANSF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 ANSF0: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled REGISTER 10-7: ANSG: PORTG ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 — — — — — — ANSG9 ANSG8 bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSG7 ANSG6 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-6 ANSG<9:6>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as ‘0’ DS39969B-page 162  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 10.3 Input Change Notification when push button or keypad devices are connected. The pull-ups and pull-downs are separately enabled The input change notification function of the I/O ports using the CNPU1 through CNPU6 registers (for allows the PIC24FJ256DA210 family of devices to gen- pull-ups), and the CNPD1 through CNPD6 registers erate interrupt requests to the processor in response to (for pull-downs). Each CN pin has individual control bits a Change-Of-State (COS) on selected input pins. This for its pull-up and pull-down. Setting a control bit feature is capable of detecting input Change-Of-States, enables the weak pull-up or pull-down for the even in Sleep mode, when the clocks are disabled. corresponding pin. Depending on the device pin count, there are up to When the internal pull-up is selected, the pin pulls up to 84external inputs that may be selected (enabled) for generating an interrupt request on a Change-Of-State. VDD – 1.1V (typical). When the internal pull-down is selected, the pin pulls down to VSS. Registers, CNEN1 through CNEN6, contain the inter- rupt enable control bits for each of the CN input pins. Note: Pull-ups on change notification pins Setting any of these bits enables a CN interrupt for the should always be disabled whenever the corresponding pins. port pin is configured as a digital output. Each CN pin has a both a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current Note: To use CN83 and CN84, which are on the source that is connected to the pin, while the D+ and D- pins, the UTRDIS bit pull-downs act as a current sink that is connected to the (U1CNFG2<0>) should be set. pin. These eliminate the need for external resistors EXAMPLE 10-1: PORT WRITE/READ IN ASSEMBLY MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction EXAMPLE 10-2: PORT WRITE/READ IN ‘C’ TRISB = 0xFF00; // Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Nop(); // Delay 1 cycle If (PORTBbits.RB13){ }; // Next Instruction  2010 Microchip Technology Inc. DS39969B-page 163

PIC24FJ256DA210 FAMILY 10.4 Peripheral Pin Select (PPS) A key difference between pin select and non-pin select peripherals is that pin select peripherals are not asso- A major challenge in general purpose devices is provid- ciated with a default I/O pin. The peripheral must ing the largest possible set of peripheral features while always be assigned to a specific I/O pin before it can be minimizing the conflict of features on I/O pins. In an used. In contrast, non pin select peripherals are always application that needs to use more than one peripheral available on a default pin, assuming that the peripheral multiplexed on a single pin, inconvenient work arounds is active and not conflicting with another peripheral. in application code or a complete redesign may be the only option. 10.4.2.1 Peripheral Pin Select Function The Peripheral Pin Select (PPS) feature provides an Priority alternative to these choices by enabling the user’s Pin-selectable peripheral outputs (e.g., OC, UART peripheral set selection and its placement on a wide transmit) will take priority over general purpose digital range of I/O pins. By increasing the pinout options functions on a pin, such as EPMP and port I/O. Special- available on a particular device, users can better tailor ized digital outputs, such as USB functionality, will take the microcontroller to their entire application, rather priority over PPS outputs on the same pin. The pin than trimming the application to fit the device. diagrams list peripheral outputs in the order of priority. The Peripheral Pin Select feature operates over a fixed Refer to them for priority concerns on a particular pin. subset of digital I/O pins. Users may independently Unlike PIC24F devices with fixed peripherals, pin map the input and/or output of any one of many digital selectable peripheral inputs will never take ownership peripherals to any one of these I/O pins. PPS is per- of a pin. The pin’s output buffer will be controlled by the formed in software and generally does not require the TRISx setting or by a fixed peripheral on the pin. If the device to be reprogrammed. Hardware safeguards are pin is configured in digital mode then the PPS input will included that prevent accidental or spurious changes to operate correctly. If an analog function is enabled on the peripheral mapping once it has been established. the pin the PPS input will be disabled. 10.4.1 AVAILABLE PINS 10.4.3 CONTROLLING PERIPHERAL PIN The PPS feature is used with a range of up to 44 pins, SELECT depending on the particular device and its pin count. PPS features are controlled through two sets of Special Pins that support the Peripheral Pin Select feature Function Registers (SFRs): one to map peripheral include the designation, “RPn” or “RPIn”, in their full pin inputs and one to map outputs. Because they are designation, where “n” is the remappable pin number. separately controlled, a particular peripheral’s input “RP” is used to designate pins that support both remap- and output (if the peripheral has both) can be placed on pable input and output functions, while “RPI” indicates any selectable function pin without constraint. pins that support remappable input functions only. The association of a peripheral to a PIC24FJ256DA210 family devices support a larger peripheral-selectable pin is handled in two different number of remappable input only pins than remappable ways, depending on if an input or an output is being input/output pins. In this device family, there are up to mapped. 32 remappable input/output pins, depending on the pin count of the particular device selected; these are num- 10.4.3.1 Input Mapping bered, RP0 through RP31. Remappable input only pins The inputs of the Peripheral Pin Select options are are numbered above this range, from RPI32 to RPI43 mapped on the basis of the peripheral; that is, a control (or the upper limit for that particular device). register associated with a peripheral dictates the pin it See Table1-1 for a summary of pinout options in each will be mapped to. The RPINRx registers are used to package offering. configure peripheral input mapping (see Register10-8 through Register10-28). Each register contains two 10.4.2 AVAILABLE PERIPHERALS sets of 6-bit fields, with each set associated with one of The peripherals managed by the PPS are all digital the pin-selectable peripherals. Programming a given only peripherals. These include general serial commu- peripheral’s bit field with an appropriate 6-bit value nications (UART and SPI), general purpose timer clock maps the RPn/RPIn pin with that value to that inputs, timer related peripherals (input capture and out- peripheral. For any given device, the valid range of put compare) and external interrupt inputs. Also values for any of the bit fields corresponds to the max- included are the outputs of the comparator module, imum number of Peripheral Pin Selections supported since these are discrete digital signals. by the device. PPS is not available for I2C™, change notification inputs, RTCC alarm outputs, EPMP signals, graphics controller signals or peripherals with analog inputs. DS39969B-page 164  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 10-3: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Mapping Input Name Function Name Register Bits External Interrupt 1 INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> External Interrupt 3 INT3 RPINR1 INT3R<5:0> External Interrupt 4 INT4 RPINR2 INT4R<5:0> Input Capture 1 IC1 RPINR7 IC1R<5:0> Input Capture 2 IC2 RPINR7 IC2R<5:0> Input Capture 3 IC3 RPINR8 IC3R<5:0> Input Capture 4 IC4 RPINR8 IC4R<5:0> Input Capture 5 IC5 RPINR9 IC5R<5:0> Input Capture 6 IC6 RPINR9 IC6R<5:0> Input Capture 7 IC7 RPINR10 IC7R<5:0> Input Capture 8 IC8 RPINR10 IC8R<5:0> Input Capture 9 IC9 RPINR15 IC9R<5:0> Output Compare Fault A OCFA RPINR11 OCFAR<5:0> Output Compare Fault B OCFB RPINR11 OCFBR<5:0> SPI1 Clock Input SCK1IN RPINR20 SCK1R<5:0> SPI1 Data Input SDI1 RPINR20 SDI1R<5:0> SPI1 Slave Select Input SS1IN RPINR21 SS1R<5:0> SPI2 Clock Input SCK2IN RPINR22 SCK2R<5:0> SPI2 Data Input SDI2 RPINR22 SDI2R<5:0> SPI2 Slave Select Input SS2IN RPINR23 SS2R<5:0> SPI3 Clock Input SCK3IN RPINR28 SCK3R<5:0> SPI3 Data Input SDI3 RPINR28 SDI3R<5:0> SPI3 Slave Select Input SS3IN RPINR29 SS3R<5:0> Timer2 External Clock T2CK RPINR3 T2CKR<5:0> Timer3 External Clock T3CK RPINR3 T3CKR<5:0> Timer4 External Clock T4CK RPINR4 T4CKR<5:0> Timer5 External Clock T5CK RPINR4 T5CKR<5:0> UART1 Clear To Send U1CTS RPINR18 U1CTSR<5:0> UART1 Receive U1RX RPINR18 U1RXR<5:0> UART2 Clear To Send U2CTS RPINR19 U2CTSR<5:0> UART2 Receive U2RX RPINR19 U2RXR<5:0> UART3 Clear To Send U3CTS RPINR21 U3CTSR<5:0> UART3 Receive U3RX RPINR17 U3RXR<5:0> UART4 Clear To Send U4CTS RPINR27 U4CTSR<5:0> UART4 Receive U4RX RPINR27 U4RXR<5:0> Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.  2010 Microchip Technology Inc. DS39969B-page 165

PIC24FJ256DA210 FAMILY 10.4.3.2 Output Mapping corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see In contrast to inputs, the outputs of the Peripheral Pin Table10-4). Select options are mapped on the basis of the pin. In this case, a control register associated with a particular Because of the mapping technique, the list of peripher- pin dictates the peripheral output to be mapped. The als for output mapping also includes a null value of RPORx registers are used to control output mapping. ‘000000’. This permits any given pin to remain discon- Each register contains two 6-bit fields, with each field nected from the output of any of the pin-selectable being associated with one RPn pin (see Register10-29 peripherals. through Register10-44). The value of the bit field TABLE 10-4: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Number(1) Function Output Name 0 NULL(2) Null 1 C1OUT Comparator 1 Output 2 C2OUT Comparator 2 Output 3 U1TX UART1 Transmit 4 U1RTS(3) UART1 Request To Send 5 U2TX UART2 Transmit 6 U2RTS(3) UART2 Request To Send 7 SDO1 SPI1 Data Output 8 SCK1OUT SPI1 Clock Output 9 SS1OUT SPI1 Slave Select Output 10 SDO2 SPI2 Data Output 11 SCK2OUT SPI2 Clock Output 12 SS2OUT SPI2 Slave Select Output 18 OC1 Output Compare 1 19 OC2 Output Compare 2 20 OC3 Output Compare 3 21 OC4 Output Compare 4 22 OC5 Output Compare 5 23 OC6 Output Compare 6 24 OC7 Output Compare 7 25 OC8 Output Compare 8 28 U3TX UART3 Transmit 29 U3RTS(3) UART3 Request To Send 30 U4TX UART4 Transmit 31 U4RTS(3) UART4 Request To Send 32 SDO3 SPI3 Data Output 33 SCK3OUT SPI3 Clock Output 34 SS3OUT SPI3 Slave Select Output 35 OC9 Output Compare 9 36 C3OUT Comparator 3 Output 37-63 (unused) NC Note 1: Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. 2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. 3: IrDA® BCLK functionality uses this output. DS39969B-page 166  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 10.4.3.3 Mapping Limitations 10.4.4.1 Control Register Lock The control schema of the Peripheral Pin Select is Under normal operation, writes to the RPINRx and extremely flexible. Other than systematic blocks that RPORx registers are not allowed. Attempted writes will prevent signal contention, caused by two physical pins appear to execute normally, but the contents of the being configured as the same functional input or two registers will remain unchanged. To change these reg- functional outputs configured as the same pin, there isters, they must be unlocked in hardware. The register are no hardware enforced lock outs. The flexibility lock is controlled by the IOLOCK bit (OSCCON<6>). extends to the point of allowing a single input to drive Setting IOLOCK prevents writes to the control multiple peripherals or a single functional output to registers; clearing IOLOCK allows writes. drive multiple output pins. To set or clear IOLOCK, a specific command sequence must be executed: 10.4.3.4 Mapping Exceptions for PIC24FJ256DA210 Devices 1. Write 46h to OSCCON<7:0>. 2. Write 57h to OSCCON<7:0>. Although the PPS registers theoretically allow for up to 64 remappable I/O pins, not all of these are imple- 3. Clear (or set) IOLOCK as a single operation. mented in all devices. For PIC24FJ256DA210 family Unlike the similar sequence with the oscillator’s LOCK devices, the maximum number of remappable pins bit, IOLOCK remains in one state until changed. This available are 44, which includes 12 input only pins. In allows all of the Peripheral Pin Selects to be configured addition, some pins in the RP and RPI sequences are with a single unlock sequence, followed by an update unimplemented in lower pin count devices. The to all control registers, then locked with a second lock differences in available remappable pins are sequence. summarized in Table10-5. 10.4.4.2 Continuous State Monitoring When developing applications that use remappable pins, users should also keep these things in mind: In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are • For the RPINRx registers, bit combinations corre- constantly monitored in hardware by shadow registers. sponding to an unimplemented pin for a particular If an unexpected change in any of the registers occurs device are treated as invalid; the corresponding (such as cell disturbances caused by ESD or other module will not have an input mapped to it. For all external events), a Configuration Mismatch Reset will PIC24FJ256DA210 family devices, this includes be triggered. all values greater than 43 (‘101011’). • For RPORx registers, the bit fields corresponding 10.4.4.3 Configuration Bit Pin Select Lock to an unimplemented pin will also be unimple- As an additional level of safety, the device can be con- mented. Writing to these fields will have no effect. figured to prevent more than one write session to the 10.4.4 CONTROLLING CONFIGURATION RPINRx and RPORx registers. The IOL1WAY CHANGES (CW2<4>) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If Because peripheral remapping can be changed during IOLOCK remains set, the register unlock procedure will run time, some restrictions on peripheral remapping not execute and the Peripheral Pin Select Control reg- are needed to prevent accidental configuration isters cannot be written to. The only way to clear the bit changes. PIC24F devices include three features to and re-enable peripheral remapping is to perform a prevent alterations to the peripheral map: device Reset. • Control register lock sequence In the default (unprogrammed) state, IOL1WAY is set, • Continuous state monitoring restricting users to one write session. Programming • Configuration bit remapping lock IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. TABLE 10-5: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ256DA210 FAMILY DEVICES RP Pins (I/O) RPI Pins Device Pin Count Total Unimplemented Total Unimplemented 64-Pin 28 RP5, RP15, RP30, RP31 1 RPI32-36, RPI38-43 (PIC24FJXXXDAX06) 100/121-Pin 32 — 12 — (PIC24FJXXXDAX10)  2010 Microchip Technology Inc. DS39969B-page 167

PIC24FJ256DA210 FAMILY 10.4.5 CONSIDERATIONS FOR Along these lines, configuring a remappable pin for a PERIPHERAL PIN SELECTION specific peripheral does not automatically turn that feature on. The peripheral must be specifically config- The ability to control Peripheral Pin Selection intro- ured for operation, and enabled as if it were tied to a fixed duces several considerations into application design pin. Where this happens in the application code (immedi- that could be overlooked. This is particularly true for ately following device Reset and peripheral configuration several common peripherals that are available only as or inside the main application routine) depends on the remappable peripherals. peripheral and its use in the application. The main consideration is that the Peripheral Pin A final consideration is that Peripheral Pin Select func- Selects are not available on default pins in the device’s tions neither override analog inputs nor reconfigure default (Reset) state. Since all RPINRx registers reset pins with analog functions for digital I/O. If a pin is to ‘111111’ and all RPORx registers reset to ‘000000’, configured as an analog input on device Reset, it must all Peripheral Pin Select inputs are tied to VSS and all be explicitly reconfigured as digital I/O when used with Peripheral Pin Select outputs are disconnected. a Peripheral Pin Select. Note: In tying Peripheral Pin Select inputs to Example10-3 shows a configuration for bidirectional RP63, RP63 need not exist on a device for communication with flow control using UART1. The the registers to be reset to it. following input and output functions are used: This situation requires the user to initialize the device • Input Functions: U1RX, U1CTS with the proper peripheral configuration before any • Output Functions: U1TX, U1RTS other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to EXAMPLE 10-3: CONFIGURING UART1 execute the unlock sequence after the device has INPUT AND OUTPUT come out of Reset. For application safety, however, it is FUNCTIONS best to set IOLOCK and lock the configuration after writing to the control registers. // Unlock Registers asm volatile( "MOV #OSCCON, w1 \n" Because the unlock sequence is timing-critical, it must "MOV #0x46, w2 \n" be executed as an assembly language routine in the "MOV #0x57, w3 \n" same manner as changes to the oscillator configura- "MOV.b w2, [w1] \n" tion. If the bulk of the application is written in ‘C’, or "MOV.b w3, [w1] \n" another high-level language, the unlock sequence "BCLR OSCCON,#6"); should be performed by writing in-line assembly. // or use C30 built-in macro: Choosing the configuration requires the review of all // __builtin_write_OSCCONL(OSCCON & 0xbf); Peripheral Pin Selects and their pin assignments, especially those that will not be used in the application. // Configure Input Functions (Table 10-2)) In all cases, unused pin-selectable peripherals should // Assign U1RX To Pin RP0 be disabled completely. Unused peripherals should RPINR18bits.U1RXR = 0; have their inputs assigned to an unused RPn/RPIn pin function. I/O pins with unused RPn functions should be // Assign U1CTS To Pin RP1 configured with the null peripheral output. RPINR18bits.U1CTSR = 1; The assignment of a peripheral to a particular pin does // Configure Output Functions (Table 10-4) not automatically perform any other configuration of the // Assign U1TX To Pin RP2 pin’s I/O circuitry. In theory, this means adding a RPOR1bits.RP2R = 3; pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is // Assign U1RTS To Pin RP3 driven. Users must be familiar with the behavior of RPOR1bits.RP3R = 4; other fixed peripherals that share a remappable pin and // Lock Registers know when to enable or disable them. To be safe, fixed asm volatile ("MOV #OSCCON, w1 \n" digital peripherals that share the same pin should be "MOV #0x46, w2 \n" disabled when not in use. "MOV #0x57, w3 \n" "MOV.b w2, [w1]\ n" "MOV.b w3, [w1] \n" "BSET OSCCON, #6") ; // or use C30 built-in macro: // __builtin_write_OSCCONL(OSCCON | 0x40); DS39969B-page 168  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 10.4.6 PERIPHERAL PIN SELECT Note: Input and output register values can only be REGISTERS changed if IOLOCK (OSCCON<6>) = 0. The PIC24FJ256DA210 family of devices implements See Section10.4.4.1 “Control Register a total of 37 registers for remappable peripheral Lock” for a specific command sequence. configuration: • Input Remappable Peripheral Registers (21) • Output Remappable Peripheral Registers (16) REGISTER 10-8: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT1R<5:0>: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ REGISTER 10-9: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT3R5 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39969B-page 169

PIC24FJ256DA210 FAMILY REGISTER 10-10: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT4R<5:0>: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits REGISTER 10-11: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T3CKR<5:0>: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits DS39969B-page 170  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-12: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T5CKR<5:0>: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T4CKR<5:0>: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits REGISTER 10-13: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39969B-page 171

PIC24FJ256DA210 FAMILY REGISTER 10-14: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC4R<5:0>: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC3R<5:0>: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits REGISTER 10-15: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC6R5 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC5R5 IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC6R<5:0>: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC5R<5:0>: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits DS39969B-page 172  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-16: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC8R5 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC8R<5:0>: Assign Input Capture 8 (IC8) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC7R<5:0>: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits REGISTER 10-17: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39969B-page 173

PIC24FJ256DA210 FAMILY REGISTER 10-18: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC9R5 IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC9R<5:0>: Assign Input Capture 9 (IC9) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ REGISTER 10-19: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3RXR<5:0>: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ DS39969B-page 174  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-20: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR<5:0>: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U1RXR<5:0>: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits REGISTER 10-21: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39969B-page 175

PIC24FJ256DA210 FAMILY REGISTER 10-22: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R<5:0>: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits REGISTER 10-23: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3CTSR<5:0>: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R<5:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits DS39969B-page 176  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-24: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK2R<5:0>: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI2R<5:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits REGISTER 10-25: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39969B-page 177

PIC24FJ256DA210 FAMILY REGISTER 10-26: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U4CTSR<5:0>: Assign UART4 Clear to Send (U4CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U4RXR<5:0>: Assign UART4 Receive (U4RX) to Corresponding RPn or RPIn Pin bits REGISTER 10-27: RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK3R5 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI3R5 SDI3R4 SDI3R3 SDI3R2 SDI3R1 SDI3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK3R<5:0>: Assign SPI3 Clock Input (SCK3IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI3R<5:0>: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits DS39969B-page 178  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-28: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS3R5 SS3R4 SS3R3 SS3R2 SS3R1 SS3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS3R<5:0>: Assign SPI3 Slave Select Input (SS31IN) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39969B-page 179

PIC24FJ256DA210 FAMILY REGISTER 10-29: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP1R<5:0>: RP1 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP1 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP0R<5:0>: RP0 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP0 (see Table10-4 for peripheral function numbers). REGISTER 10-30: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP3R<5:0>: RP3 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP3 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP2R<5:0>: RP2 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP2 (see Table10-4 for peripheral function numbers). DS39969B-page 180  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-31: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP5R<5:0>: RP5 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP5 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP4R<5:0>: RP4 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP4 (see Table10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as ‘0’. REGISTER 10-32: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP7R<5:0>: RP7 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP7 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R<5:0>: RP6 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP6 (see Table10-4 for peripheral function numbers).  2010 Microchip Technology Inc. DS39969B-page 181

PIC24FJ256DA210 FAMILY REGISTER 10-33: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP9R<5:0>: RP9 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP9 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP8R<5:0>: RP8 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP8 (see Table10-4 for peripheral function numbers). REGISTER 10-34: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP11R<5:0>: RP11 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP11 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP10R<5:0>: RP10 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP10 (see Table10-4 for peripheral function numbers). DS39969B-page 182  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-35: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP13R<5:0>: RP13 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP13 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP12R<5:0>: RP12 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP12 (see Table10-4 for peripheral function numbers). REGISTER 10-36: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP15R<5:0>: RP15 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP0 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP14 (see Table10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as ‘0’.  2010 Microchip Technology Inc. DS39969B-page 183

PIC24FJ256DA210 FAMILY REGISTER 10-37: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP17R<5:0>: RP17 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP17 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP16R<5:0>: RP16 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP16 (see Table10-4 for peripheral function numbers). REGISTER 10-38: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP19R<5:0>: RP19 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP19 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP18R<5:0>: RP18 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP18 (see Table10-4 for peripheral function numbers). DS39969B-page 184  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-39: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP21R<5:0>: RP21 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP21 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP20R<5:0>: RP20 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP20 (see Table10-4 for peripheral function numbers). REGISTER 10-40: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP23R<5:0>: RP23 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP23 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP22 (see Table10-4 for peripheral function numbers).  2010 Microchip Technology Inc. DS39969B-page 185

PIC24FJ256DA210 FAMILY REGISTER 10-41: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP25R<5:0>: RP25 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP25 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP24R<5:0>: RP24 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP24 (see Table10-4 for peripheral function numbers). REGISTER 10-42: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP27R<5:0>: RP27 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP27 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP26R<5:0>: RP26 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP26 (see Table10-4 for peripheral function numbers). DS39969B-page 186  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 10-43: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP29R<5:0>: RP29 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP29 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP28R<5:0>: RP28 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP28 (see Table10-4 for peripheral function numbers). REGISTER 10-44: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP31R5 RP31R4 RP31R3 RP31R2 RP31R1 RP31R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP30R5 RP30R4 RP30R3 RP30R2 RP30R1 RP30R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP31R<5:0>: RP31 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP31 (see Table10-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP30R<5:0>: RP30 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP30 (see Table10-4 for peripheral function numbers). Note 1: Unimplemented in 64-pin devices; read as ‘0’.  2010 Microchip Technology Inc. DS39969B-page 187

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 188  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 11.0 TIMER1 Figure11-1 presents a block diagram of the 16-bit timer module. Note: This data sheet summarizes the features To configure Timer1 for operation: of this group of PIC24F devices. It is not intended to be a comprehensive reference 1. Set the TON bit (= 1). source. For more information, refer to the 2. Select the timer prescaler ratio using the “PIC24F Family Reference Manual”, TCKPS<1:0> bits. Section 14. “Timers” (DS39704). The 3. Set the Clock and Gating modes using the TCS information in this data sheet supersedes and TGATE bits. the information in the FRM. 4. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. The Timer1 module is a 16-bit timer, which can serve as the time counter for the Real-Time Clock (RTC) or 5. Load the timer period value into the PR1 operate as a free-running, interval timer/counter. register. Timer1 can operate in three modes: 6. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP<2:0>, to set • 16-Bit Timer the interrupt priority. • 16-Bit Synchronous Counter • 16-Bit Asynchronous Counter Timer1 also supports these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation during CPU Idle and Sleep modes • Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS<1:0> TON 2 SOSCO/ 1x T1CK Gate Prescaler SOSCEN Sync 01 1, 8, 64, 256 SOSCI TCY 00 TGATE TGATE TCS 1 Q D Set T1IF 0 Q CK 0 Reset TMR1 1 Sync Comparator TSYNC Equal PR1  2010 Microchip Technology Inc. DS39969B-page 189

PIC24FJ256DA210 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS39969B-page 190  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 12.0 TIMER2/3 AND TIMER4/5 To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). Note: This data sheet summarizes the features 2. Select the prescaler ratio for Timer2 or Timer4 of this group of PIC24F devices. It is not using the TCKPS<1:0> bits. intended to be a comprehensive reference source. For more information, refer to the 3. Set the Clock and Gating modes using the TCS “PIC24F Family Reference Manual”, and TGATE bits. If TCS is set to an external Section 14. “Timers” (DS39704). The clock, RPINRx (TxCK) must be configured to information in this data sheet supersedes an available RPn/RPIn pin. For more informa- the information in the FRM. tion, see Section 10.4“Peripheral Pin Select (PPS)”. The Timer2/3 and Timer4/5 modules are 32-bit timers, 4. Load the timer period value. PR3 (or PR5) will which can also be configured as four independent, 16-bit contain the most significant word (msw) of the timers with selectable operating modes. value while PR2 (or PR4) contains the least As 32-bit timers, Timer2/3 and Timer4/5 can each significant word (lsw). operate in three modes: 5. If interrupts are required, set the interrupt enable • Two independent 16-bit timers with all 16-bit bit, T3IE or T5IE; use the priority bits, T3IP<2:0> operating modes (except Asynchronous Counter or T5IP<2:0>, to set the interrupt priority. Note mode) that while Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 • Single 32-bit timer interrupt. • Single 32-bit synchronous counter 6. Set the TON bit (= 1). They also support these features: The timer value, at any point, is stored in the register • Timer Gate Operation pair, TMR<3:2> (or TMR<5:4>). TMR3 (TMR5) always • Selectable Prescaler Settings contains the most significant word of the count, while • Timer Operation during Idle and Sleep modes TMR2 (TMR4) contains the least significant word. • Interrupt on a 32-Bit Period Register Match To configure any of the timers for individual 16-bit • ADC Event Trigger (only on Timer2/3 in 32-bit operation: mode and Timer3 in 16-bit mode) 1. Clear the T32 bit corresponding to that timer Individually, all four of the 16-bit timers can function as (T2CON<3> for Timer2 and Timer3 or synchronous timers or counters. They also offer the T4CON<3> for Timer4 and Timer5). features listed above, except for the ADC Event 2. Select the timer prescaler ratio using the Trigger; this is implemented only on Timer2/3 in 32-bit TCKPS<1:0> bits. mode and Timer3 in 16-bit mode. The operating modes 3. Set the Clock and Gating modes using the TCS and enabled features are determined by setting the and TGATE bits. See Section 10.4“Peripheral appropriate bit(s) in the T2CON, T3CON, T4CON and Pin Select (PPS)” for more information. T5CON registers. T2CON and T4CON are shown in 4. Load the timer period value into the PRx register. generic form in Register12-1; T3CON and T5CON are 5. If interrupts are required, set the interrupt enable shown in Register12-2. bit, TxIE; use the priority bits, TxIP<2:0>, to set For 32-bit timer/counter operation, Timer2 and Timer4 the interrupt priority. are the least significant word; Timer3 and Timer4 are 6. Set the TON (TxCON<15> = 1) bit. the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2010 Microchip Technology Inc. DS39969B-page 191

PIC24FJ256DA210 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> TON 2 T2CK 1x (T4CK) Gate Prescaler Sync 01 1, 8, 64, 256 TCY 00 TGATE TGATE(2) TCS(2) 1 Q D Set T3IF (T5IF) Q CK 0 PR3 PR2 (PR5) (PR4) ADC Event Trigger(3) Equal Comparator MSB LSB TMR3 TMR2 Sync Reset (TMR5) (TMR4) 16 Read TMR2 (TMR4)(1) Write TMR2 (TMR4)(1) 16 TMR3HLD 16 (TMR5HLD) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. 2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4“Peripheral Pin Select (PPS)” for more information. 3: The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39969B-page 192  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TCKPS<1:0> TON 2 T2CK 1x (T4CK) Gate Prescaler Sync 01 1, 8, 64, 256 TGATE 00 TCY TCS(1) 1 Q D TGATE(1) Set T2IF (T4IF) Q CK 0 Reset TMR2 (TMR4) Sync Comparator Equal PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4“Peripheral Pin Select (PPS)” for more information. FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM TCKPS<1:0> T3CK TON 2 Sync 1x (T5CK) Prescaler 01 1, 8, 64, 256 TGATE 00 TCY TCS(1) 1 Q D TGATE(1) Set T3IF (T5IF) Q CK 0 Reset TMR3 (TMR5) ADC Event Trigger(2) Comparator Equal PR3 (PR5) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4“Peripheral Pin Select (PPS)” for more information. 2: The ADC event trigger is available only on Timer3.  2010 Microchip Technology Inc. DS39969B-page 193

PIC24FJ256DA210 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON<3> = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit(1) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(2) 1 = External clock from pin, TxCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation. 2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. For more information, see Section 10.4“Peripheral Pin Select (PPS)”. 3: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS39969B-page 194  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(1,2) 1 = External clock from pin, TyCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON. 2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. See Section 10.4“Peripheral Pin Select (PPS)” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.  2010 Microchip Technology Inc. DS39969B-page 195

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 196  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 13.0 INPUT CAPTURE WITH 13.1 General Operating Modes DEDICATED TIMERS 13.1.1 SYNCHRONOUS AND TRIGGER Note: This data sheet summarizes the features MODES of this group of PIC24F devices. It is not When the input capture module operates in a intended to be a comprehensive reference free-running mode, the internal 16-bit counter, source. For more information, refer to the ICxTMR, counts up continuously, wrapping around “PIC24F Family Reference Manual”, from FFFFh to 0000h on each overflow, with its period Section 34. “Input Capture with synchronized to the selected external clock source. Dedicated Timer” (DS39722). The infor- When a capture event occurs, the current 16-bit value mation in this data sheet supersedes the of the internal counter is written to the FIFO buffer. information in the FRM. In Synchronous mode, the module begins capturing Devices in the PIC24FJ256DA210 family comprise events on the ICx pin as soon as its selected clock nineindependent input capture modules. Each of the source is enabled. Whenever an event occurs on the modules offers a wide range of configuration and selected sync source, the internal counter is reset. In operating options for capturing external pulse events Trigger mode, the module waits for a Sync event from and generating interrupts. another internal module to occur before allowing the Key features of the input capture module include: internal counter to run. • Hardware configurable for 32-bit operation in all Standard, free-running operation is selected by setting modes by cascading two adjacent modules the SYNCSEL bits (ICxCON2<4:0>) to ‘00000’ and clearing the ICTRIG bit (ICxCON2<7>). Synchronous • Synchronous and Trigger modes of output and Trigger modes are selected any time the compare operation, with up to 30 user-selectable SYNCSEL bits are set to any value except ‘00000’. sync/trigger sources available The ICTRIG bit selects either Synchronous or Trigger • A 4-level FIFO buffer for capturing and holding mode; setting the bit selects Trigger mode operation. In timer values for several events both modes, the SYNCSEL bits determine the • Configurable interrupt generation sync/trigger source. • Up to 6 clock sources available for each module, When the SYNCSEL bits are set to ‘00000’ and driving a separate internal 16-bit counter ICTRIG is set, the module operates in Software Trigger The module is controlled through two registers: mode. In this case, capture operations are started by ICxCON1 (Register13-1) and ICxCON2 (Register13-2). manually setting the TRIGSTAT bit (ICxCON2<6>). A general block diagram of the module is shown in Figure13-1. FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM ICM<2:0> ICI1<:0> Prescaler Edge Detect Logic Event and Set ICXIF Counter and Interrupt 1:1/4/16 Clock Synchronizer Logic ICX Pin(1) ICTSEL<2:0> Increment 16 IC Clock Clock ICXTMR 4-Level FIFO Buffer Sources Select 16 Reset 16 Sync and Sync and Trigger ICXBUF Trigger Sources Logic SYNCSEL<4:0> Trigger ICOV, ICBNE System Bus Note 1: The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 197

PIC24FJ256DA210 FAMILY 13.1.2 CASCADED (32-BIT) MODE For 32-bit cascaded operations, the setup procedure is slightly different: By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent 1. Set the IC32 bits for both modules even and odd modules can be configured to function as (ICyCON2<8>) and (ICxCON2<8>), enabling a single 32-bit module. (For example, Modules 1 and 2 the even numbered module first. This ensures are paired, as are Modules 3 and 4, and so on.) The the modules will start functioning in unison. odd numbered module (ICx) provides the Least Signif- 2. Set the ICTSEL and SYNCSEL bits for both icant 16 bits of the 32-bit register pairs and the even modules to select the same sync/trigger and module (ICy) provides the Most Significant 16 bits. time base source. Set the even module first, Wrap-arounds of the ICx registers cause an increment then the odd module. Both modules must use of their corresponding ICy registers. the same ICTSEL and SYNCSEL settings. Cascaded operation is configured in hardware by 3. Clear the ICTRIG bit of the even module setting the IC32 bits (ICxCON2<8>) for both modules. (ICyCON2<7>). This forces the module to run in Synchronous mode with the odd module, 13.2 Capture Operations regardless of its trigger setting. 4. Use the odd module’s ICI bits (ICxCON1<6:5>) The input capture module can be configured to capture to set the desired interrupt frequency. timer values and generate interrupts on rising edges on 5. Use the ICTRIG bit of the odd module ICx or all transitions on ICx. Captures can be config- (ICxCON2<7>) to configure Trigger or ured to occur on all rising edges or just some (every 4th Synchronous mode operation. or 16th). Interrupts can be independently configured to generate on each event or a subset of events. Note: For Synchronous mode operation, enable the sync source as the last step. Both To set up the module for capture operations: input capture modules are held in Reset 1. Configure the ICx input for one of the available until the sync source is enabled. Peripheral Pin Select pins. 6. Use the ICM bits of the odd module 2. If Synchronous mode is to be used, disable the (ICxCON1<2:0>) to set the desired capture sync source before proceeding. mode. 3. Make sure that any previous data has been The module is ready to capture events when the time removed from the FIFO by reading ICxBUF until base and the sync/trigger source are enabled. When the ICBNE bit (ICxCON1<3>) is cleared. the ICBNE bit (ICxCON1<3>) becomes set, at least 4. Set the SYNCSEL bits (ICxCON2<4:0>) to the one capture value is available in the FIFO. Read input desired sync/trigger source. capture values from the FIFO until the ICBNE clears to 5. Set the ICTSEL bits (ICxCON1<12:10>) for the ‘0’. desired clock source. For 32-bit operation, read both the ICxBUF and 6. Set the ICI bits (ICxCON1<6:5>) to the desired ICyBUF for the full 32-bit timer value (ICxBUF for the interrupt frequency lsw, ICyBUF for the msw). At least one capture value is 7. Select Synchronous or Trigger mode operation: available in the FIFO buffer when the odd module’s a) Check that the SYNCSEL bits are not set to ICBNE bit (ICxCON1<3>) becomes set. Continue to ‘00000’. read the buffer registers until ICBNE is cleared b) For Synchronous mode, clear the ICTRIG (performed automatically by hardware). bit (ICxCON2<7>). c) For Trigger mode, set ICTRIG, and clear the TRIGSTAT bit (ICxCON2<6>). 8. Set the ICM bits (ICxCON1<2:0>) to the desired operational mode. 9. Enable the selected sync/trigger source. DS39969B-page 198  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 13-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-10 ICTSEL<2:0>: Input Capture Timer Select bits 111 = System clock (FOSC/2) 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer2 000 = Timer3 bit 9-7 Unimplemented: Read as ‘0’ bit 6-5 ICI<1:0>: Select Number of Captures Per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits(1) 111 = Interrupt mode: input capture functions as an interrupt pin only when the device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Prescaler Capture mode: capture on every 16th rising edge 100 = Prescaler Capture mode: capture on every 4th rising edge 011 = Simple Capture mode: capture on every rising edge 010 = Simple Capture mode: capture on every falling edge 001 = Edge Detect Capture mode: capture on every edge (rising and falling), ICI<1:0> bits do not control interrupt generation for this mode 000 = Input capture module turned off Note 1: The ICx input must also be configured to an available RPn/RPIn pin. For more information, see Section10.4 “Peripheral Pin Select (PPS)”.  2010 Microchip Technology Inc. DS39969B-page 199

PIC24FJ256DA210 FAMILY REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0 HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 IC32: Cascade Two IC Modules Enable bit (32-bit operation) 1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = ICx functions independently as a 16-bit module bit 7 ICTRIG: ICx Sync/Trigger Select bit 1 = Trigger ICx from the source designated by the SYNCSELx bits 0 = Synchronize ICx with the source designated by the SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running (set in hardware, can be set in software) 0 = Timer source has not been triggered and is being held clear bit 5 Unimplemented: Read as ‘0’ bit 4-0 SYNCSEL<4:0>: Synchronization/Trigger Source Selection bits 11111 = Reserved 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(1) 11011 = A/D(1) 11010 = Comparator 3(1) 11001 = Comparator 2(1) 11000 = Comparator 1(1) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 1000x = Reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2 01011 = Timer1 01010 = Input Capture 5(2) 01001 = Output Compare 9 . . . 00010 = Output Compare 2 00001 = Output Compare 1 00000 = Not synchronized to any other module Note 1: Use these inputs as trigger sources only and never as sync sources. 2: Never use an IC module as its own trigger source, by selecting this mode. DS39969B-page 200  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 14.0 OUTPUT COMPARE WITH In Synchronous mode, the module begins performing DEDICATED TIMERS its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on Note: This data sheet summarizes the features the selected sync source, the module’s internal counter of this group of PIC24F devices. It is not is reset. In Trigger mode, the module waits for a sync intended to be a comprehensive reference event from another internal module to occur before source. For more information, refer to the allowing the counter to run. “PIC24F Family Reference Manual”, Free-running mode is selected by default or any time Section 35. “Output Compare with that the SYNCSEL bits (OCxCON2<4:0>) are set to Dedicated Timer” (DS39723). The infor- ‘00000’. Synchronous or Trigger modes are selected mation in this data sheet supersedes the any time the SYNCSEL bits are set to any value except information in the FRM. ‘00000’. The OCTRIG bit (OCxCON2<7>) selects either Synchronous or Trigger mode; setting the bit Devices in the PIC24FJ256DA210 family feature all of selects Trigger mode operation. In both modes, the the 9independent output compare modules. Each of SYNCSEL bits determine the sync/trigger source. these modules offers a wide range of configuration and operating options for generating pulse trains on internal 14.1.2 CASCADED (32-BIT) MODE device events, and can produce pulse-width modulated waveforms for driving power applications. By default, each module operates independently with its own set of 16-bit timer and duty cycle registers. To Key features of the output compare module include: increase resolution, adjacent even and odd modules • Hardware configurable for 32-bit operation in all can be configured to function as a single 32-bit module. modes by cascading two adjacent modules (For example, Modules 1 and 2 are paired, as are • Synchronous and Trigger modes of output Modules 3 and 4, and so on.) The odd numbered compare operation, with up to 31 user-selectable module (OCx) provides the Least Significant 16 bits of trigger/sync sources available the 32-bit register pairs and the even module (OCy) provides the Most Significant 16 bits. Wrap-arounds of • Two separate period registers (a main register, the OCx registers cause an increment of their OCxR, and a secondary register, OCxRS) for corresponding OCy registers. greater flexibility in generating pulses of varying widths Cascaded operation is configured in hardware by set- • Configurable for single pulse or continuous pulse ting the OC32 bit (OCxCON2<8>) for both modules. generation on an output event, or continuous For more details on cascading, refer to the “PIC24F PWM waveform generation Family Reference Manual”, Section 35. “Output Compare with Dedicated Timer”. • Up to 6 clock sources available for each module, driving a separate internal 16-bit counter 14.1 General Operating Modes 14.1.1 SYNCHRONOUS AND TRIGGER MODES When the output compare module operates in a free-running mode, the internal 16-bit counter, OCxTMR, runs counts up continuously, wrapping around from 0xFFFF to 0x0000 on each overflow, with its period synchronized to the selected external clock source. Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs.  2010 Microchip Technology Inc. DS39969B-page 201

PIC24FJ256DA210 FAMILY FIGURE 14-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) OCMx OCINV OCxCON1 OCTRIS OCTSELx FLTOUT OCxCON2 SYNCSELx FLTTRIEN TRIGSTAT FLTMD TRIGMODE ENFLT<2:0> OCTRIG OCxR and OCFLT<2:0> DCB<1:0> DCB<1:0> Match Event OCx Pin(1) Comparator Clock Increment OC Clock Select Sources OC Output and OCxTMR Reset Fault Logic Match Event OCFA/OCFB(2) Comparator Match Event Trigger and Trigger and Sync Sources Sync Logic OCxRS Reset OCx Interrupt Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 2: The OCFA/OCFB fault inputs must be assigned to an available RPn/RPIn pin before use. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 14.2 Compare Operations 3. Write the rising edge value to OCxR and the falling edge value to OCxRS. In Compare mode (Figure14-1), the output compare 4. Set the Timer Period register, PRy, to a value module can be configured for single-shot or continuous equal to or greater than the value in OCxRS. pulse generation. It can also repeatedly toggle an 5. Set the OCM<2:0> bits for the appropriate output pin on each timer event. compare operation (= 0xx). To set up the module for compare operations: 6. For Trigger mode operations, set OCTRIG to 1. Configure the OCx output for one of the enable Trigger mode. Set or clear TRIGMODE to available Peripheral Pin Select pins. configure trigger operation and TRIGSTAT to 2. Calculate the required values for the OCxR and select a hardware or software trigger. For (for Double Compare modes) OCxRS Duty Cycle Synchronous mode, clear OCTRIG. registers: 7. Set the SYNCSEL<4:0> bits to configure the a) Determine the instruction clock cycle time. trigger or synchronization source. If free-running Take into account the frequency of the timer operation is required, set the SYNCSEL external clock to the timer source (if one is bits to ‘00000’ (no sync/trigger source). used) and the timer prescaler settings. 8. Select the time base source with the OCTSEL<2:0> bits. If necessary, set the TON b) Calculate time to the rising edge of the bits for the selected timer, which enables the output pulse relative to the timer start value compare time base to count. Synchronous (0000h). mode operation starts as soon as the time base c) Calculate the time to the falling edge of the is enabled; Trigger mode operation starts after a pulse based on the desired pulse width and trigger source event occurs. the time to the rising edge of the pulse. DS39969B-page 202  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY For 32-bit cascaded operation, these steps are also 14.3 Pulse-Width Modulation (PWM) necessary: Mode 1. Set the OC32 bits for both registers In PWM mode, the output compare module can be (OCyCON2<8>) and (OCxCON2<8>). Enable configured for edge-aligned or center-aligned pulse the even numbered module first to ensure the waveform generation. All PWM operations are modules will start functioning in unison. double-buffered (buffer registers are internal to the 2. Clear the OCTRIG bit of the even module module and are not mapped into SFR space). (OCyCON2), so the module will run in Synchronous mode. To configure the output compare module for PWM operation: 3. Configure the desired output and Fault settings for OCy. 1. Configure the OCx output for one of the 4. Force the output pin for OCx to the output state available Peripheral Pin Select pins. by clearing the OCTRIS bit. 2. Calculate the desired duty cycles and load them 5. If Trigger mode operation is required, configure into the OCxR register. the trigger options in OCx by using the OCTRIG 3. Calculate the desired period and load it into the (OCxCON2<7>), TRIGMODE (OCxCON1<3>) OCxRS register. and SYNCSEL (OCxCON2<4:0>) bits. 4. Select the current OCx as the synchronization 6. Configure the desired Compare or PWM mode source by writing 0x1F to the SYNCSEL<4:0> of operation (OCM<2:0>) for OCy first, then for bits (OCxCON2<4:0>) and ‘0’ to the OCTRIG bit OCx. (OCxCON2<7>). Depending on the output mode selected, the module 5. Select a clock source by writing to the holds the OCx pin in its default state and forces a tran- OCTSEL<2:0> bits (OCxCON<12:10>). sition to the opposite state when OCxR matches the 6. Enable interrupts, if required, for the timer and timer. In Double Compare modes, OCx is forced back output compare modules. The output compare to its default state when a match with OCxRS occurs. interrupt is required for PWM Fault pin utilization. The OCxIF interrupt flag is set after an OCxR match in 7. Select the desired PWM mode in the OCM<2:0> Single Compare modes and after each OCxRS match bits (OCxCON1<2:0>). in Double Compare modes. 8. Appropriate Fault inputs may be enabled by using Single-shot pulse events only occur once, but may be the ENFLT<2:0> bits as described in repeated by simply rewriting the value of the Register14-1. OCxCON1 register. Continuous pulse events continue 9. If a timer is selected as a clock source, set the indefinitely until terminated. selected timer prescale value. The selected timer’s prescaler output is used as the clock input for the OCx timer, and not the selected timer output. Note: This peripheral contains input and output functions that may need to be configured by the Peripheral Pin Select. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 203

PIC24FJ256DA210 FAMILY FIGURE 14-2: OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCMx OCxCON2 OCINV OCTSELx OCTRIS SYNCSELx OCxR and FLTOUT TRIGSTAT DCB<1:0> FLTTRIEN TRIGMODE FLTMD OCTRIG Rollover/Reset ENFLT<2:0> OCFLT<2:0> OCxR and DCB<1:0> Buffers DCB<1:0> OCx Pin(1) Comparator OC Clock Clock Increment MEvaetcnht Select Sources OC Output and OCxTMR Rollover Fault Logic Reset OCFA/OCFB(2) Comparator Match Event Match Trigger and Event Trigger and Sync Logic Sync Sources OCxRS Buffer Rollover/Reset OCxRS OCx Interrupt Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 2: The OCFA/OCFB fault inputs must be assigned to an available RPn/RPIn pin before use. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 14.3.1 PWM PERIOD The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation14-1. EQUATION 14-1: CALCULATING THE PWM PERIOD(1) PWM Period = [(PRy) + 1 • TCY • (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled. Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles. DS39969B-page 204  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 14.3.2 PWM DUTY CYCLE • If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty The PWM duty cycle is specified by writing to the cycle). OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty • If OCxRS is greater than PRy, the pin will remain cycle value is not latched until a match between PRy high (100% duty cycle). and TMRy occurs (i.e., the period is complete). This See Example14-1 for PWM mode timing details. provides a double buffer for the PWM duty cycle and is Table14-1 and Table14-2 show example PWM essential for glitchless PWM operation. frequencies and resolutions for a device operating at Some important boundary parameters of the PWM duty 4 MIPS and 10 MIPS, respectively. cycle include: EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1) log10( FCY ) FPWM • (Timer Prescale Value) Maximum PWM Resolution (bits) = bits log (2) 10 Note1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. EXAMPLE 14-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) 1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2ms PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value) 19.2ms = PR2 + 1) • 62.5 ns • 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32MHz device clock rate: PWM Resolution = log10(FCY/FPWM)/log102) bits = (log (16 MHz/52.08 kHz)/log 2) bits 10 10 = 8.3 bits Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1) PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh Resolution (bits) 16 16 15 12 10 7 5 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1) PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh Resolution (bits) 16 16 15 12 10 7 5 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.  2010 Microchip Technology Inc. DS39969B-page 205

PIC24FJ256DA210 FAMILY REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2(2) ENFLT1(2) bit 15 bit 8 R/W-0 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 ENFLT0(2) OCFLT2(2) OCFLT1(2) OCFLT0(2) TRIGMODE OCM2(1) OCM1(1) OCM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare x in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-10 OCTSEL<2:0>: Output Compare x Timer Select bits 111 = Peripheral clock (FCY) 110 = Reserved 101 = Reserved 100 = Timer1 clock (only synchronous clock is supported) 011 = Timer5 clock 010 = Timer4 clock 001 = Timer3 clock 000 = Timer2 clock bit 9 ENFLT2: Fault Input 2 Enable bit(2) 1 = Fault 2 (Comparator 1/2/3 out) is enabled(3) 0 = Fault 2 is disabled bit 8 ENFLT1: Fault Input 1 Enable bit(2) 1 = Fault 1 (OCFB pin) is enabled(4) 0 = Fault 1 is disabled bit 7 ENFLT0: Fault Input 0 Enable bit(2) 1 = Fault 0 (OCFA pin) is enabled(4) 0 = Fault 0 is disabled bit 6 OCFLT2: PWM Fault 2 (Comparator 1/2/3) Condition Status bit(2,3) 1 = PWM Fault 2 has occurred 0 = No PWM Fault 2 has occurred bit 5 OCFLT1: PWM Fault 1 (OCFB pin) Condition Status bit(2,4) 1 = PWM Fault 1 has occurred 0 = No PWM Fault 1 has occurred bit 4 OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit(2,4) 1 = PWM Fault 0 has occurred 0 = No PWM Fault 0 has occurred Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section10.4 “Peripheral Pin Select (PPS)”. 2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. 3: The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6 channels; Comparator 3 output controls the OC7-OC9 channels. 4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section10.4 “Peripheral Pin Select (PPS)”. DS39969B-page 206  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software bit 2-0 OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx(2) 110 = Edge-Aligned PWM Mode on OCx(2) 101 = Double Compare Continuous Pulse mode: Initialize the OCx pin low, the toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initialize the OCx pin low, toggle the OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin 010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces the OCx pin low 001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces the OCx pin high 000 = Output compare channel is disabled Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section10.4 “Peripheral Pin Select (PPS)”. 2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. 3: The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6 channels; Comparator 3 output controls the OC7-OC9 channels. 4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section10.4 “Peripheral Pin Select (PPS)”.  2010 Microchip Technology Inc. DS39969B-page 207

PIC24FJ256DA210 FAMILY REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1(3) DCB0(3) OC32 bit 15 bit 8 R/W-0 R/W-0 HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is cleared in software 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts bit 14 FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault bit 13 FLTTRIEN: Fault Output State Select bit 1 = Pin is forced to an output on a Fault condition 0 = Pin I/O condition is unaffected by a Fault bit 12 OCINV: OCMP Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted bit 11 Unimplemented: Read as ‘0’ bit 10-9 DCB<11:0>: PWM Duty Cycle Least Significant bits(3) 11 = Delay OCx falling edge by ¾ of the instruction cycle 10 = Delay OCx falling edge by ½ of the instruction cycle 01 = Delay OCx falling edge by ¼ of the instruction cycle 00 = OCx falling edge occurs at the start of the instruction cycle bit 8 OC32: Cascade Two OC Modules Enable bit (32-bit operation) 1 = Cascade module operation enabled 0 = Cascade module operation disabled bit 7 OCTRIG: OCx Trigger/Sync Select bit 1 = Trigger OCx from the source designated by the SYNCSELx bits 0 = Synchronize OCx with the source designated by the SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear bit 5 OCTRIS: OCx Output Pin Direction Select bit 1 = OCx pin is tri-stated 0 = Output compare peripheral x is connected to an OCx pin Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. 3: The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110). DS39969B-page 208  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 1000x = Reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2 01011 = Timer1 01010 = Input Capture 5(2) 01001 = Output Compare 9(1) 01000 = Output Compare 8(1) 00111 = Output Compare 7(1) 00110 = Output Compare 6(1) 00101 = Output Compare 5(1) 00100 = Output Compare 4(1) 00011 = Output Compare 3(1) 00010 = Output Compare 2(1) 00001 = Output Compare 1(1) 00000 = Not synchronized to any other module Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. 3: The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110).  2010 Microchip Technology Inc. DS39969B-page 209

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 210  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 15.0 SERIAL PERIPHERAL The module also supports a basic framed SPI protocol INTERFACE (SPI) while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. Note: This data sheet summarizes the features The SPI serial interface consists of four pins: of this group of PIC24F devices. It is not • SDIx: Serial Data Input intended to be a comprehensive reference • SDOx: Serial Data Output source. For more information, refer to the “PIC24F Family Reference Manual”, • SCKx: Shift Clock Input or Output Section 23. “Serial Peripheral Interface • SSx: Active-Low Slave Select or Frame (SPI)” (DS39699). The information in this Synchronization I/O Pulse data sheet supersedes the information in The SPI module can be configured to operate using 2, the FRM. 3 or 4 pins. In the 3-pin mode, SSx is not used. In the The Serial Peripheral Interface (SPI) module is a 2-pin mode, both SDOx and SSx are not used. synchronous serial interface useful for communicating Block diagrams of the module in Standard and with other peripheral or microcontroller devices. These Enhanced modes are shown in Figure15-1 and peripheral devices may be serial EEPROMs, shift Figure15-2. registers, display drivers, A/D Converters, etc. The SPI module is compatible with the SPI and SIOP Motorola® Note: In this section, the SPI modules are referred to together as SPIx or separately interfaces. All devices of the PIC24FJ256DA210 family as SPI1, SPI2 or SPI3. Special Function include three SPI modules. Registers will follow a similar notation. For The module supports operation in two buffer modes. In example, SPIxCON1 and SPIxCON2 refer Standard mode, data is shifted through a single serial to the control registers for any of the 3 SPI buffer. In Enhanced Buffer mode, data is shifted modules. through an 8-level FIFO buffer. Note: Do not perform read-modify-write opera- tions (such as bit-oriented instructions) on the SPIxBUF register in either Standard or Enhanced Buffer mode.  2010 Microchip Technology Inc. DS39969B-page 211

PIC24FJ256DA210 FAMILY To set up the SPI module for the Standard Master mode To set up the SPI module for the Standard Slave mode of operation: of operation: 1. If using interrupts: 1. Clear the SPIxBUF register. a) Clear the SPIxIF bit in the respective IFS 2. If using interrupts: register. a) Clear the SPIxIF bit in the respective IFS b) Set the SPIxIE bit in the respective IEC register. register. b) Set the SPIxIE bit in the respective IEC c) Write the SPIxIP bits in the respective IPC register. register to set the interrupt priority. c) Write the SPIxIP bits in the respective IPC 2. Write the desired settings to the SPIxCON1 register to set the interrupt priority. and SPIxCON2 registers with MSTEN 3. Write the desired settings to the SPIxCON1 (SPIxCON1<5>) = 1. and SPIxCON2 registers with MSTEN 3. Clear the SPIROV bit (SPIxSTAT<6>). (SPIxCON1<5>) = 0. 4. Enable SPI operation by setting the SPIEN bit 4. Clear the SMP bit. (SPIxSTAT<15>). 5. If the CKE bit (SPIxCON1<8>) is set, then the 5. Write the data to be transmitted to the SPIxBUF SSEN bit (SPIxCON1<7>) must be set to enable register. Transmission (and reception) will start the SSx pin. as soon as data is written to the SPIxBUF 6. Clear the SPIROV bit (SPIxSTAT<6>). register. 7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). FIGURE 15-1: SPIx MODULE BLOCK DIAGRAM (STANDARD MODE) SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx/FSYNCx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus DS39969B-page 212  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY To set up the SPI module for the Enhanced Buffer To set up the SPI module for the Enhanced Buffer Master mode of operation: Slave mode of operation: 1. If using interrupts: 1. Clear the SPIxBUF register. a) Clear the SPIxIF bit in the respective IFS 2. If using interrupts: register. a) Clear the SPIxIF bit in the respective IFS b) Set the SPIxIE bit in the respective IEC register. register. b) Set the SPIxIE bit in the respective IEC c) Write the SPIxIP bits in the respective IPC register. register. c) Write the SPIxIP bits in the respective IPC 2. Write the desired settings to the SPIxCON1 register to set the interrupt priority. and SPIxCON2 registers with MSTEN 3. Write the desired settings to the SPIxCON1 (SPIxCON1<5>) = 1. and SPIxCON2 registers with MSTEN 3. Clear the SPIROV bit (SPIxSTAT<6>). (SPIxCON1<5>) = 0. 4. Select Enhanced Buffer mode by setting the 4. Clear the SMP bit. SPIBEN bit (SPIxCON2<0>). 5. If the CKE bit is set, then the SSEN bit must be 5. Enable SPI operation by setting the SPIEN bit set, thus enabling the SSx pin. (SPIxSTAT<15>). 6. Clear the SPIROV bit (SPIxSTAT<6>). 6. Write the data to be transmitted to the SPIxBUF 7. Select Enhanced Buffer mode by setting the register. Transmission (and reception) will start SPIBEN bit (SPIxCON2<0>). as soon as data is written to the SPIxBUF 8. Enable SPI operation by setting the SPIEN bit register. (SPIxSTAT<15>). FIGURE 15-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE) SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx/FSYNCx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer 8-Level FIFO 8-Level FIFO Receive Buffer Transmit Buffer SPIXBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus  2010 Microchip Technology Inc. DS39969B-page 213

PIC24FJ256DA210 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC SPIEN(1) — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0, HSC R/C-0, HS R-0, HSC R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HSC = Hardware Settable/Clearable bit bit 15 SPIEN: SPIx Enable bit(1) 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPI transfers pending. Slave mode: Number of SPI transfers unread. bit 7 SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and ready to send or receive 0 = SPIx Shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded (The user software has not read the previous data in the SPIxBUF register.) 0 = No overflow has occurred bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when the last bit is shifted into SPIxSR; as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot 011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit set) 010 = Interrupt when the SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in the receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT bit set) Note 1: If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section10.4 “Peripheral Pin Select (PPS)” for more information. DS39969B-page 214  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR. In Enhanced Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty In Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from the SPIxSR to the buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 215

PIC24FJ256DA210 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK(1) DISSDO(2) MODE16 SMP CKE(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(4) CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx Pin bit (SPI Master modes only)(1) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx Pin bit(2) 1 = SDOx pin is not used by the module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at the end of data output time 0 = Input data sampled at the middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable (Slave mode) bit(4) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by the module; pin is controlled by the port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for the clock is a high level; active state is a low level 0 = Idle state for the clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 4: If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. DS39969B-page 216  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 4: If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 217

PIC24FJ256DA210 FAMILY REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD SPIFPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPIFE SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled 0 = Framed SPIx support is disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with the first bit clock 0 = Frame sync pulse precedes the first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced buffer is enabled 0 = Enhanced buffer is disabled (Legacy mode) DS39969B-page 218  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) Processor 1 (SPI Master) Processor 2 (SPI Slave) SDOx SDIx Serial Receive Buffer Serial Receive Buffer (SPIxRXB) (SPIxRXB)(2) Shift Register SDIx SDOx Shift Register (SPIxSR) (SPIxSR)(2) MSb LSb MSb LSb Serial Transmit Buffer Serial Transmit Buffer (SPIxTXB) (SPIxTXB)(2) Serial Clock SPIx Buffer SCKx SCKx SPIx Buffer (SPIxBUF)(2) (SPIxBUF)(2) SSx(1) MSTEN (SPIxCON1<5>) = 1) SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 15-4: SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) Processor 1 (SPI Enhanced Buffer Master) Processor 2 (SPI Enhanced Buffer Slave) SDOx SDIx SDIx SDOx Shift Register Shift Register (SPIxSR) (SPIxSR) MSb LSb MSb LSb 8-Level FIFO Buffer 8-Level FIFO Buffer SPIx Buffer Serial Clock SPIx Buffer (SPIxBUF)(2) SCKx SCKx (SPIxBUF)(2) SSx SSx(1) MSTEN (SPIxCON1<5>) = 1 and SSEN (SPIxCON1<7>) = 1, SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 0 and SPIBEN (SPIxCON2<0>) = 1 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF.  2010 Microchip Technology Inc. DS39969B-page 219

PIC24FJ256DA210 FAMILY FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24F Processor 2 (SPI Master, Frame Master) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse FIGURE 15-6: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24F Processor 2 SPI Master, Frame Slave) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F Processor 2 (SPI Slave, Frame Master) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync. Pulse FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F Processor 2 (SPI Slave, Frame Slave) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse DS39969B-page 220  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FCY FSCK = Primary Prescaler x Secondary Prescaler Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 15-1: SAMPLE SCKx FREQUENCIES(1,2) Secondary Prescaler Settings FCY = 16 MHz 1:1 2:1 4:1 6:1 8:1 1:1 Invalid 8000 4000 2667 2000 4:1 4000 2000 1000 667 500 Primary Prescaler Settings 16:1 1000 500 250 167 125 64:1 250 125 63 42 31 FCY = 5 MHz 1:1 5000 2500 1250 833 625 4:1 1250 625 313 208 156 Primary Prescaler Settings 16:1 313 156 78 52 39 64:1 78 39 20 13 10 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: SCKx frequencies shown in kHz.  2010 Microchip Technology Inc. DS39969B-page 221

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 222  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 16.0 INTER-INTEGRATED 16.1 Communicating as a Master in a CIRCUIT™ (I2C™) Single Master Environment The details of sending a message in Master mode Note: This data sheet summarizes the features depends on the communications protocol for the device of this group of PIC24F devices. It is not being communicated with. Typically, the sequence of intended to be a comprehensive reference events is as follows: source. For more information, refer to the “PIC24F Family Reference Manual”, 1. Assert a Start condition on SDAx and SCLx. Section 24. “Inter-Integrated Circuit™ 2. Send the I2C device address byte to the slave (I2C™)” (DS39702). The information in with a write indication. this data sheet supersedes the information 3. Wait for and verify an Acknowledge from the in the FRM. slave. The Inter-Integrated Circuit™ (I2C™) module is a serial 4. Send the first data byte (sometimes known as interface useful for communicating with other periph- the command) to the slave. eral or microcontroller devices. These peripheral 5. Wait for and verify an Acknowledge from the devices may be serial EEPROMs, display drivers, A/D slave. Converters, etc. 6. Send the serial memory address low byte to the The I2C module supports these features: slave. • Independent master and slave logic 7. Repeat steps 4 and 5 until all data bytes are sent. • 7-bit and 10-bit device addresses • General call address, as defined in the I2C protocol 8. Assert a Repeated Start condition on SDAx and SCLx. • Clock stretching to provide delays for the 9. Send the device address byte to the slave with processor to respond to a slave data request a read indication. • Both 100kHz and 400kHz bus specifications 10. Wait for and verify an Acknowledge from the • Configurable address masking slave. • Multi-Master modes to prevent loss of messages 11. Enable master reception to receive serial in arbitration memory data. • Bus Repeater mode, allowing the acceptance of 12. Generate an ACK or NACK condition at the end all messages as a slave regardless of the address of a received byte of data. • Automatic SCL 13. Generate a Stop condition on SDAx and SCLx. A block diagram of the module is shown in Figure16-1.  2010 Microchip Technology Inc. DS39969B-page 223

PIC24FJ256DA210 FAMILY FIGURE 16-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c ogi Read Collision ol L Write Detect ntr o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read ShiftClock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS39969B-page 224  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 16.2 Setting Baud Rate When 16.3 Slave Address Masking Operating as a Bus Master The I2CxMSK register (Register16-3) designates To compute the Baud Rate Generator reload value, use address bit positions as “don’t care” for both 7-Bit and Equation16-1. 10-Bit Addressing modes. Setting a particular bit loca- tion (= 1) in the I2CxMSK register causes the slave EQUATION 16-1: COMPUTING BAUD RATE module to respond whether the corresponding address RELOAD VALUE(1,2) bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both FSCL = FCY addresses, ‘0000000’ and ‘0100000’. FCY I2CxBRG + 1 + To enable address masking, the Intelligent Peripheral 10,000,000 or: Management Interface (IPMI) must be disabled by ( FCY FCY ) clearing the IPMIEN bit (I2CxCON<11>). I2CxBRG = – – 1 FSCL 10,000,000 Note: As a result of changes in the I2C™ proto- Note1: Based on FCY = FOSC/2; Doze mode and col, the addresses in Table16-2 are PLL are disabled. reserved and will not be Acknowledged in Slave mode. This includes any address 2: These clock rate values are for guidance mask settings that include any of these only. The actual clock rate can be affected addresses. by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 16-1: I2C™ CLOCK RATES(1,2) I2CxBRG Value Required System FSCL FCY Actual FSCL (Decimal) (Hexadecimal) 100 kHz 16MHz 157 9D 100kHz 100kHz 8MHz 78 4E 100kHz 100kHz 4MHz 39 27 99kHz 400kHz 16MHz 37 25 404kHz 400kHz 8MHz 18 12 404kHz 400kHz 4MHz 9 9 385kHz 400kHz 2MHz 4 4 385kHz 1MHz 16MHz 13 D 1.026MHz 1MHz 8MHz 6 6 1.026MHz 1MHz 4MHz 3 3 0.909MHz Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 16-2: I2C™ RESERVED ADDRESSES(1) Slave Address R/W Bit Description 0000 000 0 General Call Address(2) 0000 000 1 Start Byte 0000 001 x CBus Address 0000 01x x Reserved 0000 1xx x HS Mode Master Code 1111 0xx x 10-Bit Slave Upper Byte(3) 1111 1xx x Reserved Note 1: The address bits listed here will never cause an address match, independent of address mask settings. 2: The address will be Acknowledged only if GCEN=1. 3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.  2010 Microchip Technology Inc. DS39969B-page 225

PIC24FJ256DA210 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear at the beginning of slave transmission. Hardware is clear at the end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses are Acknowledged 0 = IPMI mode is disabled bit 10 A10M: 10-Bit Slave Addressing bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specifications 0 = Disables the SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching DS39969B-page 226  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master. Applicable during master receive.) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit. Hardware is clear at the end of the master Acknowledge sequence. 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive data byte. 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on the SDAx and SCLx pins. Hardware is clear at the end of the master Stop sequence. 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Repeated Start condition on the SDAx and SCLx pins. Hardware is clear at the end of the master Repeated Start sequence 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at end of the master Start sequence. 0 = Start condition is not in progress  2010 Microchip Technology Inc. DS39969B-page 227

PIC24FJ256DA210 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D/A P S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HSC = Hardware Settable/Clearable bit bit 15 ACKSTAT: Acknowledge Status bit 1 = NACK was detected last 0 = ACK was detected last Hardware is set or clear at the end of Acknowledge. bit 14 TRSTAT: Transmit Status bit (When operating as I2C™ master. Applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at the beginning of master transmission; hardware is clear at the end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware is set at the detection of a bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when the address matches the general call address; hardware is clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at the match of the 2nd byte of the matched 10-bit address; hardware is clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at an occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at the device address match. Hardware is set after a transmission finishes or by reception of a slave byte. DS39969B-page 228  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 2 R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware is set or clear after the reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with the received byte; hardware is clear when the software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN; hardware is clear at the completion of data transmission.  2010 Microchip Technology Inc. DS39969B-page 229

PIC24FJ256DA210 FAMILY REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits 1 = Enable masking for bit x of the incoming message address; bit match is not required in this position 0 = Disable masking for bit x; bit match is required in this position DS39969B-page 230  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 17.0 UNIVERSAL ASYNCHRONOUS • Fully Integrated Baud Rate Generator with 16-Bit RECEIVER TRANSMITTER Prescaler • Baud Rates Ranging from 15 bps to 1Mbps at (UART) 16MIPS Note: This data sheet summarizes the features • 4-Deep, First-In-First-Out (FIFO) Transmit Data of this group of PIC24F devices. It is not Buffer intended to be a comprehensive reference • 4-Deep FIFO Receive Data Buffer source. For more information, refer to the • Parity, Framing and Buffer Overrun Error Detection “PIC24F Family Reference Manual”, • Support for 9-bit mode with Address Detect Section 21. “UART” (DS39708). The (9th bit = 1) information in this data sheet supersedes • Transmit and Receive Interrupts the information in the FRM. • Loopback mode for Diagnostic Support The Universal Asynchronous Receiver Transmitter • Support for Sync and Break Characters (UART) module is one of the serial I/O modules available • Supports Automatic Baud Rate Detection in the PIC24F device family. The UART is a full-duplex, • IrDA® Encoder and Decoder Logic asynchronous system that can communicate with peripheral devices, such as personal computers, • 16x Baud Clock Output for IrDA Support LIN/J2602, RS-232 and RS-485 interfaces. The module A simplified block diagram of the UART is shown in also supports a hardware flow control option with the Figure17-1. The UART module consists of these key UxCTS and UxRTS pins, and also includes an IrDA® important hardware elements: encoder and decoder. • Baud Rate Generator The primary features of the UART module are: • Asynchronous Transmitter • Full-Duplex, 8 or 9-Bit data transmission through • Asynchronous Receiver the UxTX and UxRX pins • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits • Hardware Flow Control option with the UxCTS and UxRTS pins FIGURE 17-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX Note: The UART inputs and outputs must all be assigned to available RPn/RPIn pins before use. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 231

PIC24FJ256DA210 FAMILY 17.1 UART Baud Rate Generator (BRG) The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG=0) and the minimum baud rate The UART module includes a dedicated, 16-bit Baud possible is FCY/(16 * 65536). Rate Generator. The UxBRG register controls the Equation17-2 shows the formula for computation of period of a free-running, 16-bit timer. Equation17-1 the baud rate with BRGH = 1. shows the formula for computation of the baud rate with BRGH=0. EQUATION 17-2: UART BAUD RATE WITH EQUATION 17-1: UART BAUD RATE WITH BRGH = 1(1,2) BRGH = 0(1,2) FCY Baud Rate = FCY 4 • (UxBRG + 1) Baud Rate = 16 • (UxBRG + 1) FCY UxBRG = – 1 FCY 4 • Baud Rate UxBRG = – 1 16 • Baud Rate Note 1: FCY denotes the instruction cycle clock Note 1: FCY denotes the instruction cycle clock frequency. frequency (FOSC/2). 2: Based on FCY = FOSC/2; Doze mode 2: Based on FCY = FOSC/2; Doze mode and PLL are disabled. and PLL are disabled. Example17-1 shows the calculation of the baud rate The maximum baud rate (BRGH = 1) possible is FCY/4 error for the following conditions: (for UxBRG=0) and the minimum baud rate possible is FCY/(4 * 65536). • FCY = 4 MHz Writing a new value to the UxBRG register causes the • Desired Baud Rate = 9600 BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. EXAMPLE 17-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1) Desired Baud Rate = FCY/(16 (BRGx + 1)) Solving for BRGx Value: BRGx = ((FCY/Desired Baud Rate)/16) – 1 BRGx = ((4000000/9600)/16) – 1 BRGx = 25 Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 Note: Based on FCY = FOSC/2; Doze mode and PLL are disabled. DS39969B-page 232  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 17.2 Transmitting in 8-Bit Data Mode 17.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART: a) Write appropriate values for data, parity and 1. Set up the UART (as described in Section17.2 Stop bits. “Transmitting in 8-Bit Data Mode”). b) Write appropriate baud rate value to the 2. Enable the UART. UxBRG register. 3. A receive interrupt will be generated when one c) Set up transmit and receive interrupt enable or more data characters have been received as and priority bits. per interrupt control bit, URXISELx. 2. Enable the UART. 4. Read the OERR bit to determine if an overrun 3. Set the UTXEN bit (causes a transmit interrupt error has occurred. The OERR bit must be reset two cycles after being set). in software. 4. Write a data byte to the lower byte of UxTXREG 5. Read UxRXREG. word. The value will be immediately transferred The act of reading the UxRXREG character will move to the Transmit Shift Register (TSR) and the the next character to the top of the receive FIFO, serial bit stream will start shifting out with the including a new set of PERR and FERR values. next rising edge of the baud clock. 5. Alternately, the data byte may be transferred 17.6 Operation of UxCTS and UxRTS while UTXEN=0 and then the user may set Control Pins UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will UARTx Clear to Send (UxCTS) and Request to Send start from a cleared state. (UxRTS) are the two hardware controlled pins that are 6. A transmit interrupt will be generated as per associated with the UART module. These two pins interrupt control bit, UTXISELx. allow the UART to operate in Simplex and Flow Control mode. They are implemented to control the transmis- 17.3 Transmitting in 9-Bit Data Mode sion and reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the UxMODE 1. Set up the UART (as described in Section17.2 register configure these pins. “Transmitting in 8-Bit Data Mode”). 2. Enable the UART. 17.7 Infrared Support 3. Set the UTXEN bit (causes a transmit interrupt). The UART module provides two types of infrared UART 4. Write UxTXREG as a 16-bit value only. support: one is the IrDA clock output to support an 5. A word write to UxTXREG triggers the transfer external IrDA encoder and decoder device (legacy of the 9-bit data to the TSR. The serial bit stream module support), and the other is the full implementa- will start shifting out with the first rising edge of tion of the IrDA encoder and decoder. Note that the baud clock. because the IrDA modes require a 16x baud clock, they 6. A transmit interrupt will be generated as per the will only work when the BRGH bit (UxMODE<3>) is ‘0’. setting of control bit, UTXISELx. 17.7.1 IrDA CLOCK OUTPUT FOR 17.4 Break and Sync Transmit EXTERNAL IrDA SUPPORT Sequence To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be The following sequence will send a message frame configured to generate the 16x baud clock. With header, made up of a Break, followed by an auto-baud UEN<1:0> = 11, the BCLKx pin will output the 16x Sync byte. baud clock if the UART module is enabled. It can be 1. Configure the UART for the desired mode. used to support the IrDA codec chip. 2. Set UTXEN and UTXBRK to set up the Break 17.7.2 BUILT-IN IrDA ENCODER AND character. DECODER 3. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). The UART has full implementation of the IrDA encoder 4. Write ‘55h’ to UxTXREG; this loads the Sync and decoder as part of the UART module. The built-in character into the transmit FIFO. IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE<12>). When enabled 5. After the Break has been sent, the UTXBRK bit (IREN = 1), the receive pin (UxRX) acts as the input is reset by hardware. The Sync character now from the infrared receiver. The transmit pin (UxTX) acts transmits. as the output to the infrared transmitter.  2010 Microchip Technology Inc. DS39969B-page 233

PIC24FJ256DA210 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by port latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS39969B-page 234  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (4 BRG clock cycles per bit) 0 = Standard-Speed mode (16 BRG clock cycles per bit) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. 2: This feature is only available for the 16x BRG mode (BRGH=0).  2010 Microchip Technology Inc. DS39969B-page 235

PIC24FJ256DA210 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit HC = Hardware Clearable bit bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX is Idle ‘0’ 0 = UxTX is Idle ‘1’ IREN = 1: 1 = UxTX is Idle ‘1’ 0 = UxTX is Idle ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: Transmit Enable bit(2) 1 = Transmit is enabled, UxTX pin controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is controlled by port. bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Note 1: Value of bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN=1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. DS39969B-page 236  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode is enabled If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (10 transition); will reset the receiver buffer and the RSR to the empty state bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN=1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 237

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 238  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 18.0 UNIVERSAL SERIAL BUS WITH The USB OTG module can function as a USB peripheral ON-THE-GO SUPPORT (USB device or as a USB host, and may dynamically switch between Device and Host modes under software OTG) control. In either mode, the same data paths and Buffer Descriptors (BDs) are used for the transmission and Note: This data sheet summarizes the features reception of data. of this group of PIC24F devices. It is not intended to be a comprehensive reference In discussing USB operation, this section will use a source. For more information, refer to the controller-centric nomenclature for describing the direc- “PIC24F Family Reference Manual”, tion of the data transfer between the microcontroller and Section 27. “USB On-The-Go (OTG)” the USB. RX (Receive) will be used to describe transfers (DS39721). The information in this data that move data from the USB to the microcontroller and sheet supersedes the information in the TX (Transmit) will be used to describe transfers that FRM. move data from the microcontroller to the USB. Table18-1 shows the relationship between data PIC24FJ256DA210 family devices contain a full-speed direction in this nomenclature and the USB tokens and low-speed compatible, On-The-Go (OTG) USB exchanged. Serial Interface Engine (SIE). The OTG capability allows the device to act either as a USB peripheral TABLE 18-1: CONTROLLER-CENTRIC device or as a USB embedded host with limited host DATA DIRECTION FOR USB capabilities. The OTG capability allows the device to HOST OR TARGET dynamically switch from device to host operation using OTG’s Host Negotiation Protocol (HNP). Direction USB Mode For more details on OTG operation, refer to the RX TX “On-The-Go Supplement to the USB 2.0 Specification”, published by the USB-IF. For more details on USB oper- Device OUT or SETUP IN ation, refer to the “Universal Serial Bus Specification”, Host IN OUT or SETUP v2.0. This chapter presents the most basic operations The USB OTG module offers these features: needed to implement USB OTG functionality in an • USB functionality in Device and Host modes, and application. A complete and detailed discussion of the OTG capabilities for application-controlled mode USB protocol and its OTG supplement are beyond the switching scope of this data sheet. It is assumed that the user already has a basic understanding of USB architecture • Software-selectable module speeds of full speed and the latest version of the protocol. (12 Mbps) or low speed (1.5 Mbps, available in Host mode only) Not all steps for proper USB operation (such as device • Support for all four USB transfer types: control, enumeration) are presented here. It is recommended interrupt, bulk and isochronous that application developers use an appropriate device driver to implement all of the necessary features. • 16 bidirectional endpoints for a total of 32 unique Microchip provides a number of application-specific endpoints resources, such as USB firmware and driver support. • DMA interface for data RAM access Refer to www.microchip.com/usb for the latest • Queues up to sixteen unique endpoint transfers firmware and driver support. without servicing • Integrated, on-chip USB transceiver with support for off-chip transceivers via a digital interface • Integrated VBUS generation with on-chip comparators and boost generation, and support of external VBUS comparators and regulators through a digital interface • Configurations for on-chip bus pull-up and pull-down resistors A simplified block diagram of the USB OTG module is shown in Figure18-1.  2010 Microchip Technology Inc. DS39969B-page 239

PIC24FJ256DA210 FAMILY FIGURE 18-1: USB OTG MODULE BLOCK DIAGRAM Full-Speed Pull-up 48 MHz USB Clock Host Pull-Down D+(1) Registers Transceiver and Transceiver Power 3.3V Control VUSB Interface D-(1) Host Pull-Down USBID(1) USB SIE VMIO(1) VPIO(1) DMH(1) DPH(1) External Transceiver Interface DMLN(1) DPLN(1) RCV(1) System USBOEN(1) RAM VBUSON(1) SRP Charge USB VBUS(1) Voltage Comparators SRP Discharge VCMPST1/VBUSVLD(1) VCMPST2/SESSVLD(1) SESSEND(1) VBUSST(1) VBUS Boost VCPCON(1) Assist Note 1: Pins are multiplexed with digital I/O and other device features. DS39969B-page 240  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 18.1 Hardware Configuration To meet compliance specifications, the USB module (and the D+ or D- pull-up resistor) should not be enabled 18.1.1 DEVICE MODE until the host actively drives VBUS high. One of the 5.5V tolerant I/O pins may be used for this purpose. 18.1.1.1 D+ Pull-up Resistor The application should never source any current onto PIC24FJ256DA210 family devices have a built-in the 5V VBUS pin of the USB cable. 1.5k resistor on the D+ line that is available when the The Dual Power mode with Self-Power Dominance microcontroller is operating in Device mode. This is (Figure18-5) allows the application to use internal used to signal an external Host that the device is power primarily, but switch to power from the USB operating in Full-Speed Device mode. It is engaged by when no internal power is available. Dual power setting the USBEN bit (U1CON<0>). If the OTGEN bit devices must also meet all of the special requirements (U1OTGCON<2>) is set, then the D+ pull-up is enabled for inrush current and Suspend mode current previ- through the DPPULUP bit (U1OTGCON<7>). ously described, and must not enable the USB module Alternatively, an external resistor may be used on D+, until VBUS is driven high. as shown in Figure18-2. FIGURE 18-3: BUS POWER ONLY FIGURE 18-2: EXTERNAL PULL-UP FOR 100 FULL-SPEED DEVICE Attach Sense VBUS MODE PIC®MCU ContrHoollestr/HUB V~B5UVS 3.3V VDD Low IQ Regulator VUSB VUSB VSS 1.5 k D+ FIGURE 18-4: SELF-POWER ONLY D- 100 Attach Sense VBUS VBUS ~5V 18.1.1.2 Power Modes V~3S.E3LVF VDD Many USB applications will likely have several different sets of power requirements and configuration. The VUSB most common power modes encountered are: 100k VSS • Bus Power Only mode • Self-Power Only mode • Dual Power with Self-Power Dominance Bus Power Only mode (Figure18-3) is effectively the FIGURE 18-5: DUAL POWER EXAMPLE simplest method. All power for the application is drawn from the USB. 100 Attach Sense To meet the inrush current requirements of the USB 2.0 VBUS Specification, the total effective capacitance appearing 3.3V across VBUS and ground must be no more than 10F. VBUS VDD ~5V In the USB Suspend mode, devices must consume no Low IQ more than 2.5 mA from the 5V VBUS line of the USB Regulator VUSB cable. During the USB Suspend mode, the D+ or D- 100k pull-up resistor must remain active, which will consume VSELF VSS some of the allowed suspend current. ~3.3V In Self-Power Only mode (Figure18-4), the USB application provides its own power, with very little power being pulled from the USB. Note that an attach indication is added to indicate when the USB has been connected and the host is actively powering VBUS.  2010 Microchip Technology Inc. DS39969B-page 241

PIC24FJ256DA210 FAMILY 18.1.2 HOST AND OTG MODES the microcontroller is running below VBUS, and is not able to source sufficient current, a separate power 18.1.2.1 D+ and D- Pull-Down Resistors supply must be provided. PIC24FJ256DA210 family devices have a built-in When the application is always operating in Host mode, 15k pull-down resistor on the D+ and D- lines. These a simple circuit can be used to supply VBUS and regu- are used in tandem to signal to the bus that the micro- late current on the bus (Figure18-6). For OTG opera- controller is operating in Host mode. They are engaged tion, it is necessary to be able to turn VBUS on or off as by setting the HOSTEN bit (U1CON<3>). If the OTGEN needed, as the microcontroller switches between bit (U1OTGCON<2>) is set, then these pull-downs are Device and Host modes. A typical example using an enabled by setting the DPPULDWN and DMPULDWN external charge pump is shown in Figure18-7. bits (U1OTGCON<5:4>). 18.1.2.2 Power Configurations In Host mode, as well as Host mode in On-The-Go operation, the USB 2.0 Specification requires that the host application should supply power on VBUS. Since FIGURE 18-6: HOST INTERFACE EXAMPLE +5V +3.3V+3.3V PIC® MCU Thermal Fuse VDD Polymer PTC VUSB 0.1 µF, 2 k 3.3V 150 µF A/D Pin Micro A/B 2 k Connector VBUS VBUS D+ D+ D- D- ID ID GND VSS FIGURE 18-7: OTG INTERFACE EXAMPLE VDD PIC® MCU MCP1253 GND VIN C+ SELECT 10 µF 1 µF C- SHND I/O VOUT PGOOD I/O Micro A/B 4.7 µF 40 k Connector VBUS VBUS D+ D+ D- D- ID ID GND VSS DS39969B-page 242  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 18.1.2.3 VBUS Voltage Generation with 18.1.3 USING AN EXTERNAL INTERFACE External Devices Some applications may require the USB interface to be When operating as a USB host, either as an A-device isolated from the rest of the system. in an OTG configuration or as an embedded host, VBUS PIC24FJ256DA210 family devices include a complete must be supplied to the attached device. interface to communicate with and control an external PIC24FJ256DA210 family devices have an internal USB transceiver, including the control of data line VBUS boost assist to help generate the required 5V pull-ups and pull-downs. The VBUS voltage generation VBUS from the available voltages on the board. This is control circuit can also be configured for different VBUS comprised of a simple PWM output to control a Switch generation topologies. mode power supply, and built-in comparators to Refer to the “PIC24F Family Reference Manual”, monitor output voltage and limit current. Section 27. “USB On-The-Go (OTG)” for information To enable voltage generation: on using the external interface. 1. Verify that the USB module is powered 18.1.4 CALCULATING TRANSCEIVER (U1PWRC<0> = 1) and that the VBUS discharge POWER REQUIREMENTS is disabled (U1OTGCON<0> = 0). 2. Set the PWM period (U1PWMRRS<7:0>) and The USB transceiver consumes a variable amount of duty cycle (U1PWMRRS<15:8>) as required. current depending on the characteristic impedance of the USB cable, the length of the cable, the VUSB supply 3. Select the required polarity of the output signal voltage and the actual data patterns moving across the based on the configuration of the external circuit USB cable. Longer cables have larger capacitances with the PWMPOL bit (U1PWMCON<9>). and consume more total energy when switching output 4. Select the desired target voltage using the states. The total transceiver current consumption will VBUSCHG bit (U1OTGCON<1>). be application-specific. Equation18-1 can help 5. Enable the PWM counter by setting the CNTEN estimate how much current actually may be required in bit to ‘1’ (U1PWMCON<8>). full-speed applications. 6. Enable the PWM module by setting the PWMEN Refer to the “PIC24F Family Reference Manual”, bit (U1PWMCON<15>) to ‘1’. Section 27. “USB On-The-Go (OTG)” for a complete 7. Enable the VBUS generation circuit discussion on transceiver power consumption. (U1OTGCON<3> = 1). Note: This section describes the general process for VBUS voltage generation and control. Please refer to the “PIC24F Family Reference Manual” for additional examples. EQUATION 18-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION 40 mA • VUSB • PZERO • PIN • LCABLE IXCVR = + IPULLUP 3.3V • 5m Legend: VUSB – Voltage applied to the VUSB pin in volts (3.0V to 3.6V). PZERO – Percentage (in decimal) of the IN traffic bits sent by the PIC® microcontroller that are a value of ‘0’. PIN – Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE – Length (in meters) of the USB cable. The USB 2.0 Specification requires that full-speed applications use cables no longer than 5m. IPULLUP – Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB cable.  2010 Microchip Technology Inc. DS39969B-page 243

PIC24FJ256DA210 FAMILY 18.2 USB Buffer Descriptors and Depending on the endpoint buffering configuration the BDT used, there are up to 64 sets of Buffer Descriptors, for a total of 256 bytes. At a minimum, the BDT must be at Endpoint buffer control is handled through a structure least 8 bytes long. This is because the USB Specifica- called the Buffer Descriptor Table (BDT). This provides tion mandates that every device must have Endpoint 0 a flexible method for users to construct and control with both input and output for initial setup. endpoint buffers of various lengths and configurations. Endpoint mapping in the BDT is dependent on three The BDT can be located in any available, 512-byte variables: aligned block of data RAM. The BDT Pointer • Endpoint number (0 to 15) (U1BDTP1) contains the upper address byte of the • Endpoint direction (RX or TX) BDT and sets the location of the BDT in RAM. The user must set this pointer to indicate the table’s location. • Ping-pong settings (U1CNFG1<1:0>) The BDT is composed of Buffer Descriptors (BDs) Figure18-8 illustrates how these variables are used to which are used to define and control the actual buffers map endpoints in the BDT. in the USB RAM space. Each BD consists of two, 16-bit In Host mode, only Endpoint 0 Buffer Descriptors are “soft” (non-fixed-address) registers, BDnSTAT and used. All transfers utilize the Endpoint 0 Buffer Descrip- BDnADR, where n represents one of the 64 possible tor and Endpoint Control register (U1EP0). For received BDs (range of 0 to 63). BDnSTAT is the status register packets, the attached device’s source endpoint is for BDn, while BDnADR specifies the starting address indicated by the value of ENDPT<3:0> in the USB status for the buffer associated with BDn. register (U1STAT<7:4>). For transmitted packet, the attached device’s destination endpoint is indicated by Note: Since BDnADR is a 16-bit register, only the value written to the Token register (U1TOK). the first 64 Kbytes of RAM can be accessed by the USB module. FIGURE 18-8: BDT MAPPING FOR ENDPOINT BUFFERING MODES PPB<1:0>=00 PPB<1:0>=01 PPB<1:0>=10 PPB<1:0>=11 No Ping-Pong Ping-Pong Buffer Ping-Pong Buffers Ping-Pong Buffers Buffers on EP0 OUT on all EPs on all other EPs except EP0 Total BDT Space: Total BDT Space: Total BDT Space: Total BDT Space: 128 Bytes 132 Bytes 256 Bytes 248 Bytes EP0 RX EP0 RX Even EP0 RX Even EP0 RX Descriptor Descriptor Descriptor Descriptor EP0 TX EP0 RX Odd EP0 RX Odd EP0 TX Descriptor Descriptor Descriptor Descriptor EP1 RX EP0 TX Even EP1 RX Even Descriptor EP0 TX Descriptor Descriptor Descriptor EP1 TX EP0 TX Odd EP1 RX Odd Descriptor EP1 RX Descriptor Descriptor Descriptor EP1 RX Even EP1 TX Even EP1 TX Descriptor Descriptor Descriptor EP1 RX Odd EP1 TX Odd EP15 TX Descriptor Descriptor Descriptor EP1 TX Even EP15 TX Descriptor Descriptor EP1 TX Odd Descriptor EP15 TX Odd EP15 TX Odd Descriptor Descriptor Note: Memory area is not shown to scale. DS39969B-page 244  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY BDs have a fixed relationship to a particular endpoint, corresponding data buffer during this time. Note that depending on the buffering configuration. Table18-2 the microcontroller core can still read BDnSTAT while provides the mapping of BDs to endpoints. This rela- the SIE owns the buffer and vice versa. tionship also means that gaps may occur in the BDT if The Buffer Descriptors have a different meaning based endpoints are not enabled contiguously. This, theoreti- on the source of the register update. Register18-1 and cally, means that the BDs for disabled endpoints could Register18-2 show the differences in BDnSTAT be used as buffer space. In practice, users should depending on its current “ownership”. avoid using such spaces in the BDT unless a method of validating BD addresses is implemented. When UOWN is set, the user can no longer depend on the values that were written to the BDs. From this point, 18.2.1 BUFFER OWNERSHIP the USB module updates the BDs as necessary, over- writing the original BD values. The BDnSTAT register is Because the buffers and their BDs are shared between updated by the SIE with the token PID and the transfer the CPU and the USB module, a simple semaphore count is updated. mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory. This 18.2.2 DMA INTERFACE is done by using the UOWN bit as a semaphore to The USB OTG module uses a dedicated DMA to distinguish which is allowed to update the BD and access both the BDT and the endpoint data buffers. associated buffers in memory. UOWN is the only bit Since part of the address space of the DMA is dedi- that is shared between the two configurations of cated to the Buffer Descriptors, a portion of the memory BDnSTAT. connected to the DMA must comprise a contiguous When UOWN is clear, the BD entry is “owned” by the address space properly mapped for the access by the microcontroller core. When the UOWN bit is set, the BD module. entry and the buffer memory are “owned” by the USB peripheral. The core should not modify the BD or its TABLE 18-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERINGMODES BDs Assigned to Endpoint Mode 3 Mode 0 Mode 1 Mode 2 Endpoint (Ping-Pong on all other EPs, (No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs) except EP0) Out In Out In Out In Out In 0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O) 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O) 3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O) 4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O) 5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O) 6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O) 7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O) 8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O) 9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O) 10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O) 11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O) 12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O) 13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O) 14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O) 15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O) Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer  2010 Microchip Technology Inc. DS39969B-page 245

PIC24FJ256DA210 FAMILY REGISTER 18-1: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, USB MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC UOWN DTS PID3 PID2 PID1 PID0 BC9 BC8 bit 15 bit 8 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UOWN: USB Own bit 1 = The USB module owns the BD and its corresponding buffer; the CPU must not modify the BD or the buffer bit 14 DTS: Data Toggle Packet bit 1 = Data 1 packet 0 = Data 0 packet bit 13-10 PID<3:0>: Packet Identifier bits (written by the USB module) In Device mode: Represents the PID of the received token during the last transfer. In Host mode: Represents the last returned PID or the transfer status indicator. bit 9-0 BC<9:0>: Byte Count bits This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. DS39969B-page 246  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY R EGISTER 18-2: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x r-0 r-0 R/W-x R/W-x R/W-x, HSC R/W-x, HSC UOWN DTS(1) Reserved Reserved DTSEN BSTALL BC9 BC8 bit 15 bit 8 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘r’ = Reserved bit x = Bit is unknown bit 15 UOWN: USB Own bit 0 = The microcontroller core owns the BD and its corresponding buffer; the USB module ignores all other fields in the BD bit 14 DTS: Data Toggle Packet bit(1) 1 = Data 1 packet 0 = Data 0 packet bit 13-12 Reserved: Maintain as ‘0’ bit 11 DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect sync value will be ignored 0 = No data toggle synchronization is performed bit 10 BSTALL: Buffer Stall Enable bit 1 = Buffer STALL enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged); corresponding EPSTALL bit will get set on any STALL handshake 0 = Buffer STALL disabled bit 9-0 BC<9:0>: Byte Count bits This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. Note 1: This bit is ignored unless DTSEN=1.  2010 Microchip Technology Inc. DS39969B-page 247

PIC24FJ256DA210 FAMILY 18.3 USB Interrupts level consists of USB error conditions, which are enabled and flagged in the U1EIR and U1EIE registers. The USB OTG module has many conditions that can An interrupt condition in any of these triggers a USB be configured to cause an interrupt. All interrupt Error Interrupt Flag (UERRIF) in the top level. sources use the same interrupt vector. Interrupts may be used to trap routine events in a USB Figure18-9 shows the interrupt logic for the USB transaction. Figure18-10 provides some common module. There are two layers of interrupt registers in events within a USB frame and their corresponding the USB module. The top level consists of overall USB interrupts. status interrupts; these are enabled and flagged in the U1IE and U1IR registers, respectively. The second FIGURE 18-9: USB OTG INTERRUPT FUNNEL Top Level (USB Status) Interrupts STALLIF STALLIE ATTACHIF ATTACHIE RESUMEIF RESUMEIE IDLEIF IDLEIE TRNIF TRNIE Second Level (USB Error) Interrupts SOFIF SOFIE BTSEF BTSEE URSTIF (DETACHIF) Set USB1IF DMAEF URSTIE (DETACHIE) DMAEE BTOEF BTOEE (UERRIF) DFN8EF UERRIE DFN8EE IDIF CRC16EF IDIE CRC16EE T1MSECIF CRC5EF (EOFEF) TIMSECIE CRC5EE (EOFEE) LSTATEIF PIDEF LSTATEIE PIDEE ACTVIF ACTVIE SESVDIF SESVDIE SESENDIF SESENDIE VBUSVDIF VBUSVDIE Top Level (USB OTG) Interrupts DS39969B-page 248  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 18.3.1 CLEARING USB OTG INTERRUPTS software by writing a ‘1’ to their locations (i.e., perform- ing a MOV type instruction). Writing a ‘0’ to a flag bit (i.e., Unlike device level interrupts, the USB OTG interrupt a BCLR instruction) has no effect. status flags are not freely writable in software. All USB OTG flag bits are implemented as hardware set only Note: Throughout this data sheet, a bit that can bits. Additionally, these bits can only be cleared in only be cleared by writing a ‘1’ to its loca- tion is referred to as “Write 1 to clear”. In register descriptions, this function is indicated by the descriptor, “K”. FIGURE 18-10: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS From Host From Host To Host SETUPToken Data ACK Set TRNIF USB Reset URSTIF From Host To Host From Host IN Token Data ACK Set TRNIF Start-Of-Frame (SOF) SOFIF From Host From Host To Host OUT Token Empty Data ACK Set TRNIF Transaction Transaction Complete RESET SOF SETUP DATA STATUS SOF Differential Data Control Transfer(1) 1ms Frame Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. 18.4 Device Mode Operation 5. Enable the USB module by setting the USBEN bit (U1CON<0>). The following section describes how to perform a com- 6. Set the OTGEN bit (U1OTGCON<2>) to enable mon Device mode task. In Device mode, USB transfers OTG operation. are performed at the transfer level. The USB module 7. Enable the endpoint zero buffer to receive the automatically performs the status phase of the transfer. first setup packet by setting the EPRXEN and 18.4.1 ENABLING DEVICE MODE EPHSHK bits for Endpoint 0 (U1EP0<3,0>=1). 8. Power up the USB module by setting the 1. Reset the Ping-Pong Buffer Pointers by setting, USBPWR bit (U1PWRC<0>). then clearing, the Ping-Pong Buffer Reset bit, PPBRST (U1CON<1>). 9. Enable the D+ pull-up resistor to signal an attach by setting DPPULUP bit (U1OTGCON<7>). 2. Disable all interrupts (U1IE and U1EIE = 00h). 3. Clear any existing interrupt flags by writing FFh to U1IR and U1EIR. 4. Verify that VBUS is present (non OTG devices only).  2010 Microchip Technology Inc. DS39969B-page 249

PIC24FJ256DA210 FAMILY 18.4.2 RECEIVING AN IN TOKEN IN 18.5 Host Mode Operation DEVICE MODE The following sections describe how to perform common 1. Attach to a USB host and enumerate as described Host mode tasks. In Host mode, USB transfers are in “Chapter 9 of the USB 2.0 Specification”. invoked explicitly by the host software. The host 2. Create a data buffer and populate it with the data software is responsible for the Acknowledge portion of to send to the host. the transfer. Also, all transfers are performed using the 3. In the appropriate (even or odd) TX BD for the Endpoint 0 Control register (U1EP0) and Buffer desired endpoint: Descriptors. a) Set up the status register (BDnSTAT) with 18.5.1 ENABLE HOST MODE AND the correct data toggle (DATA0/1) value and DISCOVER A CONNECTED DEVICE the byte count of the data buffer. b) Set up the address register (BDnADR) with 1. Enable Host mode by setting the HOSTEN bit the starting address of the data buffer. (U1CON<3>). This causes the Host mode con- trol bits in other USB OTG registers to become c) Set the UOWN bit of the status register to available. ‘1’. 2. Enable the D+ and D- pull-down resistors by set- 4. When the USB module receives an IN token, it ting the DPPULDWN and DMPULDWN bits automatically transmits the data in the buffer. (U1OTGCON<5:4>). Disable the D+ and D- Upon completion, the module updates the status pull-up resistors by clearing the DPPULUP and register (BDnSTAT) and sets the Transfer DMPULUP bits (U1OTGCON<7:6>). Complete Interrupt Flag, TRNIF (U1IR<3>). 3. At this point, SOF generation begins with the 18.4.3 RECEIVING AN OUT TOKEN IN SOF counter loaded with 12,000. Eliminate DEVICE MODE noise on the USB by clearing the SOFEN bit (U1CON<0>) to disable Start-Of-Frame packet 1. Attach to a USB host and enumerate as generation. described in “Chapter 9 of the USB 2.0 4. Enable the device attached interrupt by setting Specification”. the ATTACHIE bit (U1IE<6>). 2. Create a data buffer with the amount of data you 5. Wait for the device attached interrupt are expecting from the host. (U1IR<6> = 1). This is signaled by the USB 3. In the appropriate (even or odd) TX BD for the device changing the state of D+ or D- from ‘0’ desired endpoint: to ‘1’ (SE0 to J state). After it occurs, wait a) Set up the status register (BDnSTAT) with 100ms for the device power to stabilize. the correct data toggle (DATA0/1) value and 6. Check the state of the JSTATE and SE0 bits in the byte count of the data buffer. U1CON. If the JSTATE bit (U1CON<7>) is ‘0’, b) Set up the address register (BDnADR) with the connecting device is low speed. If the con- the starting address of the data buffer. necting device is low speed, set the low c) Set the UOWN bit of the status register to LSPDEN and LSPD bits (U1ADDR<7> and ‘1’. U1EP0<7>) to enable low-speed operation. 4. When the USB module receives an OUT token, 7. Reset the USB device by setting the USBRST it automatically receives the data sent by the bit (U1CON<4>) for at least 50ms, sending host to the buffer. Upon completion, the module Reset signaling on the bus. After 50ms, updates the status register (BDnSTAT) and sets terminate the Reset by clearing USBRST. the Transfer Complete Interrupt Flag, TRNIF 8. In order to keep the connected device from (U1IR<3>). going into suspend, enable the SOF packet generation by setting the SOFEN bit. 9. Wait 10ms for the device to recover from Reset. 10. Perform enumeration as described by “Chapter 9 of the USB 2.0 Specification”. DS39969B-page 250  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 18.5.2 COMPLETE A CONTROL 8. Initialize the current (even or odd) RX or TX (RX TRANSACTION TO A CONNECTED for IN, TX for OUT) EP0 BD to transfer the data. DEVICE a) Write C040h to BD0STAT. This sets the UOWN, configures Data Toggle (DTS) to 1. Follow the procedure described in DATA1 and sets the byte count to the length Section18.5.1 “Enable Host Mode and Dis- of the data buffer (64 or 40h in this case). cover a Connected Device” to discover a device. b) Set BD0ADR to the starting address of the data buffer. 2. Set up the Endpoint Control register for bidirectional control transfers by writing 0Dh to 9. Write the Token register with the appropriate IN U1EP0 (this sets the EPCONDIS, EPTXEN and or OUT token to Endpoint 0, the target device’s EPHSHK bits). default control pipe (e.g., write 90h to U1TOK for an IN token for a GET DEVICE DESCRIPTOR 3. Place a copy of the device framework setup command). This initiates an IN token on the bus command in a memory buffer. See “Chapter 9 of followed by a data packet from the device to the the USB 2.0 Specification” for information on the host. When the data packet completes, the device framework command set. BD0STAT is written and a transfer done interrupt 4. Initialize the Buffer Descriptor (BD) for the is asserted (the TRNIF flag is set). For control current (even or odd) TX EP0 to transfer the transfers with a single packet data phase, this eight bytes of command data for a device completes the data phase of the setup transac- framework command (i.e., GET DEVICE tion as referenced in “Chapter 9 of the USB DESCRIPTOR): Specification”. If more data needs to be a) Set the BD data buffer address (BD0ADR) transferred, return to step 8. to the starting address of the 8-byte 10. To initiate the status phase of the setup transac- memory buffer containing the command. tion, set up a buffer in memory to receive or send b) Write 8008h to BD0STAT (this sets the the zero length status phase data packet. UOWN bit and sets a byte count of 8). 11. Initialize the current (even or odd) TX EP0 BD to 5. Set the USB device address of the target device transfer the status data: in the address register (U1ADDR<6:0>). After a a) Set the BDT buffer address field to the start USB bus Reset, the device USB address will be address of the data buffer. zero. After enumeration, it will be set to another b) Write 8000h to BD0STAT (set UOWN bit, value between 1 and 127. configure DTS to DATA0 and set byte count 6. Write D0h to U1TOK; this is a SETUP token to to 0). Endpoint 0, the target device’s default control 12. Write the Token register with the appropriate IN pipe. This initiates a SETUP token on the bus, or OUT token to Endpoint 0, the target device’s followed by a data packet. The device hand- default control pipe (e.g., write 01h to U1TOK for shake is returned in the PID field of BD0STAT an OUT token for a GET DEVICE DESCRIPTOR after the packets are complete. When the USB command). This initiates an OUT token on the module updates BD0STAT, a transfer done bus followed by a zero length data packet from interrupt is asserted (the TRNIF flag is set). This the host to the device. When the data packet completes the setup phase of the setup transac- completes, the BD is updated with the tion as referenced in “Chapter 9 of the USB handshake from the device and a transfer done Specification”. interrupt is asserted (the TRNIF flag is set). This 7. To initiate the data phase of the setup transac- completes the status phase of the setup trans- tion (i.e., get the data for the GET DEVICE action as described in “Chapter 9 of the USB DESCRIPTOR command), set up a buffer in Specification”. memory to store the received data. Note: Only one control transaction can be performed per frame.  2010 Microchip Technology Inc. DS39969B-page 251

PIC24FJ256DA210 FAMILY 18.5.3 SEND A FULL-SPEED BULK DATA 18.6 OTG Operation TRANSFER TO A TARGET DEVICE 18.6.1 SESSION REQUEST PROTOCOL 1. Follow the procedure described in Section18.5.1 (SRP) “Enable Host Mode and Discover a Connected Device” and Section18.5.2 “Complete a Con- An OTG A-device may decide to power down the VBUS trol Transaction to a Connected Device” to supply when it is not using the USB link through the Ses- discover and configure a device. sion Request Protocol (SRP). Software may do this by 2. To enable transmit and receive transfers with clearing VBUSON (U1OTGCON<3>). When the VBUS handshaking enabled, write 1Dh to U1EP0. If supply is powered down, the A-device is said to have the target device is a low-speed device, also set ended a USB session. the LSPD (U1EP0<7>) bit. If you want the hard- An OTG A-device or embedded host may repower the ware to automatically retry indefinitely if the VBUS supply at any time (initiate a new session). An target device asserts a NAK on the transfer, OTG B-device may also request that the OTG A-device clear the Retry Disable bit, RETRYDIS repower the VBUS supply (initiate a new session). This (U1EP0<6>). is accomplished via Session Request Protocol (SRP). 3. Set up the BD for the current (even or odd) TX Prior to requesting a new session, the B-device must EP0 to transfer up to 64 bytes. first check that the previous session has definitely 4. Set the USB device address of the target device ended. To do this, the B-device must check for two in the address register (U1ADDR<6:0>). conditions: 5. Write an OUT token to the desired endpoint to 1. VBUS supply is below the session valid voltage, and U1TOK. This triggers the module’s transmit 2. Both D+ and D- have been low for at least 2ms. state machines to begin transmitting the token and the data. The B-device will be notified of Condition 1 by the 6. Wait for the Transfer Done Interrupt Flag, SESENDIF (U1OTGIR<2>) interrupt. Software will TRNIF. This indicates that the BD has been have to manually check for Condition 2. released back to the microprocessor and the Note: When the A-device powers down the VBUS transfer has completed. If the retry disable bit is supply, the B-device must disconnect its set, the handshake (ACK, NAK, STALL or pull-up resistor from power. If the device is ERROR (0Fh)) is returned in the BD PID field. If self-powered, it can do this by clearing a STALL interrupt occurs, the pending packet DPPULUP (U1OTGCON<7>) and must be dequeued and the error condition in the DMPULUP (U1OTGCON<6>). target device cleared. If a detach interrupt occurs (SE0 for more than 2.5µs), then the The B-device may aid in achieving Condition 1 by dis- target has detached (U1IR<0> is set). charging the VBUS supply through a resistor. Software may do this by setting VBUSDIS (U1OTGCON<0>). 7. Once the transfer done interrupt occurs (TRNIF is set), the BD can be examined and the next After these initial conditions are met, the B-device may data packet queued by returning to step 2. begin requesting the new session. The B-device begins Note: USB speed, transceiver and pull-ups by pulsing the D+ data line. Software should do this by should only be configured during the mod- setting DPPULUP (U1OTGCON<7>). The data line ule setup phase. It is not recommended to should be held high for 5 to 10ms. change these settings while the module is The B-device then proceeds by pulsing the VBUS enabled. supply. Software should do this by setting PUVBUS (U1CNFG2<4>). When an A-device detects SRP sig- naling (either via the ATTACHIF (U1IR<6>) interrupt or via the SESVDIF (U1OTGIR<3>) interrupt), the A-device must restore the VBUS supply by either setting VBUSON (U1OTGCON<3>) or by setting the I/O port controlling the external power source. The B-device should not monitor the state of the VBUS supply while performing VBUS supply pulsing. When the B-device does detect that the VBUS supply has been restored (via the SESVDIF (U1OTGIR<3>) interrupt), the B-device must reconnect to the USB link by pulling up D+ or D- (via the DPPULUP or DMPULUP). The A-device must complete the SRP by driving USB Reset signaling. DS39969B-page 252  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 18.6.2 HOST NEGOTIATION PROTOCOL When the B-device has finished in its role as host, it (HNP) stops all bus activity and turns on its D+ pull-up resistor by setting DPPULUP. When the A-device detects a In USB OTG applications, a Dual Role Device (DRD) is suspend condition (Idle for 3ms), the A-device turns off a device that is capable of being either a host or a its D+ pull-up. The A-device may also power-down the peripheral. Any OTG DRD must support Host VBUS supply to end the session. When the A-device Negotiation Protocol (HNP). detects the connect condition (via ATTACHIF), the HNP allows an OTG B-device to temporarily become A-device resumes host operation and drives Reset the USB host. The A-device must first enable the signaling. B-device to follow HNP. Refer to the “On-The-Go Supplement to the USB 2.0 Specification” for more 18.6.3 EXTERNAL VBUS COMPARATORS information regarding HNP. HNP may only be initiated The external VBUS comparator option is enabled by set- at full speed. ting the UVCMPDIS bit (U1CNFG2<1>). This disables After being enabled for HNP by the A-device, the the internal VBUS comparators, removing the need to B-device requests being the host any time that the USB attach VBUS to the microcontroller’s VBUS pin. link is in suspend state, by simply indicating a discon- The external comparator interface uses either the nect. This can be done in software by clearing VCMPST1 and VCMPST2 pins, or the VBUSVLD, DPPULUP and DMPULUP. When the A-device detects SESSVLD and SESSEND pins, based upon the setting the disconnect condition (via the URSTIF (U1IR<0>) of the UVCMPSEL bit (U1CNFG2<5>). These pins are interrupt), the A-device may allow the B-device to take digital inputs and should be set in the following patterns over as host. The A-device does this by signaling con- (see Table18-3), based on the current level of the VBUS nect as a full-speed function. Software may accomplish voltage. this by setting DPPULUP. If the A-device responds instead with resume signaling, the A-device remains as host. When the B-device detects the connect condition (via ATTACHIF (U1IR<6>), the B-device becomes host. The B-device drives Reset signaling prior to using the bus. TABLE 18-3: EXTERNAL VBUS COMPARATOR STATES If UVCMPSEL = 0 VCMPST1 VCMPST2 Bus Condition 0 0 VBUS < VB_SESS_END 1 0 VB_SESS_END < VBUS < VA_SESS_VLD 0 1 VA_SESS_VLD < VBUS < VA_VBUS_VLD 1 1 VBUS > VBUS_VLD If UVCMPSEL = 1 VBUSVLD SESSVLD SESSEND Bus Condition 0 0 1 VBUS < VB_SESS_END 0 0 0 VB_SESS_END < VBUS < VA_SESS_VLD 0 1 0 VA_SESS_VLD < VBUS < VA_VBUS_VLD 1 1 0 VBUS > VBUS_VLD  2010 Microchip Technology Inc. DS39969B-page 253

PIC24FJ256DA210 FAMILY 18.7 USB OTG Module Registers With the exception of U1PWMCON and U1PWMRRS, all USB OTG registers are implemented in the Least There are a total of 37 memory mapped registers asso- Significant Byte of the register. Bits in the upper byte ciated with the USB OTG module. They can be divided are unimplemented and have no function. Note that into four general categories: some registers are instantiated only in Host mode, • USB OTG Module Control (12) while other registers have different bit instantiations • USB Interrupt (7) and functions in Device and Host modes. • USB Endpoint Management (16) The registers described in the following sections are • USB VBUS Power Control (2) those that have bits with specific control and configura- tion features. The following registers are used for data This total does not include the (up to) 128 BD registers or address values only: in the BDT. Their prototypes, described in Register18-1 and Register18-2, are shown separately • U1BDTP1: Specifies the 256-word page in data in Section18.2 “USB Buffer Descriptors and the RAM used for the BDT; 8-bit value with bit 0 fixed BDT”. as ‘0’ for boundary alignment. • U1FRML and U1FRMH: Contains the 11-bit byte counter for the current data frame. • U1PWMRRS: Contains the 8-bit value for PWM duty cycle bits<15:8> and PWM period bits<7:0> for the VBUS boost assist PWM module. DS39969B-page 254  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 18.7.1 USB OTG MODULE CONTROL REGISTERS REGISTER 18-3: U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC U-0 R-0, HSC U-0 R-0, HSC R-0, HSC U-0 R-0, HSC ID — LSTATE — SESVD SESEND — VBUSVD bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ID: ID Pin State Indicator bit 1 = No plug is attached, or a type B cable has been plugged into the USB receptacle 0 = A type A plug has been plugged into the USB receptacle bit 6 Unimplemented: Read as ‘0’ bit 5 LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1ms 0 = The USB line state has not been stable for the previous 1ms bit 4 Unimplemented: Read as ‘0’ bit 3 SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device bit 2 SESEND: B Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the B-device 0 = The VBUS voltage is above VB_SESS_END on the B-device bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVD: A VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device  2010 Microchip Technology Inc. DS39969B-page 255

PIC24FJ256DA210 FAMILY R EGISTER 18-4: U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPPULUP DMPULUP DPPULDWN(1) DMPULDWN(1) VBUSON(1) OTGEN(1) VBUSCHG(1) VBUSDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 DPPULUP: D+ Pull-up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled bit 6 DMPULUP: D- Pull-up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled bit 4 DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled bit 3 VBUSON: VBUS Power-on bit(1) 1 = VBUS line is powered 0 = VBUS line is not powered bit 2 OTGEN: OTG Features Enable bit(1) 1 = USB OTG is enabled; all D+/D- pull-up and pull-down bits are enabled 0 = USB OTG is disabled; D+/D- pull-up and pull-down bits are controlled in hardware by the settings of the HOSTEN and USBEN (U1CON<3,0>) bits bit 1 VBUSCHG: VBUS Charge Select bit(1) 1 = VBUS line is set to charge to 3.3V 0 = VBUS line is set to charge to 5V bit 0 VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line is discharged through a resistor 0 = VBUS line is not discharged Note 1: These bits are only used in Host mode; do not use in Device mode. DS39969B-page 256  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 18-5: U1PWRC: USB POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0 U-0 U-0 R/W-0, HC R/W-0 UACTPND — — USLPGRD — — USUSPND USBPWR bit 7 bit 0 Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires the USLPGRD bit to be set) 0 = Module may be suspended or powered down bit 6-5 Unimplemented: Read as ‘0’ bit 4 USLPGRD: Sleep/Suspend Guard bit 1 = Indicate to the USB module that it is about to be suspended or powered down 0 = No suspend bit 3-2 Unimplemented: Read as ‘0’ bit 1 USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a low-power state 0 = Normal USB OTG operation bit 0 USBPWR: USB Operation Enable bit 1 = USB OTG module is enabled 0 = USB OTG module is disabled(1) Note 1: Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON<3,0> and U1OTGCON<2>) are all cleared.  2010 Microchip Technology Inc. DS39969B-page 257

PIC24FJ256DA210 FAMILY REGISTER 18-6: U1STAT: USB STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC U-0 U-0 ENDPT3 ENDPT2 ENDPT1 ENDPT0 DIR PPBI(1) — — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 ENDPT<3:0>: Number of the Last Endpoint Activity bits (Represents the number of the BDT updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 . . . 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last BD Direction Indicator bit 1 = The last transaction was a transmit transfer (TX) 0 = The last transaction was a receive transfer (RX) bit 2 PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the odd BD bank 0 = The last transaction was to the even BD bank bit 1-0 Unimplemented: Read as ‘0’ Note 1: This bit is only valid for endpoints with available even and odd BD registers. DS39969B-page 258  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 18-7: U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R-x, HSC R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — SE0 PKTDIS — HOSTEN RESUME PPBRST USBEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected bit 5 PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing are disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing are enabled bit 4 Unimplemented: Read as ‘0’ bit 3 HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated 0 = Resume signaling is disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the even BD banks 0 = Ping-Pong Buffer Pointers are not reset bit 0 USBEN: USB Module Enable bit 1 = USB module and supporting circuitry are enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry are disabled (device detached)  2010 Microchip Technology Inc. DS39969B-page 259

PIC24FJ256DA210 FAMILY REGISTER 18-8: U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-x, HSC R-x, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 JSTATE: Live Differential Receiver J State Flag bit 1 = J state (differential ‘0’ in low speed, differential ‘1’ in full speed) is detected on the USB 0 = No J state is detected bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected bit 5 TOKBUSY: Token Busy Status bit 1 = Token is being executed by the USB module in On-The-Go state 0 = No token is being executed bit 4 USBRST: Module Reset bit 1 = USB Reset has been generated; for software Reset, application must set this bit for 50ms, then clear it 0 = USB Reset is terminated bit 3 HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated; software must set bit for 10ms and then clear to enable remote wake-up 0 = Resume signaling is disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the even BD banks 0 = Ping-Pong Buffer Pointers are not reset bit 0 SOFEN: Start-Of-Frame Enable bit 1 = Start-Of-Frame token is sent every one 1 ms 0 = Start-Of-Frame token is disabled DS39969B-page 260  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY R EGISTER 18-9: U1ADDR: USB ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN(1) ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB module operates at low speed 0 = USB module operates at full speed bit 6-0 ADDR<6:0>: USB Device Address bits Note 1: Host mode only. In Device mode, this bit is unimplemented and read as ‘0’. REGISTER 18-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID3 PID2 PID1 PID0 EP3 EP2 EP1 EP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 PID<3:0>: Token Type Identifier bits 1101 = SETUP (TX) token type transaction(1) 1001 = IN (RX) token type transaction(1) 0001 = OUT (TX) token type transaction(1) bit 3-0 EP<3:0>: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. Note 1: All other combinations are reserved and are not to be used.  2010 Microchip Technology Inc. DS39969B-page 261

PIC24FJ256DA210 FAMILY R EGISTER 18-11: U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 CNT<7:0>: Start-Of-Frame Size bits Value represents 10 + (packet size of n bytes). For example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet R EGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 UTEYE UOEMON(1) — USBSIDL — — PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled bit 6 UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive bit 5 Unimplemented: Read as ‘0’ bit 4 USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation in Idle mode bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 PPB<1:0>: Ping-Pong Buffers Configuration bits 11 = Even/Odd ping-pong buffers are enabled for Endpoints 1 to 15 10 = Even/Odd ping-pong buffers are enabled for all endpoints 01 = Even/Odd ping-pong buffers are enabled for OUT Endpoint 0 00 = Even/Odd ping-pong buffers are disabled Note 1: This bit is only active when the UTRDIS bit (U1CNFG2<0>) is set. DS39969B-page 262  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 18-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — UVCMPSEL PUVBUS EXTI2CEN UVBUSDIS(1) UVCMPDIS(1) UTRDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 UVCMPSEL: VBUS Comparator External Interface Selection bit 1 = Use VBUSVLD, SESSVLD and SESSEND as comparator interface pins 0 = Use VCMPST1 and VCMPST2 as comparator interface pins bit 4 PUVBUS: VBUS Pull-Up Enable bit 1 = Pull-up on VBUS pin is enabled 0 = Pull-up on VBUS pin is disabled bit 3 EXTI2CEN: I2C™ Interface For External Module Control Enable bit 1 = External module(s) is controlled via the I2C™ interface 0 = External module(s) controlled via the dedicated pins bit 2 UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder is disabled; digital output control interface is enabled 0 = On-chip boost regulator builder is active bit 1 UVCMPDIS: On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator is disabled; digital input status interface is enabled 0 = On-chip charge VBUS comparator is active bit 0 UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver is disabled; digital transceiver interface is enabled 0 = On-chip transceiver is active Note 1: Never change these bits while the USBPWR bit is set (U1PWRC<0> = 1).  2010 Microchip Technology Inc. DS39969B-page 263

PIC24FJ256DA210 FAMILY 18.7.2 USB INTERRUPT REGISTERS REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS U-0 R/K-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state is detected 0 = No ID state change is detected bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1ms, but different from the last time 0 = USB line state has not been stable for 1ms bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS is detected 0 = No activity on the D+/D- lines or VBUS is detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device detected; VBUS has crossed VB_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = VBUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB OTG Specification)(1) 0 = No VBUS change on A-device is detected Note 1: VBUS threshold crossings may be either rising or falling. Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39969B-page 264  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 18-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled  2010 Microchip Technology Inc. DS39969B-page 265

PIC24FJ256DA210 FAMILY REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 Unimplemented: Read as ‘0’ bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state is observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3ms or more) 0 = No Idle condition is detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of the current token is complete; read the U1STAT register for endpoint information 0 = Processing of the current token is not complete; clear the U1STAT register or load the next token from STAT (clearing this bit causes the STAT FIFO to advance) bit 2 SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token is received by the peripheral or the Start-Of-Frame threshold is reached by the host 0 = No Start-Of-Frame token is received or threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred bit 0 URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise oper- ations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39969B-page 266  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; it is set if the bus state is not SE0 and there has been no bus activity for 2.5s 0 = No peripheral attacement has been detected bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state is observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3ms or more) 0 = No Idle condition is detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of the current token is complete; read the U1STAT register for endpoint information 0 = Processing of the current token not complete; clear the U1STAT register or load the next token from U1STAT bit 2 SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred bit 0 DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module; Reset state must be cleared before this bit can be reasserted 0 = No peripheral detachment is detected. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bit- wise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.  2010 Microchip Technology Inc. DS39969B-page 267

PIC24FJ256DA210 FAMILY REGISTER 18-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STALLIE ATTACHIE(1) RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE DETACHIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)(1) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 RESUMEIE: Resume Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 IDLEIE: Idle Detect Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 SOFIE: Start-Of-Frame Token Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 UERRIE: USB Error Condition Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: Unimplemented in Device mode, read as ‘0’. DS39969B-page 268  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 18-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS BTSEF — DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF EOFEF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error has been detected bit 6 Unimplemented: Read as ‘0’ bit 5 DMAEF: DMA Error Flag bit 1 = A USB DMA error condition is detected; the data size indicated by the BD byte count field is less than the number of received bytes, the received data is truncated 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed bit 1 For Device mode: CRC5EF: CRC5 Host Error Flag bit 1 = Token packet is rejected due to CRC5 error 0 = Token packet is accepted (no CRC5 error) For Host mode: EOFEF: End-Of-Frame Error Flag bit 1 = End-Of-Frame error has occurred 0 = End-Of-Frame interrupt is disabled bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.  2010 Microchip Technology Inc. DS39969B-page 269

PIC24FJ256DA210 FAMILY R EGISTER 18-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE — DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE EOFEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 For Device mode: CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled For Host mode: EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DS39969B-page 270  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 18.7.3 USB ENDPOINT MANAGEMENT REGISTERS REGISTER 18-21: U1EPn: USB ENDPOINT n CONTROL REGISTERS (n = 0 TO 15) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD(1) RETRYDIS(1) — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)(1) 1 = Direct connection to a low-speed device is enabled 0 = Direct connection to a low-speed device is disabled bit 6 RETRYDIS: Retry Disable bit (U1EP0 only)(1) 1 = Retry NAK transactions is disabled 0 = Retry NAK transactions is enabled; retry is done in hardware bit 5 Unimplemented: Read as ‘0’ bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN and EPRXEN = 1: 1 = Disable Endpoint n from control transfers; only TX and RX transfers are allowed 0 = Enable Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed For all other combinations of EPTXEN and EPRXEN: This bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake is enabled 0 = Endpoint handshake is disabled (typically used for isochronous endpoints) Note 1: These bits are available only for U1EP0 and only in Host mode. For all other U1EPn registers, these bits are always unimplemented and read as ‘0’.  2010 Microchip Technology Inc. DS39969B-page 271

PIC24FJ256DA210 FAMILY 18.7.4 USB VBUS POWER CONTROL REGISTER REGISTER 18-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 PWMEN — — — — — PWMPOL CNTEN bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in the Reset state specified by PWMPOL bit 14-10 Unimplemented: Read as ‘0’ bit 9 PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low bit 8 CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39969B-page 272  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 19.0 ENHANCED PARALLEL Key features of the EPMP module are: MASTER PORT (EPMP) • Extended Data Space (EDS) interface allows Direct Access from the CPU Note: This data sheet summarizes the features • Up to 23 Programmable Address Lines of this group of PIC24F devices. It is not • Up to 2 Chip Select Lines intended to be a comprehensive reference • Up to 2 Acknowledgement Lines (one per chip source. For more information, refer to the select) “PIC24F Family Reference Manual”, Section 42. “Enhanced Parallel Master • 4-bit, 8-bit or 16-bit wide Data Bus Port (EPMP)” (DS39730). The informa- • Programmable Strobe Options (per chip select) tion in this data sheet supersedes the - Individual Read and Write Strobes or; information in the FRM. - Read/Write Strobe with Enable Strobe The Enhanced Parallel Master Port (EPMP) module is • Programmable Address/Data Multiplexing present in PIC24FJXXXDAX10 devices and not in • Programmable Address Wait States PIC24FJXXXDAX06 devices. The EPMP provides a • Programmable Data Wait States (per chip select) parallel 4-bit (Master mode only), 8-bit (Master and • Programmable Polarity on Control Signals (per Slave modes) or 16-bit (Master mode only) data bus chip select) interface to communicate with off-chip modules, such • Legacy Parallel Slave Port Support as memories, FIFOs, LCD controllers and other micro- controllers. This module can serve as either the master • Enhanced Parallel Slave Support or the slave on the communication bus. For EPMP - Address Support Master modes, all external addresses are mapped into - 4-Byte Deep Auto-Incrementing Buffer the internal Extended Data Space (EDS). This is done • Alternate Master feature by allocating a region of the EDS for each chip select, and then assigning each chip select to a particular 19.1 ALTPMP Setting external resource, such as a memory or external con- troller. This region should not be assigned to another Many of the lower order EPMP address pins are shared device resource, such as RAM or SFRs. To perform a with ADC inputs. This is an untenable situation for write or read on an external resource, the CPU should users that need both the ADC channels and the EPMP simply perform a write or read within the address range bus. If the user does not need to use all the address assigned for EPMP. bits, then by clearing the ALTPMP (CW3<12>) Config- uration bit, the lower order address bits can be mapped Note: The EPMP module is not present in 64-pin to higher address pins, which frees the ADC channels. devices (PIC24FJXXXDAX06). The EPMP has an alternative master feature. The graphics controller module can control the EPMP directly in Alternate Master mode to access an external graphics buffer. TABLE 19-1: ALTERNATE EPMP PINS Pin ALTPMP = 0 ALTPMP = 1 RA14 PMCS2 PMA22 RC4 PMA22 PMCS2 RF12 PMA5 PMA18 RG6 PMA18 PMA5 RG7 PMA20 PMA4 RA3 PMA4 PMA20 RG8 PMA21 PMA3 RA4 PMA3 PMA21  2010 Microchip Technology Inc. DS39969B-page 273

PIC24FJ256DA210 FAMILY TABLE 19-2: PARALLEL MASTER PORT PIN DESCRIPTION Pin Name Type Description PMA<22:16> O Address bus bits<22-16> O Address bus bit<15> O Chip Select 2 (alternate location) PMA<15>, PMCS2 I/O Data bus bit<15> when port size is 16 bits and address is multiplexed O Address bus bit<14> O Chip Select 1 (alternate location) PMA<14>, PMCS1 I/O Data bus bit 14 when port size is 16-bit and address is multiplexed O Address bus bit< 13-8> PMA<13:8> I/O Data bus bits<13-8> when port size is 16 bits and address is multiplexed PMA<7:3> O Address bus bit< 7-3> PMA<2>, PMALU O Address bus bit<2> O Address latch upper strobe for multiplexed address I/O Address bus bit<1> PMA<1>, PMALH O Address latch high strobe for multiplexed address I/O Address bus bit<0> PMA<0>, PMALL O Address latch low strobe for multiplexed address PMD<15:8> I/O Data bus bits<15-8> when address is not multiplexed I/O Data bus bits<7-4> PMD<7:4> O Address bus bits<7-4> when port size is 4 bits and address is multiplexed with 1 address phase PMD<3:0> I/O Data bus bits<3-0> PMCS1 I/O Chip Select 1 PMCS2 O Chip Select 2 PMWR, PMENB I/O Write strobe or Enable signal depending on Strobe mode I/O Read strobe or Read/Write signal depending on Strobe PMRD, PMRD/PMWR mode PMBE1 O Byte indicator PMBE0 O Nibble or byte indicator PMACK1 I Acknowledgment 1 PMACK2 I Acknowledgment 2 DS39969B-page 274  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 19-1: PMCON1: EPMP CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 — MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = EPMP is enabled 0 = EPMP is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower address bits are multiplexed with data bits using 3 address phases 10 = Lower address bits are multiplexed with data bits using 2 address phases 01 = Lower address bits are multiplexed with data bits using 1 address phase 00 = Address and data appear on separate pins bit 10 Unimplemented: Read as ‘0’ bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 10 = Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0> 01 = Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD<7:0> 00 = Legacy Parallel Slave Port; PMRD, PMWR, PMCS and PMD<7:0> pins are used bit 7-6 CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = PMA<15> used for Chip Select 2, PMA<14> used for Chip Select 1 01 = PMA<15> used for Chip Select 2, PMCS1 used for Chip Select 1 00 = PMCS2 used for Chip Select 2, PMCS1 used for Chip Select 1 bit 5 ALP: Address Latch Polarity bit 1 = Active-high (PMALL, PMALH and PMALU) 0 = Active-low (PMALL, PMALH and PMALU) bit 4 ALMODE: Address Latch Strobe Mode bit 1 = Enable “smart” address strobes (each address phase is only present if the current access would cause a different address in the latch than the previous address) 0 = Disable “smart” address strobes bit 3 Unimplemented: Read as ‘0’ bit 2 BUSKEEP: Bus Keeper bit 1 = Data bus keeps its last value when not actively being driven 0 = Data bus is in high-impedance state when not actively being driven bit 1-0 IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt generated at the end of a read/write cycle 00 = No interrupt is generated  2010 Microchip Technology Inc. DS39969B-page 275

PIC24FJ256DA210 FAMILY REGISTER 19-2: PMCON2: EPMP CONTROL REGISTER 2 R-0, HSC U-0 R/C-0, HS R/C-0, HS R-0, HSC R-1, HSC R/W-0 R/W-0 BUSY — ERROR TIMEOUT AMREQ CURMST MSTSEL1 MSTSEL0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16 bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14 Unimplemented: Read as ‘0’ bit 13 ERROR: Error bit 1 = Transaction error (illegal transaction was requested) 0 = Transaction completed successfully bit 12 TIMEOUT: Time-Out bit 1 = Transaction timed out 0 = Transaction completed successfully bit 11 AMREQ: Alternate Master Request bit 1 = The Alternate Master is requesting use of EPMP 0 = The Alternate Master is not requesting use of EPMP bit 10 CURMST: Current Master bit 1 = EPMP access is granted to CPU 0 = EPMP access is granted to alternate master bit 9-8 MSTSEL<1:0>: Parallel Port Master Select bits 11 = Alternate master I/Os direct access (EPMP Bypass mode) 10 = Reserved 01 = Alternate master 00 = CPU bit 7-0 RADDR<23:16>: Parallel Master Port Reserved Address Space bits(1) Note 1: If RADDR<23:16> = 00000000, then the last EDS address for Chip Select 2 will be 0xFFFFFF. DS39969B-page 276  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 19-3: PMCON3: EPMP CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PTWREN PTRDEN PTBE1EN PTBE0EN — AWAITM1 AWAITM0 AWAITE bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PTEN22 PTEN21 PTEN20 PTEN19 PTEN18 PTEN17 PTEN16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTWREN: Write/Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled bit 14 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled bit 13 PTBE1EN: High Nibble/Byte Enable Port Enable bit 1 = PMBE1 port is enabled 0 = PMBE1 port is disabled bit 12 PTBE0EN: Low Nibble/Byte Enable Port Enable bit 1 = PMBE0 port is enabled 0 = PMBE0 port is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-9 AWAITM<1:0>: Address Latch Strobe Wait States bits 11 = Wait of 3½ TCY 10 = Wait of 2½ TCY 01 = Wait of 1½ TCY 00 = Wait of ½ TCY bit bit 8 AWAITE: Address Hold After Address Latch Strobe Wait States bits 1 = Wait of 1¼ TCY 0 = Wait of ¼ TCY bit 7 Unimplemented: Read as ‘0’ bit 6-0 PTEN<22:16>: EPMP Address Port Enable bits 1 = PMA<22:16> function as EPMP address lines 0 = PMA<22:16> function as port I/Os  2010 Microchip Technology Inc. DS39969B-page 277

PIC24FJ256DA210 FAMILY REGISTER 19-4: PMCON4: EPMP CONTROL REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN15: PMA15 Port Enable bit 1 = PMA15 functions as either Address Line 15 or Chip Select 2 0 = PMA15 functions as port I/O bit 14 PTEN14: PMA14 Port Enable bit 1 = PMA14 functions as either Address Line 14 or Chip Select 1 0 = PMA14 functions as port I/O bit 13-3 PTEN<13:3>: EPMP Address Port Enable bits 1 = PMA<13:3> function as EPMP address lines 0 = PMA<13:3> function as port I/Os bit 2-0 PTEN<2:0>: PMALU/PMALH/PMALL Strobe Enable bits 1 = PMA<2:0> function as either address lines or address latch strobes 0 = PMA<2:0> function as port I/Os DS39969B-page 278  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 19-5: PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSDIS CSP CSPTEN BEP — WRSP RDSP SM bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ACKP PTSZ1 PTSZ0 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CSDIS: Chip Select x Disable bit 1 = Disable the Chip Select x functionality 0 = Enable the Chip Select x functionality bit 14 CSP: Chip Select x Polarity bit 1 = Active-high (PMCSx) 0 = Active-low (PMCSx) bit 13 CSPTEN: PMCSx Port Enable bit 1 = PMCSx port is enabled 0 = PMCSx port is disabled bit 12 BEP: Chip Select x Nibble/Byte Enable Polarity bit 1 = Nibble/Byte enable active-high (PMBE0, PMBE1) 0 = Nibble/Byte enable active-low (PMBE0, PMBE1) bit 11 Unimplemented: Read as ‘0’ bit 10 WRSP: Chip Select x Write Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode when SM = 1: 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 9 RDSP: Chip Select x Read Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode when SM = 1: 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/Write strobe active-low (PMRD/PMWR) bit 8 SM: Chip Select x Strobe Mode bit 1 = Read/Write and enable strobes (PMRD/PMWR and PMENB) 0 = Read and write strobes (PMRD and PMWR) bit 7 ACKP: Chip Select x Acknowledge Polarity bit 1 = ACK active-high (PMACK1) 0 = ACK active-low (PMACK1) bit 6-5 PTSZ<1:0>: Chip Select x Port Size bits 11 = Reserved 10 = 16-bit port size (PMD<15:0>) 01 = 4-bit port size (PMD<3:0>) 00 = 8-bit port size (PMD<7:0>) bit 4-0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 279

PIC24FJ256DA210 FAMILY REGISTER 19-6: PMCSxBS: CHIP SELECT x BASE ADDRESS REGISTER R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 bit 15 bit 8 R/W(1) U-0 U-0 U-0 R/W(1) U-0 U-0 U-0 BASE15 — — — BASE11 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 BASE<23:15>: Chip Select x Base Address bits(2) bit 6-4 Unimplemented: Read as ‘0’ bit 3 BASE<11>: Chip Select x Base Address bits(2) bit 2-0 Unimplemented: Read as ‘0’ Note 1: Value at POR is 0x0200 for PMCS1BS and 0x0600 for PMCS2BS. 2: If the whole PMCS2BS register is written together as 0x0000, then the last EDS address for the Chip Select 1 will be 0xFFFFFF. In this case, the Chip Select 2 should not be used. PMCS1BS has no such feature. DS39969B-page 280  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 19-7: PMCSxMD: CHIP SELECT x MODE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 ACKM<1:0>: Chip Select x Acknowledge Mode bits 11 = Reserved 10 = PMACKx is used to determine when a read/write operation is complete 01 = PMACKx is used to determine when a read/write operation is complete with time-out If DWAITM<3:0> = 0000, the maximum time-out is 255 TCY, else it is DWAITM<3:0> cycles. 00 = PMACKx is not used bit 13-11 AMWAIT<2:0>: Chip Select x Alternate Master Wait States bits 111 = Wait of 10 alternate master cycles . . . 001 = Wait of 4 alternate master cycles 000 = Wait of 3 alternate master cycles bit 10-8 Unimplemented: Read as ‘0’ bit 7-6 DWAITB<1:0>: Chip Select x Data Setup Before Read/Write Strobe Wait States bits 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY bit 5-2 DWAITM<3:0>: Chip Select x Data Read/Write Strobe Wait States bits For Write operations: 1111 = Wait of 15½ TCY . . . 0001 = Wait of 1½ TCY 0000 = Wait of ½ TCY For Read operations: 1111 = Wait of 15¾ TCY . . . 0001 = Wait of 1¾ TCY 0000 = Wait of ¾ TCY bit 1-0 DWAITE<1:0>: Chip Select x Data Hold After Read/Write Strobe Wait States bits For Write operations: 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY For Read operations: 11 = Wait of 3 TCY 10 = Wait of 2 TCY 01 = Wait of 1 TCY 00 = Wait of 0 TCY  2010 Microchip Technology Inc. DS39969B-page 281

PIC24FJ256DA210 FAMILY REGISTER 19-8: PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY) R-0, HSC R/W-0 HS U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1, HSC R/W-0 HS U-0 U-0 R-1, HSC R-1, HSC R-1, HSC R-1, HSC OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IBxF: Input Buffer x Status Full bit(1) 1 = Input buffer contains unread data (reading buffer will clear this bit) 0 = Input buffer does not contain unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OBxE: Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains untransmitted data Note 1: Even though an individual bit represents the byte in the buffer, the bits corresponding to the Word (byte 0 and 1, or byte 2 and 3) gets cleared even on byte reading. DS39969B-page 282  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 19-9: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: EPMP Module TTL Input Buffer Select bit(2) 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit must also be set. 2: Unimplemented in 64-pin devices (PIC24FJXXXDAX06); maintain as ‘0’.  2010 Microchip Technology Inc. DS39969B-page 283

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 284  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 20.0 REAL-TIME CLOCK AND • Visibility of half of one second period CALENDAR (RTCC) • Provides calendar – weekday, date, month and year Note: This data sheet summarizes the features • Alarm configurable for half a second, one of this group of PIC24F devices. It is not second,10 seconds, one minute, 10 minutes, one intended to be a comprehensive reference hour, one day, one week, one month or one year source. For more information, refer to the • Alarm repeat with decrementing counter “PIC24F Family Reference Manual”, • Alarm with indefinite repeat chime Section 29. “Real-Time Clock and • Year, 2000 to 2099, leap year correction Calendar (RTCC)” (DS39696). The information in this data sheet • BCD format for smaller software overhead supersedes the information in the FRM. • Optimized for long-term battery operation • User calibration of the 32.768 kHz clock The Real-Time Clock and Calendar (RTCC) provides a crystal/32K INTRC frequency with periodic function that can be calibrated. auto-adjust Key features of the RTCC module are: - Calibration to within ±2.64 seconds error per • Operates in Sleep mode month • Provides hours, minutes and seconds using - Calibrates up to 260 ppm of crystal error 24-hour format FIGURE 20-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain 32.768 kHz Input RCFGCAL from SOSC RTCC Prescalers ALCFGRPT YEAR 0.5s MTHDY RTCC Timer RTCVAL WKDYHR Alarm Event MINSEC Comparator ALMTHDY Compare Registers ALRMVAL ALWDHR with Masks ALMINSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE  2010 Microchip Technology Inc. DS39969B-page 285

PIC24FJ256DA210 FAMILY 20.1 RTCC Module Registers TABLE 20-2: ALRMVAL REGISTER MAPPING The RTCC module registers are organized into three categories: ALRMPTR Alarm Value Register Window • RTCC Control Registers <1:0> ALRMVAL<15:8> ALRMVAL<7:0> • RTCC Value Registers 00 ALRMMIN ALRMSEC • Alarm Value Registers 01 ALRMWD ALRMHR 20.1.1 REGISTER MAPPING 10 ALRMMNTH ALRMDAY To limit the register interface, the RTCC Timer and 11 — — Alarm Time registers are accessed through the corre- Considering that the 16-bit core does not distinguish sponding register pointers. The RTCC Value register between 8-bit and 16-bit read operations, the user must window (RTCVALH and RTCVALL) uses the RTCPTR be aware that when reading either the ALRMVALH or bits (RCFGCAL<9:8>) to select the desired Timer ALRMVALL bytes, they will decrement the register pair (see Table20-1). ALRMPTR<1:0> value. The same applies to the By writing the RTCVALH byte, the RTCC Pointer value, RTCVALH or RTCVALL bytes with the RTCPTR<1:0> RTCPTR<1:0> bits, decrement by one until they reach being decremented. ‘00’. Once they reach ‘00’, the MINUTES and Note: This only applies to read operations and SECONDS value will be accessible through RTCVALH not write operations. and RTCVALL until the pointer value is manually changed. 20.1.2 WRITE LOCK TABLE 20-1: RTCVAL REGISTER MAPPING In order to perform a write to any of the RTCC Timer registers, the RTCWREN (RCFGCAL<13>) bit must be RTCC Value Register Window RTCPTR set (refer to Example20-1). <1:0> RTCVAL<15:8> RTCVAL<7:0> Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit 00 MINUTES SECONDS (RCFGCAL<13>) is kept clear at any 01 WEEKDAY HOURS other time. For the RTCWREN bit to be 10 MONTH DAY set, there is only 1 instruction cycle time window allowed between the unlock 11 — YEAR sequence and the setting of RTCWREN; The Alarm Value register window (ALRMVALH and therefore, it is recommended that code ALRMVALL) uses the ALRMPTR bits follow the procedure in Example20-1. (ALCFGRPT<9:8>) to select the desired Alarm register For applications written in C, the unlock pair (see Table20-2). sequence should be implemented using By writing the ALRMVALH byte, the Alarm Pointer in-line assembly. value bits, ALRMPTR<1:0>, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. EXAMPLE 20-1: SETTING THE RTCWREN BIT asm volatile("disi #5"); asm volatile("mov #0x55, w7"); asm volatile("mov w7, _NVMKEY"); asm volatile("mov #0xAA, w8"); asm volatile("mov w8, _NVMKEY"); asm volatile("bset _RCFGCAL, #13"); //set the RTCWREN bit DS39969B-page 286  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 20.1.3 RTCC CONTROL REGISTERS REGISTER 20-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0, HSC R/W-0, HSC RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL<15:8>: 11 =Reserved 10 =MONTH 01 =WEEKDAY 00 =MINUTES RTCVAL<7:0>: 11 = YEAR 10 = DAY 01 = HOURS 00 = SECONDS Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.  2010 Microchip Technology Inc. DS39969B-page 287

PIC24FJ256DA210 FAMILY REGISTER 20-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment . . . 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. REGISTER 20-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: EPMP Module TTL Input Buffer Select bit 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit must also be set. DS39969B-page 288  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 20-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HSC R/W-0, HSC ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0>=00h and CHIME=0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits 11xx = Reserved – do not use 101x = Reserved – do not use 1001 = Once a year (except when configured for February 29th, once every 4 years) 1000 = Once a month 0111 = Once a week 0110 = Once a day 0101 = Every hour 0100 = Every 10 minutes 0011 = Every minute 0010 = Every 10 seconds 0001 = Every second 0000 = Every half second bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL<15:8>: 11 = Unimplemented 10 = ALRMMNTH 01 = ALRMWD 00 = ALRMMIN ALRMVAL<7:0>: 11 = Unimplemented 10 = ALRMDAY 01 = ALRMHR 00 = ALRMSEC bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME=1.  2010 Microchip Technology Inc. DS39969B-page 289

PIC24FJ256DA210 FAMILY 20.1.4 RTCVAL REGISTER MAPPINGS REGISTER 20-4: YEAR: YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to the YEAR register is only allowed when RTCWREN=1. REGISTER 20-5: MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS39969B-page 290  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 20-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 20-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. DS39969B-page 291

PIC24FJ256DA210 FAMILY 20.1.5 ALRMVAL REGISTER MAPPINGS REGISTER 20-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS39969B-page 292  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 20-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 20-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. DS39969B-page 293

PIC24FJ256DA210 FAMILY 20.2 Calibration 20.3 Alarm The real-time crystal input can be calibrated using the • Configurable from half second to one year periodic auto-adjust feature. When properly calibrated, • Enabled using the ALRMEN bit the RTCC can provide an error of less than 3 seconds (ALCFGRPT<15>, Register20-3) per month. This is accomplished by finding the number • One-time alarm and repeat alarm options of error clock pulses for one minute and storing the available value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of 20.3.1 CONFIGURING THE ALARM RCFGCAL is multiplied by four and will either be added The alarm feature is enabled using the ALRMEN bit. or subtracted from the RTCC timer, once every minute. This bit is cleared when an alarm is issued. Writes to Refer to the following steps for RTCC calibration: ALRMVAL should only take place when ALRMEN=0. 1. Using another timer resource on the device, the As shown in Figure20-2, the interval selection of the user must find the error of the 32.768kHz alarm is configured through the AMASK bits crystal. (ALCFGRPT<13:10>). These bits determine which and 2. Once the error is known, it must be converted to how many digits of the alarm must match the clock the number of error clock pulses per minute and value for the alarm to occur. loaded into the RCFGCAL register. The alarm can also be configured to repeat based on a EQUATION 20-1: RTCC CALIBRATION preconfigured interval. The amount of times this occurs, once the alarm is enabled, is stored in the Error (clocks per minute) = (Ideal Frequency† – ARPT bits, ARPT<7:0> (ALCFGRPT<7:0>). When the Measured Frequency) x 60 value of the ARPT bits equals 00h and the CHIME bit †Ideal Frequency = 32,768H (ALCFGRPT<14>) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading 3. a) If the oscillator is faster then ideal (negative ARPT<7:0> with FFh. result form Step 2), the RCFGCAL register value needs to be negative. This causes the specified After each alarm is issued, the value of the ARPT bits number of clock pulses to be subtracted from is decremented by one. Once the value has reached the timer counter, once every minute. 00h, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the b) If the oscillator is slower then ideal (positive alarm will turn off. result from Step 2), the RCFGCAL register value needs to be positive. This causes the specified Indefinite repetition of the alarm can occur if the CHIME number of clock pulses to be added to the timer bit = 1. Instead of the alarm being disabled when the counter, once every minute. value of the ARPT bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set. 4. Divide the number of error clocks per minute by 4 to get the correct CAL value and load the 20.3.2 ALARM INTERRUPT RCFGCAL register with the correct value. At every alarm event, an interrupt is generated. In addi- (Each 1-bit increment in CAL adds or subtracts tion, an alarm pulse output is provided that operates at 4 pulses). half the frequency of the alarm. This output is Writes to the lower half of the RCFGCAL register completely synchronous to the RTCC clock and can be should only occur when the timer is turned off or used as a trigger clock to other peripherals. immediately after the rising edge of the seconds pulse. Note: Changing any of the registers, other then Note: It is up to the user to include in the error the RCFGCAL and ALCFGRPT registers value the initial error of the crystal, drift and the CHIME bit while the alarm is due to temperature and drift due to crystal enabled (ALRMEN = 1), can result in a aging. false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. DS39969B-page 294  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY FIGURE 20-2: ALARM MASK SETTINGS Day of Alarm Mask Setting the (AMASK<3:0>) Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s 0100 – Every 10 minutes m s s 0101 – Every hour m m s s 0110 – Every day h h m m s s 0111 – Every week d h h m m s s 1000 – Every month d d h h m m s s 1001 – Every year(1) m m d d h h m m s s Note 1: Annually, except when configured for February 29.  2010 Microchip Technology Inc. DS39969B-page 295

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 296  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 21.0 32-BIT PROGRAMMABLE The 32-bit programmable CRC generator provides a CYCLIC REDUNDANCY CHECK hardware implemented method of quickly generating checksums for various networking and security (CRC) GENERATOR applications. It offers the following features: Note: This data sheet summarizes the features • User-programmable CRC polynomial equation, of this group of PIC24F devices. It is not up to 32 bits intended to be a comprehensive reference • Programmable shift direction (little or big-endian) source. For more information, refer to the • Independent data and polynomial lengths “PIC24F Family Reference Manual”, • Configurable interrupt output Section 41. “32-Bit Programmable • Data FIFO Cyclic Redundancy Check (CRC)” (DS39729). The information in this data Figure21-1 displays a simplified block diagram of the sheet supersedes the information in the CRC generator. A simple version of the CRC shift FRM. engine is displayed in Figure21-2. FIGURE 21-1: CRC BLOCK DIAGRAM CRCDATH CRCDATL Variable FIFO FIFO Empty (4x32, 8x16 or 16x8) Event CRCISEL CRCWDATH CRCWDATL 1 CRC LENDIAN 0 Interrupt Shift Buffer 1 CRC Shift Engine 0 Shift Complete Event Shifter Clock 2 * FCY FIGURE 21-2: CRC SHIFT ENGINE DETAIL CRC Shift Engine CRCWDATH CRCWDATL Read/Write Bus X0 X1 Xn(1) Shift Buffer Data Bit 0 Bit 1 Bit n(1) Note 1: n = PLEN<4:1> + 1.  2010 Microchip Technology Inc. DS39969B-page 297

PIC24FJ256DA210 FAMILY 21.1 User Interface 21.1.2 DATA INTERFACE The module incorporates a FIFO that works with a vari- 21.1.1 POLYNOMIAL INTERFACE able data width. Input data width can be configured to The CRC module can be programmed for CRC any value between one and 32 bits using the polynomials of up of up the 32nd order, using up to 32 bits. DWIDTH<4:0> bits (CRCCON2<12:8>). When the data width is greater than 15, the FIFO is four words Polynomial length, which reflects the highest exponent deep. When the DWITDH bits are between 15 and 8, in the equation, is selected by the PLEN<4:0> bits the FIFO is 8 words deep. When the DWIDTH bits are (CRCCON2<4:0>). less than 8, the FIFO is 16 words deep. The CRCXORL and CRCXORH registers control which The data for which the CRC is to be calculated must exponent terms are included in the equation. Setting a first be written into the FIFO. Even if the data width is particular bit includes that exponent term in the equa- less than 8, the smallest data element that can be writ- tion; functionally, this includes an XOR operation on the ten into the FIFO is one byte. For example, if DWIDTH corresponding bit in the CRC engine. Clearing the bit is five, then the size of the data is DWIDTH + 1 or six. disables the XOR. The data is written as a whole byte; the two unused For example, consider two CRC polynomials, one a upper bits are ignored by the module. 16-bit and the other a 32-bit equation. Once data is written into the MSb of the CRCDAT reg- isters (that is, MSb as defined by the data width), the EQUATION 21-1: 16-BIT, 32-BIT CRC value of the VWORD<4:0> bits (CRCCON1<12:8>) POLYNOMIALS increments by one. For example, if DWIDTH is 24, the VWORD bits will increment when bit 7 of CRCDATH is X16 + X12 + X5 + 1 written. Therefore, CRCDATL must always be written and to before CRCDATH. The CRC engine starts shifting data when the CRCGO X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 bit is set and the value of VWORD is greater than zero. Each word is copied out of the FIFO into a buffer regis- ter, which decrements VWORD. The data is then To program these polynomial into the CRC generator, shifted out of the buffer. The CRC engine continues set the register bits as shown in Table21-1. shifting at a rate of two bits per instruction cycle, until VWORD reaches zero. This means that for a given Note that the appropriate positions are set to ‘1’ to indi- data width, it takes half that number of instructions for cate they are used in the equation (for example, X26 each word to complete the calculation. For example, it and X23). The ‘0’ bit required by the equation is always takes 16 cycles to calculate the CRC for a single word XORed; thus, X0 is a don’t care. For a polynomial of length 32, it is assumed that the 32nd bit will be used. of 32-bit data. Therefore, the X<31:1> bits do not have the 32nd bit. When VWORD reaches the maximum value for the configured value of DWIDTH (4, 8 or 16), the CRCFUL bit becomes set. When VWORD reaches zero, the CRCMPT bit becomes set. The FIFO is emptied and the VWORD<4:0> bits are set to ‘00000’ whenever CRCEN is ‘0’. At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. TABLE 21-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS Bit Values CRC Control Bits 16-Bit Polynomial 32-Bit Polynomial PLEN<4:0> 01111 11111 X<31:16> 0000 0000 0000 0001 0000 0100 1100 0001 X<15:0> 0001 0000 0010 000X 0001 1101 1011 011x DS39969B-page 298  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 21.1.3 DATA SHIFT DIRECTION 3. Preload the FIFO by writing to the CRCDATL and CRCDATH registers until the CRCFUL bit is The LENDIAN bit (CRCCON1<3>) is used to control set or no data is left. the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) 4. Clear old results by writing 00h to CRCWDATL causes the CRC to shift data, LSb first. This setting and CRCWDATH. The CRCWDAT registers can allows better integration with various communication also be left unchanged to resume a previously schemes and removes the overhead of reversing the halted calculation. bit order in software. Note that this only changes the 5. Set the CRCGO bit to start calculation. direction the data is shifted into the engine. The result 6. Write remaining data into the FIFO as space of the CRC calculation will still be a normal CRC result, becomes available. not a reverse CRC result. 7. When the calculation completes, CRCGO is automatically cleared. An interrupt will be 21.1.4 INTERRUPT OPERATION generated if CRCISEL = 1. The module generates an interrupt that is configurable 8. Read CRCWDATL and CRCWDATH for the by the user for either of two conditions. result of the calculation. If CRCISEL is ‘0’, an interrupt is generated when the There are eight registers used to control programmable VWORD<4:0> bits make a transition from a value of ‘1’ CRC operation: to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated • CRCCON1 after the CRC operation finishes and the module sets the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ • CRCCON2 will not generate an interrupt. Note that when an • CRCXORL interrupt occurs, the CRC calculation would not yet be • CRCXORH complete. The module will still need (PLEN + 1)/2 clock • CRCDATL cycles after the interrupt is generated until the CRC • CRCDATH calculation is finished. • CRCWDATL 21.1.5 TYPICAL OPERATION • CRCWDATH To use the module for a typical CRC calculation: The CRCCON1 and CRCCON2 registers (Register21-1 and Register21-2) control the operation 1. Set the CRCEN bit to enable the module. of the module and configure the various settings. 2. Configure the module for desired operation: a) Program the desired polynomial using the The CRCXOR registers (Register21-3 and CRCXORL and CRCXORH registers, and the Register21-4) select the polynomial terms to be used PLEN<4:0> bits. in the CRC equation. The CRCDAT and CRCWDAT b) Configure the data width and shift direction registers are each register pairs that serve as buffers using the DWIDTH and LENDIAN bits. for the double-word input data, and CRC processed c) Select the desired interrupt mode using the output, respectively. CRCISEL bit.  2010 Microchip Technology Inc. DS39969B-page 299

PIC24FJ256DA210 FAMILY REGISTER 21-1: CRCCON1: CRC CONTROL 1 REGISTER R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0, HSC R-1, HSC R/W-0 R/W-0, HC R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HC = Hardware Cleared HSC = Hardware Settable/Clearable bit bit 15 CRCEN: CRC Enable bit 1 = Enables module 0 = Disables module; all state machines, pointers and CRCWDAT/CRCDATH reset; other SFRs are NOT reset bit 14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<4:0>  7 or 16 when PLEN<4:0> 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; the final word of data is still shifting through the CRC 0 = Interrupt on shift is complete and results are ready bit 4 CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter is turned off bit 3 LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the CRC, starting with the LSb (little endian) 0 = Data word is shifted into the CRC, starting with the MSb (big endian) bit 2-0 Unimplemented: Read as ‘0’ DS39969B-page 300  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 21-2: CRCCON2: CRC CONTROL 2 REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH<4:0>: Data Word Width Configuration bits Configures the width of the data word (data word width – 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN<4:0>: Polynomial Length Configuration bits Configures the length of the polynomial (polynomial length – 1). REGISTER 21-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X15 X14 X13 X12 X11 X10 X9 X8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X7 X6 X5 X4 X3 X2 X1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X<15:1>: XOR of Polynomial Term xn Enable bits bit 0 Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 301

PIC24FJ256DA210 FAMILY REGISTER 21-4: CRCXORH: CRC XOR HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X31 X30 X29 X28 X27 X26 X25 X24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X23 X22 X21 X20 X19 X18 X17 X16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 X<31:16>: XOR of Polynomial Term xn Enable bits REGISTER 21-5: CRCDATL: CRC DATA LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DATA<15:0>: CRC Input Data bits Writing to this register fills the FIFO; reading from this register returns ‘0’. REGISTER 21-6: CRCDATH: CRC DATA HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DATA<15:0>: CRC Input Data bits Writing to this register fills the FIFO; reading from this register returns ‘0’. DS39969B-page 302  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 21-7: CRCWDATL: CRC SHIFT LOW REGISTER R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA15 SDATA14 SDATA13 SDATA12 SDATA11 SDATA10 SDATA9 SDATA8 bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA7 SDATA6 SDATA5 SDATA4 SDATA3 SDATA2 SDATA1 SDATA0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SDATA<15:0>: CRC Shift Register bits Writing to this register writes to the CRC Shift register through the CRC write bus. Reading from this register reads the CRC read bus. REGISTER 21-8: CRCWDATH: CRC SHIFT HIGH REGISTER R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA31 SDATA30 SDATA29 SDATA28 SDATA27 SDATA26 SDATA25 SDATA24 bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA23 SDATA22 SDATA21 SDATA20 SDATA19 SDATA18 SDATA17 SDATA16 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SDATA<31:16>: CRC Input Data bits Writing to this register writes to the CRC Shift register through the CRC write bus. Reading from this register reads the CRC read bus.  2010 Microchip Technology Inc. DS39969B-page 303

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 304  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 22.0 GRAPHICS CONTROLLER Key features of the GFX module include: MODULE (GFX) • Direct interface to three categories of display glasses: Note: This data sheet summarizes the features - Monochrome STN of this group of PIC24F devices. It is not - Color STN intended to be a comprehensive reference - Color TFT source. For more information, refer to the “PIC24F Family Reference Manual”, • Programmable vertical and horizontal synchroni- Section 43. “Graphics Controller Mod- zation signals’ timing and display clock frequency ule (GFX)” (DS39731). The information in to meet display’s frame rates this data sheet supersedes the information • Optional internal or external display buffer to in the FRM. accommodate different types of display resolution • Graphic hardware accelerators: The Graphics Controller (GFX) module is specifically designed to directly interface with the display glasses, - Character Graphics Processing Unit with a built-in analog drive, to individually control pixels (CHRGPU) in the screen. The module also provides an accelerated - Rectangle Copy Graphics Processing Unit rendering of vertical and horizontal lines, rectangles, (RCCGPU) copying of rectangular area between different locations - Inflate Processing Unit (IPU) on the screen, drawing texts and decompressing • 256 Entries Color Look-up Table (CLUT) packed data. The use of the accelerated rendering is • Supports 1/2/4/8/16 bits-per-pixel (bpp) color depth performed using command registers. Once initiated, • Programmable display resolution the hardware will perform the rendering, and the software can either poll the status, or use the interrupts • Supports multiple display interfaces: to continue rendering of the succeeding shapes. - 4/8/16-bit Monochrome STN - 4/8/16-bit Color STN - 9/12/18/24-bit color TFT (18 and 24-bit displays are connected as 16-bit 5-6-5 RGB color format) FIGURE 22-1: GRAPHICS MODULE OVERVIEW PIC24F Graphics Controller Module Display Interface Display Module Clock (DISPCLK) Interface System Clock Registers GD<15:0> and Control Interface HSYNC Graphics Controller Clock GPU Command (G1CLK) Interface VSYNC play ss s a Di Gl o GEN T RCCGPU CHRGPU IPU GPWR CLUT Memory Request Arbiter GCLK System RAM  2010 Microchip Technology Inc. DS39969B-page 305

PIC24FJ256DA210 FAMILY 22.1 GFX Module Registers REGISTER 22-1: G1CMDL: GPU COMMAND LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCMD15 GCMD14 GCMD13 GCMD12 GCMD11 GCMD10 GCMD9 GCMD8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCMD7 GCMD6 GCMD5 GCMD4 GCMD3 GCMD2 GCMD1 GCMD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 GCMD<15:0>: Low GPU Command bits The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). Writes to this register will not trigger the loading of GCMD <31:0> to the command FIFO. For command FIFO loading, see the G1CMDH register description. REGISTER 22-2: G1CMDH: GPU COMMAND HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCMD31 GCMD30 GCMD29 GCMD28 GCMD27 GCMD26 GCMD25 GCMD24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCMD23 GCMD22 GCMD21 GCMD20 GCMD19 GCMD18 GCMD17 GCMD16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 GCMD<31:16>: High GPU Command bits The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). A word write to the G1CMDH register triggers the loading of GCMD<31:0> to the command FIFO. Byte writes to the G1CMDH are allowed but only a high byte write will trigger the command loading to the FIFO. Low byte write to this register will only update the G1CMDH<7:0> bits. DS39969B-page 306  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-3: G1CON1: DISPLAY CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G1EN — G1SIDL GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC PUBPP2 PUBPP1 PUBPP0 GCMDCNT4 GCMDCNT3 GCMDCNT2 GCMDCNT1 GCMDCNT0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 G1EN: Module Enable bit 1 = Display module is enabled 0 = Display module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 G1SIDL: Stop in Idle bit 1 = Display module stops in Idle mode 0 = Display module does not stop in Idle mode bit 12-8 GCMDWMK<4:0>: Command FIFO Watermark bits Sets the command watermark level that triggers the CMDLVIF interrupt and sets the CMDLV flag; GCMDWMK<4:0> (10000 = Reserved) 10000 = If the number of commands present in the FIFO goes from 16 to 15 commands, the CMDLVIF interrupt will trigger and the CMDLV flag will be set 01111 = f the number of commands present in the FIFO goes from 15 to 14 commands, CMDLVIF interrupt will trigger and CMDLV flag will be set . . . 00001 = If the number of commands present in the FIFO goes from 1 to 0 commands, the CMDLVIF interrupt will trigger and the CMDLV flag will be set 00000 = CMDLVIF interrupt will not trigger and the CMDLV flag will not be set bit 7-5 PUBPP<2:0>: GPU bits-per-pixel (bpp) Setting bits Other = Reserved 100 = 16 bits-per-pixel 011 = 8 bits-per-pixel 010 = 4 bits-per-pixel 001 = 2 bits-per -pixel 000 = 1-bit -per-pixel bit 4-0 GCMDCNT<4:0>: Command FIFO Occupancy Status bits When the FIFO is full, any additional commands written to the FIFO are discarded. 10000 = 16 commands are present in the FIFO 01111 = 15 commands are present in the FIFO . . . 0001 = 1 command is present in the FIFO 0000 = 0 command is present in the FIFO  2010 Microchip Technology Inc. DS39969B-page 307

PIC24FJ256DA210 FAMILY REGISTER 22-4: G1CON2: DISPLAY CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 DPGWDTH1 DPGWDTH0 DPSTGER1 DPSTGER0 — — DPTEST1 DPTEST0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 DPBPP2 DPBPP1 DPBPP0 — — DPMODE2 DPMODE1 DPMODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 DPGWDTH<1:0>: STN Display Glass Data Width bits 11 = Reserved 10 = 16 bits wide 01 = 8 bits wide 00 = 4 bits wide These bits have no effect on TFT mode. TFT display glass data width is always assumed to be 16 bits wide. bit 13-12 DPSTGER<1:0>: Display Data Timing Stagger bits 11 = Delays of the display data are staggered in groups: Bit group 0: 0 4 8 12 – not delayed Bit group 1: 1 5 9 13 – delayed by ½ GPUCLK cycle Bit group 2: 2 6 10 14 – delayed by full GPUCLK cycle Bit group 3: 3 7 11 15 – delayed by 1 ½ GPUCLK cycle 10 = Even bits of the display data are delayed by 1 full GPUCLK cycle; odd bits are not delayed 01 = Odd bits of the display data are delayed by ½ GPUCLK cycle; even bits are not delayed 00 = Display data timing is all synchronized on one clock GPUCLK edge bit 11-10 Unimplemented: Read as ‘0’ bit 9-8 DPTEST<1:0>: Display Test Pattern Generator bits 11 = Borders 10 = Bars 01 = Black screen 00 = Normal Display mode; test patterns are off bit 7-5 DPBPP<2:0>: Display bits-per-pixel Setting bits This setting must match the GPU bits-per-pixel set in PUBPP<2:0> (G1CON1<7:5>). 100 = 16 bits-per-pixel 011 = 8 bits-per-pixel 010 = 4 bits-per-pixel 001 = 2 bits-per-pixel 000 = 1 bit-per-pixel Other = Reserved bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 DPMODE<2:0>: Display Glass Type bits 011 = Color STN type 010 = Mono STN type 001 = TFT type 000 = Display off Other = Reserved DS39969B-page 308  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-5: G1CON3: DISPLAY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — DPPINOE DPPOWER bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPCLKPOL DPENPOL DPVSPOL DPHSPOL DPPWROE DPENOE DPVSOE DPHSOE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 DPPINOE: Display Pin Output Pad Enable bit DPPINOE is the master output enable and must be set to allow GDBEN<15:0>, DPENOE, DPPWROE, DPVSOE and DPHSOE to enable the associated pads 1 = Enable display output pads 0 = Disable display output signals as set by GDBEN<15:0> Pins used by the signals are assigned to the next enabled module that uses the same pins. For data signals, GDBEN<15:0> can be used to disable or enable specific data signals while DPPINOE is set. bit 8 DPPOWER: Display Power-up Power-Down Sequencer Control bit Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)” for details. 1 = Set Display Power Sequencer Control port (GPWR) to ‘1’ 0 = Set Power Control Sequencer signal (GPWR) ‘0’ bit 7 DPCLKPOL: Display Glass Clock (GCLK) Polarity bit 1 = Display latches data on the positive edge of GCLK 0 = Display latches data on the negative edge of GCLK bit 6 DPENPOL: Display Enable Signal (GEN) Polarity bit For TFT mode (DPMODE (G1CON2<2:0>) = 001): 1 = Active-high (GEN) 0 = Active-low (GEN) For STN mode (DPMODE (G1CON2<2:0>) = 010 or 011): 1 = GEN connects to the shift clock input of the display (Shift Clock mode) 0 = GEN connects to the MOD input of the display (Line/Frame Toggle mode) bit 5 DPVSPOL: Display Vertical Synchronization (VSYNC) Polarity bit 1 = Active-high (VSYNC) 0 = Active-low (VSYNC) bit 4 DPHSPOL: Display Horizontal Synchronization (HSYNC) Polarity bit 1 = Active-high (HSYNC) 0 = Active-low (HSYNC) bit 3 DPPWROE: Display Power-up/Power-Down Sequencer Control port (GPWR) enable bit 1 = GPWR port is enabled (pin controlled by the DPPOWER bit (G1CON3<8>)) 0 = GPWR port is disabled (pin can be used as an ordinary I/O) bit 2 DPENOE: Display Enable Port Enable bit 1 = GEN port is enabled 0 = GEN port is disabled  2010 Microchip Technology Inc. DS39969B-page 309

PIC24FJ256DA210 FAMILY REGISTER 22-5: G1CON3: DISPLAY CONTROL REGISTER 3 (CONTINUED) bit 1 DPVSOE: Display Vertical Synchronization Port Enable bit 1 = VSYNC port is enabled 0 = VSYNC port is disabled bit 0 DPHSOE: Display Horizontal Synchronization Port Enable bit 1 = HSYNC port is enabled 0 = HSYNC port is disabled REGISTER 22-6: G1STAT: GFX STATUS REGISTER R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 U-0 PUBUSY — — — — — — — bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC IPUBUSY RCCBUSY CHRBUSY VMRGN HMRGN CMDLV CMDFUL CMDMPT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PUBUSY: Processing Units are Busy Status bit This bit is logically equivalent to the ORed combination of IPUBUSY, RCCBUSY or CHRBUSY. 1 = At least one processing unit is busy 0 = None of the processing units are busy bit 14-8 Unimplemented: Read as ‘0’ bit 7 IPUBUSY: Inflate Processing Unit Busy Status bit 1 = IPU is busy 0 = IPU is not busy bit 6 RCCBUSY: Rectangle Copy Graphics Processing Unit Busy Status bit 1 = RCCGPU is busy 0 = RCCGPU is not busy bit 5 CHRBUSY: Character Graphics Processing Unit Busy Status bit 1 = CHRGPU is busy 0 = CHRGPU is not busy bit 4 VMRGN: Vertical Blanking Status bit 1 = Display interface is in the vertical blanking period 0 = Display interface is not in the vertical blanking period bit 3 HMRGN: Horizontal Blanking Status bit 1 = Display interface is in the horizontal blanking period 0 = Display interface is not in the horizontal blanking period bit 2 CMDLV: Command Watermark Level Status bit The number of commands in the command FIFO changed from equal (=) to the command watermark value to less than (<) the Command Watermark value set in CMDWMK (G1CON1<12:8>) register bits. 1 = Command in FIFO is less than the set CMDWMK value 0 = Command in FIFO is equal to or greater than the set CMDWMK value bit 1 CMDFUL: Command FIFO Full Status bit 1 = Command FIFO is full 0 = Command FIFO is not full bit 0 CMDMPT: Command FIFO Empty Status bit 1 = Command FIFO is empty 0 = Command FIFO is not empty DS39969B-page 310  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-7: G1IE: GFX INTERRUPT ENABLE REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 PUIE — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPUIE RCCIE CHRIE VMRGNIE HMRGNIE CMDLVIE CMDFULIE CMDMPTIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PUIE: Processing Units Complete Interrupt Enable bit 1 = Enables the PU complete interrupt 0 = Disables the PU complete interrupt bit 14-8 Unimplemented: Read as ‘0’ bit 7 IPUIE: Inflate Processing Unit Complete Interrupt Enable bit 1 = Enables the IPU complete interrupt 0 = Disables the IPU complete interrupt bit 6 RCCIE: Rectangle Copy Graphics Processing Unit Complete Interrupt bit 1 = Enables the RCCGPU complete interrupt 0 = Disables the RCCGPU complete interrupt bit 5 CHRIE: Character Graphics Processing Unit Busy Interrupt bit 1 = Enables the CHRGPU busy interrupt 0 = Disables the CHRGPU busy interrupt bit 4 VMRGNIE: Vertical Blanking Interrupt Enable bit 1 = Enables the vertical blanking period interrupt 0 = Disables the vertical blanking period interrupt bit 3 HMRGNIE: Horizontal Blanking Interrupt Enable bit 1 = Enables the horizontal blanking period interrupt 0 = Disables the horizontal blanking period interrupt bit 2 CMDLVIE: Command Watermark Interrupt Enable bit 1 = Enables the command watermark interrupt bit 0 = Disables the command watermark interrupt bit bit 1 CMDFULIE: Command FIFO Full Interrupt Enable bit 1 = Enables the command FIFO full interrupt 0 = Disables the command FIFO full interrupt bit 0 CMDMPTIE: Command FIFO Empty Interrupt Enable bit 1 = Enables the command FIFO empty interrupt 0 = Disables the command FIFO empty interrupt  2010 Microchip Technology Inc. DS39969B-page 311

PIC24FJ256DA210 FAMILY REGISTER 22-8: G1IR: GFX INTERRUPT STATUS REGISTER R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0 U-0 PUIF — — — — — — — bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS IPUIF(1) RCCIF(1) CHRIF(1) VMRGNIF HMRGNIF CMDLVIF CMDFULIF CMDMPTIF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PUIF: Processing Units Complete Interrupt Flag bit PUIF is an ORed combination of IPUIF, RCCIF and CHRIF. 1 = One or more PUs completed command execution (must be cleared in software) 0 = All PUs are Idle or busy completing command execution bit 14-8 Unimplemented: Read as ‘0’ bit 7 IPUIF: Inflate Processing Unit Complete Interrupt Flag bit(1) 1 = IPU completed command execution (must be cleared in software) 0 = IPU is Idle or busy completing command execution bit 6 RCCIF: Rectangle Copy Graphics Processing Unit Complete Interrupt Flag bit(1) 1 = RCCGPU completed command execution (must be cleared in software) 0 = RCCGPU is Idle or busy completing command execution bit 5 CHRIF: Character Graphics Processing Unit Complete Interrupt Flag bit(1) 1 = CHRGPU completed command execution (must be cleared in software) 0 = CHRGPU is Idle or busy completing command execution bit 4 VMRGNIF: Vertical Blanking Interrupt Flag bit 1 = Display interface is in the vertical blanking period (must be cleared in software) 0 = Display interface is not in the vertical blanking period bit 3 HMRGNIF: Horizontal Blanking Interrupt Flag bit 1 = Display interface is in the horizontal blanking period (must be cleared in software) 0 = Display interface is not in the horizontal blanking period bit 2 CMDLVIF: Command Watermark Interrupt Flag bit 1 = Command watermark level is reached (must be cleared in software) 0 = Command watermark level is not yet reached bit 1 CMDFULIF: Command FIFO Full Interrupt Flag bit 1 = Command FIFO is full (must be cleared in software) 0 = Command FIFO is not full bit 0 CMDMPTIF: Command FIFO Empty Interrupt Flag bit 1 = Command FIFO is empty (must be cleared in software) 0 = Command FIFO is not empty Note 1: The logic of each Processing Unit Status bit is the reverse of the PUIF. This provides flexibility on software code utilizing the processing units. DS39969B-page 312  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-9: G1W1ADRL: GPU WORK AREA 1 START ADDRESS REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W1ADR15 W1ADR14 W1ADR13 W1ADR12 W1ADR11 W1ADR10 W1ADR9 W1ADR8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W1ADR7 W1ADR6 W1ADR5 W1ADR4 W1ADR3 W1ADR2 W1ADR1 W1ADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 W1ADR<15:0>: GPU Work Area 1 Start Address Low bits Work area address must point to an even byte address in memory. REGISTER 22-10: G1W1ADRH: GPU WORK AREA 1 START ADDRESS REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W1ADR23 W1ADR22 W1ADR21 W1ADR20 W1ADR19 W1ADR18 W1ADR17 W1ADR16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 W1ADR<23:16>: GPU Work Area 1 Start Address High bits Work area address must point to an even byte address in memory. REGISTER 22-11: G1W2ADRL: GPU WORK AREA 2 START ADDRESS REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W2ADR15 W2ADR14 W2ADR13 W2ADR12 W2ADR11 W2ADR10 W2ADR9 W2ADR8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W2ADR7 W2ADR6 W2ADR5 W2ADR4 W2ADR3 W2ADR2 W2ADR1 W2ADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 W2ADR<15:0>: GPU Work Area 2 Start Address Low bits Work area address must point to an even byte address in memory.  2010 Microchip Technology Inc. DS39969B-page 313

PIC24FJ256DA210 FAMILY REGISTER 22-12: G1W2ADRH: GPU WORK AREA 2 START ADDRESS REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W2ADR23 W2ADR22 W2ADR21 W2ADR20 W2ADR19 W2ADR18 W2ADR17 W2ADR16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 W2ADR<23:16>: GPU Work Area 2 Start Address High bits Work area address must point to an even byte address in memory. REGISTER 22-13: G1PUW: GPU WORK AREA WIDTH REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PUW10 PUW9 PUW8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PUW7 PUW6 PUW5 PUW4 PUW3 PUW2 PUW1 PUW0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 PUW<10:0>: GPU Work Area Width bits (in pixels) REGISTER 22-14: G1PUH: GPU WORK AREA HEIGHT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PUH10 PUH9 PUH8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PUH7 PUH6 PUH5 PUH4 PUH3 PUH2 PUH1 PUH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 PUH<10:0>: GPU Work Area Height bits (in pixels) DS39969B-page 314  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-15: G1DPADRL: DISPLAY BUFFER START ADDRESS REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPADR15 DPADR14 DPADR13 DPADR12 DPADR11 DPADR10 DPADR9 DPADR8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPADR7 DPADR6 DPADR5 DPADR4 DPADR3 DPADR2 DPADR1 DPADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DPADR<15:0>: Display Buffer Start Address Low bits Display buffer start address must point to an even byte address in memory. REGISTER 22-16: G1DPADRH: DISPLAY BUFFER START ADDRESS REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPADR23 DPADR22 DPADR21 DPADR20 DPADR19 DPADR18 DPADR17 DPADR16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 DPADR<23:16>: Display Buffer Start Address High bits Display buffer start address must point to an even byte address in memory. REGISTER 22-17: G1DPW: DISPLAY BUFFER WIDTH REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DPW10 DPW9 DPW8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPW7 DPW6 DPW5 DPW4 DPW3 DPW2 DPW1 DPW0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 DPW<10:0>: Display Frame Width bits (in pixels)  2010 Microchip Technology Inc. DS39969B-page 315

PIC24FJ256DA210 FAMILY REGISTER 22-18: G1DPH: DISPLAY BUFFER HEIGHT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DPH10 DPH9 DPH8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 DPH<10:0>: Display Frame Height bits (in pixels) REGISTER 22-19: G1DPWT: DISPLAY TOTAL WIDTH REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DPWT10 DPWT9 DPWT8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPWT7 DPWT6 DPWT5 DPWT4 DPWT3 DPWT2 DPWT1 DPWT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 DPWT<10:0>: Display Total Width bits (in pixels) REGISTER 22-20: G1DPHT: DISPLAY TOTAL HEIGHT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DPHT10 DPHT9 DPHT8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPHT7 DPHT6 DPHT5 DPHT4 DPHT3 DPHT2 DPHT1 DPHT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 DPHT<10:0>: Display Total Height bits (in pixels) DS39969B-page 316  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-21: G1ACTDA: ACTIVE DISPLAY AREA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACTLINE7 ACTLINE6 ACTLINE5 ACTLINE4 ACTLINE3 ACTLINE2 ACTLINE1 ACTLINE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACTPIX7 ACTPIX6 ACTPIX5 ACTPIX4 ACTPIX3 ACTPIX2 ACTPIX1 ACTPIX0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 ACTLINE<7:0>: Number of Lines Before the First Active (Displayed) Line bits Typically, ACTLINEx = VENSTx (G1DBLCON<15:8>). This register is added for versatility in the timing of the active lines. For TFT mode, DPMODE bits (G1CON2<2:0>) = 001; the minimum value is 2. For STN mode, DPMODE bits (G1CON2<2:0>) = 010,011,100; the minimum value is 0. bit 7-0 ACTPIX<7:0>: Number of Pixels Before the First Active (Displayed) Pixel bits (in DISPCLKs) Typically, ACTPIXx = HENSTx (G1DBLCON<7:0>). This register is added for versatility in the timing of the active pixels. Note that the programmed value is computed in DISPCLK cycles. This value is dependent on the DPGWDTH bit (G1CON2<15:14>). Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)” for details. REGISTER 22-22: G1HSYNC: HORIZONTAL SYNCHRONIZATION CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSLEN7 HSLEN6 HSLEN5 HSLEN4 HSLEN3 HSLEN2 HSLEN1 HSLEN0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSST7 HSST6 HSST5 HSST4 HSST3 HSST2 HSST1 HSST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 HSLEN<7:0>: HSYNC Pulse-Width Configuration bits (in DISPCLKs) DPHSOE bit (G1CON3<0>) must be set for the HSYNC signal to toggle; minimum value is 1. bit 7-0 HSST<7:0>: HSYNC Start Delay Configuration bits (in DISPCLKs) This is the number of DISPCLK cycles from the start of horizontal blanking to the start of HSYNC active.  2010 Microchip Technology Inc. DS39969B-page 317

PIC24FJ256DA210 FAMILY REGISTER 22-23: G1VSYNC: VERTICAL SYNCHRONIZATION CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VSLEN7 VSLEN6 VSLEN5 VSLEN4 VSLEN3 VSLEN2 VSLEN1 VSLEN0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VSST7 VSST6 VSST5 VSST4 VSST3 VSST2 VSST1 VSST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 VSLEN<7:0>: VSYNC Pulse-Width Configuration bits (in lines) The DPVSOE bit (G1CON3<1>) must be set for the VSYNC signal to toggle; minimum value is 1. bit 7-0 VSST<7:0>: VSYNC Start Delay Configuration bits (in lines) This is the number of lines from the start of vertical blanking to the start of VSYNC active. REGISTER 22-24: G1DBLCON: DISPLAY BLANKING CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VENST7 VENST6 VENST5 VENST4 VENST3 VENST2 VENST1 VENST0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HENST7 HENST6 HENST5 HENST4 HENST3 HENST2 HENST1 HENST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 VENST<7:0>: Vertical Blanking Start to First Displayed Line Configuration bits (in lines) This is the number of lines from the start of vertical blanking to the first displayed line of a frame. bit 7-0 HENST<7:0>: Horizontal Blanking Start to First Displayed Pixel Configuration bits (in DISPCLKs) This is the number of GCLK cycles from the start of horizontal blanking to the first displayed pixel of each displayed line. DS39969B-page 318  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-25: G1CLUT: COLOR LOOK-UP TABLE CONTROL REGISTER R/W-0 R-0, HSC U-0 U-0 U-0 U-0 R/W-0 R/W-0 CLUTEN CLUTBUSY — — — — CLUTTRD CLUTRWEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLUTADR7 CLUTADR6 CLUTADR5 CLUTADR4 CLUTADR3 CLUTADR2 CLUTADR1 CLUTADR0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CLUTEN: Color Look-up Table Enable Control bit 1 = Color look-up table is enabled 0 = Color look-up table is disabled bit 14 CLUTBUSY: Color Look-up Table Busy Status bit 1 = A CLUT entry read/write access is being executed 0 = No CLUT entry read/write access is being executed bit 13-10 Unimplemented: Read as ‘0’ bit 9 CLUTTRD: Color Look-up Table Read Trigger bit Enabling this bit will trigger a read to the CLUT location determined by the CLUTADR bits (G1CLUT<7:0>) with CLUTRWEN enabled. 1 = CLUT read trigger is enabled (must be cleared in software after reading data in the G1CLUTRD register) 0 = CLUT read trigger is disabled bit 8 CLUTRWEN: Color Look-up Table Read/Write Enable Control bit This bit must be set when reading or modifying entries on the CLUT and it must also be cleared when CLUT is used by the display controller. 1 = Color look-up table read/write enabled; display controller cannot access the CLUT 0 = Color look-up table read/write disabled; display controller can access the CLUT bit 7-0 CLUTADR<7:0>: Color Look-up Table Memory Address bits  2010 Microchip Technology Inc. DS39969B-page 319

PIC24FJ256DA210 FAMILY REGISTER 22-26: G1CLUTWR: COLOR LOOK-UP TABLE (CLUT) MEMORY WRITE DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLUTWR15 CLUTWR14 CLUTWR13 CLUTWR12 CLUTWR11 CLUTWR10 CLUTWR9 CLUTWR8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLUTWR7 CLUTWR6 CLUTWR5 CLUTWR4 CLUTWR3 CLUTWR2 CLUTWR1 CLUTWR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CLUTWR<15:0>: Color Look-up Table Memory Write Data bits A write to this register triggers a write to the CLUT memory at the address pointed to by the CLUTADR bits. A word write or a high byte write to this register triggers a write to the CLUT memory at the address pointed to by CLUTADR. Low byte write to this register will only update the G1CLUTWR<7:0> and no write to CLUT memory will be triggered. During power-up and power-down of the display, the most recent data written to this register will be used to control the timing of the GPWR signal. Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)” for details on writing entries to the CLUT. REGISTER 22-27: G1CLUTRD: COLOR LOOK-UP TABLE (CLUT) MEMORY READ DATA REGISTER R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CLUTRD15 CLUTRD14 CLUTRD13 CLUTRD12 CLUTRD11 CLUTRD10 CLUTRD9 CLUTRD8 bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CLUTRD7 CLUTRD6 CLUTRD5 CLUTRD4 CLUTRD3 CLUTRD2 CLUTRD1 CLUTRD0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CLUTRD<15:0>: Color Look-up Table Memory Read Data bits This register contains the most recent read from the CLUT memory pointed to by the CLUTADR bits (G1CLUT<7:0>). Reading of the CLUT memory is triggered when the CLUTTRD bit (G1CLUT<9>) goes from ‘0’ to ‘1’. Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)” for details on reading entries from the CLUT. DS39969B-page 320  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-28: G1MRGN: INTERRUPT ADVANCE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VBAMGN7 VBAMGN6 VBAMGN5 VBAMGN4 VBAMGN3 VBAMGN2 VBAMGN1 VBAMGN0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HBAMGN7 HBAMGN6 HBAMGN5 HBAMGN4 HBAMGN3 HBAMGN2 HBAMGN1 HBAMGN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 VBAMGN<7:0>: Vertical Blanking Advance bits The number of DISPCLK cycles in advance that the vertical blanking interrupt will assert ahead of the actual start of the vertical blanking. bit 7-0 HBAMGN<7:0>: Horizontal Blanking Advance bits The number of DISPCLK cycles in advance that the horizontal blanking interrupt will assert ahead of the actual start of the horizontal blanking. REGISTER 22-29: G1CHRX: CHARACTER-X COORDINATE PRINT POSITION REGISTER U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC — — — — — CURPOSX10 CURPOSX9 CURPOSX8 bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CURPOSX7 CURPOSX6 CURPOSX5 CURPOSX4 CURPOSX3 CURPOSX2 CURPOSX1 CURPOSX0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 CURPOSX<10:0>: Current Character Position in the X-Coordinate bits  2010 Microchip Technology Inc. DS39969B-page 321

PIC24FJ256DA210 FAMILY REGISTER 22-30: G1CHRY: CHARACTER Y-COORDINATE PRINT POSITION REGISTER U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC — — — — — CURPOSY10 CURPOSY9 CURPOSY8 bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CURPOSY7 CURPOSY6 CURPOSY5 CURPOSY4 CURPOSY3 CURPOSY2 CURPOSY1 CURPOSY0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 CURPOSY<10:0>: Current Character Position in the Y-Coordinate bits REGISTER 22-31: G1IPU: INFLATE PROCESSOR STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC — — HUFFERR(2) BLCKERR(2) LENERR(2) WRAPERR(2) IPUDONE(1,2) BFINAL(1,2) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 HUFFERR: Undefined Huffmann Code Encountered Status bit(2) 1 = Undefined code is encountered 0 = No undefined code is encountered bit 4 BLCKERR: Undefined Block Code Encountered Status bit(2) 1 = Undefined block is encountered 0 = No undefined block is encountered bit 3 LENERR: Mismatch in Expected Block Length Status bit(2) 1 = Mismatch in block length is detected 0 = No mismatch in block length is detected bit 2 WRAPERR: Wrap-Around Error Status bit(2) 1 = Wrap-around error is encountered 0 = No wrap-around error is encountered bit 1 IPUDONE: IPU Decompression Status bit(1,2) 1 = Decompression is done 0 = Decompression is not yet done bit 0 BFINAL: Final Block Encountered Status bit(1,2) 1 = Final block is encountered 0 = Final block is not encountered Note 1: IPUDONE and BFINAL status bits are set after successful decompression. 2: All IPU status bits are available after each decompression. All status bits are automatically cleared every time a decompression command (IPU_DECOMPRESS) is issued. DS39969B-page 322  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 22-32: G1DBEN: DATA I/O PAD ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GDBEN15 GDBEN14 GDBEN13 GDBEN12 GDBEN11 GDBEN10 GDBEN9 GDBEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GDBEN7 GDBEN6 GDBEN5 GDBEN4 GDBEN3 GDBEN2 GDBEN1 GDBEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 GDBEN<15:0>: Display Data Pads Output Enable bits 1 = Corresponding display data (GD<x>) pin is enabled 0 = Corresponding display data (GD<x>) pin is disabled GDBEN<15:0> can be used to disable or enable specific data signals while the DPPINOE bit (G1CON3<9>) is set. GDBENx DPPINOE (where x = 0 to 15) 1 1 Display data signal (GD) associated with GDBENx is enabled. 1 0 Display data signal (GD) associated with GDBENx is disabled. 0 x Display data signal (GD) associated with GDBENx is disabled.  2010 Microchip Technology Inc. DS39969B-page 323

PIC24FJ256DA210 FAMILY 22.2 Display Resolution and Memory 22.4 Display Buffer and Work Areas Requirements Memory Locations The PIC24FJ256DA210 family of devices has two vari- The PIC24FJ256DA210 family of devices has variants ants in terms of on-board RAM (24-Kbyte and 96-Kbyte with two on-board RAM sizes. These are the 24-Kbyte variants). The 24-Kbyte variant supports monochrome and 96-Kbyte variants. These two RAM variants are displays while the 96-Kbyte variant supports Quarter further divided in terms of pin counts. The 100-pin VGA (QVGA) color displays, up to 256 colors. Support of count device will have the EPMP module available for higher resolution displays with higher color depth extending RAM for applications. The 64-pin count requirements are available by extending the data space device will not have the EPMP modules. Extending the through external memory. Table22-1 provides the sum- RAM size is necessary for applications that require mary of image buffer memory requirements of different larger display buffers and work areas. It is recom- display resolutions and color depth requirements. mended that the display buffers and work areas are not mapped into an area that overlaps the internal RAM 22.3 Display Clock (GCLK) Source and the external RAM. The external RAM can be interfaced using the EPMP module. For details, refer to Frequency of the Graphics Controller Display Clock the “PIC24F Family Reference Manual”, Section 42. (GCLK) signal is determined by programming the “Enhanced Parallel Master Port (EPMP)” GCLKDIV bits (CLKDIV2<15:9>). For more informa- (DS39730). tion, refer to the “PIC24F Family Reference Manual”, Section 6. “Oscillator” (DS39700). TABLE 22-1: BUFFER MEMORY REQUIREMENTS vs. DISPLAY CONFIGURATION Display Buffer Memory Requirements (Bytes) Display Resolution 1 Bpp 2 Bpp 4 Bpp 8 Bpp 16 Bpp 480x272 (WQVGA) 16320 32640 65280 130560 261120 320x240 (QVGA) 9600 19200 38400 76800 153600 240x160 (HQVGA) 4800 9600 19200 38400 76800 160x160 3200 6400 12800 25600 51200 160x120 (QQVGA) 2400 4800 9600 19200 38400 128x64 1024 2048 4096 8192 16384 Legend: Less than 24-Kbyte RAM variants (PIC24FJXXXDA106) Less than 96-Kbyte RAM variants (PIC24FJXXXDA2XX) External Memory with 96 Kbytes/24 Kbytes of RAM variants (PIC24FJXXXDAX10) DS39969B-page 324  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 23.0 10-BIT HIGH-SPEED A/D A block diagram of the A/D Converter is shown in CONVERTER Figure23-1. To perform an A/D conversion: Note: This data sheet summarizes the features 1. Configure the A/D module: of this group of PIC24F devices. It is not a) Configure the port pins as analog inputs intended to be a comprehensive reference and/or select band gap reference inputs source. For more information, refer to the (ANCFG registers). “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” b) Select the voltage reference source to (DS39705). The information in this data match the expected range on analog inputs sheet supersedes the information in the (AD1CON2<15:13>). FRM. c) Select the analog conversion clock to match the desired data rate with the The 10-bit A/D Converter has the following key processor clock (AD1CON3<7:0>). features: d) Select the appropriate sample/conversion • Successive Approximation (SAR) conversion sequence (AD1CON1<7:5> and • Conversion speeds of up to 500 ksps AD1CON3<12:8>). • 24 analog input pins (PIC24FJXXXDAX10 e) Select how the conversion results are devices) and 16 analog input pins presented in the buffer (AD1CON1<9:8>). (PIC24FJXXXDAX06 devices) f) Select the interrupt rate (AD1CON2<6:2>). • External voltage reference input pins g) Turn on the A/D module (AD1CON1<15>). • Internal band gap reference inputs 2. Configure the A/D interrupt (if required): • Automatic Channel Scan mode a) Clear the AD1IF bit. • Selectable conversion trigger source b) Select the A/D interrupt priority. • 32-word conversion result buffer • Selectable Buffer Fill modes • Four result alignment options • Operation during CPU Sleep and Idle modes On all PIC24FJ256DA210 family devices, the 10-bit A/D Converter has 24 analog input pins, designated AN0 through AN23. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins.  2010 Microchip Technology Inc. DS39969B-page 325

PIC24FJ256DA210 FAMILY FIGURE 23-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD VR+ AVSS ct e 16 el VREF+ SR VR- V VREF- Comparator VINH VR- VR+ AN0 S/H DAC VINL AN1 AN2 10-Bit SAR Conversion Logic VINH A X Data Formatting U M VINL AD1BUF0: AD1BUF1F AD1CON1 AD1CON2 AD1CON3 AD1CHS VINH ANCFG B X AD1CSSL AN23 U M AD1CSSH VBG VINL VBG/2 VBG/6 VCAP Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control DS39969B-page 326  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 23-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0, HSC R-0, HSC SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 FORM<1:0>: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU event ends sampling and starts conversion 101 = Reserved 100 = Timer5 compare ends sampling and starts conversion 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion bit 4-3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after the last conversion completes. The SAMP bit is auto-set. 0 = Sampling begins when the SAMP bit is set bit 1 SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done Note 1: The values of the ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module.  2010 Microchip Technology Inc. DS39969B-page 327

PIC24FJ256DA210 FAMILY REGISTER 23-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 r — CSCNA — — bit 15 bit 8 R-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: r = Reserved bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits VCFG<2:0> VR+ VR- 000 AVDD AVSS 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin 1xx AVDD AVSS bit 12 Reserved: Maintain as ‘0’ bit 11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for the CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer, 10-1F, user should access data in 00-0F 0 = A/D is currently filling buffer, 00-0F, user should access data in 10-1F bit 6-2 SMPI<4:0>: Sample/Convert Sequences Per Interrupt Selection bits 11111 = Interrupts at the completion of conversion for each 32nd sample/convert sequence 11110 = Interrupts at the completion of conversion for each 31st sample/convert sequence . . . 00001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 00000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: Buffer Mode Select bit 1 = Buffer is configured as two 16-word buffers (ADC1BUFn<31:16> and ADC1BUFn<15:0>) 0 = Buffer is configured as one 32-word buffer (ADC1BUFn<31:0>) bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for the first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses the MUX A input multiplexer settings DS39969B-page 328  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 23-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock is derived from the system clock bit 14-13 Reserved: Maintain as ‘0’ bit 12-8 SAMC<4:0>: Auto-Sample Time bits 11111 = 31 TAD . . . 00001 = 1 TAD 00000 = 0 TAD (not recommended) bit 7-0 ADCS<7:0>: A/D Conversion Clock Select bits 11111111 = 256 * TCY ······ 00000001 = 2 * TCY 00000000 = TCY  2010 Microchip Technology Inc. DS39969B-page 329

PIC24FJ256DA210 FAMILY REGISTER 23-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — CH0SB4(1) CH0SB3(1) CH0SB2(1) CH0SB1(1) CH0SB0(1) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA4(1) CH0SA3(1) CH0SA2(1) CH0SA1(1) CH0SA0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for MUX B(1) Other = Not available; do not use 11111 = No channel used; all inputs are floating; used for CTMU 11011 = Channel 0 positive input is the band gap divided-by-six reference (VBG/6) 11010 = Channel 0 positive input is the core voltage (VCAP) 11001 = Channel 0 positive input is the band gap reference (VBG) 11000 = Channel 0 positive input is the band gap divided-by-two reference (VBG/2) 10111 = Channel 0 positive input is AN23(2) . . . 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for MUX(1) Other = Not available; do not use 11111 = No Channel used; all inputs are floating; used for CTMU 11011 = Channel 0 positive input is the band gap divided-by-six reference (VBG/6) 11010 = Channel 0 positive input is the core voltage (VCAP) 11001 = Channel 0 positive input is the band gap reference (VBG) 11000 = Channel 0 positive input is the band gap divided-by-two reference (VBG/2) 10111 = Channel 0 positive input is AN23(2) . . . 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 Note 1: Combinations not shown here (11100 to 11110) are unimplemented; do not use. 2: Channel 0 positive inputs, AN16 through AN23, are not available on 64-pin devices (PIC24FJXXXDAX06). DS39969B-page 330  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 23-5: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — VBG6EN VBG2EN VBGEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 VBG6EN: A/D Input VBG/6 Enable bit 1 = Band gap voltage divided-by-six reference (VBG/6) is enabled 0 = Band gap divided-by-six reference (VBG/6) is disabled bit 1 VBG2EN: A/D Input VBG/2 Enable bit 1 = Band gap voltage divided-by-two reference (VBG/2) is enabled 0 = Band gap divided-by-two reference (VBG/2) is disabled bit 0 VBGEN: A/D Input VBG Enable bit 1 = Band gap voltage reference (VBG) is enabled 0 = Band gap reference (VBG) is disabled REGISTER 23-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CSSL<15:0>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel is selected for input scan 0 = Analog channel is omitted from input scan  2010 Microchip Technology Inc. DS39969B-page 331

PIC24FJ256DA210 FAMILY REGISTER 23-7: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CSSL27 CSSL26 CSSL25 CSSL24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL23(1) CSSL22(1) CSSL21(1) CSSL20(1) CSSL19(1) CSSL18(1) CSSL17(1) CSSL16(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 CSSL27: A/D Input Band Gap Scan Selection bit 1 = Band gap divided-by-six reference (VBG/6) is selected for input scan 0 = Analog channel is omitted from input scan bit 10 CSSL26: A/D Input Band Gap Scan Selection bit 1 = Internal core voltage (VCAP) is selected for input scan 0 = Analog channel is omitted from input scan bit 9 CSSL25: A/D Input Half Band Gap Scan Selection bit 1 = Band gap reference (VBG) is selected for input scan 0 = Analog channel is omitted from input scan bit 8 CSSL24: A/D Input Band Gap Scan Selection bit 1 = Band gap divided-by-two reference (VBG/2) is selected for input scan 0 = Analog channel is omitted from input scan bit 7-0 CSSL<23:16>: Analog Input Pin Scan Selection bits(1) 1 = Corresponding analog channel selected for input scan 0 = Analog channel is omitted from input scan Note 1: Unimplemented in 64-pin devices, read as ‘0’. EQUATION 23-1: A/D CONVERSION CLOCK PERIOD(1) TAD ADCS = – 1 TCY TAD = TCY • (ADCS = 1) Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. DS39969B-page 332  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY FIGURE 23-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD RIC  250 Sampling RSS  5 k(Typical) Switch VT = 0.6V Rs ANx RSS CHOLD VA 6C-P1I1N pF VT = 0.6V IL5E0A0K AnGAE == 4D.A4 Cp FC a(Tpyapciictaanl)ce (Typical) VSS Legend:CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from DAC) Note: CPIN value depends on the device package and is not tested. The effect of CPIN IS negligible if Rs  5 k. FIGURE 23-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) Voltage Level 0 V-R V+ – V-RRV- +R1024 512*(V+ – V-)RR 1024 1023*(V+ – V-)RR 1024V+R (V – V)INHINL V- +R V- +R  2010 Microchip Technology Inc. DS39969B-page 333

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 334  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 24.0 TRIPLE COMPARATOR The comparator outputs may be directly connected to MODULE the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of Note: This data sheet summarizes the features the comparator available on the pin. of this group ofPIC24F devices. It is not A simplified block diagram of the module in shown in intended to be a comprehensive reference Figure24-1. Diagrams of the possible individual source. For more information, refer to the comparator configurations are shown in Figure24-2. associated “PIC24F Family Reference Each comparator has its own control register, Manual”. CMxCON (Register24-1), for enabling and configuring The triple comparator module provides three dual input its operation. The output and event status of all three comparators. The inputs to the comparator can be comparators is provided in the CMSTAT register configured to use any one of five external analog inputs (Register24-2). (CxINA, CxINB, CxINC, CxIND and VREF+) and a voltage reference input from one of the internal band gap references or the comparator voltage reference generator (VBG, VBG/2, VBG/6 and CVREF). FIGURE 24-1: TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL<1:0> CCH<1:0> Trigger/Interrupt CEVT Input CPOL Logic COE Select VIN- Logic C1 CXINB 00 VIN+ C1OUT Pin CXINC 01 COUT - 10 CXIND 11 EVPOL<1:0> VBG 00 VBG/2 01 Trigger/Interrupt CEVT VBG/6 10 CPOL Logic COE 11 VIN- VREF+ C2 VIN+ C2OUT Pin CVREFM<1:0>(1) COUT EVPOL<1:0> 0 CXINA + 0 1 Trigger/Interrupt CEVT VREF+ Logic CPOL COE CVREF 1 VIN- C3 CVREFP(1) VIN+ C3OUT Pin COUT CREF Note 1: Refer Register25-1 for bit details.  2010 Microchip Technology Inc. DS39969B-page 335

PIC24FJ256DA210 FAMILY FIGURE 24-2: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0 Comparator Off CEN=0, CREF=x, CCH<1:0>=xx COE VIN- Cx VIN+ Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare CEN=1, CCH<1:0>=00 CVREFM<1:0> = xx CEN=1, CCH<1:0> =01 CVREFM<1:0> = xx COE COE CXINB VIN- CXINC VIN- Cx Cx VIN+ VIN+ CXINA CxOUT CXINA CxOUT Pin Pin Comparator CxIND > CxINA Compare Comparator VBG > CxINA Compare CEN=1, CCH<1:0> =10 CVREFM<1:0> = xx CEN=1, CCH<1:0> =11 CVREFM<1:0> = 00 COE COE CXIND VIN- VBG VIN- Cx Cx VIN+ VIN+ CXINA CxOUT CXINA CxOUT Pin Pin Comparator VBG > CxINA Compare Comparator VBG > CxINA Compare CEN=1, CCH<1:0> =11 CVREFM<1:0> = 01 CEN=1, CCH<1:0> =11 CVREFM<1:0> = 10 COE COE VBG/2 VIN- VBG/6 VIN- CXINA VIN+ Cx CxOUT CXINA VIN+ Cx CxOUT Pin Pin Comparator CxIND > CxINA Compare CEN=1, CCH<1:0> =11 CVREFM<1:0> = 11 COE VREF+ VIN- Cx VIN+ CXINA CxOUT Pin DS39969B-page 336  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY FIGURE 24-3: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN=1, CCH<1:0> =00 CVREFM <1:0> = xx CEN=1, CCH<1:0> =01 CVREFM<1:0> = xx COE COE CXINB VIN- CXINC VIN- Cx Cx CVREF VIN+ CxOUT CVREF VIN+ CxOUT Pin Pin Comparator CxIND > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:0> =10 CVREFM<1:0> = xx CEN=1, CCH<1:0> =11 CVREFM<1:0> = 00 COE COE CXIND VIN- VBG VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT Pin Pin Comparator VBG > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:0> =11 CVREFM<1:0> = 01 CEN=1, CCH<1:0> =11 CVREFM<1:0> = 10 COE COE VBG/2 VIN- VBG/6 VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT Pin Pin Comparator CxIND > CVREF Compare CEN=1, CCH<1:0> =11 CVREFM<1:0> = 11 COE VREF+ VIN- Cx VIN+ CVREF CxOUT Pin FIGURE 24-4: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 1 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN=1, CCH<1:0> =00 CVREFM<1:0> = xx CEN=1, CCH<1:0>=01 CVREFM<1:0> = xx COE COE CXINB VIN- CXINC VIN- Cx Cx VREF+ VIN+ CxOUT VREF+ VIN+ CxOUT Pin Pin Comparator CxIND > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:>=10 CVREFM<1:0> = xx CEN=1, CCH<1:0>=11 CVREFM<1:0> = 00 COE COE CXIND VIN- VBG VIN- VREF+ VIN+ Cx CxOUT VREF+ VIN+ Cx CxOUT Pin Pin Comparator VBG > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:0>=11 CVREFM<1:0> = 01 CEN=1, CCH<1:0> =11 CVREFM<1:0> = 10 COE COE VBG/2 VIN- VBG/6 VIN- VREF+ VIN+ Cx CxOUT VREF+ VIN+ Cx CxOUT Pin Pin  2010 Microchip Technology Inc. DS39969B-page 337

PIC24FJ256DA210 FAMILY R EGISTER 24-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0, HS R-0, HSC CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event that is defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT=0) 10 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ DS39969B-page 338  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 24-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CXINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM<1:0> bits in the CVRCON register 10 = Inverting input of the comparator connects to the CXIND pin 01 = Inverting input of the comparator connects to the CXINC pin 00 = Inverting input of the comparator connects to the CXINB pin REGISTER 24-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC CMIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON<9>). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON<9>). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON<8>). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>).  2010 Microchip Technology Inc. DS39969B-page 339

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 340  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 25.0 COMPARATOR VOLTAGE 25.1 Configuring the Comparator REFERENCE Voltage Reference The voltage reference module is controlled through the Note: This data sheet summarizes the features CVRCON register (Register25-1). The comparator of this group of PIC24F devices. It is not voltage reference provides two ranges of output intended to be a comprehensive reference voltage, each with 16 distinct levels. The range to be source. For more information, refer to the used is selected by the CVRR bit (CVRCON<5>). The “PIC24F Family Reference Manual”, primary difference between the ranges is the size of the Section 19. “Comparator Module” (DS39710). The information in this data steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. sheet supersedes the information in the FRM. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ AVDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U 16 Steps M 1 CVREF o- 6-t CVROE 1 R R CVREF Pin R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 AVSS  2010 Microchip Technology Inc. DS39969B-page 341

PIC24FJ256DA210 FAMILY REGISTER 25-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CVREFP: Voltage Reference Select bit (valid only when CREF is ‘1’) 1 = VREF+ is used as a reference voltage to the comparators 0 = The CVR (4-bit DAC) within this module provides the the reference voltage to the comparators bit 9-8 CVREFM<1:0>: Band Gap Reference Source Select bits (valid only when CCH<1:0> = 11) 00 = Band gap voltage is provided as an input to the comparators 01 = Band gap voltage divided-by-two is provided as an input to the comparators 10 = Band gap voltage divided-by-six is provided as an input to the comparators 11 = VREF+ pin is provided as an input the comparators bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF- 0 = Comparator reference source CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0  CVR<3:0>  15 bits When CVRR = 1: CVREF = (CVR<3:0>/ 24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC) DS39969B-page 342  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 26.0 CHARGE TIME source polarity selection, and edge sequencing. The MEASUREMENT UNIT (CTMU) CTMUICON register controls the selection and trim of the current source. Note: This data sheet summarizes the features of this group ofPIC24F devices. It is not 26.1 Measuring Capacitance intended to be a comprehensive reference The CTMU module measures capacitance by generat- source. For more information, refer to the ing an output pulse with a width equal to the time associated “PIC24F Family Reference between edge events on two separate input channels. Manual”, Section 11. “Charge Time The pulse edge events to both input channels can be Measurement Unit (CTMU)” (DS39724). selected from four sources: two internal peripheral The information in this data sheet modules (OC1 and Timer1) and two external pins supersedes the information in the FRM. (CTEDG1 and CTEDG2). This pulse is used with the The Charge Time Measurement Unit (CTMU) is a flex- module’s precision current source to calculate ible analog module that provides accurate differential capacitance according to the relationship: time measurement between pulse sources, as well as dV asynchronous pulse generation. Its key features C = I------- dT include: For capacitance measurements, the A/D Converter • Four edge input trigger sources samples an external capacitor (CAPP) on one of its • Polarity control for each edge source input channels after the CTMU output’s pulse. A preci- • Control of edge sequence sion resistor (RPR) provides current source calibration • Control of response to edges on a second A/D channel. After the pulse ends, the • Time measurement resolution of 1nanosecond converter determines the voltage on the capacitor. The • Accurate current source suitable for capacitive actual calculation of capacitance is performed in software by the application. measurement Together with other on-chip analog modules, the CTMU Figure26-1 shows the external connections used for capacitance measurements, and how the CTMU and can be used to precisely measure time, measure capacitance, measure relative changes in capacitance A/D modules are related in this application. This or generate output pulses that are independent of the example also shows the edge events coming from Timer1, but other configurations using external edge system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. sources are possible. A detailed discussion on measur- ing capacitance and time with the CTMU module is The CTMU is controlled through two registers: provided in the “PIC24F Family Reference Manual”. CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge FIGURE 26-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse A/D Converter ANx ANY CAPP RPR  2010 Microchip Technology Inc. DS39969B-page 343

PIC24FJ256DA210 FAMILY 26.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN (CTMUCON<12>) bit, the Time measurements on the pulse width can be similarly internal current source is connected to the B input of performed using the A/D module’s internal capacitor Comparator 2. A capacitor (CDELAY) is connected to (CAD) and a precision resistor for current calibration. the Comparator 2 pin, C2INB, and the comparator volt- Figure26-2 shows the external connections used for age reference, CVREF, is connected to C2INA. CVREF time measurements, and how the CTMU and A/D is then configured for a specific trip point. The module modules are related in this application. This example begins to charge CDELAY when an edge event is also shows both edge events coming from the external detected. When CDELAY charges above the CVREF trip CTEDG pins, but other configurations using internal point, a pulse is output on CTPLS. The length of the edge sources are possible. A detailed discussion on pulse delay is determined by the value of CDELAY and measuring capacitance and time with the CTMU module the CVREF trip point. is provided in the “PIC24F Family Reference Manual”. Figure26-3 shows the external connections for pulse generation, as well as the relationship of the different 26.3 Pulse Generation and Delay analog modules required. While CTEDG1 is shown as The CTMU module can also generate an output pulse the input pulse source, other options are available. A with edges that are not synchronous with the device’s detailed discussion on pulse generation with the CTMU system clock. More specifically, it can generate a pulse module is provided in the “PIC24F Family Reference with a programmable delay from an edge event input to Manual”. the module. FIGURE 26-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT TIME PIC24F Device CTMU CTEDG1 EDG1 Current Source CTEDG2 EDG2 Output Pulse A/D Converter ANx CAD RPR FIGURE 26-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTMU CTEDG1 EDG1 CTPLS Current Source Comparator C2INB C2 CDELAY CVREF DS39969B-page 344  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY R EGISTER 26-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HSC R/W-0, HSC EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 10 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information.  2010 Microchip Technology Inc. DS39969B-page 345

PIC24FJ256DA210 FAMILY REGISTER 26-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section10.4 “Peripheral Pin Select (PPS)” for more information. REGISTER 26-2: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current bit 9-8 IRNG<1:0>: Current Source Range Select bits 11 = 100  Base Current 10 = 10  Base Current 01 = Base current level (0.55A nominal) 00 = Current source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39969B-page 346  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 27.0 SPECIAL FEATURES 27.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ256DA210 Note: This data sheet summarizes the features FAMILY DEVICES of this group of PIC24F devices. It is not In PIC24FJ256DA210 family devices, the configuration intended to be a comprehensive reference bytes are implemented as volatile memory. This means source. For more information, refer to the that configuration data must be programmed each time following sections of the “PIC24F Family the device is powered up. Configuration data is stored Reference Manual”. The information in in the three words at the top of the on-chip program this data sheet supersedes the information memory space, known as the Flash Configuration in the FRMs. Words. Their specific locations are shown in • Section 9. “Watchdog Timer (WDT)” Table27-1. These are packed representations of the (DS39697) actual device Configuration bits, whose actual • Section 32. “High-Level Device locations are distributed among several locations in Integration” (DS39719) configuration space. The configuration data is automat- • Section 33. “Programming and ically loaded from the Flash Configuration Words to the Diagnostics” (DS39716) proper Configuration registers during device Resets. PIC24FJ256DA210 family devices include several Note: Configuration data is reloaded on all types features intended to maximize application flexibility and of device Resets. reliability, and minimize cost through elimination of When creating applications for these devices, users external components. These are: should always specifically allocate the location of the • Flexible Configuration Flash Configuration Word for configuration data. This is • Watchdog Timer (WDT) to make certain that program code is not stored in this • Code Protection address when the code is compiled. • JTAG Boundary Scan Interface The upper byte of all Flash Configuration Words in pro- • In-Circuit Serial Programming™ gram memory should always be ‘0000 0000’. This • In-Circuit Emulation makes them appear to be NOP instructions in the remote event that their locations are ever executed by 27.1 Configuration Bits accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘0’s to these The Configuration bits can be programmed (read as ‘0’), locations has no effect on device operation. or left unprogrammed (read as ‘1’), to select various Note: Performing a page erase operation on the device configurations. These bits are mapped starting at last page of program memory clears the program memory location F80000h. A detailed explana- Flash Configuration Words, enabling code tion of the various bit functions is provided in protection as a result. Therefore, users Register27-1 through Register27-6. should avoid performing page erase Note that address F80000h is beyond the user program operations on the last page of program memory space. In fact, it belongs to the configuration memory. memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 27-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ256DA210 FAMILY DEVICES Configuration Word Addresses Device 1 2 3 4 PIC24FJ128DAXXX 157FEh 157FCh 157FAh 157F8h PIC24FJ256DAXXX 2ABFEh 2ABFCh 2ABFAh 2ABF8h  2010 Microchip Technology Inc. DS39969B-page 347

PIC24FJ256DA210 FAMILY REGISTER 27-1: CW1: FLASH CONFIGURATION WORD 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 reserved JTAGEN GCP GWRP DEBUG reserved ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS ALTVREF(1) FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 Reserved: The value is unknown; program as ‘0’ bit 14 JTAGEN: JTAG Port Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled bit 13 GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space bit 12 GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are not allowed bit 11 DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode bit 10 Reserved: Always maintain as ‘1’ bit 9-8 ICS<1:0>: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use bit 7 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’ bit 5 ALTVREF: Alternate VREF Pin Selection bit(1) 1 = VREF is on a default pin (VREF+ on RA10 and VREF- on RA9) 0 = VREF is on an alternate pin (VREF+ on RB0 and VREF- on RB1) Note 1: Unimplemented in 64-pin devices, maintain at ‘1’ (VREF+ on RB0 and VREF- on RB1). DS39969B-page 348  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 27-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Note 1: Unimplemented in 64-pin devices, maintain at ‘1’ (VREF+ on RB0 and VREF- on RB1).  2010 Microchip Technology Inc. DS39969B-page 349

PIC24FJ256DA210 FAMILY REGISTER 27-2: CW2: FLASH CONFIGURATION WORD 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 IESO PLLDIV2 PLLDIV1 PLLDIV0 PLL96MHZ FNOSC2 FNOSC1 FNOSC0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 r-1 R/PO-1 R/PO-1 FCKSM1 FCKSM0 OSCIOFCN IOL1WAY reserved reserved POSCMD1 POSCMD0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) is enabled 0 = IESO mode (Two-Speed Start-up) is disabled bit 14-12 PLLDIV<2:0>: 96 MHz PLL Prescaler Select bits 111 = Oscillator input is divided by 12 (48 MHz input) 110 = Oscillator input is divided by 8 (32 MHz input) 101 = Oscillator input is divided by 6 (24 MHz input) 100 = Oscillator input is divided by 5 (20 MHz input) 011 = Oscillator input is divided by 4 (16 MHz input) 010 = Oscillator input is divided by 3 (12 MHz input) 001 = Oscillator input is divided by 2 (8 MHz input) 000 = Oscillator input is used directly (4 MHz input) bit 11 PLL96MHZ: 96 MHz PLL Start-Up Enable bit 1 = 96 MHz PLL is enabled automatically on start-up 0 = 96 MHz PLL is software controlled (can be enabled by setting the PLLEN bit in CLKDIV<5>) bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 5 OSCIOFCN: OSCO Pin Configuration bit If POSCMD<1:0> = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD<1:0> = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. DS39969B-page 350  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 27-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed bit 3-2 Reserved: Always maintain as ‘1’ bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected REGISTER 27-3: CW3: FLASH CONFIGURATION WORD 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 WPEND WPCFG WPDIS ALTPMP(1) WUTSEL1 WUTSEL0 SOSCSEL1 SOSCSEL0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 WPFP7 WPFP6 WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 bit 7 bit 0 Legend: PO = Program-Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment upper boundary is at the last page of program memory; the lower boundary is the code page specified by WPFP<7:0> 0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper boundary is the code page specified by WPFP<7:0> bit 14 WPCFG: Configuration Word Code Page Write Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected(3) 0 = Last page and Flash Configuration Words are write-protected, provided WPDIS = ‘0’ bit 13 WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection is disabled 0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and WPFPx Configuration bits bit 12 ALTPMP: Alternate EPMP Pin Mapping bit(1) 1 = EPMP pins are in default location mode 0 = EPMP pins are in alternate location mode Note 1: Unimplemented in 64-pin devices, maintain at ‘1’. 2: Ensure that the SCLKI pin is made a digital input while using this configuration, see Table10-1. 3: Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page, the Configuration Word’s page is protected.  2010 Microchip Technology Inc. DS39969B-page 351

PIC24FJ256DA210 FAMILY REGISTER 27-3: CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) bit 11-10 WUTSEL<1:0>: Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator start-up time is used 01 = Fast regulator start-up time is used x0 = Reserved; do not use bit 9-8 SOSCSEL<1:0>: SOSC Selection Configuration bits 11 = Secondary oscillator is in Default (high drive strength) Oscillator mode 10 = Reserved; do not use 01 = Secondary oscillator is in Low-Power (low drive strength) Oscillator mode 00 = External clock (SCLKI) or Digital I/O mode(2) bit 7-0 WPFP<7:0>: Write Protected Code Segment Boundary Page bits Designates the 512 instruction words page boundary of the protected code segment. If WPEND = 1: Specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device. If WPEND = 0: Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary. Note 1: Unimplemented in 64-pin devices, maintain at ‘1’. 2: Ensure that the SCLKI pin is made a digital input while using this configuration, see Table10-1. 3: Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page, the Configuration Word’s page is protected. REGISTER 27-4: CW4: FLASH CONFIGURATION WORD 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 reserved reserved reserved reserved reserved reserved reserved reserved bit 15 bit 8 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 reserved reserved reserved reserved reserved reserved reserved reserved bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘0’ bit 15-0 Reserved: Always maintain as ‘1’ DS39969B-page 352  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY REGISTER 27-5: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-16 Unimplemented: Read as ‘1’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 01000001 = PIC24FJ256DA210 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 00001000 = PIC24FJ128DA206 00001001 = PIC24FJ128DA106 00001010 = PIC24FJ128DA210 00001011 = PIC24FJ128DA110 00001100 = PIC24FJ256DA206 00001101 = PIC24FJ256DA106 00001110 = PIC24FJ256DA210 00001111 = PIC24FJ256DA110  2010 Microchip Technology Inc. DS39969B-page 353

PIC24FJ256DA210 FAMILY REGISTER 27-6: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Device revision identifier bits 27.2 On-Chip Voltage Regulator Low-Voltage Detect Interrupt Flag, LVDIF (IFS4<8>). This can be used to generate an interrupt to trigger an All PIC24FJ256DA210 family devices power their core orderly shutdown. digital logic at a nominal 1.8V. This may create an issue for designs that are required to operate at a higher FIGURE 27-1: CONNECTIONS FOR THE typical voltage, such as 3.3V. To simplify system ON-CHIP REGULATOR design, all devices in the PIC24FJ256DA210 family incorporate an on-chip regulator that allows the device Regulator Enabled (ENVREG tied to VDD): to run its core logic from VDD. 3.3V(1) The regulator is controlled by the ENVREG pin. Tying VDD PIC24FJXXXDA1/DA2 to the pin enables the regulator, which in turn, provides VDD power to the core from the other VDD pins. When the reg- ENVREG ulator is enabled, a low-ESR capacitor (such as ceramic) must be connected to the VCAP pin (Figure27-1). This VCAP helps to maintain the stability of the regulator. The recom- CEFC mended value for the filter capacitor (CEFC) is provided in (10F typ) VSS Section30.1 “DC Characteristics”. Note 1: This is a typical operating voltage. Refer to Section30.1 “DC Characteristics” for 27.2.1 VOLTAGE REGULATOR the full operating ranges of VDD. LOW-VOLTAGE DETECTION When the on-chip regulator is enabled, it provides a 27.2.2 ON-CHIP REGULATOR AND POR constant voltage of 1.8V nominal to the digital core When the voltage regulator is enabled, it takes approx- logic. imately 10s for it to generate output. During this time, The regulator can provide this level from a VDD of about designated as TVREG, code execution is disabled. 2.1V, all the way up to the device’s VDDMAX. It does not TVREG is applied every time the device resumes have the capability to boost VDD levels. In order to pre- operation after any power-down, including Sleep mode. vent “brown-out” conditions when the voltage drops too TVREG is determined by the status of the VREGS bit low for the regulator, the Brown-out Reset occurs. Then (RCON<8>) and the WUTSEL Configuration bits the regulator output follows VDD with a typical voltage (CW3<11:10>). Refer to Section30.0 “Electrical drop of 300 mV. Characteristics” for more information on TVREG. To provide information about when the regulator voltage starts reducing, the on-chip regulator includes a simple Low-Voltage Detect circuit, which sets the DS39969B-page 354  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 27.2.3 ON-CHIP REGULATOR AND BOR 27.3 Watchdog Timer (WDT) When the on-chip regulator is enabled, For PIC24FJ256DA210 family devices, the WDT is PIC24FJ256DA210 family devices also have a simple driven by the LPRC oscillator. When the WDT is brown-out capability. If the voltage supplied to the reg- enabled, the clock source is also enabled. ulator is inadequate to maintain the output level, the The nominal WDT clock source from LPRC is 31kHz. regulator Reset circuitry will generate a Brown-out This feeds a prescaler that can be configured for either Reset. This event is captured by the BOR (RCON<1>) 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. flag bit. The brown-out voltage specifications are The prescaler is set by the FWPSA Configuration bit. provided in Section 7. “Reset” (DS39712) in the With a 31kHz input, the prescaler yields a nominal “PIC24F Family Reference Manual”. WDT Time-out period (TWDT) of 1ms in 5-bit mode or Note: For more information, see Section30.0 4ms in 7-bit mode. “Electrical Characteristics”. The infor- A variable postscaler divides down the WDT prescaler mation in this data sheet supersedes the output and allows for a wide range of time-out periods. information in the FRM. The postscaler is controlled by the WDTPS<3:0> Con- figuration bits (CW1<3:0>), which allows the selection 27.2.4 VOLTAGE REGULATOR STANDBY of a total of 16 settings, from 1:1 to 1:32,768. Using the MODE prescaler and postscaler time-out periods, ranging When enabled, the on-chip regulator always consumes from 1ms to 131 seconds, can be achieved. a small incremental amount of current over IDD/IPD, The WDT, prescaler and postscaler are reset: including when the device is in Sleep mode, even though the core digital logic does not require power. To • On any device Reset provide additional savings in applications where power • On the completion of a clock switch, whether resources are critical, the regulator can be made to invoked by software (i.e., setting the OSWEN bit enter Standby mode on its own whenever the device after changing the NOSC bits) or by hardware goes into Sleep mode. This feature is controlled by the (i.e., Fail-Safe Clock Monitor) VREGS bit (RCON<8>). Clearing the VREGS bit • When a PWRSAV instruction is executed enables the Standby mode. When waking up from (i.e., Sleep or Idle mode is entered) Standby mode, the regulator needs to wait for TVREG to • When the device exits Sleep or Idle mode to expire before wake-up. resume normal operation The regulator wake-up time required for Standby • By a CLRWDT instruction during normal execution mode is controlled by the WUTSEL<1:0> If the WDT is enabled, it will continue to run during (CW3<11:10>) Configuration bits. The regulator Sleep or Idle modes. When the WDT time-out occurs, wake-up time is lower when WUTSEL<1:0> = 01, and the device will wake the device and code execution will higher when WUTSEL<1:0> = 11. Refer to the TVREG continue from where the PWRSAV instruction was exe- specification in Table30-10 for regulator wake-up cuted. The corresponding SLEEP or IDLE time. (RCON<3:2>) bits will need to be cleared in software When the regulator’s Standby mode is turned off after the device wakes up. (VREGS = 1), the device wakes up without waiting for The WDT Flag bit, WDTO (RCON<4>), is not auto- TVREG. However, with the VREGS bit set, the power matically cleared following a WDT time-out. To detect consumption while in Sleep mode will be approximately subsequent WDT events, the flag must be cleared in 40 A higher than what it would be if the regulator was software. allowed to enter Standby mode. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed.  2010 Microchip Technology Inc. DS39969B-page 355

PIC24FJ256DA210 FAMILY 27.3.1 WINDOWED OPERATION 27.3.2 CONTROL REGISTER The Watchdog Timer has an optional Fixed-Window The WDT is enabled or disabled by the FWDTEN mode of operation. In this Windowed mode, CLRWDT Configuration bit. When the FWDTEN Configuration bit instructions can only reset the WDT during the last 1/4 is set, the WDT is always enabled. of the programmed WDT period. A CLRWDT instruction The WDT can be optionally controlled in software when executed before that window causes a WDT Reset, the FWDTEN Configuration bit has been programmed similar to a WDT time-out. to ‘0’. The WDT is enabled in software by setting the Windowed WDT mode is enabled by programming the SWDTEN Control bit (RCON<5>). The SWDTEN WINDIS Configuration bit (CW1<6>) to ‘0’. control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. FIGURE 27-2: WDT BLOCK DIAGRAM SWDTEN LPRC Control FWDTEN Wake from Sleep FWPSA WDTPS<3:0> Prescaler WDT Postscaler LPRC Input (5-bit/7-bit) Counter 1:1 to 1:32.768 WDT Overflow Reset 31 kHz 1 ms/4 ms All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS39969B-page 356  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 27.4 Program Verification and The size and type of protection for the segmented code Code Protection range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code seg- PIC24FJ256DA210 family devices provide two compli- ment protection is enabled by programming the WPDIS mentary methods to protect application code from bit (= 0). The WPFP bits specify the size of the segment overwrites and erasures. These also help to protect the to be protected, by specifying the 512-word code page device from inadvertent configuration changes during that is the start or end of the protected segment. The run time. specified region is inclusive, therefore, this page will also be protected. 27.4.1 GENERAL SEGMENT PROTECTION The WPEND bit determines if the protected segment For all devices in the PIC24FJ256DA210 family, the uses the top or bottom of the program space as a on-chip program memory space is treated as a single boundary. Programming WPEND (= 0) sets the bottom block, known as the General Segment (GS). Code pro- of program memory (000000h) as the lower boundary tection for this block is controlled by one Configuration of the protected segment. Leaving WPEND unpro- bit, GCP. This bit inhibits external reads and writes to grammed (= 1) protects the specified page through the the program memory space. It has no direct effect in last page of implemented program memory, including normal execution mode. the Configuration Word locations. Write protection is controlled by the GWRP bit in the A separate bit, WPCFG, is used to protect the last page Configuration Word. When GWRP is programmed to of program space, including the Flash Configuration ‘0’, internal write and erase operations to program Words. Programming WPCFG (=0) protects the last memory are blocked. page in addition to the pages selected by the WPEND and WPFP<7:0> bits setting. This is useful in circum- 27.4.2 CODE SEGMENT PROTECTION stances where write protection is needed for both the In addition to global General Segment protection, a code segment in the bottom of the memory and the separate subrange of the program memory space can Flash Configuration Words. be individually protected against writes and erases. The various options for segment code protection are This area can be used for many purposes where a sep- shown in Table27-2. arate block of write and erase-protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in the PIC24FJ256DA210 family devices can be located by the user anywhere in the program space and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. It does not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half.  2010 Microchip Technology Inc. DS39969B-page 357

PIC24FJ256DA210 FAMILY 27.4.3 CONFIGURATION REGISTER To safeguard against unpredictable events, Configura- PROTECTION tion bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity The Configuration registers are protected against error and trigger a device Reset. inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of The data for the Configuration registers is derived from the RP registers – shadow registers contain a compli- the Flash Configuration Words in program memory. mentary value which is constantly compared with the When the GCP bit is set, the source data for device actual value. configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code segment protection setting. TABLE 27-2: CODE SEGMENT PROTECTION CONFIGURATION OPTIONS Segment Configuration Bits Write/Erase Protection of Code Segment WPDIS WPEND WPCFG 1 X x No additional protection is enabled; all program memory protection is configured by GCP and GWRP. 0 1 x Addresses from the first address of the code page are defined by WPFP<7:0> through the end of implemented program memory (inclusive), write/erase protected, including Flash Configuration Words. 0 0 1 Address 000000h through the last address of the code page is defined by WPFP<7:0> (inclusive), write/erase protected. 0 0 0 Address 000000h through the last address of code page is defined by WPFP<7:0> (inclusive), write/erase protected and the last page, including Flash Configuration Words are write/erase protected. 27.5 JTAG Interface 27.7 In-Circuit Debugger PIC24FJ256DA210 family devices implement a JTAG When MPLAB® ICD 3 is selected as a debugger, the interface, which supports boundary scan device in-circuit debugging functionality is enabled. This func- testing. tion allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled 27.6 In-Circuit Serial Programming™ through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. PIC24FJ256DA210 family microcontrollers can be seri- To use the in-circuit debugger function of the device, ally programmed while in the end application circuit. the design must implement ICSP connections to This is simply done with two lines for clock (PGECx) MCLR, VDD, VSS and the PGECx/PGEDx pin pair des- and data (PGEDx), and three other lines for power ignated by the ICS Configuration bits. In addition, when (VDD), ground (VSS) and MCLR. This allows customers the feature is enabled, some of the resources are not to manufacture boards with unprogrammed devices available for general use. These resources include the and then program the microcontroller just before first 80 bytes of data RAM and two I/O pins. shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. DS39969B-page 358  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 28.0 DEVELOPMENT SUPPORT 28.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS39969B-page 359

PIC24FJ256DA210 FAMILY 28.2 MPLAB C Compilers for Various 28.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 28.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 28.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 28.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39969B-page 360  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 28.7 MPLAB SIM Software Simulator 28.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip’s most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet buffer and logic analyzer display extend the power of easy-to-use graphical user interface of MPLAB Inte- the simulator to record and track program execution, grated Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer’s PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 28.10 PICkit 3 In-Circuit Debugger/Programmer and 28.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer’s PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with ment in-circuit debugging and In-Circuit Serial Pro- in-circuit debugger systems (RJ11) or with the new gramming™. high-speed, noise tolerant, Low-Voltage Differential Sig- The PICkit 3 Debug Express include the PICkit 3, demo nal (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables.  2010 Microchip Technology Inc. DS39969B-page 361

PIC24FJ256DA210 FAMILY 28.11 PICkit 2 Development 28.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 28.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39969B-page 362  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 29.0 INSTRUCTION SET SUMMARY The literal instructions that involve data movement may use some of the following operands: Note: This chapter is a brief summary of the • A literal value to be loaded into a W register or file PIC24F instruction set architecture and is register (specified by the value of ‘k’) not intended to be a comprehensive • The W register or file register where the literal reference source. value is to be loaded (specified by ‘Wb’ or ‘f’) The PIC24F instruction set adds many enhancements However, literal instructions that involve arithmetic or to the previous PIC® MCU instruction sets, while main- logical operations use some of the following operands: taining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program • The first source operand which is a register ‘Wb’ memory word. Only three instructions require two without any address modifier program memory locations. • The second source operand which is a literal value Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction • The destination of the result (only if not the same type and one or more operands, which further specify as the first source operand), which is typically a the operation of the instruction. The instruction set is register ‘Wd’ with or without an address modifier highly orthogonal and is grouped into four basic The control instructions may use some of the following categories: operands: • Word or byte-oriented operations • A program memory address • Bit-oriented operations • The mode of the table read and table write • Literal operations instructions • Control operations All instructions are a single word, except for certain Table29-1 shows the general symbols used in double-word instructions, which were made describing the instructions. The PIC24F instruction set double-word instructions so that all the required infor- summary in Table29-2 lists all the instructions, along mation is available in these 48 bits. In the second word, with the status flags affected by each instruction. the 8MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most word or byte-oriented W register instructions (including barrel shift instructions) have three Most single-word instructions are executed in a single operands: instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- • The first source operand which is typically a tion. In these cases, the execution takes two instruction register ‘Wb’ without any address modifier cycles, with the additional instruction cycle(s) executed • The second source operand which is typically a as a NOP. Notable exceptions are the BRA (uncondi- register ‘Ws’ with or without an address modifier tional/computed branch), indirect CALL/GOTO, all table • The destination of the result which is typically a reads and writes, and RETURN/RETFIE instructions, register ‘Wd’ with or without an address modifier which are single-word instructions but take two or three cycles. However, word or byte-oriented file register instructions have two operands: Certain instructions that involve skipping over the sub- sequent instruction require either two or three cycles if • The file register specified by the value ‘f’ the skip is performed, depending on whether the • The destination, which could either be the file instruction being skipped is a single-word or two-word register ‘f’ or the W0 register, which is denoted as instruction. Moreover, double-word moves require two ‘WREG’ cycles. The double-word instructions execute in two Most bit-oriented instructions (including simple instruction cycles. rotate/shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’)  2010 Microchip Technology Inc. DS39969B-page 363

PIC24FJ256DA210 FAMILY TABLE 29-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit Bit Selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16383} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388607}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0..W15} Wns One of 16 source working registers {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39969B-page 364  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 29-2: INSTRUCTION SET OVERVIEW Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2010 Microchip Technology Inc. DS39969B-page 365

PIC24FJ256DA210 FAMILY TABLE 29-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep COM COM f f = f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C, DC, N, OV, Z (Wb – Ws – C) CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 C DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DS39969B-page 366  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 29-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC INC f f = f + 1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z IOR IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None POP.S Pop Shadow Registers 1 1 All PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None  2010 Microchip Technology Inc. DS39969B-page 367

PIC24FJ256DA210 FAMILY TABLE 29-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None DS39969B-page 368  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 29-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N  2010 Microchip Technology Inc. DS39969B-page 369

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 370  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256DA210 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256DA210 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS.........................-0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD < 3.0V............................................-0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD > 3.0V..................................................... -0.3V to (+5.5V) Voltage on VBUS pin with respect to VSS, independent of VDD or VUSB ................................................. -0.3V to (+5.5V) Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note1: Maximum allowable current is a function of device maximum power dissipation (see Table30-1). †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010 Microchip Technology Inc. DS39969B-page 371

PIC24FJ256DA210 FAMILY 30.1 DC Characteristics FIGURE 30-1: PIC24FJ256DA210 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.6V 3.6V PIC24FJXXXDA1 )D D V 2.2V 2.2V ( e VBOR VBOR g a t ol V 32 MHz Frequency Note: VCAP (nominal On-Chip Regulator output voltage) = 1.8V. TABLE 30-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit PIC24FJ256DA210 family: Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Power Dissipation (with ENVREG = 1): Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJMAX – TA)/JA W TABLE 30-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Note Package Thermal Resistance, 12x12x1 mm TQFP JA 69.4 — °C/W (Note 1) Package Thermal Resistance, 10x10x1 mm TQFP JA 76.6 — °C/W (Note 1) Package Thermal Resistance, 9x9x0.9 mm QFN JA 28.0 — °C/W (Note 1) Package Thermal Resistance, 10x10x1.1 mm BGA JA 40.2 — °C/W (Note 1) Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS39969B-page 372  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 30-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ Max Units Conditions No. Operating Voltage DC10 Supply Voltage VDD VBOR — 3.6 V Regulator enabled VCAP(2) — 1.8V — V Regulator enabled DC12 VDR RAM Data Retention 1.5 — — V Voltage(1) DC16 VPOR VDD Start Voltage Vss — — V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-3.3V in 66 ms to Ensure Internal 0-2.5V in 50ms Power-on Reset Signal VBOR Brown-out Reset Voltage 2.0 2.10 2.2 V Regulator enabled on VDD Transition, High-to-Low VLVD LVD Trip Voltage — VBOR + 0.10 — V Note 1: This is the limit to which the RAM data can be retained, while the on-chip regulator output voltage starts following the VDD. 2: This is the on-chip regulator output voltage specification.  2010 Microchip Technology Inc. DS39969B-page 373

PIC24FJ256DA210 FAMILY TABLE 30-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) DC20D 0.8 1.3 mA -40°C DC20E 0.8 1.3 mA +25°C 3.3V(3) 1 MIPS DC20F 0.8 1.3 mA +85°C DC23D 3.0 4.8 mA -40°C DC23E 3.0 4.8 mA +25°C 3.3V(3) 4 MIPS DC23F 3.0 4.8 mA +85°C DC24D 12.0 18 mA -40°C DC24E 12.0 18 mA +25°C 3.3V(3) 16 MIPS DC24F 12.0 18 mA +85°C DC31D 55 95 A -40°C DC31E 55 95 A +25°C 3.3V(3) LPRC (31 kHz) DC31F 135 225 A +85°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR=VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. 3: On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. DS39969B-page 374  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 30-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical(1) Max Units Conditions No. Idle Current (IIDLE)(2) DC40D 170 320 A -40°C DC40E 170 320 A +25°C 3.3V(3) 1 MIPS DC40F 220 380 A +85°C DC43D 0.6 1.2 mA -40°C DC43E 0.6 1.2 mA +25°C 3.3V(3) 4 MIPS DC43F 0.7 1.2 mA +85°C DC47D 2.3 4.8 mA -40°C DC47E 2.3 4.8 mA +25°C 3.3V(3) 16 MIPS DC47F 2.4 4.8 mA +85°C DC50D 0.8 1.8 mA -40°C FRC (4 MIPS) DC50E 0.8 1.8 mA +25°C 3.3V(3) DC50F 1.0 1.8 mA +85°C DC51D 40.0 85 A -40°C LPRC (31 kHz) DC51E 40.0 85 A +25°C 3.3V(3) DC51F 120.0 210 A +85°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IIDLE current is measured with the core off; OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. 3: On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled.  2010 Microchip Technology Inc. DS39969B-page 375

PIC24FJ256DA210 FAMILY TABLE 30-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD)(2) DC60D 20.0 45 A -40°C DC60E 20.0 45 A +25°C 3.3V(3) Base power-down current(4) DC60H 55.0 105 A +60°C DC60F 95.0 185 A +85°C DC61D 1.0 3.5 A -40°C DC61E 1.0 3.5 A +25°C 31 kHz LPRC oscillator with 3.3V(3) DC61H 1.0 3.5 A +60°C RTCC, WDT or Timer1:ILPRC(4) DC61F 2.5 6.5 A +85°C DC62D 1.5 6 A -40°C Low drive strength, 32 kHz crystal DC62E 1.5 6 A +25°C 3.3V(3) with RTCC or Timer1: ISOSC; DC62H 1.5 6 A +60°C SOSCSEL<1:0> = 01(4) DC62F 8.0 18 A +85°C DC63D 4.0 18 A -40°C 32 kHz crystal DC63E 4.0 18 A +25°C 3.3V(3) with RTCC or Timer1: ISOSC; DC63H 6.5 18 A +60°C SOSCSEL<1:0> = 11(4) DC63F 12.0 25 A +85°C Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IPD is measured with the device in Sleep mode (all peripherals and clocks are shut down). All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. 3: On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. 4: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39969B-page 376  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 30-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise DC CHARACTERISTICS stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbo Characteristic Min Typ(1) Max Units Conditions No. l VIL Input Low Voltage(3) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C™ Buffer: VSS — 0.3 VDD V DI19 I/O Pins with SMBus Buffer: VSS — 0.8 V SMBus enabled VIH Input High Voltage(3) DI20 I/O Pins with ST Buffer: with Analog Functions, 0.8VDD — VDD V Digital Only 0.8VDD — 5.5 V DI21 I/O Pins with TTL Buffer: with Analog Functions, 0.25 VDD + 0.8 — VDD V Digital Only 0.25 VDD + 0.8 — 5.5 V DI25 MCLR 0.8 VDD — VDD V DI26 OSCI (XT mode) 0.7 VDD — VDD V DI27 OSCI (HS mode) 0.7 VDD — VDD V DI28 I/O Pins with I2C™ Buffer: with Analog Functions, 0.7 VDD — VDD V Digital Only 0.7 VDD — 5.5 V DI29 I/O Pins with SMBus Buffer: 2.5V  VPIN  VDD with Analog Functions, 2.1 VDD V Digital Only 2.1 5.5 V DI30 ICNPU CNxx Pull-up Current 150 350 550 A VDD = 3.3V, VPIN = VSS DI30A ICNPD CNxx Pull-down Current 15 70 150 A VDD = 3.3V, VPIN = VDD IIL Input Leakage Current(2) DI50 I/O Ports — — +1 A VSS  VPIN  VDD, pin at high-impedance DI51 Analog Input Pins — — +1 A VSS  VPIN  VDD, pin at high-impedance DI55 MCLR — — +1 A VSS VPIN VDD DI56 OSCI/CLKI — — +1 A VSS VPIN VDD, EC, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Negative current is defined as current sourced by the pin. 3: Refer to Table1-1 for I/O pins buffer types.  2010 Microchip Technology Inc. DS39969B-page 377

PIC24FJ256DA210 FAMILY TABLE 30-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VOL Output Low Voltage DO10 I/O Ports — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2.2V DO16 OSCO/CLKO — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2.2V VOH Output High Voltage DO20 I/O Ports 3.0 — — V IOH = -3.0 mA, VDD = 3.6V 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.65 — — V IOH = -1.0 mA, VDD = 2.2V 1.4 — — V IOH = -3.0 mA, VDD = 2.2V DO26 OSCO/CLKO 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.4 — — V IOH = -1.0 mA, VDD = 2.2V Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 30-9: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.2V to 3.6V (unless otherwise DC CHARACTERISTICS stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10000 — — E/W -40C to +85C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D133A TIW Self-Timed Word Write — 20 — s Cycle Time Self-Timed Row Write — 1.5 — ms Cycle Time D133B TIE Self-Timed Page Erase 20 — 40 ms Time D134 TRETD Characteristic Retention 20 — — Year If no other specifications are violated D135 IDDP Supply Current during — 16 — mA Programming Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39969B-page 378  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 30-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage — 1.8 — V VBG Internal Band Gap Reference — 1.2 — V CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 Ohm recommended; < 5 Ohm required. TVREG — 10 — s VREGS = 1, VREGS = 0 with WUTSEL<1:0> = 01 or any POR or BOR — 190 — s Sleep wake-up with VREGS = 0 and WUTSEL<1:0> = 11 TBG Band Gap Reference Start-up — 1 — ms Time 30.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ256DA210 family AC characteristics and timing parameters. TABLE 30-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Operating voltage VDD range as described in Section30.1 “DC Characteristics”. FIGURE 30-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSCO VSS 15 pF for OSCO output  2010 Microchip Technology Inc. DS39969B-page 379

PIC24FJ256DA210 FAMILY TABLE 30-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO50 COSCO OSCO/CLKO Pin — — 15 pF In XT and HS modes when external clock is used to drive OSCI DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 30-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 DS39969B-page 380  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 30-13: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS10 FOSC External CLKI Frequency DC — 32 MHz EC (External clocks allowed 4 — 48 MHz ECPLL only in EC mode) Oscillator Frequency 3.5 — 10 MHz XT 4 — 8 MHz XTPLL 10 — 32 MHz HS 10 — 32 MHz HSPLL 31 — 33 kHz SOSC OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(2) 62.5 — DC ns OS30 TosL, External Clock in (OSCI) 0.45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock in (OSCI) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3) — 6 10 ns OS41 TckF CLKO Fall Time(3) — 6 10 ns Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). TABLE 30-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.2V TO 3.6V) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OS50 FPLLI PLL Input Frequency 4 — 48 MHz ECPLL mode Range(2) 4 32 MHz HSPLL mode 4 8 MHz XTPLL mode OS51 FSYS PLL Output Frequency 95.76 — 96.24 MHz Range OS52 TLOCK PLL Start-up Time — — 200 s (Lock Time) OS53 DCLK CLKO Stability (Jitter) -0.25 — 0.25 % Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS39969B-page 381

PIC24FJ256DA210 FAMILY TABLE 30-15: INTERNAL RC ACCURACY Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for Industrial Param Characteristic Min Typ Max Units Conditions No. F20 FRC Accuracy @ -1 ±0.15 1 % -40°C  TA +85°C 2.2V  VDD 3.6V 8MHz(1,2) F21 LPRC @ 31 kHz -20 — 20 % -40°C  TA +85°C VCAP (on-chip regulator output voltage) = 1.8V Note 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. 2: To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum. TABLE 30-16: RC OSCILLATOR START-UP TIME Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Characteristic Min Typ Max Units Conditions No. TFRC — 15 — s TLPRC — 50 — s TABLE 30-17: RESET AND BROWN-OUT RESET REQUIREMENTS Standard Operating Conditions: 2.2V to 3.6V (unless other- AC CHARACTERISTICS wise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ Max Units Conditions No. SY10 TMCL MCLR Pulse width (Low) 2 — — s SY12 TPOR Power-on Reset Delay — 2 — s SY13 TIOZ I/O High-Impedance from MCLR — — 100 ns Low or Watchdog Timer Reset SY25 TBOR Brown-out Reset Pulse Width 1 — — s VDD VBOR TRST Internal State Reset Time — 50 — s DS39969B-page 382  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY FIGURE 30-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure30-2 for load conditions. TABLE 30-18: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise AC CHARACTERISTICS stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx Pin High or Low 20 — — ns Time (input) DI40 TRBP CNx High or Low Time 2 — — TCY (input) Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2010 Microchip Technology Inc. DS39969B-page 383

PIC24FJ256DA210 FAMILY TABLE 30-19: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V VDD – 0.3 VDD + 0.3 or 2.2 or 3.6 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V AD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 V Voltage Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V (Note 2) AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 VINL Absolute VINL Input AVSS – 0.3 AVDD/2 V Voltage AD13 Leakage Current — ±1.0 ±610 nA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5k AD17 RIN Recommended Impedance — — 2.5K  10-bit of Analog Voltage Source ADC Accuracy AD20B Nr Resolution — 10 — bits AD21B INL Integral Nonlinearity — ±1 <±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22B DNL Differential Nonlinearity — ±0.5 <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23B GERR Gain Error — ±1 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD24B EOFF Offset Error — ±1 ±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25B Monotonicity(1) — — — — Guaranteed Note 1: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. 2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference. DS39969B-page 384  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY TABLE 30-20: ADC CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.2V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD ADC Clock Period 75 — — ns TCY = 75 ns, AD1CON3 in default state AD51 tRC ADC Internal RC Oscillator — 250 — ns Period Conversion Rate AD55 tCONV Conversion Time — 12 — TAD AD56 FCNV Throughput Rate — — 500 ksps AVDD > 2.7V AD57 tSAMP Sample Time — 1 — TAD Clock Parameters AD61 tPSS Sample Start Delay from Setting 2 — 3 TAD Sample bit (SAMP) Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.  2010 Microchip Technology Inc. DS39969B-page 385

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 386  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY 31.0 PACKAGING INFORMATION 31.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX PIC24FJ256 XXXXXXXXXX DA106-I/ XXXXXXXXXX PTe3 YYWWNNN 1020017 64-Lead QFN (9x9x0.9 mm) Example XXXXXXXXXXX PIC24FJ256 XXXXXXXXXXX DA206-I/MRe3 XXXXXXXXXXX 1010017 YYWWNNN 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX PIC24FJ256DA XXXXXXXXXXXX 110-I/PTe3 YYWWNNN 1020017 121-BGA (10x10x1.1 mm) Example XXXXXXXXXXXX PIC24FJ256DA XXXXXXXXXXXX 110-I/BGe3 YYWWNNN 1020017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS39969B-page 387

PIC24FJ256DA210 FAMILY 31.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 N b NOTE1 123 NOTE2 α A c φ A2 β A1 L L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 ;(cid:5) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)@/1 DS39969B-page 388  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)  2010 Microchip Technology Inc. DS39969B-page 389

PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 390  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS39969B-page 391

PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 392  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY (cid:27)(cid:28)(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 e E E1 N b NOTE1 123 NOTE2 α c A φ β L A1 L1 A2 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 (cid:15)(cid:4)(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)(cid:5)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:16) (cid:4)(cid:30)(cid:15)@ (cid:4)(cid:30)(cid:17)(cid:16) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:15)(cid:4)(cid:4)1  2010 Microchip Technology Inc. DS39969B-page 393

PIC24FJ256DA210 FAMILY (cid:27)(cid:28)(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) DS39969B-page 394  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS39969B-page 395

PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 396  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY APPENDIX A: REVISION HISTORY Revision A (February 2010) Original data sheet for the PIC24FJ256DA210 family of devices. Revision B (May 2010) Minor changes throughout text and the values in Section30.0 “Electrical Characteristics” were updated.  2010 Microchip Technology Inc. DS39969B-page 397

PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 398  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY INDEX A Shared I/O Port Structure.........................................157 SPI Master, Frame Master Connection....................220 A/D Conversion SPI Master, Frame Slave Connection......................220 10-Bit High-Speed A/D Converter.............................325 SPI Master/Slave Connection A/D Converter...................................................................325 (Enhanced Buffer Modes).................................219 Analog Input Model...................................................333 SPI Master/Slave Connection Transfer Function......................................................333 (Standard Mode)...............................................219 AC Characteristics SPI Slave, Frame Master Connection......................220 ADC Conversion Timing...........................................385 SPI Slave, Frame Slave Connection........................220 CLKO and I/O Timing................................................383 SPIx Module (Enhanced Mode)................................213 Internal RC Accuracy................................................382 SPIx Module (Standard Mode).................................212 Alternate Interrupt Vector Table (AIVT)..............................93 System Clock............................................................141 Alternative Master Triple Comparator Module........................................335 EPMP........................................................................273 UART (Simplified).....................................................231 Assembler USB OTG MPASM Assembler...................................................360 Device Mode Power Modes..............................241 B USB OTG Interrupt Funnel.......................................248 Block Diagram USB OTG Module.....................................................240 CRC..........................................................................297 Watchdog Timer (WDT)............................................356 Block Diagrams C 10-Bit High-Speed A/D Converter.............................326 C Compilers 16-Bit Asynchronous Timer3 and Timer5.................193 MPLAB C18..............................................................360 16-Bit Synchronous Timer2 and Timer4...................193 Charge Time Measurement Unit (CTMU).........................343 16-Bit Timer1 Module................................................189 Key Features............................................................343 32-Bit Timer2/3 and Timer4/5...................................192 Charge Time Measurement Unit. See CTMU. 96 MHz PLL..............................................................150 Code Examples Accessing Program Space Using Table Basic Sequence for Clock Switching in Operations..........................................................77 Assembly..........................................................149 Addressing for Table Registers...................................81 Configuring UART1 I/O Input/Output BDT Mapping for Endpoint Buffering Modes............244 Functions (PPS)...............................................168 CALL Stack Frame......................................................75 EDS Read From Program Memory in Assembly........80 Comparator Voltage Reference................................341 EDS Read in Assembly..............................................72 CPU Programmer’s Model..........................................41 EDS Write in Assembly..............................................73 CRC Shift Engine Detail............................................297 Erasing a Program Memory Block (Assembly)...........84 CTMU Connections and Internal Configuration I/O Port Read/Write in ‘C’.........................................163 for Capacitance Measurement..........................343 I/O Port Read/Write in Assembly..............................163 CTMU Typical Connections and Internal Initiating a Programming Sequence...........................85 Configuration for Pulse Delay Generation........344 PWRSAV Instruction Syntax....................................155 CTMU Typical Connections and Internal Setting the RTCWREN Bit........................................286 Configuration for Time Measurement...............344 Single-Word Flash Programming...............................86 Data Access From Program Space Single-Word Flash Programming Address Generation...........................................76 (‘C’ Language)....................................................86 Graphics Module Overview.......................................305 I2C Module................................................................224 Code Protection................................................................357 Code Segment Protection........................................357 Individual Comparator Configurations, Configuration Options.......................................358 CREF = 0..........................................................336 Configuration Protection...........................................358 Individual Comparator Configurations, Comparator Voltage Reference........................................341 CREF = 1 and CVREFP = 0.............................337 Configuring...............................................................341 Individual Comparator ConfigurationS, Configuration Bits.............................................................347 CREF = 1 and CVREFP = 1.............................337 Core Features.....................................................................15 Input Capture............................................................197 CPU On-Chip Regulator Connections...............................354 Arithmetic Logic Unit (ALU)........................................43 Output Compare (16-Bit Mode).................................202 Control Registers........................................................42 Output Compare (Double-Buffered, Core Registers............................................................40 16-Bit PWM Mode)...........................................204 Programmer’s Model..................................................39 PCI24FJ256DA210 Family (General).........................20 CRC PIC24F CPU Core......................................................40 32-Bit Programmable Cyclic PSV Operation (Higher Word)....................................79 Redundancy Check..........................................297 PSV Operation (Lower Word).....................................79 Polynomials..............................................................298 Reset System..............................................................87 Setup Examples for 16 and 32-Bit Polynomials.......298 RTCC........................................................................285 User Interface...........................................................298  2010 Microchip Technology Inc. DS39969B-page 399

PIC24FJ256DA210 FAMILY CTMU F Measuring Capacitance............................................343 Flash Configuration Words.........................................46, 347 Measuring Time........................................................344 Flash Program Memory......................................................81 Pulse Delay and Generation.....................................344 and Table Instructions................................................81 Customer Change Notification Service.............................405 Enhanced ICSP Operation.........................................82 Customer Notification Service...........................................405 JTAG Operation..........................................................82 Customer Support.............................................................405 Programming Algorithm..............................................84 D RTSP Operation.........................................................82 Single-Word Programming.........................................86 Data Memory Address Space............................................................47 G Memory Map...............................................................48 Graphics Controller (GFX)................................................305 Near Data Space........................................................49 Key Features............................................................305 SFR Space..................................................................49 Graphics Controller Module (GFX)...................................305 Software Stack............................................................75 Graphics Display Module Space Organization, Alignment..................................49 Display Clock (GCLK) Source..................................324 DC Characteristics Display Configuration................................................324 I/O Pin Input Specifications.......................................377 Memory Locations....................................................324 I/O Pin Output Specifications....................................378 Memory Requirements.............................................324 Program Memory......................................................378 Module Registers......................................................306 Development Support.......................................................359 Graphics Display Module (GFX).......................................305 Device Features 100/121--Pin...............................................................19 I 64-Pin..........................................................................18 I/O Ports Doze Mode........................................................................156 Analog Port Pins Configuration.................................158 E Analog/Digital Function of an I/O Pin........................158 Input Change Notification.........................................163 EDS...................................................................................273 Open-Drain Configuration.........................................158 Electrical Characteristics Parallel (PIO)............................................................157 A/D Specifications.....................................................384 Peripheral Pin Select................................................164 Absolute Maximum Ratings......................................371 Pull-ups and Pull-downs...........................................163 Capacitive Loading on Output Pin............................380 Selectable Input Sources..........................................165 External Clock Timing...............................................381 I2C Idle Current...............................................................375 Clock Rates..............................................................225 Load Conditions and Requirements for Reserved Addresses................................................225 Specifications....................................................379 Setting Baud Rate as Bus Master.............................225 Operating Current.....................................................374 Slave Address Masking............................................225 PLL Clock Timing Specifications...............................381 Idle Mode..........................................................................156 Power-Down Current................................................376 Input Capture RC Oscillator Start-up Time......................................382 32-Bit Mode..............................................................198 Reset and Brown-out Reset Requirements..............382 Operations................................................................198 Temperature and Voltage Specifications..................373 Synchronous and Trigger Modes..............................197 Thermal Conditions...................................................372 Input Capture with Dedicated Timers...............................197 V/F Graph.................................................................372 Input Voltage Levels for Port or Pin Voltage Regulator Specifications..............................379 Tolerated Description Input.......................................158 Enhanced Parallel Master Port. See EPMP......................273 Instruction Set ENVREG Pin.....................................................................354 Overview...................................................................365 EPMP................................................................................273 Summary..................................................................363 Alternative Master.....................................................273 Instruction-Based Power-Saving Modes...................155, 156 Key Features.............................................................273 Interfacing Program and Data Spaces................................75 Master Port Pins.......................................................274 Inter-Integrated Circuit. See I2C.......................................223 Equations Internet Address...............................................................405 16-Bit, 32-Bit CRC Polynomials................................298 Interrupt Vector Table (IVT)................................................93 A/D Conversion Clock Period...................................332 Interrupts Baud Rate Reload Calculation..................................225 Control and Status Registers......................................96 Calculating the PWM Period.....................................204 Implemented Vectors..................................................95 Calculation for Maximum PWM Resolution...............205 Reset Sequence.........................................................93 Estimating USB Transceiver Current Setup and Service Procedures.................................140 Consumption.....................................................243 Trap Vectors...............................................................94 Relationship Between Device and SPI Vector Table...............................................................94 Clock Speed......................................................221 RTCC Calibration......................................................294 J UART Baud Rate with BRGH = 0.............................232 JTAG Interface..................................................................358 UART Baud Rate with BRGH = 1.............................232 Errata..................................................................................14 DS39969B-page 400  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY K Program Memory Access Using Table Instructions................................77 Key Features.....................................................................347 Address Construction.................................................75 CTMU........................................................................343 Address Space...........................................................45 EPMP........................................................................273 Flash Configuration Words.........................................46 RTCC........................................................................285 Memory Maps.............................................................45 M Organization...............................................................46 Memory Organization..........................................................45 Reading From Program Memory Using EDS.............78 Microchip Internet Web Site..............................................405 Pulse-Width Modulation (PWM) Mode..............................203 MPLAB ASM30 Assembler, Linker, Librarian...................360 Pulse-Width Modulation. See PWM. MPLAB Integrated Development PWM Environment Software...............................................359 Duty Cycle and Period..............................................204 MPLAB PM3 Device Programmer....................................362 R MPLAB REAL ICE In-Circuit Emulator System.................361 Reader Response.............................................................406 MPLINK Object Linker/MPLIB Object Librarian................360 Reference Clock Output...................................................152 N Register Maps Near Data Space................................................................49 A/D Converter.............................................................61 ANCFG.......................................................................64 O ANSEL........................................................................64 Oscillator Configuration Comparators...............................................................66 96 MHz PLL..............................................................149 CPU Core...................................................................50 Clock Selection.........................................................142 CRC............................................................................66 Clock Switching.........................................................148 CTMU.........................................................................62 Sequence..........................................................148 Enhanced Parallel Master/Slave Port.........................65 CPU Clocking Scheme.............................................142 Graphics.....................................................................69 Display Clock Frequency Division.............................152 I2C™...........................................................................56 Initial Configuration on POR.....................................142 ICN.............................................................................51 USB Operations........................................................151 Input Capture..............................................................54 Output Compare Interrupt Controller......................................................52 32-Bit Mode...............................................................201 NVM............................................................................70 Synchronous and Trigger Modes..............................201 Output Compare.........................................................55 Output Compare with Dedicated Timers...........................201 Pad Configuration.......................................................60 Peripheral Pin Select..................................................67 P PMD............................................................................70 Packaging.........................................................................387 PORTA.......................................................................58 Details.......................................................................388 PORTB.......................................................................58 Marking.....................................................................387 PORTC.......................................................................59 Peripheral Enable Bits......................................................156 PORTD.......................................................................59 Peripheral Module Disable Bits.........................................156 PORTE.......................................................................59 Peripheral Pin Select (PPS)..............................................164 PORTF.......................................................................60 Available Peripherals and Pins.................................164 PORTG.......................................................................60 Configuration Control................................................167 RTCC..........................................................................65 Considerations for Use.............................................168 SPI..............................................................................58 Input Mapping...........................................................164 System........................................................................70 Mapping Exceptions..................................................167 Timers.........................................................................53 Output Mapping........................................................166 UART..........................................................................57 Peripheral Priority.....................................................164 USB OTG...................................................................63 Registers...................................................................169 Registers Pin Descriptions AD1CHS (A/D Input Select)......................................330 100-Pin Devices............................................................8 AD1CON1 (A/D Control 1)........................................327 121 (BGA)-Pin Devices...............................................11 AD1CON2 (A/D Control 2)........................................328 64-Pin Devices..............................................................6 AD1CON3 (A/D Control 3)........................................329 Pin Diagrams AD1CSSH (A/D Input Scan Select, High).................332 100-Pin TQFP...............................................................7 AD1CSSL (A/D Input Scan Select, Low)..................331 121-Pin BGA...............................................................10 ALCFGRPT (Alarm Configuration)...........................289 64-Pin TQFP/QFN........................................................5 ALMINSEC (Alarm Minutes and Seconds Value).....293 Pinout Descriptions.............................................................21 ALMTHDY (Alarm Month and Day Value)................292 POR ALWDHR (Alarm Weekday and Hours Value).........293 and On-Chip Voltage Regulator................................354 ANCFG (A/D Band Gap Reference Power-Saving Configuration)...................................................331 Clock Frequency and Clock Switching......................155 ANSA (PORTA Analog Function Selection).............159 Features....................................................................155 ANSB (PORTB Analog Function Selection).............160 Instruction-Based Modes..........................................155 ANSC (PORTC Analog Function Selection).............160 Power-up Requirements...................................................355 ANSD (PORTD Analog Function Selection).............161 Product Identification System...........................................407 ANSE (PORTE Analog Function Selection).............161  2010 Microchip Technology Inc. DS39969B-page 401

PIC24FJ256DA210 FAMILY ANSF (PORTF Analog Function Selection)..............162 G1STAT (Graphics Control Status)..........................310 ANSG (PORTG Analog Function Selection).............162 G1VSYNC (Vertical Synchronization Control)..........318 BDnSTAT Prototype (Buffer Descriptor n G1W1ADRH (GPU Work Area 1 Status, CPU Mode)...........................................247 Start Address High)..........................................313 BDnSTAT Prototype (Buffer Descriptor n G1W1ADRL (GPU Work Area 1 Status, USB Mode)...........................................246 Start Address Low)...........................................313 CLKDIV (Clock Divider)............................................145 G1W2ADRH (GPU Work Area 2 CLKDIV2 (Clock Divider 2).......................................147 Start Address High...........................................314 CMSTAT (Comparator Status)..................................339 G1W2ADRL (GPU Work Area 2 CMxCON (Comparator x Control).............................338 Start Address Low)...........................................313 CORCON (CPU Core Control)..............................43, 98 I2CxCON (I2Cx Control)...........................................226 CRCCON1 (CRC Control 1).....................................300 I2CxMSK (I2Cx Slave Mode Address Mask)............230 CRCCON2 (CRC Control 2).....................................301 I2CxSTAT (I2Cx Status)...........................................228 CRCDATH (CRC Data High)....................................302 ICxCON1 (Input Capture x Control 1).......................199 CRCDATL (CRC Data Low)......................................302 ICxCON2 (Input Capture x Control 2).......................200 CRCWDATH (CRC Shift High).................................303 IEC0 (Interrupt Enable Control 0).............................109 CRCWDATL (CRC Shift Low)...................................303 IEC1 (Interrupt Enable Control 1).............................110 CRCXORH (CRC XOR High)...................................302 IEC2 (Interrupt Enable Control 2).............................112 CRCXORL (CRC XOR Polynomial, IEC3 (Interrupt Enable Control 3).............................113 Low Byte)..........................................................301 IEC4 (Interrupt Enable Control 4).............................114 CTMUCON (CTMU Control).....................................345 IEC5 (Interrupt Enable Control 5).............................115 CTMUICON (CTMU Current Control).......................346 IEC6 (Interrupt Enable Control 6).............................116 CVRCON (Comparator Voltage IFS0 (Interrupt Flag Status 0)...................................101 Reference Control)............................................342 IFS1 (Interrupt Flag Status 1)...................................102 CW1 (Flash Configuration Word 1)...........................348 IFS2 (Interrupt Flag Status 2)...................................103 CW2 (Flash Configuration Word 2)...........................350 IFS3 (Interrupt Flag Status 3)...................................105 CW3 (Flash Configuration Word 3)...........................351 IFS4 (Interrupt Flag Status 4)...................................106 CW4 (Flash Configuration Word 4)...........................352 IFS5 (Interrupt Flag Status 5)...................................107 DEVID (Device ID)....................................................353 IFS6 (Interrupt Flag Status 6)...................................108 DEVREV (Device Revision)......................................354 INTCON1 (Interrupt Control 1)....................................99 G1ACTDA (Active Display Area)..............................317 INTCON2 (Interrupt Control 2)..................................100 G1CHRX (Character X-Coordinate INTTREG (Interrupt Controller Test..........................139 Print Position)....................................................321 IPC0 (Interrupt Priority Control 0).............................117 G1CHRY (Character Y-Coordinate IPC1 (Interrupt Priority Control 1).............................118 Print Position)....................................................322 IPC10 (Interrupt Priority Control 10).........................127 G1CLUT (Color Look-up Table Control)...................319 IPC11 (Interrupt Priority Control 11).........................128 G1CLUTRD (Color Look-up Table Memory IPC12 (Interrupt Priority Control 12).........................129 Read Data)........................................................320 IPC13 (Interrupt Priority Control 13).........................130 G1CLUTWR (Color Look-up Table Memory IPC15 (Interrupt Priority Control 15).........................131 Write Data)........................................................320 IPC16 (Interrupt Priority Control 16).........................132 G1CMDH (GPU Command High).............................306 IPC18 (Interrupt Priority Control 18).........................133 G1CMDL (GPU Command Low)...............................306 IPC19 (Interrupt Priority Control 19).........................133 G1CON1 (Display Control 1)....................................307 IPC2 (Interrupt Priority Control 2).............................119 G1CON2 (Display Control 2)....................................308 IPC20 (Interrupt Priority Control 20).........................134 G1CON3 (Display Control 3)....................................309 IPC21 (Interrupt Priority Control 21).........................135 G1DBEN (Data I/O Pad Enable)...............................323 IPC22 (Interrupt Priority Control 22).........................136 G1DBLCON (Display Blanking Control)....................318 IPC23 (Interrupt Priority Control 23).........................137 G1DPADRH (Display Buffer Start IPC25 (Interrupt Priority Control 25).........................138 Address High)...................................................315 IPC3 (Interrupt Priority Control 3).............................120 G1DPADRL (Display Buffer Start IPC4 (Interrupt Priority Control 4).............................121 Address Low)....................................................315 IPC5 (Interrupt Priority Control 5).............................122 G1DPDPH (Display Buffer Height)...........................316 IPC6 (Interrupt Priority Control 6).............................123 G1DPHT (Display Total Height)................................316 IPC7 (Interrupt Priority Control 7).............................124 G1DPW (Display Buffer Width).................................315 IPC8 (Interrupt Priority Control 8).............................125 G1DPWT (Display Total Width)................................316 IPC9 (Interrupt Priority Control 9).............................126 G1HSYNC (Horizontal IPCn (Interrupt Priority Control 0-23)........................137 Synchronization Control)...................................317 MINSEC (RTCC Minutes and Seconds Value).........291 G1IE (GFX Interrupt Enable)....................................311 MTHDY (RTCC Month and Day Value)....................290 G1IPU (Inflate Processor Status)..............................322 NVMCON (Flash Memory Control).............................83 G1IR (GFX Interrupt Status).....................................312 OCxCON1 (Output Compare x Control 1)................206 G1MRGN (Interrupt Advance)..................................321 OCxCON2 (Output Compare x Control 2)................208 G1PUH (GPU Work Area Height).............................314 OSCCON (Oscillator Control)...................................143 G1PUW (GPU Work Area Width).............................314 DS39969B-page 402  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY OSCTUN (FRC Oscillator Tune)...............................146 Revision History................................................................397 PADCFG1 (Pad Configuration Control)............283, 288 RTCC PMCON1 (EPMP Control 1).....................................275 Alarm Configuration..................................................294 PMCON2 (EPMP Control 2).....................................276 Calibration................................................................294 PMCON3 (EPMP Control 3).....................................277 Key Features............................................................285 PMCON4 (EPMP Control 4).....................................278 Register Mapping.....................................................286 PMCSxBS (Chip Select x Base Address).................280 S PMCSxCF (Chip Select x Configuration)..................279 PMCSxMD (Chip Select x Mode)..............................281 Selective Peripheral Power Control..................................156 PMSTAT (EPMP Status, Slave Mode)......................282 Serial Peripheral Interface (SPI).......................................211 RCFGCAL (RTCC Calibration and Configuration)....287 Serial Peripheral Interface. See SPI. RCON (Reset Control)................................................88 SFR Space.........................................................................49 REFOCON (Reference Oscillator Control)...............153 Sleep Mode......................................................................155 RPINRn (PPS Input).........................................169–179 Software Simulator (MPLAB SIM)....................................361 RPORn (PPS Output).......................................180–187 Software Stack...................................................................75 SPIxCON1 (SPIx Control 1)......................................216 Special Features.................................................................16 SPIxCON2 (SPIx Control 2)......................................218 SPI....................................................................................211 SPIxSTAT (SPIx Status and Control).......................214 T SR (ALU STATUS)...............................................42, 97 T1CON (Timer1 Control)...........................................190 Timer1..............................................................................189 TxCON (Timer2 and Timer4 Control)........................194 Timer2/3 and Timer4/5.....................................................191 TyCON (Timer3 and Timer5 Control)........................195 Timing Diagrams U1ADDR (USB Address)..........................................261 CLKO and I/O Timing...............................................383 U1CNFG1 (USB Configuration 1).............................262 External Clock..........................................................380 U1CNFG2 (USB Configuration 2).............................263 Triple Comparator.............................................................335 U1CON (USB Control, Device Mode).......................259 Triple Comparator Module................................................335 U1CON (USB Control, Host Mode)...........................260 U U1EIE (USB Error Interrupt Enable).........................270 UART................................................................................231 U1EIR (USB Error Interrupt Status)..........................269 Baud Rate Generator (BRG)....................................232 U1EPn (USB Endpoint n Control).............................271 IrDA Support.............................................................233 U1IE (USB Interrupt Enable).....................................268 Operation of UxCTS and UxRTS Pins......................233 U1IR (USB Interrupt Status, Device Mode)..............266 Receiving in 8-Bit or 9-Bit Data Mode......................233 U1IR (USB Interrupt Status, Host Mode)..................267 Transmitting U1OTGCON (USB OTG Control).............................256 Break and Sync Sequence...............................233 U1OTGIE (USB OTG Interrupt Enable, in 8-Bit Data Mode............................................233 Host Mode).......................................................265 Transmitting in 9-Bit Data Mode...............................233 U1OTGIR (USB OTG Interrupt Status, Universal Asynchronous Receiver Transmitter. See UART. Host Mode).......................................................264 Universal Serial Bus U1OTGSTAT (USB OTG Status)..............................255 U1PWMCON USB (VBUS PWM Generator Buffer Descriptors Control).............................................................272 Assignment in Different Buffering Modes.........245 U1PWRC (USB Power Control)................................257 Interrupts U1SOF (USB OTG Start-Of-Token and USB Transactions......................................249 Threshold, Host Mode).....................................262 Universal Serial Bus. See USB OTG. U1STAT (USB Status)..............................................258 USB On-The-Go (OTG)......................................................16 U1TOK (USB Token, Host Mode).............................261 USB OTG.........................................................................239 UxMODE (UARTx Mode)..........................................234 Buffer Descriptors and BDT......................................244 UxSTA (UARTx Status and Control).........................236 Device Mode Operation............................................249 WKDYHR (RTCC Weekday and Hours Value).........291 DMA Interface...........................................................245 YEAR (RTCC Year Value)........................................290 Hardware Resets Calculating BOR (Brown-out Reset)..............................................87 Transceiver Power Requirements............243 Clock Source Selection...............................................90 Hardware Configuration............................................241 CM (Configuration Mismatch Reset)...........................87 Device Mode.....................................................241 Delay Times................................................................91 External Interface.............................................243 Device Times..............................................................90 Host and OTG Modes.......................................242 IOPUWR (Illegal Opcode Reset)................................87 VBUS Voltage Generation.................................243 MCLR (Pin Reset).......................................................87 Host Mode Operation...............................................250 POR (Power-on Reset)...............................................87 Interrupts..................................................................248 RCON Flags Operation...............................................89 Operation..................................................................252 SFR States..................................................................90 Registers..................................................................254 SWR (RESET Instruction)...........................................87 VBUS Voltage Generation.........................................243 TRAPR (Trap Conflict Reset)......................................87 UWR (Uninitialized W Register Reset).......................87 WDT (Watchdog Timer Reset)....................................87  2010 Microchip Technology Inc. DS39969B-page 403

PIC24FJ256DA210 FAMILY V W Voltage Regulator (On-Chip).............................................354 Watchdog Timer (WDT)....................................................355 and BOR...................................................................355 Control Register........................................................356 Low Voltage Detection..............................................354 Windowed Operation................................................356 Standby Mode...........................................................355 WWW Address.................................................................405 WWW, On-Line Support.....................................................14 DS39969B-page 404  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. DS39969B-page 405

PIC24FJ256DA210 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC24FJ256DA210 Family Literature Number: DS39969B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39969B-page 406  2010 Microchip Technology Inc.

PIC24FJ256DA210 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 DA2 10 T - I / PT - XXX Examples: a) PIC24FJ128DA206-I/PT: Microchip Trademark PIC24F device with Graphics Controller and USB On-The-Go, 128-KB program memory, Architecture 96-KB data memory, 64-pin, Industrial temp., Flash Memory Family TQFP package. Program Memory Size (KB) b) PIC24FJ256DA110-I/PT: PIC24F device with Graphics Controller and Product Group USB On-The-Go, 256-KB program memory, Pin Count 24-KB data memory, 100-pin, Industrial temp., TQFP package. Tape and Reel Flag (if applicable) c) PIC24FJ256DA210-I/BG: Temperature Range PIC24F device with Graphics Controller and Package USB On-The-Go, 256-KB program memory, 96-KB data memory, 121-pin, Industrial temp., Pattern BGA package. Architecture 24 = 16-bit modified Harvard without DSP Flash Memory Family FJ = Flash program memory Product Group DA2= General purpose microcontrollers with Graphics Controller and USB On-The-Go Pin Count 06 = 64-pin 10 = 100-pin (TQFP)/121-pin (BGA) Temperature Range I = -40C to +85C (Industrial) Package PT = 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack) PT = 64-lead, TQFP (Thin Quad Flatpack) MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack, No Lead) BG = 121-pin BGA package Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2010 Microchip Technology Inc. DS39969B-page 407

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC24FJ128DA106-I/MR PIC24FJ128DA106-I/PT PIC24FJ128DA106T-I/MR PIC24FJ128DA106T-I/PT PIC24FJ128DA110-I/BG PIC24FJ128DA110-I/PT PIC24FJ128DA110T-I/BG PIC24FJ128DA110T-I/PT PIC24FJ128DA206-I/MR PIC24FJ128DA206-I/PT PIC24FJ128DA206T-I/MR PIC24FJ128DA206T-I/PT PIC24FJ128DA210-I/BG PIC24FJ128DA210-I/PT PIC24FJ128DA210T-I/BG PIC24FJ128DA210T-I/PT PIC24FJ256DA106-I/MR PIC24FJ256DA106-I/PT PIC24FJ256DA106T-I/MR PIC24FJ256DA106T-I/PT PIC24FJ256DA110-I/BG PIC24FJ256DA110-I/PT PIC24FJ256DA110T-I/BG PIC24FJ256DA110T-I/PT PIC24FJ256DA206-I/MR PIC24FJ256DA206-I/PT PIC24FJ256DA206T-I/MR PIC24FJ256DA206T-I/PT PIC24FJ256DA210-I/BG PIC24FJ256DA210-I/PT PIC24FJ256DA210T-I/BG PIC24FJ256DA210T-I/PT