PIC24F16KL402 FAMILY Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with XLP Technology Power Management Modes: Peripheral Features: • Run – CPU, Flash, SRAM and Peripherals On • High-Current Sink/Source (18mA/18mA) on All • Doze – CPU Clock Runs Slower than Peripherals I/O Pins • Idle – CPU Off, SRAM and Peripherals On • Configurable Open-Drain Outputs on Digital I/O Pins • Sleep – CPU, Flash and Peripherals Off and SRAM On • Up to Three External Interrupt Sources • Low-Power Consumption: • Two 16-Bit Timer/Counters with Selectable Clock - Run mode currents of 150 µA/MHz typical at 1.8V Sources - Idle mode currents under 80 µA/MHz at 1.8V • Up to Two 8-Bit Timers/Counters with Programmable Prescalers - Sleep mode currents as low as 30 nA at +25°C • Two Capture/Compare/PWM (CCP) modules: - Watchdog Timer as low as 210 nA at +25°C - Modules automatically configure and drive I/O High-Performance CPU: - 16-bit Capture with max. resolution 40ns - 16-bit Compare with max. resolution 83.3ns • Modified Harvard Architecture - 1-bit to 10-bit PWM resolution • Up to 16 MIPS Operation @ 32MHz • Up to One Enhanced CCP module: • 8MHz Internal Oscillator: - Backward compatible with CCP - 4x PLL option - 1, 2 or 4 PWM outputs - Multiple divide options - Programmable dead time • 17-Bit x 17-Bit Single-Cycle Hardware - Auto-shutdown on external event Fractional/integer Multiplier • Up to Two Master Synchronous Serial Port modules • 32-Bit by 16-Bit Hardware Divider (MSSPs) with Two Modes of Operation: • 16 x 16-Bit Working Register Array - 3-wire SPI (all four modes) • C Compiler Optimized Instruction Set - I2C™ Master, Multi-Master and Slave modes and Architecture (ISA): 7-Bit/10-Bit Addressing - 76 base instructions • Up to Two UART modules: - Flexible addressing modes - Supports RS-485, RS-232 and LIN/J2602 • Linear Program Memory Addressing - On-chip hardware encoder/decoder for IrDA® • Linear Data Memory Addressing - Auto-wake-up on Start bit • Two Address Generation Units (AGU) for Separate - Auto-Baud Detect (ABD) Read and Write Addressing of Data Memory - Two-byte transmit and receive FIFO buffers Memory Peripherals r e Device Pins P(rFbolyagtserahsm) (bDyatetas) E(EbDPyaRtetaOs )M 10-Bit A/D (ch) Comparators 8/16-Bit Timers CCP/ECCP MSSP ® UART w/IrDA Ultra Low-Pow Wake-up PIC24F16KL402 28 16K 1024 512 12 2 2/2 2/1 2 2 Y PIC24F08KL402 28 8K 1024 512 12 2 2/2 2/1 2 2 Y PIC24F16KL401 20 16K 1024 512 12 2 2/2 2/1 2 2 Y PIC24F08KL401 20 8K 1024 512 12 2 2/2 2/1 2 2 Y PIC24F08KL302 28 8K 1024 256 — 2 2/2 2/1 2 2 Y PIC24F08KL301 20 8K 1024 256 — 2 2/2 2/1 2 2 Y PIC24F08KL201 20 8K 512 — 12 1 1/2 2/0 1 1 Y PIC24F08KL200 14 8K 512 — 7 1 1/2 2/0 1 1 Y PIC24F04KL101 20 4K 512 — — 1 1/2 2/0 1 1 Y PIC24F04KL100 14 4K 512 — — 1 1/2 2/0 1 1 Y  2011-2013 Microchip Technology Inc. DS30001037C-page 1

PIC24F16KL402 FAMILY Analog Features: • Fail-Safe Clock Monitor (FSCM) Operation: - Detects clock failure and switches to on-chip, • 10-Bit, up to 12-Channel Analog-to-Digital (A/D) Low-Power RC (LPRC) oscillator Converter: • Power-on Reset (POR), Power-up Timer (PWRT) - 500ksps conversion rate and Oscillator Start-up Timer (OST) - Conversion available during Sleep and Idle • Flexible Watchdog Timer (WDT): • Dual Rail-to-Rail Analog Comparators with - Uses its own Low-Power RC oscillator Programmable Input/Output Configuration - Windowed operating modes • On-Chip Voltage Reference - Programmable period of 2ms to 131s Special Microcontroller Features: • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 Pins • Operating Voltage Range of 1.8V to 3.6V • Programmable High/Low-Voltage Detect (HLVD) • 10,000 Erase/Write Cycle Endurance Flash Program • Programmable Brown-out Reset (BOR): Memory, Typical - Configurable for software controlled operation and • 100,000 Erase/Write Cycle Endurance Data shutdown in Sleep mode EEPROM, Typical - Selectable trip points (1.8V, 2.7V and 3.0V) • Flash and Data EEPROM Data Retention: - Low-power 2.0V POR re-arm 40 Years Minimum • Self-Programmable under Software Control • Programmable Reference Clock Output DS30001037C-page 2  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Pin Diagrams: PIC24FXXKL302/402 28-Pin SPDIP/SSOP/SOIC(1) MCLR/VPP/RA5 1 28 VDD VREF+/CVREF+/AN0/SDA2/CN2/RA0 2 27 VSS PGED1/AN2/ULPWU/CC1IVNRDE/FC-/2VINREBF/-U/A2NTX1//CCNN34//RRAB10 34 (2)02402 2265 CANVR9E/TF3/ACNK1/R0/ECF1OO/USST/1F/LCTN01/I1N/RTB1/1C5N12/RB14 PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 5 3L 24 AN11/SDO1/CN13/RB13 AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2 6 KLXK 23 AN12/HLVDIN/SS2/CCP2/CN14/RB12 C1INA/C2INC/SCL2/CN7/RB3 7 XX 22 PGEC2/SCK1/P1C/CN15/RB11 VSS 8 FX4F 21 PGED2/SDI1/P1B/CN16/RB10 OSCI/AN13/CLKI/CN30/RA2 9 24C2 20 C2OUT/CCP1/P1A/INT2/CN8/RA6 SOOSSCCOI//AANN1145//CUL2KROTS/C/CNN291//RRAB34 1110 PICPI 1198 SSDDIA21/C/TC1PC3K//CUN19R/TRSA/7P1D/CN21/RB9 SOSCO/SCLKI/U2CTS/CN0/RA4 12 17 SCL1/U1CTS/CN22/RB8 VDD 13 16 U1TX/INT0/CN23/RB7 PGED3/ASDA1(2)/SCK2/CN27/RB5 14 15 PGEC3/ASCL1(2)/SDO2/CN24/RB6 28-Pin QFN(1) 4 1 B R 2/ CV-/V-/AN1/CN3/RA1REFREFV+/CV+/AN0/SDA2/CN2/RA0REFREFMCLR/ V/RA5PPVDDVSSAN9/T3CK/REFO/SS1/CN11/RB15CV/AN10/C1OUT/FLT0/INT1/CN1REF 28272625242322 PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/CN4/RB0 1 21 AN11/SDO1/CN13/RB13 PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 2 20 AN12/HLVDIN/SS2/CCP2/CN14/RB12 AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2 3 PIC24FXXKL302(2)19 PGEC2/SCK1/P1C/CN15/RB11 C1INA/C2INC/SCL2/CN7/RB3 4 18 PGED2/SDI1/P1B/CN16/RB10 PIC24FXXKL402 VSS 5 17 C2OUT/CCP1/P1A/INT2/CN8/RA6 OSCI/AN13/CLKI/CN30/RA2 6 16 SDI2/CCP3/CN9/RA7 OSCO/AN14/CLKO/CN29/RA3 7 15 SDA1/T1CK/U1RTS/P1D/CN21/RB9 8 91011121314 44D5678 BADBBBB RRVRRRR 1/0/ 7/4/3/2/ NN 2222 CC NNNN TS/TS/ 2/C2/C0/CS/C RC KOTT 22 CDNC SOSCI/AN15/USOSCO/SCLKI/U (2)GED3/ASDA1/S(2)GEC3/ASCL1/SU1TX/ISCL1/U1 PP Contact your Microchip sales team for Chip Scale Package (CSP) availability. Note 1: Analog features (indicated in red) are not available on PIC24FXXKL302 devices. 2: Alternate location for I2C™ functionality of MSSP1, as determined by the I2C1SEL Configuration bit.  2011-2013 Microchip Technology Inc. DS30001037C-page 3

PIC24F16KL402 FAMILY Pin Diagrams: PIC24FXXKL301/401 20-Pin PDIP/SSOP/SOIC(1) MCLR/VPP/RA5 1 20 VDD PGEC2P/GVREEDF2+//CCVVRREEFF-+/V/ARNEF0-//SADNA12/S/SDDOI22//CCNN23//RRAA10 23 (2)01401 1198 VASNS9/SCL2/T3CK/REFO/SCK2/CN11/RB15 PGED1/AN2/UPLGPEWCU1//ACN13IN/CD1/CIN2CIN/CB2/UIN2AT/XU/2PR1CX//CCNN54//RRBB10 45 KL3XKL 1176 CANVR11E/FS/ADNO110/P/S1DDI/1C/CN11O3/URTB/1F3LT0/INT1/CN12/RB14 PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4 6 XXFX 15 AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12 OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2 7 F4 14 C2OUT/CCP1/P1A/INT2/CN8/RA6 OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3 8 24C2 13 SDA1/T1CK/U1RTS/CCP3/CN21/RB9 PGED3/SOSCAIN/A4N/T135G/U/U2R1RTSX//CCNN16//RRBB24 910 PICPI 1121 SUC1TLX1//UIN1TC0T/CSN/S2S31/R/CBN722/RB8 0 20-Pin QFN(1) RA 2/ 1N AC O2/CN3/RDA2/SDI2/ DS 1/SN0/ NA V-/V-/AREFREF+/CV+/REFREF/RA5P CV P D2/C2/R/V PGEPGEMCLVDDVSS 2019181716 PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0 1 15 AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15 PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 2PIC24FXXKL301(2)14 CVREF/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14 AN4/T3G/U1RX/CN6/RB2 3 PIC24FXXKL401 13 AN11/SDO1/P1D/CN13/RB13 OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2 4 12 AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12 OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3 5 11 C2OUT/CCP1/P1A/INT2/CN8/RA6 6 7 8 910 44789 BABBB RRRRR 1/0/3/2/1/ NN222 CCNNN TS/TS/0/C1/C3/C RCTSP 22NSC SOSCI/AN15/UOSCO/SCLKI/UU1TX/ISCL1/U1CTS/T1CK/U1RTS/C ED3/C3/S DA1/ GE S PG P Note 1: Analog features (indicated in red) are not available on PIC24FXXKL301 devices. 2: Alternate location for I2C™ functionality of MSSP1, as determined by the I2C1SEL Configuration bit. DS30001037C-page 4  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Pin Diagrams: PIC24FXXKL10X/20X 20-Pin QFN(1) 1A0 AR 3/RN2/ NC 1/CN0/ NA CV-/V-/AREFREFV+/CV+/REFREFPP/RA5 D2/C2/R/V EELDS GGCDS PPMVV 2019181716 PGED1/AN2/ULPWU/C1IND/CN4/RB0 1 15 AN9/T3CK/REFO/CN11/RB15 PGEC1/AN3/C1INC/CN5/RB1 2 PIC24FXXKL101(2)14 CVREF/AN10/SDI1/C1OUT/INT1/CN12/RB14 AN4/T3G/U1RX/CN6/RB2 3 13 AN11/SDO1/CN13/RB13 PIC24FXXKL201 OSCI/AN13/C1INB/CLKI/CN30/RA2 4 12 AN12/HLVDIN/SCK1/CCP2/CN14/RB12 OSCO/AN14/C1INA/CLKO/CN29/RA3 5 11 CCP1/INT2/CN8/RA6 6 7 8 910 44789 BABBB RRRRR 1/0/3/2/1/ NN222 CCNNN ED3/SOSCI/AN15/C3/SOSCO/SCLKI/U1TX/INT0/CCL1/U1CTS/SS1/CA1/T1CK/U1RTS/C GE SD PG S P 20-Pin PDIP/SSOP/SOIC(1) MCLR/VPP/RA5 1 20 VDD PPGGEECD22/V/CREVFR+E/FC-/VVRREEFF+-//AANN01//CCNN23//RRAA01 23 (2)01201 1198 VANSS9/T3CK/REFO/CN11/RB15 PGED1/APNG2E/UCL1P/AWNU3//CC11IINNDC//CCNN45//RRBB10 45 KL1XKL 1176 CANVR11E/FS/ADNO110/C/SND1I13//CR1BO13UT/INT1/CN12/RB14 AN4/T3G/U1RX/CN6/RB2 6 XXFX 15 AN12/HLVDIN/SCK1/CCP2/CN14/RB12 OSCI/AN13/C1INB/CLKI/CN30/RA2 7 F4 14 CCP1/INT2/CN8/RA6 OSCO/AN14/C1INA/CLKO/CN29/RA3 8 24C2 13 SDA1/T1CK/U1RTS/CN21/RB9 PGED3/SOSCI/AN15/CN1/RB4 9 PICPI 12 SCL1/U1CTS/SS1/CN22/RB8 PGEC3/SOSCO/SCLKI/CN0/RA4 10 11 U1TX/INT0/CN23/RB7 14-Pin PDIP/TSSOP(1) PGEC2/VREF+/CVREF+M/ACNL0R//CVNPP2//RRAA50 12 (2)000 1143 VVDSSD 02 PGED2/CVREF-/VREF-/AN1/ULPWU/CN3/RA1 3 L1KL 12 AN9/T3CK/REFO/U1RX/SS1/INT0/CN11/RB15 OSCI/AN13/C1INB/CLKI/CN30/RA2 4 XKXX 11 CVREF/AN10/T3G/U1TX/SDI1/C1OUT/INT1/CN12/RB14 OSCO/AN14/C1INA/CLKO/CN29/RA3 5 XF 10 CCP1/INT2/CN8/RA6 F4 PGED3/SOSCI/AN15/HLVDIN/CN1/RB4 6 24C2 9 SDA1/T1CK/U1RTS/SDO1/CCP2/CN21/RB9 PGEC3/SOSCO/SCLKI/CN0/RA4 7 PICPI 8 SCL1/U1CTS/SCK1/CN22/RB8 Note 1: Analog features (indicated in red) are not available on PIC24FXXKL100/101 devices. 2: Alternate location for I2C™ functionality of MSSP1, as determined by the I2C1SEL Configuration bit.  2011-2013 Microchip Technology Inc. DS30001037C-page 5

PIC24F16KL402 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................21 3.0 CPU ...........................................................................................................................................................................................25 4.0 Memory Organization.................................................................................................................................................................31 5.0 Flash Program Memory..............................................................................................................................................................47 6.0 Data EEPROM Memory.............................................................................................................................................................53 7.0 Resets........................................................................................................................................................................................59 8.0 Interrupt Controller.....................................................................................................................................................................65 9.0 Oscillator Configuration..............................................................................................................................................................95 10.0 Power-Saving Features............................................................................................................................................................105 11.0 I/O Ports...................................................................................................................................................................................111 12.0 Timer1 .....................................................................................................................................................................................115 13.0 Timer2 Module.........................................................................................................................................................................117 14.0 Timer3 Module.........................................................................................................................................................................119 15.0 Timer4 Module.........................................................................................................................................................................123 16.0 Capture/Compare/PWM (CCP) and Enhanced CCP Modules.................................................................................................125 17.0 Master Synchronous Serial Port (MSSP).................................................................................................................................135 18.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................149 19.0 10-Bit High-Speed A/D Converter............................................................................................................................................157 20.0 Comparator Module..................................................................................................................................................................167 21.0 Comparator Voltage Reference................................................................................................................................................171 22.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................173 23.0 Special Features......................................................................................................................................................................175 24.0 Development Support...............................................................................................................................................................187 25.0 Instruction Set Summary..........................................................................................................................................................191 26.0 Electrical Characteristics..........................................................................................................................................................199 27.0 Packaging Information..............................................................................................................................................................225 Appendix A: Revision History.............................................................................................................................................................251 Appendix B: Migrating from PIC18/PIC24 to PIC24F16KL402..........................................................................................................251 Index..................................................................................................................................................................................................253 The Microchip Web Site.....................................................................................................................................................................257 Customer Change Notification Service..............................................................................................................................................257 Customer Support..............................................................................................................................................................................257 Product Identification System.............................................................................................................................................................259 DS30001037C-page 6  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011-2013 Microchip Technology Inc. DS30001037C-page 7

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 8  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 1.0 DEVICE OVERVIEW • Doze Mode Operation: When timing-sensitive applications, such as serial communications, This document contains device-specific information for require the uninterrupted operation of peripherals, the following devices: the CPU clock speed can be selectively reduced, allowing incremental power savings without • PIC24F04KL100 • PIC24F04KL101 missing a beat. • PIC24F08KL200 • PIC24F08KL201 • Instruction-Based Power-Saving Modes: The • PIC24F08KL301 • PIC24F08KL302 microcontroller can suspend all operations, or • PIC24F08KL401 • PIC24F16KL401 selectively shut down its core while leaving its • PIC24F08KL402 • PIC24F16KL402 peripherals active, with a single instruction in software. The PIC24F16KL402 family adds an entire range of economical, low pin count and low-power devices to 1.1.3 OSCILLATOR OPTIONS AND Microchip’s portfolio of 16-bit microcontrollers. Aimed FEATURES at applications that require low-power consumption but The PIC24F16KL402 family offers five different more computational ability than an 8-bit platform can oscillator options, allowing users a range of choices in provide, these devices offer a range of tailored developing application hardware. These include: peripheral sets that allow the designer to optimize both price point and features with no sacrifice of • Two Crystal modes using crystals or ceramic functionality. resonators. • Two External Clock modes offering the option of a 1.1 Core Features divide-by-2 clock output. • Two Fast Internal Oscillators (FRCs): One with a 1.1.1 16-BIT ARCHITECTURE nominal 8 MHz output and the other with a Central to all PIC24F devices is the 16-bit modified nominal 500 kHz output. These outputs can also Harvard architecture, first introduced with Microchip’s be divided under software control to provide clock dsPIC® digital signal controllers. The PIC24F CPU core speed as low as 31 kHz or 2 kHz. offers a wide range of enhancements, such as: • A Phase Locked Loop (PLL) frequency multiplier, available to the External Oscillator modes and the • 16-bit data and 24-bit address paths with the 8 MHz FRC Oscillator, which allows clock speeds ability to move information between data and of up to 32 MHz. memory spaces • A separate Internal RC Oscillator (LPRC) with a • Linear addressing of up to 12Mbytes (program fixed 31 kHz output, which provides a low-power space) and 64Kbytes (data) option for timing-insensitive applications. • A 16-element Working register array with built-in software stack support The internal oscillator block also provides a stable • A 17 x 17 hardware multiplier with support for reference source for the Fail-Safe Clock Monitor integer math (FSCM). This option constantly monitors the main clock • Hardware support for 32-bit by 16-bit division source against a reference signal provided by the internal oscillator and enables the controller to switch to • An instruction set that supports multiple the internal oscillator, allowing for continued low-speed addressing modes and is optimized for high-level operation or a safe application shutdown. languages, such as C • Operational performance up to 16 MIPS 1.1.4 EASY MIGRATION 1.1.2 POWER-SAVING TECHNOLOGY The consistent pinout scheme used throughout the entire family also helps in migrating to the next larger All of the devices in the PIC24F16KL402 family device. This is true when moving between devices with incorporate a range of features that can significantly the same pin count, or even jumping from 20-pin or reduce power consumption during operation. Key 28-pin devices to 44-pin/48-pin devices. features include: The PIC24F family is pin compatible with devices in the • On-the-Fly Clock Switching: The device clock dsPIC33 family, and shares some compatibility with the can be changed under software control to the pinout schema for PIC18 and dsPIC30. This extends Timer1 source, or the internal, Low-Power RC the ability of applications to grow, from the relatively (LPRC) oscillator during operation, allowing the simple, to the powerful and complex. user to incorporate power-saving ideas into their software designs.  2011-2013 Microchip Technology Inc. DS30001037C-page 9

PIC24F16KL402 FAMILY 1.2 Other Special Features 1.3 Details on Individual Family Members • Communications: The PIC24F16KL402 family incorporates multiple serial communication Devices in the PIC24F16KL402 family are available in peripherals to handle a range of application 14-pin, 20-pin and 28-pin packages. The general block requirements. The MSSP module implements diagram for all devices is shown in Figure1-1. both SPI and I2C™ protocols, and supports both The PIC24F16KL402 family may be thought of as four Master and Slave modes of operation for each. different device groups, each offering a slightly different Devices also include one of two UARTs with built-in IrDA® encoders/decoders. set of features. These differ from each other in multiple ways: • Analog Features: Select members of the PIC24F16KL402 family include a 10-bit A/D • The size of the Flash program memory Converter module. The A/D module incorporates • The presence and size of data EEPROM programmable acquisition time, allowing for a • The presence of an A/D Converter and the channel to be selected and a conversion to be number of external analog channels available initiated without waiting for a sampling period, as • The number of analog comparators well as faster sampling speeds. • The number of general purpose timers The comparator modules are configurable for a • The number and type of CCP modules wide range of operations and can be used as (i.e., CCP vs. ECCP) either a single or double comparator module. • The number of serial communications modules (both MSSPs and UARTs) The general differences between the different sub-families are shown in Table1-1. The feature sets for specific devices are summarized in Table1-2 and Table1-3. A list of the individual pin features available on the PIC24F16KL402 family devices, sorted by function, is provided in Table1-4 (for PIC24FXXKL40X/30X devices) and Table1-5 (for PIC24FXXKL20X/10X devices). Note that these tables show the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of this data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. TABLE 1-1: FEATURE COMPARISON FOR PIC24F16KL402 FAMILY GROUPS Program Data Serial Timers CCP and A/D Device Group Memory EEPROM (MSSP/ Comparators (8/16-bit) ECCP (channels) (bytes) (bytes) UART) PIC24FXXKL10X 4K — 1/2 2/0 1/1 — 1 PIC24FXXKL20X 8K — 1/2 2/0 1/1 7 or 12 1 PIC24FXXKL30X 8K 256 2/2 2/1 2/2 — 2 PIC24FXXKL40X 8K or 16K 512 2/2 2/1 2/2 12 2 DS30001037C-page 10  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 1-2: DEVICE FEATURES FOR PIC24F16KL40X/30X DEVICES 2 2 2 1 1 1 0 0 0 0 0 0 4 4 3 4 4 3 L L L L L L K K K K K K Features 16 08 08 16 08 08 F F F F F F 4 4 4 4 4 4 2 2 2 2 2 2 C C C C C C PI PI PI PI PI PI Operating Frequency DC – 32 MHz Program Memory (bytes) 16K 8K 8K 16K 8K 8K Program Memory (instructions) 5632 2816 2816 5632 2816 2816 Data Memory (bytes) 1024 1024 1024 1024 1024 1024 Data EEPROM Memory (bytes) 512 512 256 512 512 256 Interrupt Sources 31 (27/4) 31 (27/4) 30 (26/4) 31 (27/4) 31 (27/4) 30 (26/4) (soft vectors/NMI traps) I/O Ports PORTA<7:0> PORTA<6:0> PORTB<15:0> PORTB<15:12,9:7,4,2:0> Total I/O Pins 24 18 Timers (8/16-bit) 2/2 2/2 2/2 2/2 2/2 2/2 Capture/Compare/PWM modules: Total 3 3 3 3 3 3 Enhanced CCP 1 1 1 1 1 1 Input Change Notification Interrupt 23 23 23 17 17 17 Serial Communications: UART 2 2 2 2 2 2 MSSP 2 2 2 2 2 2 10-Bit Analog-to-Digital Module 12 12 — 12 12 — (input channels) Analog Comparators 2 2 2 2 2 2 Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 28-Pin SPDIP/SSOP/SOIC/QFN 20-Pin PDIP/SSOP/SOIC/QFN  2011-2013 Microchip Technology Inc. DS30001037C-page 11

PIC24F16KL402 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24F16KL20X/10X DEVICES 1 1 0 0 0 0 0 0 2 1 2 1 L L L L K K K K Features 08 04 08 04 F F F F 4 4 4 4 2 2 2 2 C C C C PI PI PI PI Operating Frequency DC – 32 MHz Program Memory (bytes) 8K 4K 8K 4K Program Memory (instructions) 2816 1408 2816 1408 Data Memory (bytes) 512 512 512 512 Data EEPROM Memory (bytes) — — — — Interrupt Sources 27 (23/4) 26 (22/4) 27 (23/4) 26 (22/4) (soft vectors/NMI traps) I/O Ports PORTA<6:0> PORTA<5:0> PORTB<15:12,9:7,4,2:0> PORTB<15:14,9:8,4,0> Total I/O Pins 17 12 Timers (8/16-bit) 1/2 1/2 1/2 1/2 Capture/Compare/PWM modules: Total 2 2 2 2 Enhanced CCP 0 0 0 0 Input Change Notification Interrupt 17 17 11 11 Serial Communications: UART 1 1 1 1 MSSP 1 1 1 1 10-Bit Analog-to-Digital Module 12 — 7 — (input channels) Analog Comparators 1 1 1 1 Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 20-Pin PDIP/SSOP/SOIC/QFN 14-Pin PDIP/TSSOP DS30001037C-page 12  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 1-1: PIC24F16KL402 FAMILY GENERAL BLOCK DIAGRAM Interrupt Data Bus Controller 16 8 16 16 PSV and Table Data Latch Data Access Control Block PCH PCL DataRAM 23 Program Counter Address Stack Repeat Latch PORTA(1) Control Control Logic Logic RA<0:7> 16 23 16 Address Latch Read AGU Write AGU Program Memory Data EEPROM Data Latch 16 Address Bus EA MUX a 24 Dat 16 16 al Inst Latch Liter PORTB(1) Inst Register RB<0:15> Instruction Decode and Control Divide Control Signals Support 16 x 16 17x17 W Reg Array OSCO/CLKO Timing Power-up Multiplier OSCI/CLKI Generation Timer Oscillator FRC/LPRC Start-up Timer Oscillators Power-on 16-Bit ALU Reset 16 Watchdog Timer Precision Band Gap BOR Reference ULPWU VDD, MCLRULPWU VSS 10-Bit Timer1 Timer2 Timer3 Timer4 Comparators A/D ECCCCPP11(/1) CCP2 CCP3(1) M1/S2S(1P) U1A/2R(1T) CN1-23(1) HLVD Note 1: All pins or features are not implemented on all device pinout configurations. See Table1-4 and Table1-5 for I/O port pin descriptions.  2011-2013 Microchip Technology Inc. DS30001037C-page 13

PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin 28-Pin Function I/O Buffer Description PDIP/ 20-Pin SPDIP/ 28-Pin SSOP/ QFN SSOP/ QFN SOIC SOIC AN0 2 19 2 27 I ANA A/D Analog Inputs. Not available on PIC24F16KL30X AN1 3 20 3 28 I ANA family devices. AN2 4 1 4 1 I ANA AN3 5 2 5 2 I ANA AN4 6 3 6 3 I ANA AN5 — — 7 4 I ANA AN9 18 15 26 23 I ANA AN10 17 14 25 22 I ANA AN11 16 13 24 21 I ANA AN12 15 12 23 20 I ANA AN13 7 4 9 6 I ANA AN14 8 5 10 7 I ANA AN15 9 6 11 8 I ANA ASCL1 — — 15 12 I/O I2C™ Alternate MSSP1 I2C Clock Input/Output ASDA1 — — 14 11 I/O I2C Alternate MSSP1 I2C Data Input/Output AVDD 20 17 28 25 I ANA Positive Supply for Analog modules AVSS 19 16 27 24 I ANA Ground Reference for Analog modules CCP1 14 11 20 17 I/O ST CCP1/ECCP1 Capture Input/Compare and PWM Output CCP2 15 12 23 20 I/O ST CCP2 Capture Input/Compare and PWM Output CCP3 13 10 19 16 I/O ST CCP3 Capture Input/Compare and PWM Output C1INA 8 5 7 4 I ANA Comparator 1 Input A (+) C1INB 7 4 6 3 I ANA Comparator 1 Input B (-) C1INC 5 2 5 2 I ANA Comparator 1 Input C (+) C1IND 4 1 4 1 I ANA Comparator 1 Input D (-) C1OUT 17 14 25 22 O — Comparator 1 Output C2INA 5 2 5 2 I ANA Comparator 2 Input A (+) C2INB 4 1 4 1 I ANA Comparator 2 Input B (-) C2INC 8 5 7 4 I ANA Comparator 2 Input C (+) C2IND 7 4 6 3 I ANA Comparator 2 Input D (-) C2OUT 14 11 20 17 O — Comparator 2 Output CLK I 7 4 9 6 I ANA Main Clock Input CLKO 8 5 10 7 O — System Clock Output Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C = I2C™/SMBus input buffer DS30001037C-page 14  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin 28-Pin Function I/O Buffer Description PDIP/ 20-Pin SPDIP/ 28-Pin SSOP/ QFN SSOP/ QFN SOIC SOIC CN0 10 7 12 9 I ST Interrupt-on-Change Inputs CN1 9 6 11 8 I ST CN2 2 19 2 27 I ST CN3 3 20 3 28 I ST CN4 4 1 4 1 I ST CN5 5 2 5 2 I ST CN6 6 3 6 3 I ST CN7 — — 7 4 I ST CN8 14 11 20 17 I ST CN9 — — 19 16 I ST CN11 18 15 26 23 I ST CN12 17 14 25 22 I ST CN13 16 13 24 21 I ST CN14 15 12 23 20 I ST CN15 — — 22 19 I ST CN16 — — 21 18 I ST CN21 13 10 18 15 I ST CN22 12 9 17 14 I ST CN23 11 8 16 13 I ST CN24 — — 15 12 I ST CN27 — — 14 11 I ST CN29 8 5 10 7 I ST CN30 7 4 9 6 I ST CVREF 17 14 25 22 I ANA Comparator Voltage Reference Output CVREF+ 2 19 2 27 I ANA Comparator Reference Positive Input Voltage CVREF- 3 20 3 28 I ANA Comparator Reference Negative Input Voltage FLT0 17 14 25 22 I ST ECCP1 Enhanced PWM Fault Input HLVDIN 15 12 23 20 I ST High/Low-Voltage Detect Input INT0 11 8 16 13 I ST Interrupt 0 Input INT1 17 14 25 22 I ST Interrupt 1 Input INT2 14 11 20 17 I ST Interrupt 2 Input MCLR 1 18 1 26 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 7 4 9 6 I ANA Main Oscillator Input OSCO 8 5 10 7 O ANA Main Oscillator Output P1A 14 11 20 17 O — ECCP1 Output A (Enhanced PWM Mode) P1B 5 2 21 18 O — ECCP1 Output B (Enhanced PWM Mode) P1C 4 1 22 19 O — ECCP1 Output C (Enhanced PWM Mode) P1D 16 13 18 15 O — ECCP1 Output D (Enhanced PWM Mode) Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C = I2C™/SMBus input buffer  2011-2013 Microchip Technology Inc. DS30001037C-page 15

PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin 28-Pin Function I/O Buffer Description PDIP/ 20-Pin SPDIP/ 28-Pin SSOP/ QFN SSOP/ QFN SOIC SOIC PGEC1 5 2 5 2 I/O ST ICSP™ Clock 1 PCED1 4 1 4 1 I/O ST ICSP Data 1 PGEC2 2 19 22 19 I/O ST ICSP Clock 2 PGED2 3 20 21 18 I/O ST ICSP Data 2 PGEC3 10 7 15 12 I/O ST ICSP Clock 3 PGED3 9 6 14 11 I/O ST ICSP Data 3 RA0 2 19 2 27 I/O ST PORTA Pins RA1 3 20 3 28 I/O ST RA2 7 4 9 6 I/O ST RA3 8 5 10 7 I/O ST RA4 10 7 12 9 I/O ST RA5 1 18 1 26 I ST RA6 14 11 20 17 I/O ST RA7 — — 19 16 I/O ST RB0 4 1 4 1 I/O ST PORTB Pins RB1 5 2 5 2 I/O ST RB2 6 3 6 3 I/O ST RB3 — — 7 4 I/O ST RB4 9 6 11 8 I/O ST RB5 — — 14 11 I/O ST RB6 — — 15 12 I/O ST RB7 11 8 16 13 I/O ST RB8 12 9 17 14 I/O ST RB9 13 10 18 15 I/O ST RB10 — — 21 18 I/O ST RB11 — — 22 19 I/O ST RB12 15 12 23 20 I/O ST RB13 16 13 24 21 I/O ST RB14 17 14 25 22 I/O ST RB15 18 15 26 23 I/O ST REFO 18 15 26 23 O — Reference Clock Output SCK1 15 12 22 19 I/O ST MSSP1 SPI Serial Input/Output Clock SCK2 18 15 14 11 I/O ST MSSP2 SPI Serial Input/Output Clock SCL1 12 9 17 14 I/O I2C MSSP1 I2C Clock Input/Output SCL2 18 15 7 4 I/O I2C MSSP2 I2C Clock Input/Output SCLKI 10 7 12 9 I ST Digital Secondary Clock Input SDA1 13 10 18 15 I/O I2C MSSP1 I2C Data Input/Output SDA2 2 19 2 27 I/O I2C MSSP2 I2C Data Input/Output SDI1 17 14 21 18 I ST MSSP1 SPI Serial Data Input SDI2 2 19 19 16 I ST MSSP2 SPI Serial Data Input SDO1 16 13 24 21 O — MSSP1 SPI Serial Data Output SDO2 3 20 15 12 O — MSSP2 SPI Serial Data Output Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C = I2C™/SMBus input buffer DS30001037C-page 16  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin 28-Pin Function I/O Buffer Description PDIP/ 20-Pin SPDIP/ 28-Pin SSOP/ QFN SSOP/ QFN SOIC SOIC SOSCI 9 6 11 8 I ANA Secondary Oscillator Input SOSCO 10 7 12 9 O ANA Secondary Oscillator Output SS1 12 9 26 23 O — SPI1 Slave Select SS2 15 12 23 20 O — SPI2 Slave Select T1CK 13 10 18 15 I ST Timer1 Clock T3CK 18 15 26 23 I ST Timer3 Clock T3G 6 3 6 3 I ST Timer3 External Gate Input U1CTS 12 9 17 14 I ST UART1 Clear-to-Send Input U1RTS 13 10 18 15 O — UART1 Request-to-Send Output U1RX 6 3 6 3 I ST UART1 Receive U1TX 11 8 16 13 O — UART1 Transmit U2CTS 10 7 12 9 I ST UART2 Clear-to-Send Input U2RTS 9 6 11 8 O — UART2 Request-to-Send Output U2RX 5 2 5 2 I ST UART2 Receive U2TX 4 1 4 1 O — UART2 Transmit ULPWU 4 1 4 1 I ANA Ultra Low-Power Wake-up Input VDD 20 17 13, 28 10, 25 P — Positive Supply for Peripheral Digital Logic and I/O Pins VREF+ 2 19 2 27 I ANA A/D Reference Voltage Input (+) VREF- 3 20 3 28 I ANA A/D Reference Voltage Input (-) VSS 19 16 8, 27 5, 24 P — Ground Reference for Logic and I/O Pins Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C = I2C™/SMBus input buffer  2011-2013 Microchip Technology Inc. DS30001037C-page 17

PIC24F16KL402 FAMILY TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin Function 14-Pin I/O Buffer Description PDIP/ 20-Pin PDIP/ SSOP/ QFN TSSOP SOIC AN0 2 19 2 I ANA A/D Analog Inputs. Not available on PIC24F16KL10X family devices. AN1 3 20 3 I ANA AN2 4 1 — I ANA AN3 5 2 — I ANA AN4 6 3 — I ANA AN9 18 15 12 I ANA AN10 17 14 11 I ANA AN11 16 13 — I ANA AN12 15 12 — I ANA AN13 7 4 4 I ANA AN14 8 5 5 I ANA AN15 9 6 6 I ANA AVDD 20 17 14 I ANA Positive Supply for Analog modules AVSS 19 16 13 I ANA Ground Reference for Analog modules CCP1 14 11 10 I/O ST CCP1 Capture Input/Compare and PWM Output CCP2 15 12 9 I/O ST CCP2 Capture Input/Compare and PWM Output C1INA 8 5 5 I ANA Comparator 1 Input A (+) C1INB 7 4 4 I ANA Comparator 1 Input B (-) C1INC 5 2 — I ANA Comparator 1 Input C (+) C1IND 4 1 — I ANA Comparator 1 Input D (-) C1OUT 17 14 11 O — Comparator 1 Output CLK I 7 4 9 I ANA Main Clock Input CLKO 8 5 10 O — System Clock Output CN0 10 7 7 I ST Interrupt-on-Change Inputs CN1 9 6 6 I ST CN2 2 19 2 I ST CN3 3 20 3 I ST CN4 4 1 — I ST CN5 5 2 — I ST CN6 6 3 — I ST CN8 14 11 10 I ST CN9 — — — I ST CN11 18 15 12 I ST CN12 17 14 11 I ST CN13 16 13 — I ST CN14 15 12 — I ST CN21 13 10 9 I ST CN22 12 9 8 I ST CN23 11 8 — I ST CN29 8 5 5 I ST CN30 7 4 4 I ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C = I2C™/SMBus input buffer DS30001037C-page 18  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin Function 14-Pin I/O Buffer Description PDIP/ 20-Pin PDIP/ SSOP/ QFN TSSOP SOIC CVREF 17 14 11 I ANA Comparator Voltage Reference Output CVREF+ 2 19 2 I ANA Comparator Reference Positive Input Voltage CVREF- 3 20 3 I ANA Comparator Reference Negative Input Voltage HLVDIN 15 12 6 I ST High/Low-Voltage Detect Input INT0 11 8 12 I ST Interrupt 0 Input INT1 17 14 11 I ST Interrupt 1 Input INT2 14 11 10 I ST Interrupt 2 Input MCLR 1 18 1 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 7 4 4 I ANA Main Oscillator Input OSCO 8 5 5 O ANA Main Oscillator Output PGEC1 5 2 — I/O ST ICSP™ Clock 1 PCED1 4 1 — I/O ST ICSP Data 1 PGEC2 2 19 2 I/O ST ICSP Clock 2 PGED2 3 20 3 I/O ST ICSP Data 2 PGEC3 10 7 7 I/O ST ICSP Clock 3 PGED3 9 6 6 I/O ST ICSP Data 3 RA0 2 19 2 I/O ST PORTA Pins RA1 3 20 3 I/O ST RA2 7 4 4 I/O ST RA3 8 5 5 I/O ST RA4 10 7 7 I/O ST RA5 1 18 1 I ST RA6 14 11 10 I/O ST RB0 4 1 — I/O ST PORTB Pins RB1 5 2 — I/O ST RB2 6 3 — I/O ST RB4 9 6 6 I/O ST RB7 11 8 — I/O ST RB8 12 9 8 I/O ST RB9 13 10 9 I/O ST RB12 15 12 — I/O ST RB13 16 13 — I/O ST RB14 17 14 11 I/O ST RB15 18 15 12 I/O ST REFO 18 15 12 O — Reference Clock Output Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C = I2C™/SMBus input buffer  2011-2013 Microchip Technology Inc. DS30001037C-page 19

PIC24F16KL402 FAMILY TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin Function 14-Pin I/O Buffer Description PDIP/ 20-Pin PDIP/ SSOP/ QFN TSSOP SOIC SCK1 15 12 8 I/O ST MSSP1 SPI Serial Input/Output Clock SCL1 12 9 8 I/O I2C MSSP1 I2C Clock Input/Output SCLKI 10 7 12 I ST Digital Secondary Clock Input SDA1 13 10 9 I/O I2C MSSP1 I2C Data Input/Output SDI1 17 14 11 I ST MSSP1 SPI Serial Data Input SDO1 16 13 9 O — MSSP1 SPI Serial Data Output SOSCI 9 6 11 I ANA Secondary Oscillator Input SOSCO 10 7 12 O ANA Secondary Oscillator Output SS1 12 9 12 O — SPI1 Slave Select T1CK 13 10 9 I ST Timer1 Clock T3CK 18 15 12 I ST Timer3 Clock T3G 6 3 11 I ST Timer3 External Gate Input U1CTS 12 9 8 I ST UART1 Clear-to-Send Input U1RTS 13 10 9 O — UART1 Request-to-Send Output U1RX 6 3 12 I ST UART1 Receive U1TX 11 8 11 O — UART1 Transmit ULPWU 3 1 3 I ANA Ultra Low-Power Wake-up Input VDD 20 17 14 P — Positive Supply for Peripheral Digital Logic and I/O Pins VREF+ 2 19 2 I ANA A/D Reference Voltage Input (+) VREF- 3 20 3 I ANA A/D Reference Voltage Input (-) VSS 19 16 13 P — Ground Reference for Logic and I/O Pins Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C = I2C™/SMBus input buffer DS30001037C-page 20  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH 16-BIT MINIMUM CONNECTIONS MICROCONTROLLERS C2(1) 2.1 Basic Connection Requirements VDD Getting started with the PIC24F16KL402 family of R1 DD SS 16-bit microcontrollers requires attention to a minimal V V R2 set of device pin connections before proceeding with MCLR development. C1 The following pins must always be connected: PIC24FXXKLXXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(1) C3(1) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(1) C4(1) These pins must also be connected if they are being used in the end application: • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes Key (all values are recommendations): (see Section2.4 “ICSP Pins”) C1 through C6: 0.1 F, 20V ceramic • OSCI and OSCO pins when an external oscillator R1: 10 kΩ source is used R2: 100Ω to 470Ω (see Section2.5 “External Oscillator Pins”) Note 1: The example shown is for a PIC24F device Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; • VREF+/VREF- pins are used when external voltage adjust the number of decoupling capacitors reference for analog modules is implemented appropriately. Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2011-2013 Microchip Technology Inc. DS30001037C-page 21

PIC24F16KL402 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: Device Reset, and Device Programming The use of decoupling capacitors on every pair of and Debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 F (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented, depending on the should be a low-ESR device, with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1F in parallel with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC24FXXKXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R110k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10k. Ensure that the On boards with power traces running longer than MCLR pin VIH and VIL specifications are met. sixinches in length, it is suggested to use a tank capac- 2: R2470 will limit any current flowing into itor for integrated circuits, including microcontrollers, to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS30001037C-page 22  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 2.4 ICSP Pins FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR The PGC and PGD pins are used for In-Circuit Serial CIRCUIT Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the Single-Sided and In-Line Layouts: ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to Copper Pour Primary Oscillator (tied to ground) Crystal experience an ESD event, a series resistor is recom- mended, with the value in the range of a few tens of DEVICE PINS ohms, not to exceed 100Ω. Pull-up resistors, series diodes and capacitors on the PGC and PGD pins are not recommended as they will Primary OSC1 Oscillator interfere with the programmer/debugger communica- tions to the device. If such discrete components are an C1 ` OSC2 application requirement, they should be removed from C2 GND the circuit during programming and debugging. Alter- ` natively, refer to the AC/DC characteristics and timing T1OSO requirements information in the respective device Flash programming specification for information on T1OS I capacitive loading limits, and pin Input Voltage High Timer1 Oscillator Crystal (VIH) and Input Voltage Low (VIL) requirements. ` For device emulation, ensure that the “Communication Channel Select” (i.e., PGCx/PGDx) pins, programmed T1 Oscillator: C1 T1 Oscillator: C2 into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip Fine-Pitch (Dual-Sided) Layouts: development tools connection requirements, refer to Section24.0 “Development Support”. Top Layer Copper Pour (tied to ground) 2.5 External Oscillator Pins Bottom Layer Copper Pour Many microcontrollers have options for at least two (tied to ground) oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to OSCO Section9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same C2 side of the board as the device. Place the oscillator Oscillator circuit close to the respective oscillator pins with no GND Crystal more than 0.5inch (12mm) between the circuit C1 components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side OSCI of the board. Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power DEVICE PINS traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board In planning the application’s routing and I/O assign- where the crystal is placed. ments, ensure that adjacent port pins and other Layout suggestions are shown in Figure2-3. In-line signals, in close proximity to the oscillator, are benign packages may be handled with a single-sided layout (i.e., free of high frequencies, short rise and fall times, that completely encompasses the oscillator pins. With and other similar noise). fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground.  2011-2013 Microchip Technology Inc. DS30001037C-page 23

PIC24F16KL402 FAMILY For additional information and design guidance on 2.6 Unused I/Os oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site Unused I/O pins should be configured as outputs and (www.microchip.com): driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the • AN826, “Crystal Oscillator Basics and Crystal output to logic low. Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” DS30001037C-page 24  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 3.0 CPU For most instructions, the core is capable of executing a data (or program data) memory read, a Working Note: This data sheet summarizes the features register (data) read, a data memory write and a of this group of PIC24F devices. It is not program (instruction) memory read per instruction intended to be a comprehensive refer- cycle. As a result, three parameter instructions can be ence source. For more information on the supported, allowing trinary operations (i.e., A+B = C) CPU, refer to the “dsPIC33/PIC24 Family to be executed in a single cycle. Reference Manual”, “CPU” (DS39703). A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic The PIC24F CPU has a 16-bit (data) modified Harvard capability and throughput. The multiplier supports architecture with an enhanced instruction set and a Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 24-bit instruction word with a variable length opcode 8-bit by 8-bit integer multiplication. All multiply field. The Program Counter (PC) is 23 bits wide and instructions execute in a single cycle. addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch The 16-bit ALU has been enhanced with integer divide mechanism is used to help maintain throughput and assist hardware that supports an iterative non-restoring provides predictable execution. All instructions execute divide algorithm. It operates in conjunction with the in a single cycle, with the exception of instructions that REPEAT instruction looping mechanism and a selection change the program flow, the double-word move of iterative divide instructions to support 32-bit (or (MOV.D) instruction and the table instructions. 16-bit), divided by a 16-bit integer signed and unsigned Overhead-free program loop constructs are supported division. All divide operations require 19 cycles to using the REPEAT instructions, which are interruptible complete, but are interruptible at any cycle boundary. at any point. The PIC24F has a vectored exception scheme, with up PIC24F devices have sixteen, 16-bit Working registers to eight sources of non-maskable traps and up to in the programmer’s model. Each of the Working 118interrupt sources. Each interrupt source can be registers can act as a data, address or address offset assigned to one of seven priority levels. register. The 16th Working register (W15) operates as A block diagram of the CPU is illustrated in Figure3-1. a Software Stack Pointer (SSP) for interrupts and calls. The upper 32Kbytes of the data space memory map 3.1 Programmer’s Model can optionally be mapped into program space at any 16K word boundary of either program memory or data Figure3-2 displays the programmer’s model for the EEPROM memory, defined by the 8-bit Program Space PIC24F. All registers in the programmer’s model are Visibility Page Address (PSVPAG) register. The pro- memory mapped and can be manipulated directly by gram to data space mapping feature lets any instruction instructions. access program space as if it were data space. Table3-1 provides a description of each register. All The Instruction Set Architecture (ISA) has been registers associated with the programmer’s model are significantly enhanced beyond that of the PIC18, but memory mapped. maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.  2011-2013 Microchip Technology Inc. DS30001037C-page 25

PIC24F16KL402 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCH PCL Data RAM 16 23 Program Counter Stack Loop Address Control Control Latch Logic Logic 23 16 RAGU Address Latch WAGU Program Memory Data EEPROM Address Bus EA MUX Data Latch ROM Latch 24 16 16 DInesctorduect iaonnd Data Control Instruction Reg al er Lit Control Signals to Various Blocks Hardware Multiplier 16 x 16 W Register Array Divide Support 16 16-Bit ALU 16 To Peripheral Modules TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT REPEAT Loop Counter Register CORCON CPU Control Register DS30001037C-page 26  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 0 W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address W8 Registers W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 Stack Pointer Limit SPLIM 0 Value Register 22 0 PC 0 Program Counter 7 0 Table Memory Page TBLPAG Address Register 7 0 Program Space Visibility PSVPAG Page Address Register 15 0 REPEAT Loop Counter RCOUNT Register 15 SRH SRL 0 ———————DC IPL RA N OV Z C ALU STATUS Register (SR) 2 1 0 15 0 ————————————IPL3PSV—— CPU Control Register (CORCON) Registers or bits are shadowed for PUSH.S and POP.S instructions.  2011-2013 Microchip Technology Inc. DS30001037C-page 27

PIC24F16KL402 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC bit 15 bit 8 R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL<2:0>: CPU Interrupt Priority Level (IPL) Status bits(1,2) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation, which effects the Z bit, has set it at some time in the past 0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit (MSb) of the result occurred Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. 2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS30001037C-page 28  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0 — — — — IPL3(1) PSV — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space is visible in data space 0 = Program space is not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: User interrupts are disabled when IPL3 = 1. 3.3 Arithmetic Logic Unit (ALU) The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a The PIC24F ALU is 16 bits wide and is capable of dedicated hardware multiplier and support hardware addition, subtraction, bit shifts and logic operations. division for a 16-bit divisor. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, 3.3.1 MULTIPLIER the ALU may affect the values of the Carry (C), Zero The ALU contains a high-speed, 17-bit x 17-bit (Z), Negative (N), Overflow (OV) and Digit Carry (DC) multiplier. It supports unsigned, signed or mixed sign Status bits in the SR register. The C and DC Status bits operation in several Multiplication modes: operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. • 16-bit x 16-bit signed • 16-bit x 16-bit unsigned The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. • 16-bit signed x 5-bit (literal) unsigned Data for the ALU operation can come from the W • 16-bit unsigned x 16-bit unsigned register array, or data memory, depending on the • 16-bit unsigned x 5-bit (literal) unsigned addressing mode of the instruction. Likewise, output • 16-bit unsigned x 16-bit signed data from the ALU can be written to the W register array • 8-bit unsigned x 8-bit unsigned or a data memory location.  2011-2013 Microchip Technology Inc. DS30001037C-page 29

PIC24F16KL402 FAMILY 3.3.2 DIVIDER 3.3.3 MULTI-BIT SHIFT SUPPORT The divide block supports 32-bit/16-bit and 16-bit/16-bit The PIC24F ALU supports both single bit and signed and unsigned integer divide operations with the single-cycle, multi-bit arithmetic and logic shifts. following data sizes: Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right 1. 32-bit signed/16-bit signed divide shift, or up to a 15-bit left shift, in a single cycle. All 2. 32-bit unsigned/16-bit unsigned divide multi-bit shift instructions only support Register Direct 3. 16-bit signed/16-bit signed divide Addressing for both the operand source and result 4. 16-bit unsigned/16-bit unsigned divide destination. The quotient for all divide instructions ends up in W0 A full summary of instructions that use the shift and the remainder in W1. Sixteen-bit signed and operation is provided in Table3-2. unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION Instruction Description ASR Arithmetic shift right source register by one or more bits. SL Shift left source register by one or more bits. LSR Logical shift right source register by one or more bits. DS30001037C-page 30  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 4.0 MEMORY ORGANIZATION User access to the program memory space is restricted to the lower half of the address range (000000h to As Harvard architecture devices, the PIC24F 7FFFFFh). The exception is the use of TBLRD/TBLWT microcontrollers feature separate program and data operations, which use TBLPAG<7> to permit access to memory space and bussing. This architecture also the Configuration bits and Device ID sections of the allows the direct access of program memory from the configuration memory space. data space during code execution. Memory maps for the PIC24F16KL402 family of devices are shown in Figure4-1. 4.1 Program Address Space The program address memory space of the PIC24F16KL402 family is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from a table operation or data space remapping, as described in Section4.3 “Interfacing Program and Data Memory Spaces”. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES PIC24F04KLXXX PIC24F08KL2XX PIC24F08KL3XX PIC24F08KL4XX PIC24F16KLXXX GOTO Instruction GOTO Instruction GOTO Instruction GOTO Instruction GOTO Instruction 000000000002hh Reset Address Reset Address Reset Address Reset Address Reset Address 000004h Interrupt Vector Table Interrupt Vector Table Interrupt Vector Table Interrupt Vector Table Interrupt Vector Table 0000FEh Reserved Reserved Reserved Reserved Reserved 000100h 000104h Alternate Vector Table Alternate Vector Table Alternate Vector Table Alternate Vector Table Alternate Vector Table 0001FEh Flash 000200h Program Memory (1408 instructions) Flash Flash Flash Program Memory Program Memory Program Memory 000AFEh e (2816 instructions) (2816 instructions) (2816 instructions) c pa Flash y S Program Memory or (5632 instructions) 0015FEh m e M er Us Unimplemented Read ‘0’ Unimplemented Unimplemented Read ‘0’ 002BFEh Unimplemented Read ‘0’ Read ‘0’ Unimplemented Read ‘0’ 7FFE00h Data EEPROM Data EEPROM Data EEPROM 7FFF00h (256 bytes) (512 bytes) (512 bytes) 7FFFFFh 800000h Reserved Reserved Reserved Reserved Reserved 800800h 800802h ce Unique ID Unique ID Unique ID Unique ID Unique ID 800808h pa 80080Ah y S Reserved Reserved Reserved Reserved Reserved or em Device Config Registers Device Config Registers Device Config Registers Device Config Registers Device Config Registers F80000h M F8000Eh n F80010h o ati ur g nfi Reserved Reserved Reserved Reserved Reserved o C FEFFFEh FF0000h DEVID (2) DEVID (2) DEVID (2) DEVID (2) DEVID (2) FFFFFFh Note: Memory areas are not displayed to scale. DS30001037C-page 31  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 4.1.1 PROGRAM MEMORY 4.1.3 DATA EEPROM ORGANIZATION In the PIC24F16KL402 family, the data EEPROM is The program memory space is organized in mapped to the top of the user program memory space, word-addressable blocks. Although it is treated as starting at address, 7FFE00, and expanding up to 24bits wide, it is more appropriate to think of each address, 7FFFFF. address of the program memory as a lower and upper The data EEPROM is organized as 16-bit wide memory word, with the upper byte of the upper word being and 256 words deep. This memory is accessed using unimplemented. The lower word always has an even Table Read and Table Write operations, similar to the address, while the upper word has an odd address, as user code memory. shown in Figure4-2. 4.1.4 DEVICE CONFIGURATION WORDS Program memory addresses are always word-aligned on the lower word, and addresses are incremented or Table4-1 provides the addresses of the device decremented by two during code execution. This Configuration Words for the PIC24F16KL402 family. arrangement also provides compatibility with data Their location in the memory map is shown in memory space addressing and makes it possible to Figure4-1. access data in the program memory space. For more information on device Configuration Words, 4.1.2 HARD MEMORY VECTORS see Section23.0 “Special Features”. All PIC24F devices reserve the addresses between TABLE 4-1: DEVICE CONFIGURATION 00000h and 000200h for hard-coded program WORDS FOR PIC24F16KL402 execution vectors. A hardware Reset vector is provided FAMILY DEVICES to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO Configuration Word Configuration Words instruction is programmed by the user at 000000h, with Addresses the actual address for the start of code at 000002h. FBS F80000 PIC24F devices also have two Interrupt Vector Tables FGS F80004 (IVT), located from 000004h to 0000FFh and 000104h to 0001FFh. These vector tables allow each of the FOSCSEL F80006 many device interrupt sources to be handled by FOSC F80008 separate ISRs. A more detailed discussion of the FWDT F8000A Interrupt Vector Tables is provided in Section8.1 FPOR F8000C “Interrupt Vector Table (IVT)”. FICD F8000E FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 000001h 00000000 000000h 000003h 00000000 000002h 000005h 00000000 000004h 000007h 00000000 000006h Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’)  2011-2013 Microchip Technology Inc. DS30001037C-page 32

PIC24F16KL402 FAMILY 4.2 Data Address Space Depending on the particular device, PIC24F16KL402 family devices implement either 512 or 1024 words of The PIC24F core has a separate, 16-bit wide data data memory. If an EA points to a location outside of memory space, addressable as a single linear range. this area, an all zero word or byte will be returned. The data space is accessed using two Address Generation Units (AGUs); one each for read and write 4.2.1 DATA SPACE WIDTH operations. The data space memory map is shown in The data memory space is organized in Figure4-3. byte-addressable, 16-bit wide blocks. Data is aligned in All Effective Addresses (EAs) in the data memory space data memory and registers as 16-bit words, but all the are 16 bits wide and point to bytes within the data space. data space EAs resolve to bytes. The Least Significant This gives a data space address range of 64Kbytes or Bytes (LSBs) of each word have even addresses, while 32Kwords. The lower half of the data memory space the Most Significant Bytes (MSBs) have odd (that is, when EA<15> = 0) is used for implemented addresses. memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility (PSV) area (see Section4.3.3 “Reading Data From Program Memory Using Program Space Visibility”). FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES(3) MSB LSB Address MSB LSB Address 0001h SFR Space 0000h SFR 07FFh 07FEh Space 0801h 0800h Data RAM Implemented 09FFh(1) 09FEh(1) Near DataSpace Data RAM 0BFFh(2) 0BFEh(2) 1FFFh 1FFEh Unimplemented Read as ‘0’ 7FFFh 7FFFh 8001h 8000h Program Space Visibility Area FFFFh FFFEh Note 1: Upper data memory boundary for PIC24FXXKL10X/20X devices. 2: Upper data memory boundary for PIC24FXXKL30X/40X devices. 3: Data memory areas are not shown to scale. DS30001037C-page 33  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 4.2.2 DATA MEMORY ORGANIZATION can clear the MSB of any W register by executing a AND ALIGNMENT Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the Although most instructions are capable of operating on PIC24F instruction set supports both word and byte word or byte data sizes, it should be noted that some operations. As a consequence of byte accessibility, all instructions operate only on words. Effective Address (EA) calculations are internally 4.2.3 NEAR DATA SPACE scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified The 8-Kbyte area between 0000h and 1FFFh is Register Indirect Addressing mode [Ws++] will result in referred to as the Near Data Space (NDS). Locations in a value of Ws + 1 for byte operations and Ws + 2 for this space are directly addressable via a 13-bit abso- word operations. lute address field within all memory direct instructions. The remainder of the data space is addressable Data byte reads will read the complete word, which indirectly. Additionally, the whole data space is contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is addressable using MOV instructions, which support Memory Direct Addressing (MDA) with a 16-bit address placed onto the LSB of the data path. That is, data field. For PIC24F16KL402 family devices, the entire memory and the registers are organized as two implemented data memory lies in Near Data Space. parallel, byte-wide entities with shared (word) address decode, but separate write lines. Data byte writes only 4.2.4 SFR SPACE write to the corresponding side of the array or register, which matches the byte address. The first 2Kbytes of the Near Data Space, from 0000h to 07FFh, are primarily occupied with Special Function All word accesses must be aligned to an even address. Registers (SFRs). These are used by the PIC24F core Mis-aligned word data fetches are not supported, so and peripheral modules for controlling the operation of care must be taken when mixing byte and word the device. operations, or translating from 8-bit MCU code. If a mis-aligned read or write is attempted, an address error SFRs are distributed among the modules that they trap will be generated. If the error occurred on a read, control and are generally grouped together by the the instruction underway is completed; if it occurred on module. Much of the SFR space contains unused a write, the instruction will be executed, but the write addresses; these are read as ‘0’. The SFR space, will not occur. In either case, a trap is then executed, where the SFRs are actually implemented, is provided allowing the system and/or user to examine the in Table4-2. Each implemented area indicates a machine state prior to execution of the address Fault. 32-byte region, where at least one address is implemented as an SFR. A complete listing of All byte loads into any W register are loaded into the implemented SFRs, including their addresses, is LSB; the MSB is not modified. provided in Table4-3 throughTable4-18. A Sign-Extend (SE) instruction is provided to allow the users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0 000h Core ICN Interrupts — 100h Timers — TMR — — — CCP — — — 200h MSSP UART — — — — I/O — 300h A/D — — — — — — 400h — — — — — — — ANSEL — 500h — — — — — — — — 600h — CMP — — — — — — — 700h — — System NVM/PMD — — — — Legend: — = No implemented SFRs in this block.  2011-2013 Microchip Technology Inc. DS30001037C-page 34

DS TABLE 4-3: CPU CORE REGISTERS MAP P 3 0 I 00 File Name Start Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All C 1 Addr Resets 0 3 2 7C WREG0 0000 Working Register 0 0000 4 -p WREG1 0002 Working Register 1 0000 ag F e WREG2 0004 Working Register 2 0000 3 1 5 WREG3 0006 Working Register 3 0000 6 WREG4 0008 Working Register 4 0000 K WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 L WREG7 000E Working Register 7 0000 4 WREG8 0010 Working Register 8 0000 0 WREG9 0012 Working Register 9 0000 2 WREG10 0014 Working Register 10 0000 F WREG11 0016 Working Register 11 0000 WREG12 0018 Working Register 12 0000 A WREG13 001A Working Register 13 0000 M WREG14 001C Working Register 14 0000 I WREG15 001E Working Register 15 — 0800 L SPLIM 0020 Stack Pointer Limit Value Register xxxx Y PCL 002E Program Counter Low Word Register 0000 PCH 0030 — — — — — — — — — Program Counter Register High Byte 0000 TBLPAG 0032 — — — — — — — — Table Memory Page Address Register 0000 PSVPAG 0034 — — — — — — — — Program Space Visibility Page Address Register 0000 RCOUNT 0036 REPEAT Loop Counter Register xxxxx SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000 CORCON 0044 — — — — — — — — — — — — IPL3 PSV — — 0000  2 DISICNT 0052 — — Disable Interrupts Counter Register xxxx 0 1 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 -2 0 1 3 M ic ro c h ip T e c h n o lo g y In c .

 2 TABLE 4-4: ICN REGISTER MAP 0 1 1-2 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 0 Name Resets 1 3 M CNPD1 0056 CN15PDE(1) CN14PDE(1) CN13PDE(1) CN12PDE CN11PDE — CN9PDE(2) CN8PDE CN7PDE(2) CN6PDE(1) CN5PDE(1) CN4PDE(1) CN3PDE CN2PDE CN1PDE CN0PDE 0000 icro CNPD2 0058 — CN30PDE CN29PDE — CN27PDE(2) — — CN24PDE(2) CN23PDE(1) CN22PDE CN21PDE — — — — CN16PDE(2) 0000 ch CNEN1 0062 CN15IE(1) CN14IE(1) CN13IE(1) CN12IE CN11IE — CN9IE(1) CN8IE CN7IE(1) CN6IE(2) CN5PIE(2) CN4IE(2) CN3IE CNIE CN1IE CN0IE 0000 ip T CNEN2 0064 — CN30IE CN29IE — CN27IE(2) — — CN24IE(2) CN23IE(1) CN22IE CN21IE — — — — CN16IE(2) 0000 e ch CNPU1 006E CN15PUE(1) CN14PUE(1) CN13PUE(1) CN12PUE CN11PUE — CN9PUE(1) CN8PUE CN7PUE(1) CN6PUE(2) CN5PUE(2) CN4PUE(2) CN3PUE CN2PUE CN1PUE CN0PUE 0000 n o CNPU2 0070 — CN30PUE CN29PUE — CN27PUE(2) — — CN24PUE(2) CN23PUE(1) CN22PUE CN21PUE — — — — CN16PUE(2) 0000 lo gy Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. In Note 1: These bits are unimplemented in 14-pin devices; read as ‘0’. c . 2: These bits are unimplemented in 14-pin and 20-pin devices; read as ‘0’. P I C 2 4 F 1 6 K L 4 0 2 D F S 3 0 A 0 0 1 0 M 3 7 C -p IL a g e 3 Y 6

D TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP P S 3 0 File All I 0 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 0 Name Resets 1 0 37 INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 2 C-p INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 4 ag IFS0 0084 NVMIF — AD1IF U1TXIF U1RXIF — — T3IF T2IF CCP2IF — — T1IF CCP1IF — INT0IF 0000 F e 3 IFS1 0086 U2TXIF U2RXIF INT2IF — T4IF(1) — CCP3IF(1) — — — — INT1IF CNIF CMIF BCL1IF SSP1IF 0000 1 7 IFS2 0088 — — — — — — — — — — T3GIF — — — — — 0000 6 IFS3 008A — — — — — — — — — — — — — BCL2IF(1) SSP2IF(1) — 0000 K IFS4 008C — — — — — — — HLVDIF — — — — — U2ERIF U1ERIF — 0000 L IFS5 008E — — — — — — — — — — — — — — — ULPWUIF 0000 4 IEC0 0094 NVMIE — AD1IE U1TXIE U1RXIE — — T3IE T2IE CCP2IE — — T1IE CCP1IE — INT0IE 0000 0 IEC1 0096 U2TXIE U2RXIE INT2IE — T4IE(1) — CCP3IE(1) — — — — INT1IE CNIE CMIE BCL1IE SSP1IE 0000 2 IEC2 0098 — — — — — — — — — — T3GIE — — — — — 0000 IEC3 009A — — — — — — — — — — — — — BCL2IE(1) SSP2IE(1) — 0000 F IEC4 009C — — — — — — — HLVDIE — — — — — U2ERIE U1ERIE — 0000 A IEC5 009E — — — — — — — — — — — — — — — ULPWUIE 0000 M IPC0 00A4 — T1IP2 T1IP1 T1IP0 — CCP1IP2 CCP1IP1 CCP1IP0 — — — — — INT0IP2 INT0IP1 INT0IP0 4404 IPC1 00A6 — T2IP2 T2IP1 T2IP0 — CCP2IP2 CCP2IP1 CCP2IP0 — — — — — — — — 4400 I L IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — — — — — — — — — T3IP2 T3IP1 T3IP0 4004 Y IPC3 00AA — NVMIP2 NVMIP1 NVMIP0 — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 4044 IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — BCL1IP2 BCL1IP1 BCL1IP0 — SSP1IP2 SSP1IP1 SS1IP0 4444 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 IPC6 00B0 — T4IP2(1) T4IP1(1) T4IP0(1) — — — — — CCP3IP2(1) CCP3IP1(1) CCP3IP0(1) — — — — 4040 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — — — — 4440 IPC9 00B6 — — — — — — — — — T3GIP2 T3GIP1 T3GIP0 — — — — 0040 IPC12 00BC — — — — — BCL2IP2(1) BCL2IP1(1) BCL2IP0(1) — SSP2IP2(1) SSP2IP1(1) SSP2IP0(1) — — — — 0440  IPC16 00C4 — — — — — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 0440 2 0 IPC18 00C8 — — — — — — — — — — — — — HLVDIP2 HLVDIP1 HLVDIP0 0004 1 1 -2 IPC20 00CC — — — — — — — — — — — — — ULPWUIP2 ULPWUIP1 ULPWUIP0 0004 0 1 INTTREG 00E0 CPUIRQ r VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 3 M Legend: — = unimplemented, read as ‘0’, r = reserved. Reset values are shown in hexadecimal. icro Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X family devices; read as ‘0’. c h ip T e c h n o lo g y In c .

 2 TABLE 4-6: TIMER REGISTER MAP 0 1 1 All -20 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 1 3 M TMR1 0100 Timer1 Register 0000 icro PR1 0102 Timer1 Period Register FFFF ch T1CON 0104 TON — TSIDL — — — T1ECS1 T1ECS0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 ip T TMR2 0106 — — — — — — — — Timer2 Register 0000 e c PR2 0108 — — — — — — — — Timer2 Period Register 00FF h n o T2CON 010A — — — — — — — — — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 0000 lo g TMR3 010C Timer3 Register 0000 y In T3GCON 010E — — — — — — — — TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 0000 c . T3DONE T3CON 0110 — — — — — — — — TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC — TMR3ON 0000 TMR4(1) 0112 — — — — — — — — Timer4 Register 0000 PR4(1) 0114 — — — — — — — — Timer4 Period Register 00FF T4CON(1) 0116 — — — — — — — — — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 0000 CCPTMRS0(1) 013C — — — — — — — — — C3TSEL0(1) — — C2TSEL0 — — C1TSEL0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P Note 1: These bits and/or registers are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X family devices; read as ‘0’. I C TABLE 4-7: CCP/ECCP REGISTER MAP 2 All 4 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets F CCP1CON 0190 — — — — — — — — PM1(1) PM0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 1 CCPR1L 0192 — — — — — — — — Capture/Compare/PWM1 Register Low Byte 0000 6 CCPR1H 0194 — — — — — — — — Capture/Compare/PWM1 Register High Byte 0000 K ECCP1DEL(1) 0196 — — — — — — — — PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 L ECCP1AS(1) 0198 — — — — — — — — ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 PSTR1CON(1) 019A — — — — — — — — CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 0001 4 0 CCP2CON 019C — — — — — — — — — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 2 CCPR2L 019E — — — — — — — — Capture/Compare/PWM2 Register Low Byte 0000 D CCPR2H 01A0 — — — — — — — — Capture/Compare/PWM2 Register High Byte 0000 F S 30 CCP3CON(1) 01A8 — — — — — — — — — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 A 00 CCPR3L(1) 01AA — — — — — — — — Capture/Compare/PWM3 Register Low Byte 0000 1 03 CCPR3H(1) 01AC — — — — — — — — Capture/Compare/PWM3 Register High Byte 0000 M 7 C-pa LNeogteend1:: —Th e=s uen bimitsp alenmde/onrt eredg, irseteards aasr e‘0 u’.n Rimepseletm vaelnuteesd aorne PsIhCo2w4nF iXnX hKeLx1a0dXec aimnda lP.IC24FXXKL20X family devices; read as ‘0’. IL g e 3 Y 8

DS TABLE 4-8: MSSP REGISTER MAP P 3 0 I 00 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All C 1 Resets 0 3 2 7C SSP1BUF 0200 — — — — — — — — MSSP1 Receive Buffer/Transmit Register 00xx 4 -p SSP1CON1 0202 — — — — — — — — WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 ag F e SSP1CON2 0204 — — — — — — — — GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 3 1 9 SSP1CON3 0206 — — — — — — — — ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 6 SSP1STAT 0208 — — — — — — — — SMP CKE D/A P S R/W UA BF 0000 SSP1ADD 020A — — — — — — — — MSSP1 Address Register (I2C™ Slave Mode) 0000 K MSSP1 Baud Rate Reload Register (I2C Master Mode) L SSP1MSK 020C — — — — — — — — MSSP1 Address Mask Register (I2C Slave Mode) 00FF 4 SSP2BUF(1) 0210 — — — — — — — — MSSP2 Receive Buffer/Transmit Register 00xx 0 SSP2CON1(1) 0212 — — — — — — — — WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 2 SSP2CON2(1) 0214 — — — — — — — — GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 SSP2CON3(1) 0216 — — — — — — — — ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 F SSP2STAT(1) 0218 — — — — — — — — SMP CKE D/A P S R/W UA BF 0000 A SSP2ADD(1) 021A — — — — — — — — MSSP2 Address Register (I2C Slave Mode) 0000 M MSSP2 Baud Rate Reload Register (I2C Master Mode) SSP2MSK(1) 021C — — — — — — — — MSSP2 Address Mask Register (I2C Slave Mode) 00FF I L Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: These bits and/or registers are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X family devices; read as ‘0’. Y TABLE 4-9: UART REGISTER MAP File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110  2 U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx 0 11 U1RXREG 0226 — — — — — — — UART1 Receive Register 0000 -2 0 U1BRG 0228 Baud Rate Generator Prescaler Register 0000 1 3 M U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 ic U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 ro c U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx h ip T U2RXREG 0236 — — — — — — — UART2 Receive Register 0000 ec U2BRG 0238 Baud Rate Generator Prescaler Register 0000 h no Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. lo g y In c .

 TABLE 4-10: PORTA REGISTER MAP 2 0 11-2 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7(1) Bit 6 Bit 5(2) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 1 3 TRISA 02C0 — — — — — — — — TRISA7 TRISA6 — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 00DF M ic PORTA 02C2 — — — — — — — — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx ro c LATA 02C4 — — — — — — — — LATA7 LATA6 — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx h ip ODCA 02C6 — — — — — — — — ODA7 ODA6 — ODA4 ODA3 ODA2 ODA1 ODA0 0000 T ec Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. h n Note 1: These ports and their associated bits are unimplemented on 14-pin and 20-pin devices; read as ‘0’. o lo 2: PORTA<5> is unavailable when MCLR functionality is enabled (MCLRE Configuration bit = 1). g y In c TABLE 4-11: PORTB REGISTER MAP . File Addr Bit 15 Bit 14 Bit 13(1) Bit 12(1) Bit 11(2) Bit 10(2) Bit 9 Bit 8 Bit 7(1) Bit 6(2) Bit 5(2) Bit 4 Bit 3(2) Bit 2(1) Bit 1(1) Bit 0 All Name Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx ODCB 02CE ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 P Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I Note 1: These ports and their associated bits are unimplemented on 14-pin and 20-pin devices. C 2: These ports and their associated bits are unimplemented in 14-pin devices. 2 4 TABLE 4-12: PAD CONFIGURATION REGISTER MAP F File All 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 6 PADCFG1 02FC — — — — SDO2DIS(1) SCK2DIS(1) SDO1DIS SCK1DIS — — — — — — — — 0000 K Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. L Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X family devices; read as ‘0’. 4 0 2 D F S 3 0 A 0 0 1 0 M 3 7 C -p IL a g e 4 Y 0

DS TABLE 4-13: A/D REGISTER MAP P 3 0 I 00 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All C 1 Name Resets 0 3 2 7C ADC1BUF0 0300 A/D Buffer 0 xxxx 4 -p ADC1BUF1 0302 A/D Buffer 1 xxxx ag F e AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000 4 1 1 AD1CON2 0322 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — — r — SMPI3 SMPI2 SMPI1 SMPI0 r ALTS 0000 6 AD1CON3 0324 ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 — — ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 K AD1CHS 0328 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 AD1CSSL 0330 CSSL15 CSSL14 CSSL13 CSSL12(1) CSSL11(1) CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 — CSSL4(1) CSSL3(1) CSSL2(1) CSSL1 CSSL0 0000 L Legend: — = unimplemented, read as ‘0’, r = reserved bit. Reset values are shown in hexadecimal. 4 Note 1: These bits are unimplemented in 14-pin devices; read as ‘0’. 0 2 TABLE 4-14: ANALOG SELECT REGISTER MAP F All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets A ANCFG 04DE — — — — — — — — — — — — — — — VBGEN 0000 M ANSA 04E0 — — — — — — — — — — — — ANSA3 ANSA2 ANSA1 ANSA0 000F I ANSB 04E2 ANSB15 ANSB14 ANSB13 ANSB12(1) — — — — — — — ANSB4 ANSB3(2) ANSB2(1) ANSB1(1) ANSB0(1) F01F(3) L Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Y Note 1: These bits are unimplemented in 14-pin devices; read as ‘0’. 2: These bits are unimplemented in 14-pin and 20-pin devices; read as ‘0’ 3: Reset value for 28-pin devices is shown. TABLE 4-15: COMPARATOR REGISTER MAP File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets  2 CMSTAT 0630 CMIDL — — — — — C2EVT(1) C1EVT — — — — — — C2OUT C1OUT xxxx 0 1 CVRCON 0632 — — — — — — — — CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000 1 -2 CM1CON 0634 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 xxxx 0 13 CM2CON(1) 0636 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 M ic Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ro Note 1: These bits and/or registers are unimplemented in PIC24FXXKL10X/20X devices; read as ‘0’. c h ip T e c h n o lo g y In c .

 TABLE 4-16: SYSTEM REGISTER MAP 2 0 11-2 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 1 3 RCON 0740 TRAPR IOPUWR SBOREN — — — CM PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1) M ic OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK — LOCK — CF SOSCDRV SOSCEN OSWEN (Note 2) ro c CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 3100 h ip OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 T ec REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000 h n HLVDCON 0756 HLVDEN — HLSIDL — — — — — VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 o log Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. y In Note 1: RCON register Reset values are dependent on the type of Reset. c 2: OSCCON register Reset values are dependent on configuration fuses and by type of Reset. . TABLE 4-17: NVM REGISTER MAP All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets NVMCON 0760 WR WREN WRERR PGMONLY — — — — — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000 NVMKEY 0766 — — — — — — — — NVM Key Register 0000 P Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I C TABLE 4-18: ULTRA LOW-POWER WAKE-UP REGISTER MAP 2 All 4 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets F ULPWCON 0768 ULPEN — ULPSIDL — — — — ULPSINK — — — — — — — — 0000 1 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 K TABLE 4-19: PMD REGISTER MAP L File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 4 0 PMD1 0770 — T4MD T3MD T2MD T1MD — — — SSP1MD U2MD U1MD — — — — ADC1MD 0000 2 PMD2 0772 — — — — — — — — — — — — — CCP3MD CCP2MD CCP1MD 0000 D PMD3 0774 — — — — — CMPMD — — — — — — — — SSP2MD — 0000 F S 30 PMD4 0776 — — — — — — — — ULPWUMD — — EEMD REFOMD — HLVDMD — 0000 A 0 01 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 M 3 7 C -p IL a g e 4 Y 2

PIC24F16KL402 FAMILY 4.2.5 SOFTWARE STACK 4.3 Interfacing Program and Data Memory Spaces In addition to its use as a Working register, the W15 register in PIC24F devices is also used as a Software The PIC24F architecture uses a 24-bit wide program Stack Pointer. The pointer always points to the first space and 16-bit wide data space. The architecture is available free word and grows from lower to higher also a modified Harvard scheme, meaning that data addresses. It predecrements for stack pops and can also be present in the program space. To use this post-increments for stack pushes, as shown in data successfully, it must be accessed in a way that Figure4-4. preserves the alignment of information in both spaces. Note that for a PC push during any CALL instruction, Apart from the normal execution, the PIC24F the MSB of the PC is zero-extended before the push, architecture provides two methods by which the ensuring that the MSB is always clear. program space can be accessed during operation: Note: A PC push during exception processing • Using table instructions to access individual bytes will concatenate the SRL register to the or words anywhere in the program space MSB of the PC prior to the push. • Remapping a portion of the program space into The Stack Pointer Limit Value (SPLIM) register, the data space, PSV associated with the Stack Pointer, sets an upper Table instructions allow an application to read or write address boundary for the stack. SPLIM is uninitialized small areas of the program memory. This makes the at Reset. As is the case for the Stack Pointer, method ideal for accessing data tables that need to be SPLIM<0> is forced to ‘0’ as all stack operations must updated from time to time. It also allows access to all be word-aligned. Whenever an EA is generated, using bytes of the program word. The remapping method W15 as a source or destination pointer, the resulting allows an application to access a large block of data on address is compared with the value in SPLIM. If the a read-only basis, which is ideal for look-ups from a contents of the Stack Pointer (W15) and the SPLIM large table of static data. It can only access the least register are equal, and a push operation is performed, significant word (lsw) of the program word. a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. 4.3.1 ADDRESSING PROGRAM SPACE Thus, for example, if it is desirable to cause a stack Since the address ranges for the data and program error trap when the stack grows beyond address, spaces are 16 and 24 bits, respectively, a method is 0DF6, in RAM, initialize the SPLIM with the value, needed to create a 23-bit or 24-bit program address 0DF4. from 16-bit data registers. The solution depends on the interface method to be used. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to For table operations, the 8-bit Table Memory Page be less than 0800h. This prevents the stack from Address register (TBLPAG) is used to define a 32Kword interfering with the Special Function Register (SFR) region within the program space. This is concatenated space. with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit (MSb) of Note: A write to the SPLIM register should not TBLPAG is used to determine if the operation occurs in be immediately followed by an indirect the user memory (TBLPAG<7> = 0) or the configuration read operation using W15. memory (TBLPAG<7> = 1). For remapping operations, the 8-bit Program Space FIGURE 4-4: CALL STACK FRAME Visibility Page Address register (PSVPAG) is used to define a 16Kword page in the program space. When 0000h 15 0 the MSb of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike the table operations, this limits s ardss remapping operations strictly to the user memory area. we ows Toer Addr PC<15:0> W15 (before CALL) Tcraebalete4d- 2fo0r atnadb lFe igoupreera4t-i5on ssh oawnd h orewm thaep ppirnogg raacmce EsAse iss Grgh 000000000 PC<22:16> from the data EA. Here, P<23:0> bits refer to a program ck Hi <Free Word> W15 (after CALL) space word, whereas the D<15:0> bits refer to a data a St space word. POP : [--W15] PUSH: [W15++] DS30001037C-page 43  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 4-20: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 PSVPAG<7:0>(2) Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. 2: PSVPAG can have only two values (‘00’ to access program memory and FF to access data EEPROM) on PIC24F16KL402 family devices. FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 bits 24 Bits Select 1 EA 0 Program Space Visibility(1) 0 PSVPAG (Remapping) 8 bits 15 bits 23 Bits User/Configuration Byte Select Space Select Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.  2011-2013 Microchip Technology Inc. DS30001037C-page 44

PIC24F16KL402 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM In Byte mode, either the upper or lower byte of MEMORY AND DATA EEPROM the lower program word is mapped to the lower MEMORY USING TABLE byte of a data address. The upper byte is INSTRUCTIONS selected when the byte select is ‘1’; the lower byte is selected when it is ‘0’. The TBLRDL and TBLWTL instructions offer a direct 2. TBLRDH (Table Read High): In Word mode, it method of reading or writing the lower word of any maps the entire upper word of a program address address within the program memory without going (P<23:16>) to a data address. Note that through data space. It also offers a direct method of D<15:8>, the ‘phantom’ byte, will always be ‘0’. reading or writing a word of any address within data EEPROM memory. The TBLRDH and TBLWTH In Byte mode, it maps the upper or lower byte of instructions are the only method to read or write the the program word to D<7:0> of the data upper 8 bits of a program space word as data. address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is Note: The TBLRDH and TBLWTH instructions are selected (byte select = 1). not used while accessing data EEPROM memory. In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or The PC is incremented by two for each successive words to a program space address. The details of 24-bit program word. This allows program memory their operation are explained in Section5.0 “Flash addresses to directly map to data space addresses. Program Memory”. Program memory can thus be regarded as two, 16-bit For all table operations, the area of program memory word-wide address spaces, residing side by side, each space to be accessed is determined by the Table with the same address range. TBLRDL and TBLWTL Memory Page Address register (TBLPAG). TBLPAG access the space which contains the least significant covers the entire program memory space of the data word, and TBLRDH and TBLWTH access the space device, including user and configuration spaces. When which contains the upper data byte. TBLPAG<7> = 0, the table page is located in the user Two table instructions are provided to move byte or memory space. When TBLPAG<7> = 1, the page is word-sized (16-bit) data to and from program space. located in configuration space. Both function as either byte or word operations. Note: Only Table Read operations will execute 1. TBLRDL (Table Read Low): In Word mode, it in the configuration memory space, and maps the lower word of the program space only then, in implemented areas, such as location (P<15:0>) to a data address (D<15:0>). the Device ID. Table write operations are not allowed. FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Data EA<15:0> TBLPAG 00 Program Space 23 16 8 0 23 15 0 000000h 00000000 00000000 00000000 002BFEh 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are provided; write operations are also valid in the 800000h user memory area. DS30001037C-page 45  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 4.3.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The MEMORY USING PROGRAM SPACE upper 8 bits of any program space location, used as VISIBILITY data, should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible The upper 32 Kbytes of data space may optionally be issues should the area of code ever be accidentally mapped into a 16K word page of the program space. executed. This provides transparent access of stored constant data from the data space without the need to use Note: PSV access is temporarily disabled during special instructions (i.e., TBLRDL/H). Table Reads/Writes. Program space access through the data space occurs For operations that use PSV and are executed outside of if the MSb of the data space EA is ‘1’ and PSV is a REPEAT loop, the MOV and MOV.D instructions will enabled by setting the PSV bit in the CPU Control require one instruction cycle, in addition to the specified (CORCON<2>) register. The location of the program execution time. All other instructions will require two memory space to be mapped into the data space is instruction cycles in addition to the specified execution determined by the Program Space Visibility Page time. Address (PSVPAG) register. This 8-bit register defines For operations that use PSV, which are executed inside any one of 256 possible pages of 16K words in program a REPEAT loop, there will be some instances that space. In effect, PSVPAG functions as the upper 8 bits require two instruction cycles, in addition to the of the program memory address, with 15 bits of the EA specified execution time of the instruction: functioning as the lower bits. • Execution in the first iteration By incrementing the PC by 2 for each program memory • Execution in the last iteration word, the lower 15 bits of data space addresses directly • Execution prior to exiting the loop due to an map to the lower 15 bits in the corresponding program interrupt space addresses. • Execution upon re-entering the loop after an Data reads from this area add an additional cycle to the interrupt is serviced instruction being executed, since two program memory fetches are required. Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a Although each data space address, 8000h and higher, single cycle. maps directly into a corresponding program memory address (see Figure4-7), only the lower 16 bits of the FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space Data Space PSVPAG 23 15 0 000000h 0000h 00 Data EA<14:0> 002BFEh The data in the page designated by PSVPAG is mapped into the upper half of the data memory 8000h space.... PSV Area ...while the lower 15 bits of the EA specify an exact address within the PSV FFFFh area. This corresponds exactly to the same lower 15 bits of the actual program space address. 800000h  2011-2013 Microchip Technology Inc. DS30001037C-page 46

PIC24F16KL402 FAMILY 5.0 FLASH PROGRAM MEMORY Run-Time Self Programming (RTSP) is accomplished using TBLRD (Table Read) and TBLWT (Table Write) Note: This data sheet summarizes the features of instructions. With RTSP, the user may write program this group of PIC24F devices. It is not memory data in blocks of 32instructions (96 bytes) at intended to be a comprehensive reference a time, and erase program memory in blocks of 32, 64 source. For more information on Flash and 128 instructions (96,192 and 384 bytes) at a time. Programming, refer to the “dsPIC33/PIC24 The NVMOP<1:0> (NVMCON<1:0>) bits decide the Family Reference Manual”, “Program erase block size. Memory” (DS39715). 5.1 Table Instructions and Flash The PIC24F16KL402 family of devices contains internal Flash program memory for storing and execut- Programming ing application code. The memory is readable, writable Regardless of the method used, Flash memory and erasable when operating with VDD over 1.8V. programming is done with the Table Read and Table Flash memory can be programmed in three ways: Write instructions. These allow direct read and write • In-Circuit Serial Programming™ (ICSP™) access to the program memory space from the data • Run-Time Self Programming (RTSP) memory while the device is in normal operating mode. • Enhanced In-Circuit Serial Programming The 24-bit target address in the program memory is (Enhanced ICSP) formed using the TBLPAG<7:0> bits and the Effective Address (EA) from a W register, specified in the table ICSP allows a PIC24F device to be serially pro- instruction, as depicted in Figure5-1. grammed while in the end application circuit. This is simply done with two lines for the programming clock The TBLRDL and TBLWTL instructions are used to read and programming data (which are named PGECx and or write to bits<15:0> of program memory. TBLRDL and PGEDx, respectively), and three other lines for power TBLWTL can access program memory in both Word (VDD), ground (VSS) and Master Clear/Program mode and Byte modes. Entry Voltage (MCLR/VPP). This allows customers to The TBLRDH and TBLWTH instructions are used to read manufacture boards with unprogrammed devices and or write to bits<23:16> of program memory. TBLRDH then program the microcontroller just before shipping and TBLWTH can also access program memory in Word the product. This also allows the most recent firmware or Byte mode. or custom firmware to be programmed. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program 0 Program Counter 0 Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2011-2013 Microchip Technology Inc. DS30001037C-page 47

PIC24F16KL402 FAMILY 5.2 RTSP Operation 5.3 Enhanced In-Circuit Serial Programming The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows Enhanced ICSP uses an on-board bootloader, known the user to erase blocks of 1 row, 2 rows and 4 rows as the program executive, to manage the programming (32,64 and 128 instructions) at a time, and to program process. Using an SPI data frame format, the program one row at a time. executive can erase, program and verify program The 1-row (96 bytes), 2-row (192 bytes) and 4-row memory. For more information on Enhanced ICSP, see (384 bytes) erase blocks and single row write block the device programming specification. (96 bytes) are edge-aligned, from the beginning of program memory. 5.4 Control Registers When data is written to program memory using TBLWT There are two SFRs used to read and write the instructions, the data is not written directly to memory. program Flash memory: NVMCON and NVMKEY. Instead, data written using Table Writes is stored in holding The NVMCON register (Register5-1) controls the blocks latches until the programming sequence is executed. that need to be erased, which memory type is to be Any number of TBLWT instructions can be executed programmed and when the programming cycle starts. and a write will be successfully performed. However, NVMKEY is a write-only register that is used for write 32TBLWT instructions are required to write the full row protection. To start a programming or erase sequence, of memory. the user must consecutively write 55h and AAh to the The basic sequence for RTSP programming is to set up NVMKEY register. For more information, refer to a Table Pointer, then do a series of TBLWT instructions to Section5.5 “Programming Operations”. load the buffers. Programming is performed by setting the control bits in the NVMCON register. 5.5 Programming Operations Data can be loaded in any order and the holding regis- A complete programming sequence is necessary for ters can be written to multiple times before performing programming or erasing the internal Flash in RTSP a write operation. Subsequent writes, however, will mode. During a programming or erase operation, the wipe out any previous writes. processor stalls (waits) until the operation is finished. Note: Writing to a location multiple times without Setting the WR bit (NVMCON<15>) starts the erasing it is not recommended. operation and the WR bit is automatically cleared when the operation is finished. All of the Table Write operations are single-word writes (two instruction cycles), because only the buffers are writ- ten. A programming cycle is required for programming each row. DS30001037C-page 48  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY(4) — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5(1) NVMOP4(1) NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1) bit 7 bit 0 Legend: SO = Settable Only bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit W = Writable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt, or termination, has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12 PGMONLY: Program Only Enable bit(4) bit 11-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Performs the erase operation specified by NVMOP<5:0> on the next WR command 0 = Performs the program operation specified by NVMOP<5:0> on the next WR command bit 5-0 NVMOP<5:0>: Programming Operation Command Byte bits(1) Erase Operations (when ERASE bit is ‘1’): 1010xx = Erases entire boot block (including code-protected boot block)(2) 1001xx = Erases entire memory (including boot block, configuration block, general block)(2) 011010 = Erases 4 rows of Flash memory(3) 011001 = Erases 2 rows of Flash memory(3) 011000 = Erases 1 row of Flash memory(3) 0101xx = Erases entire configuration block (except code protection bits) 0100xx = Erases entire data EEPROM(4) 0011xx = Erases entire general memory block programming operations 0001xx = Writes 1 row of Flash memory (when ERASE bit is ‘0’)(3) Note 1: All other combinations of the NVMOP<5:0> bits are no operation. 2: Available in ICSP™ mode only. Refer to the device programming specification. 3: The address in the Table Pointer decides which rows will be erased. 4: This bit is used only while accessing data EEPROM. It is implemented only in devices with data EEPROM.  2011-2013 Microchip Technology Inc. DS30001037C-page 49

PIC24F16KL402 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR 4. Write the first 32 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example5-1). 5. Write the program block to Flash memory: The user can program one row of Flash program memory at a time by erasing the programmable row. a) Set the NVMOPx bits to ‘000100’ to The general process is as follows: configure for row programming. Clear the ERASE bit and set the WREN bit. 1. Read a row of program memory (32instructions) b) Write 55h to NVMKEY. and store in data RAM. c) Write AAh to NVMKEY. 2. Update the program data in RAM with the desired new data. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of 3. Erase a row (see Example5-1): the write cycle. When the write to Flash a) Set the NVMOPx bits (NVMCON<5:0>) to memory is done, the WR bit is cleared ‘011000’ to configure for row erase. Set the automatically. ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow b) Write the starting address of the block to be any erase or program operation to proceed. After the erased into the TBLPAG and W registers. programming command has been executed, the user c) Write 55h to NVMKEY. must wait for the programming time until programming d) Write AAh to NVMKEY. is complete. The two instructions following the start of e) Set the WR bit (NVMCON<15>). The erase the programming sequence should be NOPs, as shown cycle begins and the CPU stalls for the in Example5-5. duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. EXAMPLE 5-1: ERASING A PROGRAM MEMORY ROW – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row erase operation MOV #0x4058, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS30001037C-page 50  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE // C example using MPLAB C30 int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Global variable located in Pgm Memory unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); // Initialize PM Page Boundary SFR offset = &progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4058; // Initialize NVMCON asm("DISI #5"); // Block all interrupts for next 5 // instructions __builtin_write_NVM(); // C30 function to perform unlock // sequence and set WR EXAMPLE 5-3: LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row programming operations MOV #0x4004, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 32nd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0] ; Write PM high byte into program latch  2011-2013 Microchip Technology Inc. DS30001037C-page 51

PIC24F16KL402 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Global variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write //Set up NVMCON for row programming NVMCON = 0x4004; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); // Initialize PM Page Boundary SFR offset = &progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write necessary number of latches for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++) { __builtin_tblwtl(offset, progData[i++]); // Write to address low word __builtin_tblwth(offset, progData[i]); // Write to upper byte offset = offset + 2; // Increment address } EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE DISI #5 ; Block all interrupts for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; 2 NOPs required after setting WR NOP ; BTSC NVMCON, #15 ; Wait for the sequence to be completed BRA $-2 ; EXAMPLE 5-6: INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE // C example using MPLAB C30 asm("DISI #5"); // Block all interrupts for next 5 instructions __builtin_write_NVM(); // Perform unlock sequence and set WR DS30001037C-page 52  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 6.0 DATA EEPROM MEMORY 6.1 NVMCON Register Note: This data sheet summarizes the features of The NVMCON register (Register6-1) is also the primary this group of PIC24F devices. It is not control register for data EEPROM program/erase intended to be a comprehensive reference operations. The upper byte contains the control bits source. For more information on Data used to start the program or erase cycle, and the flag bit EEPROM, refer to the “dsPIC33/PIC24 to indicate if the operation was successfully performed. Family Reference Manual”, “Data The lower byte of NVMCOM configures the type of NVM EEPROM” (DS39720). operation that will be performed. The data EEPROM memory is a Nonvolatile Memory 6.2 NVMKEY Register (NVM), separate from the program and volatile data RAM. Data EEPROM memory is based on the same The NVMKEY is a write-only register that is used to Flash technology as program memory, and is optimized prevent accidental writes or erasures of data EEPROM for both long retention and a higher number of locations. erase/write cycles. To start any programming or erase sequence, the The data EEPROM is mapped to the top of the user pro- following instructions must be executed first, in the gram memory space, with the top address at program exact order provided: memory address, 7FFFFFh. For PIC24FXXKL4XX 1. Write 55h to NVMKEY. devices, the size of the data EEPROM is 256 words 2. Write AAh to NVMKEY. (7FFE00h to 7FFFFFh). For PIC24FXXKL3XX devices, the size of the data EEPROM is 128 words (7FFF00h to After this sequence, a write will be allowed to the 7FFFFFh). The data EEPROM is not implemented in NVMCON register for one instruction cycle. In most PIC24F08KL20X or PIC24F04KL10X devices. cases, the user will simply need to set the WR bit in the NVMCON register to start the program or erase cycle. The data EEPROM is organized as 16-bit wide Interrupts should be disabled during the unlock memory. Each word is directly addressable, and is sequence. readable and writable during normal operation over the entire VDD range. The MPLAB® C30 C compiler provides a defined library procedure (builtin_write_NVM) to perform the Unlike the Flash program memory, normal program unlock sequence. Example6-1illustrates how the execution is not stopped during a data EEPROM unlock sequence can be performed with in-line program or erase operation. assembly. The data EEPROM programming operations are controlled using the three NVM Control registers: • NVMCON: Nonvolatile Memory Control Register • NVMKEY: Nonvolatile Memory Key Register • NVMADR: Nonvolatile Memory Address Register EXAMPLE 6-1: DATA EEPROM UNLOCK SEQUENCE //Disable Interrupts For 5 instructions asm volatile("disi #5"); //Issue Unlock Sequence asm volatile ("mov #0x55, W0 \n" "mov W0, NVMKEY \n" "mov #0xAA, W1 \n" "mov W1, NVMKEY \n"); // Perform Write/Erase operations asm volatile ("bset NVMCON, #WR \n" "nop \n" "nop \n");  2011-2013 Microchip Technology Inc. DS30001037C-page 53

PIC24F16KL402 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5(1) NVMOP4(1) NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit SO = Settable Only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit (program or erase) 1 = Initiates a data EEPROM erase or write cycle (can be set but not cleared in software) 0 = Write cycle is complete (cleared automatically by hardware) bit 14 WREN: Write Enable bit (erase or program) 1 = Enables an erase or program operation 0 = No operation allowed (device clears this bit on completion of the write/erase operation) bit 13 WRERR: Flash Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or WDT Reset during programming operation) 0 = The write operation completed successfully bit 12 PGMONLY: Program Only Enable bit 1 = Write operation is executed without erasing target address(es) first 0 = Automatic erase-before-write; write operations are preceded automatically by an erase of target address(es) bit 11-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase Operation Select bit 1 = Performs an erase operation when WR is set 0 = Performs a write operation when WR is set bit 5-0 NVMOP<5:0>: Programming Operation Command Byte bits(1) Erase Operations (when ERASE bit is ‘1’): 011010 = Erases 8 words 011001 = Erases 4 words 011000 = Erases 1 word 0100xx = Erases entire data EEPROM Programming Operations (when ERASE bit is ‘0’): 001xxx = Writes 1 word Note 1: These NVMOP configurations are unimplemented on PIC24F04KL10X and PIC24F08KL20X devices. DS30001037C-page 54  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 6.3 NVM Address Register 6.4 Data EEPROM Operations As with Flash program memory, the NVM Address The EEPROM block is accessed using Table Read and Registers, NVMADRU and NVMADR, form the 24-bit Table Write operations, similar to those used for pro- Effective Address (EA) of the selected row or word for gram memory. The TBLWTH and TBLRDH instructions data EEPROM operations. The NVMADRU register is are not required for data EEPROM operations since the used to hold the upper 8 bits of the EA, while the memory is only 16 bits wide (data on the lower address NVMADR register is used to hold the lower 16 bits of is valid only). The following programming operations the EA. These registers are not mapped into the can be performed on the data EEPROM: Special Function Register (SFR) space; instead, they • Erase one, four or eight words directly capture the EA<23:0> of the last Table Write • Bulk erase the entire data EEPROM instruction that has been executed and selects the data • Write one word EEPROM row to erase. Figure6-1 depicts the program • Read one word memory EA that is formed for programming and erase operations. Note: Unexpected results will be obtained if the Like program memory operations, the Least Significant user attempts to read the EEPROM while bit (LSb) of NVMADR is restricted to even addresses. a programming or erase operation is This is because any given address in the data EEPROM underway. space consists of only the lower word of the program The C30 C compiler includes library memory width; the upper word, including the uppermost procedures to automatically perform the “phantom byte”, is unavailable. This means that the LSb Table Read and Table Write operations, of a data EEPROM address will always be ‘0’. manage the Table Pointer and write Similarly, the Most Significant bit (MSb) of NVMADRU buffers, and unlock and initiate memory is always ‘0’, since all addresses lie in the user program write sequences. This eliminates the need space. to create assembler macros or time critical routines in C for each application. FIGURE 6-1: DATA EEPROM ADDRESSING WITH TBLPAG The library procedures are used in the code examples detailed in the following sections. General descriptions AND NVM ADDRESS of each process are provided for users who are not REGISTERS using the C30 compiler libraries. 24-Bit PM Address 7Fh xxxxh 0 TBLPAG W Register EA 0 NVMADRU NVMADR  2011-2013 Microchip Technology Inc. DS30001037C-page 55

PIC24F16KL402 FAMILY 6.4.1 ERASE DATA EEPROM A typical erase sequence is provided in Example6-2. This example shows how to do a one-word erase. The data EEPROM can be fully erased, or can be Similarly, a four-word erase and an eight-word erase partially erased, at three different sizes: one word, four can be done. This example uses C library procedures to words or eight words. The bits, NVMOP<1:0> manage the Table Pointer (builtin_tblpage and (NVMCON<1:0>), decide the number of words to be builtin_tbloffset) and the Erase Page Pointer erased. To erase partially from the data EEPROM, the (builtin_tblwtl). The memory unlock sequence following sequence must be followed: (builtin_write_NVM) also sets the WR bit to initiate 1. Configure NVMCON to erase the required the operation and returns control when complete. number of words: one, four or eight. 2. Load TBLPAG and WREG with the EEPROM address to be erased. 3. Clear the NVMIF status bit and enable the NVM interrupt (optional). 4. Write the key sequence to NVMKEY. 5. Set the WR bit to begin the erase cycle. 6. Either poll the WR bit or wait for the NVM interrupt (NVMIF is set). EXAMPLE 6-2: SINGLE-WORD ERASE int __attribute__ ((space(eedata))) eeData = 0x1234; // Global variable located in EEPROM unsigned int offset; // Set up NVMCON to erase one word of data EEPROM NVMCON = 0x4058; // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address __builtin_tblwtl(offset, 0); // Write EEPROM data to write latch asm volatile ("disi #5"); // Disable Interrupts For 5 Instructions __builtin_write_NVM(); // Issue Unlock Sequence & Start Write Cycle while(NVMCONbits.WR=1); // Optional: Poll WR bit to wait for // write sequence to complete DS30001037C-page 56  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 6.4.1.1 Data EEPROM Bulk Erase 6.4.2 SINGLE-WORD WRITE To erase the entire data EEPROM (bulk erase), the To write a single word in the data EEPROM, the address registers do not need to be configured following sequence must be followed: because this operation affects the entire data 1. Erase one data EEPROM word (as mentioned in EEPROM. The following sequence helps in performing Section6.4.1 “Erase Data EEPROM”) if a bulk erase: PGMONLY bit (NVMCON<12>) is set to ‘1’. 1. Configure NVMCON to Bulk Erase mode. 2. Write the data word into the data EEPROM 2. Clear the NVMIF status bit and enable the NVM latch. interrupt (optional). 3. Program the data word into the EEPROM: 3. Write the key sequence to NVMKEY. - Configure the NVMCON register to program one 4. Set the WR bit to begin the erase cycle. EEPROM word (NVMCON<5:0> = 0001xx). 5. Either poll the WR bit or wait for the NVM - Clear the NVMIF status bit and enable the NVM interrupt (NVMIF is set). interrupt (optional). - Write the key sequence to NVMKEY. A typical bulk erase sequence is provided in - Set the WR bit to begin the erase cycle. Example6-3. - Either poll the WR bit or wait for the NVM interrupt (NVMIF set). - To get cleared, wait until NVMIF is set. A typical single-word write sequence is provided in Example6-4. EXAMPLE 6-3: DATA EEPROM BULK ERASE // Set up NVMCON to bulk erase the data EEPROM NVMCON = 0x4050; // Disable Interrupts For 5 Instructions asm volatile ("disi #5"); // Issue Unlock Sequence and Start Erase Cycle __builtin_write_NVM(); EXAMPLE 6-4: SINGLE-WORD WRITE TO DATA EEPROM int __attribute__ ((space(eedata))) eeData = 0x1234; // Global variable located in EEPROM int newData; // New data to write to EEPROM unsigned int offset; // Set up NVMCON to erase one word of data EEPROM NVMCON = 0x4004; // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address __builtin_tblwtl(offset, newData); // Write EEPROM data to write latch asm volatile ("disi #5"); // Disable Interrupts For 5 Instructions __builtin_write_NVM(); // Issue Unlock Sequence & Start Write Cycle while(NVMCONbits.WR=1); // Optional: Poll WR bit to wait for // write sequence to complete  2011-2013 Microchip Technology Inc. DS30001037C-page 57

PIC24F16KL402 FAMILY 6.4.3 READING THE DATA EEPROM A typical read sequence using the Table Pointer management (builtin_tblpage and To read a word from data EEPROM, the Table Read builtin_tbloffset) and Table Read instruction is used. Since the EEPROM array is only (builtin_tblrdl) procedures from the C30 compiler 16bits wide, only the TBLRDL instruction is needed. library is provided in Example6-5. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location Program Space Visibility (PSV) can also be used to followed by a TBLRDL instruction. read locations in the data EEPROM. EXAMPLE 6-5: READING THE DATA EEPROM USING THE TBLRD COMMAND int __attribute__ ((space(eedata))) eeData = 0x1234; // Global variable located in EEPROM int data; // Data read from EEPROM unsigned int offset; // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address data = __builtin_tblrdl(offset); // Write EEPROM data to write latch DS30001037C-page 58  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 7.0 RESETS Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU Note: This data sheet summarizes the features and peripherals are forced to a known Reset state. of this group of PIC24F devices. It is not Most registers are unaffected by a Reset; their status is intended to be a comprehensive refer- unknown on a Power-on Reset (POR) and unchanged ence source. For more information on by all other Resets. Resets, refer to the “dsPIC33/PIC24 Note: Refer to the specific peripheral or CPU Family Reference Manual”, “Reset with section of this manual for register Reset Programmable Brown-out Reset” states. (DS39728). The Reset module combines all Reset sources and All types of device Reset will set a corresponding status controls the device Master Reset Signal, SYSRST. The bit in the RCON register to indicate the type of Reset following is a list of device Reset sources: (see Register7-1). A POR will clear all bits except for the BOR and POR bits (RCON<1:0>) which are set. • POR: Power-on Reset The user may set or clear any bit at any time during • MCLR: Pin Reset code execution. The RCON bits only serve as status • SWR: RESET Instruction bits. Setting a particular Reset status bit in software will • WDTR: Watchdog Timer Reset not cause a device Reset to occur. • BOR: Brown-out Reset The RCON register also has other bits associated with • TRAPR: Trap Conflict Reset the Watchdog Timer (WDT) and device power-saving • IOPUWR: Illegal Opcode Reset states. The function of these bits is discussed in other • UWR: Uninitialized W Register Reset sections of this manual. A simplified block diagram of the Reset module is Note: The status bits in the RCON register shown in Figure7-1. should be cleared after they are read so that the next RCON register value, after a device Reset, will be meaningful. FIGURE 7-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise POR Detect SYSRST BOREN<1:0> VDD 0 00 Brown-out BOR SBOREN 01 Reset SLEEP 10 1 11 Configuration Mismatch Trap Conflict Illegal Opcode Uninitialized W Register  2011-2013 Microchip Technology Inc. DS30001037C-page 59

PIC24F16KL402 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0(3) U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR SBOREN — — — CM PMSLP bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or an Uninitialized W register is used as an Address Pointer and caused a Reset 0 = An illegal opcode or Uninitialized W register Reset has not occurred bit 13 SBOREN: Software Enable/Disable of BOR bit(3) 1 = BOR is turned on in software 0 = BOR is turned off in software bit 12-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred bit 8 PMSLP: Program Memory Power During Sleep bit 1 = Program memory bias voltage remains powered during Sleep 0 = Program memory bias voltage is powered down during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 3: The SBOREN bit is forced to ‘0’ when disabled by the Configuration bits, BOREN<1:0> (FPOR<1:0>). When the Configuration bits are set to enable SBOREN, the default Reset state will be ‘1’. DS30001037C-page 60  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set after a POR) 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 3: The SBOREN bit is forced to ‘0’ when disabled by the Configuration bits, BOREN<1:0> (FPOR<1:0>). When the Configuration bits are set to enable SBOREN, the default Reset state will be ‘1’. TABLE 7-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap Conflict Event POR IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR CM (RCON<9>) Configuration Mismatch Reset POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR IDLE (RCON<2>) PWRSAV #IDLE Instruction POR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits may be set or cleared by the user software. 7.1 Clock Source Selection at Reset TABLE 7-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK If clock switching is enabled, the system clock source at SWITCHING ENABLED) device Reset is chosen, as shown in Table7-2. If clock switching is disabled, the system clock source is always Reset Type Clock Source Determinant selected according to the oscillator Configuration bits. POR FNOSCx Configuration bits For more information, see Section9.0 “Oscillator Configuration”. BOR (FNOSC<10:8>) MCLR COSCx Control bits WDTO (OSCCON<14:12>) SWR  2011-2013 Microchip Technology Inc. DS30001037C-page 61

PIC24F16KL402 FAMILY 7.2 Device Reset Times The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after The Reset times for various types of device Reset are the SYSRST signal is released. summarized in Table7-3. Note that the System Reset Signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS System Clock Reset Type Clock Source SYSRST Delay Notes Delay POR(6) EC TPOR + TPWRT — 1, 2 FRC, FRCDIV TPOR + TPWRT TFRC 1, 2, 3 LPRC TPOR + TPWRT TLPRC 1, 2, 3 ECPLL TPOR + TPWRT TLOCK 1, 2, 4 FRCPLL TPOR + TPWRT TFRC + TLOCK 1, 2, 3, 4 XT, HS, SOSC TPOR+ TPWRT TOST 1, 2, 5 XTPLL, HSPLL TPOR + TPWRT TOST + TLOCK 1, 2, 4, 5 BOR EC TPWRT — 2 FRC, FRCDIV TPWRT TFRC 2, 3 LPRC TPWRT TLPRC 2, 3 ECPLL TPWRT TLOCK 2, 4 FRCPLL TPWRT TFRC + TLOCK 2, 3, 4 XT, HS, SOSC TPWRT TOST 2, 5 XTPLL, HSPLL TPWRT TFRC + TLOCK 2, 3, 4 All Others Any Clock — — None Note 1: TPOR = Power-on Reset delay. 2: TPWRT = 64 ms nominal if the Power-up Timer is enabled; otherwise, it is zero. 3: TFRC and TLPRC = RC oscillator start-up times. 4: TLOCK = PLL lock time. 5: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the oscillator clock to the system. 6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC, and in such cases, FRC start-up time is valid. Note: For detailed operating frequency and timing specifications, see Section26.0 “Electrical Characteristics”. DS30001037C-page 62  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 7.2.1 POR AND LONG OSCILLATOR 7.4 Brown-out Reset (BOR) START-UP TIMES PIC24F16KL402 family devices implement a BOR The oscillator start-up circuitry and its associated delay circuit, which provides the user several configuration timers are not linked to the device Reset delays that and power-saving options. The BOR is controlled by occur at power-up. Some crystal circuits (especially the BORV<1:0> and BOREN<1:0> Configuration bits low-frequency crystals) will have a relatively long (FPOR<6:5,1:0>). There are a total of four BOR start-up time. Therefore, one or more of the following configurations, which are provided in Table7-3. conditions is possible after SYSRST is released: The BOR threshold is set by the BORV<1:0> bits. If • The oscillator circuit has not begun to oscillate. BOR is enabled (any values of BOREN<1:0>, except • The Oscillator Start-up Timer (OST) has not ‘00’), any drop of VDD below the set threshold point will expired (if a crystal oscillator is used). reset the device. The chip will remain in BOR until VDD • The PLL has not achieved a lock (if PLL is used). rises above the threshold. The device will not begin to execute code until a valid If the Power-up Timer is enabled, it will be invoked after clock source has been released to the system. VDD rises above the threshold. Then, it will keep the chip Therefore, the oscillator and PLL start-up delays must in Reset for an additional time delay, TPWRT, if VDD be considered when the Reset delay time must be drops below the threshold while the power-up timer is known. running. The chip goes back into a BOR and the Power-up Timer will be initialized. Once VDD rises above 7.2.2 FAIL-SAFE CLOCK MONITOR the threshold, the Power-up Timer will execute the (FSCM) AND DEVICE RESETS additional time delay. If the FSCM is enabled, it will begin to monitor the BOR and the Power-up Timer (PWRT) are inde- system clock source when SYSRST is released. If a pendently configured. Enabling the BOR Reset does valid clock source is not available at this time, the not automatically enable the PWRT. device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator 7.4.1 SOFTWARE ENABLED BOR in the Trap Service Routine (TSR). When BOREN<1:0> = 01, the BOR can be enabled or 7.3 Special Function Register Reset disabled by the user in software. This is done with the States control bit, SBOREN (RCON<13>). Setting SBOREN enables the BOR to function, as previously described. Most of the Special Function Registers (SFRs) Clearing the SBOREN disables the BOR entirely. The associated with the PIC24F CPU and peripherals are SBOREN bit only operates in this mode; otherwise, it is reset to a particular value at a device Reset. The SFRs read as ‘0’. are grouped by their peripheral or CPU function and their Placing BOR under software control gives the user the Reset values are specified in each section of this manual. additional flexibility of tailoring the application to its The Reset value for each SFR does not depend on the environment without having to reprogram the device to type of Reset, with the exception of four registers. The change the BOR configuration. It also allows the user Reset value for the Reset Control register, RCON, will to tailor the incremental current that the BOR depend on the type of device Reset. The Reset value consumes. While the BOR current is typically very for the Oscillator Control register, OSCCON, will small, it may have some impact in low-power depend on the type of Reset and the programmed applications. values of the FNOSC bits in the Flash Configuration Word (FOSCSEL); see Table7-2. The RCFGCAL and Note: Even when the BOR is under software NVMCON registers are only affected by a POR. control, the BOR Reset voltage level is still set by the BORV<1:0> Configuration bits; it can not be changed in software.  2011-2013 Microchip Technology Inc. DS30001037C-page 63

PIC24F16KL402 FAMILY 7.4.2 DETECTING BOR 7.4.3 DISABLING BOR IN SLEEP MODE When BOR is enabled, the BOR bit (RCON<1>) is When BOREN<1:0> = 10, BOR remains under always reset to ‘1’ on any BOR or POR event. This hardware control and operates as previously makes it difficult to determine if a BOR event has described. However, whenever the device enters Sleep occurred just by reading the state of BOR alone. A mode, BOR is automatically disabled. When the device more reliable method is to simultaneously check the returns to any other operating mode, BOR is state of both POR and BOR. This assumes that the automatically re-enabled. POR and BOR bits are reset to ‘0’ in the software, This mode allows for applications to recover from immediately after any POR event. If the BOR bit is ‘1’ brown-out situations, while actively executing code while POR is ‘0’, it can be reliably assumed that a BOR when the device requires BOR protection the most. At event has occurred. the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. Note: Even when the device exits from Deep Sleep mode, both the POR and BOR are set. DS30001037C-page 64  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 8.0 INTERRUPT CONTROLLER 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE (AIVT) Note: This data sheet summarizes the features of The Alternate Interrupt Vector Table (AIVT) is located this group of PIC24F devices. It is not after the IVT, as shown in Figure8-1. Access to the AIVT intended to be a comprehensive reference is provided by the ALTIVT control bit (INTCON2<15>). If source. For more information on the Inter- the ALTIVT bit is set, all interrupt and exception rupt Controller, refer to the “dsPIC33/PIC24 processes will use the alternate vectors instead of the Family Reference Manual”, “Interrupts” default vectors. The alternate vectors are organized in (DS39707). the same manner as the default vectors. The PIC24F interrupt controller reduces the numerous The AIVT supports emulation and debugging efforts by peripheral interrupt request signals to a single interrupt providing a means to switch between an application request signal to the CPU. It has the following features: and a support environment without requiring the • Up to eight processor exceptions and interrupt vectors to be reprogrammed. This feature also software traps enables switching between applications for evaluation • Seven user-selectable priority levels of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with • Interrupt Vector Table (IVT) with up to 118 vectors the same addresses used in the IVT. • Unique vector for each interrupt or exception source 8.2 Reset Sequence • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug A device Reset is not a true exception, because the support interrupt controller is not involved in the Reset process. • Fixed interrupt entry and return latencies The PIC24F devices clear their registers in response to a Reset, which forces the Program Counter (PC) to 8.1 Interrupt Vector Table (IVT) zero. The microcontroller then begins program execution at location, 000000h. The user programs a The IVT is shown in Figure8-1. The IVT resides in the GOTO instruction at the Reset address, which redirects program memory, starting at location, 000004h. The the program execution to the appropriate start-up IVT contains 126 vectors, consisting of eight non-mas- routine. kable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Note: Any unimplemented or unused vector Each interrupt vector contains a 24-bit wide address. locations in the IVT and AIVT should be The value programmed into each interrupt vector loca- programmed with the address of a default tion is the starting address of the associated Interrupt interrupt handler routine that contains a Service Routine (ISR). RESET instruction. Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. PIC24F16KL402 family devices implement 32non-maskable traps and unique interrupts; these are summarized in Table8-1 and Table8-2.  2011-2013 Microchip Technology Inc. DS30001037C-page 65

PIC24F16KL402 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction 000000h Reset – GOTO Address 000002h Reserved 000004h Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000014h Interrupt Vector 1 — — — Interrupt Vector 52 00007Ch Interrupt Vector Table (IVT)(1) Interrupt Vector 53 00007Eh y orit Interrupt Vector 54 000080h Pri — er — d Or — al Interrupt Vector 116 0000FCh ur Interrupt Vector 117 0000FEh at N Reserved 000100h ng Reserved 000102h asi Reserved cre Oscillator Fail Trap Vector De Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000114h Interrupt Vector 1 — Alternate Interrupt Vector Table (AIVT)(1) — — Interrupt Vector 52 00017Ch Interrupt Vector 53 00017Eh Interrupt Vector 54 000180h — — — Interrupt Vector 116 Interrupt Vector 117 0001FEh Start of Code 000200h Note 1: See Table8-2 for the interrupt vector list. DS30001037C-page 66  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h Reserved 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector Interrupt Source IVT Address AIVT Address Number Flag Enable Priority ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0> External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0> External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4> MSSP1 Bus Collision Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4> MSSP1 SPI or I2C™ Event 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0> MSSP2 Bus Collision Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8> MSSP2 SPI or I2C Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4> Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12> HLVD (High/Low-Voltage Detect) 72 0000A4h 0001A4h IFS4<8> IEC4<8> IPC17<2:0> NVM (NVM Write Complete) 15 000032h 000132h IFS0<15> IEC0<15> IPC3<14:12> CCP1/ECCP1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8> CCP2 6 000020h 000120h IFS0<6> IEC0<6> IPC1<10:8> CCP3 25 000046h 000146h IFS1<9> IEC1<9> IPC6<6:4> Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12> Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12> Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0> Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12> Timer3 Gate External Count 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4> UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4> UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12> UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0> UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8> UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8> UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12> ULPW (Ultra Low-Power Wake-up) 80 0000B4h 0001B4h IFS5<0> IEC5<0> IPC20<2:0>  2011-2013 Microchip Technology Inc. DS30001037C-page 67

PIC24F16KL402 FAMILY 8.3 Interrupt Control and Status The INTTREG register contains the associated Registers interrupt vector number and the new CPU Interrupt Priority Level, which are latched into the Vector Depending on the particular device, the Number (VECNUM<6:0>) and the Interrupt Level PIC24F16KL402 family of devices implements up to (ILR<3:0>) bit fields in the INTTREG register. The new 28registers for the interrupt controller: Interrupt Priority Level is the priority of the pending • INTCON1 interrupt. • INTCON2 The interrupt sources are assigned to the IFSx, IECx • IFS0 through IFS5 and IPCx registers in the same sequence listed in • IEC0 through IEC5 Table8-2. For example, the INT0 (External Interrupt 0) • IPC0 through IPC7, ICP9, IPC12, ICP16, ICP18 is depicted as having a vector number and a natural and IPC20 order priority of 0. The INT0IF status bit is found in IFS0<0>, the INT0IE enable bit in IEC0<0> and the • INTTREG INT0IP<2:0> priority bits are in the first position of IPC0 Global interrupt control functions are controlled from (IPC0<2:0>). INTCON1 and INTCON2. INTCON1 contains the Although they are not specifically part of the interrupt Interrupt Nesting Disable (NSTDIS) bit, as well as the control hardware, two of the CPU control registers control and status flags for the processor trap sources. contain bits that control interrupt functionality. The ALU The INTCON2 register controls the external interrupt STATUS Register (SR) contains the IPL<2:0> bits request signal behavior and the use of the AIV table. (SR<7:5>). These indicate the current CPU Interrupt The IFSx registers maintain all of the interrupt request Priority Level. The user may change the current CPU flags. Each source of interrupt has a status bit, which is priority level by writing to the IPL bits. set by the respective peripherals or external signal, and The CORCON register contains the IPL3 bit, which is cleared via software. together with the IPL<2:0> bits, also indicates the cur- The IECx registers maintain all of the interrupt enable rent CPU priority level. IPL3 is a read-only bit so that bits. These control bits are used to individually enable the trap events cannot be masked by the user’s interrupts from the peripherals or external signals. software. The IPCx registers are used to set the Interrupt Priority All interrupt registers are described in Register8-3 Level for each source of interrupt. Each user interrupt through Register8-30, in the following sections. source can be assigned to one of eight priority levels. DS30001037C-page 68  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: See Register3-1 for the description of these bits, which are not dedicated to interrupt control functions. 2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1. 3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. Note: Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”.  2011-2013 Microchip Technology Inc. DS30001037C-page 69

PIC24F16KL402 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0 — — — — IPL3(2) PSV(1) — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 1-0 Unimplemented: Read as ‘0’ Note 1: See Register3-2 for the description of this bit, which is not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. Note: Bit 2 is described in Section 3.0 “CPU”. DS30001037C-page 70  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS30001037C-page 71

PIC24F16KL402 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Uses Alternate Interrupt Vector Table 0 = Uses standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS30001037C-page 72  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 NVMIF — AD1IF U1TXIF U1RXIF — — T3IF bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 T2IF CCP2IF — — T1IF CCP1IF — INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NVMIF: NVM Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 Unimplemented: Read as ‘0’ bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10-9 Unimplemented: Read as ‘0’ bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 CCP2IF: Capture/Compare/PWM2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 CCP1IF: Capture/Compare/PWM1 Interrupt Flag Status bit (ECCP1 on PIC24FXXKL40X devices) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 Unimplemented: Read as ‘0’ bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2011-2013 Microchip Technology Inc. DS30001037C-page 73

PIC24F16KL402 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U2TXIF(1) U2RXIF(1) INT2IF — T4IF(1) — CCP3IF(1) — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF CMIF BCL1IF SSP1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 Unimplemented: Read as ‘0’ bit 11 T4IF: Timer4 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 Unimplemented: Read as ‘0’ bit 9 CCP3IF: Capture/Compare/PWM3 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 BCL1IF: MSSP1 I2C™ Bus Collision Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SSP1IF: MSSP1 SPI/I2C Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. DS30001037C-page 74  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — T3GIF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 T3GIF: Timer3 External Gate Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-0 Unimplemented: Read as ‘0’ REGISTER 8-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — BCL2IF(1) SSP2IF(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 BCL2IF: MSSP2 I2C™ Bus Collision Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SSP2IF: MSSP2 SPI/I2C Event Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 75

PIC24F16KL402 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — U2ERIF(1) U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-3 Unimplemented: Read as ‘0’ bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: This bit is unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ULPWUIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS30001037C-page 76  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 NVMIE — AD1IE U1TXIE U1RXIE — — T3IE bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 T2IE CCP2IE — — T1IE CCP1IE — INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NVMIE: NVM Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 Unimplemented: Read as ‘0’ bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10-9 Unimplemented: Read as ‘0’ bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 CCP2IE: Capture/Compare/PWM2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 CCP1IE: Capture/Compare/PWM1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 Unimplemented: Read as ‘0’ bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2011-2013 Microchip Technology Inc. DS30001037C-page 77

PIC24F16KL402 FAMILY REGISTER 8-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U2TXIE(1) U2RXIE(1) INT2IE — T4IE(1) — CCP3IE(1) — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE CMIE BCL1IE SSP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 Unimplemented: Read as ‘0’ bit 11 T4IE: Timer4 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 Unimplemented: Read as ‘0’ bit 9 CCP3IE: Capture/Compare/PWM3 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8-5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 BCL1IE: MSSP1 I2C™ Bus Collision Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SSP1IE: MSSP1 SPI/I2C Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. DS30001037C-page 78  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — T3GIE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 T3GIF: Timer3 External Gate Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-0 Unimplemented: Read as ‘0’ REGISTER 8-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — BCL2IE(1) SSP2IE(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 BCL2IE: MSSP2 I2C™ Bus Collision Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 SSP2IF: MSSP2 SPI/I2C Event Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 79

PIC24F16KL402 FAMILY REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — U2ERIE(1) U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7-3 Unimplemented: Read as ‘0’ bit 2 U2ERIE: UART2 Error Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: This bit is unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. REGISTER 8-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ULPWUIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable Bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS30001037C-page 80  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — CCP1IP2 CCP1IP1 CCP1IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CCP1IP<2:0>: Capture/Compare/PWM1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2013 Microchip Technology Inc. DS30001037C-page 81

PIC24F16KL402 FAMILY REGISTER 8-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — CCP2IP2 CCP2IP1 CCP2IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CCP2IP<2:0>: Capture/Compare/PWM2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS30001037C-page 82  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1RXIP2 U1RXIP1 U1RXIP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2013 Microchip Technology Inc. DS30001037C-page 83

PIC24F16KL402 FAMILY REGISTER 8-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP<2:0>: NVM Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30001037C-page 84  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — BCL1IP2 BCL1IP1 BCL1IP0 — SSP1IP2 SSP1IP1 SSP1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 BCL1IP<2:0>: MSSP1 I2C™ Bus Collision Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SSP1IP<2:0>: MSSP1 SPI/I2C Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2013 Microchip Technology Inc. DS30001037C-page 85

PIC24F16KL402 FAMILY REGISTER 8-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30001037C-page 86  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T4IP2(1) T4IP1(1) T4IP0(1) — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CCP3IP2(1) CCP3IP1(1) CCP3IP0(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 CCP3IP: Capture/Compare/PWM3 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 87

PIC24F16KL402 FAMILY REGISTER 8-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2(1) U2TXIP1(1) U2TXIP0(1) — U2RXIP2(1) U2RXIP1(1) U2RXIP0(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT2IP2 INT2IP1 INT2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. DS30001037C-page 88  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-25: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T3GIP2 T3GIP1 T3GIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 T3GIP<2:0>: Timer3 External Gate Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS30001037C-page 89

PIC24F16KL402 FAMILY REGISTER 8-26: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — BCL2IP2(1) BCL2IP1(1) BCL2IP0(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SSP2IP2(1) SSP2IP1(1) SSP2IP0(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 BCL2IP<2:0>: MSSP2 I2C™ Bus Collision Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SSP2IP<2:0>: MSSP2 SPI/I2C Event Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices. DS30001037C-page 90  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — U2ERIP2(1) U2ERIP1(1) U2ERIP0(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2(1) U1ERIP1(1) U1ERIP0(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 91

PIC24F16KL402 FAMILY REGISTER 8-28: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 8-29: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — ULPWUIP2 ULPWUIP1 ULPWUIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 6-4 ULPWUIP<2:0>: Ultra Low-Power Wake-up Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30001037C-page 92  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 8-30: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 r-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ r VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will happen when the CPU priority is higher than the interrupt priority) 0 = No interrupt request is left unacknowledged bit 14 Reserved: Maintain as ‘0’ bit 13 VHOLD: Vector Hold bit Allows Vector Number Capture and Changes What Interrupt is Stored in the VECNUM bit: 1 = VECNUM<6:0> will contain the value of the highest priority pending interrupt, instead of the current interrupt 0 = VECNUM<6:0> will contain the value of the last Acknowledged interrupt (last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is Number 135 • • • 0000001 = Interrupt vector pending is Number 9 0000000 = Interrupt vector pending is Number 8  2011-2013 Microchip Technology Inc. DS30001037C-page 93

PIC24F16KL402 FAMILY 8.4 Interrupt Setup Procedures 8.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, 8.4.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. 8.4.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the All user interrupts can be disabled using the following appropriate IPCx register. The priority level will procedure: depend on the specific application and the type 1. Push the current SR value onto the software of interrupt source. If multiple priority levels are stack using the PUSH instruction. not desired, the IPCx register control bits, for all 2. Force the CPU to Priority Level 7 by inclusive enabled interrupt sources, may be programmed ORing the value, OEh, with SRL. to the same non-zero value. To enable user interrupts, the POP instruction may be Note: At a device Reset, the IPCx registers are used to restore the previous SR value. initialized, such that all user interrupt Only user interrupts with a priority level of 7 or less can sources are assigned to Priority Level 4. be disabled. Trap sources (Levels8-15) cannot be 3. Clear the interrupt flag status bit associated with disabled. the peripheral in the associated IFSx register. The DISI instruction provides a convenient way to 4. Enable the interrupt source by setting the disable interrupts of Priority Levels 1-6 for a fixed interrupt enable control bit associated with the period. Level 7 interrupt sources are not disabled by source in the appropriate IECx register. the DISI instruction. 8.4.2 INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR and initialize the IVT with the correct vector address depends on the programming language (i.e., C or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS30001037C-page 94  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 9.0 OSCILLATOR • Software-controllable switching between various CONFIGURATION clock sources. • Software-controllable postscaler for selective Note: This data sheet summarizes the features clocking of CPU for system power savings. of this group of PIC24F devices. It is not • System frequency range declaration bits for EC intended to be a comprehensive refer- mode. When using an external clock source, the ence source. For more information on current consumption is reduced by setting the Oscillator Configuration, refer to the declaration bits to the expected frequency range. “dsPIC33/PIC24 Family Reference • A Fail-Safe Clock Monitor (FSCM) that detects clock Manual”, “Oscillator with 500 kHz failure and permits safe application recovery or Low-Power FRC” (DS39726). shutdown. The oscillator system for the PIC24F16KL402 family of A simplified diagram of the oscillator system is shown in devices has the following features: Figure9-1. • A total of five external and internal oscillator options as clock sources, providing 11 different clock modes. • On-chip, 4x Phase Locked Loop (PLL) to boost internal operating frequency on select internal and external oscillator sources. FIGURE 9-1: PIC24F16KL402 FAMILY CLOCK DIAGRAM Primary Oscillator REFOCON<15:8> XT, HS, EC OSCO Reference Clock Generator OSCI XTPLL, HSPLL, ECPLL, FRCPLL 4 x PLL REFO 8 MHz er 4 MHz 8 MHz al FRCDIV FRC sc Oscillator st o P Peripherals 500 kHz CLKDIV<10:8> FRC LPFRC Oscillator CLKO LPRC LPRC er Oscillator 31 kHz (nominal) al CPU c s st Secondary Oscillator Po SOSC SOSCO CLKDIV<14:12> SOSCEN Enable SOSCI Oscillator Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT, DSWDT Clock Source Option for Other Modules  2011-2013 Microchip Technology Inc. DS30001037C-page 95

PIC24F16KL402 FAMILY 9.1 CPU Clocking Scheme 9.2 Initial Configuration on POR The system clock source can be provided by one of The oscillator source (and operating mode) that is used four sources: at a device Power-on Reset (POR) event is selected using Configuration bit settings. The Oscillator • Primary Oscillator (POSC) on the OSCI and Configuration bit settings are located in the Configuration OSCO pins registers in the program memory (for more information, • Secondary Oscillator (SOSC) on the SOSCI and see Section23.2 “Configuration Bits”). The Primary SOSCO pins Oscillator Configuration bits, POSCMD<1:0> PIC24F16KL402 family devices consist of two (FOSC<1:0>), and the Initial Oscillator Select types of secondary oscillators: Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), - High-Power Secondary Oscillator select the oscillator source that is used at a POR. The - Low-Power Secondary Oscillator FRC Primary Oscillator with Postscaler (FRCDIV) is the These can be selected by using the SOSCSEL default (unprogrammed) selection. The secondary (FOSC<5>) bit. oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The EC • Fast Internal RC (FRC) Oscillator mode Frequency Range Configuration bits, - 8 MHz FRC Oscillator POSCFREQ<1:0> (FOSC<4:3>), optimize power - 500 kHz Lower Power FRC Oscillator consumption when running in EC mode. The default • Low-Power Internal RC (LPRC) Oscillator with two configuration is “frequency range is greater than 8MHz”. modes: The Configuration bits allow users to choose between - High-Power/High-Accuracy mode the various clock modes, shown in Table9-1. - Low-Power/Low-Accuracy mode 9.2.1 CLOCK SWITCHING MODE The primary oscillator and 8 MHz FRC sources have the CONFIGURATION BITS option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the pro- The FCKSMx Configuration bits (FOSC<7:6>) are grammable clock divider. The selected clock source used jointly to configure device clock switching and the generates the processor and peripheral clock sources. FSCM. Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when The processor clock source is divided by two to produce FCKSM<1:0> are both programmed (‘00’). the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the primary oscillator. TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Notes 8 MHz FRC Oscillator with Postscaler (FRCDIV) Internal 11 111 1, 2 500 kHz FRC Oscillator with Postscaler Internal 11 110 1 (LPFRCDIV) Low-Power RC Oscillator (LPRC) Internal 11 101 1 Secondary (Timer1) Oscillator (SOSC) Secondary 00 100 1 Primary Oscillator (HS) with PLL Module Primary 10 011 (HSPLL) Primary Oscillator (EC) with PLL Module (ECPLL) Primary 00 011 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 8 MHz FRC Oscillator with PLL Module Internal 11 001 1 (FRCPLL) 8 MHz FRC Oscillator (FRC) Internal 11 000 1 Note 1: OSCO pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. DS30001037C-page 96  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 9.3 Control Registers The Clock Divider register (Register9-2) controls the features associated with Doze mode, as well as the The operation of the oscillator is controlled by three postscaler for the FRC oscillator. Special Function Registers (SFRs): The FRC Oscillator Tune register (Register9-3) allows • OSCCON the user to fine-tune the FRC oscillator. OSCTUN • CLKDIV functionality has been provided to help customers com- • OSCTUN pensate for temperature effects on the FRC frequency The OSCCON register (Register9-1) is the main over a wide range of temperatures. The tuning step-size control register for the oscillator. It controls clock is an approximation and is neither characterized nor source switching and allows the monitoring of clock tested. sources. REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0, HSC R-0, HSC R-0, HSC U-0 R/W-x(1) R/W-x(1) R/W-x(1) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/SO-0, HSC U-0 R-0, HSC(2) U-0 R/CO-0, HS R/W-0(3) R/W-0 R/W-0 CLKLOCK — LOCK — CF SOSCDRV SOSCEN OSWEN bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit HS = Hardware Settable bit CO = Clearable Only bit SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV) 110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL) 000 = 8 MHz FRC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1) 111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV) 110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL) 000 = 8 MHz FRC Oscillator (FRC) Note 1: Reset values for these bits are determined by the FNOSC<2:0> Configuration bits. 2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 3: When SOSC is selected to run from a digital clock input rather than an external crystal (SOSCSRC=0), this bit has no effect.  2011-2013 Microchip Technology Inc. DS30001037C-page 97

PIC24F16KL402 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enable bit If FSCM is Enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is Disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 Unimplemented: Read as ‘0’ bit 5 LOCK: PLL Lock Status bit(2) 1 = PLL module is in lock or the PLL module start-up timer is satisfied 0 = PLL module is out of lock, the PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 SOSCDRV: Secondary Oscillator Drive Strength bit(3) 1 = High-power SOSC circuit is selected 0 = Low/high-power select is done via the SOSCSRC Configuration bit bit 1 SOSCEN: 32kHz Secondary Oscillator (SOSC) Enable bit 1 = Enables secondary oscillator 0 = Disables secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiates an oscillator switch to the clock source specified by the NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Reset values for these bits are determined by the FNOSC<2:0> Configuration bits. 2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 3: When SOSC is selected to run from a digital clock input rather than an external crystal (SOSCSRC=0), this bit has no effect. DS30001037C-page 98  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit, and reset the CPU and peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: CPU-to-Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: DOZE Enable bit(1) 1 = DOZE<2:0> bits specify the CPU-to-peripheral clock ratio 0 = CPU and the peripheral clock ratio are set to 1:1 bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits When COSC<2:0> (OSCCON<14:12) = 111 or 001: 111 = 31.25 kHz (divide-by-256) 110 = 125 kHz (divide-by-64) 101 = 250 kHz (divide-by-32) 100 = 500 kHz (divide-by-16) 011 = 1 MHz (divide-by-8) 010 = 2 MHz (divide-by-4) 001 = 4 MHz (divide-by-2) (default) 000 = 8 MHz (divide-by-1) When COSC<2:0> (OSCCON<14:12>) = 110: 111 = 1.95 kHz (divide-by-256) 110 = 7.81 kHz (divide-by-64) 101 = 15.62 kHz (divide-by-32) 100 = 31.25 kHz (divide-by-16) 011 = 62.5 kHz (divide-by-8) 010 = 125 kHz (divide-by-4) 001 = 250 kHz (divide-by-2) (default) 000 = 500 kHz (divide-by-1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.  2011-2013 Microchip Technology Inc. DS30001037C-page 99

PIC24F16KL402 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 • • • 000001 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 • • • 100001 100000 = Minimum frequency deviation Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. DS30001037C-page 100  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 9.4 Clock Switching Operation Once the basic sequence is completed, the system clock hardware responds automatically, as follows: With few limitations, applications are free to switch 1. The clock switching hardware compares the between any of the four clock sources (POSC, SOSC, COSCx bits with the new value of the NOSCx FRC and LPRC) under software control and at any bits. If they are the same, then the clock switch time. To limit the possible side effects that could result is a redundant operation. In this case, the from this flexibility, PIC24F devices have a safeguard OSWEN bit is cleared automatically and the lock built into the switching process. clock switch is aborted. Note: The Primary Oscillator mode has three 2. If a valid clock switch has been initiated, the different submodes (XT, HS and EC), LOCK (OSCCON<5>) and CF (OSCCON<3>) which are determined by the POSCMDx bits are cleared. Configuration bits. While an application 3. The new oscillator is turned on by the hardware can switch to and from Primary Oscillator if it is not currently running. If a crystal oscillator mode in software, it cannot switch must be turned on, the hardware will wait until between the different primary submodes the OST expires. If the new source is using the without reprogramming the device. PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). 9.4.1 ENABLING CLOCK SWITCHING 4. The hardware waits for 10 clock cycles from the To enable clock switching, the FCKSM1 Configuration bit new clock source and then performs the clock in the FOSC Configuration register must be programmed switch. to ‘0’. (Refer to Section23.0 “Special Features” for 5. The hardware clears the OSWEN bit to indicate a further details.) If the FCKSM1 Configuration bit is successful clock transition. In addition, the unprogrammed (‘1’), the clock switching function and NOSCx bits value is transferred to the COSCx FSCM function are disabled; this is the default setting. bits. The NOSCx control bits (OSCCON<10:8>) do not 6. The old clock source is turned off at this time, control the clock selection when clock switching is with the exception of LPRC (if WDT or FSCM, disabled. However, the COSCx bits (OSCCON<14:12>) with LPRC as a clock source, are enabled) or will reflect the clock source selected by the FNOSCx SOSC (if SOSCEN remains enabled). Configuration bits. Note1: The processor will continue to execute The OSWEN control bit (OSCCON<0>) has no effect code throughout the clock switching when clock switching is disabled; it is held at ‘0’ at all sequence. Timing-sensitive code should times. not be executed during this time. 9.4.2 OSCILLATOR SWITCHING 2: Direct clock switches between any SEQUENCE Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This At a minimum, performing a clock switch requires this applies to clock switches in either direc- basic sequence: tion. In these instances, the application 1. If desired, read the COSCx bits must switch to FRC mode as a transition (OSCCON<14:12>) to determine the current clock source between the two PLL modes. oscillator source. 2. Perform the unlock sequence to allow a write to the OSCCON register high byte. 3. Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source. 4. Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch.  2011-2013 Microchip Technology Inc. DS30001037C-page 101

PIC24F16KL402 FAMILY The following code sequence for a clock switch is 9.5 Reference Clock Output recommended: In addition to the CLKO output (FOSC/2) available in 1. Disable interrupts during the OSCCON register certain oscillator modes, the device clock in the unlock and write sequence. PIC24F16KL402 family devices can also be configured 2. Execute the unlock sequence for the OSCCON to provide a reference clock output signal to a port pin. high byte by writing 78h and 9Ah to This feature is available in all oscillator configurations OSCCON<15:8>, in two back-to-back and allows the user to select a greater range of clock instructions. submultiples to drive external devices in the 3. Write the new oscillator source to the NOSCx application. bits in the instruction immediately following the This reference clock output is controlled by the unlock sequence. REFOCON register (Register9-4). Setting the ROEN 4. Execute the unlock sequence for the OSCCON bit (REFOCON<15>) makes the clock signal available low byte by writing 46h and 57h to on the REFO pin. The RODIV bits (REFOCON<11:8>) OSCCON<7:0>, in two back-to-back instructions. enable the selection of 16 different clock divider 5. Set the OSWEN bit in the instruction immediately options. following the unlock sequence. The ROSSLP and ROSEL bits (REFOCON<13:12>) 6. Continue to execute code that is not control the availability of the reference output during clock-sensitive (optional). Sleep mode. The ROSEL bit determines if the oscillator 7. Invoke an appropriate amount of software delay on OSC1 and OSC2, or the current system clock (cycle counting) to allow the selected oscillator source, is used for the reference clock output. The and/or PLL to start and stabilize. ROSSLP bit determines if the reference source is 8. Check to see if OSWEN is ‘0’. If it is, the switch available on REFO when the device is in Sleep mode. was successful. If OSWEN is still set, then check To use the reference clock output in Sleep mode, both the LOCK bit to determine the cause of failure. the ROSSLP and ROSEL bits must be set. The device The core sequence for unlocking the OSCCON register clock must also be configured for one of the primary and initiating a clock switch is shown in Example9-1. modes (EC, HS or XT). Therefore, if the ROSEL bit is also not set, the oscillator on OSC1 and OSC2 will be EXAMPLE 9-1: BASIC CODE SEQUENCE powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output FOR CLOCK SWITCHING frequency to change as the system clock changes ;Place the new oscillator selection in W0 during any clock switches. ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 DS30001037C-page 102  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator is enabled on REFO pin 0 = Reference oscillator is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator is used as the base clock(1) 0 = System clock is used as the base clock; the base clock reflects any clock switching of the device bit 11-8 RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.  2011-2013 Microchip Technology Inc. DS30001037C-page 103

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 104  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 10.0 POWER-SAVING FEATURES 10.1 Clock Frequency and Clock Switching Note: This data sheet summarizes the features of this group of PIC24F devices. It is not PIC24F devices allow for a wide range of clock intended to be a comprehensive frequencies to be selected under application control. If reference source. For more information the system clock configuration is not locked, users can on Power-Saving Features, refer to the choose low-power or high-precision oscillators by simply “dsPIC33/PIC24 Family Reference changing the NOSCx bits. The process of changing a Manual”, “Power-Saving Features with system clock during operation, as well as limitations to Deep Sleep” (DS39727). the process, are discussed in more detail in Section9.0 “Oscillator Configuration”. The PIC24F16KL402 family of devices provides the ability to manage power consumption by selectively 10.2 Instruction-Based Power-Saving managing clocking to the CPU and the peripherals. In Modes general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower PIC24F devices have two special power-saving modes consumed power. All PIC24F devices manage power that are entered through the execution of a special consumption using several strategies: PWRSAV instruction. Sleep mode stops clock operation • Clock frequency and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to • Instruction-based Idle and Sleep modes continue operation. • Hardware-based periodic wake-up from Sleep The assembly syntax of the PWRSAV instruction is • Software Controlled Doze mode shown in Example10-1. • Selective peripheral control in software Note: SLEEP_MODE and IDLE_MODE are Combinations of these methods can be used to constants defined in the assembler selectively tailor an application’s power consumption, include file for the selected device. while still maintaining critical application features, such as timing-sensitive communications. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2011-2013 Microchip Technology Inc. DS30001037C-page 105

PIC24F16KL402 FAMILY 10.2.1 SLEEP MODE 10.2.2 IDLE MODE Sleep mode includes these features: Idle mode has these features: • The system clock source is shut down. If an • The CPU will stop executing instructions. on-chip oscillator is used, it is turned off. • The WDT is automatically cleared. • The device current consumption will be reduced • The system clock source remains active. By to a minimum, provided that no I/O pin is sourcing default, all peripheral modules continue to operate current. normally from the system clock source, but can • The I/O pin directions and states are frozen. also be selectively disabled (see Section10.5 “Selective Peripheral Module Control”). • The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source • If the WDT or FSCM is enabled, the LPRC will is disabled. also remain active. • The LPRC clock will continue to run in Sleep The device will wake from Idle mode on any of these mode if any active module has selected the LPRC events: as its source, including the WDT, Timer1 and • Any interrupt that is individually enabled Timer3. • Any device Reset • The WDT, if enabled, is automatically cleared • A WDT time-out prior to entering Sleep mode. • Some device features, or peripherals, may On wake-up from Idle, the clock is re-applied to the continue to operate in Sleep mode. This includes CPU. Instruction execution begins immediately, start- items, such as the Input Change Notification ing with the instruction following the PWRSAV instruction (ICN) on the I/O ports or peripherals that use an or the first instruction in the ISR. external clock input. Any peripheral that requires 10.2.3 INTERRUPTS COINCIDENT WITH the system clock source for its operation will be POWER SAVE INSTRUCTIONS disabled in Sleep mode. Any interrupt that coincides with the execution of a The device will wake-up from Sleep mode on any of PWRSAV instruction will be held off until entry into Sleep these events: or Idle mode has completed. The device will then • On any interrupt source that is individually wake-up from Sleep or Idle mode. enabled • On any form of device Reset • On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered. DS30001037C-page 106  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 10.3 Ultra Low-Power Wake-up See Example10-2 for initializing the ULPWU module. A series resistor, between RB0 and the external The Ultra Low-Power Wake-up (ULPWU) on pin, RB0, capacitor, provides overcurrent protection for the allows a slow falling voltage to generate an interrupt RB0/AN2/ULPWU pin and enables software calibration without excess current consumption. This feature of the time-out (see Figure10-1). provides a low-power technique for periodically waking up the device from Sleep mode. FIGURE 10-1: SERIES RESISTOR To use this feature: R 1. Charge the capacitor on RB0 by configuring the 1 RB0 RB0 pin to an output and setting it to ‘1’. 2. Stop charging the capacitor by configuring RB0 as an input. C 1 3. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the ULPWCON register. 4. Configure Sleep mode. 5. Enter Sleep mode. A timer can be used to measure the charge time and The time-out is dependent on the discharge time of the discharge time of the capacitor. The charge time can RC circuit on RB0. When the voltage on RB0 drops then be adjusted to provide the desired delay in Sleep. below VIL, the device wakes up and executes the next This technique compensates for the affects of tempera- instruction. ture, voltage and component accuracy. The peripheral When the ULPWU module wakes the device from can also be configured as a simple, programmable Sleep mode, the ULPWUIF bit (IFS5<0>) is set. Soft- Low-Voltage Detect (LVD) or temperature sensor. ware can check this bit upon wake-up to determine the wake-up source. EXAMPLE 10-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION //****************************************************************************** // 1. Charge the capacitor on RB0 //****************************************************************************** TRISBbits.TRISB0 = 0; LATBbits.LATB0 = 1; for(i = 0; i < 10000; i++) Nop(); //****************************************************************************** //2. Stop Charging the capacitor on RB0 //****************************************************************************** TRISBbits.TRISB0 = 1; //****************************************************************************** //3. Enable ULPWU Interrupt //****************************************************************************** IFS5bits.ULPWUIF = 0; IEC5bits.ULPWUIE = 1; IPC20bits.ULPWUIP = 0x7; //****************************************************************************** //4. Enable the Ultra Low Power Wakeup module and allow capacitor discharge //****************************************************************************** ULPWCONbits.ULPEN = 1; ULPWCONbits.ULPSINK = 1; //****************************************************************************** //5. Enter Sleep Mode //****************************************************************************** Sleep(); //for Sleep, execution will resume here  2011-2013 Microchip Technology Inc. DS30001037C-page 107

PIC24F16KL402 FAMILY REGISTER 10-1: ULPWCON: ULPWU CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 ULPEN — ULPSIDL — — — — ULPSINK bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ULPEN: ULPWU Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ULPSIDL: ULPWU Stop in Idle Select bit 1 = Discontinues module operation when the device enters Idle mode 0 = Continues module operation in Idle mode bit 12-9 Unimplemented: Read as ‘0’ bit 8 ULPSINK: ULPWU Current Sink Enable bit 1 = Current sink is enabled 0 = Current sink is disabled bit 7-0 Unimplemented: Read as ‘0’ DS30001037C-page 108  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 10.4 Doze Mode 10.5 Selective Peripheral Module Control Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies Idle and Doze modes allow users to substantially for reducing power consumption. There may be reduce power consumption by slowing or stopping the circumstances, however, where this is not practical. For CPU clock. Even so, peripheral modules still remain example, it may be necessary for an application to clocked and thus, consume power. There may be maintain uninterrupted, synchronous communication, cases where the application needs what these modes even while it is doing nothing else. Reducing system do not provide: the allocation of power resources to clock speed may introduce communication errors, CPU processing, with minimal power consumption while using a power-saving mode may stop from the peripherals. communications completely. PIC24F devices address this requirement by allowing Doze mode is a simple and effective alternative method peripheral modules to be selectively disabled, reducing to reduce power consumption while the device is still or eliminating their power consumption. This can be executing code. In this mode, the system clock done with two control bits: continues to operate from the same source and at the • The Peripheral Enable bit, generically named, same speed. Peripheral modules continue to be “XXXEN”, located in the module’s main control clocked at the same speed, while the CPU clock speed SFR. is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to • The Peripheral Module Disable (PMD) bit, access the SFRs while the CPU executes code at a generically named, “XXXMD”, located in one of slower rate. the PMD Control registers. Doze mode is enabled by setting the DOZEN bit Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the state, the control and status registers associated with default. the peripheral will also be disabled, so writes to those registers will have no effect, and read values will be It is also possible to use Doze mode to selectively reduce invalid. Many peripheral modules have a corresponding power consumption in event driven applications. This PMD bit. allows clock-sensitive functions, such as synchronous communications, to continue without interruption. Mean- In contrast, disabling a module by clearing its XXXEN bit, disables its functionality, but leaves its registers while, the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to available to be read and written to. Power consumption full-speed CPU operation on interrupts is enabled by is reduced, but not by as much as when the PMD bits setting the ROI bit (CLKDIV<15>). By default, interrupt are used. events have no effect on Doze mode operation. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, “XXXIDL”. By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature disables the module while in Idle mode, allowing further reduction of power consumption during Idle mode. This enhances power savings for extremely critical power applications.  2011-2013 Microchip Technology Inc. DS30001037C-page 109

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 110  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 11.0 I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as Note: This data sheet summarizes the features of a general purpose output pin is disabled. The I/O pin this group of PIC24F devices. It is not may be read, but the output driver for the parallel port intended to be a comprehensive reference bit will be disabled. If a peripheral is enabled, but the source. For more information on the I/O peripheral is not actively driving a pin, that pin may be Ports, refer to the “dsPIC33/PIC24 Family driven by a port. Reference Manual”, “I/O Ports with All port pins have three registers directly associated Peripheral Pin Select (PPS)” (DS39711). with their operation as digital I/O. The Data Direction Note that the PIC24F16KL402 family register (TRISx) determines whether the pin is an input devices do not support Peripheral Pin or an output. If the data direction bit is a ‘1’, then the pin Select features. is an input. All port pins are defined as inputs after a Reset. Reads from the Data Latch register (LATx), read All of the device pins (except VDD and VSS) are shared the latch. Writes to the Data Latch, write the latch. between the peripherals and the parallel I/O ports. All Reads from the port (PORTx), read the port pins, while I/O input ports feature Schmitt Trigger inputs for writes to the port pins, write the latch. improved noise immunity. Any bit and its associated data and control registers, 11.1 Parallel I/O (PIO) Ports that are not valid for a particular device, will be dis- abled. That means the corresponding LATx and TRISx A parallel I/O port that shares a pin with a peripheral is, registers, and the port pin will read as zeros. in general, subservient to the peripheral. The When a pin is shared with another peripheral or func- peripheral’s output buffer data and control signals are tion that is defined as an input only, it is nevertheless, provided to a pair of multiplexers. The multiplexers regarded as a dedicated port because there is no select whether the peripheral or the associated port other competing source of outputs. has ownership of the output data and control signals of the I/O pin. Figure11-1 illustrates how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED I/O PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + CK WR PORT Data Latch Read LAT Input Data Read PORT  2011-2013 Microchip Technology Inc. DS30001037C-page 111

PIC24F16KL402 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION When reading the PORTx register, all pins configured as analog input channels will read as cleared (a low In addition to the PORTx, LATx and TRISx registers for level). Analog levels on any pin that is defined as a dig- data control, each port pin can be individually ital input (including the ANx pins) may cause the input configured for either digital or open-drain output. This is buffer to consume current that exceeds the device controlled by the Open-Drain Control register, ODCx, specifications. associated with each port. Setting any of the bits configures the corresponding pin to act as an 11.2.1 ANALOG SELECTION REGISTER open-drain output. I/O pins with shared analog functionality, such as A/D The maximum open-drain voltage allowed is the same inputs and comparator inputs, must have their digital as the maximum VIH specification. inputs shut off when analog functionality is used. Note that analog functionality includes an analog voltage 11.1.2 I/O PORT WRITE/READ TIMING being applied to the pin externally. One instruction cycle is required between a port To allow for analog control, the ANSx registers are direction change or port write operation and a read provided. There is one ANS register for each port operation of the same port. Typically, this instruction (ANSA and ANSB, Register11-1 and Register11-2). would be a NOP. Within each ANSx register, there is a bit for each pin that shares analog functionality with the digital I/O 11.2 Configuring Analog Port Pins functionality. If a particular pin does not have an analog The use of the ANSx and TRISx registers control the function, that bit is unimplemented. operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRISx bit set (input). If the TRISx bit is cleared (output), the digital output level (VOH or VOL) will be converted. DS30001037C-page 112  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 11-1: ANSA: PORTA ANALOG SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 ANSA<3:0>: Analog Select Control bits 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active REGISTER 11-2: ANSB: PORTB ANALOG SELECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 ANSB15 ANSB14 ANSB13(1) ANSB12(1) — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — ANSB4 ANSB3(2) ANSB2(1) ANSB1(1) ANSB0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 ANSB<15:12>: Analog Select Control bits(1) 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active bit 11-5 Unimplemented: Read as ‘0’ bit 4-0 ANSB<4:0>: Analog Select Control bits(2) 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active Note 1: ANSB<13:12,2:0> are unimplemented on 14-pin devices. 2: ANSB<3> is unimplemented on 14-pin and 20-pin devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 113

PIC24F16KL402 FAMILY 11.3 Input Change Notification On any pin, only the pull-up resistor or the pull-down resistor should be enabled, but not both of them. If the The Input Change Notification (ICN) function of the I/O push button or the keypad is connected to VDD, enable ports allows the PIC24F16KL402 family of devices to the pull-down, or if they are connected to VSS, enable generate interrupt requests to the processor in response the pull-up resistors. The pull-ups are enabled sepa- to a Change-of-State (COS) on selected input pins. This rately using the CNPU1 and CNPU2 registers, which feature is capable of detecting input Change-of-States, contain the control bits for each of the CN pins. even in Sleep mode, when the clocks are disabled. Setting any of the control bits enables the weak Depending on the device pin count, there are up to pull-ups for the corresponding pins. The pull-downs are 23external signals that may be selected (enabled) for enabled separately, using the CNPD1 and CNPD2 generating an interrupt request on a Change-of-State. registers, which contain the control bits for each of the There are six control registers associated with the CN pins. Setting any of the control bits enables the Change Notification (CN) module. The CNEN1 and weak pull-downs for the corresponding pins. CNEN2 registers contain the interrupt enable control bits for each of the CN input pins. Setting any of these When the internal pull-up is selected, the pin uses VDD as the pull-up source voltage. When the internal bits enables a CN interrupt for the corresponding pins. pull-down is selected, the pins are pulled down to VSS Each CN pin also has a weak pull-up/pull-down by an internal resistor. Make sure that there is no exter- connected to it. The pull-ups act as a current source nal pull-up source/pull-down sink when the internal that is connected to the pin. The pull-downs act as a pull-ups/pull-downs are enabled. current sink to eliminate the need for external resistors when push button or keypad devices are connected. Note: Pull-ups and pull-downs on Change Notifi- cation pins should always be disabled whenever the port pin is configured as a digital output. EXAMPLE 11-1: PORT WRITE/READ EXAMPLE (ASSEMBLY LANGUAGE) MOV #0xFF00, W0 ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs MOV W0, TRISB MOV #0x00FF, W0 ; Enable PORTB<15:8> digital input buffers MOV W0, ANSB NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction EXAMPLE 11-2: PORT WRITE/READ EXAMPLE (C LANGUAGE) TRISB = 0xFF00; // Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs ANSB = 0x00FF; // Enable PORTB<15:8> digital input buffers NOP(); // Delay 1 cycle if(PORTBbits.RB13 == 1) // execute following code if PORTB pin 13 is set. { } DS30001037C-page 114  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 12.0 TIMER1 Figure12-1 illustrates a block diagram of the 16-bit Timer1 module. Note: This data sheet summarizes the features of To configure Timer1 for operation: this group of PIC24F devices. It is not intended to be a comprehensive reference 1. Set the TON bit (= 1). source. For more information on Timers, 2. Select the timer prescaler ratio using the refer to the “dsPIC33/PIC24 Family TCKPS<1:0> bits. Reference Manual”, “Timers” (DS39704). 3. Set the Clock and Gating modes using the TCS and TGATE bits. The Timer1 module is a 16-bit timer which can operate 4. Set or clear the TSYNC bit to configure as a free-running, interval timer/counter, or serve as the synchronous or asynchronous operation. time counter for a software-based Real-Time Clock (RTC). Timer1 is only reset on initial VDD power-on 5. Load the timer period value into the PR1 events. This allows the timer to continue operating as an register. RTC clock source through other types of device Reset. 6. If interrupts are required, set the Timer1 Interrupt Enable bit, T1IE. Use the Timer1 Interrupt Priority Timer1 can operate in three modes: bits, T1IP<2:0>, to set the interrupt priority. • 16-Bit Timer • 16-Bit Synchronous Counter • 16-Bit Asynchronous Counter Timer1 also supports these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation During CPU Idle and Sleep modes • Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TECS<1:0> LPRC TCKPS<1:0> TON 2 SOSCO Gate Prescaler Sync 1, 8, 64, 256 SOSCI SOSCEN TGATE T1CK TCS FOSC/2 TGATE Q D Set T1IF Q CK Reset TMR1 Sync Comparator TSYNC Equal PR1  2011-2013 Microchip Technology Inc. DS30001037C-page 115

PIC24F16KL402 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON — TSIDL — — — T1ECS1(1) T1ECS0(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 T1ECS <1:0>: Timer1 Extended Clock Select bits(1) 11 = Reserved; do not use 10 = Timer1 uses the LPRC as the clock source 01 = Timer1 uses the external clock from T1CK 00 = Timer1 uses the Secondary Oscillator (SOSC) as the clock source bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = Timer1 clock source is selected by T1ECS<1:0> 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: The T1ECSx bits are valid only when TCS = 1. DS30001037C-page 116  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 13.0 TIMER2 MODULE This module is controlled through the T2CON register (Register13-1), which enables or disables the timer Note: This data sheet summarizes the features and configures the prescaler and postscaler. Timer2 of this group of PIC24F devices. It is not can be shut off by clearing control bit, TMR2ON intended to be a comprehensive (T2CON<2>), to minimize power consumption. reference source. For more information The prescaler and postscaler counters are cleared on Timers, refer to the “dsPIC33/PIC24 when any of the following occurs: Family Reference Manual”, “Timers” • A write to the TMR2 register (DS39704). • A write to the T2CON register The Timer2 module incorporates the following features: • Any device Reset (POR, BOR, MCLR or • 8-bit Timer and Period registers (TMR2 and PR2, WDT Reset) respectively) TMR2 is not cleared when T2CON is written. • Readable and writable (both registers) A simplified block diagram of the module is shown in • Software programmable prescaler (1:1, 1:4 and Figure13-1. 1:16) • Software programmable postscaler (1:1 through 1:16) • Interrupt on TMR2 to PR2 match • Optional Timer3 gate on TMR2 to PR2 match • Optional use as the shift clock for the MSSP modules FIGURE 13-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set T2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSPx) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/2 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus  2011-2013 Microchip Technology Inc. DS30001037C-page 117

PIC24F16KL402 FAMILY REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 1111 = 1:16 Postscale 1110 = 1:15 Postscale • • • 0001 = 1:2 Postscale 0000 = 1:1 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 10 = Prescaler is 16 01 = Prescaler is 4 00 = Prescaler is 1 DS30001037C-page 118  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 14.0 TIMER3 MODULE • Selectable clock source (internal or external) with device clock, SOSC or LPRC oscillator options Note: This data sheet summarizes the features • Interrupt-on-overflow of this group of PIC24F devices. It is not • Multiple timer gating options, including: intended to be a comprehensive refer- - User-selectable gate sources and polarity ence source. For more information on Timers, refer to the “dsPIC33/PIC24 - Gate/toggle operation Family Reference Manual”, “Timers” - Single Pulse (One-Shot) mode (DS39704). • Module Reset on ECCP Special Event Trigger The Timer3 timer/counter modules incorporate these The Timer3 module is controlled through the T3CON features: register (Register14-1). A simplified block diagram of the Timer3 module is shown in Figure14-1. • Software-selectable operation as a 16-bit timer or counter The FOSC clock source should not be used with the ECCP capture/compare features. If the timer will be • One 16-bit readable and writable Timer Value used with the capture or compare features, always register select one of the other timer clocking options. FIGURE 14-1: TIMER3 BLOCK DIAGRAM SOSC Components SOSCEN EN TMR3CS<1:0> SOSCO/T1CK SOSC 1 LPRC 11 SOSCI 10 Prescaler Gate Sync T3CK 0 FOSC/2 01 1, 2, 4, 8 FOSC 00 2 Synchronized T3OSCEN T3CKPS<1:0> Clock Input T3SYNC 1 0 T3GSS<1:0> Set T3GIF T3G 00 TMR2 Match 01 Toggle One-Shot Gate C1OUT 10 Select Select Control C2OUT/LPRC 11 T3GTM T3GSPM TMR3GE T3GGO T3GPOL Q D Set Flag bit, TMR3 T3IF, on Overflow 16 16 Internal Data Bus  2011-2013 Microchip Technology Inc. DS30001037C-page 119

PIC24F16KL402 FAMILY REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC — TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 TMR3CS<1:0>: Timer3 Clock Source Select bits 11 = Low-Power RC Oscillator (LPRC) 10 = External clock source (selected by T3CON<3>) 01 = Instruction clock (FOSC/2) 00 = System clock (FOSC)(1) bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T3OSCEN: Timer3 Oscillator Enable bit 1 = SOSC (Secondary Oscillator) is used as a clock source 0 = T3CK digital input pin is used as a clock source bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit When TMR3CS<1:0> = 1x: 1 = Does not synchronize the external clock input 0 = Synchronizes the external clock input(2) When TMR3CS<1:0> = 0x: This bit is ignored; Timer3 uses the internal clock. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture or compare features. 2: This option must be selected when the timer will be used with ECCP/CCP. DS30001037C-page 120  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 14-2: T3GCON: TIMER3 GATE CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 T3DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 TMR3GE: Timer3 Gate Enable bit If TMR3ON = 0: This bit is ignored. If TMR3ON = 1: 1 = Timer counting is controlled by the Timer3 gate function 0 = Timer counts regardless of the Timer3 gate function bit 6 T3GPOL: Timer3 Gate Polarity bit 1 = Timer gate is active-high (Timer3 counts when the gate is high) 0 = Timer gate is active-low (Timer3 counts when the gate is low) bit 5 T3GTM: Timer3 Gate Toggle Mode bit 1 = Timer Gate Toggle mode is enabled. 0 = Timer Gate Toggle mode is disabled and toggle flip-flop is cleared Timer3 gate flip-flop toggles on every rising edge. bit 4 T3GSPM: Timer3 Gate Single Pulse Mode bit 1 = Timer Gate Single Pulse mode is enabled and is controlling the Timer3 gate 0 = Timer Gate Single Pulse mode is disabled bit 3 T3GGO/T3DONE: Timer3 Gate Single Pulse Acquisition Status bit 1 = Timer gate single pulse acquisition is ready, waiting for an edge 0 = Timer gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T3GSPM is cleared. bit 2 T3GVAL: Timer3 Gate Current State bit Indicates the current state of the timer gate that could be provided to the TMR3 register; unaffected by the state of TMR3GE. bit 1-0 T3GSS<1:0>: Timer3 Gate Source Select bits 11 = Comparator 2 output 10 = Comparator 1 output 01 = TMR2 to match PR2 output 00 = T3G input pin Note 1: Initializing T3GCON prior to T3CON is recommended.  2011-2013 Microchip Technology Inc. DS30001037C-page 121

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 122  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 15.0 TIMER4 MODULE The Timer4 module has a control register shown in Register15-1. Timer4 can be shut off by clearing Note: This data sheet summarizes the features control bit, TMR4ON (T4CON<2>), to minimize power of this group of PIC24F devices. It is not consumption. The prescaler and postscaler selection of intended to be a comprehensive refer- Timer4 is controlled by this register. ence source. For more information on The prescaler and postscaler counters are cleared Timers, refer to the “dsPIC33/PIC24 when any of the following occurs: Family Reference Manual”, “Timers” • A write to the TMR4 register (DS39704). • A write to the T4CON register The Timer4 module is implemented in • Any device Reset (POR, BOR, MCLR or WDT PIC24FXXKL30X/40X devices only. It has the following Reset) features: TMR4 is not cleared when T4CON is written. • Eight-bit Timer register (TMR4) Figure15-1 is a simplified block diagram of the Timer4 • Eight-bit Period register (PR4) module. • Readable and writable (all registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR4 match of PR4 FIGURE 15-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 T4OUTPS<3:0> Set T4IF Postscaler 2 T4CKPS<1:0> TMR4 Output (to PWM) TMR4/PR4 Reset Match 1:1, 1:4, 1:16 FOSC/2 TMR4 Comparator PR4 Prescaler 8 8 8 Internal Data Bus  2011-2013 Microchip Technology Inc. DS30001037C-page 123

PIC24F16KL402 FAMILY REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Select bits 1111 = 1:16 Postscale 1110 = 1:15 Postscale • • • 0001 = 1:2 Postscale 0000 = 1:1 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 10 = Prescaler is 16 01 = Prescaler is 4 00 = Prescaler is 1 DS30001037C-page 124  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 16.0 CAPTURE/COMPARE/PWM 16.1 Timer Selection (CCP) AND ENHANCED CCP On all PIC24F16KL402 family devices, the CCP and MODULES ECCP modules use Timer3 as the time base for cap- ture and compare operations. PWM and Enhanced Note: This data sheet summarizes the features PWM operations may use either Timer2 or Timer4. of this group of PIC24F devices. It is not PWM time base selection is done through the intended to be a comprehensive refer- CCPTMRS0 register (Register16-6). ence source. For more information on the Capture/Compare/PWM module, refer to 16.2 CCP I/O Pins the “dsPIC33/PIC24 Family Reference Manual”. To configure I/O pins with a CCP function, the proper mode must be selected by setting the CCPxM<3:0> Depending on the particular device, PIC24F16KL402 bits. family devices include up to three CCP and/or ECCP Where the Enhanced CCP module is available, it may modules. Key features of all CCP modules include: have up to four PWM outputs depending on the • 16-bit input capture for a range of edge events selected operating mode. These outputs are desig- • 16-bit output compare with multiple output options nated, P1A through P1D. The outputs that are active • Single-output Pulse-Width Modulation (PWM) depend on the ECCP operating mode selected. To with up to 10 bits of resolution configure I/O pins for Enhanced PWM operation, the • User-selectable time base from any available proper PWM mode must be selected by setting the timer PM<1:0> and CCPxM<3:0> bits. • Special Event Trigger on capture and compare events to automatically trigger a range of peripherals ECCP modules also include these features: • Operation in Half-Bridge and Full-Bridge (Forward and Reverse) modes • Pulse steering control across any or all Enhanced PWM pins with user-configurable steering synchronization • User-configurable external Fault detect with auto-shutdown and auto-restart PIC24FXXKL40X/30X devices instantiate three CCP modules, one Enhanced (ECCP1) and two standard (CCP2 and CCP3). All other devices instantiate two standard CCP modules (CCP1 and CCP2).  2011-2013 Microchip Technology Inc. DS30001037C-page 125

PIC24F16KL402 FAMILY FIGURE 16-1: GENERIC CAPTURE MODE BLOCK DIAGRAM Set CCPxIF TMR3H TMR3L (E)CCPx Pin Prescaler and  1, 4, 16 Edge Detect CCPRxH CCPRxL 4 CCPxCON<3:0> 4 Q1:Q4 FIGURE 16-2: GENERIC COMPARE MODE BLOCK DIAGRAM Special Event Trigger Set CCPxIF (Timer3 Reset) CCPRxH CCPRxL CCPx Pin Compare Output S Q Comparator Match Logic R CCP 4 Output Enable TMR3H TMR3L CCPxCON<3:0> FIGURE 16-3: SIMPLIFIED PWM BLOCK DIAGRAM CCPxCON<5:4> Duty Cycle Registers CCPRxL CCPRxH (Slave) Comparator R Q CCPx TMR2(2) (1) S CCPx Comparator Output Enable Clear Timer, CCP1 Pin and Latch D.C. PR2(2) Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. 2: Either Timer2 or Timer4 may be used as the PWM time base. DS30001037C-page 126  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 16-4: SIMPLIFIED BLOCK DIAGRAM OF ENHANCED PWM MODE Duty Cycle Registers DC1B<1:0> PM<1:0> CCP1M<3:0> 2 4 CCPR1L ECCP1/P1A ECCP1/P1A Output ECCP Enable CCPR1H (Slave) P1B P1B Output Output ECCP Enable Comparator R Q Controller P1C P1C Output TMR2(2) (1) S ECCP Enable P1D P1D Output Comparator Clear Timer, ECCP Enable CCP1 Pin and Latch D.C. PR2(2) ECCP1DEL Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10- bit time base. 2: Either Timer2 or Timer4 may be used as the Enhanced PWM time base.  2011-2013 Microchip Technology Inc. DS30001037C-page 127

PIC24F16KL402 FAMILY REGISTER 16-1: CCPxCON: CCPx CONTROL REGISTER(STANDARD CCP MODULES) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3(1) CCPxM2(1) CCPxM1(1) CCPxM0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module bits Capture and Compare modes: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCxB<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits(1) 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = PWM mode 1011 = Compare mode: Special Event Trigger; resets timer on CCPx match (CCPxIF bit is set) 1010 = Compare mode: Generates software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1001 =Compare mode: Initializes CCPx pin high; on compare match, forces CCPx pin low (CCPxIF bit is set) 1000 = Compare mode: Initializes CCPx pin low; on compare match, forces CCPx pin high (CCPxIF bit is set) 0111 = Capture mode: Every 16th rising edge 0110 = Capture mode: Every 4th rising edge 0101 = Capture mode: Every rising edge 0100 = Capture mode: Every falling edge 0011 = Reserved 0010 = Compare mode: Toggles output on match (CCPxIF bit is set) 0001 = Reserved 0000 = Capture/Compare/PWM is disabled (resets CCPx module) Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start the A/D conversion on a CCPx match. DS30001037C-page 128  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 16-2: CCP1CON: ECCP1 CONTROL REGISTER(ECCP MODULES ONLY)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PM1 PM0 DC1B1 DC1B0 CCP1M3(2) CCP1M2(2) CCP1M1(2) CCP1M0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 PM<1:0>: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A is assigned as a capture input or compare output; P1B, P1C and P1D are assigned as port pins If CCP1M<3:2> = 11: 11 = Full-bridge output reverse: P1B is modulated; P1C is active; P1A and P1D are inactive 10 = Half-bridge output: P1A, P1B are modulated with dead-band control; P1C and P1D are assigned as port pins 01 = Full-bridge output forward: P1D is modulated; P1A is active; P1B, P1C are inactive 00 = Single output: P1A, P1B, P1C and P1D are controlled by steering bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP1 Module bits Capture and Compare modes: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DC1B<9:2>) of the duty cycle are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP1 Module Mode Select bits(2) 1111 = PWM mode: P1A and P1C are active-low; P1B and P1D are active-low 1110 = PWM mode: P1A and P1C are active-low; P1B and P1D are active-high 1101 = PWM mode: P1A and P1C are active-high; P1B and P1D are active-low 1100 = PWM mode: P1A and P1C are active-high; P1B and P1D are active-high 1011 = Compare mode: Special Event Trigger; resets timer on CCP1 match (CCPxIF bit is set) 1010 = Compare mode: Generates software interrupt on compare match (CCP1IF bit is set, CCP1 pin reflects I/O state) 1001 = Compare mode: Initializes CCP1 pin high; on compare match, forces CCP1 pin low (CCP1IF bit is set) 1000 =Compare mode: Initializes CCP1 pin low; on compare match, forces CCP1 pin high (CCP1IF bit is set) 0111 = Capture mode: Every 16th rising edge 0110 = Capture mode: Every 4th rising edge 0101 = Capture mode: Every rising edge 0100 = Capture mode: Every falling edge 0011 = Reserved 0010 = Compare mode: Toggles output on match (CCP1IF bit is set) 0001 = Reserved 0000 = Capture/Compare/PWM is disabled (resets CCP1 module) Note 1: This register is implemented only on PIC24FXXKL40X/30X devices. For all other devices, CCP1CON is configured as Register16-1. 2: CCP1M<3:0> = 1011 will only reset the timer and not start the A/D conversion on a CCP1 match.  2011-2013 Microchip Technology Inc. DS30001037C-page 129

PIC24F16KL402 FAMILY REGISTER 16-3: ECCP1AS: ECCP1 AUTO-SHUTDOWN CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ECCPASE: ECCP1 Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in a shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP1 Auto-Shutdown Source Select bits 111 =VIL on FLT0 pin, or either C1OUT or C2OUT is high 110 =VIL on FLT0 pin or C2OUT comparator output is high 101 =VIL on FLT0 pin or C1OUT comparator output is high 100 =VIL on FLT0 pin 011 =Either C1OUT or C2OUT is high 010 =C2OUT comparator output is high 001 =C1OUT comparator output is high 000 =Auto-shutdown is disabled bit 3-2 PSSAC<1:0>: P1A and P1C Pins Shutdown State Control bits 1x = P1A and P1C pins tri-state 01 = Drive pins, P1A and P1C, to ‘1’ 00 = Drive pins, P1A and P1C, to ‘0’ bit 1-0 PSSBD<1:0>: P1B and P1D Pins Shutdown State Control bits 1x = P1B and P1D pins tri-state 01 = Drive pins, P1B and P1D, to ‘1’ 00 = Drive pins, P1B and P1D, to ‘0’ Note 1: This register is implemented only on PIC24FXXKL40X/30X devices. Note1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period. DS30001037C-page 130  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 16-4: ECCP1DEL: ECCP1 ENHANCED PWM CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn = Number of FCY (FOSC/2) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active. Note 1: This register is implemented only on PIC24FXXKL40X/30X devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 131

PIC24F16KL402 FAMILY REGISTER 16-5: PSTR1CON: ECCP1 PULSE STEERING CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering bits 00 = Complementary output assignment is disabled; the STR<D:A> bits are used to determine Steering mode 01 = P1A and P1B are selected as the complementary output pair 10 = P1A and P1C are selected as the complementary output pair 11 = P1A and P1D are selected as the complementary output pair bit 5 Unimplemented: Read as ‘0’ bit 4 STRSYNC: Steering Sync bit 1 = Output steering update occurs on the next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRD: Steering Enable D bit 1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1D pin is assigned to port pin bit 2 STRC: Steering Enable C bit 1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1C pin is assigned to port pin bit 1 STRB: Steering Enable B bit 1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1B pin is assigned to port pin bit 0 STRA: Steering Enable A bit 1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1A pin is assigned to port pin Note 1: This register is only implemented on PIC24FXXKL40X/30X devices. In addition, PWM Steering mode is available only when CCP1M<3:2>=11 and PM<1:0>=00. DS30001037C-page 132  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 16-6: CCPTMRS0: CCP TIMER SELECT CONTROL REGISTER 0(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 — C3TSEL0 — — C2TSEL0 — — C1TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 C3TSEL0: CCP3 Timer Selection bit 1 = CCP3 uses TMR3/TMR4 0 = CCP3 uses TMR3/TMR2 bit 5-4 Unimplemented: Read as ‘0’ bit 3 C2TSEL0: CCP2 Timer Selection bit 1 = CCP2 uses TMR3/TMR4 0 = CCP2 uses TMR3/TMR2 bit 2-1 Unimplemented: Read as ‘0’ bit 0 C1TSEL0: CCP1/ECCP1 Timer Selection bit 1 = CCP1/ECCP1 uses TMR3/TMR4 0 = CCP1/ECCP1 uses TMR3/TMR2 Note 1: This register is unimplemented on PIC24FXXKL20X/10X devices; maintain as ‘0’.  2011-2013 Microchip Technology Inc. DS30001037C-page 133

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 134  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 17.0 MASTER SYNCHRONOUS 17.1 I/O Pin Configuration for SPI SERIAL PORT (MSSP) In SPI Master mode, the MSSP module will assert con- trol over any pins associated with the SDOx and SCKx Note: This data sheet summarizes the features outputs. This does not automatically disable other digi- of this group of PIC24F devices. It is not tal functions associated with the pin, and may result in intended to be a comprehensive refer- the module driving the digital I/O port inputs. To prevent ence source. For more information on this, the MSSP module outputs must be disconnected MSSP, refer to the “dsPIC33/PIC24 from their output pins while the module is in SPI Master Family Reference Manual”. mode. While disabling the module temporarily may be The Master Synchronous Serial Port (MSSP) module is an option, it may not be a practical solution in all an 8-bit serial interface, useful for communicating with applications. other peripheral or microcontroller devices. These The SDOx and SCKx outputs for the module can be peripheral devices may be serial EEPROMs, Shift selectively disabled by using the SDOxDIS and registers, display drivers, A/D Converters, etc. The SCKxDIS bits in the PADCFG1 register (Register17-10). MSSP module can operate in one of two modes: Setting the bit disconnects the corresponding output for a • Serial Peripheral Interface (SPI) particular module from its assigned pin. • Inter-Integrated Circuit (I2C™) - Full Master mode - Slave mode (with general address call) The SPI interface supports these modes in hardware: • Master mode • Slave mode • Daisy-Chaining Operation in Slave mode • Synchronized Slave operation The I2C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode with 10-Bit And 7-Bit Addressing and Address Masking • Byte NACKing • Selectable Address and Data Hold and Interrupt Masking  2011-2013 Microchip Technology Inc. DS30001037C-page 135

PIC24F16KL402 FAMILY FIGURE 17-1: MSSPx BLOCK DIAGRAM (SPIMODE) Internal Data Bus Read Write SSPxBUF SDIx SSPxSR Shift Clock bit 0 SDOx SSx SSx Control Enable Edge Select 2 Clock Select SSPxADD<7:0> SSPM<3:0> SMP:CKE 4 7 (T M R 2 O u t p ut) 2 SCKx 2 Baud Edge Rate Select Generator Prescaler TOSC 4, 16, 64 Data to TXx/RXx in SSPxSR TRISx bit Note: Refer to the device data sheet for pin multiplexing. FIGURE 17-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) Shift Register SDIx SDOx Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2 DS30001037C-page 136  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 17-3: MSSPx BLOCK DIAGRAM (I2C™ MODE) Internal Data Bus Read Write SSPxBUF SCLx Shift Clock SSPxSR SDAx MSb LSb Address Mask Match Detect Address Match SSPxADD SSttaarrtt aanndd Set/Reset S, P bits Stop bit Detect Note: Only port I/O names are shown in this diagram. Refer to the text for a full list of multiplexed functions. 2 FIGURE 17-4: MSSPx BLOCK DIAGRAM (I C™ MASTER MODE) Internal Data Bus Read Write SSPM<3:0> SSPxBUF SSPxADD<6:0> SDAx Shift Baud SDAx In Clock Rate SSPxSR Generator MSb LSb Start bit, Stop bit, Acknowledge Generate SCLx Start bit Detect, Clock Cntl RCV Enable Stop bit Detect, Write Collision Detect, Clock Arbitrate/WCOL Detect SCLx In Clock Arbitration (hold off clock source) Bus Collision State Counter for Set/Reset S, P (SSPxSTAT), WCOL; End of XMIT/RCV Set SSPxIF, BCLxIF; Reset ACKSTAT, PEN  2011-2013 Microchip Technology Inc. DS30001037C-page 137

PIC24F16KL402 FAMILY REGISTER 17-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SMP: Sample bit SPI Master mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C™ mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSPx module is disabled; SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit 1 = Receive is complete, SSPxBUF is full 0 = Receive is not complete, SSPxBUF is empty Note 1: The polarity of the clock state is set by the CKP bit (SSPxCON1<4>). DS30001037C-page 138  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 17-2: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enables SMBus specific inputs 0 = Disables SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit In Slave mode:(2) 1 = Read 0 = Write In Master mode:(3) 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated Note 1: This bit is cleared on RESET and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode.  2011-2013 Microchip Technology Inc. DS30001037C-page 139

PIC24F16KL402 FAMILY REGISTER 17-2: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) (CONTINUED) bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = Transmit is in progress, SSPxBUF is full 0 = Transmit is complete, SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on RESET and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode. DS30001037C-page 140  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 17-3: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: MSSPx Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of over- flow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: MSSPx Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: MSSPx Mode Select bits(3) 1010 = SPI Master mode, Clock = FOSC/(2 * ([SSPxADD] + 1))(4) 0101 = SPI Slave mode, Clock = SCKx pin; SSx pin control is disabled, SSx can be used as an I/O pin 0100 = SPI Slave mode, Clock = SCKx pin; SSx pin control is enabled 0011 = SPI Master mode, Clock = TMR2 output/2 0010 = SPI Master mode, Clock = FOSC/32 0001 = SPI Master mode, Clock = FOSC/8 0000 = SPI Master mode, Clock = FOSC/2 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. 4: SSPxADD value of 0 is not supported when the Baud Rate Generator is used in SPI mode.  2011-2013 Microchip Technology Inc. DS30001037C-page 141

PIC24F16KL402 FAMILY REGISTER 17-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: MSSPx Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: MSSPx Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables the serial port and configures these pins as I/O port pins bit 4 CKP: SCLx Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch); used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: MSSPx Mode Select bits(2) 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts is enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts is enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, Clock = FOSC/(2 * ([SSPxADD] + 1))(3) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. 3: SSPxADD values of 0, 1 or 2 are not supported when the Baud Rate Generator is used with I2C mode. DS30001037C-page 142  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 17-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address is disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = No Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (Master mode only)(2) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits ACKDT data bit; automatically cleared by hardware 0 = Acknowledge sequence is Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive is Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(2) 1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Stop condition is Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(2) 1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Repeated Start condition is Idle bit 0 SEN: Start Condition Enable bit(2) Master Mode: 1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Start condition is Idle Slave Mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch is enabled) 0 = Clock stretching is disabled Note 1: The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).  2011-2013 Microchip Technology Inc. DS30001037C-page 143

PIC24F16KL402 FAMILY REGISTER 17-6: SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN(1) SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ACKTIM: Acknowledge Time Status bit (I2C™ mode only) Unused in SPI mode. bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) Unused in SPI mode. bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) Unused in SPI mode. bit 4 BOEN: Buffer Overwrite Enable bit(1) In SPI Slave mode: 1 = SSPxBUF updates every time that a new data byte is shifted in, ignoring the BF bit 0 = If a new byte is received with the BF bit of the SSPxSTAT register already set, the SSPOV bit of the SSPxCON1 register is set and the buffer is not updated bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only) Unused in SPI mode. bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) Unused in SPI mode. bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) Unused in SPI mode. bit 0 DHEN: Data Hold Enable bit (Slave mode only) Unused in SPI mode. Note 1: For daisy-chained SPI operation: Allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSPxBUF. DS30001037C-page 144  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 17-7: SSPxCON3: MSSPx CONTROL REGISTER 3 (I2C™ MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM(2) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ACKTIM: Acknowledge Time Status bit(2) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on the 8th falling edge of the SCLx clock 0 = Not an Acknowledge sequence, cleared on the 9th rising edge of the SCLx clock bit 6 PCIE: Stop Condition Interrupt Enable bit 1 = Enables interrupt on detection of a Stop condition 0 = Stop detection interrupts are disabled(1) bit 5 SCIE: Start Condition Interrupt Enable bit 1 = Enables interrupt on detection of the Start or Restart conditions 0 = Start detection interrupts are disabled(1) bit 4 BOEN: Buffer Overwrite Enable bit I 2 C Master mode: This bit is ignored. I 2 C Slave mode: 1 = SSPxBUF is updated and an ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0 0 = SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT: SDAx Hold Time Selection bit 1 = Minimum of 300ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100ns hold time on SDAx after the falling edge of SCLx bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (Slave mode only) 1 = Enables slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (Slave mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte; the CKP bit of the SSPxCON1 register will be cleared and SCLx will be held low 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low 0 = Data holding is disabled Note 1: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. 2: The ACKTIM status bit is active only when the AHEN bit or DHEN bit is set.  2011-2013 Microchip Technology Inc. DS30001037C-page 145

PIC24F16KL402 FAMILY REGISTER 17-8: SSPxADD: MSSPx SLAVE ADDRESS/BAUD RATE GENERATOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 ADD<7:0>: Slave Address/Baud Rate Generator Value bits SPI Master and I 2 C™ Master modes: Reloads value for Baud Rate Generator. Clock period is (([SPxADD] + 1) *2)/FOSC. I 2 C Slave modes: Represents 7 or 8 bits of the slave address, depending on the addressing mode used: 7-Bit mode: Address is ADD<7:1>; ADD<0> is ignored. 10-Bit LSb mode: ADD<7:0> are the Least Significant bits of the address. 10-Bit MSb mode: ADD<2:1> are the two Most Significant bits of the address; ADD<7:3> are always ‘11110’ as a specification requirement, ADD<0> is ignored. REGISTER 17-9: SSPxMSK: I2C™ SLAVE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK<7:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 MSK<7:0>: Slave Address Mask Select bits(1) 1 = Masking of corresponding bit of SSPxADD is enabled 0 = Masking of corresponding bit of SSPxADD is disabled Note 1: MSK0 is not used as a mask bit in 7-bit addressing. DS30001037C-page 146  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 17-10: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SDO2DIS(1) SCK2DIS(1) SDO1DIS SCK1DIS bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 SDO2DIS: MSSP2 SDO2 Pin Disable bit(1) 1 = The SPI output data (SDO2) of MSSP2 to the pin is disabled 0 = The SPI output data (SDO2) of MSSP2 is output to the pin bit 10 SCK2DIS: MSSP2 SCK2 Pin Disable bit(1) 1 = The SPI clock (SCK2) of MSSP2 to the pin is disabled 0 = The SPI clock (SCK2) of MSSP2 is output to the pin bit 9 SDO1DIS: MSSP1 SDO1 Pin Disable bit 1 = The SPI output data (SDO1) of MSSP1 to the pin is disabled 0 = The SPI output data (SDO1) of MSSP1 is output to the pin bit 8 SCK1DIS: MSSP1 SCK1 Pin Disable bit 1 = The SPI clock (SCK1) of MSSP1 to the pin is disabled 0 = The SPI clock (SCK1) of MSSP1 is output to the pin bit 7-0 Unimplemented: Read as ‘0’ Note 1: These bits are implemented only on PIC24FXXKL40X/30X devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 147

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 148  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 18.0 UNIVERSAL ASYNCHRONOUS • Fully Integrated Baud Rate Generator (IBRG) with RECEIVER TRANSMITTER 16-Bit Prescaler • Baud Rates Ranging from 1Mbps to 15bps at (UART) 16MIPS Note: This data sheet summarizes the features • Two-Level Deep, First-In-First-Out (FIFO) of this group of PIC24F devices. It is not Transmit Data Buffer intended to be a comprehensive refer- • Two-Level Deep, FIFO Receive Data Buffer ence source. For more information on the • Parity, Framing and Buffer Overrun Error Universal Asynchronous Receiver Detection Transmitter, refer to the “dsPIC33/PIC24 • Support for 9-Bit mode with Address Detect Family Reference Manual”, “UART” (9th bit = 1) (DS39708). • Transmit and Receive Interrupts The Universal Asynchronous Receiver Transmitter • Loopback mode for Diagnostic Support (UART) module is one of the serial I/O modules • Support for Sync and Break Characters available in this PIC24F device family. The UART is a • Supports Automatic Baud Rate Detection full-duplex, asynchronous system that can communicate • IrDA Encoder and Decoder Logic with peripheral devices, such as personal computers, LIN/J2602, RS-232 and RS-485 interfaces. This module • 16x Baud Clock Output for IrDA® Support also supports a hardware flow control option with the A simplified block diagram of the UART module is UxCTS and UxRTS pins, and also includes an IrDA® shown in Figure18-1. The UART module consists of encoder and decoder. these important hardware elements: The primary features of the UART module are: • Baud Rate Generator • Full-Duplex, 8-Bit or 9-Bit Data Transmission • Asynchronous Transmitter Through the UxTX and UxRX Pins • Asynchronous Receiver • Even, Odd or No Parity Options (for 8-bit data) • One or Two Stop bits • Hardware Flow Control Option with UxCTS and UxRTS Pins FIGURE 18-1: UARTx SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® UxBCLK Hardware Flow Control UxRTS UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2011-2013 Microchip Technology Inc. DS30001037C-page 149

PIC24F16KL402 FAMILY 18.1 UART Baud Rate Generator (BRG) The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate The UART module includes a dedicated 16-bit Baud possible is FCY/(16 * 65536). Rate Generator (BRG). The UxBRG register controls Equation18-2 shows the formula for computation of the period of a free-running, 16-bit timer. Equation18-1 the baud rate with BRGH = 1. provides the formula for computation of the baud rate with BRGH = 0. EQUATION 18-2: UARTx BAUD RATE WITH EQUATION 18-1: UARTx BAUD RATE WITH BRGH = 1(1) BRGH = 0(1) FCY Baud Rate = FCY 4 • (UxBRG + 1) Baud Rate = 16 • (UxBRG + 1) FCY UxBRG = – 1 4 • Baud Rate FCY UxBRG = – 1 16 • Baud Rate Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. The maximum baud rate (BRGH = 1) possible is FCY/4 (for UxBRG = 0) and the minimum baud rate possible Example18-1 provides the calculation of the baud rate is FCY/(4 * 65536). error for the following conditions: Writing a new value to the UxBRG register causes the • FCY = 4 MHz BRG timer to be reset (cleared). This ensures the BRG • Desired Baud Rate = 9600 does not wait for a timer overflow before generating the new baud rate. EXAMPLE 18-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1) Desired Baud Rate = FCY/(16 (UxBRG + 1)) Solving for UxBRG Value: UxBRG = ((FCY/Desired Baud Rate)/16) – 1 UxBRG = ((4000000/9600)/16) – 1 UxBRG = 25 Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 = 0.16% Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. DS30001037C-page 150  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 18.2 Transmitting in 8-Bit Data Mode 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART: a) Write appropriate values for data, parity and 1. Set up the UART (as described in Section18.2 Stop bits. “Transmitting in 8-Bit Data Mode”). b) Write appropriate baud rate value to the 2. Enable the UART. UxBRG register. 3. A receive interrupt will be generated when one c) Set up transmit and receive interrupt enable or more data characters have been received as and priority bits. per interrupt control bit, URXISELx. 2. Enable the UART. 4. Read the OERR bit to determine if an overrun 3. Set the UTXEN bit (causes a transmit interrupt, error has occurred. The OERR bit must be reset two cycles after being set). in software. 4. Write data byte to lower byte of UxTXREG word. 5. Read UxRXREG. The value will be immediately transferred to the The act of reading the UxRXREG character will move Transmit Shift Register (TSR) and the serial bit the next character to the top of the receive FIFO, stream will start shifting out with the next rising including a new set of PERR and FERR values. edge of the baud clock. 5. Alternately, the data byte may be transferred 18.6 Operation of UxCTS and UxRTS while UTXEN = 0 and then, the user may set Control Pins UTXEN. This will cause the serial bit stream to begin immediately, because the baud clock will UARTx Clear-to-Send (UxCTS) and Request-to-Send start from a cleared state. (UxRTS) are the two hardware-controlled pins that are 6. A transmit interrupt will be generated as per associated with the UART module. These two pins interrupt control bit, UTXISELx. allow the UART to operate in Simplex and Flow Control modes. They are implemented to control the 18.3 Transmitting in 9-Bit Data Mode transmission and reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the UxMODE 1. Set up the UART (as described in Section18.2 register configure these pins. “Transmitting in 8-Bit Data Mode”). 2. Enable the UART. 18.7 Infrared Support 3. Set the UTXEN bit (causes a transmit interrupt, The UART module provides two types of infrared UART twocycles after being set). support: one is the IrDA clock output to support an 4. Write UxTXREG as a 16-bit value only. external IrDA encoder and decoder device (legacy 5. A word write to UxTXREG triggers the transfer module support), and the other is the full of the 9-bit data to the TSR. The serial bit stream implementation of the IrDA encoder and decoder. will start shifting out with the first rising edge of As the IrDA modes require a 16x baud clock, they will the baud clock. only work when the BRGH bit (UxMODE<3>) is ‘0’. 6. A transmit interrupt will be generated as per the setting of control bit, UTXISELx. 18.7.1 EXTERNAL IrDA SUPPORT – IrDA CLOCK OUTPUT 18.4 Break and Sync Transmit To support external IrDA encoder and decoder devices, Sequence the UxBCLK pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. When The following sequence will send a message frame UEN<1:0> = 11, the UxBCLK pin will output the 16x header made up of a Break, followed by an auto-baud baud clock if the UART module is enabled; it can be Sync byte. used to support the IrDA codec chip. 1. Configure the UART for the desired mode. 2. Set UTXEN and UTXBRK – sets up the Break 18.7.2 BUILT-IN IrDA ENCODER AND character. DECODER 3. Load the UxTXREG with a dummy character to The UART has full implementation of the IrDA encoder initiate transmission (value is ignored). and decoder as part of the UART module. The built-in 4. Write ‘55h’ to UxTXREG – loads the Sync IrDA encoder and decoder functionality is enabled character into the transmit FIFO. using the IREN bit (UxMODE<12>). When enabled 5. After the Break has been sent, the UTXBRK bit (IREN = 1), the receive pin (UxRX) acts as the input is reset by hardware. The Sync character now from the infrared receiver. The transmit pin (UxTX) acts transmits. as the output to the infrared transmitter.  2011-2013 Microchip Technology Inc. DS30001037C-page 151

PIC24F16KL402 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2) R/W-0(2) UARTEN — USIDL IREN(1) RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(1) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits(2) 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by port latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ Note 1: This feature is is only available for the 16x BRG mode (BRGH=0). 2: Bit availability depends on pin availability. DS30001037C-page 152  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is is only available for the 16x BRG mode (BRGH=0). 2: Bit availability depends on pin availability.  2011-2013 Microchip Technology Inc. DS30001037C-page 153

PIC24F16KL402 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle ‘0’ 0 = UxTX Idle ‘1’ If IREN = 1: 1 = UxTX Idle ‘1’ 0 = UxTX Idle ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits; followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: UARTx Transmit Enable bit 1 = Transmit is enabled; UxTX pin is controlled by UARTx 0 = Transmit is disabled; any pending transmission is aborted and the buffer is reset. UxTX pin is controlled by the PORT register. bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and the transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty; a transmission is in progress or queued bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on the RSR transfer, making the receive buffer full (i.e., has 2 data characters) 10 = Reserved 01 = Reserved 00 = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters DS30001037C-page 154  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of the received data=1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (10 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty  2011-2013 Microchip Technology Inc. DS30001037C-page 155

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 156  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 19.0 10-BIT HIGH-SPEED A/D A block diagram of the A/D Converter is displayed in CONVERTER Figure19-1. To perform an A/D conversion: Note: This data sheet summarizes the features of 1. Configure the A/D module: this group of PIC24F devices. It is not a) Configure port pins as analog inputs and/ intended to be a comprehensive reference or select band gap reference inputs source. For more information on the 10-Bit (ANSA<3:0>, ANSB<15:12,4:0> and High-Speed A/D Converter, refer to the ANCFG<0>). “dsPIC33/PIC24 Family Reference Manual”, “10-Bit A/D Converter” b) Select the voltage reference source to (DS39705). match the expected range on analog inputs (AD1CON2<15:13>). The 10-bit A/D Converter has the following key c) Select the analog conversion clock to match features: the desired data rate with the processor • Successive Approximation (SAR) conversion clock (AD1CON3<7:0>). • Conversion speeds of up to 500ksps d) Select the appropriate sample/conversion sequence (AD1CON1<7:5> and • Up to 12 analog input pins AD1CON3<12:8>). • External voltage reference input pins e) Select how conversion results are • Internal band gap reference input presented in the buffer (AD1CON1<9:8>). • Automatic Channel Scan mode f) Select interrupt rate (AD1CON2<5:2>). • Selectable conversion trigger source g) Turn on A/D module (AD1CON1<15>). • Two-word conversion result buffer 2. Configure A/D interrupt (if required): • Selectable Buffer Fill modes a) Clear the AD1IF bit. • Four result alignment options b) Select A/D interrupt priority. • Operation during CPU Sleep and Idle modes Depending on the particular device, PIC24F16KL402 family devices implement up to 12 analog input pins, designated AN0 through AN4 and AN9 through AN15. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins.  2011-2013 Microchip Technology Inc. DS30001037C-page 157

PIC24F16KL402 FAMILY FIGURE 19-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD VR+ AVSS ect 16 el S VREF+ R VR- V VREF- Comparator VINH VR- VR+ S/H DAC VINL AN0 VINH 10-Bit SAR Conversion Logic AN1 A AN2(1) X Data Formatting U M AN3(1) AN1 AN4(1) VINL AN9 ADC1BUF0: ADC1BUF1 AN10 AD1CON1 AN11(1) AD1CON2 AD1CON3 AN12(1) AD1CHS AN13 VINH AD1CSSL B X AN14 MU AN15 AN1 VINL VBG Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control Note 1: Unimplemented in 14-pin devices. DS30001037C-page 158  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 19-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HSC R-0, HSC SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: A/D Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 FORM<1:0>: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = Reserved 010 = Timer1 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing the SAMP bit ends sampling and starts conversion bit 4-3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after the last conversion completes; SAMP bit is auto-set 0 = Sampling begins when the SAMP bit is set bit 1 SAMP: A/D Sample Enable bit 1 = A/D Sample-and-Hold amplifier is sampling input 0 = A/D Sample-and-Hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is not done Note 1: Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module.  2011-2013 Microchip Technology Inc. DS30001037C-page 159

PIC24F16KL402 FAMILY REGISTER 19-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 OFFCAL(1) — CSCNA — — bit 15 bit 8 R-x U-0 R/W-0 R/W-0 R/W-0 R/W-0 r-0 R/W-0 r — SMPI3 SMPI2 SMPI1 SMPI0 r ALTS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits VCFG<2:0> VR+ VR- 000 AVDD AVSS 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin 1xx AVDD AVSS bit 12 OFFCAL: Offset Calibration bit(1) 1 = Conversions to get the offset calibration value 0 = Conversions to get the actual input value bit 11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for MUX A Input Multiplexer bit 1 = Scans inputs 0 = Does not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 Reserved: Ignore this value bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = • • = Reserved, do not use (may cause conversion data loss) • 0010 = 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 Reserved: Always maintain as ‘0’ bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for the first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings Note 1: When the OFFCAL bit is set, inputs are disconnected and tied to AVSS. This sets the inputs of the A/D to zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG contents nor channel input selection. Any analog input switches are disconnected from the A/D Converter in this mode. The conversion result is stored by the user software and used to compensate subsequent conversions. This can be done by adding the two’s complement of the result obtained with the OFFCAL bit set to all normal A/D conversions. DS30001037C-page 160  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 19-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock bit 14 EXTSAM: Extended Sampling Time bit 1 = A/D is still sampling after SAMP=0 0 = A/D is finished sampling bit 13 PUMPEN: Charge Pump Enable bit 1 = Charge pump for switches is enabled 0 = Charge pump for switches is disabled bit 12-8 SAMC<4:0>: Auto-Sample Time bits 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD (not recommended) bit 7-6 Unimplemented: Maintain as ‘0’ bit 5-0 ADCS<5:0>: A/D Conversion Clock Select bits 11111 = 64 • TCY 11110 = 63 • TCY • • • 00001 = 2 • TCY 00000 = TCY  2011-2013 Microchip Technology Inc. DS30001037C-page 161

PIC24F16KL402 FAMILY - REGISTER 19-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 14-12 Unimplemented: Read as ‘0’ bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits 1111 = AN15 1110 = AN14 1101 = AN13 1100 = AN12(1) 1011 = AN11(1) 1010 = AN10 1001 = AN9 1000 = Upper guardband rail (0.785 * VDD) 0111 = Lower guardband rail (0.215 * VDD) 0110 = Internal band gap reference (VBG) 0101 = Reserved; do not use 0100 = AN4(1) 0011 = AN3(1) 0010 = AN2(1) 0001 = AN1 0000 = AN0 bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits Bit combinations are identical to those for CH0SB<3:0> (above). Note 1: Unimplemented on 14-pin devices; do not use. DS30001037C-page 162  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 19-5: AD1CSSL: A/D INPUT SCAN SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL<15:8>(1) bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL<7:6> — CSSL<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 CSSL<15:6>: A/D Input Pin Scan Selection bits(1) 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan bit 5 Unimplemented: Read as ‘0’ bit 4-0 CSSL<4:0>: A/D Input Pin Scan Selection bits(1) 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Note 1: CSSL<12:11,4:2> bits are unimplemented on 14-pin devices. REGISTER 19-6: ANCFG: ANALOG INPUT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — VBGEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 VBGEN: Internal Band Gap Reference Enable bit 1 = Internal band gap voltage is available as a channel input to the A/D Converter 0 = Band gap is not available to the A/D Converter  2011-2013 Microchip Technology Inc. DS30001037C-page 163

PIC24F16KL402 FAMILY EQUATION 19-1: A/D CONVERSION CLOCK PERIOD(1) TAD ADCS = – 1 TCY TAD = TCY • (ADCS + 1) Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. FIGURE 19-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD RIC  250W Sampling RSS  5 k (Typical) Switch VT = 0.6V Rs ANx RSS CHOLD VA C6-P1I1N pF VT = 0.6V I±L5E0A0K AnGAE == D4.A4C p FC a(Tpyapciictaanl)ce (Typical) VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to Various Junctions RIC = Interconnect Resistance RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from DAC) Note: CPIN value depends on device package and is not tested. Effect of CPIN is negligible if Rs  5 k. DS30001037C-page 164  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 19-3: A/D TRANSFER FUNCTION Digital Output Code Binary (Decimal) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) Voltage Level 0 V-R V+ - V-RR- + R1024 12 * (V+ - V-)RR 1024 23 * (V+ - V-)RR 1024V+R V- VINH INL V 5 0 V- + R 1- + VR  2011-2013 Microchip Technology Inc. DS30001037C-page 165

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 166  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 20.0 COMPARATOR MODULE The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, Note: This data sheet summarizes the features of the I/O pad logic makes the unsynchronized output of this group of PIC24F devices. It is not the comparator available on the pin. intended to be a comprehensive reference A simplified block diagram of the module is displayed in source. For more information on the Figure20-1. Diagrams of the possible individual Comparator module, refer to the comparator configurations are displayed in “dsPIC33/PIC24 Family Reference Figure20-2. Manual”, “Dual Comparator Module” (DS39710). Each comparator has its own control register, CMxCON (Register20-1), for enabling and configuring Depending on the particular device, the comparator its operation. The output and event status of all three module provides one or two analog comparators. The comparators is provided in the CMSTAT register inputs to the comparator can be configured to use any (Register20-2). one of up to four external analog inputs, as well as a voltage reference input from either the internal band gap reference, divided by 2 (VBG/2), or the comparator voltage reference generator. FIGURE 20-1: COMPARATOR MODULE BLOCK DIAGRAM CCH<1:0> CREF EVPOL<1:0> Trigger/Interrupt CEVT CXINB CPOL Logic COE CXINC(1) Input VIN- Select VIN+ C1 CXIND(1) Logic C1OUT Pin COUT VBG/2 (Note 2) EVPOL<1:0> Trigger/Interrupt CEVT Logic CPOL COE CXINA VIN- C2 CVREF VIN+ C2OUT Pin COUT Note 1: These inputs are unavailable on 14-pin (PIC24FXXKL100/200) devices. 2: Comparator 2 is unimplemented on PIC24FXXKL10X/20X devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 167

PIC24F16KL402 FAMILY FIGURE 20-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON=0, CREF=x, CCH<1:0>=xx COE VIN- – Cx VIN+ Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare(1) CON=1, CREF=0, CCH<1:0>=00 CON=1, CREF=0, CCH<1:0>=01 COE COE CXINB VIN- – CXINC VIN- – Cx Cx VIN+ VIN+ CXINA CxOUT CXINA CxOUT Pin Pin Comparator CxIND > CxINA Compare(1) Comparator VBG > CxINA Compare CON=1, CREF=0, CCH<1:0>=10 CON=1, CREF=0, CCH<1:0>=11 COE COE CXIND VIN- – VBG/2 VIN- – Cx Cx VIN+ VIN+ CXINA CxOUT CXINA CxOUT Pin Pin Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare(1) CON=1, CREF=1, CCH<1:0>=00 CON=1, CREF=1, CCH<1:0>=01 COE COE CXINB VIN- – CXINC VIN- – Cx Cx VIN+ VIN+ CVREF CxOUT CVREF CxOUT Pin Pin Comparator CxIND > CVREF Compare(1) Comparator VBG > CVREF Compare CON=1, CREF=1, CCH<1:0>=10 CON=1, CREF=1, CCH<1:0>=11 COE COE CXIND VIN- – VBG/2 VIN- – Cx Cx VIN+ VIN+ CVREF CxOUT CVREF CxOUT Pin Pin Note 1: This configuration is unavailable on 14-pin (PIC24FXXKL100/200) devices. DS30001037C-page 168  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0 CON COE CPOL CLPWR — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1(1) EVPOL0(1) — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12 CLPWR: Comparator Low-Power Mode Select bit 1 = Comparator operates in Low-Power mode 0 = Comparator does not operate in Low-Power mode bit 11-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits(1) 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT=0) 10 = Trigger/event/interrupt is generated on the high-to-low transition of the comparator output 01 = Trigger/event/Interrupt is generated on the low-to-high transition of the comparator output 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CxINA pin Note 1: If EVPOL<1:0> is set to a value other than ‘00’, the first interrupt generated will occur on any transition of COUT, regardless of if it is a rising or falling edge. Subsequent interrupts will occur based on the EVPOLx bits setting. 2: Unimplemented on 14-pin (PIC24FXXKL100/200) devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 169

PIC24F16KL402 FAMILY REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTER (CONTINUED) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of the comparator connects to VBG/2 10 = Inverting input of the comparator connects to the CxIND pin(2) 01 = Inverting input of the comparator connects to the CxINC pin(2) 00 = Inverting input of the comparator connects to the CxINB pin Note 1: If EVPOL<1:0> is set to a value other than ‘00’, the first interrupt generated will occur on any transition of COUT, regardless of if it is a rising or falling edge. Subsequent interrupts will occur based on the EVPOLx bits setting. 2: Unimplemented on 14-pin (PIC24FXXKL100/200) devices. REGISTER 20-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC CMIDL — — — — — C2EVT(1) C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC — — — — — — C2OUT(1) C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all enabled comparators in Idle mode bit 14-10 Unimplemented: Read as ‘0’ bit 9 C2EVT: Comparator 2 Event Status bit (read-only)(1) Shows the current event status of Comparator 2 (CM2CON<9>). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). bit 7-2 Unimplemented: Read as ‘0’ bit 1 C2OUT: Comparator 2 Output Status bit (read-only)(1) Shows the current output of Comparator 2 (CM2CON<8>). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>). Note 1: These bits are unimplemented on PIC24FXXKL10X/20X devices. DS30001037C-page 170  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 21.0 COMPARATOR VOLTAGE 21.1 Configuring the Comparator REFERENCE Voltage Reference The comparator voltage reference module is controlled Note: This data sheet summarizes the features of through the CVRCON register (Register21-1). The this group of PIC24F devices. It is not comparator voltage reference provides a range of intended to be a comprehensive reference output voltages, with 32 distinct levels. source. For more information on the Comparator Voltage Reference, refer to the The comparator voltage reference supply voltage can “dsPIC33/PIC24 Family Reference Man- come from either VDD and VSS, or the external VREF+ ual”, “Comparator Voltage Reference and VREF-. The voltage source is selected by the Module” (DS39709). CVRSS bit (CVRCON<5>). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 21-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ AVDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U 32 Steps M 1 CVREF o- 2-t 3 R R R 8R CVRSS = 1 VREF- CVRSS = 0 AVSS  2011-2013 Microchip Technology Inc. DS30001037C-page 171

PIC24F16KL402 FAMILY REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin bit 5 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF- 0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 4-0 CVR<4:0>: Comparator VREF Value Selection 0 ≤ CVR<4:0> ≤ 31 bits When CVRSS = 1: CVREF = (VREF-) + (CVR<4:0>/32) • (VREF+ – VREF-) When CVRSS = 0: CVREF = (AVSS) + (CVR<4:0>/32) • (AVDD – AVSS) DS30001037C-page 172  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 22.0 HIGH/LOW-VOLTAGE DETECT An interrupt flag is set if the device experiences an (HLVD) excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will Note: This data sheet summarizes the features of branch to the interrupt vector address and the software this group of PIC24F devices. It is not can then respond to the interrupt. intended to be a comprehensive reference The HLVD Control register (see Register22-1) source. For more information on the completely controls the operation of the HLVD module. High/Low-Voltage Detect, refer to the This allows the circuitry to be “turned off” by the user “dsPIC33/PIC24 Family Reference under software control, which minimizes the current Manual”, “High-Level Integration with consumption for the device. Programmable High/Low-Voltage Detect (HLVD)” (DS39725). The High/Low-Voltage Detect module (HLVD) is a programmable circuit that allows the user to specify both the device voltage trip point and the direction of change. FIGURE 22-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM Externally Generated Trip Point VDD VDD HLVDIN HLVDL<3:0> HLVDEN VDIR X U M Set 1 – HLVDIF o- 6-t 1 Internal Voltage Reference 1.2V Typical HLVDEN  2011-2013 Microchip Technology Inc. DS30001037C-page 173

PIC24F16KL402 FAMILY REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 HLSIDL: HLVD Stop in Idle Mode bit 1 = Discontinues module operation when the device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 VDIR: Voltage Change Direction Select bit 1 = Event occurs when the voltage equals or exceeds the trip point (HLVDL<3:0>) 0 = Event occurs when the voltage equals or falls below the trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the internal reference voltage is stable and the High-Voltage Detect logic generates the interrupt flag at the specified voltage range 0 = Indicates that the internal reference voltage is unstable and the High-Voltage Detect logic will not generate the interrupt flag at the specified voltage range, and the HLVD interrupt should not be enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 HLVDL<3:0>: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Trip Point 14(1) 1101 = Trip Point 13(1) 1100 = Trip Point 12(1) . . . 0000 = Trip Point 0(1) Note 1: For the actual trip point, see Section26.0 “Electrical Characteristics”. DS30001037C-page 174  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 23.0 SPECIAL FEATURES The General Segment, configured via the FGS Config- uration register, can have two levels of security: Note: This data sheet summarizes the features of • No Security (GSS0 = 1): The GS is not this group of PIC24F devices. It is not code-protected and can be read in all modes. intended to be a comprehensive reference • Standard Security (GSS0 = 0): The GS is source. For more information on the code-protected, preventing ICSP reads of the Watchdog Timer, High-Level Device Flash memory. Integration and Programming Diagnostics, refer to the individual sections of the For more detailed information on these Security “dsPIC33/PIC24 Family Reference modes, refer to the “dsPIC33/PIC24 Family Reference Manual” provided below: Manual”, “CodeGuard™ Security” (DS70199). • “Watchdog Timer (WDT)” (DS39697) 23.2 Configuration Bits • “High-Level Integration with Programmable High/Low-Voltage The Configuration bits can be programmed (read as ‘0’), Detect (HLVD)” (DS39725) or left unprogrammed (read as ‘1’), to select various • “Programming and Diagnostics” device configurations. These bits are mapped starting at (DS39716) program memory location, F80000h. A complete list is provided in Table23-1. A detailed explanation of the PIC24F16KL402 family devices include several various bit functions is provided in Register23-1 through features intended to maximize application flexibility and Register23-7. reliability, and minimize cost through elimination of external components. These are: The address, F80000h, is beyond the user program memory space. In fact, it belongs to the configuration • Flexible Configuration memory space (800000h-FFFFFFh), which can only be • Watchdog Timer (WDT) accessed using Table Reads and Table Writes. • Code Protection • In-Circuit Serial Programming™ (ICSP™) TABLE 23-1: CONFIGURATION REGISTERS • In-Circuit Emulation LOCATIONS • Factory Programmed Unique ID Configuration Address Register 23.1 Code Protect Security Options FBS F80000 The Boot Segment (BS) and General Segment (GS) FGS F80004 are two segments on this device with separate programmable security levels. The Boot Segment, con- FOSCSEL F80006 figured via the FBS Configuration register, can have FOSC F80008 three possible levels of security: FWDT F8000A • No Security (BSS = 111): The Boot Segment is FPOR F8000C not utilized and all addresses in program memory FICD F8000E are part of the General Segment (GS). • Standard Security (BSS = 110 or 101): The Boot Segment is enabled and code-protected, preventing ICSP reads of the Flash memory. Standard security also prevents Flash reads and writes of the BS from the GS. The BS can still read and write to itself. • High Security (BSS = 010 or 001): The Boot Segment is enabled with all of the security pro- vided by Standard Security mode. In addition, in High-Security mode, there are program flow change restrictions in place. While executing from the GS, program flow changes that attempt to enter the BS (e.g., branch (BRA) or CALL instructions) can only enter the BS at one of the first 32 instruc- tion locations (0x200 to 0x23F). Attempting to jump into the BS at an instruction higher than this will result in an Illegal Opcode Reset.  2011-2013 Microchip Technology Inc. DS30001037C-page 175

PIC24F16KL402 FAMILY REGISTER 23-1: FBS: BOOT SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 R/C-1(1) R/C-1(1) R/C-1(1) R/C-1(1) — — — — BSS2 BSS1 BSS0 BWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-1 BSS<2:0>: Boot Segment Program Flash Code Protection bits(1) 111 = No Boot Segment; all program memory space is General Segment 110 = Standard security Boot Segment starts at 0200h, ends at 0AFEh 101 = Standard security Boot Segment starts at 0200h, ends at 15FEh(2) 100 = Reserved 011 = Reserved 010 = High-security Boot Segment starts at 0200h, ends at 0AFEh 001 = High-security Boot Segment starts at 0200h, ends at 15FEh(2) 000 = Reserved bit 0 BWRP: Boot Segment Program Flash Write Protection bit(1) 1 = Boot Segment may be written 0 = Boot Segment is write-protected Note 1: Code protection bits can only be programmed by clearing them. They can be reset to their default factory state (‘1’), but only by performing a bulk erase and reprogramming the entire device. 2: This selection is available only on PIC24F16KL40X devices. REGISTER 23-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/C-1(1) R/C-1(1) — — — — — — GSS0 GWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 GSS0: General Segment Code Flash Code Protection bit(1) 1 = No protection 0 = Standard security is enabled bit 0 GWRP: General Segment Code Flash Write Protection bit(1) 1 = General Segment may be written 0 = General Segment is write-protected Note 1: Code protection bits can only be programmed by clearing them. They can be reset to their default factory state (‘1’), but only by performing a bulk erase and reprogramming the entire device. DS30001037C-page 176  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 23-3: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-0 R/P-0 R/P-1 IESO LPRCSEL SOSCSRC — — FNOSC2 FNOSC1 FNOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) bit 6 LPRCSEL: Internal LPRC Oscillator Power Select bit 1 = High-Power/High-Accuracy mode 0 = Low-Power/Low-Accuracy mode bit 5 SOSCSRC: Secondary Oscillator Clock Source Configuration bit 1 = SOSC analog crystal function is available on the SOSCI/SOSCO pins 0 = SOSC crystal is disabled; digital SCLKI function is selected on the SOSCO pin bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 FNOSC<2:0>: Oscillator Selection bits 111 = 8 MHz FRC Oscillator with Divide-by-N (FRCDIV) 110 = 500 kHz Low-Power FRC Oscillator with Divide-by-N (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Divide-by-N with PLL module (FRCDIV+PLL) 000 = 8 MHz FRC Oscillator (FRC)  2011-2013 Microchip Technology Inc. DS30001037C-page 177

PIC24F16KL402 FAMILY REGISTER 23-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-0 R/P-0 R/P-1 R/P-1 R/P-1 R/P-0 R/P-1 R/P-1 FCKSM1 FCKSM0 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 5 SOSCSEL: Secondary Oscillator Power Selection Configuration bit 1 = Secondary oscillator is configured for high-power operation 0 = Secondary oscillator is configured for low-power operation bit 4-3 POSCFREQ<1:0>: Primary Oscillator Frequency Range Configuration bits 11 = Primary oscillator/external clock input frequency is greater than 8 MHz 10 = Primary oscillator/external clock input frequency is between 100 kHz and 8 MHz 01 = Primary oscillator/external clock input frequency is less than 100 kHz 00 = Reserved; do not use bit 2 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal is active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or 00) 0 = CLKO output is disabled bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator mode is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = External Clock mode is selected DS30001037C-page 178  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 23-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 R/P-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN1 WINDIS FWDTEN0 FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7,5 FWDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT is enabled in hardware 10 = WDT is controlled with the SWDTEN bit setting 01 = WDT is enabled only while device is active; WDT is disabled in Sleep, SWDTEN bit is disabled 00 = WDT is disabled in hardware; SWDTEN bit is disabled bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard WDT is selected; windowed WDT is disabled 0 = Windowed WDT is enabled; note that executing a CLRWDT instruction while the WDT is disabled in hardware and software (FWDTEN<1:0> = 00 and SWDTEN (RCON<5> = 0) will not cause a device Reset bit 4 FWPSA: WDT Prescaler bit 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32 bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1  2011-2013 Microchip Technology Inc. DS30001037C-page 179

PIC24F16KL402 FAMILY REGISTER 23-6: FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 R/P-1 R/P-1 MCLRE(1) BORV1(2) BORV0(2) I2C1SEL(3) PWRTEN — BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit(1) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is disabled bit 6-5 BORV<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset is set to the low trip point 10 = Brown-out Reset is set to the middle trip point 01 = Brown-out Reset is set to the high trip point 00 = Downside protection on POR is enabled (Low-Power BOR is selected) bit 4 I2C1SEL: Alternate MSSP1 I2C™ Pin Mapping bit(3) 1 = Default location for SCL1/SDA1 pins (RB8 and RB9) 0 = Alternate location for SCL1/SDA1 pins (ASCL1/RB6 and ASDA1/RB5) bit 3 PWRTEN: Power-up Timer Enable bit 1 = PWRT is enabled 0 = PWRT is disabled bit 2 Unimplemented: Read as ‘0’ bit 1-0 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR is enabled in hardware; SBOREN bit is disabled 10 = BOR is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled 01 = BOR is controlled with the SBOREN bit setting 00 = BOR is disabled in hardware; SBOREN bit is disabled Note 1: The MCLRE fuse can only be changed when using the VPP-Based ICSP™ mode entry. This prevents a user from accidentally locking out the device from the low-voltage test entry. 2: Refer to Table26-5 for BOR trip point voltages. 3: Implemented in 28-pin devices only. This bit position must be programmed (= 1) in all other devices for I2C functionality to be available. DS30001037C-page 180  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 23-7: FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER R/P-1 U-1 U-1 U-0 U-0 U-0 R/P-1 R/P-1 DEBUG — — — — — ICS1 ICS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled bit 6-5 Unimplemented: Read as ‘1’ bit 4-2 Unimplemented: Read as ‘0’ bit 1-0 ICS<1:0:> ICD Pin Select bits 11 = PGEC1/PGED1 are used for programming and debugging the device(1) 10 = PGEC2/PGED2 are used for programming and debugging the device 01 = PGEC3/PGED3 are used for programming and debugging the device 00 = Reserved; do not use Note 1: PGEC1/PGED1 are not available on PIC24F04KL100 (14-pin) devices.  2011-2013 Microchip Technology Inc. DS30001037C-page 181

PIC24F16KL402 FAMILY 23.3 Unique ID To ensure a globally Unique ID across other Microchip microcontroller families, the “Unique ID” value should A read-only Unique ID value is stored at addresses, be further concatenated with the family and Device ID 800802h through 800808h. This factory programmed values stored at address, FF0000h. value is unique to each microcontroller produced in the PIC24F16KL402 family. To access this region, use Table Read instructions or Program Space Visibility. REGISTER 23-8: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘0’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 01001011 = PIC24F16KL402 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 00000001 = PIC24F04KL100 00000010 = PIC24F04KL101 00000101 = PIC24F08KL200 00000110 = PIC24F08KL201 00001010 = PIC24F08KL301 00000000 = PIC24F08KL302 00001110 = PIC24F08KL401 00000100 = PIC24F08KL402 00011110 = PIC24F16KL401 00010100 = PIC24F16KL402 DS30001037C-page 182  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY REGISTER 23-9: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Revision Identifier bits  2011-2013 Microchip Technology Inc. DS30001037C-page 183

PIC24F16KL402 FAMILY 23.4 Watchdog Timer (WDT) The WDT Time-out Flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To For the PIC24F16KL402 family of devices, the WDT is detect subsequent WDT events, the flag must be driven by the LPRC oscillator. When the WDT is cleared in software. enabled, the clock source is also enabled. Note: The CLRWDT and PWRSAV instructions The nominal WDT clock source from LPRC is 31kHz. clear the prescaler and postscaler counts This feeds a prescaler that can be configured for either when executed. 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. 23.4.1 WINDOWED OPERATION With a 31kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1ms in 5-bit mode or The Watchdog Timer has an optional Fixed Window 4ms in 7-bit mode. mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 A variable postscaler divides down the WDT prescaler of the programmed WDT period. A CLRWDT instruction, output and allows for a wide range of time-out periods. executed before that window, causes a WDT Reset The postscaler is controlled by the Configuration bits, similar to a WDT time-out. WDTPS<3:0> (FWDT<3:0>), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the Windowed WDT mode is enabled by programming the prescaler and postscaler time-out periods, ranges from Configuration bit, WINDIS (FWDT<6>), to ‘0’. 1ms to 131 seconds can be achieved. 23.4.2 CONTROL REGISTER The WDT, prescaler and postscaler are reset: The WDT is enabled or disabled by the FWDTEN<1:0> • On any device Reset Configuration bits. When both the FWDTEN<1:0> • On the completion of a clock switch, whether Configuration bits are set, the WDT is always enabled. invoked by software (i.e., setting the OSWEN bit after changing the NOSCx bits) or by hardware The WDT can be optionally controlled in software when (i.e., Fail-Safe Clock Monitor) the FWDTEN<1:0> Configuration bits have been pro- • When a PWRSAV instruction is executed grammed to ‘10’. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The (i.e., Sleep or Idle mode is entered) SWDTEN control bit is cleared on any device Reset. • When the device exits Sleep or Idle mode to The software WDT option allows the user to enable the resume normal operation WDT for critical code segments, and disable the WDT • By a CLRWDT instruction during normal execution during non-critical segments, for maximum power sav- If the WDT is enabled in hardware (FWDTEN<1:0> = 11), ings. When the FWTEN<1:0> bits are set to ‘01’, the it will continue to run during Sleep or Idle modes. When WDT is enabled only in Run and Idle modes, and is dis- the WDT time-out occurs, the device will wake and code abled in Sleep. Software control of the WDT SWDTEN execution will continue from where the PWRSAV bit (RCON<5>) is disabled with this setting. instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after the device wakes up. FIGURE 23-1: WDT BLOCK DIAGRAM SWDTEN LPRC Control FWDTEN Wake from Sleep FWPSA WDTPS<3:0> Prescaler WDT Postscaler WDT Overflow LPRC Input (5-Bit/7-Bit) Counter 1:1 to 1:32.768 Reset 31 kHz 1 ms/4 ms All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS30001037C-page 184  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 23.5 Program Verification and 23.7 In-Circuit Debugger Code Protection When MPLAB® ICD 3, MPLAB REAL ICE™ or For all devices in the PIC24F16KL402 family, code PICkit™3 is selected as a debugger, the in-circuit protection for the Boot Segment is controlled by the debugging functionality is enabled. This function allows BSS<2:0> Configuration bits and the General Segment simple debugging functions when used with by the Configuration bit, GSS0. These bits inhibit exter- MPLABIDE. Debugging functionality is controlled nal reads and writes to the program memory space through the PGECx and PGEDx pins. This has no direct effect in normal execution mode. To use the in-circuit debugger function of the device, Write protection is controlled by bit, BWRP, for the Boot the design must implement ICSP connections to Segment and bit, GWRP, for the General Segment in MCLR, VDD, VSS, PGECx, PGEDx and the pin pair. In the Configuration Word. When these bits are pro- addition, when the feature is enabled, some of the grammed to ‘0’, internal write and erase operations to resources are not available for general use. These program memory are blocked. resources include the first 80 bytes of data RAM and two I/O pins. 23.6 In-Circuit Serial Programming PIC24F16KL402 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.  2011-2013 Microchip Technology Inc. DS30001037C-page 185

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 186  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 24.0 DEVELOPMENT SUPPORT 24.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2011-2013 Microchip Technology Inc. DS30001037C-page 187

PIC24F16KL402 FAMILY 24.2 MPLAB XC Compilers 24.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other related modules together relocatable object files and archives to create an exe- • Flexible creation of libraries with easy module cutable file. MPLAB XC Compiler uses the assembler listing, replacement, deletion and extraction to produce its object file. Notable features of the assembler include: 24.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 24.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS30001037C-page 188  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 24.6 MPLAB X SIM Software Simulator 24.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 24.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 24.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com- with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 24.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2011-2013 Microchip Technology Inc. DS30001037C-page 189

PIC24F16KL402 FAMILY 24.11 Demonstration/Development 24.12 Third-Party Development Tools Boards, Evaluation Kits and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS30001037C-page 190  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 25.0 INSTRUCTION SET SUMMARY The literal instructions that involve data movement may use some of the following operands: Note: This chapter is a brief summary of the • A literal value to be loaded into a W register or file PIC24F Instruction Set Architecture (ISA) register (specified by the value of ‘k’) and is not intended to be a comprehensive • The W register or file register where the literal reference source. value is to be loaded (specified by ‘Wb’ or ‘f’) The PIC24F instruction set adds many enhancements However, literal instructions that involve arithmetic or to the previous PIC® MCU instruction sets, while logical operations use some of the following operands: maintaining an easy migration from previous PIC MCU • The first source operand, which is a register ‘Wb’ instruction sets. Most instructions are a single program without any address modifier memory word. Only three instructions require two program memory locations. • The second source operand, which is a literal value Each single-word instruction is a 24-bit word divided • The destination of the result (only if not the same into an 8-bit opcode, which specifies the instruction as the first source operand), which is typically a type and one or more operands, which further specify register ‘Wd’ with or without an address modifier the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic The control instructions may use some of the following categories: operands: • Word or byte-oriented operations • A program memory address • Bit-oriented operations • The mode of the Table Read and Table Write • Literal operations instructions • Control operations All instructions are a single word, except for certain double-word instructions, which were made Table25-1 lists the general symbols used in describing double-word instructions so that all of the required the instructions. The PIC24F instruction set summary information is available in these 48 bits. In the second in Table25-2 lists all the instructions, along with the word, the 8MSbs are ‘0’s. If this second word is status flags affected by each instruction. executed as an instruction (by itself), it will execute as Most word or byte-oriented W register instructions a NOP. (including barrel shift instructions) have three Most single-word instructions are executed in a single operands: instruction cycle, unless a conditional test is true or the • The first source operand, which is typically a Program Counter (PC) is changed as a result of the register ‘Wb’ without any address modifier instruction. In these cases, the execution takes two • The second source operand, which is typically a instruction cycles, with the additional instruction register ‘Ws’ with or without an address modifier cycle(s) executed as a NOP. Notable exceptions are the • The destination of the result, which is typically a BRA (unconditional/computed branch), indirect register ‘Wd’ with or without an address modifier CALL/GOTO, all Table Reads and Table Writes, and RETURN/RETFIE instructions, which are single-word However, word or byte-oriented file register instructions instructions but take two or three cycles. have two operands: Certain instructions that involve skipping over the • The file register specified by the value, ‘f’ subsequent instruction require either two or three • The destination, which could either be the file cycles if the skip is performed, depending on whether register, ‘f’, or the W0 register, which is denoted the instruction being skipped is a single-word or as ‘WREG’ two-word instruction. Moreover, double-word moves Most bit-oriented instructions (including simple require two cycles. The double-word instructions rotate/shift instructions) have two operands: execute in two instruction cycles. • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’)  2011-2013 Microchip Technology Inc. DS30001037C-page 191

PIC24F16KL402 FAMILY TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor Working register pair (direct addressing) Wn One of 16 Working registers {W0..W15} Wnd One of 16 destination Working registers {W0..W15} Wns One of 16 source Working registers {W0..W15} WREG W0 (Working register used in File register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS30001037C-page 192  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2011-2013 Microchip Technology Inc. DS30001037C-page 193

PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep COM COM f f = f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C, DC, N, OV, Z (Wb – Ws – C) CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 C DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DS30001037C-page 194  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC INC f f = f + 1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z IOR IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None POP.S Pop Shadow Registers 1 1 All PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None  2011-2013 Microchip Technology Inc. DS30001037C-page 195

PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None DS30001037C-page 196  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N  2011-2013 Microchip Technology Inc. DS30001037C-page 197

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 198  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 26.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24F16KL402 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F16KL402 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.5V Voltage on any combined analog and digital pin, with respect to VSS ...........................................-0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V) Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(1)...........................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(1)...............................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table26-1). † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2011-2013 Microchip Technology Inc. DS30001037C-page 199

PIC24F16KL402 FAMILY 26.1 DC Characteristics FIGURE 26-1: PIC24F16KL402 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.60V 3.00V 3.00V )D D V ( e 1.80V g a t ol V 8 MHz 32 MHz Frequency Note: For frequencies between 8MHz and 32MHz, FMAX = 20 MHz * (VDD – 1.8) + 8 MHz. FIGURE 26-2: PIC24F16KL402 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED) 3.60V 3.60V 3.00V 3.00V )D D V ( e 1.80V g a t ol V 8 MHz 24 MHz Frequency Note: For frequencies between 8MHz and 24MHz, FMAX = 13.33 MHz * (VDD – 1.8) + 8 MHz. DS30001037C-page 200  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 26-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 26-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 20-Pin PDIP JA 62.4 — °C/W 1 Package Thermal Resistance, 28-Pin SPDIP JA 60 — °C/W 1 Package Thermal Resistance, 20-Pin SSOP JA 108 — °C/W 1 Package Thermal Resistance, 28-Pin SSOP JA 71 — °C/W 1 Package Thermal Resistance, 20-Pin SOIC JA 75 — °C/W 1 Package Thermal Resistance, 28-Pin SOIC JA 80.2 — °C/W 1 Package Thermal Resistance, 20-Pin QFN JA 43 — °C/W 1 Package Thermal Resistance, 28-Pin QFN JA 32 — °C/W 1 Package Thermal Resistance, 14-Pin PDIP JA 62.4 — °C/W 1 Package Thermal Resistance, 14-Pin TSSOP JA 108 — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. TABLE 26-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Para Symbol Characteristic Min Typ(1) Max Units Conditions m No. DC10 VDD Supply Voltage 1.8 — 3.6 V DC12 VDR RAM Data Retention 1.5 — — V Voltage(2) DC16 VPOR VDD Start Voltage VSS — 0.7 V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-3.3V in 0.1s to Ensure Internal 0-2.5V in 60ms Power-on Reset Signal VBG Band Gap Voltage 1.14 1.2 1.26 V Reference Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: This is the limit to which VDD can be lowered without losing RAM data.  2011-2013 Microchip Technology Inc. DS30001037C-page 201

PIC24F16KL402 FAMILY TABLE 26-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. DC18 VHLVD HLVD Voltage on VDD HLVDL<3:0> = 0000 — 1.85 1.94 V Transition HLVDL<3:0> = 0001 1.81 1.90 2.00 V HLVDL<3:0> = 0010 1.85 1.95 2.05 V HLVDL<3:0> = 0011 1.90 2.00 2.10 V HLVDL<3:0> = 0100 1.95 2.05 2.15 V HLVDL<3:0> = 0101 2.06 2.17 2.28 V HLVDL<3:0> = 0110 2.12 2.23 2.34 V HLVDL<3:0> = 0111 2.24 2.36 2.48 V HLVDL<3:0> = 1000 2.31 2.43 2.55 V HLVDL<3:0> = 1001 2.47 2.60 2.73 V HLVDL<3:0> = 1010 2.64 2.78 2.92 V HLVDL<3:0> = 1011 2.74 2.88 3.02 V HLVDL<3:0> = 1100 2.85 3.00 3.15 V HLVDL<3:0> = 1101 2.96 3.12 3.28 V HLVDL<3:0> = 1110 3.22 3.39 3.56 V TABLE 26-5: BOR TRIP POINTS Standard Operating Conditions: 1.8V to 3.6V Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. DC19 BOR Voltage on VDD BORV = 00 1.85 2.0 2.15 V Note 1 Transition BORV = 01 2.90 3.0 3.38 V BORV = 10 2.53 2.7 3.07 V BORV = 11 1.75 1.85 2.05 V Note 1: LPBOR re-arms the POR circuit but does not cause a BOR. DS30001037C-page 202  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)(2) Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max Units Conditions IDD Current DC20 0.154 0.350 1.8V mA +85V°C 0.301 0.630 3.3V 0.5 MIPS, — .500 1.8V FOSC = 1 MHz mA +125°C — .800 3.3V DC22 0.300 — 1.8V 1 MIPS, mA +85°C 0.585 — 3.3V FOSC = 2 MHz DC24 7.76 12.0 3.3V +85°C 16 MIPS, mA — 18.0 3.3V +125°C FOSC = 32 MHz DC26 1.44 — 1.8V FRC (4 MIPS), mA +85°C 2.71 — 3.3V FOSC = 8 MHz DC30 4.00 28.0 1.8V µA +85°C 9.00 55.0 3.3V LPRC (15.5 KIPS), — 45.0 1.8V FOSC = 31 kHz µA +125°C — 90.0 3.3V Note 1: Data in the Typical column is at 3.3V, +25°C, unless otherwise stated. 2: IDD is measured with all peripherals disabled. All I/Os are configured as outputs and set low; PMDx bits are set to ‘1’ and WDT, etc., are all disabled. TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)(2) Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE) DC40 0.035 0.080 1.8V mA +85°C 0.077 0.150 3.3V 0.5 MIPS, — 0.160 1.8V FOSC = 1 MHz mA +125°C — 0.300 3.3V DC42 0.076 — 1.8V 1 MIPS, mA +85°C 0.146 — 3.3V FOSC = 2 MHz DC44 2.52 3.20 mA 3.3V +85°C 16 MIPS, — 5.00 mA 3.3V +125°C FOSC = 32 MHz DC46 0.45 — mA 1.8V FRC (4 MIPS), +85°C 0.76 — mA 3.3V FOSC = 8 MHz DC50 0.87 18.0 µA 1.8V +85°C 1.55 40.0 µA 3.3V LPRC (15.5 KIPS), — 27.0 µA 1.8V FOSC = 31 kHz +125°C — 50.0 µA 3.3V Note 1: Data in the Typical column is at 3.3V, +25°C, unless otherwise stated. 2: IIDLE is measured with all I/Os configured as outputs and set low; PMDx bits are set to ‘1’ and WDT, etc., are all disabled.  2011-2013 Microchip Technology Inc. DS30001037C-page 203

PIC24F16KL402 FAMILY TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD) DC60 0.01 0.20 µA -40°C 0.03 0.20 µA +25°C 0.06 0.87 µA +60°C 1.8V 0.20 1.35 µA +85°C — 8.00 µA +125ºC Sleep Mode(2) 0.01 0.54 µA -40°C 0.03 0.54 µA +25°C 0.08 1.68 µA +60°C 3.3V 0.25 2.45 µA +85°C — 10.00 µA +125ºC Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: Base IPD is measured with all peripherals and clocks disabled. All I/Os are configured as outputs and set low; PMDx bits are set to ‘1’ and WDT, etc., are all disabled DS30001037C-page 204  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 26-9: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max Units Conditions Module Differential Current (IPD) DC71 0.21 0.65 µA 1.8V +85°C 0.45 0.95 µA 3.3V Watchdog Timer Current: — 1.30 µA 1.8V WDT(2,3) +125°C — 1.50 µA 3.3V DC72 0.69 1.50 µA 1.8V 32 kHz Crystal with Timer1: +85°C 1.00 1.50 µA 3.3V SOSC (SOSCSEL = 0)(2) DC75 5.24 — µA 1.8V +85°C 5.16 11.00 µA 3.3V HLVD(2,3) — 12.00 µA 1.8V +125°C — 15.00 µA 3.3V DC76 4.15 9.00 µA 3.3V +85°C BOR(2,3) — 11.0 µA 3.3V +125°C DC78 0.03 0.20 µA 1.8V +85°C 0.03 0.20 µA 3.3V LPBOR(2) — 0.40 µA 1.8V +125°C — 0.40 µA 3.3V Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 3: This current applies to Sleep only.  2011-2013 Microchip Technology Inc. DS30001037C-page 205

PIC24F16KL402 FAMILY TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage(4) DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C™ Buffer VSS — 0.3 VDD V SMBus disabled DI19 I/O Pins with SMBus Buffer VSS — 0.8 V SMBus enabled VIH Input High Voltage(4,5) DI20 I/O Pins: with Analog Functions 0.8 VDD — VDD V Digital Only 0.8 VDD — VDD V DI25 MCLR 0.8 VDD — VDD V DI26 OSCI (XT mode) 0.7 VDD — VDD V DI27 OSCI (HS mode) 0.7 VDD — VDD V DI28 I/O Pins with I2C Buffer: with Analog Functions 0.7 VDD — VDD V Digital Only 0.7 VDD — VDD V DI29 I/O Pins with SMBus 2.1 — VDD V 2.5V  VPIN  VDD DI30 ICNPU CNx Pull-up Current 50 250 500 A VDD = 3.3V, VPIN = VSS DI31 IPU Maximum Load Current — — 30 A VDD = 2.0V for Digital High Detection — — 1000 A VDD = 3.3V w/Internal Pull-up IIL Input Leakage Current(2,3) DI50 I/O Ports — 0.050 ±0.100 A VSS  VPIN  VDD, Pin at high-impedance DI51 VREF+, VREF-, AN0, AN1 — 0.300 ±0.500 A VSS  VPIN  VDD, Pin at high-impedance Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Refer to Table1-4 and Table1-5 for I/O pin buffer types. 5: VIH requirements are met when the internal pull-ups are enabled. DS30001037C-page 206  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 26-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. VOL Output Low Voltage DO10 All I/O Pins — — 0.4 V IOL = 4.0 mA VDD = 3.6V — — 0.4 V IOL = 3.5 mA VDD = 2.0V DO16 OSC2/CLKO — — 0.4 V IOL = 1.2 mA VDD = 3.6V — — 0.4 V IOL = 0.4 mA VDD = 2.0V VOH Output High Voltage DO20 All I/O Pins 3 — — V IOH = -3.0 mA VDD = 3.6V 1.6 — — V IOH = -1.0 mA VDD = 2.0V DO26 OSC2/CLKO 3 — — V IOH = -1.0 mA VDD = 3.6V 1.6 — — V IOH = -0.5 mA VDD = 2.0V Note 1: Data in “Typ” column is at +25°C unless otherwise stated. TABLE 26-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10,000(2) — — E/W D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D133A TIW Self-Timed Write Cycle — 2 — ms Time D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D135 IDDP Supply Current During — 10 — mA Programming Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Self-write and block erase.  2011-2013 Microchip Technology Inc. DS30001037C-page 207

PIC24F16KL402 FAMILY TABLE 26-13: DC CHARACTERISTICS: DATA EEPROM MEMORY Standard Operating Conditions: 1.8V to 3.6V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. Data EEPROM Memory D140 EPD Cell Endurance 100,000 — — E/W D141 VPRD VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D143A TIWD Self-Timed Write Cycle — 4 — ms Time D143B TREF Number of Total — 10M — E/W Write/Erase Cycles Before Refresh D144 TRETDD Characteristic Retention 40 — — Year Provided no other specifications are violated D145 IDDPD Supply Current during — 7 — mA Programming Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. TABLE 26-14: DC CHARACTERISTICS: COMPARATOR Standard Operating Conditions: 2.0V < VDD < 3.6V Operating temperature -40°C < TA  +85°C (unless otherwise stated) -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — 20 40 mV D301 VICM Input Common-Mode Voltage 0 — VDD V D302 CMRR Common-Mode Rejection 55 — — dB Ratio TABLE 26-15: DC CHARACTERISTICS: COMPARATOR VOLTAGE REFERENCE Standard Operating Conditions: 2.0V < VDD < 3.6V Operating temperature -40°C < TA  +85°C (unless otherwise stated) -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Comments No. VRD310 CVRES Resolution — — VDD/32 LSb VRD311 CVRAA Absolute Accuracy — — AVDD – 1.5 LSb VRD312 CVRUR Unit Resistor Value (R) — 2k —  DS30001037C-page 208  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 26.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24F16KL402 Family AC characteristics and timing parameters. TABLE 26-16: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Operating voltage VDD range as described in Section26.1 “DC Characteristics”. FIGURE 26-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for All Pins Except OSCO Load Condition 2 – for OSCO VDD/2 RL Pin CL VSS Pin CL RL = 464 CL = 50 pF for all pins except OSCO VSS 15 pF for OSCO output TABLE 26-17: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO50 COSC2 OSCO/CLKO Pin — — 15 pF In XT and HS modes when external clock is used to drive OSCI DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2011-2013 Microchip Technology Inc. DS30001037C-page 209

PIC24F16KL402 FAMILY FIGURE 26-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 26-18: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. OS10 FOSC External CLKI Frequency DC — 32 MHz EC (External clocks allowed 4 — 8 MHz ECPLL only in EC mode) Oscillator Frequency 0.2 — 4 MHz XT 4 — 25 MHz HS 4 — 8 MHz HSPLL 31 — 33 kHz SOSC OS20 TOSC TOSC = 1/FOSC — — — — See Parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(2) 62.5 — DC ns OS30 TosL, External Clock in (OSCI) 0.45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock in (OSCI) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3) — 6 10 ns OS41 TckF CLKO Fall Time(3) — 6 10 ns Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS30001037C-page 210  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 26-19: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic(1) Min Typ(2) Max Units Conditions No. OS50 FPLLI PLL Input Frequency 4 — 8 MHz ECPLL, HSPLL modes, Range -40°C  TA  +85°C OS51 FSYS PLL Output Frequency 16 — 32 MHz -40°C  TA  +85°C Range OS52 TLOCK PLL Start-up Time — 1 2 ms (Lock Time) OS53 DCLK CLKO Stability (Jitter) -2 1 2 % Measured over 100 ms period Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 26-20: INTERNAL RC OSCILLATOR ACCURACY Standard Operating Conditions: 1.8V to 3.6V AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. F20 FRC @ 8 MHz(1) -2 — +2 % +25°C 3.0V  VDD  3.6V -5 — +5 % -40°C  TA +85°C 1.8V  VDD  3.6V -10 — +10 % -40°C  TA +125°C 1.8V  VDD  3.6V F21 LPRC @ 31 kHz(2) -15 — +15 % -40°C  TA +85°C 1.8V  VDD  3.6V -25 — +25 % -40°C  TA +125°C 1.8V  VDD  3.6V Note 1: The frequency is calibrated at +25°C and 3.3V. The OSCTUN bits can be used to compensate for temperature drift. 2: The change of LPRC frequency as VDD changes. TABLE 26-21: INTERNAL RC OSCILLATOR SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ Max Units Conditions No. TFRC FRC Start-up Time — 5 — s TLPRC LPRC Start-up Time — 70 — s  2011-2013 Microchip Technology Inc. DS30001037C-page 211

PIC24F16KL402 FAMILY FIGURE 26-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure26-3 for load conditions. TABLE 26-22: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx pin High or Low 20 — — ns Time (output) DI40 TRBP CNx High or Low Time 2 — — TCY (input) Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. DS30001037C-page 212  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 26-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ(1) Max. Units Conditions No. SY10 TmcL MCLR Pulse Width (low) 2 — — s SY11 TPWRT Power-up Timer Period 50 64 90 ms SY12 TPOR Power-on Reset Delay 1 5 10 s SY13 TIOZ I/O High-Impedance from — — 100 ns MCLR Low or Watchdog Timer Reset SY20 TWDT Watchdog Timer Time-out 0.85 1.0 1.15 ms 1.32 prescaler Period 3.4 4.0 4.6 ms 1:128 prescaler SY25 TBOR Brown-out Reset Pulse 1 — — s Width SY45 TRST Internal State Reset Time — 5 — s SY55 TLOCK PLL Start-up Time — 100 — s SY65 TOST Oscillator Start-up Time — 1024 — TOSC SY71 TPM Program Memory Wake-up — 1 — s Sleep wake-up with Time PMSLP = 0 Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. TABLE 26-24: COMPARATOR TIMINGS Param Symbol Characteristic Min Typ Max Units Comments No. 300 TRESP Response Time(1,2) — 150 400 ns 301 TMC2OV Comparator Mode Change to — — 10 s Output Valid(2) Note 1: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. 2: Parameters are characterized but not tested. TABLE 26-25: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Param Symbol Characteristic Min Typ Max Units Comments No. VR310 TSET Settling Time(1) — — 10 s Note 1: Settling time is measured while CVRSS = 1 and the CVR<3:0> bits transition from ‘0000’ to ‘1111’.  2011-2013 Microchip Technology Inc. DS30001037C-page 213

PIC24F16KL402 FAMILY FIGURE 26-6: CAPTURE/COMPARE/PWM TIMINGS (ECCP1, ECCP2 MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure26-3 for load conditions. TABLE 26-26: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP1, ECCP2 MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No Prescaler 0.5 TCY + 20 — ns Time With Prescaler 20 — ns 51 TCCH CCPx Input No Prescaler 0.5 TCY + 20 — ns High Time With Prescaler 20 — ns 52 TCCP CCPx Input Period Greater of: — ns N = prescale 40 or value (1, 4 or 16) 2 TCY + 40 N 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns DS30001037C-page 214  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 26-7: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SCKx (CKP = 0) 78 79 SCKx (CKP = 1) 79 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure26-3 for load conditions. TABLE 26-27: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns FSCK SCKx Frequency — 10 MHz  2011-2013 Microchip Technology Inc. DS30001037C-page 215

PIC24F16KL402 FAMILY FIGURE 26-8: EXAMPLE SPI MASTER MODE TIMING (CKE=1) 81 SCKx (CKP = 0) 79 73 SCKx (CKP = 1) 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure26-3 for load conditions. TABLE 26-28: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 35 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL FSCK SCKx Frequency — 10 MHz DS30001037C-page 216  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 26-9: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 83 71 72 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure26-3 for load conditions. TABLE 26-29: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx  to SCKx  or SCKx  Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SSx to Write to SSPxBUF 3 TCY — ns 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 83 TSCH2SSH, SSx  after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH FSCK SCKx Frequency — 10 MHz Note 1: Requires the use of Parameter 73A. 2: Only if Parameters 71A and 72A are used.  2011-2013 Microchip Technology Inc. DS30001037C-page 217

PIC24F16KL402 FAMILY FIGURE 26-10: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SSx 70 SCKx 83 (CKP = 0) 71 72 73 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure26-3 for load conditions. TABLE 26-30: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx  to SCKx  or SCKx  Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SSx to Write to SSPxBUF 3 TCY — ns 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx  to SDOx Output High-Impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid After SCKx Edge — 50 ns TSCL2DOV 82 TSSL2DOV SDOx Data Output Valid After SSx  Edge — 50 ns 83 TSCH2SSH, SSx  After SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH FSCK SCKx Frequency — 10 MHz Note 1: Requires the use of Parameter 73A. 2: Only if Parameters 71A and 72A are used. DS30001037C-page 218  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 26-11: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure26-3 for load conditions. TABLE 26-31: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 26-12: I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure26-3 for load conditions.  2011-2013 Microchip Technology Inc. DS30001037C-page 219

PIC24F16KL402 FAMILY TABLE 26-32: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz MSSP module 1.5 — TCY 101 TLOW Clock Low Time 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz MSSP module 1.5 — TCY 102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock 400 kHz mode 0.6 — s pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before 400 kHz mode 1.3 — s a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS30001037C-page 220  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY FIGURE 26-13: MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure26-3 for load conditions. TABLE 26-33: I2C™ BUS START/STOP BITS REQUIREMENTS (MASTER MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —  2011-2013 Microchip Technology Inc. DS30001037C-page 221

PIC24F16KL402 FAMILY FIGURE 26-14: MSSPx I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure26-3 for load conditions. TABLE 26-34: I2C™ BUS DATA REQUIREMENTS (MASTER MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — — 400 kHz mode 2(TOSC)(BRG + 1) — — 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — — 400 kHz mode 2(TOSC)(BRG + 1) — — 102 TR SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 103 TF SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — — Only relevant for Repeated Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — — Start condition 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — — After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — — clock pulse is generated 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 1) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — — Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — — 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but Parameter 107250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, Parameter 102 + Parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCLx line is released. DS30001037C-page 222  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY TABLE 26-35: A/D MODULE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of: — Lesser of: V VDD – 0.3 VDD + 0.3 or 1.8 or 3.6 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V AD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 V Voltage Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V (Note 1) AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 VINL Absolute VINL Input AVSS – 0.3 AVDD/2 V Voltage AD17 RIN Recommended — — 2.5K  10-bit Impedance of Analog Voltage Source A/D Accuracy AD20b NR Resolution — 10 — bits AD21b INL Integral Nonlinearity — ±1 ±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22b DNL Differential Nonlinearity — ±1 ±1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23b GERR Gain Error — ±1 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD24b EOFF Offset Error — ±1 ±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25b Monotonicity — — — — (Note 2) Note 1: Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference. 2: The A/D conversion result never decreases with an increase in the input voltage.  2011-2013 Microchip Technology Inc. DS30001037C-page 223

PIC24F16KL402 FAMILY TABLE 26-36: A/D CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 1.8V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD A/D Clock Period 75 — — ns TCY = 75 ns, AD1CON3 is in default state AD51 TRC A/D Internal RC Oscillator Period — 250 — ns Conversion Rate AD55 TCONV Conversion Time — 12 — TAD AD56 FCNV Throughput Rate — — 500 ksps AVDD  2.7V AD57 TSAMP Sample Time — 1 — TAD AD58 TACQ Acquisition Time 750 — — ns (Note 2) AD59 TSWC Switching Time from Convert to — — (Note 3) — Sample AD60 TDIS Discharge Time 0.5 — — TAD Clock Parameters AD61 TPSS Sample Start Delay from Setting 2 — 3 TAD Sample bit (SAMP) Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). 3: On the following cycle of the device clock. DS30001037C-page 224  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 14-Lead PDIP (300 mil) Example PIC24F04KL100 -I/P e3 1316012 20-Lead PDIP (300 mil) Example XXXXXXXXXXXXXXXXX PIC24F08KL201 XXXXXXXXXXXXXXXXX -I/P e3 YYWWNNN 1316012 28-Lead SPDIP (.300”) Example PIC24F16KL302 -I/SPe3 1316012 Legend: XX...X Product-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2013 Microchip Technology Inc. DS30001037C-page 225

PIC24F16KL402 FAMILY 20-Lead SOIC (7.50 mm) Example XXXXXXXXXXXX PIC24F08KL301 XXXXXXXXXXXX -I/SO e3 XXXXXXXXXXXX 1316012 YYWWNNN 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC24F08KL302 XXXXXXXXXXXXXXXXXXXX -I/SOe3 XXXXXXXXXXXXXXXXXXXX YYWWNNN 1316012 14-Lead TSSOP (4.4 mm) Example XXXXXXXX 24F08KL1 YYWW 1316 NNN 012 20-Lead SSOP (5.30 mm) Example PIC24F08KL 401-I/SS e3 1316012 DS30001037C-page 226  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY 28-Lead SSOP (5.30 mm) Example PIC24F08KL 402-I/SS e3 1316012 20-Lead QFN (5x5x0.9 mm) Example PIN 1 PIN 1 24F08 KL301 -I/MQ e3 1316012 28-Lead QFN (5x5x0.9 mm) Example PIN 1 PIN 1 24F08 KL302 -I/MQe3 1316012 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX 24F08KL3 01-I/ML e3 XXXXXXXX 1316012 YYWWNNN  2011-2013 Microchip Technology Inc. DS30001037C-page 227

PIC24F16KL402 FAMILY 27.2 Package Details The following sections give the technical details of the packages. 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(cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:20)(cid:4)(cid:29)(cid:4).(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2(cid:2)1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)01 DS30001037C-page 228  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY !(cid:24)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:24)(cid:24)(cid:9)(cid:25)(cid:14)(cid:11)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)(cid:10)(cid:16)(cid:18)(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) (cid:2) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)% (cid:19)7+8-(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:3)(cid:4) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2)1(cid:22)+ (cid:13)(cid:10)(cid:12)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) < < (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:20)(cid:29)(cid:29)0 (cid:20)(cid:29),(cid:4) (cid:20)(cid:29)(cid:24)0 1(cid:28) (cid:14)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:29) (cid:20)(cid:4)(cid:29)0 < < (cid:22)(cid:11)(cid:10)!(cid:16)"(cid:14)(cid:9)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)!(cid:16)"(cid:14)(cid:9)(cid:2)=(cid:7)"%(cid:11) - (cid:20),(cid:4)(cid:4) (cid:20),(cid:29)(cid:4) (cid:20),(cid:3)0 (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)0(cid:4) (cid:20)(cid:3)>(cid:4) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:20)(cid:24)>(cid:4) (cid:29)(cid:20)(cid:4),(cid:4) (cid:29)(cid:20)(cid:4)?(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:29)(cid:29)0 (cid:20)(cid:29),(cid:4) (cid:20)(cid:29)0(cid:4) 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:20)(cid:4)(cid:4)> (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:29)0 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ((cid:29) (cid:20)(cid:4)(cid:23)0 (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10))(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:20)(cid:4)(cid:29)(cid:23) (cid:20)(cid:4)(cid:29)> (cid:20)(cid:4)(cid:3)(cid:3) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10))(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)* (cid:14)1 < < (cid:20)(cid:23),(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) *(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)$(cid:7)(cid:8)(cid:28)(cid:15)%(cid:2)+(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)%(cid:14)(cid:9)(cid:7) %(cid:7)(cid:8)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:20)(cid:4)(cid:29)(cid:4).(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:24)1  2011-2013 Microchip Technology Inc. DS30001037C-page 229

PIC24F16KL402 FAMILY !"(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)#$(cid:14)(cid:19)(cid:19)(cid:28)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)#(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:24)(cid:24)(cid:9)(cid:25)(cid:14)(cid:11)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)#(cid:10)(cid:16)(cid:18)(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)% (cid:19)7+8-(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:3)> (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2)1(cid:22)+ (cid:13)(cid:10)(cid:12)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) < < (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:20)(cid:29)(cid:3)(cid:4) (cid:20)(cid:29),0 (cid:20)(cid:29)0(cid:4) 1(cid:28) (cid:14)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:29) (cid:20)(cid:4)(cid:29)0 < < (cid:22)(cid:11)(cid:10)!(cid:16)"(cid:14)(cid:9)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)!(cid:16)"(cid:14)(cid:9)(cid:2)=(cid:7)"%(cid:11) - (cid:20)(cid:3)(cid:24)(cid:4) (cid:20),(cid:29)(cid:4) (cid:20),,0 (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)>0 (cid:20)(cid:3)(cid:24)0 :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:29)(cid:20),(cid:23)0 (cid:29)(cid:20),?0 (cid:29)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:29)(cid:29)(cid:4) (cid:20)(cid:29),(cid:4) (cid:20)(cid:29)0(cid:4) 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:20)(cid:4)(cid:4)> (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:29)0 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ((cid:29) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)0(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10))(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:20)(cid:4)(cid:29)(cid:23) (cid:20)(cid:4)(cid:29)> (cid:20)(cid:4)(cid:3)(cid:3) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10))(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)* (cid:14)1 < < (cid:20)(cid:23),(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) *(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)$(cid:7)(cid:8)(cid:28)(cid:15)%(cid:2)+(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)%(cid:14)(cid:9)(cid:7) %(cid:7)(cid:8)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:20)(cid:4)(cid:29)(cid:4).(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1 DS30001037C-page 230  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 231

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 232  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 233

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 234  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 235

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 236  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 237

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 238  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 239

PIC24F16KL402 FAMILY !(cid:24)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)#%&(cid:14)(cid:19)$(cid:9)#(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)’(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)##(cid:21)(cid:9)(cid:22)(cid:9)()(cid:23)(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)##’(cid:10)(cid:30)(cid:9) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:3)(cid:4) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?0(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:29)(cid:20)?0 (cid:29)(cid:20)(cid:5)0 (cid:29)(cid:20)>0 (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)0 < < :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)>(cid:4) >(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) 0(cid:20)(cid:4)(cid:4) 0(cid:20),(cid:4) 0(cid:20)?(cid:4) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) ?(cid:20)(cid:24)(cid:4) (cid:5)(cid:20)(cid:3)(cid:4) (cid:5)(cid:20)0(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)00 (cid:4)(cid:20)(cid:5)0 (cid:4)(cid:20)(cid:24)0 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:3)0(cid:2)(cid:26)-3 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) < (cid:4)(cid:20)(cid:3)0 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)V (cid:23)V >V 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20)(cid:3)(cid:3) < (cid:4)(cid:20),> (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)-32 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:3)1 DS30001037C-page 240  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 241

PIC24F16KL402 FAMILY !"(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)#%&(cid:14)(cid:19)$(cid:9)#(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)’(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)##(cid:21)(cid:9)(cid:22)(cid:9)()(cid:23)(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)##’(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:3)> (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?0(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:29)(cid:20)?0 (cid:29)(cid:20)(cid:5)0 (cid:29)(cid:20)>0 (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)0 < < :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)>(cid:4) >(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) 0(cid:20)(cid:4)(cid:4) 0(cid:20),(cid:4) 0(cid:20)?(cid:4) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:29)(cid:4)(cid:20)(cid:3)(cid:4) (cid:29)(cid:4)(cid:20)0(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)00 (cid:4)(cid:20)(cid:5)0 (cid:4)(cid:20)(cid:24)0 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:3)0(cid:2)(cid:26)-3 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) < (cid:4)(cid:20)(cid:3)0 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)V (cid:23)V >V 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20)(cid:3)(cid:3) < (cid:4)(cid:20),> (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)-32 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:5),1 DS30001037C-page 242  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 243

PIC24F16KL402 FAMILY 20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-120A DS30001037C-page 244  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 245

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30001037C-page 246  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS30001037C-page 247

PIC24F16KL402 FAMILY 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern With 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-2140A DS30001037C-page 248  2011-2013 Microchip Technology Inc.

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DS30001037C-page 249

PIC24F16KL402 FAMILY !"(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)*(cid:17)(cid:7)(cid:8)(cid:9)+(cid:11)(cid:7)(cid:13),(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)$(cid:7)-(cid:6)(cid:9)(cid:20).(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)/0/(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)*+(cid:31)(cid:30) 1(cid:14)(cid:13)%(cid:9)(cid:24))(((cid:9)(cid:25)(cid:25)(cid:9)2(cid:27)(cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19)-(cid:13)% (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS30001037C-page 250  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: MIGRATING FROM PIC18/PIC24 TO Revision A (September 2011) PIC24F16KL402 Original data sheet for the PIC24F16KL402 family of The PIC24F16KL402 family combines traditional devices. PIC18 peripherals with a faster PIC24 core to provide a low-cost, high-performance microcontroller with Revision B (November 2011) low-power consumption. Updates DC Specifications in Tables 26-6 through 26-9 Code written for PIC18 devices can be migrated to the (all Typical and Maximum values). PIC24F16KL402 by using a C compiler that generates PIC24 machine level instructions. Assembly language Updates AC Specifications in Tables 26-7 through code will need to be rewritten using PIC24 instructions. 26-30 (SPI Timing Requirements) with the addition of The PIC24 instruction set shares similarities to the the FSCK specification. PIC18 instruction set, which should ease porting of Other minor typographic corrections throughout. assembly code. Application code will require changes to support certain PIC24 peripherals. Revision C (October 2013) Code written for PIC24 devices can be migrated to the PIC24F16KL402 without many code changes. Certain Adds +125°C Extended Temperature information. peripherals, however, will require application changes Updates several packaging drawings in Section27.0 to support modules that were traditionally available “Packaging Information”. Other minor typographic only on PIC18 devices. corrections throughout. Refer to TableB-1 for a list of peripheral modules on the PIC24F16KL402 and where they originated from. TABLE B-1: TABLE B-1: PIC24F16KL402 PERIPHERAL MODULE ORIGINATING ARCHITECTURE Peripheral Module PIC18 PIC24 ECCP/CCP X — MSSP (I2C™/SPI) X — Timer2/4 (8-bit) X — Timer3 (16-bit) X — Timer1 (16-bit) — X 10-Bit A/D Converter — X Comparator — X Comparator Voltage — X Reference UART — X HLVD — X  2011-2013 Microchip Technology Inc. DS30001037C-page 251

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 252  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY INDEX A C A/D C Compilers 10-Bit High-Speed A/D Converter.............................157 MPLAB XC Compilers..............................................188 Conversion Timing Requirements.............................224 Capture/Compare/PWM (CCP)........................................125 Module Specifications...............................................223 CCP/ECCP A/D Converter CCP I/O Pins............................................................125 Analog Input Model...................................................164 Timer Selection.........................................................125 Transfer Function......................................................165 Code Examples AC Characteristics Data EEPROM Bulk Erase.........................................57 A/D Module...............................................................223 Data EEPROM Unlock Sequence..............................53 Capacitive Loading Requirements on Erasing a Program Memory Row, Output Pins.......................................................209 Assembly Language...........................................50 Internal RC Oscillator Accuracy................................211 Erasing a Program Memory Row, C Language..........51 Internal RC Oscillator Specifications.........................211 I/O Port Write/Read (Assembly Language)..............114 Load Conditions and Requirements..........................209 I/O Port Write/Read (C Language)...........................114 Temperature and Voltage Specifications..................209 Initiating a Programming Sequence, Assembler Assembly Language...........................................52 MPASM Assembler...................................................188 Initiating a Programming Sequence, C Language......52 Loading the Write Buffers, Assembly Language........51 B Loading the Write Buffers, C Language.....................52 Block Diagrams PWRSAV Instruction Syntax....................................105 10-Bit High-Speed A/D Converter.............................158 Reading Data EEPROM Using the 16-Bit Timer1............................................................115 TBLRD Command..............................................58 Accessing Program Memory with Sequence for Clock Switching..................................102 Table Instructions...............................................45 Single-Word Erase.....................................................56 CALL Stack Frame......................................................43 Single-Word Write to Data EEPROM.........................57 Capture Mode Operation..........................................126 Ultra Low-Power Wake-up Initialization....................107 Comparator Module..................................................167 Code Protection................................................................185 Comparator Voltage Reference Module...................171 Comparator.......................................................................167 Compare Mode Operation........................................126 Comparator Voltage Reference........................................171 CPU Programmer’s Model..........................................27 Configuring...............................................................171 Data Access From Program Space Configuration Bits.............................................................175 Address Generation............................................44 Core Features.......................................................................9 Data EEPROM Addressing with TBLPAG and CPU NVM Registers....................................................55 ALU.............................................................................29 Enhanced PWM Mode..............................................127 Control Registers........................................................28 High/Low-Voltage Detect (HLVD) Module................173 Core Registers............................................................26 Individual Comparator Configurations.......................168 Programmer’s Model..................................................25 MCLR Pin Connections Example................................22 Customer Change Notification Service.............................257 MSSPx Module (I2C Master Mode)...........................137 Customer Notification Service..........................................257 MSSPx Module (I2C Mode).......................................137 Customer Support.............................................................257 MSSPx Module (SPI Mode)......................................136 D PIC24F CPU Core......................................................26 PIC24F16KL402 Family (General)..............................13 Data EEPROM Memory......................................................53 PSV Operation............................................................46 Erasing.......................................................................56 PWM Operation (Simplified).....................................126 Nonvolatile Memory Registers Recommended Minimum Connections.......................21 NVMCON............................................................53 Reset System..............................................................59 NVMKEY............................................................53 Serial Resistor...........................................................107 NVMADR(U).......................................................55 Shared I/O Port Structure.........................................111 Operations..................................................................55 Simplified UARTx......................................................149 Programming SPI Master/Slave Connection...................................136 Bulk Erase..........................................................57 Suggested Placement of Oscillator Circuit..................23 Reading Data EEPROM.....................................58 System Clock..............................................................95 Single-Word Write..............................................57 Table Register Addressing..........................................47 Data Memory Timer2.......................................................................117 Address Space...........................................................33 Timer3.......................................................................119 Memory Map...............................................................33 Timer4.......................................................................123 Near Data Space........................................................34 Watchdog Timer (WDT)............................................184 Organization...............................................................34 SFR Space.................................................................34 Software Stack...........................................................43 Space Width...............................................................33  2011-2013 Microchip Technology Inc. DS30001037C-page 253

PIC24F16KL402 FAMILY DC Characteristics Inter-Integrated Circuit. See I2C. BOR Trip Points........................................................202 Internet Address...............................................................257 Comparator...............................................................208 Interrupt Sources Comparator Voltage Reference................................208 TMR3 Overflow.........................................................119 Data EEPROM Memory............................................208 TMR4 to PR4 Match (PWM).....................................123 High/Low-Voltage Detect..........................................202 Interrupts I/O Pin Input Specifications.......................................206 Alternate Interrupt Vector Table (AIVT)......................65 I/O Pin Output Specifications....................................207 Control and Status Registers......................................68 Idle Current (IIDLE)....................................................203 Implemented Vectors..................................................67 Operating Current (IDD).............................................203 Interrupt Vector Table (IVT)........................................65 Power-Down Current (IPD)................................204, 205 Reset Sequence.........................................................65 Program Memory......................................................207 Setup Procedures.......................................................94 Temperature and Voltage Specifications..................201 Trap Vectors...............................................................67 Demo/Development Boards, Evaluation and Vector Table...............................................................66 Starter Kits................................................................190 M Development Support.......................................................187 Third-Party Tools......................................................190 Master Synchronous Serial Port (MSSP).........................135 Device Features for PIC24F16KL20X/10X I/O Pin Configuration for SPI....................................135 Devices (Summary)....................................................12 Microchip Internet Web Site..............................................257 Device Features for PIC24F16KL40X/30X MPLAB Assembler, Linker, Librarian................................188 Devices (Summary)....................................................11 MPLAB ICD 3 In-Circuit Debugger...................................189 MPLAB PM3 Device Programmer....................................189 E MPLAB REAL ICE In-Circuit Emulator System................189 Electrical Characteristics MPLAB X Integrated Development Absolute Maximum Ratings......................................199 Environment Software..............................................187 Thermal Operating Conditions..................................201 MPLAB X SIM Software Simulator...................................189 Thermal Packaging Characteristics..........................201 MPLIB Object Librarian.....................................................188 V/F Graph, Extended................................................200 MPLINK Object Linker......................................................188 V/F Graph, Industrial.................................................200 N Enhanced CCP.................................................................125 Equations Near Data Space................................................................34 A/D Conversion Clock Period...................................164 O UARTx Baud Rate with BRGH = 0............................150 UARTx Baud Rate with BRGH = 1............................150 Oscillator Configuration Errata....................................................................................7 Clock Switching........................................................101 Examples Sequence.........................................................101 Baud Rate Error Calculation (BRGH = 0).................150 Configuration Bit Values for Clock Selection..............96 CPU Clocking Scheme...............................................96 F Initial Configuration on POR.......................................96 Flash Program Memory Reference Clock Output...........................................102 Control Registers........................................................48 Oscillator, Timer3..............................................................119 Enhanced ICSP Operation..........................................48 P Programming Algorithm..............................................50 Programming Operations............................................48 Packaging RTSP Operation..........................................................48 Details.......................................................................228 Table Instructions........................................................47 Marking.....................................................................225 PICkit 3 In-Circuit Debugger/Programmer........................189 G Pinout Descriptions Getting Started Guidelines for 16-Bit MCUs.......................21 PIC24F16KL20X/10X Devices....................................18 PIC24F16KL40X/30X Devices....................................14 H Power-Saving...................................................................109 High/Low-Voltage Detect (HLVD).....................................173 Power-Saving Features....................................................105 Clock Frequency, Clock Switching...........................105 I Coincident Interrupts.................................................106 I/O Ports Instruction-Based Modes..........................................105 Analog Port Configuration.........................................112 Idle....................................................................106 Analog Selection Registers.......................................112 Sleep................................................................106 Input Change Notification..........................................114 Selective Peripheral Control.....................................109 Open-Drain Configuration.........................................112 Ultra Low-Power Wake-up (ULPWU).......................107 Parallel (PIO)............................................................111 Product Identification System...........................................259 In-Circuit Debugger...........................................................185 Program and Data Memory In-Circuit Serial Programming (ICSP)...............................185 Access Using Table Instructions.................................45 Instruction Set Program Space Visibility.............................................46 Opcode Symbols.......................................................192 Program and Data Memory Spaces Overview...................................................................193 Addressing..................................................................43 Summary...................................................................191 Interfacing...................................................................43 DS30001037C-page 254  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY Program Memory IEC4 (Interrupt Enable Control 4)...............................80 Address Space............................................................31 IEC5 (Interrupt Enable Control 5)...............................80 Data EEPROM............................................................32 IFS0 (Interrupt Flag Status 0).....................................73 Device Configuration Words.......................................32 IFS1 (Interrupt Flag Status 1).....................................74 Hard Memory Vectors.................................................32 IFS2 (Interrupt Flag Status 2).....................................75 Organization................................................................32 IFS3 (Interrupt Flag Status 3).....................................75 Program Space IFS4 (Interrupt Flag Status 4).....................................76 Memory Map...............................................................31 IFS5 (Interrupt Flag Status 5).....................................76 Program Verification.........................................................185 INTCON 2 (Interrupt Control 2)..................................72 PWM (CCP Module) INTCON1 (Interrupt Control 1)...................................71 TMR4 to PR4 Match.................................................123 INTTREG (Interrupt Control and Status)....................93 IPC0 (Interrupt Priority Control 0)...............................81 R IPC1 (Interrupt Priority Control 1)...............................82 Register Maps IPC12 (Interrupt Priority Control 12)...........................90 A/D Converter.............................................................41 IPC16 (Interrupt Priority Control 16)...........................91 Analog Select..............................................................41 IPC18 (Interrupt Priority Control 18)...........................92 CCP/ECCP.................................................................38 IPC2 (Interrupt Priority Control 2)...............................83 Comparator.................................................................41 IPC20 (Interrupt Priority Control 20)...........................92 CPU Core....................................................................35 IPC3 (Interrupt Priority Control 3)...............................84 ICN..............................................................................36 IPC4 (Interrupt Priority Control 4)...............................85 Interrupt Controller......................................................37 IPC5 (Interrupt Priority Control 5)...............................86 MSSP..........................................................................39 IPC6 (Interrupt Priority Control 6)...............................87 NVM............................................................................42 IPC7 (Interrupt Priority Control 7)...............................88 Pad Configuration.......................................................40 IPC9 (Interrupt Priority Control 9)...............................89 PMD............................................................................42 NVMCON (Flash Memory Control).............................49 PORTA........................................................................40 NVMCON (Nonvolatile Memory Control)....................54 PORTB........................................................................40 OSCCON (Oscillator Control).....................................97 System, Clock Control................................................42 OSCTUN (FRC Oscillator Tune)..............................100 Timer...........................................................................38 PADCFG1 (Pad Configuration Control)....................147 UART..........................................................................39 PSTR1CON (ECCP1 Pulse Steering Control)..........132 Ultra Low-Power Wake-up..........................................42 RCON (Reset Control)................................................60 Registers REFOCON (Reference Oscillator Control)...............103 AD1CHS (A/D Input Select)......................................162 SR (ALU STATUS)...............................................28, 69 AD1CON1 (A/D Control 1)........................................159 SSPxADD (MSSPx Slave Address/Baud AD1CON2 (A/D Control 2)........................................160 Rate Generator)................................................146 AD1CON3 (A/D Control 3)........................................161 SSPxCON1 (MSSPx Control 1, I2C Mode)..............142 AD1CSSL (A/D Input Scan Select)...........................163 SSPxCON1 (MSSPx Control 1, SPI Mode)..............141 ANCFG (Analog Input Configuration).......................163 SSPxCON2 (MSSPx Control 2, I2C Mode)..............143 ANSA (PORTA Analog Selection)............................113 SSPxCON3 (MSSPx Control 3, I2C Mode)..............145 ANSB (PORTB Analog Selection)............................113 SSPxCON3 (MSSPx Control 3, SPI Mode)..............144 CCP1CON (ECCP1 Control, Enhanced CCP)..........129 SSPxMSK (I2C Slave Address Mask)......................146 CCPTMRS0 (CCP Timer Select Control 0)..............133 SSPxSTAT (MSSPx Status, I2C Mode)....................139 CCPxCON (CCPx Control, Standard CCP)..............128 SSPxSTAT (MSSPx Status, SPI Mode)...................138 CLKDIV (Clock Divider)..............................................99 T1CON (Timer1 Control)..........................................116 CMSTAT (Comparator Status)..................................170 T2CON (Timer2 Control)..........................................118 CMxCON (Comparator x Control).............................169 T3CON (Timer3 Control)..........................................120 CORCON (CPU Control)......................................29, 70 T3GCON (Timer3 Gate Control)...............................121 CVRCON (Comparator Voltage T4CON (Timer4 Control)..........................................124 Reference Control)...........................................172 ULPWCON (ULPWU Control)..................................108 DEVID (Device ID)....................................................182 UxMODE (UARTx Mode).........................................152 DEVREV (Device Revision)......................................183 UxSTA (UARTx Status and Control)........................154 ECCP1AS (ECCP1 Auto-Shutdown Control)............130 Resets ECCP1DEL (ECCP1 Enhanced PWM Control)........131 Brown-out Reset (BOR)..............................................63 FBS (Boot Segment Configuration)..........................176 Clock Source Selection..............................................61 FGS (General Segment Configuration).....................176 Delay Times................................................................62 FICD (In-Circuit Debugger Configuration).................181 Device Times..............................................................62 FOSC (Oscillator Configuration)...............................178 RCON Flag Operation................................................61 FOSCSEL (Oscillator Selection Configuration).........177 SFR States.................................................................63 FPOR (Reset Configuration).....................................180 Revision History................................................................251 FWDT (Watchdog Timer Configuration)...................179 S HLVDCON (High/Low-Voltage Detect Control).........174 IEC0 (Interrupt Enable Control 0)...............................77 Serial Peripheral Interface. See SPI Mode. IEC1 (Interrupt Enable Control 1)...............................78 SFR Space.........................................................................34 IEC2 (Interrupt Enable Control 2)...............................79 Software Stack...................................................................43 IEC3 (Interrupt Enable Control 3)...............................79  2011-2013 Microchip Technology Inc. DS30001037C-page 255

PIC24F16KL402 FAMILY T U Timer1...............................................................................115 UART................................................................................149 Timer2...............................................................................117 Baud Rate Generator (BRG)....................................150 Timer3...............................................................................119 Break and Sync Transmit Sequence........................151 Oscillator...................................................................119 IrDA Support.............................................................151 Overflow Interrupt.....................................................119 Operation of UxCTS and UxRTS Control Pins.........151 Timer4...............................................................................123 Receiving in 8-Bit or 9-Bit Data Mode.......................151 PR4 Register.............................................................123 Transmitting in 8-Bit Data Mode...............................151 TMR4 Register..........................................................123 Transmitting in 9-Bit Data Mode...............................151 TMR4 to PR4 Match Interrupt...................................123 Unique ID..........................................................................182 Timing Diagrams W Capture/Compare/PWM (ECCP1, ECCP2)..............214 CLKO and I/O...........................................................212 Watchdog Timer (WDT)....................................................184 Example SPI Master Mode (CKE = 0)......................215 Windowed Operation................................................184 Example SPI Master Mode (CKE = 1)......................216 WWW Address.................................................................257 Example SPI Slave Mode (CKE = 0)........................217 WWW, On-Line Support.......................................................7 Example SPI Slave Mode (CKE = 1)........................218 External Clock...........................................................210 I2C Bus Data.............................................................219 I2C Bus Start/Stop Bits..............................................219 MSSPx I2C Bus Data................................................222 MSSPx I2C Bus Start/Stop Bits.................................221 Timing Requirements A/D Conversion.........................................................224 Capture/Compare/PWM (ECCP1, ECCP2)..............214 CLKO and I/O...........................................................212 Comparator...............................................................213 Comparator Voltage Reference Settling Time..........213 External Clock...........................................................210 I2C Bus Data (Slave Mode).......................................220 I2C Bus Data Requirements (Master Mode).............222 I2C Bus Start/Stop Bits (Master Mode).....................221 I2C Bus Start/Stop Bits (Slave Mode).......................219 PLL Clock Specifications..........................................211 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset..............213 SPI Mode (Master Mode, CKE = 0)..........................215 SPI Mode (Master Mode, CKE = 1)..........................216 SPI Slave Mode (CKE = 1).......................................218 Timing Requirements SPI Mode (Slave Mode, CKE = 0)...................................................................217 DS30001037C-page 256  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011-2013 Microchip Technology Inc. DS30001037C-page 257

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 258  2011-2013 Microchip Technology Inc.

PIC24F16KL402 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 F 16 KL4 02 T - I / PT - XXX Examples: a) PIC24F16KL402-I/ML: General Purpose, Microchip Trademark 16-Kbyte Program Memory, 28-Pin, Industrial Temperature, QFN Package Architecture b) PIC24F04KL101T-I/SS: General Purpose, Flash Memory Family 4-Kbyte Program Memory, 20-Pin, Industrial Temperature, SSOP Package, Tape-and-Reel Program Memory Size (Kbytes) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture 24 = 16-bit modified Harvard without DSP Flash Memory Family F = Standard voltage range Flash program memory Product Group KL4 = General purpose microcontrollers KL3 KL2 KL1 Pin Count 00 = 14-pin 01 = 20-pin 02 = 28-pin Temperature Range I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package SP = SPDIP SO = SOIC SS = SSOP ST = TSSOP ML, MQ = QFN P = PDIP Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2011-2013 Microchip Technology Inc. DS30001037C-page 259

PIC24F16KL402 FAMILY NOTES: DS30001037C-page 260  2011-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-620-9 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2011-2013 Microchip Technology Inc. DS30001037C-page 261

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC24F16KL402-I/MQ PIC24F08KL302-I/MQ PIC24F08KL402-I/MQ PIC24F04KL100-I/P PIC24F04KL100-I/ST PIC24F04KL100T-I/ST PIC24F04KL101-I/MQ PIC24F04KL101-I/P PIC24F04KL101-I/SO PIC24F04KL101-I/SS PIC24F04KL101T-I/MQ PIC24F04KL101T-I/SO PIC24F04KL101T-I/SS PIC24F08KL200-I/P PIC24F08KL200-I/ST PIC24F08KL200T-I/ST PIC24F08KL201-I/MQ PIC24F08KL201-I/P PIC24F08KL201-I/SO PIC24F08KL201-I/SS PIC24F08KL201T-I/MQ PIC24F08KL201T-I/SO PIC24F08KL201T-I/SS PIC24F08KL301-I/MQ PIC24F08KL301-I/P PIC24F08KL301-I/SO PIC24F08KL301-I/SS PIC24F08KL301T-I/MQ PIC24F08KL301T-I/SO PIC24F08KL301T-I/SS PIC24F08KL302-I/ML PIC24F08KL302-I/SO PIC24F08KL302-I/SP PIC24F08KL302-I/SS PIC24F08KL302T-I/ML PIC24F08KL302T-I/SO PIC24F08KL302T-I/SS PIC24F08KL401-I/MQ PIC24F08KL401-I/P PIC24F08KL401-I/SO PIC24F08KL401-I/SS PIC24F08KL401T-I/MQ PIC24F08KL401T-I/SO PIC24F08KL401T-I/SS PIC24F08KL402-I/ML PIC24F08KL402-I/SO PIC24F08KL402-I/SP PIC24F08KL402-I/SS PIC24F08KL402T-I/ML PIC24F08KL402T-I/SO PIC24F08KL402T-I/SS PIC24F16KL401-I/MQ PIC24F16KL401-I/P PIC24F16KL401-I/SO PIC24F16KL401-I/SS PIC24F16KL401T-I/MQ PIC24F16KL401T-I/SO PIC24F16KL401T-I/SS PIC24F16KL402-I/ML PIC24F16KL402-I/SO PIC24F16KL402-I/SP PIC24F16KL402-I/SS PIC24F16KL402T-I/ML PIC24F16KL402T-I/SO PIC24F16KL402T-I/SS PIC24F08KL302T-I/MQ PIC24F08KL402T-I/MQ PIC24F16KL402T-I/MQ PIC24F04KL101-E/P PIC24F16KL401-E/SO PIC24F08KL201-E/P PIC24F08KL301-E/SS PIC24F08KL402-E/SS PIC24F08KL401-E/SS PIC24F08KL302-E/SO PIC24F08KL201-E/MQ PIC24F08KL401-E/MQ PIC24F08KL301-E/SO PIC24F08KL201-E/SO PIC24F16KL402-E/SS PIC24F16KL401-E/P PIC24F08KL200-E/ST PIC24F16KL401-E/MQ PIC24F16KL401-E/SS PIC24F16KL402-E/ML PIC24F04KL101-E/MQ PIC24F08KL402-E/MQ PIC24F08KL302-E/ML PIC24F16KL402-E/SP PIC24F08KL201-E/SS PIC24F08KL402-E/ML PIC24F08KL401-E/P PIC24F08KL302-E/SS PIC24F08KL302-E/SP PIC24F08KL401-E/SO PIC24F04KL100-E/P PIC24F16KL402-E/MQ PIC24F08KL301-E/MQ PIC24F08KL402-E/SO PIC24F04KL100-E/ST