PIC24F16KA102 Family Data Sheet 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology  2008-2011 Microchip Technology Inc. DS39927C

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT, devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC, intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-690-7 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39927C-page 2  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology Power Management Modes: Analog Features: • Run – CPU, Flash, SRAM and Peripherals On • 10-Bit, up to 9-Channel Analog-to-Digital Converter: • Doze – CPU Clock Runs Slower than Peripherals - 500ksps conversion rate • Idle – CPU Off, Flash, SRAM and Peripherals On - Conversion available during Sleep and Idle • Sleep – CPU, Flash and Peripherals Off and • Dual Analog Comparators with Programmable Input/ SRAM On Output Configuration • Deep Sleep – CPU, Flash, SRAM and • Charge Time Measurement Unit (CTMU): Most Peripherals Off: - Used for capacitance sensing - Run mode currents down to 8 A typical - Time measurement, down to 1 ns resolution - Idle mode currents down to 2 A typical - Delay/pulse generation, down to 1 ns resolution - Deep Sleep mode currents down to 20 nA typical - RTCC 490 nA, 32 kHz, 1.8V Special Microcontroller Features: - Watchdog Timer 350 nA, 1.8V typical • Operating Voltage Range of 1.8V to 3.6V • High-Current Sink/Source (18mA/18mA) on All I/O Pins High-Performance CPU: • Flash Program Memory: • Modified Harvard Architecture - Erase/write cycles: 10,000 minimum • Up to 16 MIPS Operation @ 32MHz - 40-years’ data retention minimum • 8MHz Internal Oscillator with 4x PLL Option and • Data EEPROM: Multiple Divide Options - Erase/write cycles: 100,000 minimum • 17-Bit by 17-Bit Single-Cycle Hardware Multiplier - 40-years’ data retention minimum • 32-Bit by 16-Bit Hardware Divider • Fail-Safe Clock Monitor • 16-Bit x 16-Bit Working Register Array • System Frequency Range Declaration bits: • C Compiler Optimized Instruction Set Architecture - Declaring the frequency range optimizes the current consumption. Peripheral Features: • Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation • Hardware Real-Time Clock and Calendar (RTCC): • In-Circuit Serial Programming™ (ICSP™) and - Provides clock, calendar and alarm functions In-Circuit Debug (ICD) via two Pins - Can run in Deep Sleep Mode • Programmable High/Low-Voltage Detect (HLVD) • Programmable Cyclic Redundancy Check (CRC) • Brown-out Reset (BOR): • Serial Communication modules: - Standard BOR with three programmable trip points; - SPI, I2C™ and two UART modules can be disabled in Sleep • Three 16-Bit Timers/Counters with Programmable • Extreme Low-Power DSBOR for Deep Sleep, Prescaler LPBOR for all other modes • 16-Bit Capture Inputs • 16-Bit Compare/PWM Output • Configurable Open-Drain Outputs on Digital I/O Pins • Up to Three External Interrupt Sources s PDIeCv2ic4eF Pins ProgramMemory(bytes) SRAM(bytes) Data EEPROM(bytes) Timers 16-Bit CaptureInput OutputCompare/PWM UART/®IrDA SPI 2IC™ 10-Bit A/D(ch) omparator CTMU (ch) RTCC C 08KA101 20 8K 1.5K 512 3 1 1 2 1 1 9 2 9 Y 16KA101 20 16K 1.5K 512 3 1 1 2 1 1 9 2 9 Y 08KA102 28 8K 1.5K 512 3 1 1 2 1 1 9 2 9 Y 16KA102 28 16K 1.5K 512 3 1 1 2 1 1 9 2 9 Y  2008-2011 Microchip Technology Inc. DS39927C-page 3

PIC24F16KA102 FAMILY Pin Diagrams 20-Pin PDIP, SSOP, SOIC(2) MCLR/VPP/RA5 1 20 VDD PGC2/AN0/VREF+/CN2/RA0 2 19 VSS PGD2/AN1/VREF-/CN3/RA1 3 01 18 REFO/SS1/T2CK/T3CK/CN11/RB15 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 4 X 17 AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 5 A 16 AN11/SDO1/CTPLS/CN13/RB13 K U1RX/CN6/RB2 6 X 15 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 7 X 14 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 8 24 13 U1RTS/U1BCLK/SDA1/CN21/RB9 PGD3/SOSCI/U2RTS/U2BCLK/CN1/RB4 9 C 12 U1CTS/SCL1/CN22/RB8 PGC3/SOSCO/T1CK/U2CTS/CN0/RA4 10 PI 11 U1TX/INT0/CN23/RB7 28-Pin SPDIP, SSOP, SOIC(2) MCLR/VPP/RA5 1 28 VDD AN0/VREF+/CN2/RA0 2 27 VSS AN1/VREF-/CN3/RA1 3 26 REFO/SS1/T2CK/T3CK/CN11/RB15 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 4 02 25 AN10/CVREF/RTCC/OCFA/C1OUT/INT1/CN12/RB14 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 5 X 24 AN11/SDO1/CTPLS/CN13/RB13 AN4/C1INB/C2IND/U1RX/CN6/RB2 6 KA 23 AN12/HLVDIN/CTED2/CN14/RB12 AN5/C1INA/C2INC/CN7/RB3 7 X 22 PGC2/SCK1/CN15/RB11 VSS 8 FX 21 PGD2/SDI1/PMD2/CN16/RB10 OSCI/CLKI/CN30/RA2 9 4 20 OC1/C2OUT/INT2/CTED1/CN8/RA6 OSCO/CLKO/CN29/RA3 10 C2 19 IC1/CN9/RA7 SOSCI/U2RTS/U2BCLK/CN1/RB4 11 PI 18 U1RTS/U1BCLK/SDA1/CN21/RB9 SOSCO/T1CK/U2CTS/CN0/RA4 12 17 U1CTS/SCL1/CN22/RB8 VDD 13 16 U1TX/INT0/CN23/RB7 PGD3/SDA1(1)/CN27/RB5 14 15 PGC3/SCL1(1)/CN24/RB6 Note 1: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set. 2: All device pins have a maximum voltage of 3.6V and are not 5V tolerant. DS39927C-page 4  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY Pin Diagrams (Continued) 20-Pin QFN(1,2) A1A0 RR N3/N2/ CC -/EF+/EF5 R RA VVR 1/0//P NNP AAV 2/2/R/ PGDPGCMCLVDDVSS 2019181716 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 1 15 REFO/SS1/T2CK/T3CK/CN11/RB15 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 2 14 AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 U1RX/CN6/RB2 3PIC24FXXKA10213 AN11/SDO1/CTPLS/ CN13/RB13 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 4 12 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 5 11 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 6 7 8 910 44789 BABBB RRRRR K/0/3/2/1/ LN222 CCNNN U2RTS/CN1/U2BO/T1CK/U2CTS/U1TX/INT0/CU1CTS/SCL1/CU1BCLK/SDA1/C SCI/OSC RTS/ SO3/S U1 3/C DG GP P Note 1: The bottom pad of the QFN package should be connected to VSS. 2: All device pins have a maximum voltage of 3.6V and are not 5V tolerant.  2008-2011 Microchip Technology Inc. DS39927C-page 5

PIC24F16KA102 FAMILY Pin Diagrams (Continued) 28-Pin QFN(2,3) 4 1 B R 2/ 1 N C 1/ T N K/CN11/RB15CFA/C1OUT/I AN1/V-/CN3/RA1REFAN0/V+/CN2/RA0REFMCLR/V/RA5PPVDDVssREFO/SS1/T2CK/T3CAN10/CV/RTCC/OREF 28272625242322 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 1 21 AN11/SDO1/CTPLS/CN13/RB13 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 2 20 AN12/HLVDIN/CTED2/CN14/RB12 AN4/C1INB/C2IND/U1RX/CN6/RB2 3 19 PGC2/SCK1/CN15/RB11 AN5/C1INA/C2INC/CN7/RB3 4 PIC24FXXKA102 18 PGD2/SDI1/PMD2/CN16/RB10 VSS 5 17 OC1/C2OUT/INT2/CTED1/CN8/RA6 OSCI/CLKI/CN30/RA2 6 16 IC1/CN9/RA7 OSCO/CLKO/CN29/RA3 7 15 U1RTS/U1BCLK/SDA1/CN21/RB9 8 9 1011121314 44D5678 BADBBBB RRVRRRR 1/0/ 7/4/3/2/ NN 2222 CC NNNN U2RTS/U2BCLK/O/T1CK/U2CTS/ (1)PGD3/SDA1/C(1)PGC3/SCL1/CU1TX/INT0/CU1CTS/SCL1/C CI/SC SO OS S Note 1: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set. 2: The bottom pad of the QFN package should be connected to VSS. 3: All device pins have a maximum voltage of 3.6V and are not 5V tolerant. DS39927C-page 6  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................17 3.0 CPU ...........................................................................................................................................................................................23 4.0 Memory Organization.................................................................................................................................................................29 5.0 Flash Program Memory..............................................................................................................................................................45 6.0 Data EEPROM Memory.............................................................................................................................................................51 7.0 Resets........................................................................................................................................................................................57 8.0 Interrupt Controller.....................................................................................................................................................................63 9.0 Oscillator Configuration..............................................................................................................................................................91 10.0 Power-Saving Features............................................................................................................................................................101 11.0 I/O Ports...................................................................................................................................................................................113 12.0 Timer1 .....................................................................................................................................................................................115 13.0 Timer2/3...................................................................................................................................................................................117 14.0 Input Capture............................................................................................................................................................................123 15.0 Output Compare.......................................................................................................................................................................125 16.0 Serial Peripheral Interface (SPI)...............................................................................................................................................131 17.0 Inter-Integrated Circuit (I2C™).................................................................................................................................................139 18.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................147 19.0 Real-Time Clock and Calendar (RTCC) ..................................................................................................................................155 20.0 Programmable Cyclic Redundancy Check (CRC) Generator..................................................................................................167 21.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................171 22.0 10-Bit High-Speed A/D Converter............................................................................................................................................173 23.0 Comparator Module..................................................................................................................................................................183 24.0 Comparator Voltage Reference................................................................................................................................................187 25.0 Charge Time Measurement Unit (CTMU)................................................................................................................................189 26.0 Special Features......................................................................................................................................................................193 27.0 Development Support...............................................................................................................................................................203 28.0 Instruction Set Summary..........................................................................................................................................................207 29.0 Electrical Characteristics..........................................................................................................................................................215 30.0 Packaging Information..............................................................................................................................................................251 Appendix A: Revision History.............................................................................................................................................................269 Index..................................................................................................................................................................................................271 The Microchip Web Site.....................................................................................................................................................................275 Customer Change Notification Service..............................................................................................................................................275 Customer Support..............................................................................................................................................................................275 Reader Response..............................................................................................................................................................................276 Product Identification System............................................................................................................................................................277  2008-2011 Microchip Technology Inc. DS39927C-page 7

PIC24F16KA102 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39927C-page 8  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24F16KA102 family This document contains device-specific information for incorporate a range of features that can significantly the following devices: reduce power consumption during operation. Key • PIC24F08KA101 items include: • PIC24F16KA101 • On-the-Fly Clock Switching: The device clock • PIC24F08KA102 can be changed under software control to the • PIC24F16KA102 Timer1 source or the internal, low-power RC The PIC24F16KA102 family introduces a new line of oscillator during operation, allowing users to extreme low-power Microchip devices: a 16-bit micro- incorporate power-saving ideas into their software controller family with a broad peripheral feature set and designs. enhanced computational performance. It also offers a • Doze Mode Operation: When timing-sensitive new migration option for those high-performance appli- applications, such as serial communications, cations, which may be outgrowing their 8-bit platforms, require the uninterrupted operation of peripherals, but do not require the numerical processing power of a the CPU clock speed can be selectively reduced, digital signal processor. allowing incremental power savings without missing a beat. 1.1 Core Features • Instruction-Based Power-Saving Modes: There 1.1.1 16-BIT ARCHITECTURE are three instruction-based power-saving modes: - Idle Mode: The core is shut down while leaving Central to all PIC24F devices is the 16-bit modified the peripherals active. Harvard architecture, first introduced with Microchip’s - Sleep Mode: The core and peripherals that dsPIC® digital signal controllers. The PIC24F CPU core require the system clock are shut down, leaving offers a wide range of enhancements, such as: the peripherals that use their own clock, or the • 16-bit data and 24-bit address paths with the clock from other devices, active. ability to move information between data and - Deep Sleep Mode: The core, peripherals (except memory spaces RTCC and DSWDT), Flash and SRAM are shut • Linear addressing of up to 12Mbytes (program down. space) and 64Kbytes (data) • A 16-element working register array with built-in 1.1.3 OSCILLATOR OPTIONS AND software stack support FEATURES • A 17 x 17 hardware multiplier with support for The PIC24F16KA102 family offers five different integer math oscillator options, allowing users a range of choices in • Hardware support for 32-bit by 16-bit division developing application hardware. These include: • An instruction set that supports multiple • Two Crystal modes using crystals or ceramic addressing modes and is optimized for high-level resonators. languages, such as C • Two External Clock modes offering the option of a • Operational performance up to 16 MIPS divide-by-2 clock output. • Two Fast Internal Oscillators (FRCs): One with a nominal 8 MHz output and the other with a nominal 500 kHz output. These outputs can also be divided under software control to provide clock speed as low as 31 kHz or 2 kHz. • A Phase Locked Loop (PLL) frequency multiplier, available to the External Oscillator modes and the 8 MHz FRC oscillator, which allows clock speeds of up to 32 MHz. • A separate Internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications.  2008-2011 Microchip Technology Inc. DS39927C-page 9

PIC24F16KA102 FAMILY The internal oscillator block also provides a stable 1.3 Details on Individual Family reference source for the Fail-Safe Clock Monitor Members (FSCM). This option constantly monitors the main clock source against a reference signal provided by the Devices in the PIC24F16KA102 family are available in internal oscillator and enables the controller to switch to 20-pin and 28-pin packages. The general block the internal oscillator, allowing for continued low-speed diagram for all devices is displayed in Figure1-1. operation or a safe application shutdown. The devices are different from each other in two ways: 1.1.4 EASY MIGRATION 1. Flash program memory (8 Kbytes for PIC24F08KA devices, 16 Kbytes for PIC24F16KA Regardless of the memory size, all the devices share devices). the same rich set of peripherals, allowing for a smooth 2. Available I/O pins and ports (18 pins on two migration path as applications grow and evolve. ports for 20-pin devices and 24 pins on two ports The consistent pinout scheme used throughout the for 28-pin devices). entire family also helps in migrating to the next larger 3. Alternate SCLx and SDAx pins are available device. This is true when moving between devices with only in 28-pin devices and not in 20-pin devices. the same pin count, or even jumping from 20-pin to 28-pin devices. All other features for devices in this family are identical; these are summarized in Table1-1. The PIC24F family is pin compatible with devices in the dsPIC33 family, and shares some compatibility with the A list of the pin features available on the pinout schema for PIC18 and dsPIC30. This extends PIC24F16KA102 family devices, sorted by function, is the ability of applications to grow from the relatively provided in Table1-2. simple, to the powerful and complex. Note: Table1-1 provides the pin location of individual peripheral features and not how 1.2 Other Special Features they are multiplexed on the same pin. This information is provided in the pinout • Communications: The PIC24F16KA102 family diagrams on pages 4, 5 and 6 of the data incorporates a range of serial communication sheet. Multiplexed features are sorted by peripherals to handle a range of application the priority given to a feature, with the requirements. There is an I2C™ module that highest priority peripheral being listed supports both the Master and Slave modes of first. operation. It also comprises UARTs with built-in IrDA® encoders/decoders and an SPI module. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speed. The 16-deep result buffer can be used either in Sleep to reduce power, or in Active mode to improve throughput. • Charge Time Measurement Unit (CTMU) Interface: The PIC24F16KA102 family includes the new CTMU interface module, which can be used for capacitive touch sensing, proximity sensing and also for precision time measurement and pulse generation. DS39927C-page 10  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24F16KA102 FAMILY 1 1 2 2 0 0 0 0 1 1 1 1 A A A A K K K K Features 08 16 08 16 F F F F 4 4 4 4 2 2 2 2 C C C C PI PI PI PI Operating Frequency DC – 32 MHz Program Memory (bytes) 8K 16K 8K 16K Program Memory (instructions) 2816 5632 2816 5632 Data Memory (bytes) 1536 Data EEPROM Memory (bytes) 512 Interrupt Sources (soft vectors/NMI traps) 30 (26/4) I/O Ports PORTA<6:0> PORTA<7:0> PORTB<15:12, 9:7, 4, 2:0> PORTB<15:0> Total I/O Pins 18 24 Timers: Total Number (16-bit) 3 32-Bit (from paired 16-bit timers) 1 Input Capture Channels 1 Output Compare/PWM Channels 1 Input Change Notification Interrupt 17 23 Serial Communications: UART 2 SPI (3-wire/4-wire) 1 I2C™ 1 10-Bit Analog-to-Digital Module (input channels) 9 Analog Comparators 2 Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 20-Pin PDIP/SSOP/SOIC/QFN 28-Pin SPDIP/SSOP/SOIC/QFN  2008-2011 Microchip Technology Inc. DS39927C-page 11

PIC24F16KA102 FAMILY FIGURE 1-1: PIC24F16KA102 FAMILY GENERAL BLOCK DIAGRAM Interrupt Data Bus Controller 16 8 16 16 PSV and Table Data Latch Data Access Control Block PCH PCL DataRAM 23 SPtraocgkram CRouenpteeart ALdadtrcehss PORTA(1) Control Control Logic Logic RA<0:7> 16 23 16 Address Latch Read AGU Write AGU Program Memory PORTB(1) Data EEPROM RB<0:15> Data Latch Address Bus EA MUX 16 a 24 Dat 16 16 al Inst Latch Liter Inst Register Instruction Decode and Control Divide Control Signals Support 16 x 16 17x17 W Reg Array OSCO/CLKO Timing Power-up Multiplier OSCI/CLKI Generation Timer Oscillator FRC/LPRC Start-up Timer Oscillators Power-on 16-Bit ALU Reset Watchdog 16 Timer DSWDT Precision Band Gap BOR Reference VDDV,SS MCLR 10-Bit HLVD RTCC Timer1 Timer2/3 CTMU Comparators A/D REFO IC1 OC1/PWM CN1-22(1) SPI1 I2C1 UART1/2 Note 1: All pins or features are not implemented on all device pinout configurations. See Table1-2 for I/O port pin descriptions. DS39927C-page 12  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS Pin Number Input Function 20-Pin 28-Pin I/O Description 20-Pin 28-Pin Buffer PDIP/SSOP/ SPDIP/ QFN QFN SOIC SSOP/SOIC AN0 2 19 2 27 I ANA A/D Analog Inputs AN1 3 20 3 28 I ANA AN2 4 1 4 1 I ANA AN3 5 2 5 2 I ANA AN4 7 4 6 3 I ANA AN5 8 5 7 4 I ANA AN10 17 14 25 22 I ANA AN11 16 13 24 21 I ANA AN12 15 12 23 20 I ANA U1BCLK 13 10 18 15 O — UART1 IrDA® Baud Clock U2BCLK 9 6 11 8 O — UART2 IrDA Baud Clock C1INA 8 5 7 4 I ANA Comparator 1 Input A (Positive Input) C1INB 7 4 6 3 I ANA Comparator 1 Input B (Negative Input Option 1) C1INC 5 2 5 2 I ANA Comparator Input C (Negative Input Option 2) C1IND 4 1 4 1 I ANA Comparator Input D (Negative Input Option 3) C1OUT 17 14 25 22 O — Comparator 1 Output C2INA 5 2 5 2 I ANA Comparator 2 Input A (Positive Input) C2INB 4 1 4 1 I ANA Comparator 2 Input B (Negative Input Option 1) C2INC 8 5 7 4 I ANA Comparator 2 Input C (Negative Input Option 2) C2IND 7 4 6 3 I ANA Comparator 2 Input D (Negative Input Option 3) C2OUT 14 11 20 17 O — Comparator 2 Output CLKI 7 4 9 6 I ANA Main Clock Input Connection CLKO 8 5 10 7 O — System Clock Output Legend: ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.  2008-2011 Microchip Technology Inc. DS39927C-page 13

PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function 20-Pin 28-Pin I/O Description 20-Pin 28-Pin Buffer PDIP/SSOP/ SPDIP/ QFN QFN SOIC SSOP/SOIC CN0 10 7 12 9 I ST Interrupt-on-Change Inputs CN1 9 6 11 8 I ST CN2 2 19 2 27 I ST CN3 3 20 3 28 I ST CN4 4 1 4 1 I ST CN5 5 2 5 2 I ST CN6 6 3 6 3 I ST CN7 — — 7 4 I ST CN8 14 11 20 17 I ST CN9 — — 19 16 I ST CN11 18 15 26 23 I ST CN12 17 14 25 22 I ST CN13 16 13 24 21 I ST CN14 15 12 23 20 I ST CN15 — — 22 19 I ST CN16 — — 21 18 I ST CN21 13 10 18 15 I ST CN22 12 9 17 14 I ST CN23 11 8 16 13 I ST CN24 — — 15 12 I ST CN27 — — 14 11 I ST CN29 8 5 10 7 I ST CN30 7 4 9 6 I ST CVREF 17 14 25 22 O ANA Comparator Voltage Reference Output CTED1 14 11 20 17 I ST CTMU Trigger Edge Input 1 CTED2 15 12 23 20 I ST CTMU Trigger Edge Input 2 CTPLS 16 13 24 21 O — CTMU Pulse Output IC1 14 11 19 16 I ST Input Capture 1 Input INT0 11 8 16 13 I ST External Interrupt Inputs INT1 17 14 25 22 I ST INT2 14 11 20 17 I ST HLVDIN 15 12 23 20 I ANA HLVD Voltage Input MCLR 1 18 1 26 I ST Master Clear (device Reset) Input OC1 14 11 20 17 O — Output Compare/PWM Outputs OCFA 17 14 25 22 I — Output Compare Fault A OSCI 7 4 9 6 I ANA Main Oscillator Input Connection OSCO 8 5 10 7 O ANA Main Oscillator Output Connection Legend: ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared. DS39927C-page 14  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function 20-Pin 28-Pin I/O Description 20-Pin 28-Pin Buffer PDIP/SSOP/ SPDIP/ QFN QFN SOIC SSOP/SOIC PGC1 5 2 5 2 I/O ST In-Circuit Debugger and ICSP™ Programming Clock PGD1 4 1 4 1 I/O ST In-Circuit Debugger and ICSP Programming Data PGC2 2 19 22 19 I/O ST In-Circuit Debugger and ICSP Programming Clock PGD2 3 20 21 18 I/O ST In-Circuit Debugger and ICSP Programming Data PGC3 10 7 15 12 I/O ST In-Circuit Debugger and ICSP Programming Clock PGD3 9 6 14 11 I/O ST In-Circuit Debugger and ICSP Programming Data RA0 2 19 2 27 I/O ST PORTA Digital I/O RA1 3 20 3 28 I/O ST RA2 7 4 9 6 I/O ST RA3 8 5 10 7 I/O ST RA4 10 7 12 9 I/O ST RA5 1 18 1 26 I/O ST RA6 14 11 20 17 I/O ST RA7 — — 19 16 I/O ST RB0 4 1 4 1 I/O ST PORTB Digital I/O RB1 5 2 5 2 I/O ST RB2 6 3 6 3 I/O ST RB3 — — 7 4 I/O ST RB4 9 6 11 8 I/O ST RB5 — — 14 11 I/O ST RB6 — — 15 12 I/O ST RB7 11 8 16 13 I/O ST RB8 12 9 17 14 I/O ST RB9 13 10 18 15 I/O ST RB10 — — 21 18 I/O ST RB11 — — 22 19 I/O ST RB12 15 12 23 20 I/O ST RB13 16 13 24 21 I/O ST RB14 17 14 25 22 I/O ST RB15 18 15 26 23 I/O ST REFO 18 15 26 23 O — Reference Clock Output RTCC 17 14 25 22 O — Real-Time Clock Alarm Output SCK1 15 12 22 19 I/O ST SPI1 Serial Clock Input/Output SCL1 12 9 17, 15(1) 14, 12 (1) I/O I2C I2C1 Synchronous Serial Clock Input/Output SDA1 13 10 18, 14(1) 15, 11(1) I/O I2C I2C1 Data Input/Output SDI1 17 14 21 18 I ST SPI1 Serial Data Input SDO1 16 13 24 21 O — SPI1 Serial Data Output SOSCI 9 6 11 8 I ANA Secondary Oscillator Input SOSCO 10 7 12 9 O ANA Secondary Oscillator Output SS1 18 15 26 23 I/O ST Slave Select Input/Frame Select Output (SPI1) Legend: ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.  2008-2011 Microchip Technology Inc. DS39927C-page 15

PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Input Function 20-Pin 28-Pin I/O Description 20-Pin 28-Pin Buffer PDIP/SSOP/ SPDIP/ QFN QFN SOIC SSOP/SOIC T1CK 10 7 12 9 I ST Timer1 Clock T2CK 18 15 26 23 I ST Timer2 Clock T3CK 18 15 26 23 I ST Timer3 Clock U1CTS 12 9 17 14 I ST UART1 Clear to Send Input U1RTS 13 10 18 15 O — UART1 Request to Send Output U1RX 6 3 6 3 I ST UART1 Receive U1TX 11 8 16 13 O — UART1 Transmit Output VDD 20 17 13, 28 10, 25 P — Positive Supply for Peripheral Digital Logic and I/O Pins VPP 1 18 1 26 P — Programming Mode Entry Voltage VREF- 3 20 3 28 I ANA A/D and Comparator Reference Voltage (low) Input VREF+ 2 19 2 27 I ANA A/D and Comparator Reference Voltage (high) Input VSS 19 16 8, 27 5, 24 P — Ground Reference for Logic and I/O Pin Legend: ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared. DS39927C-page 16  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH 16-BIT MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC24F16KA102 family family R1 DD SS of 16-bit microcontrollers requires attention to a V V R2 minimal set of device pin connections before MCLR proceeding with development. VCAP (1) The following pins must always be connected: C1 (3) C7 PIC24FXXKXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • VCAP pins (see Section2.4 “Voltage Regulator Pin (VCAP)”) These pins must also be connected if they are being Key (all values are recommendations): used in the end application: C1 through C6: 0.1 F, 20V ceramic • PGECx/PGEDx pins used for In-Circuit Serial C7: 10 F, 16V tantalum or ceramic Programming™ (ICSP™) and debugging purposes R1: 10 kΩ (see Section2.5 “ICSP Pins”) R2: 100Ω to 470Ω • OSCI and OSCO pins when an external oscillator Note 1: See Section2.4 “Voltage Regulator Pin source is used (VCAP)” for explanation of VCAP pin (see Section2.6 “External Oscillator Pins”) connections. Additionally, the following pins may be required: 2: The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. • VREF+/VREF- pins are used when external voltage Other devices may have more or less pairs; reference for analog modules is implemented adjust the number of decoupling capacitors Note: The AVDD and AVSS pins must always be appropriately. connected, regardless of whether any of 3: Some PIC24F K parts do not have a the analog modules are being used. regulator. The minimum mandatory connections are shown in Figure2-1.  2008-2011 Microchip Technology Inc. DS39927C-page 17

PIC24F16KA102 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: Device Reset, and Device Programming The use of decoupling capacitors on every pair of and Debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 F (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented, depending on the should be a low-ESR device, with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1F in parallel with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC24FXXKXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1 10k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10k. Ensure that the On boards with power traces running longer than MCLR pin VIH and VIL specifications are met. sixinches in length, it is suggested to use a tank capac- 2: R2470 will limit any current flowing into itor for integrated circuits, including microcontrollers, to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS39927C-page 18  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 2.4 Voltage Regulator Pin (VCAP) Refer to Section29.0 “Electrical Characteristics” for information on VDD and VDDCORE. Note: This section applies only to PIC24F K devices with an on-chip voltage regulator. FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR Some of the PIC24F K devices have an internal voltage regulator. These devices have the voltage regulator SUGGESTED VCAP output brought out on the VCAP pin. On the PIC24F K 10 devices with regulators, a low-ESR (<5Ω) capacitor is required on the VCAP pin to stabilize the voltage 1 regulator output. The VCAP pin must not be connected to VDD and must use a capacitor of 10 µF connected to ) ground. The type can be ceramic or tantalum. Suitable R ( 0.1 examples of capacitors are shown in Table2-1. S E Capacitors with equivalent specifications can be used. 0.01 Designers may use Figure2-3 to evaluate ESR equivalence of candidate devices. 0.001 The placement of this capacitor should be close to VCAP. 0.01 0.1 1 10 100 1000 10,000 It is recommended that the trace length not exceed Frequency (MHz) 0.25inch (6mm). Refer to Section29.0 “Electrical Note: Typical data measurement at 25°C, 0V DC bias. Characteristics” for additional information. TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Nominal Make Part # Base Tolerance Rated Voltage Temp. Range Capacitance TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC  2008-2011 Microchip Technology Inc. DS39927C-page 19

PIC24F16KA102 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITORS CAPACITANCE CHARACTERISTICS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic %) 10 e ( 0 capacitors very attractive in many types of applications. ng-10 16V Capacitor ha-20 Ceramic capacitors are suitable for use with the inter- C-30 nal voltage regulator of this microcontroller. However, ance --5400 10V Capacitor some care is needed in selecting the capacitor to cit-60 ensure that it maintains sufficient capacitance over the Capa--8700 6.3V Capacitor intended operating range of the application. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) Typical low-cost, 10 F ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial toler- When selecting a ceramic capacitor to be used with the ance specifications for these types of capacitors are internal voltage regulator, it is suggested to select a often specified as ±10% to ±20% (X5R and X7R), or high-voltage rating, so that the operating voltage is a -20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt- that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at also vary based on additional factors, such as the 16V for the 3.3V or 2.5V core voltage. Suggested applied DC bias voltage and the temperature. The total capacitors are shown in Table2-1. in-circuit tolerance is, therefore, much wider than the initial tolerance specification. 2.5 ICSP Pins The X5R and X7R capacitors typically exhibit satisfac- The PGC and PGD pins are used for In-Circuit Serial tory temperature stability (ex: ±15% over a wide Programming™ (ICSP™) and debugging purposes. It temperature range, but consult the manufacturer's data is recommended to keep the trace length between the sheets for exact specifications). However, Y5V capaci- ICSP connector and the ICSP pins on the device as tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to specifications of +22%/-82%. Due to the extreme experience an ESD event, a series resistor is recom- temperature tolerance, a 10 F nominal rated Y5V type mended, with the value in the range of a few tens of capacitor may not deliver enough total capacitance to ohms, not to exceed 100Ω. meet minimum internal voltage regulator stability and Pull-up resistors, series diodes and capacitors on the transient response requirements. Therefore, Y5V PGC and PGD pins are not recommended as they will capacitors are not recommended for use with the interfere with the programmer/debugger communica- internal regulator if the application must operate over a tions to the device. If such discrete components are an wide temperature range. application requirement, they should be removed from In addition to temperature tolerance, the effective the circuit during programming and debugging. Alter- capacitance of large value ceramic capacitors can vary natively, refer to the AC/DC characteristics and timing substantially, based on the amount of DC voltage requirements information in the respective device applied to the capacitor. This effect can be very signifi- Flash programming specification for information on cant, but is often overlooked or is not always capacitive loading limits, and pin input voltage high documented. (VIH) and input low (VIL) requirements. A typical DC bias voltage vs. capacitance graph for For device emulation, ensure that the “Communication X7R type capacitors is shown in Figure2-4. Channel Select” (i.e., PGCx/PGDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section27.0 “Development Support”. DS39927C-page 20  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR Many microcontrollers have options for at least two CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts: Section9.0 “Oscillator Configuration” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSC1 Oscillator of the board. C1 ` OSC2 Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power T1OSO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board T1OS I Timer1 Oscillator where the crystal is placed. Crystal ` Layout suggestions are shown in Figure2-5. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With T1 Oscillator: C1 T1 Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins and other Bottom Layer signals, in close proximity to the oscillator, are benign Copper Pour (i.e., free of high frequencies, short rise and fall times, (tied to ground) and other similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.7 Unused I/Os DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low.  2008-2011 Microchip Technology Inc. DS39927C-page 21

PIC24F16KA102 FAMILY NOTES: DS39927C-page 22  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 3.0 CPU For most instructions, the core is capable of executing a data (or program data) memory read, a working Note: This data sheet summarizes the features register (data) read, a data memory write and a of this group of PIC24F devices. It is not program (instruction) memory read per instruction intended to be a comprehensive refer- cycle. As a result, three parameter instructions can be ence source. For more information on the supported, allowing trinary operations (that is, CPU, refer to the “PIC24F Family A+B = C) to be executed in a single cycle. Reference Manual”, Section 2. “CPU” A high-speed, 17-bit by 17-bit multiplier has been (DS39703). included to significantly enhance the core arithmetic capability and throughput. The multiplier supports The PIC24F CPU has a 16-bit (data) modified Harvard Signed, Unsigned and Mixed mode, 16-bit by 16-bit or architecture with an enhanced instruction set and a 8-bit by 8-bit integer multiplication. All multiply 24-bit instruction word with a variable length opcode instructions execute in a single cycle. field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program The 16-bit ALU has been enhanced with integer divide memory space. A single-cycle instruction prefetch assist hardware that supports an iterative non-restoring mechanism is used to help maintain throughput and divide algorithm. It operates in conjunction with the provides predictable execution. All instructions execute REPEAT instruction looping mechanism and a selection in a single cycle, with the exception of instructions that of iterative divide instructions to support 32-bit (or change the program flow, the double-word move 16-bit), divided by 16-bit integer signed and unsigned (MOV.D) instruction and the table instructions. division. All divide operations require 19 cycles to Overhead-free program loop constructs are supported complete but are interruptible at any cycle boundary. using the REPEAT instructions, which are interruptible The PIC24F has a vectored exception scheme with up at any point. to eight sources of non-maskable traps and up to PIC24F devices have sixteen, 16-bit working registers 118interrupt sources. Each interrupt source can be in the programmer’s model. Each of the working assigned to one of seven priority levels. registers can act as a data, address or address offset A block diagram of the CPU is illustrated in Figure3-1. register. The 16th working register (W15) operates as a Software Stack Pointer (SSP) for interrupts and calls. 3.1 Programmer’s Model The upper 32Kbytes of the data space memory map can optionally be mapped into program space at any Figure3-2 displays the programmer’s model for the 16K word boundary of either program memory or data PIC24F. All registers in the programmer’s model are EEPROM memory defined by the 8-bit Program Space memory mapped and can be manipulated directly by Visibility Page Address (PSVPAG) register. The instructions. program to data space mapping feature lets any Table3-1 provides a description of each register. All instruction access program space as if it were data registers associated with the programmer’s model are space. memory mapped. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.  2008-2011 Microchip Technology Inc. DS39927C-page 23

PIC24F16KA102 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCH PCL Data RAM 16 23 Program Counter Stack Loop Address Control Control Latch Logic Logic 23 16 RAGU Address Latch WAGU Program Memory Data EEPROM Address Bus EA MUX Data Latch ROM Latch 24 16 16 Instruction a Decode and Dat Control Instruction Reg al er Lit Control Signals to Various Blocks Hardware Multiplier 16 x 16 W Register Array Divide Support 16 16-Bit ALU 16 To Peripheral Modules TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register DS39927C-page 24  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 0 W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address W8 Registers W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 Stack Pointer Limit SPLIM 0 Value Register 22 0 PC 0 Program Counter 7 0 Table Memory Page TBLPAG Address Register 7 0 Program Space Visibility PSVPAG Page Address Register 15 0 Repeat Loop Counter RCOUNT Register 15 SRH SRL 0 ———————DC IPL RA N OV Z C ALU STATUS Register (SR) 2 1 0 15 0 ————————————IPL3PSV—— CPU Control Register (CORCON) Registers or bits shadowed for PUSH.S and POP.S instructions.  2008-2011 Microchip Technology Inc. DS39927C-page 25

PIC24F16KA102 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HSC — — — — — — — DC bit 15 bit 8 R/W-0, HSC(1) R/W-0, HSC(1) R/W-0, HSC(1) R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU Interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation, which effects the Z bit, has set it at some time in the past 0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit (MSb) of the result occurred Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. 2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39927C-page 26  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(1) PSV — — bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space is visible in data space 0 = Program space is not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: User interrupts are disabled when IPL3 = 1. 3.3 Arithmetic Logic Unit (ALU) The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a The PIC24F ALU is 16 bits wide and is capable of dedicated hardware multiplier and support hardware addition, subtraction, bit shifts and logic operations. division for 16-bit divisor. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, 3.3.1 MULTIPLIER the ALU may affect the values of the Carry (C), Zero The ALU contains a high-speed, 17-bit x 17-bit (Z), Negative (N), Overflow (OV) and Digit Carry (DC) multiplier. It supports unsigned, signed or mixed sign Status bits in the SR register. The C and DC Status bits operation in several multiplication modes: operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. • 16-bit x 16-bit signed • 16-bit x 16-bit unsigned The ALU can perform 8-bit or 16-bit operations, • 16-bit signed x 5-bit (literal) unsigned depending on the mode of the instruction that is used. Data for the ALU operation can come from the W • 16-bit unsigned x 16-bit unsigned register array, or data memory, depending on the • 16-bit unsigned x 5-bit (literal) unsigned addressing mode of the instruction. Likewise, output • 16-bit unsigned x 16-bit signed data from the ALU can be written to the W register array • 8-bit unsigned x 8-bit unsigned or a data memory location.  2008-2011 Microchip Technology Inc. DS39927C-page 27

PIC24F16KA102 FAMILY 3.3.2 DIVIDER 3.3.3 MULTI-BIT SHIFT SUPPORT The divide block supports 32-bit/16-bit and 16-bit/16-bit The PIC24F ALU supports both single bit and signed and unsigned integer divide operations with the single-cycle, multi-bit arithmetic and logic shifts. following data sizes: Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right 1. 32-bit signed/16-bit signed divide shift, or up to a 15-bit left shift, in a single cycle. All 2. 32-bit unsigned/16-bit unsigned divide multi-bit shift instructions only support Register Direct 3. 16-bit signed/16-bit signed divide Addressing for both the operand source and result 4. 16-bit unsigned/16-bit unsigned divide destination. The quotient for all divide instructions ends up in W0 A full summary of instructions that use the shift and the remainder in W1. Sixteen-bit signed and operation is provided below in Table3-2. unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION Instruction Description ASR Arithmetic shift right source register by one or more bits. SL Shift left source register by one or more bits. LSR Logical shift right source register by one or more bits. DS39927C-page 28  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 4.0 MEMORY ORGANIZATION The user access to the program memory space is restricted to the lower half of the address range As with Harvard architecture devices, the PIC24F (000000h to 7FFFFFh). The exception is the use of microcontrollers feature separate program and data TBLRD/TBLWT operations, which use TBLPAG<7> to memory space and busing. This architecture also permit access to the Configuration bits and Device ID allows the direct access of program memory from the sections of the configuration memory space. data space during code execution. Memory maps for the PIC24F16KA102 family of devices are displayed in Figure4-1. 4.1 Program Address Space The program address memory space of the PIC24F devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from a table operation or data space remapping, as described in Section4.3 “Interfacing Program and Data Memory Spaces”. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES PIC24F08KA10X PIC24F16KA10X GOTO Instruction GOTO Instruction 000000h 000002h Reset Address Reset Address 000004h Interrupt Vector Table Interrupt Vector Table 0000FEh Reserved Reserved 000100h Alternate Vector Table Alternate Vector Table 00000011F04Ehh 000200h Flash Program Memory ce (2816 instructions) a p User Flash S y Program Memory 0015FEh or (5632 instructions) m e M er s U Unimplemented Read ‘0’ 002BFE Unimplemented Read ‘0’ 7FFE00h Data EEPROM Data EEPROM 7FFFFFh 800000h e Reserved Reserved c a p S y or m F7FFFEh Me Device Config Registers Device Config Registers F80000h n F80010h o F80012h ati ur g nfi Reserved Reserved o C FEFFFEh DEVID (2) DEVID (2) FF0000h FFFFFFh Note: Memory areas are not displayed to scale.  2008-2011 Microchip Technology Inc. DS39927C-page 29

PIC24F16KA102 FAMILY 4.1.1 PROGRAM MEMORY 4.1.3 DATA EEPROM ORGANIZATION In the PIC24F16KA102 family, the data EEPROM is The program memory space is organized in mapped to the top of the user program memory space, word-addressable blocks. Although it is treated as starting at address, 7FFE00, and expanding up to 24bits wide, it is more appropriate to think of each address, 7FFFFF. address of the program memory as a lower and upper The data EEPROM is organized as 16-bit wide memory word, with the upper byte of the upper word being and 256 words deep. This memory is accessed using unimplemented. The lower word always has an even table read and write operations similar to the user code address, while the upper word has an odd address memory. (Figure4-2). 4.1.4 DEVICE CONFIGURATION WORDS Program memory addresses are always word-aligned on the lower word, and addresses are incremented or Table4-1 provides the addresses of the device Config- decremented by two during code execution. This uration Words for the PIC24F16KA102 family. Their arrangement also provides compatibility with data location in the memory map is displayed in Figure4-1. memory space addressing and makes it possible to Refer to Section26.1 “Configuration Bits” for more access data in the program memory space. information on device Configuration Words. 4.1.2 HARD MEMORY VECTORS TABLE 4-1: DEVICE CONFIGURATION All PIC24F devices reserve the addresses between WORDS FOR PIC24F16KA102 00000h and 000200h for hard coded program FAMILY DEVICES execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the Configuration Word Configuration Word PC on device Reset to the actual start of code. A GOTO Addresses instruction is programmed by the user at 000000h with FBS F80000 the actual address for the start of code at 000002h. FGS F80004 PIC24F devices also have two Interrupt Vector Tables, located from 000004h to 0000FFh, and FOSCSEL F80006 000104h to 0001FFh. These vector tables allow each FOSC F80008 of the many device interrupt sources to be handled FWDT F8000A by separate ISRs. Section8.1 “Interrupt Vector FPOR F8000C (IVT) Table” discusses the Interrupt Vector Tables in more detail. FICD F8000E FDS F80010 FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 000001h 00000000 000000h 000003h 00000000 000002h 000005h 00000000 000004h 000007h 00000000 000006h Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS39927C-page 30  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 4.2 Data Address Space 4.2.1 DATA SPACE WIDTH The PIC24F core has a separate, 16-bit wide data The data memory space is organized in memory space, addressable as a single linear range. byte-addressable, 16-bit wide blocks. Data is aligned in The data space is accessed using two Address data memory and registers as 16-bit words, but all the Generation Units (AGUs), one each for read and write data space EAs resolve to bytes. The Least Significant operations. The data space memory map is displayed Bytes (LSBs) of each word have even addresses, while in Figure4-3. the Most Significant Bytes (MSBs) have odd addresses. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64Kbytes or 32Kwords. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility (PSV) area (see Section4.3.3 “Reading Data From Program Memory Using Program Space Visibility”). PIC24F16KA102 family devices implement a total of 768words of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES MSB LSB Address MSB LSB Address 0001h SFR Space 0000h SFR 07FFh 07FEh Space 0801h 0800h Near Data Space Data RAM Implemented Data RAM 0DFFh 0DFEh 1FFF 1FFEh Unimplemented Read as ‘0’ 7FFFh 7FFFh 8001h 8000h Program Space Visibility Area FFFFh FFFEh Note: Data memory areas are not shown to scale.  2008-2011 Microchip Technology Inc. DS39927C-page 31

PIC24F16KA102 FAMILY 4.2.2 DATA MEMORY ORGANIZATION Although most instructions are capable of operating on AND ALIGNMENT word or byte data sizes, it should be noted that some instructions operate only on words. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the 4.2.3 NEAR DATA SPACE PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all The 8-Kbyte area between 0000h and 1FFFh is EA calculations are internally scaled to step through referred to as the Near Data Space. Locations in this space are directly addressable via a 13-bit absolute word-aligned memory. For example, the core recog- nizes that Post-Modified Register Indirect Addressing address field within all memory direct instructions. The remainder of the data space is addressable indirectly. mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Data byte reads will read the complete word, which Addressing (MDA) with a 16-bit address field. For contains the byte, using the LSB of any EA to PIC24F16KA102 family devices, the entire determine which byte to select. The selected byte is implemented data memory lies in Near Data Space placed onto the LSB of the data path. That is, the data (NDS). memory and the registers are organized as two parallel, byte-wide entities with shared (word) address 4.2.4 SFR SPACE decode, but separate write lines. Data byte writes only The first 2Kbytes of the Near Data Space, from 0000h write to the corresponding side of the array or register, to 07FFh, are primarily occupied with Special Function which matches the byte address. Registers (SFRs). These are used by the PIC24F core All word accesses must be aligned to an even address. and peripheral modules for controlling the operation of Misaligned word data fetches are not supported, so the device. care must be taken when mixing byte and word SFRs are distributed among the modules that they operations, or translating from 8-bit MCU code. If a mis- control and are generally grouped together by that aligned read or write is attempted, an address error module. Much of the SFR space contains unused trap will be generated. If the error occurred on a read, addresses; these are read as ‘0’. The SFR space, the instruction underway is completed; if it occurred on where the SFRs are actually implemented, is provided a write, the instruction will be executed, but the write in Table4-2. Each implemented area indicates a will not occur. In either case, a trap is then executed, 32-byte region where at least one address is allowing the system and/or user to examine the implemented as an SFR. A complete listing of machine state prior to execution of the address Fault. implemented SFRs, including their addresses, is All byte loads into any W register are loaded into the provided in Table4-3 throughTable4-23. LSB; the MSB is not modified. A Sign-Extend instruction (SE) is provided to allow the users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0 000h Core ICN Interrupts — 100h Timers Capture — Compare — — — 200h I2C™ UART SPI — — I/O 300h A/D/CMTU — — — — — — 400h — — — — — — — — 500h — — — — — — — — 600h — RTC/Comp CRC — — 700h — — System/DS/HLVD NVM/PMD — — — — Legend: — = No implemented SFRs in this block. DS39927C-page 32  2008-2011 Microchip Technology Inc.

 TABLE 4-3: CPU CORE REGISTERS MAP 2 0 0 File All 8 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Name Resets 0 1 1 WREG0 0000 Working Register 0 0000 M ic WREG1 0002 Working Register 1 0000 roc WREG2 0004 Working Register 2 0000 h ip WREG3 0006 Working Register 3 0000 T e WREG4 0008 Working Register 4 0000 c hn WREG5 000A Working Register 5 0000 o lo WREG6 000C Working Register 6 0000 g y In WREG7 000E Working Register 7 0000 c. WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Register 11 0000 WREG12 0018 Working Register 12 0000 WREG13 001A Working Register 13 0000 WREG14 001C Working Register 14 0000 P WREG15 001E Working Register 15 0800 I SPLIM 0020 Stack Pointer Limit Value Register xxxx C PCL 002E Program Counter Low Byte Register 0000 2 PCH 0030 — — — — — — — — Program Counter Register High Byte 0000 4 TBLPAG 0032 — — — — — — — — Table Memory Page Address Register 0000 F PSVPAG 0034 — — — — — — — — Program Space Visibility Page Address Register 0000 1 RCOUNT 0036 REPEAT Loop Counter Register xxxx 6 SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000 K CORCON 0044 — — — — — — — — — — — — IPL3 PSV — — 0000 DISICNT 0052 — — Disable Interrupts Counter Register xxxx A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 0 2 F DS A 3 9 9 M 2 7 C -pa IL g e 3 Y 3

D P S TABLE 4-4: ICN REGISTER MAP 3 9 I 9 File All C 2 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 Name Resets C -pag CNEN1 0060 CN15IE(1) CN14IE CN13IE CN12IE CN11IE(1) — CN9IE CN8IE CN7IE(1) CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 24 e CNEN2 0062 — CN30IE CN29IE — CN27IE(1) — — CN24IE(1) CN23IE CN22IE CN21IE — — — — CN16IE(1) 0000 3 F 4 CNPU1 0068 CN15PUE(1) CN14PUE CN13PUE CN12PUE CN11PUE(1) — CN9PUE CN8PUE CN7PUE(1) CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 1 CNPU2 006A — CN30PUE CN29PUE — CN27PUE(1) — — CN24PUE(1) CN23PUE CN22PUE CN21PUE — — — — CN16PUE(1) 0000 6 CNPD1 0070 CN15PDE(1) CN14PDE CN13PDE CN12PDE CN11PDE(1) — CN9PDE CN8PDE CN7PDE(1) CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE 0000 K CNPD2 0072 — CN30PDE CN29PDE — CN27PDE(1) — — CN24PDE(1) CN23PDE CN22PDE CN21PDE — — — — CN16PDE(1) 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A Note1: These bits are not implemented in 20-pin devices. 1 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP 0 2 File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets F INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 A INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 M IFS0 0084 NVMIF — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF — — — T1IF OC1IF IC1IF INT0IF 0000 IFS1 0086 U2TXIF U2RXIF INT2IF — — — — — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 I L IFS3 008A — RTCIF — — — — — — — — — — — — — — 0000 Y IFS4 008C — — CTMUIF — — — — HLVDIF — — — — CRCIF U2ERIF U1ERIF — 0000 IEC0 0094 NVMIE — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE — — — T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 U2TXIE U2RXIE INT2IE — — — — — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 IEC3 009A — RTCIE — — — — — — — — — — — — — — 0000 IEC4 009C — — CTMUIE — — — — HLVDIE — — — — CRCIE U2ERIE U1ERIE — 0000 IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 IPC1 00A6 — T2IP2 T2IP1 T2IP0 — — — — — — — — — — — — 4444  2 IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444 00 IPC3 00AA — NVMIP2 NVMIP1 NVMIP0 — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 4044 8 -2 IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 4444 0 11 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 M IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — — — — 4440 ic ro IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 0400 c h ip IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440 Te IPC18 00C8 — — — — — — — — — — — — — HLVDIP2 HLVDIP1 HLVDIP0 0004 c hn IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040 o lo INTTREG 00E0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-6: TIMER REGISTER MAP 2 0 08-2 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 1 1 TMR1 0100 Timer1 Register 0000 M ic PR1 0102 Timer1 Period Register FFFF roc T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 h ip TMR2 0106 Timer2 Register 0000 T e TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) 0000 c h n TMR3 010A Timer3 Register 0000 o log PR2 010C Timer2 Period Register FFFF y In PR3 010E Timer3 Period Register FFFF c . T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-7: INPUT CAPTURE REGISTER MAP File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets P IC1BUF 0140 InputCapture1 Register FFFF I C IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 4 TABLE 4-8: OUTPUT COMPARE REGISTER MAP F File All 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 6 OC1RS 0180 Output Compare 1 Secondary Register FFFF K OC1R 0182 Output Compare 1 Register FFFF A OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 1 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 2 F DS A 3 9 9 M 2 7 C -pa IL g e 3 Y 5

D TABLE 4-9: I2C™ REGISTER MAP P S 3 9927 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC C -p I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 2 age I2C1TRN 0202 — — — — — — — — I2C1Transmit Register 00FF 4 36 I2C1BRG 0204 — — — — — — — I2C1 Baud Rate Generator Register 0000 F I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 1 6 I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 K I2C1ADD 020A — — — — — — I2C1 Address Register 0000 I2C1MSK 020C — — — — — — AMSK9 AMSK8 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in h.5adecimal. 1 0 TABLE 4-10: UART REGISTER MAP 2 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Name Resets F U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 A U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 M U1TXREG 0224 — — — — — — — UART1 Transmit Register 0000 I U1RXREG 0226 — — — — — — — UART1 Receive Register 0000 L U1BRG 0228 Baud Rate Generator Prescaler Register 0000 Y U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 U2TXREG 0234 — — — — — — — UART2 Transmit Register 0000 U2RXREG 0236 — — — — — — — UART2 Receive Register 0000 U2BRG 0238 Baud Rate Generator Prescaler 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  2 TABLE 4-11: SPI REGISTER MAP 0 0 8 File All -20 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 1 1 M SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000 icro SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 ch SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 ip T SPI1BUF 0248 SPI1 Transmit/Receive Buffer 0000 e ch Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n o lo g y In c .

 2 TABLE 4-12: PORTA REGISTER MAP 0 08-2 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5(1) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 1 1 M TRISA 02C0 — — — — — — — — TRISA7(4) TRISA6 — TRISA4 TRISA3(5,6) TRISA2(5) TRISA1 TRISA0 00DF ic PORTA 02C2 — — — — — — — — RA7(4) RA6 RA5 RA4(3) RA3(5,6) RA2(5) RA1(2) RA0(2) xxxx ro ch LATA 02C4 — — — — — — — — LATA7(4) LATA6 — LATA4 LATA3(5,6) LATA2(5) LATA1 LATA0 xxxx ip T ODCA 02C6 — — — — — — — — ODA7(4) ODA6 — ODA4 ODA3(5,6) ODA2(5) ODA1 ODA0 0000 e ch Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. no Note1: This bit is available only when MCLRE=0. lo 2: A read of RA1 and RA0 results in ‘0’ when debug is active on the PGC2/PGD2 pin. g y 3: A read of RA4 results in ‘0’ when debug is active on the PGC3/PGD3 pin. In 4: These bits are not implemented in 20-pin devices. c . 5: These bits are available only when the primary oscillator is disabled (POSCMD<1:0> = 00); otherwise read as ‘0’. 6: These bits are available only when the primary oscillator is disabled or EC mode is selected (POSCMD<1:0> = 00 or 11) and CLKO is disabled (OSCIOFNC = 0); otherwise read as ‘0’. TABLE 4-13: PORTB REGISTER MAP File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11(3) TRISB10(3) TRISB9 TRISB8 TRISB7 TRISB6(3) TRISB5(3) TRISB4 TRISB3(3) TRISB2 TRISB1 TRISB0 FFFF P PORTB 02CA RB15 RB14 RB13 RB12 RB11(3) RB10(3) RB9 RB8 RB7 RB6(3) RB5(3) RB4(2) RB3(3) RB2 RB1(1) RB0(1) xxxx I LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11(3) LATB10(3) LATB9 LATB8 LATB7 LATB6(3) LATB5(3) LATB4 LATB3(3) LATB2 LATB1 LATB0 xxxx C ODCB 02CE ODB15 ODB14 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 Note1: A read of RB1 and RB0 results in ‘0’ when debug is active on the PGEC1/PGED1 pins. F 2: A read of RB4 results in ‘0’ when debug is active on the PGEC3/PGED3 pins. 3: PORTB bits, 11, 10, 6, 5 and 3, are not implemented in 20-pin devices. 1 6 TABLE 4-14: PAD CONFIGURATION REGISTER MAP K File A Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Name 1 PADCFG1 02FC — — — — — — — — — — — SMBUSDEL OC1TRIS RTSECSEL1 RTSECSEL0 — 0000 0 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 F DS A 3 9 9 M 2 7 C -pa IL g e 3 Y 7

D TABLE 4-15: A/D REGISTER MAP P S 3 9927 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets IC C -p ADC1BUF0 0300 A/D Data Buffer 0 xxxx 2 age ADC1BUF1 0302 A/D Data Buffer 1 xxxx 4 3 ADC1BUF2 0304 A/D Data Buffer 2 xxxx F 8 ADC1BUF3 0306 A/D Data Buffer 3 xxxx 1 ADC1BUF4 0308 A/D Data Buffer 4 xxxx 6 ADC1BUF5 030A A/D Data Buffer 5 xxxx K ADC1BUF6 030C A/D Data Buffer 6 xxxx ADC1BUF7 030E A/D Data Buffer 7 xxxx A ADC1BUF8 0310 A/D Data Buffer 8 xxxx 1 ADC1BUF9 0312 A/D Data Buffer 9 xxxx 0 ADC1BUFA 0314 A/D Data Buffer 10 xxxx 2 ADC1BUFB 0316 A/D Data Buffer 11 xxxx ADC1BUFC 0318 A/D Data Buffer 12 xxxx F ADC1BUFD 031A A/D Data Buffer 13 xxxx A ADC1BUFE 031C A/D Data Buffer 14 xxxx ADC1BUFF 031E A/D Data Buffer 15 xxxx M AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000 I AD1CON2 0322 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — — BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 L AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 — — ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 Y AD1CHS 0328 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 AD1PCFG 032C — — — PCFG12 PCFG11 PCFG10 — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 AD1CSSL 0330 — — — CSSL12 CSSL11 CSSL10 — — — — CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-16: CTMU REGISTER MAP  File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 2 Name Resets 0 08 CTMUCON 033C CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 -2 0 CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000 1 1 M Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-17: REAL-TIME CLOCK AND CALENDAR REGISTER MAP 2 0 08-2 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 1 1 M ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<15:0> xxxx ic ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 ro c RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<15:0> xxxx h ip T RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 ec Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. h n o lo TABLE 4-18: DUAL COMPARATOR REGISTER MAP g y In File All c Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 . Name Resets CMSTAT 0630 CMSIDL — — — — — C2EVT C1EVT — — — — — — C2OUT C1OUT 0000 CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 CM1CON 0634 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 CM2CON 0636 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P TABLE 4-19: CRC REGISTER MAP I C File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 Name Resets 4 CRCCON 0640 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 0040 F CRCXOR 0642 X<15:1> — 0000 1 CRCDAT 0644 CRC Data Input Register 0000 6 CRCWDAT 0646 CRC Result Register 0000 K Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A 1 0 2 F DS A 3 9 9 M 2 7 C -pa IL g e 3 Y 9

D TABLE 4-20: CLOCK CONTROL REGISTER MAP P S 3 9927 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC C -p RCON 0740 TRAPR IOPUWR SBOREN — — DPSLP — PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1) 2 age OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK — LOCK — CF — SOSCEN OSWEN (Note 2) 4 4 F 0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 3140 1 OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 6 REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000 K HLVDCON 0756 HLVDEN — HLSIDL — — — — — VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A Note1: RCON register Reset values are dependent on the type of Reset. 1 2: OSCCON register Reset values are dependent on configuration fuses and by type of Reset. 0 2 TABLE 4-21: DEEP SLEEP REGISTER MAP F All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets(1) A DSCON 0758 DSEN — — — — — — — — — — — — — DSBOR RELEASE 0000 M DSWAKE 075A — — — — — — — DSINT0 DSFLT — — DSWDT DSRTCC DSMCLR — DSPOR 0000 I DSGPR0 075C Deep Sleep General Purpose Register 0 0000 L DSGPR1 075E Deep Sleep General Purpose Register 1 0000 Y Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note1: The Deep Sleep registers are only reset on a VDD POR event. TABLE 4-22: NVM REGISTER MAP All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets  2 NVMCON 0760 WR WREN WRERR PGMONLY — — — — — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 00 NVMKEY 0766 — — — — — — — — NVMKEY7 NVMKEY6 NVMKEY5 NVMKEY4 NVMKEY3 NVMKEY2 NVMKEY1 NVMKEY0 0000 8 -2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 1 Note1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. 1 M ic roc TABLE 4-23: PMD REGISTER MAP h ip T File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets e ch PMD1 0770 — — T3MD T2MD T1MD — — — I2C1MD U2MD U1MD — SPI1MD — — ADC1MD 0000 n olo PMD2 0772 — — — — — — — IC1MD — — — — — — — OC1MD 0000 gy PMD3 0774 — — — — — CMPMD RTCCMD — CRCPMD — — — — — — — 0000 Inc PMD4 0776 — — — — — — — — — — — EEMD REFOMD CTMUMD HLVDMD — 0000 . Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24F16KA102 FAMILY 4.2.5 SOFTWARE STACK 4.3 Interfacing Program and Data Memory Spaces In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software The PIC24F architecture uses a 24-bit wide program Stack Pointer. The pointer always points to the first space and 16-bit wide data space. The architecture is available free word and grows from lower to higher also a modified Harvard scheme, meaning that data addresses. It pre-decrements for stack pops and can also be present in the program space. To use this post-increments for stack pushes, as depicted in data successfully, it must be accessed in a way that Figure4-4. preserves the alignment of information in both spaces. For a PC push during any CALL instruction, the MSB of Apart from the normal execution, the PIC24F the PC is Zero-Extended before the push, ensuring that architecture provides two methods by which the the MSB is always clear. program space can be accessed during operation: Note: A PC push during exception processing • Using table instructions to access individual bytes will concatenate the SRL register to the or words anywhere in the program space MSB of the PC prior to the push. • Remapping a portion of the program space into The Stack Pointer Limit Value (SPLIM) register, the data space, PSV associated with the Stack Pointer, sets an upper Table instructions allow an application to read or write address boundary for the stack. SPLIM is uninitialized small areas of the program memory. This makes the at Reset. As is the case for the Stack Pointer, method ideal for accessing data tables that need to be SPLIM<0> is forced to ‘0’ as all stack operations must updated from time to time. It also allows access to all be word-aligned. Whenever an EA is generated using bytes of the program word. The remapping method W15 as a source or destination pointer, the resulting allows an application to access a large block of data on address is compared with the value in SPLIM. If the a read-only basis, which is ideal for look ups from a contents of the Stack Pointer (W15) and the SPLIM large table of static data. It can only access the least register are equal, and a push operation is performed, significant word (lsw) of the program word. a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. 4.3.1 ADDRESSING PROGRAM SPACE Thus, for example, if it is desirable to cause a stack Since the address ranges for the data and program error trap when the stack grows beyond address, 0DF6 spaces are 16 and 24 bits, respectively, a method is in RAM, initialize the SPLIM with the value, 0DF4. needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the Similarly, a Stack Pointer underflow (stack error) trap is interface method to be used. generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from For table operations, the 8-bit Table Memory Page interfering with the Special Function Register (SFR) Address register (TBLPAG) is used to define a 32Kword space. region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space Note: A write to the SPLIM register should not address. In this format, the Most Significant bit (MSb) of be immediately followed by an indirect TBLPAG is used to determine if the operation occurs in read operation using W15. the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). FIGURE 4-4: CALL STACK FRAME For remapping operations, the 8-bit Program Space Visibility Page Address register (PSVPAG) is used to 0000h 15 0 define a 16Kword page in the program space. When the MSb of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program s ardss space address. Unlike the table operations, this limits ows Tower Addre PC<15:0> W15 (before CALL) rSeemea pTpaibnlge o4p-2e4ra tiaonnds sFtriigcutlrye to4 -t5h e tuos ekrn mowem hooryw a rtehae. Grgh 000000000 PC<22:16> program EA is created for table operations and ck Hi <Free Word> W15 (after CALL) remapping accesses from the data EA. Here, P<23:0> a St refers to a program space word, whereas D<15:0> POP : [--W15] refers to a data space word. PUSH: [W15++]  2008-2011 Microchip Technology Inc. DS39927C-page 41

PIC24F16KA102 FAMILY TABLE 4-24: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 PSVPAG<7:0>(2) Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. 2: PSVPAG can have only two values (‘00’ to access program memory and FF to access data EEPROM) on the PIC24F16KA102 family. FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select 1 EA 0 Program Space Visibility(1) 0 PSVPAG (Remapping) 8 Bits 15 Bits 23 Bits User/Configuration Byte Select Space Select Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS39927C-page 42  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM In Byte mode, either the upper or lower byte of MEMORY AND DATA EEPROM the lower program word is mapped to the lower MEMORY USING TABLE byte of a data address. The upper byte is INSTRUCTIONS selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. The TBLRDL and TBLWTL instructions offer a direct 2. TBLRDH (Table Read High): In Word mode, it method of reading or writing the lower word of any maps the entire upper word of a program address address within the program memory without going (P<23:16>) to a data address. Note that through data space. It also offers a direct method of D<15:8>, the ‘phantom’ byte, will always be ‘0’. reading or writing a word of any address within data EEPROM memory. The TBLRDH and TBLWTH instruc- In Byte mode, it maps the upper or lower byte of tions are the only method to read or write the upper 8 bits the program word to D<7:0> of the data of a program space word as data. address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is Note: The TBLRDH and TBLWTH instructions are not selected (byte select = 1). used while accessing data EEPROM memory. In a similar fashion, two table instructions, TBLWTH The PC is incremented by 2 for each successive and TBLWTL, are used to write individual bytes or 24-bit program word. This allows program memory words to a program space address. The details of addresses to directly map to data space addresses. their operation are explained in Section5.0 “Flash Program memory can thus be regarded as two 16-bit, Program Memory”. word-wide address spaces, residing side by side, each For all table operations, the area of program memory with the same address range. TBLRDL and TBLWTL space to be accessed is determined by the Table access the space which contains the least significant Memory Page Address register (TBLPAG). TBLPAG data word, and TBLRDH and TBLWTH access the space covers the entire program memory space of the which contains the upper data byte. device, including user and configuration spaces. When Two table instructions are provided to move byte or TBLPAG<7> = 0, the table page is located in the user word-sized (16-bit) data to and from program space. memory space. When TBLPAG<7> = 1, the page is Both function as either byte or word operations. located in configuration space. 1. TBLRDL (Table Read Low): In Word mode, it Note: Only table read operations will execute in the maps the lower word of the program space configuration memory space, and only then, in location (P<15:0>) to a data address (D<15:0>). implemented areas, such as the Device ID. Table write operations are not allowed. FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space Data EA<15:0> TBLPAG 00 23 16 8 0 00000000 23 15 0 000000h 00000000 00000000 002BFEh 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are provided; write operations are also valid in the 800000h user memory area.  2008-2011 Microchip Technology Inc. DS39927C-page 43

PIC24F16KA102 FAMILY 4.3.3 READING DATA FROM PROGRAM Although each data space address, 8000h and higher, MEMORY USING PROGRAM SPACE maps directly into a corresponding program memory VISIBILITY address (see Figure4-7), only the lower 16bits of the 24-bit program word are used to contain the data. The The upper 32Kbytes of data space may optionally be upper 8 bits of any program space locations used as mapped into an 8K word page (in PIC24F08KA1XX data should be programmed with ‘1111 1111’ or ‘0000 devices) and a 16Kword page (in PIC24F16KA1XX 0000’ to force a NOP. This prevents possible issues devices) of the program space. This provides should the area of code ever be accidentally executed. transparent access of stored constant data from the data space without the need to use special instructions Note: PSV access is temporarily disabled during (i.e., TBLRDL/H). table reads/writes. Program space access through the data space occurs For operations that use PSV and are executed outside if the MSb of the data space, EA, is ‘1’, and PSV is a REPEAT loop, the MOV and MOV.D instructions will enabled by setting the PSV bit in the CPU Control require one instruction cycle in addition to the specified (CORCON<2>) register. The location of the program execution time. All other instructions will require two memory space to be mapped into the data space is instruction cycles in addition to the specified execution determined by the Program Space Visibility Page time. Address register (PSVPAG). This 8-bit register defines For operations that use PSV, which are executed inside any one of 256possible pages of 16Kwords in pro- a REPEAT loop, there will be some instances that gram space. In effect, PSVPAG functions as the upper require two instruction cycles in addition to the 8 bits of the program memory address, with the 15bits specified execution time of the instruction: of the EA functioning as the lower bits. • Execution in the first iteration By incrementing the PC by 2 for each program memory • Execution in the last iteration word, the lower 15 bits of data space addresses directly • Execution prior to exiting the loop due to an map to the lower 15 bits in the corresponding program interrupt space addresses. • Execution upon re-entering the loop after an Data reads from this area add an additional cycle to the interrupt is serviced instruction being executed, since two program memory Any other iteration of the REPEAT loop will allow the fetches are required. instruction accessing data, using PSV, to execute in a single cycle. FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space Data Space PSVPAG 23 15 0 00 000000h 0000h Data EA<14:0> 002BFEh The data in the page designated by PSVPAG is mapped into the upper half of the data memory 8000h space.... PSV Area ...while the lower 15 bits of the EA specify an exact address within the PSV FFFFh area. This corresponds exactly to the same lower 15 bits of the actual program space address. 800000h DS39927C-page 44  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 5.0 FLASH PROGRAM MEMORY Real-Time Self-Programming (RTSP) is accomplished using TBLRD (table read) and TBLWT (table write) Note: This data sheet summarizes the features of instructions. With RTSP, the user may write program this group of PIC24F devices. It is not memory data in blocks of 32instructions (96 bytes) at a intended to be a comprehensive reference time, and erase program memory in blocks of 32, 64 and source. For more information on Flash Pro- 128 instructions (96,192 and384bytes) at a time. gramming, refer to the “PIC24F Family The NVMOP<1:0> (NVMCON<1:0>) bits decide the Reference Manual”, Section 4. “Program erase block size. Memory” (DS39715). 5.1 Table Instructions and Flash The PIC24FJ64GA family of devices contains internal Flash program memory for storing and executing appli- Programming cation code. The memory is readable, writable and Regardless of the method used, Flash memory erasable when operating with VDD over 1.8V. programming is done with the table read and write Flash memory can be programmed in three ways: instructions. These allow direct read and write access to • In-Circuit Serial Programming™ (ICSP™) the program memory space from the data memory while • Run-Time Self-Programming (RTSP) the device is in normal operating mode. The 24-bit target • Enhanced In-Circuit Serial Programming address in the program memory is formed using the (Enhanced ICSP) TBLPAG<7:0> bits and the Effective Address (EA) from a W register, specified in the table instruction, as ICSP allows a PIC24F16KA102 device to be serially depicted in Figure5-1. programmed while in the end application circuit. This is simply done with two lines for the programming clock The TBLRDL and the TBLWTL instructions are used to and programming data (which are named PGCx and read or write to bits<15:0> of program memory. PGDx, respectively), and three other lines for power TBLRDL and TBLWTL can access program memory in (VDD), ground (VSS) and Master Clear/Program Mode both Word and Byte modes. Entry Voltage (MCLR/VPP). This allows customers to The TBLRDH and TBLWTH instructions are used to read manufacture boards with unprogrammed devices and or write to bits<23:16> of program memory. TBLRDH then program the microcontroller just before shipping and TBLWTH can also access program memory in Word the product. This also allows the most recent firmware or Byte mode. or custom firmware to be programmed. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program 0 Program Counter 0 Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2008-2011 Microchip Technology Inc. DS39927C-page 45

PIC24F16KA102 FAMILY 5.2 RTSP Operation 5.3 Enhanced In-Circuit Serial Programming The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows Enhanced ICSP uses an on-board bootloader, known the user to erase blocks of 1 row, 2 rows and 4 rows as the program executive, to manage the programming (32,64 and 128 instructions) at a time and to program process. Using an SPI data frame format, the program one row at a time. It is also possible to program single executive can erase, program and verify program words. memory. For more information on Enhanced ICSP, see The 1-row (96 bytes), 2-row (192 bytes) and 4-row the device programming specification. (384 bytes) erase blocks, and single row write block (96 bytes) are edge-aligned, from the beginning of 5.4 Control Registers program memory. There are two SFRs used to read and write the When data is written to program memory using TBLWT program Flash memory: NVMCON and NVMKEY. instructions, the data is not written directly to memory. The NVMCON register (Register5-1) controls the Instead, data written using table writes is stored in holding blocks that need to be erased, which memory type is to latches until the programming sequence is executed. be programmed and when the programming cycle Any number of TBLWT instructions can be executed starts. and a write will be successfully performed. However, NVMKEY is a write-only register that is used for write 32TBLWT instructions are required to write the full row protection. To start a programming or erase sequence, of memory. the user must consecutively write 55h and AAh to the The basic sequence for RTSP programming is to set up NVMKEY register. Refer to Section5.5 “Programming a Table Pointer, then do a series of TBLWT instructions to Operations” for further details. load the buffers. Programming is performed by setting the control bits in the NVMCON register. 5.5 Programming Operations Data can be loaded in any order and the holding A complete programming sequence is necessary for registers can be written to multiple times before programming or erasing the internal Flash in RTSP performing a write operation. Subsequent writes, mode. During a programming or erase operation, the however, will wipe out any previous writes. processor stalls (waits) until the operation is finished. Note: Writing to a location multiple times without Setting the WR bit (NVMCON<15>) starts the erasing it is not recommended. operation and the WR bit is automatically cleared when the operation is finished. All of the table write operations are single-word writes (two instruction cycles), because only the buffers are written. A programming cycle is required for programming each row. DS39927C-page 46  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY(4) — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5(1) NVMOP4(1) NVMOP3(1) NVMOP2(1) NVMOP1(1) NVMOP0(1) bit 7 bit 0 Legend: SO = Settable Only bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit W = Writable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12 PGMONLY: Program Only Enable bit(4) bit 11-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<5:0> on the next WR command 0 = Perform the program operation specified by NVMOP<5:0> on the next WR command bit 5-0 NVMOP<5:0>: Programming Operation Command Byte bits(1) Erase Operations (when ERASE bit is ‘1’): 1010xx = Erase entire boot block (including code-protected boot block)(2) 1001xx = Erase entire memory (including boot block, configuration block, general block)(2) 011010 = Erase 4 rows of Flash memory(3) 011001 = Erase 2 rows of Flash memory(3) 011000 = Erase 1 row of Flash memory(3) 0101xx = Erase entire configuration block (except code protection bits) 0100xx = Erase entire data EEPROM(4) 0011xx = Erase entire general memory block programming operations 0001xx = Write 1 row of Flash memory (when ERASE bit is ‘0’)(3) Note 1: All other combinations of NVMOP<5:0> are no operation. 2: Available in ICSP™ mode only. Refer to device programming specification. 3: The address in the Table Pointer decides which rows will be erased. 4: This bit is used only while accessing data EEPROM.  2008-2011 Microchip Technology Inc. DS39927C-page 47

PIC24F16KA102 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR 4. Write the first 32 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example5-1). 5. Write the program block to Flash memory: The user can program one row of Flash program memory at a time by erasing the programmable row. a) Set the NVMOP bits to ‘000100’ to The general process is: configure for row programming. Clear the ERASE bit and set the WREN bit. 1. Read a row of program memory b) Write 55h to NVMKEY. (32instructions) and store in data RAM. c) Write AAh to NVMKEY. 2. Update the program data in RAM with the d) Set the WR bit. The programming cycle desired new data. begins and the CPU stalls for the duration 3. Erase a row (see Example5-1): of the write cycle. When the write to Flash a) Set the NVMOP bits (NVMCON<5:0>) to memory is done, the WR bit is cleared ‘011000’ to configure for row erase. Set the automatically. ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. For protection against accidental operations, the write b) Write the starting address of the block to be initiate sequence for NVMKEY must be used to allow erased into the TBLPAG and W registers. any erase or program operation to proceed. After the programming command has been executed, the user c) Write 55h to NVMKEY. must wait for the programming time until programming d) Write AAh to NVMKEY. is complete. The two instructions following the start of e) Set the WR bit (NVMCON<15>). The erase the programming sequence should be NOPs, as cycle begins and the CPU stalls for the displayed in Example5-5. duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. EXAMPLE 5-1: ERASING A PROGRAM MEMORY ROW – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row erase operation MOV #0x4058, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted EXAMPLE 5-2: ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE // C example using MPLAB C30 int __attribute__ ((space(auto_psv))) progAddr = 0x1234; // Variable located in Pgm Memory, declared as a // global variable unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); // Initialize PM Page Boundary SFR offset = __builtin_tbloffset(&progAddr); // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4058; // Initialize NVMCON asm("DISI #5"); // Block all interrupts for next 5 instructions __builtin_write_NVM(); // C30 function to perform unlock // sequence and set WR DS39927C-page 48  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY EXAMPLE 5-3: LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row programming operations MOV #0x4004, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x1500, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 32nd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0] ; Write PM high byte into program latch EXAMPLE 5-4: LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 int __attribute__ ((space(auto_psv))) progAddr = 0x1234 // Variable located in Pgm Memory unsigned int offset; unsigned int i; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; // Buffer of data to write //Set up NVMCON for row programming NVMCON = 0x4004; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = __builtin_tblpage(&progAddr); // Initialize PM Page Boundary SFR offset = __builtin_tbloffset(&progAddr); // Initialize lower word of address //Perform TBLWT instructions to write necessary number of latches for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++) { __builtin_tblwtl(offset, progData[i++]); // Write to address low word __builtin_tblwth(offset, progData[i]); // Write to upper byte offset = offset + 2; // Increment address }  2008-2011 Microchip Technology Inc. DS39927C-page 49

PIC24F16KA102 FAMILY EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE DISI #5 ; Block all interrupts for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; 2 NOPs required after setting WR NOP ; BTSC NVMCON, #15 ; Wait for the sequence to be completed BRA $-2 ; EXAMPLE 5-6: INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE // C example using MPLAB C30 asm("DISI #5"); // Block all interrupts for next 5 instructions __builtin_write_NVM(); // Perform unlock sequence and set WR DS39927C-page 50  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 6.0 DATA EEPROM MEMORY 6.1 NVMCON Register Note: This data sheet summarizes the features The NVMCON register (Register6-1) is also the pri- of this group of PIC24F devices. It is not mary control register for data EEPROM program/erase intended to be a comprehensive refer- operations. The upper byte contains the control bits ence source. For more information on used to start the program or erase cycle, and the flag Data EEPROM, refer to the “PIC24F bit to indicate if the operation was successfully Family Reference Manual”, Section 5. performed. The lower byte of NVMCOM configures the “Data EEPROM” (DS39720). type of NVM operation that will be performed. The data EEPROM memory is a Nonvolatile Memory 6.2 NVMKEY Register (NVM), separate from the program and volatile data RAM. Data EEPROM memory is based on the same The NVMKEY is a write-only register that is used to Flash technology as program memory, and is optimized prevent accidental writes or erasures of data EEPROM for both long retention and a higher number of locations. erase/write cycles. To start any programming or erase sequence, the The data EEPROM is mapped to the top of the user following instructions must be executed first, in the program memory space, with the top address at exact order provided: program memory address, 7FFE00h to 7FFFFFh. The 1. Write 55h to NVMKEY. size of the data EEPROM is 256 words in 2. Write AAh to NVMKEY. PIC24F16KA102 devices. After this sequence, a write will be allowed to the The data EEPROM is organized as 16-bit wide NVMCON register for one instruction cycle. In most memory. Each word is directly addressable, and is cases, the user will simply need to set the WR bit in the readable and writable during normal operation over the NVMCON register to start the program or erase cycle. entire VDD range. Interrupts should be disabled during the unlock Unlike the Flash program memory, normal program sequence. execution is not stopped during a data EEPROM The MPLAB® C30 C compiler provides a defined library program or erase operation. procedure (builtin_write_NVM) to perform the The data EEPROM programming operations are unlock sequence. Example6-1illustrates how the controlled using the three NVM Control registers: unlock sequence can be performed with in-line assembly. • NVMCON: Nonvolatile Memory Control Register • NVMKEY: Nonvolatile Memory Key Register • NVMADR: Nonvolatile Memory Address Register EXAMPLE 6-1: DATA EEPROM UNLOCK SEQUENCE //Disable Interrupts For 5 instructions asm volatile ("disi #5"); //Issue Unlock Sequence asm volatile ("mov #0x55, W0 \n" "mov W0, NVMKEY \n" "mov #0xAA, W1 \n" "mov W1, NVMKEY \n"); // Perform Write/Erase operations asm volatile ("bset NVMCON, #WR \n" "nop \n" "nop \n");  2008-2011 Microchip Technology Inc. DS39927C-page 51

PIC24F16KA102 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/S-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit S = Settable bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit (program or erase) 1 = Initiates a data EEPROM erase or write cycle (can be set but not cleared in software) 0 = Write cycle is complete (cleared automatically by hardware) bit 14 WREN: Write Enable bit (erase or program) 1 = Enable an erase or program operation 0 = No operation allowed (device clears this bit on completion of the write/erase operation) bit 13 WRERR: Flash Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or WDT Reset during programming operation) 0 = The write operation completed successfully bit 12 PGMONLY: Program Only Enable bit 1 = Write operation is executed without erasing target address(es) first 0 = Automatic erase-before-write: write operations are preceded automatically by an erase of target address(es) bit 11-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase Operation Select bit 1 = Perform an erase operation when WR is set 0 = Perform a write operation when WR is set bit 5-0 NVMOP<5:0>: Programming Operation Command Byte bits Erase Operations (when ERASE bit is ‘1’): 011010 = Erase 8 words 011001 = Erase 4 words 011000 = Erase 1 word 0100xx = Erase entire data EEPROM Programming Operations (when ERASE bit is ‘0’): 001xx = Write 1 word DS39927C-page 52  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 6.3 NVM Address Register Like program memory operations, the Least Significant bit (LSb) of NVMADR is restricted to even addresses. As with Flash program memory, the NVM Address This is because any given address in the data Registers, NVMADRU and NVMADR, form the 24-bit EEPROM space consists of only the lower word of the Effective Address (EA) of the selected row or word for program memory width; the upper word, including the data EEPROM operations. The NVMADRU register is uppermost “phantom byte”, are unavailable. This used to hold the upper 8 bits of the EA, while the means that the LSb of a data EEPROM address will NVMADR register is used to hold the lower 16 bits of always be ‘0’. the EA. These registers are not mapped into the Similarly, the Most Significant bit (MSb) of NVMADRU Special Function Register (SFR) space; instead, they is always ‘0’, since all addresses lie in the user program directly capture the EA<23:0> of the last table write space. instruction that has been executed and selects the data EEPROM row to erase. Figure6-1 depicts the program memory EA that is formed for programming and erase operations. FIGURE 6-1: DATA EEPROM ADDRESSING WITH TBLPAG AND NVM ADDRESS REGISTERS 24-Bit PM Address 7Fh xxxxh 0 TBLPAG W Register EA 0 NVMADRU NVMADR 6.4 Data EEPROM Operations Note1: Unexpected results will be obtained should the user attempt to read the The EEPROM block is accessed using table read and EEPROM while a programming or erase write operations, similar to those used for program operation is underway. memory. The TBLWTH and TBLRDH instructions are not required for data EEPROM operations, since the 2: The C30 C compiler includes library memory is only 16 bits wide (data on the lower address procedures to automatically perform the is valid only). The following programming operations table read and table write operations, can be performed on the data EEPROM: manage the Table Pointer and write buffers, and unlock and initiate memory • Erase one, four or eight words write sequences. This eliminates the • Bulk erase the entire data EEPROM need to create assembler macros or time • Write one word critical routines in C for each application. • Read one word The library procedures are used in the code examples detailed in the following sections. General descriptions of each process are provided for users who are not using the C30 compiler libraries.  2008-2011 Microchip Technology Inc. DS39927C-page 53

PIC24F16KA102 FAMILY 6.4.1 ERASE DATA EEPROM A typical erase sequence is provided in Example6-2. This example shows how to do a one-word erase. Sim- The data EEPROM can be fully erased, or can be ilarly, a four-word erase and an eight-word erase can partially erased, at three different sizes: one word, four be done. This example uses ‘C’ library procedures to words or eight words. The bits, NVMOP<1:0> manage the Table Pointer (builtin_tblpage and (NVMCON<1:0>), decide the number of words to be builtin_tbloffset) and the Erase Page Pointer erased. To erase partially from the data EEPROM, the (builtin_tblwtl). The memory unlock sequence following sequence must be followed: (builtin_write_NVM) also sets the WR bit to initiate 1. Configure NVMCON to erase the required the operation and returns control when complete. number of words: one, four or eight. 2. Load TBLPAG and WREG with the EEPROM address to be erased. 3. Clear NVMIF status bit and enable NVM interrupt (optional). 4. Write the key sequence to NVMKEY. 5. Set the WR bit to begin erase cycle. 6. Either poll the WR bit or wait for the NVM interrupt (NVMIF set). EXAMPLE 6-2: SINGLE-WORD ERASE int __attribute__ ((space(eedata))) eeData = 0x1234; // Variable located in EEPROM unsigned int offset; // Set up NVMCON to erase one word of data EEPROM NVMCON = 0x4058; // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address __builtin_tblwtl(offset, 0); // Write EEPROM data to write latch asm volatile ("disi #5"); // Disable Interrupts For 5 Instructions __builtin_write_NVM(); // Issue Unlock Sequence & Start Write Cycle DS39927C-page 54  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 6.4.1.1 Data EEPROM Bulk Erase 6.4.2 SINGLE-WORD WRITE To erase the entire data EEPROM (bulk erase), the To write a single word in the data EEPROM, the address registers do not need to be configured following sequence must be followed: because this operation affects the entire data 1. Erase one data EEPROM word (as mentioned in EEPROM. The following sequence helps in performing Section6.4.1 “Erase Data EEPROM”) if the bulk erase: PGMONLY bit (NVMCON<12>) is set to ‘1’. 1. Configure NVMCON to Bulk Erase mode. 2. Write the data word into the data EEPROM 2. Clear NVMIF status bit and enable NVM latch. interrupt (optional). 3. Program the data word into the EEPROM: 3. Write the key sequence to NVMKEY. - Configure the NVMCON register to program one 4. Set the WR bit to begin erase cycle. EEPROM word (NVMCON<5:0> = 0001xx). 5. Either poll the WR bit or wait for the NVM - Clear NVMIF status bit and enable NVM interrupt (NVMIF is set). interrupt (optional). - Write the key sequence to NVMKEY. A typical bulk erase sequence is provided in - Set the WR bit to begin erase cycle. Example6-3. - Either poll the WR bit or wait for the NVM interrupt (NVMIF is set). - To get cleared, wait until NVMIF is set. A typical single-word write sequence is provided in Example6-4. EXAMPLE 6-3: DATA EEPROM BULK ERASE // Set up NVMCON to bulk erase the data EEPROM NVMCON = 0x4050; // Disable Interrupts For 5 Instructions asm volatile ("disi #5"); // Issue Unlock Sequence and Start Erase Cycle __builtin_write_NVM(); EXAMPLE 6-4: SINGLE-WORD WRITE TO DATA EEPROM int __attribute__ ((space(eedata))) eeData = 0x1234; // Variable located in EEPROM,declared as a global variable. int newData; // New data to write to EEPROM unsigned int offset; // Set up NVMCON to erase one word of data EEPROM NVMCON = 0x4004; // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address __builtin_tblwtl(offset, newData); // Write EEPROM data to write latch asm volatile ("disi #5"); // Disable Interrupts For 5 Instructions __builtin_write_NVM(); // Issue Unlock Sequence & Start Write Cycle  2008-2011 Microchip Technology Inc. DS39927C-page 55

PIC24F16KA102 FAMILY 6.4.3 READING THE DATA EEPROM A typical read sequence, using the Table Pointer manage- ment (builtin_tblpage and builtin_tbloffset) To read a word from data EEPROM, the table read and table read (builtin_tblrdl) procedures from the instruction is used. Since the EEPROM array is only C30 compiler library, is provided in Example6-5. 16bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG Program Space Visibility (PSV) can also be used to and WREG with the address of the EEPROM location, read locations in the data EEPROM. followed by a TBLRDL instruction. EXAMPLE 6-5: READING THE DATA EEPROM USING THE TBLRD COMMAND int __attribute__ ((space(eedata))) eeData = 0x1234; // Variable located in EEPROM,declared // as a global variable int data; // Data read from EEPROM unsigned int offset; // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address data = __builtin_tblrdl(offset); // Write EEPROM data to write latch DS39927C-page 56  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 7.0 RESETS Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU Note: This data sheet summarizes the features and peripherals are forced to a known Reset state. of this group of PIC24F devices. It is not Most registers are unaffected by a Reset; their status is intended to be a comprehensive unknown on a Power-on Reset (POR) and unchanged reference source. For more information by all other Resets. on Resets, refer to the “PIC24F Family Note: Refer to the specific peripheral or CPU Reference Manual”, Section 40. “Reset section of this manual for register Reset with Programmable Brown-out Reset” states. (DS39728). The Reset module combines all Reset sources and All types of device Reset will set a corresponding status controls the device Master Reset Signal, SYSRST. The bit in the RCON register to indicate the type of Reset following is a list of device Reset sources: (see Register7-1). A POR will clear all bits except for the BOR and POR bits (RCON<1:0>) which are set. • POR: Power-on Reset The user may set or clear any bit at any time during • MCLR: Pin Reset code execution. The RCON bits only serve as status • SWR: RESET Instruction bits. Setting a particular Reset status bit in software will • WDTR: Watchdog Timer Reset not cause a device Reset to occur. • BOR: Brown-out Reset The RCON register also has other bits associated with • Low-Power BOR/Deep Sleep BOR the Watchdog Timer (WDT) and device power-saving • TRAPR: Trap Conflict Reset states. The function of these bits is discussed in other • IOPUWR: Illegal Opcode Reset sections of this manual. • UWR: Uninitialized W Register Reset Note: The status bits in the RCON register Figure7-1 displays a simplified block diagram of the should be cleared after they are read so Reset module. that the next RCON register value, after a device Reset, will be meaningful. FIGURE 7-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise POR Detect SYSRST BOREN<1:0> VDD 0 00 Brown-out BOR RCON<SBOREN> 01 Reset SLEEP 10 1 11 Trap Conflict Illegal Opcode Uninitialized W Register  2008-2011 Microchip Technology Inc. DS39927C-page 57

PIC24F16KA102 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER(1) R/W-0, HS R/W-0, HS R/W-0 U-0 U-0 R/C-0, HS R/W-0, HS R/W-0 TRAPR IOPUWR SBOREN — — DPSLP CM PMSLP bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13 SBOREN: Software Enable/Disable of BOR bit 1 = BOR is turned on in software 0 = BOR is turned off in software bit 12-11 Unimplemented: Read as ‘0’ bit 10 DPSLP: Deep Sleep Mode Flag bit 1 = Deep Sleep has occurred 0 = Deep Sleep has not occurred bit 9 CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch has occurred 0 = A Configuration Word Mismatch has not occurred bit 8 PMSLP: Program Memory Power During Sleep bit 1 = Program memory bias voltage remains powered during Sleep 0 = Program memory bias voltage is powered down during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS39927C-page 58  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set after a POR) 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. TABLE 7-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap Conflict Event POR IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR CM (RCON<9>) Configuration Mismatch Reset POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR IDLE (RCON<2>) PWRSAV #IDLE Instruction POR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — DPSLP (RCON<10>) PWRSAV #SLEEP instruction with DSCON <DSEN> set POR Note: All Reset flag bits may be set or cleared by the user software.  2008-2011 Microchip Technology Inc. DS39927C-page 59

PIC24F16KA102 FAMILY 7.1 Clock Source Selection at Reset 7.2 Device Reset Times If clock switching is enabled, the system clock source at The Reset times for various types of device Reset are device Reset is chosen, as shown in Table7-2. If clock summarized in Table7-3. Note that the system Reset switching is disabled, the system clock source is always signal, SYSRST, is released after the POR and PWRT selected according to the oscillator Configuration bits. delay times expire. Refer to Section9.0 “Oscillator Configuration” for The time at which the device actually begins to execute further details. code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and TABLE 7-2: OSCILLATOR SELECTION vs. the PLL lock time. The OST and PLL lock times occur TYPE OF RESET (CLOCK in parallel with the applicable SYSRST delay times. SWITCHING ENABLED) The FSCM delay determines the time at which the Reset Type Clock Source Determinant FSCM begins to monitor the system clock source after the SYSRST signal is released. POR FNOSC Configuration bits BOR (FNOSC<10:8>) MCLR COSC Control bits WDTO (OSCCON<14:12>) SWR TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS System Clock Reset Type Clock Source SYSRST Delay Notes Delay POR(6) EC TPOR + TPWRT — 1, 2 FRC, FRCDIV TPOR + TPWRT TFRC 1, 2, 3 LPRC TPOR + TPWRT TLPRC 1, 2, 3 ECPLL TPOR + TPWRT TLOCK 1, 2, 4 FRCPLL TPOR + TPWRT TFRC + TLOCK 1, 2, 3, 4 XT, HS, SOSC TPOR+ TPWRT TOST 1, 2, 5 XTPLL, HSPLL TPOR + TPWRT TOST + TLOCK 1, 2, 4, 5 BOR EC TPWRT — 2 FRC, FRCDIV TPWRT TFRC 2, 3 LPRC TPWRT TLPRC 2, 3 ECPLL TPWRT TLOCK 2, 4 FRCPLL TPWRT TFRC + TLOCK 2, 3, 4 XT, HS, SOSC TPWRT TOST 2, 5 XTPLL, HSPLL TPWRT TFRC + TLOCK 2, 3, 4 All Others Any Clock — — None Note 1: TPOR = Power-on Reset (POR) delay. 2: TPWRT = 64 ms nominal if the Power-up Timer (PWRT) is enabled; otherwise, it is zero. 3: TFRC and TLPRC = RC oscillator start-up times. 4: TLOCK = PLL lock time. 5: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the oscillator clock to the system. 6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC, and in such cases, FRC start-up time is valid. Note: For detailed operating frequency and timing specifications, see Section29.0 “Electrical Characteristics”. DS39927C-page 60  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 7.2.1 POR AND LONG OSCILLATOR 7.5 Brown-out Reset (BOR) START-UP TIMES The PIC24F16KA102 family devices implement a BOR The oscillator start-up circuitry and its associated delay circuit, which provides the user several configuration timers are not linked to the device Reset delays that and power-saving options. The BOR is controlled by occur at power-up. Some crystal circuits (especially the BORV<1:0> and BOREN<1:0> Configuration bits low-frequency crystals) will have a relatively long (FPOR<6:5,1:0>). There are a total of four BOR start-up time. Therefore, one or more of the following configurations, which are provided in Table7-3. conditions is possible after SYSRST is released: The BOR threshold is set by the BORV<1:0> bits. If • The oscillator circuit has not begun to oscillate. BOR is enabled (any values of BOREN<1:0>, except • The Oscillator Start-up Timer (OST) has not ‘00’), any drop of VDD below the set threshold point will expired (if a crystal oscillator is used). reset the device. The chip will remain in BOR until VDD • The PLL has not achieved a lock (if PLL is used). rises above threshold. The device will not begin to execute code until a valid If the Power-up Timer is enabled, it will be invoked after clock source has been released to the system. There- VDD rises above the threshold. Then, it will keep the chip fore, the oscillator and PLL start-up delays must be in Reset for an additional time delay, TPWRT, if VDD drops considered when the Reset delay time must be known. below the threshold while the Power-up Timer is running. The chip goes back into a BOR and the Power-up Timer 7.2.2 FAIL-SAFE CLOCK MONITOR will be initialized. Once VDD rises above the threshold, (FSCM) AND DEVICE RESETS the Power-up Timer will execute the additional time delay. If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a BOR and the Power-up Timer are independently valid clock source is not available at this time, the configured. Enabling the BOR Reset does not device will automatically switch to the FRC oscillator automatically enable the PWRT. and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR). 7.5.1 SOFTWARE ENABLED BOR 7.3 Special Function Register Reset When BOREN<1:0> = 01, the BOR can be enabled or States disabled by the user in software. This is done with the control bit, SBOREN (RCON<13>). Setting SBOREN Most of the Special Function Registers (SFRs) associ- enables the BOR to function as previously described. ated with the PIC24F CPU and peripherals are reset to a Clearing the SBOREN disables the BOR entirely. The particular value at a device Reset. The SFRs are SBOREN bit operates only in this mode; otherwise, it is grouped by their peripheral or CPU function and their read as ‘0’. Reset values are specified in each section of this manual. Placing BOR under software control gives the user the The Reset value for each SFR does not depend on the additional flexibility of tailoring the application to its type of Reset with the exception of four registers. The environment without having to reprogram the device to Reset value for the Reset Control register, RCON, will change the BOR configuration. It also allows the user depend on the type of device Reset. The Reset value to tailor the incremental current that the BOR con- for the Oscillator Control register, OSCCON, will sumes. While the BOR current is typically very small, it depend on the type of Reset and the programmed may have some impact in low-power applications. values of the FNOSC bits in the Flash Configuration Word (FOSCSEL); see Table7-2. The RCFGCAL and Note: Even when the BOR is under software NVMCON registers are only affected by a POR. control, the BOR Reset voltage level is still set by the BORV<1:0> Configuration bits; 7.4 Deep Sleep BOR (DSBOR) it can not be changed in software. Deep Sleep BOR is a very low-power BOR circuitry, used when the device is in Deep Sleep mode. Due to low-current consumption, accuracy may vary. The DSBOR trip point is around 2.0V. DSBOR is enabled by configuring DSBOREN (FDS<6>) = 1. DSBOREN will re-arm the POR to ensure the device will reset if VDD drops below the POR threshold.  2008-2011 Microchip Technology Inc. DS39927C-page 61

PIC24F16KA102 FAMILY 7.5.2 DETECTING BOR 7.5.3 DISABLING BOR IN SLEEP MODE When BOR is enabled, the BOR bit (RCON<1>) is When BOREN<1:0> = 10, BOR remains under hard- always reset to ‘1’ on any BOR or POR event. This ware control and operates as previously described. makes it difficult to determine if a BOR event has However, whenever the device enters Sleep mode, occurred just by reading the state of BOR alone. A BOR is automatically disabled. When the device more reliable method is to simultaneously check the returns to any other operating mode, BOR is state of both POR and BOR. This assumes that the automatically re-enabled. POR and BOR bits are reset to ‘0’ in the software This mode allows for applications to recover from immediately after any POR event. If the BOR bit is ‘1’ brown-out situations, while actively executing code, while the POR bit is ‘0’, it can be reliably assumed that when the device requires BOR protection the most. At a BOR event has occurred. the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. Note: Even when the device exits from Deep Sleep mode, both the POR and BOR are set. DS39927C-page 62  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 8.0 INTERRUPT CONTROLLER 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE (AIVT) Note: This data sheet summarizes the features The Alternate Interrupt Vector Table (AIVT) is located of this group of PIC24F devices. It is not after the IVT, as displayed in Figure8-1. Access to the intended to be a comprehensive AIVT is provided by the ALTIVT control bit reference source. For more information (INTCON2<15>). If the ALTIVT bit is set, all interrupt on the Interrupt Controller, refer to the and exception processes will use the alternate vectors “PIC24F Family Reference Manual”, instead of the default vectors. The alternate vectors are Section 8. “Interrupts” (DS39707). organized in the same manner as the default vectors. The PIC24F interrupt controller reduces the numerous The AIVT supports emulation and debugging efforts by peripheral interrupt request signals to a single interrupt providing a means to switch between an application request signal to the CPU. It has the following features: and a support environment without requiring the • Up to eight processor exceptions and interrupt vectors to be reprogrammed. This feature also software traps enables switching between applications for evaluation • Seven user-selectable priority levels of different software algorithms at run-time. If the AIVT is not needed, the AIVT should be programmed with • Interrupt Vector Table (IVT) with up to 118 vectors the same addresses used in the IVT. • Unique vector for each interrupt or exception source 8.2 Reset Sequence • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug A device Reset is not a true exception because the support interrupt controller is not involved in the Reset process. • Fixed interrupt entry and return latencies The PIC24F devices clear their registers in response to a Reset, which forces the Program Counter (PC) to 8.1 Interrupt Vector (IVT) Table zero. The microcontroller then begins program execu- tion at location, 000000h. The user programs a GOTO The IVT is displayed in Figure8-1. The IVT resides in instruction at the Reset address, which redirects the the program memory, starting at location, 000004h. program execution to the appropriate start-up routine. The IVT contains 126 vectors, consisting of eight non-maskable trap vectors, plus, up to 118 sources of Note: Any unimplemented or unused vector interrupt. In general, each interrupt source has its own locations in the IVT and AIVT should be vector. Each interrupt vector contains a 24-bit wide programmed with the address of a default address. The value programmed into each interrupt interrupt handler routine that contains a vector location is the starting address of the associated RESET instruction. Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with Vector 0 will take priority over interrupts at any other vector address. PIC24F16KA102 family devices implement non-maskable traps and unique interrupts; these are summarized in Table8-1 and Table8-2.  2008-2011 Microchip Technology Inc. DS39927C-page 63

PIC24F16KA102 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction 000000h Reset – GOTO Address 000002h Reserved 000004h Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000014h Interrupt Vector 1 — — — Interrupt Vector 52 00007Ch y Interrupt Vector Table (IVT)(1) orit Interrupt Vector 53 00007Eh Pri Interrupt Vector 54 000080h er — d — Or — ural Interrupt Vector 116 0000FCh at Interrupt Vector 117 0000FEh N g Reserved 000100h n Reserved 000102h si a Reserved e cr Oscillator Fail Trap Vector e D Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000114h Interrupt Vector 1 — — — Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 52 00017Ch Interrupt Vector 53 00017Eh Interrupt Vector 54 000180h — — — Interrupt Vector 116 Interrupt Vector 117 0001FEh Start of Code 000200h Note 1: See Table8-2 for the interrupt vector list. DS39927C-page 64  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h Reserved 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector AIVT Interrupt Source IVT Address Number Address Flag Enable Priority ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> CTMU 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4> External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0> External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0> External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4> I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4> I2C1 Slave Event 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0> Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4> Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12> HLVD High/Low-Voltage Detect 72 0000A4h 0001A4h IFS4<8> IEC4<8> IPC17<2:0> NVM – NVM Write Complete 15 000032h 000132h IFS0<15> IEC0<15> IPC3<14:12> Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8> Real-Time Clock/Calendar 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8> SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4> SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8> Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12> Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12> Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0> UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4> UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12> UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0> UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8> UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8> UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12>  2008-2011 Microchip Technology Inc. DS39927C-page 65

PIC24F16KA102 FAMILY 8.3 Interrupt Control and Status The INTTREG register contains the associated inter- Registers rupt vector number and the new CPU interrupt priority level, which are latched into the Vector Number The PIC24F16KA102 family of devices implements a (VECNUM<6:0>) and the Interrupt Level (ILR<3:0>) bit total of 22 registers for the interrupt controller: fields in the INTTREG register. The new interrupt • INTCON1 priority level is the priority of the pending interrupt. • INTCON2 The interrupt sources are assigned to the IFSx, IECx • IFS0, IFS1, IFS3 and IFS4 and IPCx registers in the same sequence listed in • IEC0, IEC1, IEC3 and IEC4 Table8-2. For example, the INT0 (External Interrupt 0) • IPC0 through IPC5, IPC7 and IPC15 through is depicted as having a vector number and a natural IPC19 order priority of 0. Thus, the INT0IF status bit is found in IFS0<0>, the INT0IE enable bit in IEC0<0> and the • INTTREG INT0IP<2:0> priority bits in the first position of IPC0 Global interrupt control functions are controlled from (IPC0<2:0>). INTCON1 and INTCON2. INTCON1 contains the Although they are not specifically part of the interrupt Interrupt Nesting Disable (NSTDIS) bit, as well as the control hardware, two of the CPU control registers control and status flags for the processor trap sources. contain bits that control interrupt functionality. The ALU The INTCON2 register controls the external interrupt STATUS register (SR) contains the IPL<2:0> bits request signal behavior and the use of the AIV table. (SR<7:5>). These indicate the current CPU interrupt The IFSx registers maintain all of the interrupt request priority level. The user may change the current CPU flags. Each source of interrupt has a status bit, which is priority level by writing to the IPL bits. set by the respective peripherals, or external signal, The CORCON register contains the IPL3 bit, which and is cleared via software. together with IPL<2:0>, also indicates the current CPU The IECx registers maintain all of the interrupt enable priority level. IPL3 is a read-only bit so that the trap bits. These control bits are used to individually enable events cannot be masked by the user’s software. interrupts from the peripherals or external signals. All interrupt registers are described in Register8-1 The IPCx registers are used to set the interrupt priority through Register8-21, in the following sections. level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. DS39927C-page 66  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — DC(1) bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) Note 1: See Register3-1 for the description of these bits, which are not dedicated to interrupt control functions. 2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. 3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. Note: Bit 8 and Bits 4 through 0 are described in Section 3.0 “CPU”.  2008-2011 Microchip Technology Inc. DS39927C-page 67

PIC24F16KA102 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(2) PSV(1) — — bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 1-0 Unimplemented: Read as ‘0’ Note 1: See Register3-2 for the description of this bit, which is not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. Note: Bit 2 is described in Section 3.0 “CPU”. DS39927C-page 68  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2008-2011 Microchip Technology Inc. DS39927C-page 69

PIC24F16KA102 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS39927C-page 70  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS NVMIF — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF bit 15 bit 8 R/W-0, HS U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS T2IF — — — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NVMIF: NVM Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 Unimplemented: Read as ‘0’ bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6-4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2008-2011 Microchip Technology Inc. DS39927C-page 71

PIC24F16KA102 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0 U-0 U-0 U-0 U2TXIF U2RXIF INT2IF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0 R/W-0 — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39927C-page 72  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-0 Unimplemented: Read as ‘0’  2008-2011 Microchip Technology Inc. DS39927C-page 73

PIC24F16KA102 FAMILY REGISTER 8-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS — — CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-9 Unimplemented: Read as ‘0’ bit 8 HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS39927C-page 74  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMIE — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE — — — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NVMIE: NVM Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 Unimplemented: Read as ‘0’ bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request not is enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2008-2011 Microchip Technology Inc. DS39927C-page 75

PIC24F16KA102 FAMILY REGISTER 8-10: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U2TXIE U2RXIE INT2IE — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS39927C-page 76  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-0 Unimplemented: Read as ‘0’  2008-2011 Microchip Technology Inc. DS39927C-page 77

PIC24F16KA102 FAMILY REGISTER 8-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-9 Unimplemented: Read as ‘0’ bit 8 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ DS39927C-page 78  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2011 Microchip Technology Inc. DS39927C-page 79

PIC24F16KA102 FAMILY REGISTER 8-14: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T2IP2 T2IP1 T2IP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ DS39927C-page 80  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2011 Microchip Technology Inc. DS39927C-page 81

PIC24F16KA102 FAMILY REGISTER 8-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP<2:0>: NVM Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS39927C-page 82  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1P<2:0>: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2011 Microchip Technology Inc. DS39927C-page 83

PIC24F16KA102 FAMILY REGISTER 8-18: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS39927C-page 84  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT2IP2 INT2IP1 INT2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2008-2011 Microchip Technology Inc. DS39927C-page 85

PIC24F16KA102 FAMILY REGISTER 8-20: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39927C-page 86  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-21: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2008-2011 Microchip Technology Inc. DS39927C-page 87

PIC24F16KA102 FAMILY REGISTER 8-22: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 8-23: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS39927C-page 88  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 8-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will happen when the CPU priority is higher than the interrupt priority) 0 = No interrupt request is left unacknowledged bit 14 Unimplemented: Read as ‘0’ bit 13 VHOLD: Allows Vector Number Capture and Changes what Interrupt is Stored in VECNUM bit 1 = VECNUM will contain the value of the highest priority pending interrupt, instead of the current interrupt 0 = VECNUM will contain the value of the last Acknowledged interrupt (last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is Number 135 • • • 0000001 = Interrupt Vector pending is Number 9 0000000 = Interrupt Vector pending is Number 8  2008-2011 Microchip Technology Inc. DS39927C-page 89

PIC24F16KA102 FAMILY 8.4 Interrupt Setup Procedures 8.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, 8.4.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. 8.4.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the All user interrupts can be disabled using the following appropriate IPCx register. The priority level will procedure: depend on the specific application and type of 1. Push the current SR value onto the software interrupt source. If multiple priority levels are not stack using the PUSH instruction. desired, the IPCx register control bits, for all 2. Force the CPU to Priority Level 7 by inclusive enabled interrupt sources, may be programmed ORing the value OEh with SRL. to the same non-zero value. To enable user interrupts, the POP instruction may be Note: At a device Reset, the IPCx registers are used to restore the previous SR value. initialized, such that all user interrupt Only user interrupts with a priority level of 7 or less can sources are assigned to Priority Level 4. be disabled. Trap sources (Levels8-15) cannot be 3. Clear the interrupt flag status bit associated with disabled. the peripheral in the associated IFSx register. The DISI instruction provides a convenient way to 4. Enable the interrupt source by setting the disable interrupts of Priority Levels 1-6 for a fixed interrupt enable control bit associated with the period. Level 7 interrupt sources are not disabled by source in the appropriate IECx register. the DISI instruction. 8.4.2 INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR and initialize the IVT with the correct vector address depends on the programming language (i.e., C or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS39927C-page 90  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 9.0 OSCILLATOR • Software-controllable switching between various CONFIGURATION clock sources. • Software-controllable postscaler for selective Note: This data sheet summarizes the fea- clocking of CPU for system power savings. tures of this group of PIC24F devices. It • System frequency range declaration bits for EC is not intended to be a comprehensive mode. When using an external clock source, the reference source. For more information current consumption is reduced by setting the on Oscillator Configuration, refer to the declaration bits to the expected frequency range. “PIC24F Family Reference Manual”, • A Fail-Safe Clock Monitor (FSCM) that detects clock Section 38. “Oscillator with 500 kHz failure and permits safe application recovery or Low-Power FRC” (DS39726). shutdown. The oscillator system for the PIC24F16KA102 family of Figure9-1 provides a simplified diagram of the oscillator devices has the following features: system. • A total of five external and internal oscillator options as clock sources, providing 11 different clock modes. • On-chip 4x Phase Locked Loop (PLL) to boost internal operating frequency on select internal and external oscillator sources. FIGURE 9-1: PIC24F16KA102 FAMILY CLOCK DIAGRAM Primary Oscillator REFOCON<15:8> XT, HS, EC OSCO Reference Clock Generator XTPLL, HSPLL OSCI ECPLL,FRCPLL 4 x PLL REFO 8 MHz 8 MHz aler 4 MHz FRCDIV FRC c s Oscillator st o P Peripherals 500 kHz LPFRC CLKDIV<10:8> FRC Oscillator CLKO LPRC LPRC Oscillator 31 kHz (nominal) aler CPU c s st Secondary Oscillator o P SOSC SOSCO SOSCEN CLKDIV<14:12> Enable Oscillator SOSCI Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT, DSWDT Clock Source Option for Other Modules  2008-2011 Microchip Technology Inc. DS39927C-page 91

PIC24F16KA102 FAMILY 9.1 CPU Clocking Scheme 9.2 Initial Configuration on POR The system clock source can be provided by one of The oscillator source (and operating mode) that is used four sources: at a device Power-on Reset (POR) event is selected using Configuration bit settings. The Oscillator • Primary Oscillator (POSC) on the OSCI and OSCO Configuration bit settings are located in the Configuration pins registers in the program memory (refer to Section26.1 • Secondary Oscillator (SOSC) on the SOSCI and “Configuration Bits” for further details). The Primary SOSCO pins Oscillator Configuration bits, POSCMD<1:0> The PIC24F16KA102 family devices consist of two (FOSC<1:0>), and the Initial Oscillator Select Configura- types of secondary oscillator: tion bits, FNOSC<2:0> (FOSCSEL<2:0>), select the - High-Power Secondary Oscillator oscillator source that is used at a POR. The FRC Primary Oscillator with Postscaler (FRCDIV) is the default (unpro- - Low-Power Secondary Oscillator grammed) selection. The secondary oscillator, or one of These can be selected by using the SOSCSEL the internal oscillators, may be chosen by programming (FOSC<5>) bit. these bit locations. The EC mode frequency range • Fast Internal RC (FRC) Oscillator Configuration bits, POSCFREQ<1:0> (FOSC<4:3>), - 8 MHz FRC Oscillator optimize power consumption when running in EC - 500 kHz Lower Power FRC Oscillator mode. The default configuration is “frequency range is greater than 8 MHz”. • Low-Power Internal RC (LPRC) Oscillator The Configuration bits allow users to choose between The primary oscillator and 8 MHz FRC sources have the various clock modes, shown in Table9-1. the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by 9.2.1 CLOCK SWITCHING MODE the programmable clock divider. The selected clock CONFIGURATION BITS source generates the processor and peripheral clock sources. The FCKSM Configuration bits (FOSC<7:6>) are used jointly to configure device clock switching and the The processor clock source is divided by two to produce FSCM. Clock switching is enabled only when FCKSM1 the internal instruction cycle clock, FCY. In this docu- is programmed (‘0’). The FSCM is enabled only when ment, the instruction cycle clock is also denoted by FCKSM<1:0> are both programmed (‘00’). FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the primary oscillator. TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Note 8 MHz FRC Oscillator with Postscaler Internal 11 111 1, 2 (FRCDIV) 500 MHz FRC Oscillator with Postscaler Internal 11 110 1 (LPFRCDIV) Low-Power RC Oscillator (LPRC) Internal 11 101 1 Secondary (Timer1) Oscillator (SOSC) Secondary 00 100 1 Primary Oscillator (HS) with PLL Module Primary 10 011 (HSPLL) Primary Oscillator (EC) with PLL Module Primary 00 011 (ECPLL) Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 8 MHz FRC Oscillator with PLL Module Internal 11 001 1 (FRCPLL) 8 MHz FRC Oscillator (FRC) Internal 11 000 1 Note 1: OSCO pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. DS39927C-page 92  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 9.3 Control Registers The Clock Divider register (Register9-2) controls the features associated with Doze mode, as well as the The operation of the oscillator is controlled by three postscaler for the FRC oscillator. Special Function Registers (SFRs): The FRC Oscillator Tune register (Register9-3) allows • OSCCON the user to fine tune the FRC oscillator over a range of • CLKDIV approximately ±5.25%. Each bit increment or decre- • OSCTUN ment changes the factory calibrated frequency of the The OSCCON register (Register9-1) is the main con- FRC oscillator by a fixed amount. trol register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0, HSC R-0, HSC R-0, HSC U-0 R/W-x(1) R/W-x(1) R/W-x(1) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/SO-0, HSC U-0 R-0, HSC(2) U-0 R/CO-0, HS U-0 R/W-0 R/W-0 CLKLOCK — LOCK — CF — SOSCEN OSWEN bit 7 bit 0 Legend: CO = Clearable Only bit SO = Settable Only bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV) 110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL) 000 = 8 MHz FRC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1) 111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV) 110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL) 000 = 8 MHz FRC Oscillator (FRC) Note 1: Reset values for these bits are determined by the FNOSC Configuration bits. 2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.  2008-2011 Microchip Technology Inc. DS39927C-page 93

PIC24F16KA102 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 Unimplemented: Read as ‘0’ bit 5 LOCK: PLL Lock Status bit(2) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 Unimplemented: Read as ‘0’ bit 1 SOSCEN: 32kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to clock source specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Reset values for these bits are determined by the FNOSC Configuration bits. 2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. DS39927C-page 94  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU and peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: CPU and Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: DOZE Enable bit(1) 1 = DOZE<2:0> bits specify the CPU and peripheral clock ratio 0 = CPU and peripheral clock ratio are set to 1:1 bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits When OSCCON (COSC<2:0>) = 111: 111 = 31.25 kHz (divide by 256) 110 = 125 kHz (divide by 64) 101 = 250 kHz (divide by 32) 100 = 500 kHz (divide by 16) 011 = 1 MHz (divide by 8) 010 = 2 MHz (divide by 4) 001 = 4 MHz (divide by 2) (default) 000 = 8 MHz (divide by 1) When OSCCON (COSC<2:0>) = 110: 111 = 1.95 kHz (divide by 256) 110 = 7.81 kHz (divide by 64) 101 = 15.62 kHz (divide by 32) 100 = 31.25 kHz (divide by 16) 011 = 62.5 kHz (divide by 8) 010 = 125 kHz (divide by 4) 001 = 250 kHz (divide by 2) (default) 000 = 500 kHz (divide by 1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.  2008-2011 Microchip Technology Inc. DS39927C-page 95

PIC24F16KA102 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 · · · 000001 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 · · · 100001 100000 = Minimum frequency deviation Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. DS39927C-page 96  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 9.4 Clock Switching Operation Once the basic sequence is completed, the system clock hardware responds automatically as follows: With few limitations, applications are free to switch 1. The clock switching hardware compares the between any of the four clock sources (POSC, SOSC, COSCx bits with the new value of the NOSCx FRC and LPRC) under software control and at any bits. If they are the same, then the clock switch time. To limit the possible side effects that could result is a redundant operation. In this case, the from this flexibility, PIC24F devices have a safeguard OSWEN bit is cleared automatically and the lock built into the switching process. clock switch is aborted. Note: The Primary Oscillator mode has three 2. If a valid clock switch has been initiated, the different submodes (XT, HS and EC), LOCK (OSCCON<5>) and CF (OSCCON<3>) which are determined by the POSCMDx bits are cleared. Configuration bits. While an application 3. The new oscillator is turned on by the hardware can switch to and from Primary Oscillator if it is not currently running. If a crystal oscillator mode in software, it cannot switch must be turned on, the hardware will wait until between the different primary submodes the OST expires. If the new source is using the without reprogramming the device. PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). 9.4.1 ENABLING CLOCK SWITCHING 4. The hardware waits for 10 clock cycles from the To enable clock switching, the FCKSM1 Configuration bit new clock source and then performs the clock in the FOSC Configuration register must be programmed switch. to ‘0’. (Refer to Section26.1 “Configuration Bits” for 5. The hardware clears the OSWEN bit to indicate a further details.) If the FCKSM1 Configuration bit is unpro- successful clock transition. In addition, the grammed (‘1’), the clock switching function and FSCM NOSCx bits value is transferred to the COSCx function are disabled; this is the default setting. bits. The NOSCx control bits (OSCCON<10:8>) do not 6. The old clock source is turned off at this time, control the clock selection when clock switching is with the exception of LPRC (if WDT, FSCM or disabled. However, the COSCx bits (OSCCON<14:12>) RTCC with LPRC as clock source are enabled) will reflect the clock source selected by the FNOSCx or SOSC (if SOSCEN remains enabled). Configuration bits. Note1: The processor will continue to execute The OSWEN control bit (OSCCON<0>) has no effect code throughout the clock switching when clock switching is disabled; it is held at ‘0’ at all sequence. Timing-sensitive code should times. not be executed during this time. 9.4.2 OSCILLATOR SWITCHING 2: Direct clock switches between any SEQUENCE Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This At a minimum, performing a clock switch requires this applies to clock switches in either basic sequence: direction. In these instances, the 1. If desired, read the COSCx bits (OSCCON<14:12>), application must switch to FRC mode as to determine the current oscillator source. a transition clock source between the two 2. Perform the unlock sequence to allow a write to PLL modes. the OSCCON register high byte. 3. Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source. 4. Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch.  2008-2011 Microchip Technology Inc. DS39927C-page 97

PIC24F16KA102 FAMILY The following code sequence for a clock switch is 9.5 Reference Clock Output recommended: In addition to the CLKO output (FOSC/2) available in 1. Disable interrupts during the OSCCON register certain oscillator modes, the device clock in the unlock and write sequence. PIC24F16KA102 family devices can also be configured 2. Execute the unlock sequence for the OSCCON to provide a reference clock output signal to a port pin. high byte by writing 78h and 9Ah to This feature is available in all oscillator configurations OSCCON<15:8> in two back-to-back instructions. and allows the user to select a greater range of clock 3. Write new oscillator source to the NOSCx bits in submultiples to drive external devices in the the instruction immediately following the unlock application. sequence. This reference clock output is controlled by the 4. Execute the unlock sequence for the OSCCON REFOCON register (Register9-4). Setting the ROEN low byte by writing 46h and 57h to bit (REFOCON<15>) makes the clock signal available OSCCON<7:0> in two back-to-back instructions. on the REFO pin. The RODIV bits (REFOCON<11:8>) 5. Set the OSWEN bit in the instruction immediately enable the selection of 16 different clock divider following the unlock sequence. options. 6. Continue to execute code that is not The ROSSLP and ROSEL bits (REFOCON<13:12>) clock-sensitive (optional). control the availability of the reference output during 7. Invoke an appropriate amount of software delay Sleep mode. The ROSEL bit determines if the oscillator (cycle counting) to allow the selected oscillator on OSC1 and OSC2, or the current system clock and/or PLL to start and stabilize. source, is used for the reference clock output. The 8. Check to see if OSWEN is ‘0’. If it is, the switch ROSSLP bit determines if the reference source is was successful. If OSWEN is still set, then check available on REFO when the device is in Sleep mode. the LOCK bit to determine the cause of failure. To use the reference clock output in Sleep mode, both The core sequence for unlocking the OSCCON register the ROSSLP and ROSEL bits must be set. The device and initiating a clock switch is provided in Example9-1. clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the ROSEL bit is EXAMPLE 9-1: BASIC CODE SEQUENCE not also set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. FOR CLOCK SWITCHING Clearing the ROSEL bit allows the reference output ;Place the new oscillator selection in W0 frequency to change as the system clock changes ;OSCCONH (high byte) Unlock Sequence during any clock switches. MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 DS39927C-page 98  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator is enabled on REFO pin 0 = Reference oscillator is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator is used as the base clock(1) 0 = System clock is used as the base clock; base clock reflects any clock switching of the device bit 11-8 RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.  2008-2011 Microchip Technology Inc. DS39927C-page 99

PIC24F16KA102 FAMILY NOTES: DS39927C-page 100  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 10.0 POWER-SAVING FEATURES The assembly syntax of the PWRSAV instruction is shown in Example10-1. Note: This data sheet summarizes the features of Note: SLEEP_MODE and IDLE_MODE are con- this group of PIC24F devices. It is not stants, defined in the assembler include intended to be a comprehensive reference file, for the selected device. source. For more information, refer to the “PIC24F Family Reference Manual”, Sleep and Idle modes can be exited as a result of an ”Section 39. Power-Saving Features enabled interrupt, WDT time-out or a device Reset. with Deep Sleep” (DS39727). When the device exits these modes, it is said to “wake-up”. The PIC24F16KA102 family of devices provides the ability to manage power consumption by selectively 10.2.1 SLEEP MODE managing clocking to the CPU and the peripherals. In Sleep mode includes these features: general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower • The system clock source is shut down. If an consumed power. All PIC24F devices manage power on-chip oscillator is used, it is turned off. consumption in four different ways: • The device current consumption will be reduced • Clock frequency to a minimum provided that no I/O pin is sourcing current. • Instruction-based Sleep, Idle and Deep Sleep modes • The I/O pin directions and states are frozen. • Software controlled Doze mode • The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source • Selective peripheral control in software is disabled. Combinations of these methods can be used to • The LPRC clock will continue to run in Sleep selectively tailor an application’s power consumption, mode if the WDT or RTCC, with LPRC as the while still maintaining critical application features, such clock source, is enabled. as timing-sensitive communications. • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. 10.1 Clock Frequency and Clock • Some device features or peripherals may Switching continue to operate in Sleep mode. This includes PIC24F devices allow for a wide range of clock items, such as the input change notification on the frequencies to be selected under application control. If I/O ports, or peripherals that use an external clock the system clock configuration is not locked, users can input. Any peripheral that requires the system choose low-power or high-precision oscillators by simply clock source for its operation will be disabled in changing the NOSC bits. The process of changing a Sleep mode. system clock during operation, as well as limitations to The device will wake-up from Sleep mode on any of the process, are discussed in more detail in Section9.0 these events: “Oscillator Configuration”. • On any interrupt source that is individually enabled 10.2 Instruction-Based Power-Saving • On any form of device Reset Modes • On a WDT time-out PIC24F devices have two special power-saving modes On wake-up from Sleep, the processor will restart with that are entered through the execution of a special the same clock source that was active when Sleep PWRSAV instruction. Sleep mode stops clock operation mode was entered. and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. Deep Sleep mode stops clock operation, code execution and all peripherals except RTCC and DSWDT. It also freezes I/O states and removes power to SRAM and Flash memory. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode BSET DSCON, #DSEN ; Enable Deep Sleep PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode  2008-2011 Microchip Technology Inc. DS39927C-page 101

PIC24F16KA102 FAMILY 10.2.2 IDLE MODE The device has a dedicated Deep Sleep Brown-out Reset (DSBOR) and a Deep Sleep Watchdog Timer Idle mode has these features: Reset (DSWDT) for monitoring voltage and time-out • The CPU will stop executing instructions. events. The DSBOR and DSWDT are independent of • The WDT is automatically cleared. the standard BOR and WDT used with other • The system clock source remains active. By power-managed modes (Sleep, Idle and Doze). default, all peripheral modules continue to operate 10.2.4.1 Entering Deep Sleep Mode normally from the system clock source, but can also be selectively disabled (see Section10.4 Deep Sleep mode is entered by setting the DSEN bit in “Selective Peripheral Module Control”). the DSCON register, and then executing a Sleep • If the WDT or FSCM is enabled, the LPRC will command (PWRSAV #SLEEP_MODE), within one also remain active. instruction cycle, to minimize the chance that Deep Sleep will be spuriously entered. The device will wake from Idle mode on any of these events: If the PWRSAV command is not given within one instruc- tion cycle, the DSEN bit will be cleared by the hardware • Any interrupt that is individually enabled and must be set again by the software before entering • Any device Reset Deep Sleep mode. The DSEN bit is also automatically • A WDT time-out cleared when exiting the Deep Sleep mode. On wake-up from Idle, the clock is re-applied to the Note: To re-enter Deep Sleep after a Deep Sleep CPU and instruction execution begins immediately, wake-up, allow a delay of at least 3 TCY starting with the instruction following the PWRSAV after clearing the RELEASE bit. instruction or the first instruction in the ISR. The sequence to enter Deep Sleep mode is: 10.2.3 INTERRUPTS COINCIDENT WITH 1. If the application requires the Deep Sleep WDT, POWER SAVE INSTRUCTIONS enable it and configure its clock source(see Any interrupt that coincides with the execution of a Section10.2.4.5 “Deep Sleep WDT” for PWRSAV instruction will be held off until entry into Sleep details). or Idle mode has completed. The device will then 2. If the application requires Deep Sleep BOR, wake-up from Sleep or Idle mode. enable it by programming the DSBOREN Configuration bit (FDS<6>). 10.2.4 DEEP SLEEP MODE 3. If the application requires wake-up from Deep In PIC24F16KA102 family devices, Deep Sleep mode Sleep on RTCC alarm, enable and configure the is intended to provide the lowest levels of power con- RTCC module (see Section19.0 “Real-Time sumption available without requiring the use of external Clock and Calendar (RTCC)” for more switches to completely remove all power from the information). device. Entry into Deep Sleep mode is completely 4. If needed, save any critical application context under software control. Exit from Deep Sleep mode can data by writing it to the DSGPR0 and DSGPR1 be triggered from any of the following events: registers (optional). • POR event 5. Enable Deep Sleep mode by setting the DSEN • MCLR event bit (DSCON<15>). • RTCC alarm (If the RTCC is present) 6. Enter Deep Sleep mode by issuing 3 NOP • External Interrupt 0 commands, and then a PWRSAV #0 instruction. • Deep Sleep Watchdog Timer (DSWDT) time-out Any time the DSEN bit is set, all bits in the DSWAKE In Deep Sleep mode, it is possible to keep the device register will be automatically cleared. Real-Time Clock and Calendar (RTCC) running without the loss of clock cycles. DS39927C-page 102  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 10.2.4.2 Exiting Deep Sleep Mode Applications which require critical data to be saved prior to Deep Sleep may use the Deep Sleep General Deep Sleep mode exits on any one of the following events: Purpose registers, DSGPR0 and DSGPR1, or data • POR event on VDD supply. If there is no DSBOR EEPROM (if available). Unlike other SFRs, the circuit to re-arm the VDD supply POR circuit, the contents of these registers are preserved while the external VDD supply must be lowered to the device is in Deep Sleep mode. After exiting Deep natural arming voltage of the POR circuit. Sleep, software can restore the data by reading the • DSWDT time-out. When the DSWDT timer times registers and clearing the RELEASE bit (DSCON<0>). out, the device exits Deep Sleep. • RTCC alarm (if RTCEN = 1). 10.2.4.4 I/O Pins During Deep Sleep • Assertion (‘0’) of the MCLR pin. During Deep Sleep, the general purpose I/O pins retain • Assertion of the INT0 pin (if the interrupt was their previous states and the Secondary Oscillator enabled before Deep Sleep mode was entered). (SOSC) will remain running, if enabled. Pins that are The polarity configuration is used to determine the configured as inputs (TRISx bit set), prior to entry into assertion level (‘0’ or ‘1’) of the pin that will cause Deep Sleep, remain high-impedance during Deep an exit from Deep Sleep mode. Exiting from Deep Sleep. Pins that are configured as outputs (TRISx bit Sleep mode requires a change on the INT0 pin clear), prior to entry into Deep Sleep, remain as output while in Deep Sleep mode. pins during Deep Sleep. While in this mode, they con- tinue to drive the output level determined by their Note: Any interrupt pending when entering corresponding LATx bit at the time of entry into Deep Deep Sleep mode is cleared, Sleep. Exiting Deep Sleep mode generally does not retain the Once the device wakes back up, all I/O pins continue to state of the device and is equivalent to a Power-on maintain their previous states, even after the device Reset (POR) of the device. Exceptions to this include has finished the POR sequence and is executing appli- the RTCC (if present), which remains operational cation code again. Pins configured as inputs during through the wake-up, the DSGPRx registers and the Deep Sleep remain high-impedance and pins config- DSWDT bit. ured as outputs continue to drive their previous value. Wake-up events that occur from the time Deep Sleep After waking up, the TRIS and LAT registers, and the exits until the time the POR sequence completes are SOSCEN bit (OSCCON<1>) are reset. If firmware ignored and are not be captured in the DSWAKE modifies any of these bits or registers, the I/O will not register. immediately go to the newly configured states. Once The sequence for exiting Deep Sleep mode is: the firmware clears the RELEASE bit (DSCON<0>), the I/O pins are “released”. This causes the I/O pins to 1. After a wake-up event, the device exits Deep take the states configured by their respective TRIS and Sleep and performs a POR. The DSEN bit is LAT bit values. cleared automatically. Code execution resumes at the Reset vector. This means that keeping the SOSC running after waking up requires the SOSCEN bit to be set before 2. To determine if the device exited Deep Sleep, clearing RELEASE. read the Deep Sleep bit, DPSLP (RCON<10>). This bit will be set if there was an exit from Deep If the Deep Sleep BOR (DSBOR) is enabled, and a Sleep mode; if the bit is set, clear it. DSBOR or a true POR event occurs during Deep 3. Determine the wake-up source by reading the Sleep, the I/O pins will be immediately released, similar DSWAKE register. to clearing the RELEASE bit. All previous state infor- mation will be lost, including the general purpose 4. Determine if a DSBOR event occurred during DSGPR0 and DSGPR1 contents. Deep Sleep mode by reading the DSBOR bit (DSCON<1>). If a MCLR Reset event occurs during Deep Sleep, the 5. If application context data has been saved, read DSGPRx, DSCON and DSWAKE registers will remain it back from the DSGPR0 and DSGPR1 valid, and the RELEASE bit will remain set. The state registers. of the SOSC will also be retained. The I/O pins, how- ever, will be reset to their MCLR Reset state. Since 6. Clear the RELEASE bit (DSCON<0>). RELEASE is still set, changes to the SOSCEN bit 10.2.4.3 Saving Context Data with the (OSCCON<1>) cannot take effect until the RELEASE bit is cleared. DSGPR0/DSGPR1 Registers In all other Deep Sleep wake-up cases, application As exiting Deep Sleep mode causes a POR, most firmware must clear the RELEASE bit in order to Special Function Registers reset to their default POR reconfigure the I/O pins. values. In addition, because VDDCORE power is not supplied in Deep Sleep mode, information in data RAM may be lost when exiting this mode.  2008-2011 Microchip Technology Inc. DS39927C-page 103

PIC24F16KA102 FAMILY 10.2.4.5 Deep Sleep WDT 10.2.4.8 Power-on Resets (PORs) To enable the DSWDT in Deep Sleep mode, program VDD voltage is monitored to produce PORs. Since exit- the Configuration bit, DSWDTEN (FDS<7>). The ing from Deep Sleep functionally looks like a POR, the device Watchdog Timer (WDT) need not be enabled for technique described in Section10.2.4.7 “Checking the DSWDT to function. Entry into Deep Sleep mode and Clearing the Status of Deep Sleep” should be automatically resets the DSWDT. used to distinguish between Deep Sleep and a true POR event. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (FDS<4>). The post- When a true POR occurs, the entire device, including scaler options are programmed by the all Deep Sleep logic (Deep Sleep registers, RTCC, DSWDTPS<3:0> Configuration bits (FDS<3:0>). The DSWDT, etc.) is reset. minimum time-out period that can be achieved is 2.1ms and the maximum is 25.7days. For more 10.2.4.9 Summary of Deep Sleep Sequence details on the FDS Configuration register and DSWDT To review, these are the necessary steps involved in configuration options, refer to Section26.0 “Special invoking and exiting Deep Sleep mode: Features”. 1. Device exits Reset and begins to execute its 10.2.4.6 Switching Clocks in Deep Sleep Mode application code. 2. If DSWDT functionality is required, program the Both the RTCC and the DSWDT may run from either appropriate Configuration bit. SOSC or the LPRC clock source. This allows both the 3. Select the appropriate clock(s) for the DSWDT RTCC and DSWDT to run without requiring both the and RTCC (optional). LPRC and SOSC to be enabled together, reducing power consumption. 4. Enable and configure the DSWDT (optional). 5. Enable and configure the RTCC (optional). Running the RTCC from LPRC will result in a loss of accuracy in the RTCC of approximately 5 to 10%. If a 6. Write context data to the DSGPRx registers more accurate RTCC is required, it must be run from the (optional). SOSC clock source. The RTCC clock source is selected 7. Enable the INT0 interrupt (optional). with the RTCOSC Configuration bit (FDS<5>). 8. Set the DSEN bit in the DSCON register. Under certain circumstances, it is possible for the 9. Enter Deep Sleep by issuing a PWRSV DSWDT clock source to be off when entering Deep #SLEEP_MODE command. Sleep mode. In this case, the clock source is turned on 10. Device exits Deep Sleep when a wake-up event automatically (if DSWDT is enabled), without the need occurs. for software intervention. However, this can cause a 11. The DSEN bit is automatically cleared. delay in the start of the DSWDT counters. In order to 12. Read and clear the DPSLP status bit in RCON, avoid this delay when using SOSC as a clock source, and the DSWAKE status bits. the application can activate SOSC prior to entering Deep Sleep mode. 13. Read the DSGPRx registers (optional). 14. Once all state related configurations are 10.2.4.7 Checking and Clearing the Status of complete, clear the RELEASE bit. Deep Sleep 15. Application resumes normal operation. Upon entry into Deep Sleep mode, the status bit DPSLP (RCON<10>), becomes set and must be cleared by software. On power-up, the software should read this status bit to determine if the Reset was due to an exit from Deep Sleep mode and clear the bit if it is set. Of the four possible combinations of DPSLP and POR bit states, three cases can be considered: • Both the DPSLP and POR bits are cleared. In this case, the Reset was due to some event other than a Deep Sleep mode exit. • The DPSLP bit is clear, but the POR bit is set. This is a normal POR. • Both the DPSLP and POR bits are set. This means that Deep Sleep mode was entered, the device was powered down and Deep Sleep mode was exited. DS39927C-page 104  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER(1) R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DSEN — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/C-0, HS — — — — — — DSBOR(2) RELEASE bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DSEN: Deep Sleep Enable bit 1 = Enters Deep Sleep on execution of PWRSAV #0 0 = Enters normal Sleep on execution of PWRSAV #0 bit 14-2 Unimplemented: Read as ‘0’ bit 1 DSBOR: Deep Sleep BOR Event bit(2) 1 = The DSBOR was active and a BOR event was detected during Deep Sleep 0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep bit 0 RELEASE: I/O Pin State Release bit 1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry 0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and LAT bits to control their states Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode. 2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this re-arms POR.  2008-2011 Microchip Technology Inc. DS39927C-page 105

PIC24F16KA102 FAMILY REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS DSFLT — — DSWDT DSRTCC DSMCLR — DSPOR(2,3) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DSINT0: Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep bit 7 DSFLT: Deep Sleep Fault Detected bit 1 = A Fault occurred during Deep Sleep, and some Deep Sleep configuration settings may have been corrupted 0 = No Fault was detected during Deep Sleep bit 6-5 Unimplemented: Read as ‘0’ bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep bit 3 DSRTCC: Real-Time Clock and Calendar Alarm bit 1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep bit 2 DSMCLR: MCLR Event bit 1 = The MCLR pin was active and was asserted during Deep Sleep 0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep bit 1 Unimplemented: Read as ‘0’ bit 0 DSPOR: Power-on Reset Event bit(2,3) 1 = The VDD supply POR circuit was active and a POR event was detected 0 = The VDD supply POR circuit was not active, or was active but did not detect a POR event Note 1: All register bits are cleared when the DSCON<DSEN> bit is set. 2: All register bits are reset only in the case of a POR event outside Deep Sleep mode, except bit, DSPOR, which does not reset on a POR event that is caused due to a Deep Sleep exit. 3: Unlike the other bits in this register, this bit can be set outside of Deep Sleep. DS39927C-page 106  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 10.3 Doze Mode 10.4 Selective Peripheral Module Control Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies Idle and Doze modes allow users to substantially for reducing power consumption. There may be reduce power consumption by slowing or stopping the circumstances, however, where this is not practical. For CPU clock. Even so, peripheral modules still remain example, it may be necessary for an application to clocked, and thus, consume power. There may be maintain uninterrupted synchronous communication, cases where the application needs what these modes even while it is doing nothing else. Reducing system do not provide: the allocation of power resources to clock speed may introduce communication errors, CPU processing with minimal power consumption from while using a power-saving mode may stop the peripherals. communications completely. PIC24F devices address this requirement by allowing Doze mode is a simple and effective alternative method peripheral modules to be selectively disabled, reducing to reduce power consumption while the device is still or eliminating their power consumption. This can be executing code. In this mode, the system clock done with two control bits: continues to operate from the same source and at the • The Peripheral Enable bit, generically named, same speed. Peripheral modules continue to be “XXXEN”, located in the module’s main control clocked at the same speed while the CPU clock speed SFR. is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to • The Peripheral Module Disable (PMD) bit, access the SFRs while the CPU executes code at a generically named, “XXXMD”, located in one of slower rate. the PMD Control registers. Doze mode is enabled by setting the DOZEN bit Both bits have similar functions in enabling or disabling (CLKDIV<11>). The ratio between peripheral and core its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible power consumption to an absolute minimum. In this state, the control and status registers associated with configurations, from 1:1 to 1:128, with 1:1 being the default. the peripheral will also be disabled, so writes to those registers will have no effect and read values will be It is also possible to use Doze mode to selectively reduce invalid. Many peripheral modules have a corresponding power consumption in event driven applications. This PMD bit. allows clock-sensitive functions, such as synchronous In contrast, disabling a module by clearing its XXXEN communications, to continue without interruption while the CPU Idles, waiting for something to invoke an bit disables its functionality, but leaves its registers available to be read and written to. Power consumption interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by set- is reduced, but not by as much as the PMD bits are used. Most peripheral modules have an enable bit; ting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. exceptions include capture, compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, “XXXIDL”. By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature disables the module while in Idle mode, allowing further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.  2008-2011 Microchip Technology Inc. DS39927C-page 107

PIC24F16KA102 FAMILY REGISTER 10-3: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — T3MD T2MD T1MD — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 I2C1MD U2MD U1MD — SPI1MD — — ADC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled. All Timer3 registers are held in Reset and are not writable. 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled. All Timer2 registers are held in Reset and are not writable. 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled. All Timer1 registers are held in Reset and are not writable. 0 = Timer1 module is enabled bit 10-8 Unimplemented: Read as ‘0’ bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled. All I2C1 registers are held in Reset and are not writable. 0 = I2C1 module is enabled bit 6 U2MD: UART2 Module Disable bit 1 = UART2 module is disabled. All UART2 registers are held in Reset and are not writable. 0 = UART2 module is enabled bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled. All UART1 registers are held in Reset and are not writable. 0 = UART1 module is enabled bit 4 Unimplemented: Read as ‘0’ bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled. All SPI1 registers are held in Reset and are not writable. 0 = SPI1 module is enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 ADC1MD: A/D Module Disable bit 1 = A/D module is disabled. All A/D registers are held in Reset and are not writable. 0 = A/D module is enabled DS39927C-page 108  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 10-4: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — I2C1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 I2C1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled. All Input Capture registers are held in Reset and are not writable. 0 = Input Capture 1 module is writable bit 7-1 Unimplemented: Read as ‘0’ bit 0 OC1MD: Input Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled. All Output Compare registers are held in Reset and are not writable. 0 = Output Compare 1 module is writable  2008-2011 Microchip Technology Inc. DS39927C-page 109

PIC24F16KA102 FAMILY REGISTER 10-5: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — CMPMD RTCCMD — bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 CRCMD — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Comparator Module Disable bit 1 = Comparator module is disabled. All Comparator Module registers are held in Reset and are not writable. 0 = Comparator module is enabled bit 9 RTCCMD: RTCC Module Disable bit 1 = RTCC module is disabled. All RTCC module registers are held in Reset and are not writable. 0 = RTCC module is enabled bit 8 Unimplemented: Read as ‘0’ bit 7 CRCMD: CRC Module Disable bit 1 = CRC module is disabled. All CRC registers are held in Reset and are not writable. 0 = CRC module is enabled bit 6-0 Unimplemented: Read as ‘0’ DS39927C-page 110  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 10-6: PMD4: PERIPHERAL MODULE DISABLE REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — EEMD REFOMD CTMUMD HLVDMD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 EEMD: EEPROM Memory Module Disable bit 1 = Disable EEPROM memory Flash panel, minimizing current consumption 0 = EEPROM memory is disabled bit 3 REFOMD: Reference Oscillator Module Disable bit 1 = Reference oscillator module is disabled. All Reference Oscillator registers are held in Reset and are not writable 0 = Reference Oscillator module is enabled bit 2 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled. All CTMU registers are held in Reset and are not writable. 0 = CTMU module is enabled bit 1 HLVDMD: HLVD Module Disable bit 1 = HLVD module is disabled. All HLVD registers are held in Reset and are not writable. 0 = HLVD module is enabled bit 0 Unimplemented: Read as ‘0’  2008-2011 Microchip Technology Inc. DS39927C-page 111

PIC24F16KA102 FAMILY NOTES: DS39927C-page 112  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 11.0 I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as Note: This data sheet summarizes the features of a general purpose output pin is disabled. The I/O pin this group of PIC24F devices. It is not may be read, but the output driver for the parallel port intended to be a comprehensive reference bit will be disabled. If a peripheral is enabled, but the source. For more information on the I/O peripheral is not actively driving a pin, that pin may be ports, refer to the “PIC24F Family Refer- driven by a port. ence Manual”, Section 12. “I/O Ports with All port pins have three registers directly associated Peripheral Pin Select (PPS)” (DS39711). with their operation as digital I/O. The Data Direction Note that the PIC24F16KA102 family register (TRISx) determines whether the pin is an input devices do not support Peripheral Pin or an output. If the data direction bit is a ‘1’, then the pin Select features. is an input. All port pins are defined as inputs after a Reset. Reads from the Data Latch register (LATx), read All of the device pins (except VDD and VSS) are shared the latch. Writes to the latch, write the latch. Reads between the peripherals and the parallel I/O ports. All from the port (PORTx), read the port pins, while writes I/O input ports feature Schmitt Trigger inputs for to the port pins, write the latch. improved noise immunity. Any bit and its associated data and control registers 11.1 Parallel I/O (PIO) Ports that are not valid for a particular device will be disabled. That means the corresponding LATx and A parallel I/O port that shares a pin with a peripheral is, TRISx registers, and the port pin will read as zeros. in general, subservient to the peripheral. The When a pin is shared with another peripheral or peripheral’s output buffer data and control signals are function that is defined as an input only, it is provided to a pair of multiplexers. The multiplexers nevertheless regarded as a dedicated port because select whether the peripheral or the associated port there is no other competing source of outputs. has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in Note: The I/O pins retain their state during Deep which a port’s digital output can drive the input of a Sleep. They will retain this state at peripheral that shares the same pin. Figure11-1 wake-up until the software restore bit displays how ports are shared with other peripherals (RELEASE) is cleared. and the associated I/O pin to which they are connected. FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + CK WR PORT Data Latch Read LAT Input Data Read PORT  2008-2011 Microchip Technology Inc. DS39927C-page 113

PIC24F16KA102 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION clocks are disabled. Depending on the device pin count, there are up to 23 external signals (CN0 through In addition to the PORT, LAT and TRIS registers for CN22) that may be selected (enabled) for generating data control, each port pin can also be individually an interrupt request on a Change-of-State. configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, There are six control registers associated with the CN associated with each port. Setting any of the bits module. The CNEN1 and CNEN2 registers contain the configures the corresponding pin to act as an interrupt enable control bits for each of the CN input open-drain output. pins. Setting any of these bits enables a CN interrupt for the corresponding pins. The maximum open-drain voltage allowed is the same as the maximum VIH specification. Each CN pin also has a weak pull-up/pull-down connected to it. The pull-ups act as a current source 11.2 Configuring Analog Port Pins that is connected to the pin and the pull-downs act as a current sink to eliminate the need for external resistors The use of the AD1PCFG and TRIS register controls when push button or keypad devices are connected. the operation of the A/D port pins. The port pins that are On any pin, only the pull-up resistor or the pull-down desired as analog inputs must have their resistor should be enabled, but not both of them. If the corresponding TRIS bit set (input). If the TRIS bit is push button or the keypad is connected to VDD, enable cleared (output), the digital output level (VOH or VOL) the pull-down, or if they are connected to VSS, enable will be converted. the pull-up resistors. The pull-ups are enabled When reading the PORT register, all pins configured as separately using the CNPU1 and CNPU2 registers, analog input channels will read as cleared (a low level). which contain the control bits for each of the CN pins. Analog levels on any pin that is defined as a digital Setting any of the control bits enables the weak input (including the ANx pins) may cause the input pull-ups for the corresponding pins. The pull-downs are buffer to consume current that exceeds the device enabled separately using the CNPD1 and CNPD2 specifications. registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the 11.2.1 I/O PORT WRITE/READ TIMING weak pull-downs for the corresponding pins. One instruction cycle is required between a port When the internal pull-up is selected, the pin uses VDD direction change or port write operation and a read as the pull-up source voltage. When the internal operation of the same port. Typically, this instruction pull-down is selected, the pins are pulled down to VSS would be a NOP. by an internal resistor. Make sure that there is no external pull-up source/pull-down sink when the 11.3 Input Change Notification internal pull-ups/pull-downs are enabled. The input change notification function of the I/O ports Note: Pull-ups and pull-downs on change allows the PIC24F16KA102 family of devices to notification pins should always be generate interrupt requests to the processor in disabled whenever the port pin is response to a Change-of-State (COS) on selected configured as a digital output. input pins. This feature is capable of detecting input Change-of-States even in Sleep mode, when the EXAMPLE 11-1: PORT WRITE/READ EXAMPLE MOV 0xFF00, W0; //Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs MOV W0, TRISBB; NOP; //Delay 1 cycle BTSS PORTB, #13; //Next Instruction Equivalent ‘C’ Code TRISB = 0xFF00; //Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs NOP(); //Delay 1 cycle if(PORTBbits.RB13 == 1) // execute following code if PORTB pin 13 is set. { } DS39927C-page 114  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 12.0 TIMER1 Figure12-1 presents a block diagram of the 16-bit Timer1 module. Note: This data sheet summarizes the features To configure Timer1 for operation: of this group of PIC24F devices. It is not intended to be a comprehensive refer- 1. Set the TON bit (= 1). ence source. For more information on 2. Select the timer prescaler ratio using the Timers, refer to the “PIC24F Family Refer- TCKPS<1:0> bits. ence Manual”, Section 14. “Timers” 3. Set the Clock and Gating modes using the TCS (DS39704). and TGATE bits. 4. Set or clear the TSYNC bit to configure The Timer1 module is a 16-bit timer which can serve as synchronous or asynchronous operation. the time counter for the Real-Time Clock (RTC), or operate as a free-running, interval timer/counter. Timer1 5. Load the timer period value into the PR1 can operate in three modes: register. 6. If interrupts are required, set the interrupt enable • 16-Bit Timer bit, T1IE. Use the priority bits, T1IP<2:0>, to set • 16-Bit Synchronous Counter the interrupt priority. • 16-Bit Asynchronous Counter Timer1 also supports these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation During CPU Idle and Sleep modes • Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS<1:0> TON 2 SOSCO/ 1x T1CK Gate Prescaler SOSCEN Sync 01 1, 8, 64, 256 SOSCI TCY 00 TGATE TGATE TCS 1 Q D Set T1IF 0 Q CK 0 Reset TMR1 1 Sync Comparator TSYNC Equal PR1  2008-2011 Microchip Technology Inc. DS39927C-page 115

PIC24F16KA102 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ DS39927C-page 116  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 13.0 TIMER2/3 To configure Timer2/3 for 32-bit operation: 1. Set the T32 bit (T2CON<3> = 1). Note: This data sheet summarizes the features 2. Select the prescaler ratio for Timer2 using the of this group of PIC24F devices. It is not TCKPS<1:0> bits. intended to be a comprehensive refer- 3. Set the Clock and Gating modes using the TCS ence source. For more information on and TGATE bits. Timers, refer to the “PIC24F Family Refer- ence Manual”, Section 14. “Timers” 4. Load the timer period value. PR3 will contain the (DS39704). msw of the value while PR2 contains the lsw. 5. If interrupts are required, set the interrupt enable The Timer2/3 module is a 32-bit timer, which can also be bit, T3IE. Use the priority bits, T3IP<2:0>, to set configured as two independent 16-bit timers with the interrupt priority. selectable operating modes. While Timer2 controls the timer, the interrupt As a 32-bit timer, Timer2/3 operates in three modes: appears as a Timer3 interrupt. • Two independent 16-bit timers (Timer2 and 6. Set the TON bit (= 1). Timer3) with all 16-bit operating modes (except Asynchronous Counter mode) The timer value, at any point, is stored in the register • Single 32-bit timer pair, TMR<3:2>. TMR3 always contains the msw of the count, while TMR2 contains the lsw. • Single 32-bit synchronous counter To configure any of the timers for individual 16-bit They also support these features: operation: • Timer gate operation 1. Clear the T32 bit in T2CON<3>. • Selectable prescaler settings 2. Select the timer prescaler ratio using the • Timer operation during Idle and Sleep modes TCKPS<1:0> bits. • Interrupt on a 32-bit Period register match 3. Set the Clock and Gating modes using the TCS • A/D Event Trigger and TGATE bits. Individually, both of the 16-bit timers can function as 4. Load the timer period value into the PRx register. synchronous timers or counters. They also offer the 5. If interrupts are required, set the interrupt enable features listed above, except for the A/D event trigger bit, TxIE; use the priority bits, TxIP<2:0>, to set (this is implemented only with Timer3). The operating the interrupt priority. modes and enabled features are determined by setting 6. Set the TON bit (TxCON<15> = 1). the appropriate bit(s) in the T2CON and T3CON registers. T2CON and T3CON are provided in generic form in Register13-1 and Register13-2, respectively. For 32-bit timer/counter operation, Timer2 is the least significant word (lsw) and Timer3 is the most significant word (msw) of the 32-bit timer. Note: For 32-bit operation, T3CON control bits are ignored. Only T2CON control bits are used for setup and control. Timer2 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags.  2008-2011 Microchip Technology Inc. DS39927C-page 117

PIC24F16KA102 FAMILY FIGURE 13-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> TON 2 T2CK 1x Gate Prescaler Sync 01 1, 8, 64, 256 TCY 00 TGATE TGATE TCS 1 Q D Set T3IF Q CK 0 PR3 PR2 A/D Event Trigger Equal Comparator MSB LSB TMR3 TMR2 Sync Reset 16 Read TMR2(1) Write TMR2(1) 16 16 TMR3HLD 16 Data Bus<15:0> Note 1: The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS39927C-page 118  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY FIGURE 13-2: TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TCKPS<1:0> TON 2 T2CK 1x Gate Prescaler Sync 01 1, 8, 64, 256 TGATE 00 TCS TCY 1 Q D TGATE Set T2IF Q CK 0 Reset TMR2 Sync Comparator Equal PR2 FIGURE 13-3: TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TCKPS<1:0> TON 2 T3CK Sync 1x Prescaler 01 1, 8, 64, 256 TGATE 00 TCY TCS 1 Q D TGATE Set T3IF Q CK 0 Reset TMR3 A/D Event Trigger Comparator Equal PR3  2008-2011 Microchip Technology Inc. DS39927C-page 119

PIC24F16KA102 FAMILY REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer2 On bit When T2CON<3> = 1: 1 = Starts 32-bit Timer2/3 0 = Stops 32-bit Timer2/3 When T2CON<3> = 0: 1 = Starts 16-bit Timer2 0 = Stops 16-bit Timer2 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer2 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer2 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit(1) 1 = Timer2 and Timer3 form a single 32-bit timer 0 = Timer2 and Timer3 act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer2 Clock Source Select bit 1 = External clock from pin, T2CK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: In 32-bit mode, the T3CON control bits do not affect 32-bit timer operation. DS39927C-page 120  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 13-2: T3CON: TIMER3 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer3 On bit(1) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer3 Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer3 Clock Source Select bit(1) 1 = External clock from the T3CK pin (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON.  2008-2011 Microchip Technology Inc. DS39927C-page 121

PIC24F16KA102 FAMILY NOTES: DS39927C-page 122  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 14.0 INPUT CAPTURE The PIC24F16KA102 family devices have one input capture channel. The input capture module has Note: This data sheet summarizes the features multiple operating modes, which are selected via the of this group of PIC24F devices. It is not IC1CON register. The operating modes include: intended to be a comprehensive • Capture timer value on every falling edge of input reference source. For more information applied at the IC1 pin on Input Capture, refer to the “PIC24F • Capture timer value on every rising edge of input Family Reference Manual”, Section 15. applied at the IC1 pin “Input Capture” (DS39701). • Capture timer value on every 4th rising edge of The input capture module is used to capture a timer input applied at the IC1 pin value from one of two selectable time bases upon an • Capture timer value on every 16th rising edge of event on an input pin. input applied at the IC1 pin The input capture features are quite useful in • Capture timer value on every rising and every applications requiring frequency (Time Period) and falling edge of input applied at the IC1 pin pulse measurement. Figure14-1 depicts a simplified • Device wake-up from capture pin during CPU block diagram of the input capture module. Sleep and Idle modes The input capture module has a four-level FIFO buffer. The number of capture events required to generate a CPU interrupt can be selected by the user. FIGURE 14-1: INPUT CAPTURE BLOCK DIAGRAM From 16-Bit Timers TMRy TMRx 16 16 1 0 ICTMR (IC1CON<7>) Prescaler Edge Detection Logic FIFO Counter R/W (1, 4, 16) Clock Synchronizer Logic IC1 Pin 3 ICM<2:0> (IC1CON<2:0>) Mode Select ICOV, ICBNE (IC1CON<4:3>) IC1BUF ICI<1:0> Interrupt IC1CON Logic System Bus Set Flag IC1IF (in IFSn Register)  2008-2011 Microchip Technology Inc. DS39927C-page 123

PIC24F16KA102 FAMILY 14.1 Input Capture Registers REGISTER 14-1: IC1CON: INPUT CAPTURE 1 CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture 1 Module Stop in Idle Control bit 1 = Input capture module will halt in CPU Idle mode 0 = Input capture module will continue to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture 1 Timer Select bit 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture 1 Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture 1 Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture 1 Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module is disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling) – ICI<1:0> bits do not control interrupt generation for this mode 000 = Input capture module is turned off DS39927C-page 124  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 15.0 OUTPUT COMPARE 10. To initiate another single pulse output, change the Timer and Compare register settings, if Note: This data sheet summarizes the features needed, and then issue a write to set the OCM of this group of PIC24F devices. It is not bits to ‘100’. Disabling and re-enabling of the intended to be a comprehensive refer- timer and clearing the TMRy register are not ence source. For more information on required, but may be advantageous for defining Output Compare, refer to the “PIC24F a pulse from a known event time boundary. Family Reference Manual”, Section 16. The output compare module does not have to be “Output Compare” (DS39706). disabled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of 15.1 Setup for Single Output Pulse the OC1CON register. Generation 15.2 Setup for Continuous Output When the OCM control bits (OC1CON<2:0>) are set to Pulse Generation ‘100’, the selected output compare channel initializes the OC1 pin to the low state and generates a single When the OCM control bits (OC1CON<2:0>) are set to output pulse. ‘101’, the selected output compare channel initializes To generate a single output pulse, the following steps the OC1 pin to the low state and generates output are required (these steps assume the timer source is pulses on each and every compare match event. initially turned off, but this is not a requirement for the For the user to configure the module for the generation module operation): of a continuous stream of output pulses, the following 1. Determine the instruction clock cycle time. Take steps are required (these steps assume the timer into account the frequency of the external clock source is initially turned off, but this is not a requirement to the timer source (if one is used) and the timer for the module operation): prescaler settings. 1. Determine the instruction clock cycle time. Take 2. Calculate time to the rising edge of the output into account the frequency of the external clock pulse relative to the TMRy start value (0000h). to the timer source (if one is used) and the timer 3. Calculate the time to the falling edge of the pulse prescaler settings. based on the desired pulse width and the time to 2. Calculate time to the rising edge of the output the rising edge of the pulse. pulse relative to the TMRy start value (0000h). 4. Write the values computed in Steps 2 and 3 3. Calculate the time to the falling edge of the pulse above into the Output Compare 1 register, based on the desired pulse width and the time to OC1R, and the Output Compare 1 Secondary the rising edge of the pulse. register, OC1RS, respectively. 4. Write the values computed in Step 2 and 3 above 5. Set Timer Period register, PRy, to value equal to into the Output Compare 1 register, OC1R, and the or greater than the value in OC1RS, the Output Output Compare 1 Secondary register, OC1RS, Compare 1 Secondary register. respectively. 6. Set the OCM bits to ‘100’ and the OCTSEL 5. Set the Timer Period register, PRy, to a value (OC1CON<3>) bit to the desired timer source. equal to or greater than the value in OC1RS. The OC1 pin state will now be driven low. 6. Set the OCM bits to ‘101’ and the OCTSEL bit to 7. Set the TON (TyCON<15>) bit to ‘1’, which the desired timer source. The OC1 pin state will enables the compare time base to count. now be driven low. 8. Upon the first match between TMRy and OC1R, 7. Enable the compare time base by setting the the OC1 pin will be driven high. TON (TyCON<15>) bit to ‘1’. 9. When the incrementing timer, TMRy, matches 8. Upon the first match between TMRy and OC1R, the Output Compare 1 Secondary register, the OC1 pin will be driven high. OC1RS, the second and trailing edge 9. When the compare time base, TMRy, matches the (high-to-low) of the pulse is driven onto the OC1 OC1RS, the second and trailing edge (high-to-low) pin. No additional pulses are driven onto the of the pulse is driven onto the OC1 pin. OC1 pin and it remains low. As a result of the 10. As a result of the second compare match event, second compare match event, the OC1IF inter- the OC1IF interrupt flag bit is set. rupt flag bit is set, which will result in an interrupt 11. When the compare time base and the value in its if it is enabled, by setting the OC1IE bit. For respective Timer Period register match, the TMRy further information on peripheral interrupts, refer register resets to 0x0000 and resumes counting. to Section8.0 “Interrupt Controller”. 12. Steps 8 through 11 are repeated and a continu- ous stream of pulses is generated indefinitely. The OC1IF flag is set on each OC1RS/TMRy compare match event.  2008-2011 Microchip Technology Inc. DS39927C-page 125

PIC24F16KA102 FAMILY 15.3 Pulse-Width Modulation (PWM) EQUATION 15-1: CALCULATING THE PWM Mode PERIOD(1) PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value) The following steps should be taken when configuring where: the output compare module for PWM operation: PWM Frequency = 1/[PWM Period] 1. Set the PWM period by writing to the selected Note 1: Based on TCY = 2 * TOSC; Doze mode Timer Period register (PRy). and PLL are disabled. 2. Set the PWM duty cycle by writing to the OC1RS register. 3. Write the OC1R register with the initial duty Note: A PRy value of N will produce a PWM cycle. period of N + 1 time base count cycles. For example, a value of 7, written into the PRy 4. Enable interrupts, if required, for the timer and register, will yield a period consisting of output compare modules. The output compare 8time base cycles. interrupt is required for PWM Fault pin utilization. 15.3.2 PWM DUTY CYCLE 5. Configure the output compare module for one of two PWM Operation modes by writing to the The PWM duty cycle is specified by writing to the OC1RS register. The OC1RS register can be written to Output Compare Mode bits, OCM<2:0> at any time, but the duty cycle value is not latched into (OC1CON<2:0>). OC1R until a match between PRy and TMRy occurs 6. Set the TMRy prescale value and enable the (i.e., the period is complete). This provides a double time base by setting TON (TxCON<15>) = 1. buffer for the PWM duty cycle and is essential for Note: The OC1R register should be initialized glitchless PWM operation. In PWM mode, OC1R is a before the output compare module is first read-only register. enabled. The OC1R register becomes a Some important boundary parameters of the PWM duty read-only Duty Cycle register when the cycle include: module is operated in the PWM modes. • If the Output Compare 1 register, OC1R, is loaded The value held in OC1R will become the with 0000h, the OC1 pin will remain low (0% duty PWM duty cycle for the first PWM period. cycle). The contents of the Output Compare 1 Secondary register, OC1RS, will not be • If OC1R is greater than PRy (Timer Period transferred into OC1R until a time base register), the pin will remain high (100% duty period match occurs. cycle). • If OC1R is equal to PRy, the OC1 pin will be low 15.3.1 PWM PERIOD for one time base count value and high for all other count values. The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be See Example15-1 for PWM mode timing details. calculated using Equation15-1. Table15-1 provides an example of PWM frequencies and resolutions for a device operating at 10 MIPS. EQUATION 15-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1) log ( FCY ) 10 FPWM • (Timer Prescale Value) Maximum PWM Resolution (bits) = bits log (2) 10 Note1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. DS39927C-page 126  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY EXAMPLE 15-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) 1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2s PWM Period = (PR2 + 1) • TCY • (Timer 2 Prescale Value) 19.2s = (PR2 + 1) • 62.5 ns • 1 PR2= 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32MHz device clock rate: PWM Resolution=log10(FCY/FPWM)/log102) bits = (log (16 MHz/52.08 kHz)/log 2) bits 10 10 = 8.3 bits Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1) PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh Resolution (bits) 16 16 15 12 10 7 5 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1) PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh Resolution (bits) 16 16 15 12 10 7 5 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.  2008-2011 Microchip Technology Inc. DS39927C-page 127

PIC24F16KA102 FAMILY FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OC1IF(1) OC1RS(1) OC1R(1) OLuotgpicut RS Q OC1(1) Output Enable 3 OCM<2:0> Comparator Mode Select OCFA(2) 0 1 OCTSEL 0 1 16 16 TMR Register Inputs Period Match Signals from Time Bases(3) from Time Bases(3) Note 1: Where ‘x’ is depicted, reference is made to the registers associated with the respective Output Compare Channel 1. 2: OCFA pin controls OC1 channel. 3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time bases associated with the module. DS39927C-page 128  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 15.4 Output Compare Register REGISTER 15-1: OC1CON: OUTPUT COMPARE 1 CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM2 OCM1 OCM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare 1 in Idle Mode Control bit 1 = Output Compare 1 will halt in CPU Idle mode 0 = Output Compare 1 will continue to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) bit 3 OCTSEL: Output Compare 1 Timer Select bit 1 = Timer3 is the clock source for Output Compare 1 0 = Timer2 is the clock source for Output Compare 1 Refer to the device data sheet for specific time bases available to the output compare module. bit 2-0 OCM<2:0>: Output Compare 1 Mode Select bits 111 = PWM mode on OC1, Fault pin; OCF1 enabled(1) 110 = PWM mode on OC1, Fault pin; OCF1 disabled(1) 101 = Initialize OC1 pin low, generate continuous output pulses on OC1 pin 100 = Initialize OC1 pin low, generate single output pulse on OC1 pin 011 = Compare event toggles OC1 pin 010 = Initialize OC1 pin high, compare event forces OC1 pin low 001 = Initialize OC1 pin low, compare event forces OC1 pin high 000 = Output compare channel is disabled Note 1: The OCFA pin controls the OC1 channel.  2008-2011 Microchip Technology Inc. DS39927C-page 129

PIC24F16KA102 FAMILY REGISTER 15-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — SMBUSDEL(3) OC1TRIS(2) RTSECSEL1(1,4) RTSECSEL0(1,4) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 3 OC1TRIS: OC1 Output Tri-State Select bit(2) 1 = OC1 output will not be active on the pin; OCPWM1 can still be used for internal triggers 0 = OC1 output will be active on the pin based on the OCPWM1 module settings bit 0 Unimplemented: Read as ‘0’ Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. 2: To enable the actual OC1 output, the OCPWM1 module has to be enabled. 3: Bit 4 is described in Section17.0 “Inter-Integrated Circuit (I2C™)”. 4: Bits 2 and 1 are described in Section19.0 Real-Time Clock and Calendar (RTCC). DS39927C-page 130  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 16.0 SERIAL PERIPHERAL The devices of the PIC24F16KA102 family offer one INTERFACE (SPI) SPI module on a device. Note: In this section, the SPI module is referred Note: This data sheet summarizes the features of to as SPI1, or separately as SPI1. Special this group of PIC24F devices. It is not Function Registers (SFRs) will follow a intended to be a comprehensive reference similar notation. For example, SPI1CON1 source. For more information on the Serial or SPI1CON2 refers to the control register Peripheral Interface, refer to the “PIC24F for the SPI1module. Family Reference Manual”, Section 23. “Serial Peripheral Interface (SPI)” To set up the SPI module for the Standard Master mode (DS39699). of operation: 1. If using interrupts: The Serial Peripheral Interface (SPI) module is a a) Clear the respective SPI1IF bit in the IFS0 synchronous serial interface useful for communicating register. with other peripheral or microcontroller devices. These peripheral devices may be serial data EEPROMs, shift b) Set the respective SPI1IE bit in the IEC0 registers, display drivers, A/D Converters, etc. The SPI register. module is compatible with the SPI and SIOP interfaces c) Write the respective SPI1IPx bits in the from Motorola®. IPC2 register to set the interrupt priority. The module supports operation in two buffer modes. In 2. Write the desired settings to the SPI1CON1 and Standard mode, data is shifted through a single serial SPI1CON2 registers with the MSTEN bit buffer. In Enhanced Buffer mode, data is shifted (SPI1CON1<5>) = 1. through an 8-level FIFO buffer. 3. Clear the SPIROV bit (SPI1STAT<6>). 4. Enable SPI operation by setting the SPIEN bit Note: Do not perform read-modify-write opera- (SPI1STAT<15>). tions (such as bit-oriented instructions) on the SPI1BUF register in either Standard or 5. Write the data to be transmitted to the SPI1BUF Enhanced Buffer mode. register. Transmission (and reception) will start as soon as data is written to the SPI1BUF The module also supports a basic framed SPI protocol register. while operating in either Master or Slave mode. A total To set up the SPI module for the Standard Slave mode of four framed SPI configurations are supported. of operation: The SPI serial interface consists of four pins: 1. Clear the SPI1BUF register. • SDI1: Serial Data Input 2. If using interrupts: • SDO1: Serial Data Output a) Clear the respective SPI1IF bit in the IFS0 • SCK1: Shift Clock Input or Output register. • SS1: Active-Low Slave Select or Frame b) Set the respective SPI1IE bit in the IEC0 Synchronization I/O Pulse register. The SPI module can be configured to operate using c) Write the respective SPI1IP bits in the IPC2 2,3 or 4 pins. In the 3-pin mode, SS1 is not used. In the register to set the interrupt priority. 2-pin mode, both SDO1 and SS1 are not used. 3. Write the desired settings to the SPI1CON1 Block diagrams of the module in Standard and and SPI1CON2 registers with the MSTEN bit Enhanced Buffer modes are displayed in Figure16-1 (SPI1CON1<5>) = 0. and Figure16-2. 4. Clear the SMP bit. 5. If the CKE bit is set, then the SSEN bit (SPI1CON1<7>) must be set to enable the SS1 pin. 6. Clear the SPIROV bit (SPI1STAT<6>). 7. Enable SPI operation by setting the SPIEN bit (SPI1STAT<15>).  2008-2011 Microchip Technology Inc. DS39927C-page 131

PIC24F16KA102 FAMILY FIGURE 16-1: SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE) SCK1 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SS1/FSYNC1 Sync Control Select Control Clock Edge SPI1CON1<1:0> ShiftControl SPI1CON1<4:2> SDO1 Enable SDI1 bit 0 Master Clock SPI1SR Transfer Transfer SPI1BUF Read SPI1BUF Write SPI1BUF 16 Internal Data Bus DS39927C-page 132  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY To set up the SPI module for the Enhanced Buffer To set up the SPI module for the Enhanced Buffer Master (EBM) mode of operation: Slave mode of operation: 1. If using interrupts: 1. Clear the SPI1BUF register. a) Clear the respective SPI1IF bit in the IFS0 2. If using interrupts: register. a) Clear the respective SPI1IF bit in the IFS0 b) Set the respective SPI1IE bit in the IEC0 register. register. b) Set the respective SPI1IE bit in the IEC0 c) Write the respective SPI1IPx bits in the register. IPC2 register. c) Write the respective SPI1IPx bits in the 2. Write the desired settings to the SPI1CON1 IPC2 register to set the interrupt priority. and SPI1CON2 registers with the MSTEN bit 3. Write the desired settings to the SPI1CON1 and (SPI1CON1<5>) = 1. SPI1CON2 registers with the MSTEN bit 3. Clear the SPIROV bit (SPI1STAT<6>). (SPI1CON1<5>) = 0. 4. Select Enhanced Buffer mode by setting the 4. Clear the SMP bit. SPIBEN bit (SPI1CON2<0>). 5. If the CKE bit is set, then the SSEN bit must be 5. Enable SPI operation by setting the SPIEN bit set, thus enabling the SS1 pin. (SPI1STAT<15>). 6. Clear the SPIROV bit (SPI1STAT<6>). 6. Write the data to be transmitted to the SPI1BUF 7. Select Enhanced Buffer mode by setting the register. Transmission (and reception) will start SPIBEN bit (SPI1CON2<0>). as soon as data is written to the SPI1BUF 8. Enable SPI operation by setting the SPIEN bit register. (SPI1STAT<15>). FIGURE 16-2: SPI1 MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE) SCK1 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SS1/FSYNC1 Sync Control Select Control Clock Edge SPI1CON1<1:0> ShiftControl SPI1CON1<4:2> SDO1 Enable SDI1 bit 0 Master Clock SPI1SR Transfer Transfer 8-Level FIFO 8-Level FIFO Receive Buffer Transmit Buffer SPI1BUF Read SPI1BUF Write SPI1BUF 16 InternalData Bus  2008-2011 Microchip Technology Inc. DS39927C-page 133

PIC24F16KA102 FAMILY REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0,HSC R/C-0, HS R/W-0, HSC R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit H = Hardware Settable bit C = Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPI1 Enable bit 1 = Enables module and configures SCK1, SDO1, SDI1 and SS1 as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 SPIBEC<2:0>: SPI1 Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPI transfers are pending. Slave mode: Number of SPI transfers are unread. bit 7 SRMPT: Shift Register (SPI1SR) Empty bit (valid in Enhanced Buffer mode) 1 = SPI1 Shift register is empty and ready to send or receive 0 = SPI1 Shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded The user software has not read the previous data in the SPI1BUF register. 0 = No overflow has occurred bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty bit 4-2 SISEL<2:0>: SPI1 Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when the SPI1 transmit buffer is full (SPITBF bit is set) 110 = Interrupt when the last bit is shifted into SPI1SR; as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPI1SR; now the transmit is complete 100 = Interrupt when one data byte is shifted into the SPI1SR; as a result, the TX FIFO has one open spot 011 = Interrupt when the SPI1 receive buffer is full (SPIRBF bit set) 010 = Interrupt when the SPI1 receive buffer is 3/4 or more full 001 = Interrupt when data is available in receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT bit is set) DS39927C-page 134  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPI1 Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPI1TXB is full 0 = Transmit has started, SPI1TXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes to the SPITBF location, loading SPITBF. Automatically cleared in hardware when the SPI1 module transfers data from SPI1TXB to SPIRBF. In Enhanced Buffer mode: Automatically set in hardware when CPU writes to the SPI1BUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. bit 0 SPIRBF: SPI1 Receive Buffer Full Status bit 1 = Receive is complete; SPI1RXB is full 0 = Receive is not complete; SPI1RXB is empty In Standard Buffer mode: Automatically set in hardware when SPI1 transfers data from SPIRBF to SPIRBF. Automatically cleared in hardware when the core reads the SPI1BUF location, reading SPIRBF. In Enhanced Buffer mode: Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR.  2008-2011 Microchip Technology Inc. DS39927C-page 135

PIC24F16KA102 FAMILY REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCK1 pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disables SDO1 pin bit 1 = SDO1 pin is not used by module; pin functions as I/O 0 = SDO1 pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPI1 Data Input Sample Phase bit Master mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time Slave mode: SMP must be cleared when SPI1 is used in Slave mode. bit 8 CKE: SPI1 Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode) 1 = SS1 pin is used for Slave mode 0 = SS1 pin is not used by the module; pin is controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS39927C-page 136  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1 (CONTINUED) bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). REGISTER 16-3: SPI1CON2: SPI1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD SPIFPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPIFE SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPI1 Support bit 1 = Framed SPI1 support is enabled 0 = Framed SPI1 support is disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control on SS1 Pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with the first bit clock 0 = Frame sync pulse precedes the first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer is enabled 0 = Enhanced Buffer is disabled (Legacy mode)  2008-2011 Microchip Technology Inc. DS39927C-page 137

PIC24F16KA102 FAMILY EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FCY FSCK = Primary Prescaler * Secondary Prescaler Note1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 16-1: SAMPLE SCK FREQUENCIES(1,2) Secondary Prescaler Settings FCY = 16 MHz 1:1 2:1 4:1 6:1 8:1 Primary Prescaler Settings 1:1 Invalid 8000 4000 2667 2000 4:1 4000 2000 1000 667 500 16:1 1000 500 250 167 125 64:1 250 125 63 42 31 FCY = 5 MHz Primary Prescaler Settings 1:1 5000 2500 1250 833 625 4:1 1250 625 313 208 156 16:1 313 156 78 52 39 64:1 78 39 20 13 10 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: SCK1 frequencies are indicated in kHz. DS39927C-page 138  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 17.0 INTER-INTEGRATED CIRCUIT 17.2 Communicating as a Master in a (I2C™) Single Master Environment The details of sending a message in Master mode Note: This data sheet summarizes the features depends on the communications protocol for the device of this group of PIC24F devices. It is not being communicated with. Typically, the sequence of intended to be a comprehensive events is as follows: reference source. For more information on the Inter-Integrated Circuit, refer to the 1. Assert a Start condition on SDA1 and SCL1. “PIC24F Family Reference Manual”, 2. Send the I2C device address byte to the slave Section 24. “Inter-Integrated Circuit™ with a write indication. (I2C™)” (DS39702). 3. Wait for and verify an Acknowledge from the The Inter-Integrated Circuit (I2C) module is a serial slave. interface useful for communicating with other 4. Send the first data byte (sometimes known as peripheral or microcontroller devices. These peripheral the command) to the slave. devices may be serial data EEPROMs, display drivers, 5. Wait for and verify an Acknowledge from the A/D Converters, etc. slave. The I2C module supports these features: 6. Send the serial memory address low byte to the slave. • Independent master and slave logic 7. Repeat Steps 4 and 5 until all data bytes are • 7-bit and 10-bit device addresses sent. • General call address, as defined in the I2C protocol 8. Assert a Repeated Start condition on SDA1 and • Automatic clock stretching to provide delays for SCL1. the processor to respond to a slave data request 9. Send the device address byte to the slave with • Both 100kHz and 400kHz bus specifications a read indication. • Configurable address masking 10. Wait for and verify an Acknowledge from the • Multi-Master modes to prevent loss of messages slave. in arbitration • Bus Repeater mode, allowing the acceptance of 11. Enable master reception to receive serial all messages as a slave regardless of the address memory data. • Automatic SCL 12. Generate an ACK or NACK condition at the end of a received byte of data. Figure17-1 illustrates a block diagram of the module. 13. Generate a Stop condition on SDA1 and SCL1. 17.1 Pin Remapping Options The I2C module is tied to a fixed pin. To allow flexibility with peripheral multiplexing, the I2C1 module in 28-pin devices can be reassigned to the alternate pins, designated as SCL1 and SDA1 during device configuration. Pin assignment is controlled by the I2C1SEL Configuration bit. Programming this bit (=0) multiplexes the module to the SCL1 and SDA1 pins.  2008-2011 Microchip Technology Inc. DS39927C-page 139

PIC24F16KA102 FAMILY FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2C1RCV Read Shift SCL1 Clock I2C1RSR LSB SDA1 Address Match Match Detect Write I2C1MSK Write Read I2C1ADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2C1STAT c ogi Read Collision ol L Write Detect ntr o C I2C1CON Acknowledge Generation Read Clock Stretching Write I2C1TRN LSB Read Shift Clock Reload Control Write BRG Down Counter I2C1BRG Read TCY/2 DS39927C-page 140  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 17.3 Setting Baud Rate When 17.4 Slave Address Masking Operating as a Bus Master The I2C1MSK register (Register17-3) designates To compute the Baud Rate Generator (BRG) reload address bit positions as “don’t care” for both 7-Bit and value, use Equation17-1. 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2C1MSK register causes the slave EQUATION 17-1: COMPUTING BAUD RATE module to respond whether the corresponding address RELOAD VALUE(1) bit value is ‘0’ or ‘1’. For example, when I2C1MSK is set to ‘00100000’, the slave module will detect both addresses: ‘0000000’ and ‘00100000’. FCY FSCL = ---------------------------------------------------------------------- FCY To enable address masking, the Intelligent Peripheral I2C1BRG+1+------------------------------ 10000000 Management Interface (IPMI) must be disabled by clearing the IPMIEN bit (I2C1CON<11>). or Note: As a result of changes in the I2C protocol, FCY FCY  I2C1BRG = ------------–------------------------------ –1 the addresses in Table17-2 are reserved FSCL 10000000 and will not be Acknowledged in Slave mode. This includes any address mask Note1: Based on FCY = FOSC/2; Doze mode and settings that include any of these PLL are disabled. addresses. TABLE 17-1: I2C™ CLOCK RATES(1) Required I2C1BRG Value Actual System FCY FSCL (Decimal) (Hexadecimal) FSCL 100kHz 16MHz 157 9D 100kHz 100kHz 8MHz 78 4E 100kHz 100kHz 4MHz 39 27 99kHz 400kHz 16MHz 37 25 404kHz 400kHz 8MHz 18 12 404kHz 400kHz 4MHz 9 9 385kHz 400kHz 2MHz 4 4 385kHz 1MHz 16MHz 13 D 1.026MHz 1MHz 8MHz 6 6 1.026MHz 1MHz 4MHz 3 3 0.909MHz Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled; TABLE 17-2: I2C™ RESERVED ADDRESSES(1) Slave R/W Description Address Bit 0000 000 0 General Call Address(2) 0000 000 1 Start Byte 0000 001 x Cbus Address 0000 010 x Reserved 0000 011 x Reserved 0000 1xx x HS Mode Master Code 1111 1xx x Reserved 1111 0xx x 10-Bit Slave Upper Byte(3) Note 1: The address bits listed here will never cause an address match, independent of the address mask settings. 2: The address will be Acknowledged only if GCEN=1. 3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.  2008-2011 Microchip Technology Inc. DS39927C-page 141

PIC24F16KA102 FAMILY REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2C1 Enable bit 1 = Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins 0 = Disables the I2C1 module; all I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCL1 Release Control bit (when operating as I2C slave) 1 = Releases SCL1 clock 0 = Holds SCL1 clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear at the beginning of slave transmission; hardware is clear at the end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave transmission. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses are Acknowledged 0 = IPMI Support mode is disabled bit 10 A10M: 10-Bit Slave Addressing bit 1 = I2C1ADD is a 10-bit slave address 0 = I2C1ADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with the SMBus specification 0 = Disables the SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2C1RSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCL1 Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching DS39927C-page 142  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master; applicable during master receive) 1 = Initiates Acknowledge sequence on SDA1 and SCL1 pins and transmits ACKDT data bit; hardware is clear at the end of the master Acknowledge sequence 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C; hardware is clear at the end of eighth bit of master receive data byte 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDA1 and SCL1 pins; hardware is clear at end of master Stop sequence 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDA1 and SCL1 pins; hardware is clear at end of master Repeated Start sequence 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDA1 and SCL1 pins; hardware is clear at end of master Start sequence 0 = Start condition is not in progress  2008-2011 Microchip Technology Inc. DS39927C-page 143

PIC24F16KA102 FAMILY REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D/A P S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit 1 = NACK was detected last 0 = ACK was detected last Hardware is set or clear at of Acknowledge. bit 14 TRSTAT: Transmit Status bit (When operating as I2C™ master; applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at beginning of master transmission; hardware is clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware is set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when address matches general call address; hardware is clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at match of 2nd byte of matched 10-bit address; hardware is clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2C1TRN register failed because the I2C module is busy 0 = No collision Hardware is set at occurrence of write to I2C1TRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2C1RCV register is still holding the previous byte 0 = No overflow Hardware is set at attempt to transfer to I2C1RCV (cleared by software). bit 5 D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was the device address Hardware is clear at device address match; hardware is set by a write to I2C1TRN or by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. DS39927C-page 144  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 2 R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates the data transfer is output from slave 0 = Write – indicates the data transfer is input to slave Hardware is set or clear after reception of I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2C1RCV is full 0 = Receive not complete, I2C1RCV is empty Hardware is set when I2C1RCV is written with received byte; hardware is clear when software reads I2C1RCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2C1TRN is full 0 = Transmit complete, I2C1TRN is empty Hardware is set when software writes to I2C1TRN; hardware is clear at completion of data transmission.  2008-2011 Microchip Technology Inc. DS39927C-page 145

PIC24F16KA102 FAMILY REGISTER 17-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match is not required in this position 0 = Disable masking for bit x; bit match is required in this position REGISTER 17-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — SMBUSDEL OC1TRIS(2,3) RTSECSEL1(1,3) RTSECSEL0(1,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 SMBUSDEL: SMBus SDA Input Delay Select bit 1 = The I2C module is configured for a longer SMBus input delay (nominal 300 ns delay) 0 = The 12C module is configured for a legacy input delay (nominal 150 ns delay) bit 0 Unimplemented: Read as ‘0’ Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set. 2: To enable the actual OC1 output, the OCPWM1 module has to be enabled. 3: Bits<3:1> are described in related chapters. DS39927C-page 146  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 18.0 UNIVERSAL ASYNCHRONOUS • Fully Integrated Baud Rate Generator (IBRG) with RECEIVER TRANSMITTER 16-Bit Prescaler • Baud Rates Ranging from 1Mbps to 15bps at (UART) 16MIPS Note: This data sheet summarizes the features • 4-Deep, First-In-First-Out (FIFO) Transmit Data of this group of PIC24F devices. It is not Buffer intended to be a comprehensive • 4-Deep FIFO Receive Data Buffer reference source. For more information • Parity, Framing and Buffer Overrun Error on the Universal Asynchronous Receiver Detection Transmitter, refer to the “PIC24F Family • Support for 9-Bit mode with Address Detect (9th Reference Manual”, Section 21. “UART” bit = 1) (DS39708). • Transmit and Receive Interrupts The Universal Asynchronous Receiver Transmitter • Loopback mode for Diagnostic Support (UART) module is one of the serial I/O modules avail- • Support for Sync and Break Characters able in this PIC24F device family. The UART is a • Supports Automatic Baud Rate Detection full-duplex asynchronous system that can communicate • IrDA Encoder and Decoder Logic with peripheral devices, such as personal computers, • 16x Baud Clock Output for IrDA Support LIN, RS-232 and RS-485 interfaces. This module also supports a hardware flow control option with the UxCTS A simplified block diagram of the UART is displayed in and UxRTS pins, and also includes an IrDA® encoder Figure18-1. The UART module consists of these and decoder. important hardware elements: The primary features of the UART module are: • Baud Rate Generator • Full-Duplex, 8-Bit or 9-Bit Data Transmission • Asynchronous Transmitter through the UxTX and UxRX Pins • Asynchronous Receiver • Even, Odd or No Parity Options (for 8-bit data) • One or Two Stop bits • Hardware Flow Control Option with UxCTS and UxRTS pins FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® UxBCLK Hardware Flow Control UxRTS UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2008-2011 Microchip Technology Inc. DS39927C-page 147

PIC24F16KA102 FAMILY 18.1 UART Baud Rate Generator (BRG) The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate The UART module includes a dedicated 16-bit Baud possible is FCY/(16 * 65536). Rate Generator (BRG). The UxBRG register controls Equation18-2 provides the formula for computation of the period of a free-running, 16-bit timer. Equation18-1 the baud rate with BRGH = 1. provides the formula for computation of the baud rate with BRGH = 0. EQUATION 18-2: UART BAUD RATE WITH EQUATION 18-1: UART BAUD RATE WITH BRGH = 1(1) BRGH = 0(1) FCY Baud Rate = FCY 4 • (UxBRG + 1) Baud Rate = 16 • (UxBRG + 1) FCY UxBRG = – 1 4 • Baud Rate UxBRG = FCY – 1 16 • Baud Rate Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. The maximum baud rate (BRGH = 1) possible is FCY/4 (for UxBRG = 0) and the minimum baud rate possible Example18-1 provides the calculation of the baud rate is FCY/(4 * 65536). error for the following conditions: Writing a new value to the UxBRG register causes the • FCY = 4 MHz BRG timer to be reset (cleared). This ensures the BRG • Desired Baud Rate = 9600 does not wait for a timer overflow before generating the new baud rate. EXAMPLE 18-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1) Desired Baud Rate = FCY/(16 (UxBRG + 1)) Solving for UxBRG value: UxBRG = ((FCY/Desired Baud Rate)/16) – 1 UxBRG = ((4000000/9600)/16) – 1 UxBRG = 25 Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 = 0.16% Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. DS39927C-page 148  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 18.2 Transmitting in 8-Bit Data Mode 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART: a) Write appropriate values for data, parity and 1. Set up the UART (as described in Section18.2 Stop bits. “Transmitting in 8-Bit Data Mode”). b) Write appropriate baud rate value to the 2. Enable the UART. UxBRG register. 3. A receive interrupt will be generated when one c) Set up transmit and receive interrupt enable or more data characters have been received, as and priority bits. per interrupt control bit, URXISELx. 2. Enable the UART. 4. Read the OERR bit to determine if an overrun 3. Set the UTXEN bit (causes a transmit interrupt error has occurred. The OERR bit must be reset two cycles after being set). in software. 4. Write data byte to lower byte of UxTXREG word. 5. Read UxRXREG. The value will be immediately transferred to the The act of reading the UxRXREG character will move Transmit Shift Register (TSR) and the serial bit the next character to the top of the receive FIFO, stream will start shifting out with the next rising including a new set of PERR and FERR values. edge of the baud clock. 5. Alternately, the data byte may be transferred 18.6 Operation of UxCTS and UxRTS while UTXEN = 0, and then, the user may set Control Pins UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will UARTx Clear to Send (UxCTS) and Request to Send start from a cleared state. (UxRTS) are the two hardware-controlled pins that are 6. A transmit interrupt will be generated as per associated with the UART module. These two pins interrupt control bit, UTXISELx. allow the UART to operate in Simplex and Flow Control modes. They are implemented to control the 18.3 Transmitting in 9-Bit Data Mode transmission and reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the UxMODE 1. Set up the UART (as described in Section18.2 register configure these pins. “Transmitting in 8-Bit Data Mode”). 2. Enable the UART. 18.7 Infrared Support 3. Set the UTXEN bit (causes a transmit interrupt The UART module provides two types of infrared UART twocycles after being set). support: one is the IrDA clock output to support an 4. Write UxTXREG as a 16-bit value only. external IrDA encoder and decoder device (legacy 5. A word write to UxTXREG triggers the transfer module support), and the other is the full of the 9-bit data to the TSR. The serial bit stream implementation of the IrDA encoder and decoder. will start shifting out with the first rising edge of As the IrDA modes require a 16x baud clock, they will the baud clock. only work when the BRGH bit (UxMODE<3>) is ‘0’. 6. A transmit interrupt will be generated as per the setting of control bit, UTXISELx. 18.7.1 EXTERNAL IrDA SUPPORT – IrDA CLOCK OUTPUT 18.4 Break and Sync Transmit To support external IrDA encoder and decoder devices, Sequence the UxBCLK pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. When The following sequence will send a message frame UEN<1:0> = 11, the UxBCLK pin will output the 16x header made up of a Break, followed by an auto-baud baud clock if the UART module is enabled; it can be Sync byte. used to support the IrDA codec chip. 1. Configure the UART for the desired mode. 2. Set UTXEN and UTXBRK – sets up the Break 18.7.2 BUILT-IN IrDA ENCODER AND character. DECODER 3. Load the UxTXREG with a dummy character to The UART has full implementation of the IrDA encoder initiate transmission (value is ignored). and decoder as part of the UART module. The built-in 4. Write ‘55h’ to UxTXREG – loads the Sync IrDA encoder and decoder functionality is enabled character into the transmit FIFO. using the IREN bit (UxMODE<12>). When enabled 5. After the Break has been sent, the UTXBRK bit (IREN = 1), the receive pin (UxRX) acts as the input is reset by hardware. The Sync character now from the infrared receiver. The transmit pin (UxTX) acts transmits. as the output to the infrared transmitter.  2008-2011 Microchip Technology Inc. DS39927C-page 149

PIC24F16KA102 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2) R/W-0(2) UARTEN — USIDL IREN(1) RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(1) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits(2) 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by port latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ Note 1: This feature is only available for the 16x BRG mode (BRGH=0). 2: Bit availability depends on pin availability. DS39927C-page 150  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH=0). 2: Bit availability depends on pin availability.  2008-2011 Microchip Technology Inc. DS39927C-page 151

PIC24F16KA102 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle ‘0’ 0 = UxTX Idle ‘1’ If IREN = 1: 1 = UxTX Idle ‘1’ 0 = UxTX Idle ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: Transmit Enable bit 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and buffer is reset. UxTX pin is controlled by the PORT register. bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters DS39927C-page 152  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (10 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty  2008-2011 Microchip Technology Inc. DS39927C-page 153

PIC24F16KA102 FAMILY REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER U-x U-x U-x U-x U-x U-x U-x W-x — — — — — — — UTX8 bit 15 bit 8 W-x W-x W-x W-x W-x W-x W-x W-x UTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 UTX0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode) bit 7-0 UTX<7:0>: Data of the Transmitted Character bits REGISTER 18-4: UxRXREG: UARTx RECEIVE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — URX8 bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC URX7 URX6 URX5 URX4 URX3 URX2 URX1 URX0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 URX8: Data of the Received Character bit (in 9-bit mode) bit 7-0 URX<7:0>: Data of the Received Character bits DS39927C-page 154  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 19.0 REAL-TIME CLOCK AND one day, one week, one month or one year CALENDAR (RTCC) • Alarm repeat with decrementing counter • Alarm with indefinite repeat chime Note: This data sheet summarizes the features of • Year 2000 to 2099 leap year correction this group of PIC24F devices. It is not • BCD format for smaller software overhead intended to be a comprehensive reference • Optimized for long-term battery operation source. For more information on the Real-Time Clock and Calendar, refer to the • User calibration of the 32.768 kHz clock “PIC24F Family Reference Manual”, crystal/32K INTRC frequency with periodic Section 29. “Real-Time Clock and auto-adjust Calendar (RTCC)” (DS39696). 19.1 RTCC Source Clock The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated. The user can select between the SOSC crystal oscillator or the LPRC internal oscillator as the clock Key features of the RTCC module are: reference for the RTCC module. This is configured • Operates in Deep Sleep mode using the RTCOSC (FDS<5>) Configuration bit. This • Selectable clock source gives the user an option to trade off system cost, • Provides hours, minutes and seconds using accuracy and power consumption, based on the overall 24-hour format system needs. • Visibility of one half second period The RTCC will continue to run, along with its chosen • Provides calendar – weekday, date, month and clock source, while the device is held in Reset with year MCLR and will continue running after MCLR is released. • Alarm-configurable for half a second, one second, 10 seconds, one minute, 10 minutes, one hour, FIGURE 19-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain Input from SOSC/LPRC RCFGCAL Oscillator RTCC Prescalers ALCFGRPT 0.5 Sec YEAR MTHDY RTCC Timer RTCVAL WKDYHR Alarm MINSEC Event Comparator ALMTHDY Alarm Registers with Masks ALRMVAL ALWDHR ALMINSEC Repeat Counter RTSECSEL<1:0> RTCC Interrupt 1s RTCC Interrupt Logic 01 Alarm Pulse 00 10 RTCC Clock Source Pin RTCOE  2008-2011 Microchip Technology Inc. DS39927C-page 155

PIC24F16KA102 FAMILY 19.2 RTCC Module Registers TABLE 19-2: ALRMVAL REGISTER MAPPING The RTCC module registers are organized into three categories: ALRMPTR Alarm Value Register Window • RTCC Control Registers <1:0> ALRMVAL<15:8> ALRMVAL<7:0> • RTCC Value Registers 00 ALRMMIN ALRMSEC • Alarm Value Registers 01 ALRMWD ALRMHR 19.2.1 REGISTER MAPPING 10 ALRMMNTH ALRMDAY To limit the register interface, the RTCC Timer and 11 — — Alarm Time registers are accessed through Considering that the 16-bit core does not distinguish corresponding register pointers. The RTCC Value between 8-bit and 16-bit read operations, the user must register window (RTCVALH and RTCVALL) uses the be aware that when reading either the ALRMVALH or RTCPTR bits (RCFGCAL<9:8>) to select the desired ALRMVALL bytes, the ALRMPTR<1:0> value will be Timer register pair (see Table19-1). decremented. The same applies to the RTCVALH or By writing the RTCVALH byte, the RTCC Pointer value, RTCVALL bytes with the RTCPTR<1:0> being the RTCPTR<1:0> bits decrement by one until they decremented. reach ‘00’. Once they reach ‘00’, the MINUTES and Note: This only applies to read operations and SECONDS value will be accessible through RTCVALH not write operations. and RTCVALL until the pointer value is manually changed. 19.2.2 WRITE LOCK TABLE 19-1: RTCVAL REGISTER MAPPING In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL<13>) must be RTCC Value Register Window RTCPTR<1:0> set (refer to Example19-1). RTCVAL<15:8> RTCVAL<7:0> Note: To avoid accidental writes to the timer, it is 00 MINUTES SECONDS recommended that the RTCWREN bit 01 WEEKDAY HOURS (RCFGCAL<13>) is kept clear at any other time. For the RTCWREN bit to be 10 MONTH DAY set, there is only one instruction cycle time 11 — YEAR window allowed between the 55h/AA The Alarm Value register window (ALRMVALH sequence and the setting of RTCWREN; and ALRMVALL) uses the ALRMPTR bits therefore, it is recommended that code (ALCFGRPT<9:8>) to select the desired Alarm register follow the procedure in Example19-1. pair (see Table19-2). 19.2.3 SELECTING RTCC CLOCK SOURCE By writing the ALRMVALH byte, the Alarm Pointer value bits (ALRMPTR<1:0>) decrement by one until The clock source for the RTCC module can be selected they reach ‘00’. Once they reach ‘00’, the ALRMMIN using the RTCOSC (FDS<5>) bit. When the bit is set to and ALRMSEC value will be accessible through ‘1’, the Secondary Oscillator (SOSC) is used as the ref- ALRMVALH and ALRMVALL until the pointer value is erence clock and when the bit is ‘0’, LPRC is used as manually changed. the reference clock. EXAMPLE 19-1: SETTING THE RTCWREN BIT asm volatile ("push w7") ; asm volatile ("push w8") ; asm volatile ("disi #5") ; asm volatile ("mov #0x55, w7") ; asm volatile ("mov w7, _NVMKEY") ; asm volatile ("mov #0xAA, w8") ; asm volatile ("mov w8, _NVMKEY") ; asm volatile ("bset _RCFGCAL, #13") ; //set the RTCWREN bit asm volatile ("pop w8") ; asm volatile ("pop w7"); DS39927C-page 156  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 19.2.4 RTCC CONTROL REGISTERS REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple, resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL<15:8>: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL<7:0>: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.  2008-2011 Microchip Technology Inc. DS39927C-page 157

PIC24F16KA102 FAMILY REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute . . . 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. REGISTER 19-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — SMBUSDEL OC1TRIS RTSECSEL1(1) RTSECSEL0(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-3 Described in Section15.0 “Output Compare” and Section17.0 “Inter-Integrated Circuit (I2C™)”. bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (can be LPRC or SOSC, depending on the RTCOSC (FDS<5>) bit setting) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin bit 0 Unimplemented: Read as ‘0’ Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set. DS39927C-page 158  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0>=00h and CHIME=0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless CHIME=1.  2008-2011 Microchip Technology Inc. DS39927C-page 159

PIC24F16KA102 FAMILY 19.2.5 RTCVAL REGISTER MAPPINGS REGISTER 19-4: YEAR: YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN2 YRTEN1 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to the YEAR register is only allowed when RTCWREN=1. REGISTER 19-5: MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of ‘0’ or ‘1’. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS39927C-page 160  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 19-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2008-2011 Microchip Technology Inc. DS39927C-page 161

PIC24F16KA102 FAMILY 19.2.6 ALRMVAL REGISTER MAPPINGS REGISTER 19-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of ‘0’ or ‘1’. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 19-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS39927C-page 162  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2008-2011 Microchip Technology Inc. DS39927C-page 163

PIC24F16KA102 FAMILY 19.3 Calibration 19.4.1 CONFIGURING THE ALARM The real-time crystal input can be calibrated using the The alarm feature is enabled using the ALRMEN bit. periodic auto-adjust feature. When properly calibrated, This bit is cleared when an alarm is issued. Writes to the RTCC can provide an error of less than 3 seconds ALRMVAL should only take place when ALRMEN = 0. per month. This is accomplished by finding the number As displayed in Figure19-2, the interval selection of the of error clock pulses and storing the value into the alarm is configured through the AMASK bits lower half of the RCFGCAL register. The 8-bit signed (ALCFGRPT<13:10>). These bits determine which and value loaded into the lower half of RCFGCAL is how many digits of the alarm must match the clock multiplied by four and will either be added or subtracted value for the alarm to occur. from the RTCC timer, once every minute. Refer to the The alarm can also be configured to repeat based on a steps below for RTCC calibration: preconfigured interval. The amount of times this 1. Using another timer resource on the device, the occurs, once the alarm is enabled, is stored in the user must find the error of the 32.768kHz crystal. ARPT<7:0> bits (ALCFGRPT<7:0>). When the value 2. Once the error is known, it must be converted to of the ARPT bits equals 00h and the CHIME bit the number of error clock pulses per minute. (ALCFGRPT<14>) is cleared, the repeat function is 3. a) If the oscillator is faster than ideal (negative disabled and only a single alarm will occur. The alarm result form Step 2), the RCFGCAL register value can be repeated, up to 255 times, by loading must be negative. This causes the specified ARPT<7:0> with FFh. number of clock pulses to be subtracted from After each alarm is issued, the value of the ARPT bits the timer counter, once every minute. is decremented by one. Once the value has reached b) If the oscillator is slower than ideal (positive 00h, the alarm will be issued one last time, after which, result from Step 2), the RCFGCAL register value the ALRMEN bit will be cleared automatically and the must be positive. This causes the specified alarm will turn off. number of clock pulses to be subtracted from Indefinite repetition of the alarm can occur if the the timer counter, once every minute. CHIME bit = 1. Instead of the alarm being disabled Divide the number of error clocks, per minute by 4, to when the value of the ARPT bits reaches 00h, it rolls get the correct calibration value and load the over to FFh and continues counting indefinitely while RCFGCAL register with the correct value. (Each 1-bit CHIME is set. increment in the calibration adds or subtracts 4 pulses). 19.4.2 ALARM INTERRUPT EQUATION 19-1: At every alarm event, an interrupt is generated. In (Ideal Frequency† – Measured Frequency) * 60 = addition, an alarm pulse output is provided that Clocks per Minute operates at half the frequency of the alarm. This output † Ideal Frequency = 32,768 Hz is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off, or Note: Changing any of the registers, other than immediately after the rising edge of the seconds pulse. the RCFGCAL and ALCFGRPT registers, and the CHIME bit while the alarm is Note: It is up to the user to include in the error enabled (ALRMEN = 1), can result in a value, the initial error of the crystal; drift false alarm event leading to a false alarm due to temperature and drift due to crystal interrupt. To avoid a false alarm event, the aging. timer and alarm values should only be changed while the alarm is disabled 19.4 Alarm (ALRMEN = 0). It is recommended that the ALCFGRPT register and the CHIME • Configurable from half second to one year bit be changed when RTCSYNC = 0. • Enabled using the ALRMEN bit (ALCFGRPT<15>) • One-time alarm and repeat alarm options available DS39927C-page 164  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY FIGURE 19-2: ALARM MASK SETTINGS Day of Alarm Mask Setting the (AMASK<3:0>) Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s 0100 - Every 10 minutes m s s 0101 - Every hour m m s s 0110 - Every day h h m m s s 0111 - Every week d h h m m s s 1000 - Every month d d h h m m s s 1001 - Every year(1) m m d d h h m m s s Note 1: Annually, except when configured for February 29.  2008-2011 Microchip Technology Inc. DS39927C-page 165

PIC24F16KA102 FAMILY NOTES: DS39927C-page 166  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 20.0 PROGRAMMABLE CYCLIC The programmable CRC generator offers the following REDUNDANCY CHECK (CRC) features: GENERATOR • User-programmable polynomial CRC equation • Interrupt output Note: This data sheet summarizes the features of • Data FIFO this group of PIC24F devices. It is not The module implements a software-configurable CRC intended to be a comprehensive reference generator. The terms of the polynomial and its length source. For more information on Program- can be programmed using the CRCXOR (X<15:1>) bits mable Cyclic Redundancy Check, refer to and the CRCCON (PLEN<3:0>) bits, respectively. the “PIC24F Family Reference Manual”, Consider the CRC equation: Section 30. “Programmable Cyclic Redundancy Check (CRC)” (DS39714). EQUATION 20-1: CRC The programmable Cyclic Redundancy Check (CRC) x16 + x12 + x5 + 1 module in PIC24F devices is a software-configurable CRC checksum generator. The CRC algorithm treats a To program this polynomial into the CRC generator, the message as a binary bit stream and divides it by a fixed CRC register bits should be set as provided in binary number. Table20-1. The remainder from this division is considered the checksum. As in division, the CRC calculation is also TABLE 20-1: EXAMPLE CRC SETUP an iterative process. The only difference is that these operations are done on modulo arithmetic based on Bit Name Bit Value mod2. For example, division is replaced with the XOR PLEN<3:0> 1111 operation (i.e., subtraction without carry). The CRC X<15:1> 000100000010000 algorithm uses the term, polynomial, to perform all of its calculations. The value of X<15:1>, the 12th bit and the 5th bit are set to ‘1’, as required by the equation. The 0 bit required by The divisor, dividend and remainder that are the equation is always XORed. For a 16-bit polynomial, represented by numbers are termed as polynomials the 16th bit is also always assumed to be XORed; with binary coefficients. therefore, the X<15:1> bits do not have the 0 bit or the 16th bit. The topology of a standard CRC generator is displayed in Figure20-2. FIGURE 20-1: CRC SHIFTER DETAILS PLEN<3:0> 0 1 2 15 CRC Shift Register Hold X1 Hold X2 Hold X3 X15 Hold XOR OUT 0 OUT 0 OUT 0 0 OUT IN IN IN IN DOUT BIT 0 BIT 1 BIT 2 BIT 15 1 1 1 1 clk clk clk clk CRC Read Bus CRC Write Bus  2008-2011 Microchip Technology Inc. DS39927C-page 167

PIC24F16KA102 FAMILY FIGURE 20-2: CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1 XOR D Q D Q D Q D Q D Q SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 clk clk clk clk clk CRC Read Bus CRC Write Bus 20.1 User Interface To empty words already written into a FIFO, the CRCGO bit must be set to ‘1’ and the CRC shifter 20.1.1 DATA INTERFACE allowed to run until the CRCMPT bit is set. To start serial shifting, a value of ‘1’ must be written to Also, to get the correct CRC reading, it will be the CRCGO bit. necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. The module incorporates a FIFO that is 8-level deep when PLEN<3:0>>7 and 16-deep, otherwise. The If a word is written when the CRCFUL bit is set, the data for which the CRC is to be calculated must first be VWORD Pointer will roll over to 0. The hardware will written into the FIFO. The smallest data element that then behave as if the FIFO is empty. However, the can be written into the FIFO is one byte. condition to generate an interrupt will not be met; therefore, no interrupt will be generated (see For example, if PLEN=5, then the size of the data is Section20.1.2 “Interrupt Operation”). PLEN+1=6. The data must be written as follows: At least one instruction cycle must pass after a write to data<5:0>=crc_input<5:0> CRCWDAT before a read of the VWORD bits is done. data<7:6>=bxx Once data is written into the CRCWDAT MSb (as 20.1.2 INTERRUPT OPERATION defined by PLEN), the value of the VWORD bits When the VWORD<4:0> bits make a transition from a (CRCCON<12:8>) increments by one. The serial value of ‘1’ to ‘0’, an interrupt will be generated. shifter starts shifting data into the CRC engine when CRCGO=1 and VWORD<4:0>>0. When the Most 20.2 Operation in Power Save Modes Significant bit (MSb) is shifted out, the VWORD bits decrement by one. The serial shifter continues shifting 20.2.1 SLEEP MODE until the VWORD bits reach zero. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD If Sleep mode is entered while the module is operating, number of clock cycles to complete the CRC the module will be suspended in its current state until calculations. clock execution resumes. When the VWORD bits reach 8 (or 16), the CRCFUL bit 20.2.2 IDLE MODE will be set. When the VWORD bits reach 0, the CRCMPT bit will be set. To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” If CSIDL=1, the module will behave the same way as the FIFO with a sufficient number of words so no it does in Sleep mode; pending interrupt events will be interrupt is generated before the next word can be passed on, even though the module clocks are not written. Once that is done, start the CRC by setting the available. CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. DS39927C-page 168  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 20.3 Registers There are four registers used to control programmable CRC operation: • CRCCON • CRCXOR • CRCDAT • CRCWDAT REGISTER 20-1: CRCCON: CRC CONTROL REGISTER U-0 U-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0, HSC R-1, HSC U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> > 7, or 16 when PLEN<3:0> 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 Unimplemented: Read as ‘0’ bit 4 CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter is turned off bit 3-0 PLEN<3:0>: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1.  2008-2011 Microchip Technology Inc. DS39927C-page 169

PIC24F16KA102 FAMILY REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X15 X14 X13 X12 X11 X10 X9 X8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X7 X6 X5 X4 X3 X2 X1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’ DS39927C-page 170  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 21.0 HIGH/LOW-VOLTAGE DETECT An interrupt flag is set if the device experiences an (HLVD) excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will Note: This data sheet summarizes the features branch to the interrupt vector address and the software of this group of PIC24F devices. It is not can then respond to the interrupt. intended to be a comprehensive The HLVD Control register (see Register21-1) reference source. For more information completely controls the operation of the HLVD module. on the High/Low-Voltage Detect, refer to This allows the circuitry to be “turned off” by the user the “PIC24F Family Reference Manual”, under software control, which minimizes the current Section 36. “High-Level Integration consumption for the device. with Programmable High/Low-Voltage Detect (HLVD)” (DS39725). The High/Low-Voltage Detect module (HLVD) is a programmable circuit that allows the user to specify both the device voltage trip point and the direction of change. FIGURE 21-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM Externally Generated Trip Point VDD HLVDIN VDD HLVDL<3:0> HLVDEN VDIR X U Set M HLVDIF 1 o- 6-t 1 Internal Band Gap Voltage Reference 1.2V Typical HLVDEN  2008-2011 Microchip Technology Inc. DS39927C-page 171

PIC24F16KA102 FAMILY REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 HLSIDL: HLVD Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 VDIR: Voltage Change Direction Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the internal reference voltage is stable and the High-Voltage Detect logic generates the interrupt flag at the specified voltage range 0 = Indicates that the internal reference voltage is unstable and the High-Voltage Detect logic will not generate the interrupt flag at the specified voltage range, and the HLVD interrupt should not be enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 HLVDL<3:0>: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Trip Point 1(1) 1101 = Trip Point 2(1) 1100 = Trip Point 3(1) . . . 0000 = Trip Point 15(1) Note 1: For actual trip point, refer to Section29.0 “Electrical Characteristics”. DS39927C-page 172  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 22.0 10-BIT HIGH-SPEED A/D A block diagram of the A/D Converter is displayed in CONVERTER Figure22-1. To perform an A/D conversion: Note: This data sheet summarizes the features 1. Configure the A/D module: of this group of PIC24F devices. It is not a) Configure port pins as analog inputs and/or intended to be a comprehensive select band gap reference inputs reference source. For more information (AD1PCFG<15:13>, AD1PCFG<9:6>). on the 10-Bit High-Speed A/D Converter, refer to the “PIC24F Family Reference b) Select voltage reference source to match Manual”, Section 17. “10-Bit A/D expected range on analog inputs Converter” (DS39705). (AD1CON2<15:13>). c) Select the analog conversion clock to match The 10-bit A/D Converter has the following key the desired data rate with the processor features: clock (AD1CON3<7:0>). • Successive Approximation (SAR) conversion d) Select the appropriate sample/conversion • Conversion speeds of up to 500ksps sequence (AD1CON1<7:5> and • Nine analog input pins AD1CON3<12:8>). • External voltage reference input pins e) Select how conversion results are presented in the buffer (AD1CON1<9:8>). • Internal band gap reference inputs f) Select interrupt rate (AD1CON2<5:2>). • Automatic Channel Scan mode g) Turn on A/D module (AD1CON1<15>). • Selectable conversion trigger source 2. Configure A/D interrupt (if required): • 16-word conversion result buffer a) Clear the AD1IF bit. • Selectable Buffer Fill modes b) Select A/D interrupt priority. • Four result alignment options • Operation During CPU Sleep and Idle modes On all PIC24F16KA102 family devices, the 10-bit A/D Converter has nine analog input pins, designated AN0 through AN5 and AN10 through AN12. In addition, there are two analog input pins for external voltage reference connections (VREF+and VREF-). These voltage reference inputs may be shared with other analog input pins.  2008-2011 Microchip Technology Inc. DS39927C-page 173

PIC24F16KA102 FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD VR+ AVSS ect 16 el VREF+ SR VR- V VREF- Comparator VINH VR- VR+ VINL S/H DAC 10-Bit SAR Conversion Logic VINH AN0 AN1 X A Data Formatting U M AN2 AN3 AN1 VINL ADC1BUF0: AN4 ADC1BUFF AN5 AD1CON1 AN10 AD1CON2 AD1CON3 AN11 AD1CHS AN12 VINH AD1PCFG B X AD1CSSL VBG MU VBG/2 AN1 VINL Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control DS39927C-page 174  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HSC R/W-0, HSC SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 FORM<1:0>: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU event ends sampling and starts conversion 101 = Reserved 100 = Reserved 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion bit 4-3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is not done Note 1: Values of ADC1BUFn registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module.  2008-2011 Microchip Technology Inc. DS39927C-page 175

PIC24F16KA102 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 OFFCAL(1) — CSCNA — — bit 15 bit 8 R-0, HSC U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits VCFG<2:0> VR+ VR- 000 AVDD AVSS 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin 1xx AVDD AVSS bit 12 OFFCAL: Offset Calibration bit(1) 1 = Converts to get the offset calibration value 0 = Converts to get the actual input value bit 11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer, 08-0F; user should access data in 00-07 0 = A/D is currently filling buffer, 00-07; user should access data in 08-0F bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence . . . 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence Note 1: When the OFFCAL bit is set, inputs are disconnected and tied to AVSS. This sets the inputs of the A/D to zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG contents nor channel input selection. Any analog input switches are disconnected from the A/D Converter in this mode. The conversion result is stored by the user software and used to compensate subsequent conversions. This can be done by adding the two’s complement of the result obtained with the OFFCAL bit set to all normal A/D conversions. DS39927C-page 176  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED) bit 1 BUFM: Buffer Mode Select bit 1 = Buffer is configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>) 0 = Buffer is configured as one 16-word buffer (ADC1BUFn<15:0>) bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings Note 1: When the OFFCAL bit is set, inputs are disconnected and tied to AVSS. This sets the inputs of the A/D to zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG contents nor channel input selection. Any analog input switches are disconnected from the A/D Converter in this mode. The conversion result is stored by the user software and used to compensate subsequent conversions. This can be done by adding the two’s complement of the result obtained with the OFFCAL bit set to all normal A/D conversions. REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto-Sample Time bits 11111 = 31 TAD · · · 00001 = 1 TAD 00000 = 0 TAD (not recommended) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ADCS<5:0>: A/D Conversion Clock Select bits 111111 = 64 • TCY 111110 = 63 • TCY · · · 000001 = 3 • TCY 000000 = 2 • TCY  2008-2011 Microchip Technology Inc. DS39927C-page 177

PIC24F16KA102 FAMILY - REGISTER 22-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 14-12 Unimplemented: Read as ‘0’ bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits 1111 = Channel 0 positive input is band gap reference (VBG) 1110 = Channel 0 positive input is band gap, divided by two, reference (VBG/2) 1101 = No channels connected (actual A/D MUX switch activates, but input floats); used for CTMU 1100 = Channel 0 positive input is AN12 1011 = Channel 0 positive input is AN11 1010 = Channel 0 positive input is AN10 1001 = Reserved 1000 = Reserved 0111 = AVDD 0110 = AVSS 0101 = Channel 0 positive input is AN5 0100 = Channel 0 positive input is AN4 0011 = Channel 0 positive input is AN3 0010 = Channel 0 positive input is AN2 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for Sample A bits 1111 = Channel 0 positive input is band gap reference (VBG) 1110 = Channel 0 positive input is band gap, divided by two, reference (VBG/2) 1101 = No channels connected (actual A/D MUX switch activates but input floats); used for CTMU 1100 = Channel 0 positive input is AN12 1011 = Channel 0 positive input is AN11 1010 = Channel 0 positive input is AN10 1001 = Reserved 1000 = Reserved 0111 = AVDD 0110 = AVSS 0101 = Channel 0 positive input is AN5 0100 = Channel 0 positive input is AN4 0011 = Channel 0 positive input is AN3 0010 = Channel 0 positive input is AN2 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 DS39927C-page 178  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 22-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PCFG15 PCFG14 — PCFG12 PCFG11 PCFG10 — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PCFG15: Analog Input Pin Configuration Control bit 1 = Analog channel is disabled from input scan 0 = Internal band gap (VBG) channel is enabled for input scan bit 14 PCFG14: Analog Input Pin Configuration Control bit 1 = Analog channel is disabled from input scan 0 = Internal VBG/2 channel is enabled for input scan bit 13 Unimplemented: Read as ‘0’ bit 12-10 PCFG<12:10>: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled 0 = Pin is configured in Analog mode; I/O port read is disabled; A/D samples pin voltage bit 9-6 Unimplemented: Read as ‘0’ bit 5-0 PCFG<5:0>: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled 0 = Pin configured in Analog mode; I/O port read is disabled; A/D samples pin voltage  2008-2011 Microchip Technology Inc. DS39927C-page 179

PIC24F16KA102 FAMILY REGISTER 22-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — CSSL12 CSSL11 CSSL10 — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-10 CSSL<12:10>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel is selected for input scan 0 = Analog channel omitted from input scan bit 9-6 Unimplemented: Read as ‘0’ bit 5-0 CSSL<5:0>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel is selected for input scan 0 = Analog channel omitted from input scan DS39927C-page 180  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY EQUATION 22-1: A/D CONVERSION CLOCK PERIOD(1) TAD ADCS = – 1 TCY TAD = TCY • (ADCS + 1) Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD RIC  250 Sampling RSS  5 k (Typical) Switch VT = 0.6V Rs ANx RSS CHOLD VA C6-P1I1N pF VT = 0.6V I±L5E0A0K AnGAE == A4./4D p cFa p(Taycpitiacnacl)e (Typical) VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from A/D) Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs  5 k.  2008-2011 Microchip Technology Inc. DS39927C-page 181

PIC24F16KA102 FAMILY FIGURE 22-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) Voltage Level 0 V-R V+ – V-RRV- +R1024 512 * (V+ – V-)RR 1024 1023 * (V+ – V-)RR 1024 V+R (V – V)INHINL + V- R - +R V DS39927C-page 182  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 23.0 COMPARATOR MODULE The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, Note: This data sheet summarizes the features the I/O pad logic makes the unsynchronized output of of this group of PIC24F devices. It is not the comparator available on the pin. intended to be a comprehensive refer- A simplified block diagram of the module is displayed ence source. For more information on the in Figure23-1. Diagrams of the possible individual Comparator module, refer to the “PIC24F comparator configurations are displayed in Family Reference Manual”, Section 46. Figure23-2. “Scalable Comparator Module” (DS39734). Each comparator has its own control register, CMxCON (Register23-1), for enabling and configuring The comparator module provides two dual input its operation. The output and event status of all three comparators. The inputs to the comparator can be comparators is provided in the CMSTAT register configured to use any one of four external analog (Register23-2). inputs, as well as a voltage reference input from either the internal band gap reference, divided by 2 (VBG/2), or the comparator voltage reference generator. FIGURE 23-1: COMPARATOR MODULE BLOCK DIAGRAM CCH<1:0> CREF EVPOL<1:0> Trigger/Interrupt CEVT CXINB CPOL Logic COE Input VIN- CXINC Select C1 Logic VIN+ CXIND C1OUT COUT Pin VBG/2 EVPOL<1:0> Trigger/Interrupt CEVT Logic CPOL COE CXINA VIN- C2 VIN+ CVREF C2OUT COUT Pin  2008-2011 Microchip Technology Inc. DS39927C-page 183

PIC24F16KA102 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON=0, CREF=x, CCH<1:0>=xx COE VIN- - Cx VIN+ Off (Read as ‘0’) CxOUT Pin Comparator CxINB < CxINA Compare Comparator CxINC < CxINA Compare CON=1, CREF=0, CCH<1:0>=00 CON=1, CREF=0, CCH<1:0>=01 COE COE CXINB VIN- - CXINC VIN- - Cx Cx VIN+ VIN+ CXINA CxOUT CXINA CxOUT Pin Pin Comparator CxIND < CxINA Compare Comparator VBG/2 < CxINA Compare CON=1, CREF=0, CCH<1:0>=10 CON=1, CREF=0, CCH<1:0>=11 COE COE CXIND VIN- - VBG/2 VIN- - Cx Cx VIN+ VIN+ CXINA CxOUT CXINA CxOUT Pin Pin Comparator CxINB < CVREF Compare Comparator CxINC < CVREF Compare CON=1, CREF=1, CCH<1:0>=00 CON=1, CREF=1, CCH<1:0>=01 COE COE CXINB VIN- - CXINC VIN- - Cx Cx VIN+ VIN+ CVREF CxOUT CVREF CxOUT Pin Pin Comparator CxIND < CVREF Compare Comparator VBG/2 < CVREF Compare CON=1, CREF=1, CCH<1:0>=10 CON=1, CREF=1, CCH<1:0>=11 COE COE CXIND VIN- - VBG/2 VIN- - Cx Cx VIN+ VIN+ CVREF CxOUT CVREF CxOUT Pin Pin DS39927C-page 184  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0 CON COE CPOL CLPWR — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12 CLPWR: Comparator Low-Power Mode Select bit 1 = Comparator operates in Low-Power mode 0 = Comparator does not operate in Low-Power mode bit 11-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT=0) 10 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled  2008-2011 Microchip Technology Inc. DS39927C-page 185

PIC24F16KA102 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED) bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CxIND pin 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to CxINB pin REGISTER 23-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC CMIDL — — — — — C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC — — — — — — C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Disable comparator interrupts when the device enters Idle mode; the module is still enabled 0 = Continue operation of all enabled comparators in Idle mode bit 14-10 Unimplemented: Read as ‘0’ bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON<9>). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). bit 7-2 Unimplemented: Read as ‘0’ bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>). DS39927C-page 186  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 24.0 COMPARATOR VOLTAGE 24.1 Configuring the Comparator REFERENCE Voltage Reference The comparator voltage reference module is controlled Note: This data sheet summarizes the features through the CVRCON register (Register24-1). The of this group of PIC24F devices. It is not comparator voltage reference provides two ranges of intended to be a comprehensive refer- output voltage, each with 16 distinct levels. The range ence source. For more information on the to be used is selected by the CVRR bit (CVRCON<5>). Comparator Voltage Reference, refer to The primary difference between the ranges is the size the “PIC24F Family Reference Manual”, Section 20. “Comparator Voltage of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. Reference Module” (DS39709). The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREFoutput. FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ AVDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U 16 Steps M 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 AVSS  2008-2011 Microchip Technology Inc. DS39927C-page 187

PIC24F16KA102 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF- 0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection 0  CVR<3:0>  15 bits When CVRR = 1 and CVRSS = 0: CVREF = (CVR<3:0>/24) * (CVRSRC) When CVRR = 0 and CVRSS = 0: CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) * (CVRSRC) When CVRR = 1 and CVRSS = 1: CVREF = ((CVR<3:0>/24) * (CVRSRC)) + VREF- When CVRR = 0 and CVRSS = 1: CVREF = (1/4 (CVRSRC) + (CVR<3:0>/32) * (CVRSRC)) + VREF- DS39927C-page 188  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 25.0 CHARGE TIME source polarity selection, and edge sequencing. The MEASUREMENT UNIT (CTMU) CTMUICON register selects the current range of current source and trims the current. Note: This data sheet summarizes the features of this group of PIC24F devices. It is not 25.1 Measuring Capacitance intended to be a comprehensive reference The CTMU module measures capacitance by source. For more information on the generating an output pulse with a width equal to the Charge Measurement Unit, refer to the time between edge events on two separate input chan- “PIC24F Family Reference Manual”, nels. The pulse edge events to both input channels can Section 11. “Charge Time Measurement be selected from four sources: two internal peripheral Unit (CTMU)” (DS39724). modules (OC1 and Timer1) and two external pins The Charge Time Measurement Unit (CTMU) is a (CTED1 and CTED2). This pulse is used with the mod- flexible analog module that provides charge measure- ule’s precision current source to calculate capacitance ment, accurate differential time measurement between according to the relationship: pulse sources and asynchronous pulse generation. Its dV I = C • key features include: dT • Four-edge input trigger sources For capacitance measurements, the A/D Converter • Polarity control for each edge source samples an external capacitor (CAPP) on one of its • Control of edge sequence input channels, after the CTMU output’s pulse. A • Control of response to edges precision resistor (RPR) provides current source • Time measurement resolution of one nanosecond calibration on a second A/D channel. After the pulse • Accurate current source suitable for capacitive ends, the converter determines the voltage on the measurement capacitor. The actual calculation of capacitance is Together with other on-chip analog modules, the CTMU performed in software by the application. can be used to precisely measure time, measure Figure25-1 displays the external connections used for capacitance, measure relative changes in capacitance, capacitance measurements, and how the CTMU and or generate output pulses that are independent of the A/D modules are related in this application. This example system clock. The CTMU module is ideal for interfacing also shows the edge events coming from Timer1, but with capacitive-based touch sensors. other configurations using external edge sources are The CTMU is controlled through two registers: possible. A detailed discussion on measuring capaci- CTMUCON and CTMUICON. CTMUCON enables the tance and time with the CTMU module is provided in the module, and controls edge source selection, edge “PIC24F Family Reference Manual”. FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse A/D Converter ANx ANY CAPP RPR  2008-2011 Microchip Technology Inc. DS39927C-page 189

PIC24F16KA102 FAMILY 25.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the Time measurements on the pulse width can be similarly internal current source is connected to the B input of performed using the A/D module’s internal capacitor Comparator 2. A capacitor (CDELAY) is connected to (CAD) and a precision resistor for current calibration. the Comparator 2 pin, C2INB, and the comparator Figure25-2 displays the external connections used for voltage reference, CVREF, is connected to C2INA. time measurements, and how the CTMU and A/D CVREF is then configured for a specific trip point. The modules are related in this application. This example module begins to charge CDELAY when an edge event also shows both edge events coming from the external is detected. When CDELAY charges above the CVREF CTED pins, but other configurations using internal trip point, a pulse is output on CTPLS. The length of the edge sources are possible. pulse delay is determined by the value of CDELAY and the CVREF trip point. 25.3 Pulse Generation and Delay Figure25-3 shows the external connections for pulse The CTMU module can also generate an output pulse generation, as well as the relationship of the different with edges that are not synchronous with the device’s analog modules required. While CTED1 is shown as system clock. More specifically, it can generate a pulse the input pulse source, other options are available. A with a programmable delay from an edge event input to detailed discussion on pulse generation with the CTMU the module. module is provided in the “PIC24F Family Reference Manual”. FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTED1 EDG1 Current Source CTED2 EDG2 Output Pulse A/D Converter ANx CAD RPR FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTMU CTED1 EDG1 CTPLS Current Source Comparator C2INB - C2 CDELAY CVREF DS39927C-page 190  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response  2008-2011 Microchip Technology Inc. DS39927C-page 191

PIC24F16KA102 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred REGISTER 25-2: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100000 = Maximum negative change from nominal current bit 9-8 IRNG<1:0>: Current Source Range Select bits 11 = 100  Base current 10 = 10  Base current 01 = Base current level (0.55A nominal) 00 = Current source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS39927C-page 192  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 26.0 SPECIAL FEATURES 26.1 Configuration Bits Note: This data sheet summarizes the features The Configuration bits can be programmed (read as ‘0’), of this group of PIC24F devices. It is not or left unprogrammed (read as ‘1’), to select various intended to be a comprehensive refer- device configurations. These bits are mapped, starting ence source. For more information on the at program memory location, F80000h. A complete list is Watchdog Timer, High-Level Device inte- provided in Table26-1. A detailed explanation of the gration and Programming Diagnostics, various bit functions is provided in Register26-1 through refer to the individual sections of the Register26-8. “PIC24F Family Reference Manual” The address, F80000h, is beyond the user program provided below: memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh), which can only be • Section 9. “Watchdog Timer (WDT)” accessed using table reads and table writes. (DS39697) • Section 36. “High-Level Integration TABLE 26-1: CONFIGURATION REGISTERS with Programmable High/ LOCATIONS Low-Voltage Detect (HLVD)” (DS39725) Configuration Address • Section 33. “Programming and Register Diagnostics” (DS39716) FBS F80000 PIC24F16KA102 family devices include several FGS F80004 features intended to maximize application flexibility and FOSCSEL F80006 reliability, and minimize cost through elimination of FOSC F80008 external components. These are: FWDT F8000A • Flexible Configuration FPOR F8000C • Watchdog Timer (WDT) FICD F8000E • Code Protection FDS F80010 • In-Circuit Serial Programming™ (ICSP™) • In-Circuit Emulation REGISTER 26-1: FBS: BOOT SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — BSS2 BSS1 BSS0 BWRP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-1 BSS<2:0>: Boot Segment Program Flash Code Protection bits 111 = No boot program Flash segment 011 = Reserved 110 = Standard security, boot program Flash segment starts at 200h, ends at 000AFEh 010 = High-security boot program Flash segment starts at 200h, ends at 000AFEh 101 = Standard security, boot program Flash segment starts at 200h, ends at 0015FEh(1) 001 = High-security, boot program Flash segment starts at 200h, ends at 0015FEh(1) 100 = Reserved 000 = Reserved bit 0 BWRP: Boot Segment Program Flash Write Protection bit 1 = Boot segment may be written 0 = Boot segment is write-protected Note 1: This selection should not be used in PIC24F08KA1XX devices.  2008-2011 Microchip Technology Inc. DS39927C-page 193

PIC24F16KA102 FAMILY REGISTER 26-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — GSS0 GWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 GSS0: General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security is enabled bit 0 GWRP: General Segment Code Flash Write Protection bit 1 = General segment may be written 0 = General segment is write-protected REGISTER 26-3: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER R/P-1 U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 IESO — — — — FNOSC2 FNOSC1 FNOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) bit 6-3 Unimplemented: Read as ‘0’ bit 2-0 FNOSC<2:0>: Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary Oscillator (XT, HS, EC) 011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = 500 kHz Low-Power FRC Oscillator with divide-by-N (LPFRCDIV) 111 = 8 MHz FRC Oscillator with divide-by-N (FRCDIV) DS39927C-page 194  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 26-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FCKSM1 FCKSM0 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 5 SOSCSEL: Secondary Oscillator Select bit 1 = Secondary oscillator is configured for high-power operation 0 = Secondary oscillator is configured for low-power operation bit 4-3 POSCFREQ<1:0>: Primary Oscillator Frequency Range Configuration bits 11 = Primary oscillator/external clock input frequency is greater than 8 MHz 10 = Primary oscillator/external clock input frequency is between 100 kHz and 8 MHz 01 = Primary oscillator/external clock input frequency is less than 100 kHz 00 = Reserved; do not use bit 2 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or 00) 0 = CLKO output is disabled bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator mode is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = External Clock mode is selected  2008-2011 Microchip Technology Inc. DS39927C-page 195

PIC24F16KA102 FAMILY REGISTER 26-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 FWDTEN: Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWDTEN bit) bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard WDT is selected; windowed WDT disabled 0 = Windowed WDT is enabled bit 5 Unimplemented: Read as ‘0’ bit 4 FWPSA: WDT Prescaler bit 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32 bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 DS39927C-page 196  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 26-6: FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 R/P-1 R/P-1 MCLRE(2) BORV1(3) BORV0(3) I2C1SEL(1) PWRTEN — BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit(2) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is disabled bit 6-5 BORV<1:0>: Brown-out Reset Enable bits(3) 11 = Brown-out Reset is set to the lowest voltage 10 = Brown-out Reset 01 = Brown-out Reset is set to the highest voltage 00 = Low-Power Brown-out Reset occurs around 2.0V bit 4 I2C1SEL: Alternate I2C1 Pin Mapping bit(1) 0 = Alternate location for SCL1/SDA1 pins 1 = Default location for SCL1/SDA1 pins bit 3 PWRTEN: Power-up Timer Enable bit 0 = PWRT is disabled 1 = PWRT is enabled bit 2 Unimplemented: Read as ‘0’ bit 1-0 BOREN<1:0>: Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled 10 = Brown-out Reset is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled 01 = Brown-out Reset is controlled with the SBOREN bit setting 00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled Note 1: Applies only to 28-pin devices. 2: The MCLRE fuse can only be changed when using the VPP-Based ICSP™ mode entry. This prevents a user from accidentally locking out the device from the low-voltage test entry. 3: Refer to Section29.0, Electrical Characteristics for the BOR voltages.  2008-2011 Microchip Technology Inc. DS39927C-page 197

PIC24F16KA102 FAMILY REGISTER 26-7: FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 DEBUG — — — — — FICD1 FICD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 FICD<1:0:> ICD Pin Select bits 11 = PGC1/PGD1 are used for programming and debugging the device 10 = PGC2/PGD2 are used for programming and debugging the device 01 = PGC3/PGD3 are used for programming and debugging the device 00 = Reserved; do not use DS39927C-page 198  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY REGISTER 26-8: FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 DSWDTEN DSBOREN RTCOSC DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled bit 6 DSBOREN: Deep Sleep/Low-Power BOR Enable bit (does not affect operation in non Deep Sleep modes) 1 = Deep Sleep BOR is enabled in Deep Sleep 0 = Deep Sleep BOR is disabled in Deep Sleep bit 5 RTCOSC: RTCC Reference Clock Select bit 1 = RTCC uses SOSC as a reference clock 0 = RTCC uses LPRC as a reference clock bit 4 DSWDTOSC: DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as a reference clock 0 = DSWDT uses SOSC as a reference clock bit 3-0 DSWDTPS<3:0>: Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) nominal 1110 = 1:536,870,912 (6.4 days) nominal 1101 = 1:134,217,728 (38.5 hours) nominal 1100 = 1:33,554,432 (9.6 hours) nominal 1011 = 1:8,388,608 (2.4 hours) nominal 1010 = 1:2,097,152 (36 minutes) nominal 1001 = 1:524,288 (9 minutes) nominal 1000 = 1:131,072 (135 seconds) nominal 0111 = 1:32,768 (34 seconds) nominal 0110 = 1:8,192 (8.5 seconds) nominal 0101 = 1:2,048 (2.1 seconds) nominal 0100 = 1:512 (528 ms) nominal 0011 = 1:128 (132 ms) nominal 0010 = 1:32 (33 ms) nominal 0001 = 1:8 (8.3 ms) nominal 0000 = 1:2 (2.1 ms) nominal  2008-2011 Microchip Technology Inc. DS39927C-page 199

PIC24F16KA102 FAMILY REGISTER 26-9: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘0’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 00001011 = PIC24F16KA102 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 00000011 = PIC24F16KA102 00001010 = PIC24F08KA102 00000001 = PIC24F16KA101 00001000 = PIC24F08KA101 REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Minor Revision Identifier bits DS39927C-page 200  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 26.2 Watchdog Timer (WDT) executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after For the PIC24F16KA102 family of devices, the WDT is the device wakes up. driven by the LPRC oscillator. When the WDT is The WDT Flag bit, WDTO (RCON<4>), is not enabled, the clock source is also enabled. automatically cleared following a WDT time-out. To The nominal WDT clock source from LPRC is 31kHz. detect subsequent WDT events, the flag must be This feeds a prescaler that can be configured for either cleared in software. 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. Note: The CLRWDT and PWRSAV instructions With a 31kHz input, the prescaler yields a nominal clear the prescaler and postscaler counts WDT time-out period (TWDT) of 1ms in 5-bit mode or when executed. 4ms in 7-bit mode. 26.2.1 WINDOWED OPERATION A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The Watchdog Timer has an optional Fixed Window The postscaler is controlled by the Configuration bits, mode of operation. In this Windowed mode, CLRWDT WDTPS<3:0> (FWDT<3:0>), which allow the selection instructions can only reset the WDT during the last of a total of 16 settings, from 1:1 to 1:32,768. Using the 1/4of the programmed WDT period. A CLRWDT instruc- prescaler and postscaler time-out periods, ranging tion executed before that window causes a WDT from 1ms to 131 seconds, can be achieved. Reset, similar to a WDT time-out. The WDT, prescaler and postscaler are reset: Windowed WDT mode is enabled by programming the Configuration bit, WINDIS (FWDT<6>), to ‘0’. • On any device Reset • On the completion of a clock switch, whether 26.2.2 CONTROL REGISTER invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware The WDT is enabled or disabled by the FWDTEN (i.e., Fail-Safe Clock Monitor) Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) The WDT can be optionally controlled in software when • When the device exits Sleep or Idle mode to the FWDTEN Configuration bit has been programmed resume normal operation to ‘0’. The WDT is enabled in software by setting the • By a CLRWDT instruction During normal execution SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software If the WDT is enabled, it will continue to run during WDT option allows the user to enable the WDT for Sleep or Idle modes. When the WDT time-out occurs, critical code segments and disable the WDT during the device will wake the device and code execution will non-critical segments for maximum power savings. continue from where the PWRSAV instruction was FIGURE 26-1: WDT BLOCK DIAGRAM SWDTEN LPRC Control FWDTEN Wake from Sleep FWPSA WDTPS<3:0> Prescaler WDT Postscaler WDT Overflow LPRC Input (5-Bit/7-Bit) Counter 1:1 to 1:32.768 Reset 31 kHz 1 ms/4 ms All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode  2008-2011 Microchip Technology Inc. DS39927C-page 201

PIC24F16KA102 FAMILY 26.3 Deep Sleep Watchdog Timer 26.5 In-Circuit Serial Programming (DSWDT) PIC24F16KA102 family microcontrollers can be In PIC24F16KA102 family devices, in addition to the serially programmed while in the end application circuit. WDT module, a DSWDT module is present which runs This is simply done with two lines for clock (PGCx) and while the device is in Deep Sleep, if enabled. It is data (PGDx), and three other lines for power, ground driven by either the SOSC or LPRC oscillator. The and the programming voltage. This allows customers to clock source is selected by the Configuration bit, manufacture boards with unprogrammed devices and DSWDTOSC (FDS<4>). then program the microcontroller just before shipping the product. This also allows the most recent firmware The DSWDT can be configured to generate a time-out or a custom firmware to be programmed. at 2.1 ms to 25.7 days by selecting the respective postscaler. The postscaler can be selected by the 26.6 In-Circuit Debugger Configuration bits, DSWDTPS<3:0> (FDS<3:0>). When the DSWDT is enabled, the clock source is also When MPLAB® ICD 2 is selected as a debugger, the enabled. in-circuit debugging functionality is enabled. This DSWDT is one of the sources that can wake-up the function allows simple debugging functions when used device from Deep Sleep mode. with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and 26.4 Program Verification and EMUDx (Emulation/Debug Data) pins. Code Protection To use the in-circuit debugger function of the device, the design must implement ICSP connections to For all devices in the PIC24F16KA102 family, code MCLR, VDD, VSS, PGCx, PGDx and the protection for the boot segment is controlled by the EMUDx/EMUCx pin pair. In addition, when the feature Configuration bit, BSS0, and the general segment by is enabled, some of the resources are not available for the Configuration bit, GSS0. These bits inhibit external general use. These resources include the first 80 bytes reads and writes to the program memory space; this of data RAM and two I/O pins. has no direct effect in normal execution mode. Write protection is controlled by bit, BWRP, for the boot segment and bit, GWRP, for the general segment in the Configuration Word. When these bits are programmed to ‘0’, internal write and erase operations to program memory are blocked. DS39927C-page 202  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 27.0 DEVELOPMENT SUPPORT 27.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C® for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. Preliminary  2008-2011 Microchip Technology Inc. DS39927C-page 203

PIC24F16KA102 FAMILY 27.2 MPLAB C Compilers for Various 27.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 27.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 27.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 27.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Preliminary DS39927C-page 204  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 27.7 MPLAB SIM Software Simulator 27.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 27.10 PICkit 3 In-Circuit Debugger/ Programmer and 27.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. Preliminary  2008-2011 Microchip Technology Inc. DS39927C-page 205

PIC24F16KA102 FAMILY 27.11 PICkit 2 Development 27.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 27.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. Preliminary DS39927C-page 206  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 28.0 INSTRUCTION SET SUMMARY The literal instructions that involve data movement may use some of the following operands: Note: This chapter is a brief summary of the • A literal value to be loaded into a W register or file PIC24F instruction set architecture and is register (specified by the value of ‘k’) not intended to be a comprehensive • The W register or file register, where the literal reference source. value is to be loaded (specified by ‘Wb’ or ‘f’) The PIC24F instruction set adds many enhancements However, literal instructions that involve arithmetic or to the previous PIC® MCU instruction sets, while logical operations use some of the following operands: maintaining an easy migration from previous PIC MCU • The first source operand, which is a register ‘Wb’ instruction sets. Most instructions are a single program without any address modifier memory word. Only three instructions require two program memory locations. • The second source operand, which is a literal value Each single-word instruction is a 24-bit word divided • The destination of the result (only if not the same into an 8-bit opcode, which specifies the instruction as the first source operand), which is typically a type and one or more operands, which further specify register ‘Wd’ with or without an address modifier the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic The control instructions may use some of the following categories: operands: • Word or byte-oriented operations • A program memory address • Bit-oriented operations • The mode of the table read and table write • Literal operations instructions • Control operations All instructions are a single word, except for certain double-word instructions, which were made Table28-1 lists the general symbols used in describing double-word instructions so that all of the required the instructions. The PIC24F instruction set summary information is available in these 48 bits. In the second in Table28-2 lists all the instructions, along with the word, the 8MSbs are ‘0’s. If this second word is status flags affected by each instruction. executed as an instruction (by itself), it will execute as Most word or byte-oriented W register instructions a NOP. (including barrel shift instructions) have three Most single-word instructions are executed in a single operands: instruction cycle, unless a conditional test is true or the • The first source operand, which is typically a Program Counter (PC) is changed as a result of the register ‘Wb’ without any address modifier instruction. In these cases, the execution takes two • The second source operand, which is typically a instruction cycles, with the additional instruction register ‘Ws’ with or without an address modifier cycle(s) executed as a NOP. Notable exceptions are the • The destination of the result, which is typically a BRA (unconditional/computed branch), indirect register ‘Wd’ with or without an address modifier CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word However, word or byte-oriented file register instructions instructions but take two or three cycles. have two operands: Certain instructions that involve skipping over the • The file register, specified by the value, ‘f’ subsequent instruction require either two or three • The destination, which could either be the file cycles if the skip is performed, depending on whether register ‘f’ or the W0 register, which is denoted as the instruction being skipped is a single-word or ‘WREG’ two-word instruction. Moreover, double-word moves Most bit-oriented instructions (including simple require two cycles. The double-word instructions rotate/shift instructions) have two operands: execute in two instruction cycles. • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’)  2008-2011 Microchip Technology Inc. DS39927C-page 207

PIC24F16KA102 FAMILY TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0..W15} Wns One of 16 source working registers {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39927C-page 208  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2008-2011 Microchip Technology Inc. DS39927C-page 209

PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep COM COM f f = f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C, DC, N, OV, Z (Wb – Ws – C) CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DS39927C-page 210  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC INC f f = f + 1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z IOR IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None POP.S Pop Shadow Registers 1 1 All PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None  2008-2011 Microchip Technology Inc. DS39927C-page 211

PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None DS39927C-page 212  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N  2008-2011 Microchip Technology Inc. DS39927C-page 213

PIC24F16KA102 FAMILY NOTES: DS39927C-page 214  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24F16KA102 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F16KA102 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +175°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.0V Voltage on any combined analog and digital pin, with respect to VSS ...........................................-0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V) Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin (1)..........................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (1)..............................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table29-1). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2008-2011 Microchip Technology Inc. DS39927C-page 215

PIC24F16KA102 FAMILY 29.1 DC Characteristics FIGURE 29-1: PIC24F16KA102 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.60V 3.00V 3.00V )D D V ( e g 1.80V a t ol V 0 0 8 MHz 16 MHz 24 MHz 32 MHz Frequency (MHz) Note: For Industrial temperatures, for frequencies between 8MHz and 32MHz, FMAX = (20 MHz/V) * (VDD – 1.8V) + 8 MHz. FIGURE 29-2: PIC24F16KA102 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 3.60V 3.60V 3.00V 3.00V ) D D V ( e g 1.80V a t ol V 0 0 8 MHz 16 MHz 24 MHz 32 MHz Frequency (MHz) Note: For Extended temperatures, for frequencies between 8MHz and 24MHz, FMAX = (13.33 MHz/V) * (VDD – 1.8V) + 8 MHz. DS39927C-page 216  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +175 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 20-Pin PDIP JA 62.4 — °C/W 1 Package Thermal Resistance, 28-Pin SPDIP JA 60 — °C/W 1 Package Thermal Resistance, 20-Pin SSOP JA 108 — °C/W 1 Package Thermal Resistance, 28-Pin SSOP JA 71 — °C/W 1 Package Thermal Resistance, 20-Pin SOIC JA 75 — °C/W 1 Package Thermal Resistance, 28-Pin SOIC JA 80.2 — °C/W 1 Package Thermal Resistance, 20-Pin QFN JA 43 — °C/W 1 Package Thermal Resistance, 28-Pin QFN JA 32 — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.  2008-2011 Microchip Technology Inc. DS39927C-page 217

PIC24F16KA102 FAMILY TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DC10 VDD Supply Voltage 1.8 — 3.6 V DC12 VDR RAM Data Retention 1.5 — — V Voltage(2) DC16 VPOR VDD Start Voltage VSS — 0.7 V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-3.3V in 0.1s to Ensure Internal 0-2.5V in 60ms Power-on Reset Signal Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: This is the limit to which VDD can be lowered without losing RAM data. TABLE 29-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. DC18 VHLVD HLVD Voltage on VDD HLVDL<3:0> = 0000 — 1.85 1.94 V Transition HLVDL<3:0> = 0001 1.81 1.90 2.00 V HLVDL<3:0> = 0010 1.85 1.95 2.05 V HLVDL<3:0> = 0011 1.90 2.00 2.10 V HLVDL<3:0> = 0100 1.95 2.05 2.15 V HLVDL<3:0> = 0101 2.06 2.17 2.28 V HLVDL<3:0> = 0110 2.12 2.23 2.34 V HLVDL<3:0> = 0111 2.24 2.36 2.48 V HLVDL<3:0> = 1000 2.31 2.43 2.55 V HLVDL<3:0> = 1001 2.47 2.60 2.73 V HLVDL<3:0> = 1010 2.64 2.78 2.92 V HLVDL<3:0> = 1011 2.74 2.88 3.02 V HLVDL<3:0> = 1100 2.85 3.00 3.15 V HLVDL<3:0> = 1101 2.96 3.12 3.28 V HLVDL<3:0> = 1110 3.22 3.39 3.56 V DS39927C-page 218  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY FIGURE 29-3: BROWN-OUT RESET CHARACTERISTICS VDDCORE (Device not in Brown-out Reset) BO15 BO10 (Device in Brown-out Reset) SY25 Reset (Due to BOR) TVREG + TRST TABLE 29-5: BOR TRIP POINTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ Max Units Conditions No. DC19 VBOR BOR Voltage on VDD Transition BOR = 00 — — — — LPBOR(1) BOR = 01 2.92 3 3.08 V BOR = 10 2.63 2.7 2.77 V BOR = 11 1.75 1.82 1.85 V DC14 VBHYS BOR Hysteresis — 5 — mV Note 1: LPBOR re-arms the POR circuit, but does not cause a BOR. LPBOR can be used to ensure a POR after the sup- ply voltage rises to a safe operating level. It does not stop code execution after the supply voltage falls below a chosen trip point.  2008-2011 Microchip Technology Inc. DS39927C-page 219

PIC24F16KA102 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max Units Conditions IDD Current(2) DC20 330 -40°C DS20a 330 +25°C DC20b 195 330 A +60°C 1.8V DC20c 330 +85°C DC20d 500 +125°C 0.5 MIPS, DC20e 590 -40°C FOSC = 1 MHz DC20f 590 +25°C DC20g 365 645 A +60°C 3.3V DC20h 720 +85°C DC20i 800 +125°C DC22 600 -40°C DC22a 600 +25°C DC22b 363 600 A +60°C 1.8V DC22c 600 +85°C DC22d 800 +125°C 1 MIPS, DC22e 1100 -40°C FOSC = 2 MHz DC22f 1100 +25°C DC22g 695 1100 A +60°C 3.3V DC22h 1100 +85°C DC22i 1500 +125°C DC23 18 -40°C DC23a 18 +25°C 16 MIPS, DC23b 11 18 mA +60°C 3.3V FOSC = 32 MHz DC23c 18 +85°C DC23d 18 +125°C DC27 3.40 -40°C DC27a 3.40 +25°C DC27b 2.25 3.40 mA +60°C 2.5V DC27c 3.40 +85°C DC27d 3.40 +125°C FRC (4 MIPS), DC27e 4.60 -40°C FOSC = 8 MHz DC27f 4.60 +25°C DC27g 3.05 4.60 mA +60°C 3.3V DC27h 4.60 +85°C DC27i 5.40 +125°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: • EC mode with clock input driven with a square wave rail-to-rail • I/Os are configured as outputs, driven low • MCLR – VDD • WDT FSCM is disabled • SRAM, program and data memory are active • All PMD bits are set except for modules being measured DS39927C-page 220  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter No. Typical(1) Max Units Conditions IDD Current(2) DC31 28 -40°C DC31a 28 +25°C 8 A 1.8V DC31b 28 +60°C DC31c 28 +85°C DC31d 55 -40°C LPRC (31 kHz) DC31e 55 +25°C DC31f 15 55 A +60°C 3.3V DC31g 55 +85°C DC31h 250 +125°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: • EC mode with clock input driven with a square wave rail-to-rail • I/Os are configured as outputs, driven low • MCLR – VDD • WDT FSCM is disabled • SRAM, program and data memory are active • All PMD bits are set except for modules being measured  2008-2011 Microchip Technology Inc. DS39927C-page 221

PIC24F16KA102 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Typical(1) Max Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set(2) DC40 100 -40°C DC40a 100 +25°C DC40b 48 100 A +60°C 1.8V DC40c 100 +85°C DC40d 100 +125°C 0.5 MIPS, DC40e 215 -40°C FOSC = 1 MHz DC40f 215 +25°C DC40g 106 215 A +60°C 3.3V DC40h 215 +85°C DC40i 450 +125°C DC42 200 -40°C DC42a 200 +25°C DC42b 94 200 A +60°C 1.8V DC42c 200 +85°C DC42d 300 +125°C 1 MIPS, DC42e 395 -40°C FOSC = 2 MHz DC42f 395 +25°C DC42g 160 395 A +60°C 3.3V DC42h 395 +85°C DC42i 600 +125°C DC43 6.0 -40°C DC43a 6.0 +25°C 16 MIPS, DC43b 3.1 6.0 mA +60°C 3.3V FOSC = 32 MHz DC43c 6.0 +85°C DC43d 6.0 +125°C DC44 0.74 -40°C DC44a 0.74 +25°C DC44b 0.56 0.74 mA +60°C 1.8V DC44c 0.74 +85°C DC44d 0.74 +125°C FRC (4 MIPS), DC44e 1.50 -40°C FOSC = 8 MHz DC44f 1.50 +25°C DC44g 0.95 1.50 mA +60°C 3.3V DC44h 1.50 +85°C DC44i 1.50 +125°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: • Core is off • EC mode with the clock input driven with a square wave rail-to-rail • I/Os are configured as outputs, driven low • MCLR – VDD • WDT FSCM are disabled • SRAM, program and data memory are active • All PMD bits are set except for the modules being measured DS39927C-page 222  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param No. Typical(1) Max Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set(2) DC50 18 -40°C DC50a 18 +25°C 2 1.8V DC50b 18 +60°C DC50c 18 +85°C DC50d 40 A -40°C LPRC (31 kHz) DC50e 40 +25°C DC50f 4 40 +60°C 3.3V DC50g 40 +85°C DC50h 60 +125°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: • Core is off • EC mode with the clock input driven with a square wave rail-to-rail • I/Os are configured as outputs, driven low • MCLR – VDD • WDT FSCM are disabled • SRAM, program and data memory are active • All PMD bits are set except for the modules being measured  2008-2011 Microchip Technology Inc. DS39927C-page 223

PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC60 0.200 -40°C DC60a 0.200 +25°C DC60b 0.025 0.870 A +60°C 1.8V DC60c 1.350 +85°C DC60d 10.00 +125°C Base Power-Down Current DC60e 0.540 -40°C (Sleep)(3) DC60f 0.540 +25°C DC60g 0.105 1.680 A +60°C 3.3V DC60h 2.450 +85°C DC60i 11.00 +125°C DC70 0.150 -40°C DC70a 0.150 +25°C DC70b 0.020 0.430 A +60°C 1.8V DC70c 0.630 +85°C DC70d 3.00 +125°C Base Deep Sleep Current DC70e 0.300 -40°C DC70f 0.300 +25°C DC70g 0.035 0.700 A +60°C 3.3V DC70h 0.980 +85°C DC70i 5.00 +125°C DC61 0.65 -40°C DC61a 0.65 +25°C DC61b 0.55 0.65 A +60°C 1.8V DC61c 0.65 +85°C DC61d 1.20 +125°C Watchdog Timer Current (WDT)(3,4) DC61e 0.95 -40°C DC61f 0.95 +25°C DC61g 0.87 0.95 A +60°C 3.3V DC61h 0.95 +85°C DC61i 1.50 +125°C Note 1: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low. WDT, etc., are all switched off. 3: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Current applies to Sleep only. 5: Current applies to Sleep and Deep Sleep. 6: Current applies to Deep Sleep only. DS39927C-page 224  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC62 0.650 -40°C DC62a 0.650 +25°C DC62b 0.450 0.650 A +60°C 1.8V DC62c 0.650 +85°C DC62d — +125°C Timer1 w/32 kHz Crystal: T132 DC62e 0.980 -40°C (SOSC – LP)(3) DC62f 0.980 +25°C DC62g 0.730 0.980 A +60°C 3.3V DC62h 0.980 +85°C DC62i — +125°C DC64 7.10 -40°C DC64a 7.10 +25°C DC64b 5.5 7.80 A +60°C 1.8V DC64c 8.30 +85°C DC64d 10.00 +125°C HLVD(3,4) DC64e 7.10 -40°C DC64f 7.10 +25°C DC64g 6.2 7.80 A +60°C 3.3V DC64h 8.30 +85°C DC64i 9.00 +125°C DC63 6.60 -40°C DC63a 6.60 +25°C DC63b 4.5 6.60 A +60°C 3.3V BOR(3,4) DC63c 6.60 +85°C DC63d 9.00 +125°C DC62 0.65 -40°C DC62a 0.65 +25°C DC62b 0.49 0.65 A +60°C 1.8V DC62c 0.65 +85°C DC62d 0.98 +125°C RTCC(3,5) DC62e 0.98 -40°C DC62f 0.98 +25°C DC62g 0.80 0.98 A +60°C 3.3V DC62h 0.98 +85°C DC62i 0.98 +125°C Note 1: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low. WDT, etc., are all switched off. 3: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Current applies to Sleep only. 5: Current applies to Sleep and Deep Sleep. 6: Current applies to Deep Sleep only.  2008-2011 Microchip Technology Inc. DS39927C-page 225

PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC70 0.200 -40°C DC70a 0.200 +25°C DC70b 0.045 0.200 A +60°C 1.8V DC70c 0.200 +85°C DC70d 1.45 +125°C LPBOR(3,4) DC70e 0.200 -40°C DC70f 0.200 +25°C DC70g 0.095 0.200 A +60°C 3.3V DC70h 0.200 +85°C DC70i 1.55 +125°C DC71 0.55 -40°C DC71a 0.55 +25°C DC71b 0.35 0.55 A +60°C 1.8V DC71c 0.55 +85°C DC71d 1.70 +125°C Deep Sleep Watchdog Timer: DC71e 0.75 -40°C DSWDT (SOSC – LP)(6) DC71f 0.75 +25°C DC71g 0.55 0.75 A +60°C 3.3V DC71h 0.75 +85°C DC71i 2.10 +125°C DC72 0.200 -40°C DC72a 0.200 +25°C DC72b 0.005 0.200 A +60°C 1.8V DC72c 0.200 +85°C DC72d 0.200 +125°C Deep Sleep BOR (DSBOR)(6) DC72e 0.200 -40°C DC72f 0.200 +25°C DC72g 0.010 0.200 A +60°C 3.3V DC72h 0.200 +85°C DC72i 0.200 +125°C Note 1: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as outputs and set low. WDT, etc., are all switched off. 3: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Current applies to Sleep only. 5: Current applies to Sleep and Deep Sleep. 6: Current applies to Deep Sleep only. DS39927C-page 226  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage(4) — — — — DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C™ Buffer VSS — 0.3 VDD V SMBus disabled DI19 I/O Pins with SMBus Buffer VSS — 0.8 V SMBus enabled VIH(5) Input High Voltage(4) — — — — DI20 I/O Pins: with Analog Functions 0.8 VDD — VDD V Digital Only 0.8 VDD — VDD V DI25 MCLR 0.8 VDD — VDD V DI26 OSCI (XT mode) 0.7 VDD — VDD V DI27 OSCI (HS mode) 0.7 VDD — VDD V DI28 I/O Pins with I2C Buffer: with Analog Functions 0.7 VDD — VDD V Digital Only 0.7 VDD — VDD V DI29 I/O Pins with SMBus 2.1 — VDD V 2.5V  VPIN  VDD DI30 ICNPU CNx Pull-up Current 50 250 500 A VDD = 3.3V, VPIN = VSS IIL Input Leakage Current(2,3) DI50 I/O Ports — 0.050 ±0.100 A VSS  VPIN  VDD, Pin at high-impedance DI51 VREF+, VREF-, AN0, AN1 — 0.300 ±0.500 A VSS  VPIN  VDD, Pin at high-impedance DI55 MCLR — — ±5.0 A VSS VPIN VDD DI56 OSCI — — ±5.0 A VSS VPIN VDD, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Refer to Table1-2 for I/O pin buffer types. 5: VIH requirements are met when internal pull-ups are enabled.  2008-2011 Microchip Technology Inc. DS39927C-page 227

PIC24F16KA102 FAMILY TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. VOL Output Low Voltage DO10 All I/O Pins — — 0.4 V IOL = 4.0 mA, VDD = 3.6V — — 0.4 V IOL = 3.5 mA, VDD = 2.0V DO16 OSC2/CLKO — — 0.4 V IOL = 8.0 mA, VDD = 3.6V — — 0.4 V IOL = 4.5 mA, VDD = 1.8V VOH Output High Voltage DO20 All I/O Pins 3 — — V IOH = -3.0 mA, VDD = 3.6V 1.8 — — V IOH = -1.0 mA, VDD = 2.0V DO26 OSC2/CLKO 3 — — V IOH = -2.5 mA, VDD = 3.6V 1.8 — — V IOH = -1.0 mA, VDD = 2.0V Note 1: Data in “Typ” column is at 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS39927C-page 228  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10,000(2) — — E/W D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D135 IDDP Supply Current During — 10 — mA Programming Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: Self-write and block erase. TABLE 29-12: DC CHARACTERISTICS: DATA EEPROM MEMORY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. Data EEPROM Memory D140 EPD Cell Endurance 100,000 — — E/W D141 VPRD VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D143A TIWD Self-Timed Write Cycle — 4 — ms Time D143B TREF Number of Total Write/Erase — 10M — E/W Cycles Before Refresh D144 TRETDD Characteristic Retention 40 — — Year Provided no other specifications are violated D145 IDDPD Supply Current During — 7 — mA Programming Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2008-2011 Microchip Technology Inc. DS39927C-page 229

PIC24F16KA102 FAMILY TABLE 29-13: COMPARATOR DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage* — 20 40 mV D301 VICM Input Common Mode Voltage* 0 — VDD V D302 CMRR Common Mode Rejection 55 — — dB Ratio* * Parameters are characterized but not tested. TABLE 29-14: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Comments No. VRD310 CVRES Resolution VDD/24 — VDD/32 LSb VRD311 CVRAA Absolute Accuracy — — AVDD – 1.5 LSb VRD312 CVRUR Unit Resistor Value (R) — 2k —  TABLE 29-15: INTERNAL VOLTAGE REFERENCES Operating Conditions: 2.0V < VDD < 3.6V Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Comments No. VBG Internal Band Gap Reference 1.14 1.2 1.26 V TIRVST Internal Reference Stabilization Time — 200 250 s TABLE 29-16: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. IOUT1 CTMU Current Source, — 550 — nA CTMUICON<1:0> = 01 Base Range IOUT2 CTMU Current Source, — 5.5 — A CTMUICON<1:0> = 10 10x Range IOUT3 CTMU Current Source, — 55 — A CTMUICON<1:0> = 11 100x Range Note 1: Nominal value at the center point of the current trim range (CTMUICON<7:2> = 000000). DS39927C-page 230  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24F16KA102 family AC characteristics and timing parameters. TABLE 29-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial AC CHARACTERISTICS -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Section29.1 “DC Characteristics”. FIGURE 29-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSCO VSS 15 pF for OSCO output TABLE 29-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO50 COSC2 OSCO/CLKO pin — — 15 pF In XT and HS modes when external clock is used to drive OSCI DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2008-2011 Microchip Technology Inc. DS39927C-page 231

PIC24F16KA102 FAMILY FIGURE 29-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 29-19: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 1.8 to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. OS10 FOSC External CLKI Frequency DC — 32 MHz EC (External clocks allowed 4 — 8 MHz ECPLL only in EC mode)(2) Oscillator Frequency(2) 0.2 — 4 MHz XT 4 — 25 MHz HS 4 — 8 MHz HSPLL 31 — 33 kHz SOSC OS20 TOSC TOSC = 1/FOSC — — — — See Parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(3) 62.5 — DC ns OS30 TosL, External Clock in (OSCI) 0.45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock in (OSCI) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(4) — 6 10 ns OS41 TckF CLKO Fall Time(4) — 6 10 ns Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Refer to Figure29-1 for the minimum voltage at a given frequency. 3: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 4: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS39927C-page 232  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 3.6V) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic(1) Min Typ(2) Max Units Conditions No. OS50 FPLLI PLL Input Frequency 4 — 8 MHz ECPLL, HSPLL modes, Range -40°C  TA  +85°C OS51 FSYS PLL Output Frequency 16 — 32 MHz -40°C  TA  +85°C Range OS52 TLOCK PLL Start-up Time — 1 2 ms (Lock Time) OS53 DCLK CLKO Stability (Jitter) -2 1 2 % Measured over a 100 ms period Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-21: AC CHARACTERISTICS: INTERNAL RC ACCURACY Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ 8 MHz(1) F20 FRC -1 — +1 % +25°C 3.0V  VDD  3.6V -3 — +3 % -40°C  TA +85°C -5 — +5 % -40°C  TA +85°C 1.8V  VDD  3.6V -10 — +10 % -40°C  TA +125°C F21 LPRC @ 31 kHz(2) -15 — 15 % +25°C -15 — 15 % -40°C  TA +85°C 1.8V  VDD  3.6V -30 — +30 % -40°C  TA +125°C Note 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. 2: Change of LPRC frequency as VDD changes.  2008-2011 Microchip Technology Inc. DS39927C-page 233

PIC24F16KA102 FAMILY TABLE 29-22: AC SPECIFICATIONS Symbol Characteristics Min Typ Max Units TLW BCLKx High Time 20 TCY/2 — ns THW BCLKx Low Time 20 (TCY * BRGx) + TCY/2 — ns TBLD BCLKx Falling Edge Delay from UxTX -50 — 50 ns TBHD BCLKx Rising Edge Delay from UxTX TCY/2 – 50 — TCY/2 + 50 ns TWAK Min. Low on UxRX Line to Cause Wake-up — 1 — s TCTS Min. Low on UxCTS Line to Start TCY — — ns Transmission TSETUP Start bit Falling Edge to System Clock Rising 3 — — ns Edge Setup Time TSTDELAY Maximum Delay in the Detection of the — — TCY + TSETUP ns Start bit Falling Edge TABLE 29-23: A/D CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) A/D CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD A/D Clock Period 75 — — ns TCY = 75 ns, AD1CON3 is in the default state AD51 TRC A/D Internal RC Oscillator Period — 250 — ns Conversion Rate AD55 TCONV Conversion Time — 12 — TAD AD56 FCNV Throughput Rate — — 500 ksps AVDD  2.7V AD57 TSAMP Sample Time — 1 — TAD AD58 TACQ Acquisition Time 750 — — ns (Note 2) AD59 TSWC Switching Time from Convert to — — (Note 3) Sample AD60 TDIS Discharge Time 0.5 — — TAD Clock Parameters AD61 TPSS Sample Start Delay from Setting 2 — 3 TAD Sample bit (SAMP) Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). 3: On the following cycle of the device clock. DS39927C-page 234  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-24: A/D MODULE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) A/D CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V VDD – 0.3 VDD + 0.3 or 1.8 or 3.6 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V AD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 V Voltage AD08 IVREF Reference Voltage Input — — 200 A VREF+ = 3.3V; sampling Current — — 1.0 mA VREF+ = 3.3V; converting AD09 ZVREF Reference Input — 10K —  (Note 3) Impedance Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V (Note 2) AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 VINL Absolute VINL Input AVSS – 0.3 AVDD/2 V Voltage AD17 RIN Recommended — — 2.5K  10-bit Impedance of Analog Voltage Source A/D Accuracy AD20b NR Resolution — 10 — bits AD21b INL Integral Nonlinearity — ±1 ±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22b DNL Differential Nonlinearity — ±1 -1 LSb VINL = AVSS = VREFL = 0V, +1.5 AVDD = VREFH = 3V AD23b GERR Gain Error — ±1 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD24b EOFF Offset Error — ±1 ±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25b Monotonicity — — — — (Note 1) Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference. 3: Impedance during sampling is at 3.3V, 25°C. This parameter is for design guidance only and is not tested.  2008-2011 Microchip Technology Inc. DS39927C-page 235

PIC24F16KA102 FAMILY FIGURE 29-6: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure29-4 for load conditions. TABLE 29-25: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx pin High or Low 20 — — ns Time (output) DI40 TRBP CNx High or Low Time 2 — — TCY (input) Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39927C-page 236  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-26: COMPARATOR TIMINGS Param Symbol Characteristic Min Typ Max Units Comments No. 300 TRESP Response Time*(1) — 150 400 ns 301 TMC2OV Comparator Mode Change to — — 10 s Output Valid* * Parameters are characterized but not tested. Note 1: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 29-27: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Param Symbol Characteristic Min Typ Max Units Comments No. VR310 TSET Settling Time(1) — — 10 s Note 1: Settling time is measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’.  2008-2011 Microchip Technology Inc. DS39927C-page 237

PIC24F16KA102 FAMILY FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR SY12 SY10 Internal POR PWRT SY11 SYSRST System Clock Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 DS39927C-page 238  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-28: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ(1) Max. Units Conditions No. SY10 TmcL MCLR Pulse Width (low) 2 — — s SY11 TPWRT Power-up Timer Period 50 64 90 ms SY12 TPOR Power-on Reset Delay 1 5 10 s SY13 TIOZ I/O High-Impedance from MCLR — — 100 ns Low or Watchdog Timer Reset SY20 TWDT Watchdog Timer Time-out Period 0.85 1.0 1.15 ms 1.32 prescaler 3.4 4.0 4.6 ms 1:128 prescaler SY25 TBOR Brown-out Reset Pulse Width 1 — — s SY35 TFSCM Fail-Safe Clock Monitor Delay — 2 2.3 s SY45 TRST Configuration Update Time — 20 — s SY55 TLOCK PLL Start-up Time — 1 — ms SY65 TOST Oscillator Start-up Time — 1024 — TOSC SY75 TFRC Fast RC Oscillator Start-up Time — 1 1.5 s SY85 TLPRC Low-Power Oscillator Start-up — — 100 s Time Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. FIGURE 29-8: BAUD RATE GENERATOR OUTPUT TIMING BRGx + 1 * TCY TLW THW BCLKx TBLD TBHD UxTX  2008-2011 Microchip Technology Inc. DS39927C-page 239

PIC24F16KA102 FAMILY FIGURE 29-9: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure29-4 for load conditions. TABLE 29-29: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial) -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — s Repeated Start condition 1 MHz mode(2) TCY/2 (BRG + 1) — s IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s After this period, the Hold Time 400 kHz mode TCY/2 (BRG + 1) — s first clock pulse is generated 1 MHz mode(2) TCY/2 (BRG + 1) — s IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — s Setup Time 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 17.3 “Setting Baud Rate When Operating as a Bus Master” for details. 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). FIGURE 29-10: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM11 IM21 SCLx IM10 IM25 IM26 IM20 SDAx In IM45 IM40 SDAx Out Note: Refer to Figure29-4 for load conditions. DS39927C-page 240  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-30: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) TBD — ns IM26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) TBD — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns From Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — — ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before a new 400 kHz mode 1.3 — s transmission can start 1 MHz mode(2) TBD — s IM50 CB Bus Capacitive Loading — 400 pF Legend: TBD = To Be Determined Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 17.3 “Setting Baud Rate When Operating as a Bus Master” for details. 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).  2008-2011 Microchip Technology Inc. DS39927C-page 241

PIC24F16KA102 FAMILY FIGURE 29-11: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 29-12: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS11 IS21 IS10 SCLx IS25 IS20 IS26 SDAx In IS45 IS40 SDAx Out TABLE 29-31: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C (Industrial) -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Max Units Conditions No. IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 — ns Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only). DS39927C-page 242  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY TABLE 29-32: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C (Industrial) -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Max Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS40 TAA:SCL Output Valid From 100 kHz mode 0 3500 ns Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start 1 MHz mode(1) 0.5 — s IS50 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only). FIGURE 29-13: START BIT EDGE DETECTION BRGx Any Value TCY Start bit Detected, BRGx Started Cycle Clock TSETUP TSTDELAY UxRX  2008-2011 Microchip Technology Inc. DS39927C-page 243

PIC24F16KA102 FAMILY FIGURE 29-14: INPUT CAPTURE TIMINGS ICx pin (Input Capture Mode) IC10 IC11 IC15 TABLE 29-33: INPUT CAPTURE Param. Symbol Characteristic Min Max Units Conditions No. IC10 TccL ICx Input Low Time – No Prescaler TCY + 20 — ns Must also meet Synchronous Timer With Prescaler 20 — ns Parameter IC15 IC11 TccH ICx Input Low Time – No Prescaler TCY + 20 — ns Must also meet Synchronous Timer With Prescaler 20 — ns Parameter IC15 IC15 TccP ICx Input Period – Synchronous Timer 2 * TCY + 40 — ns N = prescale N value (1, 4, 16) TABLE 29-34: OUTPUT CAPTURE Param. Symbol Characteristic Min Max Units Conditions No. OC11 TCCR OC1 Output Rise Time — 10 ns — — ns OC10 TCCF OC1 Output Fall Time — 10 ns — — ns FIGURE 29-15: OUTPUT COMPARE TIMINGS OCx (Output Compare or PWM Mode) OC11 OC10 DS39927C-page 244  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY FIGURE 29-16: PWM MODULE TIMING REQUIREMENTS OC20 OCFx OC15 PWM TABLE 29-35: PWM TIMING REQUIREMENTS Param. Symbol Characteristic Min Typ† Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — 25 ns VDD = 3.0V, -40C to +125C Change OC20 TFH Fault Input Pulse Width 50 — — ns VDD = 3.0V, -40C to +125C † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2008-2011 Microchip Technology Inc. DS39927C-page 245

PIC24F16KA102 FAMILY FIGURE 29-17: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 0) SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP31 SP30 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 TABLE 29-36: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP10 TscL SCKx Output Low Time(2) TCY/2 — — ns SP11 TscH SCKx Output High Time(2) TCY/2 — — ns SP20 TscF SCKx Output Fall Time(3) — 10 25 ns SP21 TscR SCKx Output Rise Time(3) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(3) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(3) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after — — 30 ns TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns TscL2diL to SCKx Edge Note1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPIx pins. DS39927C-page 246  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY FIGURE 29-18: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 1) SP36 SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP40 SP30,SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP41 TABLE 29-37: SPIx MODULE MASTER MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP10 TscL SCKx Output Low Time(2) TCY/2 — — ns SP11 TscH SCKx Output High Time(2) TCY/2 — — ns SP20 TscF SCKx Output Fall Time(3) — 10 25 ns SP21 TscR SCKx Output Rise Time(3) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(3) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(3) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after — — 30 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns TscL2diL to SCKx Edge Note1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPIx pins.  2008-2011 Microchip Technology Inc. DS39927C-page 247

PIC24F16KA102 FAMILY FIGURE 29-19: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 0) SSx SP50 SP52 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP72 SP73 SP35 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 TABLE 29-38: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP70 TscL SCKx Input Low Time 30 — — ns SP71 TscH SCKx Input High Time 30 — — ns SP72 TscF SCKx Input Fall Time(2) — 10 25 ns SP73 TscR SCKx Input Rise Time(2) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(2) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(2) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after — — 30 ns TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output High-Impedance(3) 10 — 50 ns SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns TscL2ssH Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPIx pins. DS39927C-page 248  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY FIGURE 29-20: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1) SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 TABLE 29-39: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP70 TscL SCKx Input Low Time 30 — — ns SP71 TscH SCKx Input High Time 30 — — ns SP72 TscF SCKx Input Fall Time(2) — 10 25 ns SP73 TscR SCKx Input Rise Time(2) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(2) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(2) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after SCKx Edge — — 30 ns TscL2doV SP40 TdiV2scH, Setup Time of SDIx Data Input to 20 — — ns TdiV2scL SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input to 20 — — ns TscL2diL SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output High-Impedance(3) 10 — 50 ns SP52 TscH2ssH SSx  after SCKx Edge 1.5 TCY + 40 — — ns TscL2ssH SP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 50 ns Note1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPIx pins.  2008-2011 Microchip Technology Inc. DS39927C-page 249

PIC24F16KA102 FAMILY NOTES: DS39927C-page 250  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 20-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC24F16KA101 XXXXXXXXXXXXXXXXX -I/Pe3 YYWWNNN 1110017 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC24F16KA102 XXXXXXXXXXXXXXXXX -I/SPe3 YYWWNNN 1110017 20-Lead SSOP Example XXXXXXXXXXX PIC24F16KA XXXXXXXXXXX 101-I/SSe3 YYWWNNN 1110017 28-Lead SSOP Example XXXXXXXXXXXX PIC24F08KA XXXXXXXXXXXX 102-I/SSe3 YYWWNNN 1110017 Legend: XX...X Product-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2008-2011 Microchip Technology Inc. DS39927C-page 251

PIC24F16KA102 FAMILY 20-Lead SOIC (.300”) Example XXXXXXXXXXXXXX PIC24F16KA101 XXXXXXXXXXXXXX -I/SOe3 XXXXXXXXXXXXXX 1110017 YYWWNNN 28-Lead SOIC (.300”) Example XXXXXXXXXXXXXXXXXXXX PIC24F16KA102 XXXXXXXXXXXXXXXXXXXX -I/SOe3 XXXXXXXXXXXXXXXXXXXX YYWWNNN 1110017 20-Lead QFN Example PIC24F XXXXXX 16KA101 XXXXXX -I/MQe3 XXXXXX 1110017 YYWWNNN 28-Lead QFN Example XXXXXXXX 24F16KA XXXXXXXX 102-I/MLe3 YYWWNNN 1110017 DS39927C-page 252  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 30.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:3)(cid:3)(cid:9)(cid:24)(cid:14)(cid:11)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)(cid:10)(cid:16)(cid:18)(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) (cid:14) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:25)(cid:19)&! (cid:28)7,8.(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)9(cid:19)’(cid:19)&! (cid:18)(cid:28)7 7:(cid:18) (cid:18)(cid:7); 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 (cid:16)(cid:4) (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:29)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3), (cid:24)(cid:22)(cid:10)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7) < < (cid:29)(cid:16)(cid:30)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:7)(cid:16) (cid:29)(cid:30)(cid:30)(cid:15) (cid:29)(cid:30)-(cid:4) (cid:29)(cid:30)(cid:6)(cid:15) 1(cid:11)!(cid:13)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7)(cid:30) (cid:29)(cid:4)(cid:30)(cid:15) < < (cid:3)(cid:23)(cid:22)"(cid:26)#(cid:13)(cid:21)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:23)(cid:22)"(cid:26)#(cid:13)(cid:21)(cid:14)=(cid:19)#&(cid:23) . (cid:29)-(cid:4)(cid:4) (cid:29)-(cid:30)(cid:4) (cid:29)-(cid:16)(cid:15) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#&(cid:23) .(cid:30) (cid:29)(cid:16)(cid:5)(cid:4) (cid:29)(cid:16)(cid:15)(cid:4) (cid:29)(cid:16)>(cid:4) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) (cid:29)(cid:6)>(cid:4) (cid:30)(cid:29)(cid:4)-(cid:4) (cid:30)(cid:29)(cid:4)?(cid:4) (cid:24)(cid:19)(cid:10)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) 9 (cid:29)(cid:30)(cid:30)(cid:15) (cid:29)(cid:30)-(cid:4) (cid:29)(cid:30)(cid:15)(cid:4) 9(cid:13)(cid:11)#(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:20) (cid:29)(cid:4)(cid:4)> (cid:29)(cid:4)(cid:30)(cid:4) (cid:29)(cid:4)(cid:30)(cid:15) 6(cid:10)(cid:10)(cid:13)(cid:21)(cid:14)9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) )(cid:30) (cid:29)(cid:4)(cid:5)(cid:15) (cid:29)(cid:4)?(cid:4) (cid:29)(cid:4)(cid:17)(cid:4) 9(cid:22)*(cid:13)(cid:21)(cid:14)9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) ) (cid:29)(cid:4)(cid:30)(cid:5) (cid:29)(cid:4)(cid:30)> (cid:29)(cid:4)(cid:16)(cid:16) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)(cid:8)(cid:22)*(cid:14)(cid:3)(cid:10)(cid:11)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:14)+ (cid:13)1 < < (cid:29)(cid:5)-(cid:4) (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) +(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)%(cid:19)(cid:20)(cid:11)(cid:25)&(cid:14),(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)&(cid:13)(cid:21)(cid:19)!&(cid:19)(cid:20)(cid:29) -(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:25)#(cid:14).(cid:30)(cid:14)#(cid:22)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)"#(cid:13)(cid:14)’(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:29)(cid:14)(cid:18)(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:14)!(cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:13)$(cid:20)(cid:13)(cid:13)#(cid:14)(cid:29)(cid:4)(cid:30)(cid:4)/(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)!(cid:19)#(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18).(cid:14)0(cid:30)(cid:5)(cid:29)(cid:15)(cid:18)(cid:29) 1(cid:3),2 1(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:30)(cid:6)1  2008-2011 Microchip Technology Inc. DS39927C-page 253

PIC24F16KA102 FAMILY (cid:2) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)!"(cid:14)(cid:19)(cid:19)(cid:27)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:3)(cid:3)(cid:9)(cid:24)(cid:14)(cid:11)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)!(cid:10)(cid:16)(cid:18)(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:25)(cid:19)&! (cid:28)7,8.(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)9(cid:19)’(cid:19)&! (cid:18)(cid:28)7 7:(cid:18) (cid:18)(cid:7); 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 (cid:16)> (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:29)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3), (cid:24)(cid:22)(cid:10)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7) < < (cid:29)(cid:16)(cid:4)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:7)(cid:16) (cid:29)(cid:30)(cid:16)(cid:4) (cid:29)(cid:30)-(cid:15) (cid:29)(cid:30)(cid:15)(cid:4) 1(cid:11)!(cid:13)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7)(cid:30) (cid:29)(cid:4)(cid:30)(cid:15) < < (cid:3)(cid:23)(cid:22)"(cid:26)#(cid:13)(cid:21)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:23)(cid:22)"(cid:26)#(cid:13)(cid:21)(cid:14)=(cid:19)#&(cid:23) . (cid:29)(cid:16)(cid:6)(cid:4) (cid:29)-(cid:30)(cid:4) (cid:29)--(cid:15) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#&(cid:23) .(cid:30) (cid:29)(cid:16)(cid:5)(cid:4) (cid:29)(cid:16)>(cid:15) (cid:29)(cid:16)(cid:6)(cid:15) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) (cid:30)(cid:29)-(cid:5)(cid:15) (cid:30)(cid:29)-?(cid:15) (cid:30)(cid:29)(cid:5)(cid:4)(cid:4) (cid:24)(cid:19)(cid:10)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) 9 (cid:29)(cid:30)(cid:30)(cid:4) (cid:29)(cid:30)-(cid:4) (cid:29)(cid:30)(cid:15)(cid:4) 9(cid:13)(cid:11)#(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:20) (cid:29)(cid:4)(cid:4)> (cid:29)(cid:4)(cid:30)(cid:4) (cid:29)(cid:4)(cid:30)(cid:15) 6(cid:10)(cid:10)(cid:13)(cid:21)(cid:14)9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) )(cid:30) (cid:29)(cid:4)(cid:5)(cid:4) (cid:29)(cid:4)(cid:15)(cid:4) (cid:29)(cid:4)(cid:17)(cid:4) 9(cid:22)*(cid:13)(cid:21)(cid:14)9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) ) (cid:29)(cid:4)(cid:30)(cid:5) (cid:29)(cid:4)(cid:30)> (cid:29)(cid:4)(cid:16)(cid:16) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)(cid:8)(cid:22)*(cid:14)(cid:3)(cid:10)(cid:11)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:14)+ (cid:13)1 < < (cid:29)(cid:5)-(cid:4) (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) +(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)%(cid:19)(cid:20)(cid:11)(cid:25)&(cid:14),(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)&(cid:13)(cid:21)(cid:19)!&(cid:19)(cid:20)(cid:29) -(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:25)#(cid:14).(cid:30)(cid:14)#(cid:22)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)"#(cid:13)(cid:14)’(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:29)(cid:14)(cid:18)(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:14)!(cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:13)$(cid:20)(cid:13)(cid:13)#(cid:14)(cid:29)(cid:4)(cid:30)(cid:4)/(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)!(cid:19)#(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18).(cid:14)0(cid:30)(cid:5)(cid:29)(cid:15)(cid:18)(cid:29) 1(cid:3),2 1(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:17)(cid:4)1 DS39927C-page 254  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)!#$(cid:14)(cid:19)"(cid:9)!(cid:24)(cid:7)(cid:11)(cid:11)(cid:9)%(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!!(cid:21)(cid:9)(cid:22)(cid:9)&’(cid:23)(cid:3)(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)!!%(cid:10)(cid:29)(cid:9) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 6(cid:25)(cid:19)&! (cid:18)(cid:28)99(cid:28)(cid:18).(cid:24).(cid:8)(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)9(cid:19)’(cid:19)&! (cid:18)(cid:28)7 7:(cid:18) (cid:18)(cid:7); 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 (cid:16)(cid:4) (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:4)(cid:29)?(cid:15)(cid:14)1(cid:3), : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)8(cid:13)(cid:19)(cid:12)(cid:23)& (cid:7) < < (cid:16)(cid:29)(cid:4)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:7)(cid:16) (cid:30)(cid:29)?(cid:15) (cid:30)(cid:29)(cid:17)(cid:15) (cid:30)(cid:29)>(cid:15) (cid:3)&(cid:11)(cid:25)#(cid:22)%%(cid:14) (cid:7)(cid:30) (cid:4)(cid:29)(cid:4)(cid:15) < < : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)=(cid:19)#&(cid:23) . (cid:17)(cid:29)(cid:5)(cid:4) (cid:17)(cid:29)>(cid:4) >(cid:29)(cid:16)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#&(cid:23) .(cid:30) (cid:15)(cid:29)(cid:4)(cid:4) (cid:15)(cid:29)-(cid:4) (cid:15)(cid:29)?(cid:4) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) ?(cid:29)(cid:6)(cid:4) (cid:17)(cid:29)(cid:16)(cid:4) (cid:17)(cid:29)(cid:15)(cid:4) 3(cid:22)(cid:22)&(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) 9 (cid:4)(cid:29)(cid:15)(cid:15) (cid:4)(cid:29)(cid:17)(cid:15) (cid:4)(cid:29)(cid:6)(cid:15) 3(cid:22)(cid:22)&(cid:10)(cid:21)(cid:19)(cid:25)& 9(cid:30) (cid:30)(cid:29)(cid:16)(cid:15)(cid:14)(cid:8).3 9(cid:13)(cid:11)#(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:20) (cid:4)(cid:29)(cid:4)(cid:6) < (cid:4)(cid:29)(cid:16)(cid:15) 3(cid:22)(cid:22)&(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13) (cid:3) (cid:4)@ (cid:5)@ >@ 9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) ) (cid:4)(cid:29)(cid:16)(cid:16) < (cid:4)(cid:29)-> (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:25)#(cid:14).(cid:30)(cid:14)#(cid:22)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)"#(cid:13)(cid:14)’(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:29)(cid:14)(cid:18)(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:14)!(cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:13)$(cid:20)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:29)(cid:16)(cid:4)(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)!(cid:19)#(cid:13)(cid:29) -(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18).(cid:14)0(cid:30)(cid:5)(cid:29)(cid:15)(cid:18)(cid:29) 1(cid:3),2 1(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)((cid:14)"!"(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)((cid:14)%(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)%(cid:22)(cid:21)’(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)"(cid:21)(cid:10)(cid:22)!(cid:13)!(cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:17)(cid:16)1  2008-2011 Microchip Technology Inc. DS39927C-page 255

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 256  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY (cid:2) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)!#$(cid:14)(cid:19)"(cid:9)!(cid:24)(cid:7)(cid:11)(cid:11)(cid:9)%(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!!(cid:21)(cid:9)(cid:22)(cid:9)&’(cid:23)(cid:3)(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)!!%(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:25)(cid:19)&! (cid:18)(cid:28)99(cid:28)(cid:18).(cid:24).(cid:8)(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)9(cid:19)’(cid:19)&! (cid:18)(cid:28)7 7:(cid:18) (cid:18)(cid:7); 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 (cid:16)> (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:4)(cid:29)?(cid:15)(cid:14)1(cid:3), : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)8(cid:13)(cid:19)(cid:12)(cid:23)& (cid:7) < < (cid:16)(cid:29)(cid:4)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:7)(cid:16) (cid:30)(cid:29)?(cid:15) (cid:30)(cid:29)(cid:17)(cid:15) (cid:30)(cid:29)>(cid:15) (cid:3)&(cid:11)(cid:25)#(cid:22)%%(cid:14) (cid:7)(cid:30) (cid:4)(cid:29)(cid:4)(cid:15) < < : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)=(cid:19)#&(cid:23) . (cid:17)(cid:29)(cid:5)(cid:4) (cid:17)(cid:29)>(cid:4) >(cid:29)(cid:16)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#&(cid:23) .(cid:30) (cid:15)(cid:29)(cid:4)(cid:4) (cid:15)(cid:29)-(cid:4) (cid:15)(cid:29)?(cid:4) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) (cid:6)(cid:29)(cid:6)(cid:4) (cid:30)(cid:4)(cid:29)(cid:16)(cid:4) (cid:30)(cid:4)(cid:29)(cid:15)(cid:4) 3(cid:22)(cid:22)&(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) 9 (cid:4)(cid:29)(cid:15)(cid:15) (cid:4)(cid:29)(cid:17)(cid:15) (cid:4)(cid:29)(cid:6)(cid:15) 3(cid:22)(cid:22)&(cid:10)(cid:21)(cid:19)(cid:25)& 9(cid:30) (cid:30)(cid:29)(cid:16)(cid:15)(cid:14)(cid:8).3 9(cid:13)(cid:11)#(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:20) (cid:4)(cid:29)(cid:4)(cid:6) < (cid:4)(cid:29)(cid:16)(cid:15) 3(cid:22)(cid:22)&(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13) (cid:3) (cid:4)@ (cid:5)@ >@ 9(cid:13)(cid:11)#(cid:14)=(cid:19)#&(cid:23) ) (cid:4)(cid:29)(cid:16)(cid:16) < (cid:4)(cid:29)-> (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:25)#(cid:14).(cid:30)(cid:14)#(cid:22)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)"#(cid:13)(cid:14)’(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:29)(cid:14)(cid:18)(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:14)!(cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:13)$(cid:20)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:29)(cid:16)(cid:4)(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)!(cid:19)#(cid:13)(cid:29) -(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18).(cid:14)0(cid:30)(cid:5)(cid:29)(cid:15)(cid:18)(cid:29) 1(cid:3),2 1(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)((cid:14)"!"(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)((cid:14)%(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)%(cid:22)(cid:21)’(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)"(cid:21)(cid:10)(cid:22)!(cid:13)!(cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:17)-1  2008-2011 Microchip Technology Inc. DS39927C-page 257

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 258  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2011 Microchip Technology Inc. DS39927C-page 259

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 260  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2011 Microchip Technology Inc. DS39927C-page 261

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 262  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2011 Microchip Technology Inc. DS39927C-page 263

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 264  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY 20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-120A  2008-2011 Microchip Technology Inc. DS39927C-page 265

PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 266  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY (cid:2) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)((cid:17)(cid:7)(cid:8)(cid:9))(cid:11)(cid:7)(cid:13)*(cid:9)(cid:30)(cid:26)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)"(cid:7)+(cid:6)(cid:9)(cid:20),(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)-.-(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)()(cid:30)(cid:29) /(cid:14)(cid:13)#(cid:9)(cid:3)’&&(cid:9)(cid:24)(cid:24)(cid:9)0(cid:26)(cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19)+(cid:13)# (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:25)(cid:19)&! (cid:18)(cid:28)99(cid:28)(cid:18).(cid:24).(cid:8)(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)9(cid:19)’(cid:19)&! (cid:18)(cid:28)7 7:(cid:18) (cid:18)(cid:7); 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 (cid:16)> (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:4)(cid:29)?(cid:15)(cid:14)1(cid:3), : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)8(cid:13)(cid:19)(cid:12)(cid:23)& (cid:7) (cid:4)(cid:29)>(cid:4) (cid:4)(cid:29)(cid:6)(cid:4) (cid:30)(cid:29)(cid:4)(cid:4) (cid:3)&(cid:11)(cid:25)#(cid:22)%%(cid:14) (cid:7)(cid:30) (cid:4)(cid:29)(cid:4)(cid:4) (cid:4)(cid:29)(cid:4)(cid:16) (cid:4)(cid:29)(cid:4)(cid:15) ,(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)4(cid:25)(cid:13)!! (cid:7)- (cid:4)(cid:29)(cid:16)(cid:4)(cid:14)(cid:8).3 : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)=(cid:19)#&(cid:23) . ?(cid:29)(cid:4)(cid:4)(cid:14)1(cid:3), .$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)=(cid:19)#&(cid:23) .(cid:16) -(cid:29)?(cid:15) -(cid:29)(cid:17)(cid:4) (cid:5)(cid:29)(cid:16)(cid:4) : (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) ?(cid:29)(cid:4)(cid:4)(cid:14)1(cid:3), .$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2)(cid:16) -(cid:29)?(cid:15) -(cid:29)(cid:17)(cid:4) (cid:5)(cid:29)(cid:16)(cid:4) ,(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)=(cid:19)#&(cid:23) ) (cid:4)(cid:29)(cid:16)- (cid:4)(cid:29)-(cid:4) (cid:4)(cid:29)-(cid:15) ,(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)9(cid:13)(cid:25)(cid:12)&(cid:23) 9 (cid:4)(cid:29)(cid:15)(cid:4) (cid:4)(cid:29)(cid:15)(cid:15) (cid:4)(cid:29)(cid:17)(cid:4) ,(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:9)&(cid:22)(cid:9).$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)# A (cid:4)(cid:29)(cid:16)(cid:4) < < (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:19)!(cid:14)!(cid:11)*(cid:14)!(cid:19)(cid:25)(cid:12)"(cid:26)(cid:11)&(cid:13)#(cid:29) -(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18).(cid:14)0(cid:30)(cid:5)(cid:29)(cid:15)(cid:18)(cid:29) 1(cid:3),2 1(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)((cid:14)"!"(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)((cid:14)%(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)%(cid:22)(cid:21)’(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)"(cid:21)(cid:10)(cid:22)!(cid:13)!(cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12),(cid:4)(cid:5)(cid:9)(cid:30)(cid:4)(cid:15)1  2008-2011 Microchip Technology Inc. DS39927C-page 267

PIC24F16KA102 FAMILY (cid:2) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)((cid:17)(cid:7)(cid:8)(cid:9))(cid:11)(cid:7)(cid:13)*(cid:9)(cid:30)(cid:26)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)"(cid:7)+(cid:6)(cid:9)(cid:20),(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)-.-(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)()(cid:30)(cid:29) /(cid:14)(cid:13)#(cid:9)(cid:3)’&&(cid:9)(cid:24)(cid:24)(cid:9)0(cid:26)(cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19)+(cid:13)# (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)255***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’5(cid:10)(cid:11)(cid:20)4(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) DS39927C-page 268  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY APPENDIX A: REVISION HISTORY • Imported Figure 40.10 from PIC24F FRM, Section 40. • Deleted TVREG spec. Revision A (November 2008) • Imported Figure 15-5 from PIC24F FRM, Original data sheet for the PIC24F16KA102 family of Section15. devices. • Imported Table 15-4 from PIC24F FRM, Section 15. • Imported Figure 16-22 from PIC24F FRM, Revision B (March 2009) Section 16. Section29.0 “Electrical Characteristics” was • Imported Table 16-9 from PIC24F FRM, Section 16. revised and minor text edits were made throughout the • Imported Figure 16-23 from PIC24F FRM, document. Section 16. • Imported Table 16-10 from PIC24F FRM, Revision C (October 2011) Section 16. • Imported Figure 21-24 from PIC24F FRM. • Changed all instances of DSWSRC to DSWAKE. Section 21. • Corrected Example5-2. • Imported Figure 21-25 from PIC24F FRM, • Corrected Example5-4. Section 21. • Corrected Example6-1. • Imported Table 21-5 from PIC24F FRM, • Corrected Example6-3. Section 21. • Added a comment to Example6-5. • Imported Figure 23-17 from PIC24F FRM, • Corrected Figure9-1 to connect the SOSCI and Section 23. SOSCO pins to the Schmitt trigger correctly. • Imported Table 23-3 from PIC24F FRM, • Added register descriptions for PMD1, PMD2, Section 23. PMD3 and PMD4. • Imported Figure 23-18 from PIC24F FRM, • Added note that RTCC will run in Reset. Section 23. • Corrected time values of ADCS • Imported Table 23-4 from PIC24F FRM, (AD1CON3<5:0>). Section 23. • Corrected CH0SB and CH0SA (AD1CHS<11:8> • Imported Figure 23-19 from PIC24F FRM, and AD1CHS<3:0>) to correctly reference AVDD Section 23. and AN3. • Imported Table 23-5 from PIC24F FRM, • Added description of PGCF15 and PGCF14 Section 23. (AD1PCFG<15:14>). • Imported Figure 23-20 from PIC24F FRM, • Edited Figure22-2 to correctly reference RIC and Section 23. the A/D capacitance. • Imported Table 23-6 from PIC24F FRM, • Changed all references from CTEDG1 to CTED1. Section 23. • Changed all references from CTEDG2 to CTED2. • Imported Figure 24-33 from PIC24F FRM, • Changed description of CMIDL: it used to say it Section 24. disables all comparators in Idle, now only disables • Imported Table 24-6 from PIC24F FRM, interrupts in Idle mode. Section 24. • Changed all references of RTCCKSEL to • Imported Figure 24-34 from PIC24F FRM, RTCOSC. Section 24. • Changed all references of DSLPBOR to • Imported Table 24-7 from PIC24F FRM, DSBOREN. Section 24. • Changed all references of DSWCKSEL to • Imported Figure 24-35 from PIC24F FRM, DSWDTOSC Section 24. • Imported Figure 40-9 from PIC24F FRM, • Imported Table 24-8 from PIC24F FRM, Section 40. Section 24. • Added spec for BOR hysteresis. • Imported Figure 24-36 from PIC24F FRM, • Edited Note 1 for Table29-5 to further describe Section 24. LPBOR. • Imported Table 24-9 from PIC24F FRM, • Edited max values of DC20d and DC20e on Section 24. Table29-6. • Edited typical value for DC61-DC61c in Table29-8. • Edited Note 2 of Table29-8. • Added Note 5 to Table29-9. • Added Table29-15. • Added AD08 and AD09 in Table29-26. • Added Note 3 to Table29-26.  2008-2011 Microchip Technology Inc. DS39927C-page 269

PIC24F16KA102 FAMILY NOTES: DS39927C-page 270  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY INDEX A Reset System ............................................................57 RTCC .......................................................................155 A/D Shared I/O Port Structure ........................................113 10-Bit High-Speed A/D Converter ............................173 Simplified UART ......................................................147 A/D Characteristics SPI1 Module (Enhanced Buffer Mode) ....................133 Conversion Timing Requirements ............................234 SPI1 Module (Standard Buffer Mode) .....................132 Module Specifications ..............................................235 System Clock .............................................................91 A/D Converter Timer2 (16-Bit Synchronous Mode) .........................119 Analog Input Model ..................................................181 Timer2/3 (32-Bit Mode) ............................................118 Transfer Function .....................................................182 Timer3 (16-Bit Synchronous Mode) .........................119 AC Characteristics Watchdog Timer (WDT) ...........................................201 Capacitive Loading Requirements on Brown-out Reset (BOR) .....................................................61 Output Pins ......................................................231 Comparator Timings ................................................237 C Comparator Voltage Reference Settling C Compilers Time Specifications ..........................................237 MPLAB C18 .............................................................204 Input Capture ...........................................................244 Charge Time Measurement Unit. See CTMU. Internal RC Accuracy ...............................................233 Code Examples Load Conditions for Device Timing Data EEPROM Bulk Erase ........................................55 Specifications ...................................................231 Data EEPROM Unlock Sequence .............................51 Output Capture ........................................................244 Erasing a Program Memory Row, Reset, Watchdog Timer, Oscillator Start-up Timer, ‘C’ Language Code ............................................48 Power-up Timer and Brown-out Reset Erasing a Program Memory Row, Timing Requirements .......................................239 Assembly Language Code ................................48 Specifications ...........................................................234 I/O Port Write/Read .................................................114 Assembler Initiating a Programming Sequence, MPASM Assembler ..................................................204 ‘C’ Language Code ............................................50 B Initiating a Programming Sequence, Assembly Language Code ................................50 Baud Rate Generator Loading the Write Buffers, ‘C’ Language Code .........49 Setting as a Bus Master ...........................................141 Loading the Write Buffers, Assembly Block Diagrams Language Code .................................................49 10-Bit High-Speed A/D Converter ............................174 PWRSAV Instruction Syntax ...................................101 16-Bit Timer1 ...........................................................115 Reading Data EEPROM Using the Accessing Program Memory with TBLRD Command .............................................56 Table Instructions ..............................................43 Sequence for Clock Switching ...................................98 CALL Stack Frame .....................................................41 Setting the RTCWREN Bit .......................................156 Comparator Module .................................................183 Single-Word Erase ....................................................54 Comparator Voltage Reference ...............................187 Single-Word Write to Data EEPROM ........................55 CPU Programmer’s Model .........................................25 Code Protection ...............................................................202 CRC Reconfigured for Polynomial ...........................168 Comparator ......................................................................183 CRC Shifter Details ..................................................167 Comparator Voltage Reference .......................................187 CTMU Connections and Internal Configuration for Configuration ...........................................................187 Capacitance Measurement ..............................189 Configuration Bits ............................................................193 CTMU Typical Connections and Internal Core Features ......................................................................9 Configuration for Pulse Delay Generation .......190 CPU CTMU Typical Connections and Internal Arithmetic (Logic Unit (ALU) ......................................27 Configuration for Time Measurement ..............190 Control Registers .......................................................26 Data Access from Program Space Core Registers ...........................................................24 Address Generation ...........................................42 Programmer’s Model .................................................23 Data EEPROM Addressing with TBLPAG, CRC NVM Address Registers ....................................53 Operation in Power Save Modes .............................168 High/Low-Voltage Detect (HLVD) ............................171 I2C Module ...............................................................140 User Interface ..........................................................168 CTMU Individual Comparator Configurations ......................184 Measuring Capacitance ...........................................189 Input Capture ...........................................................123 Measuring Time .......................................................190 Output Compare ......................................................128 Pulse Generation and Delay ....................................190 PIC24F CPU Core .....................................................24 Customer Change Notification Service ............................275 PIC24F16KA102 Family (General) ............................12 Customer Notification Service .........................................275 PSV Operation ...........................................................44 Customer Support ............................................................275  2008-2011 Microchip Technology Inc. DS39927C-page 271

PIC24F16KA102 FAMILY D Examples Baud Rate Error Calculation (BRG) .........................148 Data EEPROM PWM Frequencies, Resolutions at 16 MIPS ............127 Bulk Erase ..................................................................55 PWM Frequencies, Resolutions at 4 MIPS ..............127 Erasing .......................................................................54 PWM Period, Duty Cycle Calculations .....................127 Operations .................................................................53 Programming F Reading Data EEPROM ....................................56 Flash and Data EEPROM Single-Word Write ..............................................55 Programming Data Memory Control Registers ...............................................51 Address Space ...........................................................31 Flash and Data EEPROM Programming Memory Map ..............................................................31 Control Registers Near Data Space .......................................................32 NVM Address Registers (NVMADRU, Organization, Alignment .............................................32 NVMADR ...................................................53 SFR Space .................................................................32 NVMCON ...........................................................51 Software Stack ...........................................................41 NVMKEY ...........................................................51 Space Width ...............................................................31 Flash Program Memory DC Characteristics Control Registers .......................................................46 Brown-out Reset Trip Points ....................................219 Enhanced ICSP Operation ........................................46 Comparator Specifications .......................................230 Programming Algorithm .............................................48 Comparator Voltage Reference Specifications ........230 Programming Operations ...........................................46 CTMU Current Source Specifications ......................230 RTSP Operation ........................................................46 Data EEPROM Memory ...........................................229 Table Instructions ......................................................45 High/Low-Voltage Detect .........................................218 I/O Pin Input Specifications ......................................227 H I/O Pin Output Specifications ...................................228 High/Low-Voltage Detect (HLVD) ....................................171 Idle Current IIDLE ......................................................222 Internal Voltage References ....................................230 I Operating Current IDD ..............................................220 I/O Ports Power-Down Current IPD .........................................224 Analog Pins Configuration .......................................114 Program Memory .....................................................229 Input Change Notification ........................................114 Temperature and Voltage Specifications .................218 Open-Drain Configuration ........................................114 Thermal Operating Conditions .................................217 Parallel (PIO) ...........................................................113 Thermal Packaging Characteristics .........................217 I2C Deep Sleep Clock Rates .............................................................141 Checking, Clearing Status .......................................104 Communicating as Master in Single Master Entering ....................................................................102 Environment ....................................................139 Sequence .................................................102, 103 Pin Remapping Options ...........................................139 Exiting ......................................................................103 Reserved Addresses ...............................................141 I/O Pins ....................................................................103 Slave Address Masking ...........................................141 POR .........................................................................104 In-Circuit Debugger ..........................................................202 Sequence Summary ................................................104 In-Circuit Serial Programming (ICSP) ..............................202 WDT .........................................................................104 Input Capture ...................................................................123 Deep Sleep BOR (DSBOR) ...............................................61 Instruction Set Development Support ......................................................203 Opcode Symbols .....................................................208 Device Features (Summary) ..............................................11 Overview ..................................................................209 Doze Mode .......................................................................107 Summary .................................................................207 E Inter-Integrated Circuit. See I2C. Internet Address ..............................................................275 Electrical Characteristics Interrupts Absolute Maximum Ratings .....................................215 Alternate Interrupt Vector Table (AIVT) .....................63 V/F Graphs (Industrial, Extended) ...........................216 Control and Status Registers .....................................66 V/F Graphs (Industrial) .............................................216 Implemented Vectors .................................................65 Equations Interrupt Service Routine (ISR) ..................................90 A/D Conversion Clock Period ..................................181 Interrupt Vector Table (IVT) .......................................63 Baud Rate Reload Calculation .................................141 Reset Sequence ........................................................63 Calculating the PWM Period ....................................126 Setup and Service Procedures ..................................90 Calculation for Maximum PWM Resolution ..............126 Trap Service Routine (TSR) ......................................90 CRC .........................................................................167 Trap Vectors ..............................................................65 Device and SPI Clock Speed Relationship ..............138 Vector Table ..............................................................64 UART Baud Rate with BRGH = 0 ............................148 UART Baud Rate with BRGH = 1 ............................148 Errata ...................................................................................8 DS39927C-page 272  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY M Output Compare ........................................................35 Pad Configuration ......................................................37 Microchip Internet Web Site .............................................275 PMD ...........................................................................40 MPLAB ASM30 Assembler, Linker, Librarian ..................204 PORTA ......................................................................37 MPLAB Integrated Development PORTB ......................................................................37 Environment Software ..............................................203 RTCC .........................................................................39 MPLAB PM3 Device Programmer ...................................206 SPI .............................................................................36 MPLAB REAL ICE In-Circuit Emulator System ................205 Timer .........................................................................35 MPLINK Object Linker/MPLIB Object Librarian ...............204 UART .........................................................................36 N Registers Near Data Space ...............................................................32 AD1CHS (A/D Input Select) .....................................178 AD1CON1 (A/D Control 1) .......................................175 O AD1CON2 (A/D Control 2) .......................................176 Oscillator Configuration AD1CON3 (A/D Control 3) .......................................177 Bit Values for Clock Selection ....................................92 AD1CSSL (A/D Input Scan Select, Low) .................180 Clock Switching ..........................................................97 AD1PCFG (A/D Port Configuration) ........................179 Sequence ...........................................................97 ALCFGRPT (Alarm Configuration) ..........................159 CPU Clocking Scheme ..............................................92 ALMINSEC (Alarm Minutes and Initial Configuration on POR ......................................92 Seconds Value) ...............................................163 Reference Clock Output .............................................98 ALMTHDY (Alarm Month and Day Value) ...............162 Output Compare ALWDHR (Alarm Weekday and Hours Value) ........162 Continuous Output Pulse Generation ......................125 CLKDIV (Clock Divider) .............................................95 Single Output Pulse Generation ..............................125 CMSTAT (Comparator Status) ................................186 CMxCON (Comparator x Control) ...........................185 P CORCON (CPU Control) .....................................27, 68 Packaging CRCCON (CRC Control) .........................................169 Details ......................................................................253 CRCXOR (CRC XOR Polynomial) ..........................170 Marking ....................................................................251 CTMUCON (CTMU Control) ....................................191 Pinout Descriptions ......................................................13–16 CTMUICON (CTMU Current Control) ......................192 Power-Saving Features ...................................................101 CVRCON (Comparator Voltage Clock Frequency, Clock Switching ...........................101 Reference Control) ..........................................188 Instruction-Based Modes .........................................101 DEVID (Device ID) ...................................................200 Deep Sleep ......................................................102 DEVREV (Device Revision) .....................................200 Idle ...................................................................102 DSCON (Deep Sleep Control) .................................105 Sleep ................................................................101 DSWAKE (Deep Sleep Wake-up Source) ...............106 Product Identification System ..........................................277 FBS (Boot Segment Configuration) .........................193 Program and Data Memory FDS (Deep Sleep Configuration) .............................199 Access Using Table Instructions ................................43 FGS (General Segment Configuration) ...................194 Program Space Visibility ............................................44 FICD (In-Circuit Debugger Configuration) ...............198 Program and Data Memory Spaces FOSC (Oscillator Configuration) ..............................195 Interfacing, Addressing ..............................................41 FOSCSEL (Oscillator Selection Configuration) .......194 Program Memory FPOR (Reset Configuration) ...................................197 Address Space ...........................................................29 FWDT (Watchdog Timer Configuration) ..................196 Configuration Word Addresses ..................................30 HLVDCON (High/Low-Voltage Detect Control) .......172 Memory Map ..............................................................29 I2C1CON (I2C1 Control) .........................................142 Program Verification ........................................................202 I2C1MSK (I2C1 Slave Mode Address Mask) ..........146 Programmable Cyclic Redundancy Check (CRC) I2C1STAT (I2C1 Status) ..........................................144 Generator .................................................................167 IC1CON (Input Capture 1 Control) ..........................124 Pulse-Width Modulation. See PWM. IEC0 (Interrupt Enable Control 0) ..............................75 IEC1 (Interrupt Enable Control 1) ..............................76 R IEC3 (Interrupt Enable Control 3) ..............................77 Reader Response ............................................................276 IEC4 (Interrupt Enable Control 4) ..............................78 Register Maps IFS0 (Interrupt Flag Status 0) ....................................71 A/D .............................................................................38 IFS1 (Interrupt Flag Status 1) ....................................72 Clock Control .............................................................40 IFS3 (Interrupt Flag Status 3) ....................................73 CPU Core ...................................................................33 IFS4 (Interrupt Flag Status 4) ....................................74 CRC ...........................................................................39 INTCON1 (Interrupt Control 1) ..................................69 CTMU .........................................................................38 INTCON2 (Interrupt Control 2) ..................................70 Deep Sleep ................................................................40 INTTREG Interrupt Control and Status ......................89 Dual Comparator ........................................................39 IPC0 (Interrupt Priority Control 0) ..............................79 I2C ..............................................................................36 IPC1 (Interrupt Priority Control 1) ..............................80 ICN .............................................................................34 IPC15 (Interrupt Priority Control 15) ..........................86 Input Capture .............................................................35 IPC16 (Interrupt Priority Control 16) ..........................87 Interrupt Controller .....................................................34 IPC18 (Interrupt Priority Control 18) ..........................88 NVM ...........................................................................40 IPC19 (Interrupt Priority Control 19) ..........................88  2008-2011 Microchip Technology Inc. DS39927C-page 273

PIC24F16KA102 FAMILY IPC2 (Interrupt Priority Control 2) ..............................81 T IPC3 (Interrupt Priority Control 3) ..............................82 Timer1 ..............................................................................115 IPC4 (Interrupt Priority Control 4) ..............................83 Timer2/3 ...........................................................................117 IPC5 (Interrupt Priority Control 5) ..............................84 Timing Diagrams IPC7 (Interrupt Priority Control 7) ..............................85 Baud Rate Generator Output ...........................239, 240 MINSEC (RTCC Minutes and Seconds Value) ........161 Brown-out Reset Characteristics .............................219 MTHDY (RTCC Month and Day Value) ...................160 CLKO and I/O Timing ..............................................236 NVMCON (Flash Memory Control) ............................47 External Clock ..........................................................232 NVMCON (Nonvolatile Memory Control) ...................52 I2C Bus Data (Master Mode) ...................................240 OC1CON (Output Compare 1 Control) ....................129 I2C Bus Data (Slave Mode) .....................................242 OSCCON (Oscillator Control) ....................................93 I2C Bus Start/Stop Bits (Master Mode) ....................240 OSCTUN (FRC Oscillator Tune) ................................96 I2C Bus Start/Stop Bits (Slave Mode) ......................242 PADCFG1 (Pad Input Capture ...........................................................244 Configuration Control) ......................130, 146, 158 Output Compare ......................................................244 PMD1 (Peripheral Module Disable 1) ......................108 PWM Requirements .................................................245 PMD2 (Peripheral Module Disable 2) ......................109 Reset, Watchdog Timer. Oscillator Start-up PMD3 (Peripheral Module Disable 3) ......................110 Timer, Power-up Timer Characteristics ...........238 PMD4 (Peripheral Module Disable 4) ......................111 SPIx Master Mode (CKE = 0) ..................................246 RCFGCAL (RTCC Calibration and SPIx Master Mode (CKE = 1) ..................................247 Configuration) ..................................................157 SPIx Slave Mode (CKE = 0) ....................................248 RCON (Reset Control) ...............................................58 SPIx Slave Mode (CKE = 1) ....................................249 REFOCON (Reference Oscillator Control) .................99 Start Bit Edge Detection ..........................................243 SPI1CON1 (SPI1 Control 1) ....................................136 Timing Requirements SPI1CON2 (SPI1 Control 2) ....................................137 CLKO and I/O ..........................................................236 SPI1STAT (SPI1 Status and Control) ......................134 External Clock ..........................................................232 SR (ALU STATUS) ..............................................26, 67 I2C Bus Data (Master Mode) ...........................240, 241 T1CON (Timer1 Control) ..........................................116 I2C Bus Data (Slave Mode) .....................................243 T2CON (Timer2 Control) ..........................................120 I2C Bus Start/Stop Bit (Slave Mode) ........................242 T3CON (Timer3 Control) ..........................................121 PLL Clock Specifications .........................................233 UxMODE (UARTx Mode) .........................................150 PWM ........................................................................245 UxRXREG (UARTx Receive) ...................................154 SPIx Master Mode (CKE = 0) ..................................246 UxSTA (UARTx Status and Control) ........................152 SPIx Master Mode (CKE = 1) ..................................247 UxTXREG (UARTx Transmit) ..................................154 SPIx Slave Mode (CKE = 0) ....................................248 WKDYHR (RTCC Weekday and Hours Value) ........161 SPIx Slave Mode (CKE = 1) ....................................249 YEAR (RTCC Year Value) .......................................160 Resets U Clock Source Selection ..............................................60 UART ...............................................................................147 Delay Times for Various Device Resets ....................60 Baud Rate Generator (BRG) ...................................148 Device Times .............................................................60 Break and Sync Transmit Sequence .......................149 RCON Flags Operation ..............................................59 IrDA Support ............................................................149 SFR States .................................................................61 Operation of UxCTS and UxRTS Control Pins ........149 Revision History ...............................................................269 Receiving in 8-Bit or 9-Bit Data Mode ......................149 RTCC ...............................................................................155 Transmitting in 8-Bit Data Mode ..............................149 Alarm Configuration .................................................164 Transmitting in 9-Bit Data Mode ..............................149 Alarm Mask Settings (figure) ....................................165 Calibration ................................................................164 W Register Mapping .....................................................156 Watchdog Timer Source Clock ............................................................155 Deep Sleep (DSWDT) .............................................202 Selection ..........................................................156 Watchdog Timer (WDT) ...................................................201 Write Lock ................................................................156 Windowed Operation ...............................................201 S WWW Address ................................................................275 WWW, On-Line Support ......................................................8 Selective Peripheral Power Control .................................107 Serial Peripheral Interface. See SPI. SFR Space .........................................................................32 Software Simulator (MPLAB SIM) ....................................205 Software Stack ...................................................................41 DS39927C-page 274  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2008-2011 Microchip Technology Inc. DS39927C-page 275

PIC24F16KA102 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC24F16KA102 Family Literature Number: DS39927C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39927C-page 276  2008-2011 Microchip Technology Inc.

PIC24F16KA102 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 F 16 KA1 02 T - I / PT - XXX Examples: a) PIC24F16KA102-I/ML: General purpose, Microchip Trademark 16-Kbyte program memory, 28-pin, Industrial temp., QFN package. Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture 24 = 16-bit modified Harvard without DSP Flash Memory Family F = Flash program memory Product Group KA1 = General purpose microcontrollers Pin Count 01 = 20-pin 02 = 28-pin Temperature Range I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package SP = SPDIP SO = SOIC SS = SSOP ML = QFN P = PDIP Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2008-2011 Microchip Technology Inc. DS39927C-page 277

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