dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, Op Amps and Advanced Analog Operating Conditions Timers/Output Compare/Input Capture • 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS • 12 General Purpose Timers: • 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS - Five 16-bit and up to two 32-bit timers/counters - Four Output Compare (OC) modules, configurable Core: 16-Bit dsPIC33E/PIC24E CPU as timers/counters • Code Efficient (C and Assembly) Architecture - PTG module with two configurable timers/counters • Two 40-Bit-Wide Accumulators - 32-bit Quadrature Encoder Interface (QEI) module, • Single Cycle (MAC/MPY) with Dual Data Fetch configurable as a timer/counter • Single-Cycle, Mixed-Sign MUL plus Hardware Divide • Four Input Capture (IC) modules • 32-Bit Multiply Support • Peripheral Pin Select (PPS) to allow Function Remap • Peripheral Trigger Generator (PTG) for Scheduling Clock Management Complex Sequences • 1.0% Internal Oscillator Communication Interfaces • Programmable PLLs and Oscillator Clock Sources • Fail-Safe Clock Monitor (FSCM) • Two UART modules (17.5 Mbps): • Independent Watchdog Timer (WDT) - With support for LIN/J2602 protocols and IrDA® • Fast Wake-up and Start-up • Two 4-Wire SPI modules (15 Mbps) • ECAN™ module (1 Mbaud) CAN 2.0B Support Power Management • Two I2C™ modules (up to 1 Mbaud) with SMBus • Low-Power Management modes (Sleep, Idle, Doze) Support • Integrated Power-on Reset and Brown-out Reset • PPS to allow Function Remap • 0.6 mA/MHz Dynamic Current (typical) • Programmable Cyclic Redundancy Check (CRC) • 30 µA IPD Current (typical) Direct Memory Access (DMA) High-Speed PWM • 4-Channel DMA with User-Selectable Priority Arbitration • Up to Three PWM Pairs with Independent Timing • UART, SPI, ADC, ECAN, IC, OC and Timers • Dead Time for Rising and Falling Edges Input/Output • 7.14 ns PWM Resolution • PWM Support for: • Sink/Source 12 mA or 6 mA, Pin-Specific for - DC/DC, AC/DC, Inverters, PFC, Lighting Standard VOH/VOL, up to 22 or 14 mA, respectively - BLDC, PMSM, ACIM, SRM for Non-Standard VOH1 • Programmable Fault Inputs • 5V Tolerant Pins • Flexible Trigger Configurations for ADC Conversions • Peripheral Pin Select (PPS) to allow Digital Function Remapping Advanced Analog Features • Selectable Open-Drain, Pull-ups and Pull-Downs • ADC module: • Up to 5 mA Overvoltage Clamp Current - Configurable as 10-bit, 1.1 Msps with four S&H or • Change Notification Interrupts on All I/O Pins 12-bit, 500 ksps with one S&H - Six analog inputs on 28-pin devices and up to Qualification and Class B Support 16 analog inputs on 64-pin devices • AEC-Q100 REVG (Grade 1, -40°C to +125°C) Planned • Flexible and Independent ADC Trigger Sources • AEC-Q100 REVG (Grade 0, -40°C to +150°C) Planned • Up to Three Op Amp/Comparators with • Class B Safety Library, IEC 60730 Direct Connection to the ADC module: - Additional dedicated comparator Debugger Development Support - Programmable references with 32 voltage points • In-Circuit and In-Application Programming • Charge Time Measurement Unit (CTMU): • Two Program and Two Complex Data Breakpoints - Supports mTouch™ capacitive touch sensing • IEEE 1149.2 Compatible (JTAG) Boundary Scan - Provides high-resolution time measurement (1 ns) • Trace and Run-Time Watch - On-chip temperature measurement  2011-2013 Microchip Technology Inc. DS70000657H-page 1

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table1 (General Purpose Families) and Table2 (Motor Control Families). Their pinout diagrams appear on the following pages. TABLE 1: dsPIC33EPXXXGP50X and PIC24EPXXXGP20X GENERAL PURPOSE FAMILIES Device Page Erase Size (Instructions) Program Flash Memory (Kbytes) RAM (Kbyte) 16-Bit/32-Bit Timers Input CaptureRemaOutput CompareppableUART Peri(2)pSPIheralECAN™ Technologys (3)External Interrupts 2IC™ CRC Generator 10-Bit/12-Bit ADC (Channels) Op Amps/Comparators CTMU PTG I/O Pins Pins Packages PIC24EP32GP202 512 32 4 PIC24EP64GP202 1024 64 8 SPDIP, PIC24EP128GP202 1024 128 16 5 4 4 2 2 — 3 2 1 6 2/3(1) Yes Yes 21 28 SSSOOIPC(4, ), PIC24EP256GP202 1024 256 32 QFN-S PIC24EP512GP202 1024 512 48 PIC24EP32GP203 512 32 4 5 4 4 2 2 — 3 2 1 8 3/4 Yes Yes 25 36 VTLA PIC24EP64GP203 1024 64 8 PIC24EP32GP204 512 32 4 PIC24EP64GP204 1024 64 8 VTLA(4), 44/ TQFP, PIC24EP128GP204 1024 128 16 5 4 4 2 2 — 3 2 1 9 3/4 Yes Yes 35 48 QFN, PIC24EP256GP204 1024 256 32 UQFN PIC24EP512GP204 1024 512 48 PIC24EP64GP206 1024 64 8 PIC24EP128GP206 1024 128 16 TQFP, 5 4 4 2 2 — 3 2 1 16 3/4 Yes Yes 53 64 PIC24EP256GP206 1024 256 32 QFN PIC24EP512GP206 1024 512 48 dsPIC33EP32GP502 512 32 4 dsPIC33EP64GP502 1024 64 8 SPDIP, dsPIC33EP128GP502 1024 128 16 5 4 4 2 2 1 3 2 1 6 2/3(1) Yes Yes 21 28 SSSOOIPC(4, ), dsPIC33EP256GP502 1024 256 32 QFN-S dsPIC33EP512GP502 1024 512 48 dsPIC33EP32GP503 512 32 4 5 4 4 2 2 1 3 2 1 8 3/4 Yes Yes 25 36 VTLA dsPIC33EP64GP503 1024 64 8 dsPIC33EP32GP504 512 32 4 dsPIC33EP64GP504 1024 64 8 VTLA(4), 44/ TQFP, dsPIC33EP128GP504 1024 128 16 5 4 4 2 2 1 3 2 1 9 3/4 Yes Yes 35 48 QFN, dsPIC33EP256GP504 1024 256 32 UQFN dsPIC33EP512GP504 1024 512 48 dsPIC33EP64GP506 1024 64 8 dsPIC33EP128GP506 1024 128 16 TQFP, 5 4 4 2 2 1 3 2 1 16 3/4 Yes Yes 53 64 dsPIC33EP256GP506 1024 256 32 QFN dsPIC33EP512GP506 1024 512 48 Note1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section25.0 “Op Amp/Comparator Module” for details. 2: Only SPI2 is remappable. 3: INT0 is not remappable. 4: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory. DS70000657H-page 2  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 2: dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X MOTOR CONTROL FAMILIES Device Page Erase Size (Instructions) Program Flash Memory (Kbytes) RAM (Kbytes) 16-Bit/32-Bit Timers Input Capture Output CompareRem(4)Motor Control PWMap(Channels)pableQuadrature Encoder Interface PeriUARTpher(2)aSPIls ECAN™ Technology (3)External Interrupts 2IC™ CRC Generator 10-Bit/12-Bit ADC (Channels) Op Amps/Comparators CTMU PTG I/O Pins Pins Packages PIC24EP32MC202 512 32 4 PIC24EP64MC202 1024 64 8 SPDIP, PIC24EP128MC202 1024 128 16 5 4 4 6 1 2 2 — 3 2 1 6 2/3(1) Yes Yes 21 28 SSSOOIPC(5, ), PIC24EP256MC202 1024 256 32 QFN-S PIC24EP512MC202 1024 512 48 PIC24EP32MC203 512 32 4 5 4 4 6 1 2 2 — 3 2 1 8 3/4 Yes Yes 25 36 VTLA PIC24EP64MC203 1024 64 8 PIC24EP32MC204 512 32 4 PIC24EP64MC204 1024 64 8 VTLA(5), 44/ TQFP, PIC24EP128MC204 1024 128 16 5 4 4 6 1 2 2 — 3 2 1 9 3/4 Yes Yes 35 48 QFN, PIC24EP256MC204 1024 256 32 UQFN PIC24EP512MC204 1024 512 48 PIC24EP64MC206 1024 64 8 PIC24EP128MC206 1024 128 16 TQFP, 5 4 4 6 1 2 2 — 3 2 1 16 3/4 Yes Yes 53 64 PIC24EP256MC206 1024 256 32 QFN PIC24EP512MC206 1024 512 48 dsPIC33EP32MC202 512 32 4 dsPIC33EP64MC202 1024 64 8 SPDIP, dsPIC33EP128MC202 1024 128 16 5 4 4 6 1 2 2 — 3 2 1 6 2/3(1) Yes Yes 21 28 SSSOOIPC(5, ), dsPIC33EP256MC202 1024 256 32 QFN-S dsPIC33EP512MC202 1024 512 48 dsPIC33EP32MC203 512 32 4 5 4 4 6 1 2 2 — 3 2 1 8 3/4 Yes Yes 25 36 VTLA dsPIC33EP64MC203 1024 64 8 dsPIC33EP32MC204 512 32 4 dsPIC33EP64MC204 1024 64 8 VTLA(5), 44/ TQFP, dsPIC33EP128MC204 1024 128 16 5 4 4 6 1 2 2 — 3 2 1 9 3/4 Yes Yes 35 48 QFN, dsPIC33EP256MC204 1024 256 32 UQFN dsPIC33EP512MC204 1024 512 48 dsPIC33EP64MC206 1024 64 8 dsPIC33EP128MC206 1024 128 16 TQFP, 5 4 4 6 1 2 2 — 3 2 1 16 3/4 Yes Yes 53 64 dsPIC33EP256MC206 1024 256 32 QFN dsPIC33EP512MC206 1024 512 48 dsPIC33EP32MC502 512 32 4 dsPIC33EP64MC502 1024 64 8 SPDIP, dsPIC33EP128MC502 1024 128 16 5 4 4 6 1 2 2 1 3 2 1 6 2/3(1) Yes Yes 21 28 SSSOOIPC(5, ), dsPIC33EP256MC502 1024 256 32 QFN-S dsPIC33EP512MC502 1024 512 48 dsPIC33EP32MC503 512 32 4 5 4 4 6 1 2 2 1 3 2 1 8 3/4 Yes Yes 25 36 VTLA dsPIC33EP64MC503 1024 64 8 Note1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section25.0 “Op Amp/Comparator Module” for details. 2: Only SPI2 is remappable. 3: INT0 is not remappable. 4: Only the PWM Faults are remappable. 5: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.  2011-2013 Microchip Technology Inc. DS70000657H-page 3

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 2: dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X MOTOR CONTROL FAMILIES (CONTINUED) Device Page Erase Size (Instructions) Program Flash Memory (Kbytes) RAM (Kbytes) 16-Bit/32-Bit Timers Input Capture Output CompareRem(4)Motor Control PWMap(Channels)pableQuadrature Encoder Interface PeriUARTpher(2)aSPIls ECAN™ Technology (3)External Interrupts 2IC™ CRC Generator 10-Bit/12-Bit ADC (Channels) Op Amps/Comparators CTMU PTG I/O Pins Pins Packages dsPIC33EP32MC504 512 32 4 dsPIC33EP64MC504 1024 64 8 VTLA(5), 44/ TQFP, dsPIC33EP128MC504 1024 128 16 5 4 4 6 1 2 2 1 3 2 1 9 3/4 Yes Yes 35 48 QFN, dsPIC33EP256MC504 1024 256 32 UQFN dsPIC33EP512MC504 1024 512 48 dsPIC33EP64MC506 1024 64 8 dsPIC33EP128MC506 1024 128 16 TQFP, 5 4 4 6 1 2 2 1 3 2 1 16 3/4 Yes Yes 53 64 dsPIC33EP256MC506 1024 256 32 QFN dsPIC33EP512MC506 1024 512 48 Note1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section25.0 “Op Amp/Comparator Module” for details. 2: Only SPI2 is remappable. 3: INT0 is not remappable. 4: Only the PWM Faults are remappable. 5: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory. DS70000657H-page 4  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams 28-Pin SPDIP/SOIC/SSOP(1,2) = Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/OA2OUT/RA0 2 27 AVSS AN1/C2IN1+/RA1 3 26 RPI47/T5CK/RB15 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4 2 25 RPI46/T3CK/RB14 02 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 5 50 24 RPI45/CTPLS/RB13 P2 PGEC1/AN4/C1IN1+/RPI34/RB2 6 XGGP 23 RPI44/RB12 PGED1/AN5/C1IN1-/RP35/RB3 7 XXXX 22 TDI/RP43/RB11 PX VSS 8 EP 21 TDO/RP42/RB10 3E OSC1/CLKI/RA2 9 C324 20 VCAP OSC2/CLKO/RA3 10 sPIPIC 19 VSS RP36/RB4 11 d 18 TMS/ASDA1/SDI1/RP41/RB9(3) CVREF2O/RP20/T1CK/RA4 12 17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8 VDD 13 16 SCK1/RP39/INT0/RB7 PGED2/ASDA2/RP37/RB5 14 15 PGEC2/ASCL2/RP38/RB6 MCLR 1 28 AVDD AN0/OA2OUT/RA0 2 27 AVSS AN1/C2IN1+/RA1 3 26 RPI47/PWM1L/T5CK/RB15 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 4 02 25 RPI46/PWM1H/T3CK/RB14 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 5 2/502 24 RPI45/PWM2L/CTPLS/RB13 02 PGEC1/AN4/C1IN1+/RPI34/RB2 6 C2MC 23 RPI44/PWM2H/RB12 PGED1/AN5/C1IN1-/RP35/RB3 7 MX 22 TDI/RP43/PWM3L/RB11 XX VSS 8 XXPX 21 TDO/RP42/PWM3H/RB10 PE OSC1/CLKI/RA2 9 E4 20 VCAP 32 OFLSTC322//CRLPK3O6//RRAB34 1110 PIC3PIC 1198 TVMSSS/ASDA1/SDI1/RP41/RB9(3) s d CVREF2O/RP20/T1CK/RA4 12 17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8 VDD 13 16 SCK1/RP39/INT0/RB7 PGED2/ASDA2/RP37/RB5 14 15 PGEC2/ASCL2/RP38/RB6 Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 5

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 28-Pin QFN-S(1,2,3) = Pins are up to 5V tolerant 1 A0 15 14 A R B B +/R UT/ K/R K/R 1 O C C N 2 5 3 2I A T T N1/C N0/O CLR VDD VSS PI47/ PI46/ A A M A A R R 28 27 26 25 24 23 22 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 1 21 RPI45/CTPLS/RB13 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 2 20 RPI44/RB12 PGEC1/AN4/C1IN1+/RPI34/RB2 3 19 TDI/RP43/RB11 dsPIC33EPXXXGP502 PGED1/AN5/C1IN1-/RP35/RB3 4 18 TDO/RP42/RB10 PIC24EPXXXGP202 VSS 5 17 VCAP OSC1/CLKI/RA2 6 16 VSS OSC2/CLKO/RA3 7 15 TMS/ASDA1/SDI1/RP41/RB9(4) 8 9 10 11 12 13 14 4 4 D 5 6 7 8 B A D B B B B R R V R R R R 6/ K/ 7/ 8/ 0/ K/ 3 C 3 3 T C RP /RP20/T1REFO2 ED2/ASDA2/RP EC2/ASCL2/RP SCK1/RP39/IN SDO1/RP40/T4 CV PG PG L1/ C S A /O F1 E R V C K/ C T Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 6  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 28-Pin QFN-S(1,2,3) = Pins are up to 5V tolerant B15 B14 R R K/ K/ +/RA1 UT/RA0 M1L/T5C M1H/T3C N1 2O W W 2I A P P AN1/C AN0/O MCLR AVDD AVSS RPI47/ RPI46/ 28 27 26 25 24 23 22 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 1 21 RPI45/PWM2L/CTPLS/RB13 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 2 20 RPI44/PWM2H/RB12 PGEC1/AN4/C1IN1+/RPI34/RB2 3 19 TDI/RP43/PWM3L/RB11 dsPIC33EPXXXMC202/502 PGED1/AN5/C1IN1-/RP35/RB3 4 PIC24EPXXXMC202 18 TDO/RP42/PWM3H/RB10 VSS 5 17 VCAP OSC1/CLKI/RA2 6 16 VSS OSC2/CLKO/RA3 7 15 TMS/ASDA1/SDI1/RP41/RB9(4) 8 9 10 11 12 13 14 4 4 D 5 6 7 8 B A D B B B B R R V R R R R 6/ K/ 7/ 8/ 0/ K/ 3 C 3 3 T C FLT32/RP /RP20/T1REFO2 ED2/ASDA2/RP EC2/ASCL2/RP SCK1/RP39/IN SDO1/RP40/T4 CV PG PG L1/ C S A /O 1 F E R V C K/ C T Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 7

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) = Pins are up to 5V tolerant 0 RB1 2/RB CTED1/ 2/CTED 33/ PI3 RPI 1/R OUT/ 1-/SS 1 N OA C2I V+/AN3/REF V-/AN2/REF N1+/RA1 2OUT/RA0 5CK/RB15 3CK/RB14 PGEC3/ PGED3/ AN1/C2I AN0/OA MCLR AVDD AVSS RPI47/T RPI46/T 36 35 34 33 32 31 30 29 28 27 RPI45/CTPLS/RB13 PGEC1/AN4/C1IN1+/RPI34/RB2 1 26 RPI44/RB12 PGED1/AN5/C1IN1-/RP35/RB3 2 25 TDI/RP43/RB11 AN6/OA3OUT/C4IN1+/OCFB/RC0 3 24 TDO/RP42/RB10 dsPIC33EP32GP503 AN7/C3IN1-/C4IN1-/RC1 4 dsPIC33EP64GP503 23 VDD VDD 5 PPIICC2244EEPP6324GGPP220033 22 VCAP VSS 6 21 VSS OSC1/CLKI/RA2 7 20 RP56/RC8 OSC2/CLKO/RA3 8 19 TMS/ASDA1/SDI1/RP41/RB9(4) SDA2/RPI24/RA8 9 10 11 12 13 14 15 16 1177 18 4 4 S D D 5 6 7 8 B A S D D B B B B R R V V V R R R R 6/ K/ 7/ 8/ 0/ K/ 3 C 3 3 T C SCL2/RP /RP20/T1REFO2 ED2/ASDA2/RP EC2/ASCL2/RP SCK1/RP39/IN SDO1/RP40/T4 CV PG PG L1/ C S A /O 1 F E R V C K/ C T Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 8  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) = Pins are up to 5V tolerant 0 RB1 2/RB CTED1/ 2/CTED 33/ PI3 RPI 1/R OA1OUT/ C2IN1-/SS K/RB15 K/RB14 V+/AN3/REF V-/AN2/REF N1+/RA1 2OUT/RA0 WM1L/T5C WM1H/T3C PGEC3/ PGED3/ AN1/C2I AN0/OA MCLR AVDD AVSS RPI47/P RPI46/P 36 35 34 33 32 31 30 29 28 27 RPI45/PWM2L/CTPLS/RB13 PGEC1/AN4/C1IN1+/RPI34/RB2 1 26 RPI44/PWM2H/RB12 PGED1/AN5/C1IN1-/RP35/RB3 2 25 TDI/RP43/PWM3L/RB11 AN6/OA3OUT/C4IN1+/OCFB/RC0 3 24 TDO/RP42/PWM3H/RB10 dsPIC33EP32MC203/503 AN7/C3IN1-/C4IN1-/RC1 4 dsPIC33EP64MC203/503 23 VDD VDD 5 PIC24EP32MC203 22 VCAP PIC24EP64MC203 VSS 6 21 VSS OSC1/CLKI/RA2 7 20 RP56/RC8 OSC2/CLKO/RA3 8 19 TMS/ASDA1/SDI1/RP41/RB9(4) SDA2/RPI24/RA8 9 10 11 12 13 14 15 16 17 18 4 4 S D D 5 6 7 8 B A S D D B B B B R R V V V R R R R 6/ K/ 7/ 8/ 0/ K/ 3 C 3 3 T C FLT32/SCL2/RP CV/RP20/T1REFO2 PGED2/ASDA2/RP PGEC2/ASCL2/RP SCK1/RP39/IN L1/SDO1/RP40/T4 C S A /O 1 F E R V C K/ C T Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 9

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 44-Pin TQFP(1,2) = Pins are up to 5V tolerant 8 B R K/ T4C RA4 0/ K/ P4 B6 B5 1C R R R T CL1/ P38/ P37/ P20/ CK/CV/ASREFO1 P39/INT0/RB7 GEC2/ASCL2/R GED2/ASDA2/R DD SS CL1/RPI53/RC5 DA1/RPI52/RC4 CK1/RPI51/RC3 DI1/RPI25/RA9 V/SDO1/RREFO2 T R P P V V S S S S C 4 3 2 1 0 9 8 7 6 5 4 4 4 4 4 4 3 3 3 3 3 3 TMS/ASDA1/RP41/RB9(3) 1 33 SCL2/RP36/RB4 RP54/RC6 2 32 SDA2/RPI24/RA8 RP55/RC7 3 31 OSC2/CLKO/RA3 RP56/RC8 4 30 OSC1/CLKI/RA2 RP57/RC9 5 29 VSS dsPIC33EPXXXGP504 VSS 6 PIC24EPXXXGP204 28 VDD VCAP 7 27 AN8/C3IN1+/U1RTS/BCLK1/RC2 RP42/RB10 8 26 AN7/C3IN1-/C4IN1-/RC1 RP43/RB11 9 25 AN6/OA3OUT/C4IN1+/OCFB/RC0 RPI44/RB12 10 24 PGED1/AN5/C1IN1-/RP35/RB3 RPI45/CTPLS/RB13 11 23 PGEC1/AN4/C1IN1+/RPI34/RB2 2 3 4 5 6 7 8 9 0 1 2 1 1 1 1 1 1 1 1 2 2 2 0 7 4 5 S D R 0 1 0 1 DO/RA1 TDI/RA CK/RB1 CK/RB1 AVS AVD MCL OUT/RA N1+/RA ED2/RB ED1/RB T PI46/T3 PI47/T5 N0/OA2 AN1/C2I PI32/CT PI33/CT R R A R R 1/ T/ S U S O N1-/ OA1 2/C2I AN3/ -/ANF +/REF E V VR 3/ ED3/ GEC G P P Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 10  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 44-Pin TQFP(1,2) = Pins are up to 5V tolerant 8 B R K/ T4C RA4 0/ K/ 4 6 5 C P B B 1 R R R T CL1/ P38/ P37/ P20/ CK/CV/ASREFO1 P39/INT0/RB7 GEC2/ASCL2/R GED2/ASDA2/R DD SS CL1/RPI53/RC5 DA1/RPI52/RC4 CK1/RPI51/RC3 DI1/RPI25/RA9 V/SDO1/RREFO2 T R P P V V S S S S C 4 3 2 1 0 9 8 7 6 5 4 4 4 4 4 4 3 3 3 3 3 3 TMS/ASDA1/RP41/RB9(3) 1 33 FLT32/SCL2/RP36/RB4 RP54/RC6 2 32 SDA2/RPI24/RA8 RP55/RC7 3 31 OSC2/CLKO/RA3 RP56/RC8 4 30 OSC1/CLKI/RA2 RP57/RC9 5 29 VSS dsPIC33EPXXXMC204/504 VSS 6 PIC24EPXXXMC204 28 VDD VCAP 7 27 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 RP42/PWM3H/RB10 8 26 AN7/C3IN1-/C4IN1-/RC1 RP43/PWM3L/RB11 9 25 AN6/OA3OUT/C4IN1+/OCFB/RC0 RPI44/PWM2H/RB12 10 24 PGED1/AN5/C1IN1-/RP35/RB3 RPI45/PWM2L/CTPLS/RB13 11 23 PGEC1/AN4/C1IN1+/RPI34/RB2 2 3 4 5 6 7 8 9 0 1 2 1 1 1 1 1 1 1 1 2 2 2 0 7 4 5 S D R 0 1 0 1 DO/RA1 TDI/RA CK/RB1 CK/RB1 AVS AVD MCL OUT/RA N1+/RA ED2/RB ED1/RB T WM1H/T3 WM1L/T5 AN0/OA2 AN1/C2I RPI32/CT RPI33/CT RPI46/P RPI47/P N1-/SS1/ OA1OUT/ 2/C2I AN3/ -/ANF +/REF E V VR 3/ ED3/ GEC G P P Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 11

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 44-Pin VTLA(1,2,3) = Pins are up to 5V tolerant 8 B R K/ T4C RA4 0/ K/ 4 6 5 C P B B 1 R R R T CL1/ P38/ P37/ P20/ CK/CV/ASREFO1 P39/INT0/RB7 GEC2/ASCL2/R GED2/ASDA2/R DD SS CL1/RPI53/RC5 DA1/RPI52/RC4 CK1/RPI51/RC3 DI1/RPI25/RA9 V/SDO1/RREFO2 T R P P V V S S S S C 44 43 42 41 40 39 38 37 36 35 34 33 SCL2/RP36/RB4 TMS/ASDA1/RP41/RB9(4) 1 32 SDA2/RPI24/RA8 RP54/RC6 2 31 OSC2/CLKO/RA3 RP55/RC7 3 30 OSC1/CLKI/RA2 RP56/RC8 4 29 VSS RP57/RC9 5 dsPIC33EPXXXGP504 28 VDD VSS 6 PIC24EPXXXGP204 27 AN8/C3IN1+/U1RTS/BCLK1/RC2 VCAP 7 26 AN7/C3IN1-/C4IN1-/RC1 RP42/RB10 8 25 AN6/OA3OUT/C4IN1+/OCFB/RC0 RP43/RB11 9 24 PGED1/AN5/C1IN1-/RP35/RB3 RPI44/RB12 10 23 PGEC1/AN4/C1IN1+/RPI34/RB2 RPI45/CTPLS/RB13 11 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 DO/RA1 TDI/RA CK/RB1 CK/RB1 AVS AVD MCL OUT/RA N1+/RA ED2/RB ED1/RB T PI46/T3 PI47/T5 N0/OA2 AN1/C2I PI32/CT PI33/CT R R A R R 1/ T/ S U S O N1-/ OA1 2/C2I AN3/ -/ANF +/REF E V VR 3/ ED3/ GEC G P P Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 12  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 44-Pin VTLA(1,2,3) = Pins are up to 5V tolerant 8 B R K/ T4C RA4 0/ K/ 4 6 5 C P B B 1 R R R T CL1/ P38/ P37/ P20/ CK/CV/ASREFO1 P39/INT0/RB7 GEC2/ASCL2/R GED2/ASDA2/R DD SS CL1/RPI53/RC5 DA1/RPI52/RC4 CK1/RPI51/RC3 DI1/RPI25/RA9 V/SDO1/RREFO2 T R P P V V S S S S C 44 43 42 41 40 39 38 37 36 35 34 33 FLT32/SCL2/RP36/RB4 TMS/ASDA1/RP41/RB9(4) 1 32 SDA2/RPI24/RA8 RP54/RC6 2 31 OSC2/CLKO/RA3 RP55/RC7 3 30 OSC1/CLKI/RA2 RP56/RC8 4 29 VSS RP57/RC9 5 dsPIC33EPXXXMC204/504 28 VDD VSS 6 PIC24EPXXXMC204 27 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 VCAP 7 26 AN7/C3IN1-/C4IN1-/RC1 RP42/PWM3H/RB10 8 25 AN6/OA3OUT/C4IN1+/OCFB/RC0 RP43/PWM3L/RB11 9 24 PGED1/AN5/C1IN1-/RP35/RB3 RPI44/PWM2H/RB12 10 23 PGEC1/AN4/C1IN1+/RPI34/RB2 RPI45/PWM2L/CTPLS/RB13 11 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 DO/RA1 TDI/RA CK/RB1 CK/RB1 AVS AVD MCL OUT/RA N1+/RA ED2/RB ED1/RB T WM1H/T3 WM1L/T5 AN0/OA2 AN1/C2I RPI32/CT RPI33/CT RPI46/P RPI47/P N1-/SS1/ OA1OUT/ 2/C2I AN3/ -/ANF +/REF E V VR 3/ ED3/ GEC G P P Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 13

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 44-Pin QFN(1,2,3) = Pins are up to 5V tolerant 8 B R K/ T4C RA4 0/ K/ 4 6 5 C P B B 1 R R R T CL1/ P38/ P37/ P20/ CK/CV/ASREFO1 P39/INT0/RB7 GEC2/ASCL2/R GED2/ASDA2/R DD SS CL1/RPI53/RC5 DA1/RPI52/RC4 CK1/RPI51/RC3 DI1/RPI25/RA9 V/SDO1/RREFO2 T R P P V V S S S S C 44 43 42 41 40 39 38 37 36 35 34 TMS/ASDA1/RP41/RB9(4) 1 33 SCL2/RP36/RB4 RP54/RC6 2 32 SDA2/RPI24/RA8 RP55/RC7 3 31 OSC2/CLKO/RA3 RP56/RC8 4 30 OSC1/CLKI/RA2 RP57/RC9 5 29 VSS dsPIC33EPXXXGP504 VSS 6 28 VDD PIC24EPXXXGP204 VCAP 7 27 AN8/C3IN1+/U1RTS/BCLK1/RC2 RP42/RB10 8 26 AN7/C3IN1-/C4IN1-/RC1 RP43/RB11 9 25 AN6/OA3OUT/C4IN1+/OCFB/RC0 RPI44/RB12 10 24 PGED1/AN5/C1IN1-/RP35/RB3 RPI45/CTPLS/RB13 11 23 PGEC1/AN4/C1IN1+/RPI34/RB2 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 DO/RA1 TDI/RA CK/RB1 CK/RB1 AVS AVD MCL OUT/RA N1+/RA ED2/RB ED1/RB T PI46/T3 PI47/T5 N0/OA2 AN1/C2I PI32/CT PI33/CT R R A R R 1/ T/ S U S O N1-/ OA1 2/C2I AN3/ -/ANEF V+/REF VR 3/ ED3/ GEC G P P Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 14  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 44-Pin QFN(1,2,3) = Pins are up to 5V tolerant 8 B R K/ T4C RA4 0/ K/ 4 6 5 C P B B 1 R R R T CL1/ P38/ P37/ P20/ CK/CV/ASREFO1 P39/INT0/RB7 GEC2/ASCL2/R GED2/ASDA2/R DD SS CL1/RPI53/RC5 DA1/RPI52/RC4 CK1/RPI51/RC3 DI1/RPI25/RA9 V/SDO1/RREFO2 T R P P V V S S S S C 44 43 42 41 40 39 38 37 36 35 34 TMS/ASDA1/RP41/RB9(4) 1 33 FLT32/SCL2/RP36/RB4 RP54/RC6 2 32 SDA2/RPI24/RA8 RP55/RC7 3 31 OSC2/CLKO/RA3 RP56/RC8 4 30 OSC1/CLKI/RA2 RP57/RC9 5 29 VSS dsPIC33EPXXXMC204/504 VSS 6 PIC24EPXXXMC204 28 VDD VCAP 7 27 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 RP42/PWM3H/RB10 8 26 AN7/C3IN1-/C4IN1-/RC1 RP43/PWM3L/RB11 9 25 AN6/OA3OUT/C4IN1+/OCFB/RC0 RPI44/PWM2H/RB12 10 24 PGED1/AN5/C1IN1-/RP35/RB3 RPI45/PWM2L/CTPLS/RB13 11 23 PGEC1/AN4/C1IN1+/RPI34/RB2 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 DO/RA1 TDI/RA CK/RB1 CK/RB1 AVS AVD MCL OUT/RA N1+/RA ED2/RB ED1/RB T WM1H/T3 WM1L/T5 AN0/OA2 AN1/C2I RPI32/CT RPI33/CT RPI46/P RPI47/P N1-/SS1/ OA1OUT/ 2/C2I AN3/ -/ANF +/REF E V VR 3/ ED3/ GEC G P P Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 15

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 48-Pin UQFN(1,2,3) = Pins are up to 5V tolerant 8 B R K/ T4C RA4 0/ K/ 4 6 5 C P B B 1 R R R T CL1/ P38/ P37/ P20/ TCK/CV/ASREFO1 RP39/INT0/RB7 PGEC2/ASCL2/R PGED2/ASDA2/R N/C VDD VSS SCL1/RPI53/RC5 SDA1/RPI52/RC4 SCK1/RPI51/RC3 SDI1/RPI25/RA9 CV/SDO1/RREFO2 48 47 46 45 44 43 42 41 40 39 38 37 TMS/ASDA1/RP41/RB9(4) 1 36 SCL2/RP36/RB4 RP54/RC6 2 35 SDA2/RPI24/RA8 RP55/RC7 3 34 OSC2/CLKO/RA3 RP56/RC8 4 33 OSC1/CLKI/RA2 RP57/RC9 5 32 N/C VSS 6 dsPIC33EPXXXGP504 31 VSS VCAP 7 PIC24EPXXXGP204 30 VDD N/C 8 29 AN8/C3IN1+/U1RTS/BCLK1/RC2 RP42/RB10 9 28 AN7/C3IN1-/C4IN1-/RC1 RP43/RB11 10 27 AN6/OA3OUT/C4IN1+/OCFB/RC0 RPI44/RB12 11 26 PGED1/AN5/C1IN1-/RP35/RB3 RPI45/CTPLS/RB13 12 25 PGEC1/AN4/C1IN1+/RPI34/RB2 13 14 15 16 17 18 19 20 21 22 23 24 0 7 4 5 S D R C 0 1 0 1 DO/RA1 TDI/RA CK/RB1 CK/RB1 AVS AVD MCL N/ OUT/RA N1+/RA ED2/RB ED1/RB T T3 T5 A2 C2I CT CT PI46/ PI47/ N0/O AN1/ PI32/ PI33/ R R A R R 1/ T/ S U S O N1-/ OA1 2/C2I AN3/ -/ANF +/REF E V VR 3/ ED3/ GEC G P P Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 16  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 48-Pin UQFN(1,2,3) = Pins are up to 5V tolerant 8 B R K/ T4C RA4 0/ K/ 4 6 5 C P B B 1 R R R T CL1/ P38/ P37/ P20/ TCK/CV/ASREFO1 RP39/INT0/RB7 PGEC2/ASCL2/R PGED2/ASDA2/R N/C VDD VSS SCL1/RPI53/RC5 SDA1/RPI52/RC4 SCK1/RPI51/RC3 SDI1/RPI25/RA9 CV/SDO1/RREFO2 48 47 46 45 44 43 42 41 40 39 38 37 TMS/ASDA1/RP41/RB9(4) 1 36 FLT32/SCL2/RP36/RB4 RP54/RC6 2 35 SDA2/RPI24/RA8 RP55/RC7 3 34 OSC2/CLKO/RA3 RP56/RC8 4 33 OSC1/CLKI/RA2 RP57/RC9 5 32 N/C VSS 6 dsPIC33EPXXXMC204/504 31 VSS VCAP 7 PIC24EPXXXMC204 30 VDD N/C 8 29 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2 RP42/PWM3H/RB10 9 28 AN7/C3IN1-/C4IN1-/RC1 RP43/PWM3L/RB11 10 27 AN6/OA3OUT/C4IN1+/OCFB/RC0 RPI44/PWM2H/RB12 11 26 PGED1/AN5/C1IN1-/RP35/RB3 RPI45/PWM2L/CTPLS/RB13 12 25 PGEC1/AN4/C1IN1+/RPI34/RB2 13 14 15 16 17 18 19 20 21 22 23 24 0 7 4 5 S D R C 0 1 0 1 DO/RA1 TDI/RA CK/RB1 CK/RB1 AVS AVD MCL N/ OUT/RA N1+/RA ED2/RB ED1/RB T WM1H/T3 WM1L/T5 AN0/OA2 AN1/C2I RPI32/CT RPI33/CT RPI46/P RPI47/P N1-/SS1/ OA1OUT/ 2/C2I AN3/ -/ANF +/REF VRE 3/V ED3/ GEC G P P Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 17

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 64-Pin TQFP(1,2,3) = Pins are up to 5V tolerant (4)9 B 13 1/R B 4 R P DO/RA10 PI45/CTPLS/ PI44/RB12P43/RB11 P42/RB10 P97/RF1 PI96/RF0 DD CAP P57/RC9 D6 D5 P56/RC8 P55/RC7 P54/RC6MS/ASDA1/R T R RR R R R V V R R R R R RT 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 TDI/RA7 1 48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RPI46/T3CK/RB14 2 47 RC13 RPI47/T5CK/RB15 3 46 RP39/INT0/RB7 RP118/RG6 4 45 RPI58/RC10 RPI119/RG7 5 dsPIC33EP64GP506 44 PGEC2/ASCL2/RP38/RB6 RP120/RG8 6 dsPIC33EP128GP506 43 PGED2/ASDA2/RP37/RB5 MCLR 7 dsPIC33EP256GP506 42 RD8 RPI121/RG9 8 dsPIC33EP512GP506 41 VSS VSS 9 PIC24EP64GP206 40 OSC2/CLKO/RC15 VDD 10 PIC24EP128GP206 39 OSC1/CLKI/RC12 AN10/RPI28/RA12 11 PIC24EP256GP206 38 VDD AN9/RPI27/RA11 12 PIC24EP512GP206 37 SCL1/RPI53/RC5 AN0/OA2OUT/RA0 13 36 SDA1/RPI52/RC4 AN1/C2IN1+/RA1 14 35 SCK1/RPI51/RC3 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 SDI1/RPI25/RA9 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16 33 CVREF2O/SDO1/RP20/T1CK/RA4 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 2 3 D S 0 1 2 1 S D 2 3 4 5 8 4 B B D S C C C 1 S D 1 1 1 1 A B PGEC1/AN4/C1IN1+/RPI34/R PGED1/AN5/C1IN1-/RP35/R AV AV N6/OA3OUT/C4IN1+/OCFB/R AN7/C3IN1-/C4IN1-/R AN8/C3IN1+/U1RTS/BCLK1/R(3)AN11/C1IN2-/U1CTS/RC V V(3)2/C2IN2-/U2RTS/BCLK2/RE(3)AN13/C3IN2-/U2CTS/RE AN14/RPI94/RE AN15/RPI95/RE SDA2/RPI24/R SCL2/RP36/R A 1 N A Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 18  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 64-Pin TQFP(1,2,3) = Pins are up to 5V tolerant 3 1 S/RB (4)B9 DO/RA10 PI45/PWM2L/CTPL PI44/PWM2H/RB12 P43/PWM3L/RB11 P42/PWM3H/RB10 P97/RF1 PI96/RF0 DD CAP P57/RC9 D6 D5 P56/RC8 P55/RC7 P54/RC6MS/ASDA1/RP41/R T R R R R R R V V R R R R R RT 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 TDI/RA7 1 48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RPI46/PWM1H/T3CK/RB14 2 47 RC13 RPI47/PWM1L/T5CK/RB15 3 46 RP39/INT0/RB7 RP118/RG6 4 45 RPI58/RC10 RPI119/RG7 5 dsPIC33EP64MC206/506 44 PGEC2/ASCL2/RP38/RB6 RP120/RG8 6 dsPIC33EP128MC206/506 43 PGED2/ASDA2/RP37/RB5 MCLR 7 dsPIC33EP256MC206/506 42 RD8 RPI121/RG9 8 dsPIC33EP512MC206/506 41 VSS VSS 9 PIC24EP64MC206 40 OSC2/CLKO/RC15 VDD 10 PIC24EP128MC206 39 OSC1/CLKI/RC12 AN10/RPI28/RA12 11 PIC24EP256MC206 38 VDD AN9/RPI27/RA11 12 PIC24EP512MC206 37 SCL1/RPI53/RC5 AN0/OA2OUT/RA0 13 36 SDA1/RPI52/RC4 AN1/C2IN1+/RA1 14 35 SCK1/RPI51/RC3 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 SDI1/RPI25/RA9 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16 33 CVREF2O/SDO1/RP20/T1CK/RA4 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 PGEC1/AN4/C1IN1+/RPI34/RB2 PGED1/AN5/C1IN1-/RP35/RB3 AVDD AVSS AN6/OA3OUT/C4IN1+/OCFB/RC0 AN7/C3IN1-/C4IN1-/RC1 8/C3IN1+/U1RTS/BCLK1/FLT3/RC2(3)AN11/C1IN2-/U1CTS/FLT4/RC11VSS VDD(3)N12/C2IN2-/U2RTS/BCLK2/RE12(3)AN13/C3IN2-/U2CTS/RE13 AN14/RPI94/RE14 AN15/RPI95/RE15 SDA2/RPI24/RA8 FLT32/SCL2/RP36/RB4 N A A Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 19

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 64-Pin QFN(1,2,3,4) = Pins are up to 5V tolerant (5)9 B 13 1/R B 4 R P DO/RA10PI45/CTPLS/ PI44/RB12P43/RB11 P42/RB10 P97/RF1PI96/RF0 DD CAP P57/RC9 D6 D5 P56/RC8 P55/RC7 P54/RC6 MS/ASDA1/R TR RR R RR V V R R R R R R T 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 TDI/RA7 1 48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RPI46/T3CK/RB14 2 47 RC13 RPI47/T5CK/RB15 3 46 RP39/INT0/RB7 RP118/RG6 4 45 RPI58/RC10 RPI119/RG7 5 dsPIC33EP64GP506 44 PGEC2/ASCL2/RP38/RB6 RP120/RG8 6 dsPIC33EP128GP506 43 PGED2/ASDA2/RP37/RB5 MCLR 7 dsPIC33EP256GP506 42 RD8 RPI121/RG9 8 dsPIC33EP512GP506 41 VSS VSS 9 PIC24EP64GP206 40 OSC2/CLKO/RC15 VDD 10 PIC24EP128GP206 39 OSC1/CLKI/RC12 AN10/RPI28/RA12 11 PIC24EP256GP206 38 VDD AN9/RPI27/RA11 12 PIC24EP512GP206 37 SCL1/RPI53/RC5 AN0/OA2OUT/RA0 13 36 SDA1/RPI52/RC4 AN1/C2IN1+/RA1 14 35 SCK1/RPI51/RC3 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 SDI1/RPI25/RA9 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16 33 CVREF2O/SDO1/RP20/T1CK/RA4 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 23 D S 0 1 2 1 S D 2 3 4 5 8 4 PGEC1/AN4/C1IN1+/RPI34/RBPGED1/AN5/C1IN1-/RP35/RB AVD AVS AN6/OA3OUT/C4IN1+/OCFB/RC AN7/C3IN1-/C4IN1-/RC AN8/C3IN1+/U1RTS/BCLK1/RC(3)AN11/C1IN2-/U1CTS/RC1 VS VD(3)12/C2IN2-/U2RTS/BCLK2/RE1(3)AN13/C3IN2-/U2CTS/RE1 AN14/RPI94/RE1 AN15/RPI95/RE1 SDA2/RPI24/RA SCL2/RP36/RB N A Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: This pin is not available as an input when OPMODE (CMxCON<10>) = 1. 4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 20  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Pin Diagrams (Continued) 64-Pin QFN(1,2,3,4) = Pins are up to 5V tolerant 3 1 S/RB (5)B9 DO/RA10 PI45/PWM2L/CTPL PI44/PWM2H/RB12P43/PWM3L/RB11 P42/PWM3H/RB10 P97/RF1 PI96/RF0 DD CAP P57/RC9D6 D5 P56/RC8 P55/RC7 P54/RC6 MS/ASDA1/RP41/R T R RR R R R V V RR R R R R T 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 TDI/RA7 1 48 TCK/CVREF1O/ASCL1/RP40/T4CK/RB8 RPI46/PWM1H/T3CK/RB14 2 47 RC13 RPI47/PWM1L/T5CK/RB15 3 46 RP39/INT0/RB7 RP118/RG6 4 45 RPI58/RC10 RPI119/RG7 5 dsPIC33EP64MC206/506 44 PGEC2/ASCL2/RP38/RB6 RP120/RG8 6 dsPIC33EP128MC206/506 43 PGED2/ASDA2/RP37/RB5 MCLR 7 dsPIC33EP256MC206/506 42 RD8 RPI121/RG9 8 dsPIC33EP512MC206/506 41 VSS VSS 9 PIC24EP64MC206 40 OSC2/CLKO/RC15 VDD 10 PIC24EP128MC206 39 OSC1/CLKI/RC12 AN10/RPI28/RA12 11 PIC24EP256MC206 38 VDD AN9/RPI27/RA11 12 PIC24EP512MC206 37 SCL1/RPI53/RC5 AN0/OA2OUT/RA0 13 36 SDA1/RPI52/RC4 AN1/C2IN1+/RA1 14 35 SCK1/RPI51/RC3 PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 15 34 SDI1/RPI25/RA9 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 16 33 CVREF2O/SDO1/RP20/T1CK/RA4 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 2 3 D S 0 1 2 1 S D 2 3 4 5 8 4 PGEC1/AN4/C1IN1+/RPI34/RB PGED1/AN5/C1IN1-/RP35/RB AVD AVS AN6/OA3OUT/C4IN1+/OCFB/RC AN7/C3IN1-/C4IN1-/RC 8/C3IN1+/U1RTS/BCLK1/FLT3/RC(3)AN11/C1IN2-/U1CTS/FLT4/RC1VS VD(3)N12/C2IN2-/U2RTS/BCLK2/RE1(3)AN13/C3IN2-/U2CTS/RE1 AN14/RPI94/RE1 AN15/RPI95/RE1 SDA2/RPI24/RA FLT32/SCL2/RP36/RB N A A Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select (PPS)” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: This pin is not available as an input when OPMODE (CMxCON<10>) = 1. 4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 21

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Table of Contents 1.0 Device Overview........................................................................................................................................................................25 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers and Microcontrollers.........................................................29 3.0 CPU............................................................................................................................................................................................35 4.0 Memory Organization.................................................................................................................................................................45 5.0 Flash Program Memory............................................................................................................................................................119 6.0 Resets .....................................................................................................................................................................................123 7.0 Interrupt Controller...................................................................................................................................................................127 8.0 Direct Memory Access (DMA)..................................................................................................................................................139 9.0 Oscillator Configuration............................................................................................................................................................153 10.0 Power-Saving Features............................................................................................................................................................163 11.0 I/O Ports...................................................................................................................................................................................173 12.0 Timer1......................................................................................................................................................................................203 13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................207 14.0 Input Capture............................................................................................................................................................................213 15.0 Output Compare.......................................................................................................................................................................219 16.0 High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only).......................................225 17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)...........249 18.0 Serial Peripheral Interface (SPI)...............................................................................................................................................265 19.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................273 20.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................281 21.0 Enhanced CAN (ECAN™) Module (dsPIC33EPXXXGP/MC50X Devices Only).....................................................................287 22.0 Charge Time Measurement Unit (CTMU) ...............................................................................................................................315 23.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC)......................................................................................................................321 24.0 Peripheral Trigger Generator (PTG) Module............................................................................................................................337 25.0 Op Amp/Comparator Module...................................................................................................................................................355 26.0 Programmable Cyclic Redundancy Check (CRC) Generator..................................................................................................373 27.0 Special Features......................................................................................................................................................................379 28.0 Instruction Set Summary..........................................................................................................................................................387 29.0 Development Support...............................................................................................................................................................397 30.0 Electrical Characteristics..........................................................................................................................................................401 31.0 High-Temperature Electrical Characteristics............................................................................................................................467 32.0 DC and AC Device Characteristics Graphs..............................................................................................................................475 33.0 Packaging Information..............................................................................................................................................................479 Appendix A: Revision History.............................................................................................................................................................507 Index................................................................................................................................................................................................. 517 The Microchip Web Site.....................................................................................................................................................................525 Customer Change Notification Service..............................................................................................................................................525 Customer Support..............................................................................................................................................................................525 Product Identification System.............................................................................................................................................................527 DS70000657H-page 22  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011-2013 Microchip Technology Inc. DS70000657H-page 23

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Ref- erence Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the dsPIC33EP64MC506 product page of the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features and other documentation, the resulting page provides links to the related family reference manual sections. • “Introduction” (DS70573) • “CPU” (DS70359) • “Data Memory” (DS70595) • “Program Memory” (DS70613) • “Flash Programming” (DS70609) • “Interrupts” (DS70600) • “Oscillator” (DS70580) • “Reset” (DS70602) • “Watchdog Timer and Power-Saving Modes” (DS70615) • “I/O Ports” (DS70598) • “Timers” (DS70362) • “Input Capture” (DS70352) • “Output Compare” (DS70358) • “High-Speed PWM” (DS70645) • “Quadrature Encoder Interface (QEI)” (DS70601) • “Analog-to-Digital Converter (ADC)” (DS70621) • “UART” (DS70582) • “Serial Peripheral Interface (SPI)” (DS70569) • “Inter-Integrated Circuit (I2C™)” (DS70330) • “Enhanced Controller Area Network (ECAN™)” (DS70353) • “Direct Memory Access (DMA)” (DS70348) • “CodeGuard™ Security” (DS70634) • “Programming and Diagnostics” (DS70608) • “Op Amp/Comparator” (DS70357) • “Programmable Cyclic Redundancy Check (CRC)” (DS70346) • “Device Configuration” (DS70618) • “Peripheral Trigger Generator (PTG)” (DS70669) • “Charge Time Measurement Unit (CTMU)” (DS70661) DS70000657H-page 24  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 1.0 DEVICE OVERVIEW This document contains device-specific information for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ Note1: This data sheet summarizes the 50X and PIC24EPXXXGP/MC20X Digital Signal features of the dsPIC33EPXXXGP50X, Controller (DSC) and Microcontroller (MCU) devices. dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X PIC24EPXXXGP/MC20X families of devices contain extensive Digital Signal Processor devices. It is not intended to be a com- (DSP) functionality with a high-performance, 16-bit prehensive resource. To complement MCU architecture. the information in this data sheet, refer to the related section of the “dsPIC33/ Figure1-1 shows a general block diagram of the core PIC24 Family Reference Manual”, and peripheral modules. Table1-1 lists the functions of which is available from the Microchip the various pins shown in the pinout diagrams. web site (www.microchip.com) 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 1-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X BLOCK DIAGRAM PORTA CPU 16 Refer to Figure3-1 for CPU diagram details. PORTB PORTC Power-up Timer Timing Oscillator PORTD Generation Start-up Timer OSC1/CLKI POR/BOR PORTE MCLR Watchdog 16 Timer VDD, VSS AVDD, AVSS PORTF PORTG PTG COomp pAamrapt/or ECAN1(2) ADC CIanpptuutre COomutppaurte II22CC12, Remappable Pins PORTS CTMU QEI1(1) PWM(1) Timers CRC SSPPII12, UUAARRTT21, Peripheral Modules Note 1: This feature or peripheral is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. 2: This feature or peripheral is only available on dsPIC33EPXXXGP/MC50X devices.  2011-2013 Microchip Technology Inc. DS70000657H-page 25

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name(4) PPS Description Type Type AN0-AN15 I Analog No Analog input channels. CLKI I ST/ No External clock source input. Always associated with OSC1 pin function. CMOS CLKO O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/ No Oscillator crystal input. ST buffer when configured in RC mode; CMOS CMOS otherwise. OSC2 I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. REFCLKO O — Yes Reference clock output. IC1-IC4 I ST Yes Capture Inputs 1 through 4. OCFA I ST Yes Compare Fault A input (for Compare channels). OCFB I ST No Compare Fault B input (for Compare channels). OC1-OC4 O — Yes Compare Outputs 1 through 4. INT0 I ST No External Interrupt 0. INT1 I ST Yes External Interrupt 1. INT2 I ST Yes External Interrupt 2. RA0-RA4, RA7-RA12 I/O ST No PORTA is a bidirectional I/O port. RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC0-RC13, RC15 I/O ST No PORTC is a bidirectional I/O port. RD5, RD6, RD8 I/O ST No PORTD is a bidirectional I/O port. RE12-RE15 I/O ST No PORTE is a bidirectional I/O port. RF0, RF1 I/O ST No PORTF is a bidirectional I/O port. RG6-RG9 I/O ST No PORTG is a bidirectional I/O port. T1CK I ST No Timer1 external clock input. T2CK I ST Yes Timer2 external clock input. T3CK I ST No Timer3 external clock input. T4CK I ST No Timer4 external clock input. T5CK I ST No Timer5 external clock input. CTPLS O ST No CTMU pulse output. CTED1 I ST No CTMU External Edge Input 1. CTED2 I ST No CTMU External Edge Input 2. U1CTS I ST No UART1 Clear-To-Send. U1RTS O — No UART1 Ready-To-Send. U1RX I ST Yes UART1 receive. U1TX O — Yes UART1 transmit. BCLK1 O ST No UART1 IrDA® baud clock output. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer Note 1: This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: This pin is available on dsPIC33EPXXXGP/MC50X devices only. 3: This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See Section16.0 “High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)” for more information. 4: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability. 5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 26  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name(4) PPS Description Type Type U2CTS I ST No UART2 Clear-To-Send. U2RTS O — No UART2 Ready-To-Send. U2RX I ST Yes UART2 receive. U2TX O — Yes UART2 transmit. BCLK2 O ST No UART2 IrDA® baud clock output. SCK1 I/O ST No Synchronous serial clock input/output for SPI1. SDI1 I ST No SPI1 data in. SDO1 O — No SPI1 data out. SS1 I/O ST No SPI1 slave synchronization or frame pulse I/O. SCK2 I/O ST Yes Synchronous serial clock input/output for SPI2. SDI2 I ST Yes SPI2 data in. SDO2 O — Yes SPI2 data out. SS2 I/O ST Yes SPI2 slave synchronization or frame pulse I/O. SCL1 I/O ST No Synchronous serial clock input/output for I2C1. SDA1 I/O ST No Synchronous serial data input/output for I2C1. ASCL1 I/O ST No Alternate synchronous serial clock input/output for I2C1. ASDA1 I/O ST No Alternate synchronous serial data input/output for I2C1. SCL2 I/O ST No Synchronous serial clock input/output for I2C2. SDA2 I/O ST No Synchronous serial data input/output for I2C2. ASCL2 I/O ST No Alternate synchronous serial clock input/output for I2C2. ASDA2 I/O ST No Alternate synchronous serial data input/output for I2C2. TMS(5) I ST No JTAG Test mode select pin. TCK I ST No JTAG test clock input pin. TDI I ST No JTAG test data input pin. TDO O — No JTAG test data output pin. C1RX(2) I ST Yes ECAN1 bus receive pin. C1TX(2) O — Yes ECAN1 bus transmit pin. FLT1(1), FLT2(1) I ST Yes PWM Fault Inputs 1 and 2. FLT3(1), FLT4(1) I ST No PWM Fault Inputs 3 and 4. FLT32(1,3) I ST No PWM Fault Input 32 (Class B Fault). DTCMP1-DTCMP3(1) I ST Yes PWM Dead-Time Compensation Inputs 1 through 3. PWM1L-PWM3L(1) O — No PWM Low Outputs 1 through 3. PWM1H-PWM3H(1) O — No PWM High Outputs 1 through 3. SYNCI1(1) I ST Yes PWM Synchronization Input 1. SYNCO1(1) O — Yes PWM Synchronization Output 1. INDX1(1) I ST Yes Quadrature Encoder Index1 pulse input. HOME1(1) I ST Yes Quadrature Encoder Home1 pulse input. QEA1(1) I ST Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary timer external clock/gate input in Timer mode. QEB1(1) I ST Yes Quadrature Encoder Phase B input in QEI1 mode. Auxiliary timer external clock/gate input in Timer mode. CNTCMP1(1) O — Yes Quadrature Encoder Compare Output 1. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer Note 1: This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: This pin is available on dsPIC33EPXXXGP/MC50X devices only. 3: This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See Section16.0 “High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)” for more information. 4: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability. 5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2.  2011-2013 Microchip Technology Inc. DS70000657H-page 27

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name(4) PPS Description Type Type C1IN1- I Analog No Op Amp/Comparator 1 Negative Input 1. C1IN2- I Analog No Comparator 1 Negative Input 2. C1IN1+ I Analog No Op Amp/Comparator 1 Positive Input 1. OA1OUT O Analog No Op Amp 1 output. C1OUT O — Yes Comparator 1 output. C2IN1- I Analog No Op Amp/Comparator 2 Negative Input 1. C2IN2- I Analog No Comparator 2 Negative Input 2. C2IN1+ I Analog No Op Amp/Comparator 2 Positive Input 1. OA2OUT O Analog No Op Amp 2 output. C2OUT O — Yes Comparator 2 output. C3IN1- I Analog No Op Amp/Comparator 3 Negative Input 1. C3IN2- I Analog No Comparator 3 Negative Input 2. C3IN1+ I Analog No Op Amp/Comparator 3 Positive Input 1. OA3OUT O Analog No Op Amp 3 output. C3OUT O — Yes Comparator 3 output. C4IN1- I Analog No Comparator 4 Negative Input 1. C4IN1+ I Analog No Comparator 4 Positive Input 1. C4OUT O — Yes Comparator 4 output. CVREF1O O Analog No Op amp/comparator voltage reference output. CVREF2O O Analog No Op amp/comparator voltage reference divided by 2 output. PGED1 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 1. PGEC1 I ST No Clock input pin for Programming/Debugging Communication Channel 1. PGED2 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 2. PGEC2 I ST No Clock input pin for Programming/Debugging Communication Channel 2. PGED3 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 3. PGEC3 I ST No Clock input pin for Programming/Debugging Communication Channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P No Positive supply for analog modules. This pin must be connected at all times. AVSS P P No Ground reference for analog modules. This pin must be connected at all times. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. VSS P — No Ground reference for logic and I/O pins. VREF+ I Analog No Analog voltage reference (high) input. VREF- I Analog No Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer Note 1: This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: This pin is available on dsPIC33EPXXXGP/MC50X devices only. 3: This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See Section16.0 “High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)” for more information. 4: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability. 5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table27-2. DS70000657H-page 28  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 16-BIT The use of decoupling capacitors on every pair of DIGITAL SIGNAL power supply pins, such as VDD, VSS, AVDD and CONTROLLERS AND AVSS is required. MICROCONTROLLERS Consider the following criteria when using decoupling capacitors: Note1: This data sheet summarizes the • Value and type of capacitor: Recommendation features of the dsPIC33EPXXXGP50X, of 0.1 µF (100 nF), 10-20V. This capacitor should dsPIC33EPXXXMC20X/50X and be a low-ESR and have resonance frequency in PIC24EPXXXGP/MC20X families of the range of 20MHz and higher. It is devices. It is not intended to be a recommended to use ceramic capacitors. comprehensive reference source. To • Placement on the printed circuit board: The complement the information in this data decoupling capacitors should be placed as close sheet, refer to the related section of the to the pins as possible. It is recommended to “dsPIC33/PIC24 Family Reference place the capacitors on the same side of the Manual”, which is available from the board as the device. If space is constricted, the Microchip web site (www.microchip.com) capacitor can be placed on another layer on the 2: Some registers and associated bits PCB using a via; however, ensure that the trace described in this section may not be length from the pin to the capacitor is within available on all devices. Refer to one-quarter inch (6mm) in length. Section4.0 “Memory Organization” in • Handling high-frequency noise: If the board is this data sheet for device-specific register experiencing high-frequency noise, above tens and bit information. of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling 2.1 Basic Connection Requirements capacitor. The value of the second capacitor can be in the range of 0.01µF to 0.001µF. Place this Getting started with the dsPIC33EPXXXGP50X, second capacitor next to the primary decoupling dsPIC33EPXXXMC20X/50X and capacitor. In high-speed circuit designs, consider PIC24EPXXXGP/MC20X families requires attention implementing a decade pair of capacitances as to a minimal set of device pin connections before close to the power and ground pins as possible. proceeding with development. The following is a list For example, 0.1 µF in parallel with 0.001 µF. of pin names, which must always be connected: • Maximizing performance: On the board layout • All VDD and VSS pins from the power supply circuit, run the power and (see Section2.2 “Decoupling Capacitors”) return traces to the decoupling capacitors first, • All AVDD and AVSS pins (regardless if ADC module and then to the device pins. This ensures that the is not used) decoupling capacitors are first in the power chain. (see Section2.2 “Decoupling Capacitors”) Equally important is to keep the trace length • VCAP between the capacitor and the power pins to a (see Section2.3 “CPU Logic Filter Capacitor minimum, thereby reducing PCB track Connection (VCAP)”) inductance. • MCLR pin (see Section2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins are used when external voltage reference for the ADC module is implemented Note: The AVDD and AVSS pins must be connected, independent of the ADC voltage reference source.  2011-2013 Microchip Technology Inc. DS70000657H-page 29

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 2-1: RECOMMENDED 2.3 CPU Logic Filter Capacitor MINIMUM CONNECTION Connection (VCAP) A low-ESR (< 1 Ohm) capacitor is required on the VCAP VDD 10 µF 0.1 µF pin, which is used to stabilize the voltage regulator Tantalum Ceramic output voltage. The VCAP pin must not be connected to P D S VDD and must have a capacitor greater than 4.7µF R A D S R1 VC V V (10µF is recommended), 16V connected to ground. The MCLR type can be ceramic or tantalum. See Section30.0 “Electrical Characteristics” for additional information. C The placement of this capacitor should be close to the dsPIC33E/PIC24E VCAP pin. It is recommended that the trace length not exceeds one-quarter inch (6 mm). See Section27.3 VSS VDD “On-Chip Voltage Regulator” for details. VDD VSS C0e.r1a mµFic VDD VSS DD SS C0e.r1a µmFic 2.4 Master Clear (MCLR) Pin A A V V The MCLR pin provides two specific device functions: 0.1 µF 0.1 µF Ceramic Ceramic • Device Reset L1(1) • Device Programming and Debugging. During device programming and debugging, the Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and resistance and capacitance that can be added to the AVDD to improve ADC noise rejection. The inductor pin must be considered. Device programmers and impedance should be less than 1 and the inductor debuggers drive the MCLR pin. Consequently, capacity greater than 10 mA. specific voltage levels (VIH and VIL) and fast signal Where: transitions must not be adversely affected. Therefore, FCNV specific values of R and C will need to be adjusted f = -------------- (i.e., ADC conversion rate/2) 2 based on the application and PCB requirements. 1 For example, as shown in Figure2-2, it is recommended f = ----------------------- 2 LC that the capacitor, C, be isolated from the MCLR pin during programming and debugging operations.  1 2 L = ----------------------   Place the components as shown in Figure2-2 within 2f C one-quarter inch (6mm) from the MCLR pin. 2.2.1 TANK CAPACITORS FIGURE 2-2: EXAMPLE OF MCLR PIN On boards with power traces running longer than six CONNECTIONS inches in length, it is suggested to use a tank capacitor VDD for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that con- R(1) nects the power supply source to the device and the R1(2) MCLR maximum current drawn by the device in the applica- tion. In other words, select the tank capacitor so that it JP dsPIC33E/PIC24E meets the acceptable voltage sag at the device. Typical values range from 4.7µF to 47µF. C Note 1: R 10k is recommended. A suggested starting value is 10k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. DS70000657H-page 30  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for ICSP and Many DSCs have options for at least two oscillators: a debugging purposes. It is recommended to keep the high-frequency Primary Oscillator and a low-frequency trace length between the ICSP connector and the ICSP Secondary Oscillator. For details, see Section9.0 pins on the device as short as possible. If the ICSP con- “Oscillator Configuration” for details. nector is expected to experience an ESD event, a The oscillator circuit should be placed on the same series resistor is recommended, with the value in the side of the board as the device. Also, place the range of a few tens of Ohms, not to exceed 100 Ohms. oscillator circuit close to the respective oscillator pins, Pull-up resistors, series diodes, and capacitors on the not exceeding one-half inch (12mm) distance PGECx and PGEDx pins are not recommended as they between them. The load capacitors should be placed will interfere with the programmer/debugger communi- next to the oscillator itself, on the same side of the cations to the device. If such discrete components are board. Use a grounded copper pour around the an application requirement, they should be removed oscillator circuit to isolate them from surrounding from the circuit during programming and debugging. circuits. The grounded copper pour should be routed Alternatively, refer to the AC/DC characteristics and directly to the MCU ground. Do not run any signal timing requirements information in the respective traces or power traces inside the ground pour. Also, if device Flash programming specification for information using a two-sided board, avoid any traces on the on capacitive loading limits and pin Voltage Input High other side of the board where the crystal is placed. A (VIH) and Voltage Input Low (VIL) requirements. suggested layout is shown in Figure2-3. Ensure that the “Communication Channel Select” (i.e., FIGURE 2-3: SUGGESTED PLACEMENT PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to OF THE OSCILLATOR MPLAB® PICkit™ 3, MPLAB ICD 3, or MPLAB CIRCUIT REALICE™. For more information on MPLAB ICD 2, ICD 3 and Main Oscillator REAL ICE connection requirements, refer to the following documents that are available on the Guard Ring Microchip web site. • “Using MPLAB® ICD 3” (poster) DS51765 Guard Trace • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Oscillator Pins Guide” DS51616 • “Using MPLAB® REAL ICE™ In-Circuit Emulator” (poster) DS51749  2011-2013 Microchip Technology Inc. DS70000657H-page 31

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 2.7 Oscillator Value Conditions on 2.9 Application Examples Device Start-up • Induction heating If the PLL of the target device is enabled and • Uninterruptable Power Supplies (UPS) configured for the device start-up oscillator, the • DC/AC inverters maximum oscillator source frequency must be limited • Compressor motor control to 3 MHz < FIN < 5.5 MHz to comply with device PLL • Washing machine 3-phase motor control start-up conditions. This means that if the external • BLDC motor control oscillator frequency is outside this range, the • Automotive HVAC, cooling fans, fuel pumps application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator • Stepper motor control frequency outside this range will violate the device • Audio and fluid sensor monitoring operating speed. • Camera lens focus and stability control Once the device powers up, the application firmware • Speech (playback, hands-free kits, answering can initialize the PLL SFRs, CLKDIV and PLLFBD, to a machines, VoIP) suitable value, and then perform a clock switch to the • Consumer audio Oscillator + PLL clock source. Note that clock switching • Industrial and building control (security systems must be enabled in the device Configuration Word. and access control) • Barcode reading 2.8 Unused I/Os • Networking: LAN switches, gateways • Data storage device management Unused I/O pins should be configured as outputs and driven to a logic low state. • Smart cards and smart card readers Alternatively, connect a 1k to 10k resistor between VSS Examples of typical application connections are shown and unused pins, and drive the output to logic low. in Figure2-4 through Figure2-8. FIGURE 2-4: BOOST CONVERTER IMPLEMENTATION IPFC VINPUT VOUTPUT k1 k3 k FET 2 Driver ADC Channel Op Amp/ PWM ADC Channel Comparator Output dsPIC33EP DS70000657H-page 32  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 2-5: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I 5V k7 DFrEivTer k1 k2 ADC M M Op Amp/ ADC Channel W W Comparator Channel P P dsPIC33EP FIGURE 2-6: MULTIPHASE SYNCHRONOUS BUCK CONVERTER 12V Input 3.3V Output k 6 k FET FET 7 Driver Driver ChAaDnCnel WMWM WM WM PWM FET PP P P PWM Driver Op Amp/Comparator k3 dsPIC33EP Op Amp/Comparator k4 Op Amp/Comparator k5 ADC Channel  2011-2013 Microchip Technology Inc. DS70000657H-page 33

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 2-7: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k k 1 2 VOUT- FET FET Driver Driver Op Amp/Comparator PWM Op Amp/ PWM Op Amp/ ADC Comparator Comparator Channel dsPIC33EP ADC Channel FIGURE 2-8: BEMF VOLTAGE MEASURED USING THE ADC MODULE dsPIC33EP/PIC24EP BLDC PWM3H PWM3L PWM2H 3-Phase PWM2L Inverter PWM1H PWM1L R49 R41 R34 R36 FLTx Fault R44 AN2 R52 Demand AN3 AN4 AN5 Phase Terminal Voltage Feedback DS70000657H-page 34  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 3.0 CPU 3.3 Data Space Addressing Note1: This data sheet summarizes the The base Data Space can be addressed as 64 Kbytes features of the dsPIC33EPXXXGP50X, (32K words). dsPIC33EPXXXMC20X/50X and The Data Space includes two ranges of memory, PIC24EPXXXGP/MC20X families of referred to as X and Y data memory. Each memory devices. It is not intended to be a range is accessible through its own independent comprehensive reference source. To com- Address Generation Unit (AGU). The MCU class of plement the information in this data sheet, instructions operates solely through the X memory refer to “CPU” (DS70359) in the AGU, which accesses the entire memory map as one “dsPIC33/PIC24 Family Reference linear Data Space. On dsPIC33EPXXXMC20X/50X Manual”, which is available from the and dsPIC33EPXXXGP50X devices, certain DSP Microchip web site (www.microchip.com). instructions operate through the X and Y AGUs to 2: Some registers and associated bits support dual operand reads, which splits the data described in this section may not be address space into two parts. The X and Y Data Spaces available on all devices. Refer to have memory locations that are device-specific, and Section4.0 “Memory Organization” in are described further in the data memory maps in this data sheet for device-specific register Section4.2 “Data Address Space”. and bit information. The upper 32 Kbytes of the Data Space memory map The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ can optionally be mapped into Program Space (PS) at 50X and PIC24EPXXXGP/MC20X CPU has a 16-bit any 32-Kbyte aligned program word boundary. The (data) modified Harvard architecture with an enhanced Program-to-Data Space mapping feature, known as instruction set, including significant support for digital Program Space Visibility (PSV), lets any instruction signal processing. The CPU has a 24-bit instruction access Program Space as if it were Data Space. word with a variable length opcode field. The Program Moreover, the Base Data Space address is used in Counter (PC) is 23 bits wide and addresses up to conjunction with a Read or Write Page register (DSRPAG 4Mx24 bits of user program memory space. or DSWPAG) to form an Extended Data Space (EDS) An instruction prefetch mechanism helps maintain address. The EDS can be addressed as 8M words or throughput and provides predictable execution. Most 16Mbytes. Refer to the “Data Memory” (DS70595) and instructions execute in a single-cycle effective execu- “Program Memory” (DS70613) sections in the tion rate, with the exception of instructions that change “dsPIC33/PIC24 Family Reference Manual” for more the program flow, the double-word move (MOV.D) details on EDS, PSV and table accesses. instruction, PSV accesses and the table instructions. On the dsPIC33EPXXXMC20X/50X and Overhead-free program loop constructs are supported dsPIC33EPXXXGP50X devices, overhead-free circular using the DO and REPEAT instructions, both of which buffers (Modulo Addressing) are supported in both X are interruptible at any point. and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for 3.1 Registers DSP algorithms. The X AGU Circular Addressing can be used with any of the MCU class of instructions. The X The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ AGU also supports Bit-Reversed Addressing to greatly 50X and PIC24EPXXXGP/MC20X devices have six- simplify input or output data re-ordering for radix-2 FFT teen, 16-bit working registers in the programmer’s algorithms. PIC24EPXXXGP/MC20X devices do not model. Each of the working registers can act as a data, support Modulo and Bit-Reversed Addressing. address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for 3.4 Addressing Modes interrupts and calls. The CPU supports these addressing modes: 3.2 Instruction Set • Inherent (no operand) The instruction set for dsPIC33EPXXXGP50X and • Relative dsPIC33EPXXXMC20X/50X devices has two classes of • Literal instructions: the MCU class of instructions and the DSP class of instructions. The instruction set for • Memory Direct PIC24EPXXXGP/MC20X devices has the MCU class of • Register Direct instructions only and does not support DSP instructions. • Register Indirect These two instruction classes are seamlessly integrated Each instruction is associated with a predefined into the architecture and execute from a single execution addressing mode group, depending upon its functional unit. The instruction set includes many addressing modes requirements. As many as six addressing modes are and was designed for optimum Ccompiler efficiency. supported for each instruction.  2011-2013 Microchip Technology Inc. DS70000657H-page 35

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 3-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X CPU BLOCK DIAGRAM X Address Bus Y Data Bus(1) X Data Bus 16 16 16 16 Interrupt PSV and Table Data Latch Data Latch Controller Data Access 8 16 Y Data X Data 24 Control Block RAM(1) RAM Address Address 16 24 24 Latch Latch s 16 16 u 24 PPCrUograPmC CHounPteCrL ess B 16 XX WRAAGGUU Stack Loop ddr Control Control A Address Latch Logic Logic Y Y AGU(1) Program Memory 16 EA MUX Data Latch 16 ch 16 24 at 24 M L IR O a R at D al er 16 Lit 16 x 16 W Register Array 16 16 16 Divide DSP Support Engine(1) 16-Bit ALU Control Signals DInesctorudcet iaonnd 16 16 to Various Blocks Control Power, Reset Ports and Oscillator Modules Peripheral Modules Note 1: This feature is not available on PIC24EPXXXGP/MC20X devices. DS70000657H-page 36  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 3.5 Programmer’s Model MC20X devices contain control registers for Modulo Addressing (dsPIC33EPXXXMC20X/50X and The programmer’s model for the dsPIC33EPXXXGP50X devices only), Bit-Reversed dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X Addressing (dsPIC33EPXXXMC20X/50X and and PIC24EPXXXGP/MC20X is shown in Figure3-2. dsPIC33EPXXXGP50X devices only) and interrupts. All registers in the programmer’s model are memory These registers are described in subsequent mapped and can be manipulated directly by sections of this document. instructions. Table3-1 lists a description of each All registers associated with the programmer’s model register. are memory mapped, as shown in Table4-1. In addition to the registers contained in the programmer’s model, the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS Register(s) Name Description W0 through W15 Working Register Array ACCA, ACCB 40-Bit DSP Accumulators PC 23-Bit Program Counter SR ALU and DSP Engine STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register DSRPAG Extended Data Space (EDS) Read Page Register DSWPAG Extended Data Space (EDS) Write Page Register RCOUNT REPEAT Loop Count Register DCOUNT(1) DO Loop Count Register DOSTARTH(1,2), DOSTARTL(1,2) DO Loop Start Address Register (High and Low) DOENDH(1), DOENDL(1) DO Loop End Address Register (High and Low) CORCON Contains DSP Engine, DO Loop Control and Trap Status bits Note 1: This register is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. 2: The DOSTARTH and DOSTARTL registers are read-only.  2011-2013 Microchip Technology Inc. DS70000657H-page 37

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 3-2: PROGRAMMER’S MODEL D15 D0 W0 (WREG) W1 W2 W3 W4 DSP Operand W5 Registers W6 W7 Working/Address Registers W8 W9 DSP Address Registers W10 W11 W12 W13 Frame Pointer/W14 PUSH.s and POP.s Shadows Stack Pointer/W15 0 Nested DO Stack SPLIM 0 Stack Pointer Limit AD39 AD31 AD15 AD0 DSP ACCA Accumulators(1) ACCB PC23 PC0 0 0 Program Counter 7 0 TBLPAG Data Table Page Address 9 0 DSRPAG X Data Space Read Page Address 8 0 DSWPAG X Data Space Write Page Address 15 0 RCOUNT Repeat Loop Counter 15 0 DCOUNT DO Loop Counter and Stack(1) 23 0 0 DOSTART 0 DO Loop Start Address and Stack(1) 23 0 0 DOEND 0 DO Loop End Address and Stack(1) 15 0 CORCON CPU Core Control Register SRL OA(1) OB(1) SA(1)SB(1) OAB(1)SAB(1)DA(1) DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register Note 1: This feature or bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. DS70000657H-page 38  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 3.6 CPU Resources 3.6.1 KEY RESOURCES Many useful resources are provided on the main prod- • “CPU” (DS70359) in the “dsPIC33/PIC24 Family uct page of the Microchip web site for the devices listed Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2013 Microchip Technology Inc. DS70000657H-page 39

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 3.7 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0 OA(1) OB(1) SA(1,4) SB(1,4) OAB(1) SAB(1) DA(1) DC bit 15 bit 8 R/W-0(2,3) R/W-0(2,3) R/W-0(2,3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2 IPL1 IPL0 RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit(1) 1 = Accumulator A has overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit(1) 1 = Accumulator B has overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1,4) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1,4) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit(1) 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1) 1 = Accumulators A or B are saturated or have been saturated at some time 0 = Neither Accumulators A or B are saturated bit 9 DA: DO Loop Active bit(1) 1 = DO loop is in progress 0 = DO loop is not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when IPL<3>= 1. 3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1. 4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations. DS70000657H-page 40  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when IPL<3>= 1. 3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1. 4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations.  2011-2013 Microchip Technology Inc. DS70000657H-page 41

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 3-2: CORCON: CORE CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 VAR — US1(1) US0(1) EDT(1,2) DL2(1) DL1(1) DL0(1) bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0 SATA(1) SATB(1) SATDW(1) ACCSAT(1) IPL3(3) SFA RND(1) IF(1) bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 VAR: Variable Exception Processing Latency Control bit 1 = Variable exception processing latency is enabled 0 = Fixed exception processing latency is enabled bit 14 Unimplemented: Read as ‘0’ bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits(1) 11 = Reserved 10 = DSP engine multiplies are mixed-sign 01 = DSP engine multiplies are unsigned 00 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit(1,2) 1 = Terminates executing DO loop at end of current loop iteration 0 = No effect bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits(1) 111 = 7 DO loops are active • • • 001 = 1 DO loop is active 000 = 0 DO loops are active bit 7 SATA: ACCA Saturation Enable bit(1) 1 = Accumulator A saturation is enabled 0 = Accumulator A saturation is disabled bit 6 SATB: ACCB Saturation Enable bit(1) 1 = Accumulator B saturation is enabled 0 = Accumulator B saturation is disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit(1) 1 = Data Space write saturation is enabled 0 = Data Space write saturation is disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit(1) 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(3) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. 2: This bit is always read as ‘0’. 3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70000657H-page 42  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED) bit 2 SFA: Stack Frame Active Status bit 1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and DSWPAG values 0 = Stack frame is not active; W14 and W15 address of EDS or Base Data Space bit 1 RND: Rounding Mode Select bit(1) 1 = Biased (conventional) rounding is enabled 0 = Unbiased (convergent) rounding is enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit(1) 1 = Integer mode is enabled for DSP multiply 0 = Fractional mode is enabled for DSP multiply Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. 2: This bit is always read as ‘0’. 3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.  2011-2013 Microchip Technology Inc. DS70000657H-page 43

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 3.8 Arithmetic Logic Unit (ALU) 3.9 DSP Engine (dsPIC33EPXXXMC20X/50X and The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X ALU is 16 bits wide, dsPIC33EPXXXGP50X Devices and is capable of addition, subtraction, bit shifts and Only) logic operations. Unless otherwise mentioned, The DSP engine consists of a high-speed 17-bit x arithmetic operations are two’s complement in nature. 17-bit multiplier, a 40-bit barrel shifter and a 40-bit Depending on the operation, the ALU can affect the adder/subtracter (with two target accumulators, round values of the Carry (C), Zero (Z), Negative (N), and saturation logic). Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as The DSP engine can also perform inherent accumulator- Borrow and Digit Borrow bits, respectively, for to-accumulator operations that require no additional subtraction operations. data. These instructions are ADD, SUB and NEG. The ALU can perform 8-bit or 16-bit operations, The DSP engine has options selected through bits in depending on the mode of the instruction that is used. the CPU Core Control register (CORCON), as listed Data for the ALU operation can come from the W below: register array or data memory, depending on the • Fractional or integer DSP multiply (IF) addressing mode of the instruction. Likewise, output • Signed, unsigned or mixed-sign DSP multiply (US) data from the ALU can be written to the W register array • Conventional or convergent rounding (RND) or a data memory location. • Automatic saturation on/off for ACCA (SATA) Refer to the “16-bit MCU and DSC Programmer’s • Automatic saturation on/off for ACCB (SATB) Reference Manual” (DS70157) for information on the SR bits affected by each instruction. • Automatic saturation on/off for writes to data memory (SATDW) The core CPU incorporates hardware support for both • Accumulator Saturation mode selection multiplication and division. This includes a dedicated (ACCSAT) hardware multiplier and support hardware for 16-bit divisor division. TABLE 3-2: DSP INSTRUCTIONS 3.8.1 MULTIPLIER SUMMARY Using the high-speed 17-bit x 17-bit multiplier, the ALU Algebraic ACC Write Instruction supports unsigned, signed, or mixed-sign operation in Operation Back several MCU multiplication modes: CLR A = 0 Yes • 16-bit x 16-bit signed ED A = (x – y)2 No • 16-bit x 16-bit unsigned • 16-bit signed x 5-bit (literal) unsigned EDAC A = A + (x – y)2 No • 16-bit signed x 16-bit unsigned MAC A = A + (x•y) Yes • 16-bit unsigned x 5-bit (literal) unsigned MAC A = A + x2 No • 16-bit unsigned x 16-bit signed • 8-bit unsigned x 8-bit unsigned MOVSAC No change in A Yes MPY A = x•y No 3.8.2 DIVIDER MPY A = x2 No The divide block supports 32-bit/16-bit and 16-bit/16-bit MPY.N A = – x•y No signed and unsigned integer divide operations with the MSC A = A – x•y Yes following data sizes: • 32-bit signed/16-bit signed divide • 32-bit unsigned/16-bit unsigned divide • 16-bit signed/16-bit signed divide • 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. DS70000657H-page 44  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.0 MEMORY ORGANIZATION 4.1 Program Address Space Note: This data sheet summarizes the The program address memory space of the features of the dsPIC33EPXXXGP50X, dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X dsPIC33EPXXXMC20X/50X and and PIC24EPXXXGP/MC20X devices is 4M PIC24EPXXXGP/MC20X families of instructions. The space is addressable by a 24-bit devices. It is not intended to be a value derived either from the 23-bit PC during program comprehensive reference source. To com- execution, or from table operation or Data Space plement the information in this data sheet, remapping, as described in Section4.8 “Interfacing refer to “Program Memory” (DS70613) in Program and Data Memory Spaces”. the “dsPIC33/PIC24 Family Reference User application access to the program memory space Manual”, which is available from the is restricted to the lower half of the address range Microchip web site (www.microchip.com). (0x000000 to 0x7FFFFF). The exception is the use of TBLRD operations, which use TBLPAG<7> to read The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ Device ID sections of the configuration memory space. 50X and PIC24EPXXXGP/MC20X architecture features separate program and data memory spaces, The program memory maps, which are presented by and buses. This architecture also allows the direct device family and memory size, are shown in access of program memory from the Data Space (DS) Figure4-1 through Figure4-5. during code execution. FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X AND PIC24EP32GP/MC20X DEVICES GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 Interrupt Vector Table 0x0001FE 0x000200 User Program ce Flash Memory Spa (11K instructions) 0x0057EA ory Flash Configuration 0x0057EC m Bytes e 0x0057FE M 0x005800 er s U Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID ce 0x800FFE pa 0x801000 y S Reserved or 0xF9FFFE m 0xFA0000 e Write Latches M 0xFA0002 n 0xFA0004 o ati ur nfig Reserved o C 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale.  2011-2013 Microchip Technology Inc. DS70000657H-page 45

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X AND PIC24EP64GP/MC20X DEVICES GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 Interrupt Vector Table 0x0001FE 0x000200 User Program ce Flash Memory Spa (22K instructions) 0x00AFEA y 0x00AFEC or Flash Configuration m Bytes e 0x00AFFE M 0x00B000 er s U Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID ce 0x800FFE pa 0x801000 y S Reserved or 0xF9FFFE m 0xFA0000 e Write Latches M 0xFA0002 n 0xFA0004 o ati ur g Reserved nfi o C 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale. DS70000657H-page 46  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-3: PROGRAM MEMORY MAP FOR dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X AND PIC24EP128GP/MC20X DEVICES GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 Interrupt Vector Table 0x0001FE 0x000200 User Program ce Flash Memory Spa (44K instructions) 0x0157EA y 0x0157EC or Flash Configuration m Bytes e 0x0157FE M 0x015800 er s U Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID ce 0x800FFE pa 0x801000 y S Reserved or 0xF9FFFE m 0xFA0000 e Write Latches M 0xFA0002 n 0xFA0004 o ati ur nfig Reserved o C 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale.  2011-2013 Microchip Technology Inc. DS70000657H-page 47

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-4: PROGRAM MEMORY MAP FOR dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X AND PIC24EP256GP/MC20X DEVICES GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 Interrupt Vector Table 0x0001FE 0x000200 User Program ce Flash Memory Spa (88K instructions) 0x02AFEA y 0x02AFEC or Flash Configuration m Bytes e 0x02AFFE M 0x02B000 er s U Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID ce 0x800FFE pa 0x801000 y S Reserved or 0xF9FFFE m 0xFA0000 e Write Latches M 0xFA0002 n 0xFA0004 o ati ur nfig Reserved o C 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale. DS70000657H-page 48  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-5: PROGRAM MEMORY MAP FOR dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X AND PIC24EP512GP/MC20X DEVICES GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 Interrupt Vector Table 0x0001FE 0x000200 User Program ce Flash Memory Spa (175K instructions) 0x0557EA ory Flash Configuration 0x0557EC m Bytes e 0x0557FE M 0x055800 er s U Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID ce 0x800FFE pa 0x801000 S Reserved y or 0xF9FFFE m 0xFA0000 e Write Latches M 0xFA0002 n 0xFA0004 o ati ur g Reserved nfi o C 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale.  2011-2013 Microchip Technology Inc. DS70000657H-page 49

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS ORGANIZATION All dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ The program memory space is organized in word- 50X and PIC24EPXXXGP/MC20X devices reserve the addressable blocks. Although it is treated as 24 bits addresses between 0x000000 and 0x000200 for hard- wide, it is more appropriate to think of each address of coded program execution vectors. A hardware Reset the program memory as a lower and upper word, with vector is provided to redirect code execution from the the upper byte of the upper word being unimplemented. default value of the PC on device Reset to the actual The lower word always has an even address, while the start of code. A GOTO instruction is programmed by the upper word has an odd address (Figure4-6). user application at address, 0x000000, of Flash memory, with the actual address for the start of code at Program memory addresses are always word-aligned address, 0x000002, of Flash memory. on the lower word and addresses are incremented, or decremented by two, during code execution. This A more detailed discussion of the Interrupt Vector arrangement provides compatibility with data memory Tables (IVTs) is provided in Section7.1 “Interrupt space addressing and makes data in the program Vector Table”. memory space accessible. FIGURE 4-6: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS70000657H-page 50  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ care must be taken when mixing byte and word 50X and PIC24EPXXXGP/MC20X CPU has a separate operations, or translating from 8-bit MCU code. If a 16-bit-wide data memory space. The Data Space is misaligned read or write is attempted, an address error accessed using separate Address Generation Units trap is generated. If the error occurred on a read, the (AGUs) for read and write operations. The data instruction underway is completed. If the error occurred memory maps, which are presented by device family on a write, the instruction is executed but the write does and memory size, are shown in Figure4-7 through not occur. In either case, a trap is then executed, Figure4-16. allowing the system and/or user application to examine All Effective Addresses (EAs) in the data memory space the machine state prior to execution of the address are 16 bits wide and point to bytes within the Data Fault. Space. This arrangement gives a base Data Space All byte loads into any W register are loaded into the address range of 64 Kbytes (32K words). LSB. The MSB is not modified. The base Data Space address is used in conjunction A Sign-Extend (SE) instruction is provided to allow user with a Read or Write Page register (DSRPAG or applications to translate 8-bit signed data to 16-bit DSWPAG) to form an Extended Data Space, which has signed values. Alternatively, for 16-bit unsigned data, a total address range of 16 Mbytes. user applications can clear the MSB of any W register dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X by executing a Zero-Extend (ZE) instruction on the and PIC24EPXXXGP/MC20X devices implement up to appropriate address. 52Kbytes of data memory (4 Kbytes of data memory 4.2.3 SFR SPACE for Special Function Registers and up to 48 Kbytes of data memory for RAM). If an EA points to a location The first 4 Kbytes of the Near Data Space, from 0x0000 outside of this area, an all-zero word or byte is returned. to 0x0FFF, is primarily occupied by Special Function Registers (SFRs). These are used by the 4.2.1 DATA SPACE WIDTH dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X The data memory space is organized in byte- and PIC24EPXXXGP/MC20X core and peripheral addressable, 16-bit-wide blocks. Data is aligned in data modules for controlling the operation of the device. memory and registers as 16-bit words, but all Data SFRs are distributed among the modules that they Space EAs resolve to bytes. The Least Significant control and are generally grouped together by module. Bytes (LSBs) of each word have even addresses, while Much of the SFR space contains unused addresses; the Most Significant Bytes (MSBs) have odd these are read as ‘0’. addresses. Note: The actual set of peripheral features and 4.2.2 DATA MEMORY ORGANIZATION interrupts varies by the device. Refer to AND ALIGNMENT the corresponding device tables and pinout diagrams for device-specific To maintain backward compatibility with PIC® MCU information. devices and improve Data Space memory usage efficiency, the dsPIC33EPXXXGP50X, 4.2.4 NEAR DATA SPACE dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X instruction set supports both word and byte The 8-Kbyte area, between 0x0000 and 0x1FFF, is operations. As a consequence of byte accessibility, all referred to as the Near Data Space. Locations in this Effective Address calculations are internally scaled to space are directly addressable through a 13-bit abso- step through word-aligned memory. For example, the lute address field within all memory direct instructions. core recognizes that Post-Modified Register Indirect Additionally, the whole Data Space is addressable Addressing mode [Ws++] results in a value of Ws + 1 using MOV instructions, which support Memory Direct for byte operations and Ws + 2 for word operations. Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working A data byte read, reads the complete word that register as an Address Pointer. contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.  2011-2013 Microchip Technology Inc. DS70000657H-page 51

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-7: DATA MEMORY MAP FOR dsPIC33EP32MC20X/50X AND dsPIC33EP32GP50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 0x1001 0x1000 X Data RAM (X) 8-Kbyte Near 4-Kbyte 0x17FF 0x17FE Data Space SRAM Space 0x1801 0x1800 Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale. DS70000657H-page 52  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-8: DATA MEMORY MAP FOR dsPIC33EP64MC20X/50X AND dsPIC33EP64GP50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 0x1001 0x1000 8-Kbyte Near Data Space X Data RAM (X) 8-Kbyte 0x1FFF 0x1FFE SRAM Space 0x2001 0x2000 Y Data RAM (Y) 0x2FFF 0x2FFE 0x3001 0x3000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2013 Microchip Technology Inc. DS70000657H-page 53

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-9: DATA MEMORY MAP FOR dsPIC33EP128MC20X/50X AND dsPIC33EP128GP50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 8-Kbyte 0x1001 0x1000 Near Data Space 0x1FFF 0x1FFE X Data RAM (X) 0x2001 0x2000 16-Kbyte 0x2FFF 0x2FFE SRAM Space 0x3001 0x3000 Y Data RAM (Y) 0x4FFF 0x4FFE 0x5001 0x5000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale. DS70000657H-page 54  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-10: DATA MEMORY MAP FOR dsPIC33EP256MC20X/50X AND dsPIC33EP256GP50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 8-Kbyte 0x1001 0x1000 Near Data Space 0x1FFF 0x1FFE X Data RAM (X) 0x2001 0x2000 32-Kbyte 0x4FFF 0x4FFE SRAM Space 0x5001 0x5000 0x7FFF 0x7FFE Y Data RAM (Y) 0x8001 0x8000 0x8FFF 0x8FFE 0x9001 0x9000 Optionally Mapped into Program Memory Space X Data (PSV) Unimplemented (X) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2013 Microchip Technology Inc. DS70000657H-page 55

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-11: DATA MEMORY MAP FOR dsPIC33EP512MC20X/50X AND dsPIC33EP512GP50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 8-Kbyte 0x1001 0x1000 Near Data Space 0x1FFF 0x1FFE 0x2001 0x2000 X Data RAM (X) 48-Kbyte 0x7FFF 0x7FFE SRAM Space 0x8001 0x8000 0x8FFF 0x8FFE 0x9001 0x9000 Y Data RAM (Y) 0xEFFF 0xEFFE 0xD001 0xD000 Optionally Mapped into Program Memory Space (PSV) X Data Unimplemented (X) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale. DS70000657H-page 56  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-12: DATA MEMORY MAP FOR PIC24EP32GP/MC20X/50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 0x1001 0x1000 8-Kbyte Near 4-Kbyte X Data RAM (X) Data Space SRAM Space 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2013 Microchip Technology Inc. DS70000657H-page 57

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-13: DATA MEMORY MAP FOR PIC24EP64GP/MC20X/50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 0x1001 0x1000 8-Kbyte Near Data Space X Data RAM (X) 8-Kbyte 0x1FFF 0x1FFE SRAM Space 0x2001 0x2000 0x2FFF 0x2FFE 0x3001 0x3000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale. DS70000657H-page 58  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-14: DATA MEMORY MAP FOR PIC24EP128GP/MC20X/50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 8-Kbyte 0x1001 0x1000 Near Data Space 0x1FFF 0x1FFE X Data RAM (X) 0x2001 0x2000 16-Kbyte SRAM Space 0x4FFF 0x4FFE 0x5001 0x5000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2013 Microchip Technology Inc. DS70000657H-page 59

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-15: DATA MEMORY MAP FOR PIC24EP256GP/MC20X/50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 8-Kbyte 0x1001 0x1000 Near Data Space 0x1FFF 0x1FFE X Data RAM (X) 0x2001 0x2000 32-Kbyte SRAM Space 0x7FFF 0x7FFE 0x8001 0x8000 0x8FFF 0x8FFE 0x9001 0x9000 Optionally Mapped into Program Memory Space (PSV) X Data Unimplemented (X) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale. DS70000657H-page 60  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-16: DATA MEMORY MAP FOR PIC24EP512GP/MC20X/50X DEVICES MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE 8-Kbyte 0x1001 0x1000 Near Data Space 0x1FFF 0x1FFE X Data RAM (X) 0x2001 0x2000 48-Kbyte SRAM Space 0x7FFF 0x7FFE 0x8001 0x8000 0xEFFF 0xEFFE 0xD001 0xD000 Optionally Mapped into Program Memory Space (PSV) X Data Unimplemented (X) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2013 Microchip Technology Inc. DS70000657H-page 61

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.2.5 X AND Y DATA SPACES 4.3 Memory Resources The dsPIC33EPXXXMC20X/50X and Many useful resources are provided on the main prod- dsPIC33EPXXXGP50X core has two Data Spaces, uct page of the Microchip web site for the devices listed X and Y. These Data Spaces can beconsidered either in this data sheet. This product page, which can be separate (for some DSP instructions) or as one unified accessed using this link, contains the latest updates linear address range (for MCU instructions). The Data and additional information. Spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature Note: In the event you are not able to access the allows certain instructions to concurrently fetch two product page using the link above, enter words from RAM, thereby enabling efficient execution this URL in your browser: of DSP algorithms, such as Finite Impulse Response http://www.microchip.com/wwwproducts/ (FIR) filtering and Fast Fourier Transform (FFT). Devices.aspx?dDocName=en555464 The X Data Space is used by all instructions and 4.3.1 KEY RESOURCES supports all addressing modes. X Data Space has separate read and write data buses. The X read data • “Program Memory” (DS70613) in the “dsPIC33/ bus is the read data path for all instructions that view PIC24 Family Reference Manual” Data Space as combined X and Y address space. It is • Code Samples also the X data prefetch path for the dual operand DSP • Application Notes instructions (MAC class). • Software Libraries The Y Data Space is used in concert with the X Data • Webinars Space by the MAC class of instructions (CLR, ED, • All Related “dsPIC33/PIC24 Family Reference EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide Manual” Sections two concurrent data read paths. • Development Tools Both the X and Y Data Spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X Data Space. Modulo Addressing and Bit-Reversed Addressing are not present in PIC24EPXXXGP/MC20X devices. All data memory writes, including in DSP instructions, view Data Space as combined X and Y address space. The boundary between the X and Y Data Spaces is device-dependent and is not user-programmable. DS70000657H-page 62  2011-2013 Microchip Technology Inc.

 4.4 Special Function Register Maps 2 0 11-20 TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY dsP 13 M File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC3 icro W0 0000 W0 (WREG) xxxx 3E c h W1 0002 W1 xxxx P ip X Te W2 0004 W2 xxxx X ch W3 0006 W3 xxxx X n G o W4 0008 W4 xxxx lo P gy W5 000A W5 xxxx 5 Inc W6 000C W6 xxxx 0X . W7 000E W7 xxxx , d W8 0010 W8 xxxx s P W9 0012 W9 xxxx I C W10 0014 W10 xxxx 3 W11 0016 W11 xxxx 3 E W12 0018 W12 xxxx P W13 001A W13 xxxx X X W14 001C W14 xxxx X W15 001E W15 xxxx M C SPLIM 0020 SPLIM 0000 2 ACCAL 0022 ACCAL 0000 0 X ACCAH 0024 ACCAH 0000 / 5 ACCAU 0026 Sign Extension of ACCA<39> ACCAU 0000 0 X ACCBL 0028 ACCBL 0000 A ACCBH 002A ACCBH 0000 N ACCBU 002C Sign Extension of ACCB<39> ACCBU 0000 D PCL 002E PCL<15:0> — 0000 P I PCH 0030 — — — — — — — — — PCH<6:0> 0000 C 2 DSRPAG 0032 — — — — — — DSRPAG<9:0> 0001 4 E DSWPAG 0034 — — — — — — — DSWPAG<8:0> 0001 P D RCOUNT 0036 RCOUNT<15:0> 0000 X S X 70 DCOUNT 0038 DCOUNT<15:0> 0000 X 0 0 DOSTARTL 003A DOSTARTL<15:1> — 0000 G 0 65 DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 0000 P 7H DOENDL 003E DOENDL<15:1> — 0000 /M -p C ag DOENDH 0040 — — — — — — — — — — DOENDH<5:0> 0000 2 e 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0X 3

D TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED) d S s 70 All P 00 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 0 6 3 57 SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 3 H-p CORCON 0044 VAR — US<1:0> EDT DL<2:0> SATA SATB SATDW ACCSAT IPL3 SFA RND IF 0020 EP ag MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 X e 6 XMODSRT 0048 XMODSRT<15:0> — 0000 X 4 X XMODEND 004A XMODEND<15:0> — 0001 G YMODSRT 004C YMODSRT<15:0> — 0000 P 5 YMODEND 004E YMODEND<15:0> — 0001 0 X XBREV 0050 BREN XBREV<14:0> 0000 , DISICNT 0052 — — DISICNT<13:0> 0000 d s TBLPAG 0054 — — — — — — — — TBLPAG<7:0> 0000 P I MSTRPR 0058 MSTRPR<15:0> 0000 C 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 E P X X X M C 2 0 X / 5 0 X A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-2: CPU CORE REGISTER MAP FOR PIC24EPXXXGP/MC20X DEVICES ONLY 2 0 1 File All d 1-20 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets sP 13 W0 0000 W0 (WREG) xxxx IC Mic W1 0002 W1 xxxx 33 roc W2 0004 W2 xxxx E h P ip W3 0006 W3 xxxx X Te W4 0008 W4 xxxx X chn W5 000A W5 xxxx XG o lo W6 000C W6 xxxx P g y In W7 000E W7 xxxx 50 c. W8 0010 W8 xxxx X, W9 0012 W9 xxxx d s W10 0014 W10 xxxx P W11 0016 W11 xxxx IC W12 0018 W12 xxxx 3 3 W13 001A W13 xxxx E P W14 001C W14 xxxx X W15 001E W15 xxxx X X SPLIM 0020 SPLIM<15:0> 0000 M PCL 002E PCL<15:1> — 0000 C PCH 0030 — — — — — — — — — PCH<6:0> 0000 2 0 DSRPAG 0032 — — — — — — DSRPAG<9:0> 0001 X / DSWPAG 0034 — — — — — — — DSWPAG<8:0> 0001 5 0 RCOUNT 0036 RCOUNT<15:0> 0000 X SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000 A N CORCON 0044 VAR — — — — — — — — — — — IPL3 SFA — — 0020 D DISICNT 0052 — — DISICNT<13:0> 0000 P TBLPAG 0054 — — — — — — — — TBLPAG<7:0> 0000 I C MSTRPR 0058 MSTRPR<15:0> 0000 2 4 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 6 0X 5

D TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY d S s 7000 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts PIC 0 6 3 57 IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 3 H E -p IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 P a g IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF — — SPI2IF SPI2EIF 0000 X e 66 IFS3 0806 — — — — — — — — — — — — — MI2C2IF SI2C2IF — 0000 XX IFS4 0808 — — CTMUIF — — — — — — — — — CRCIF U2EIF U1EIF — 0000 G P IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000 5 IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000 0 X IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 , d IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 s IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE — — SPI2IE SPI2EIE 0000 P I IEC3 0826 — — — — — — — — — — — — — MI2C2IE SI2C2IE — 0000 C 3 IEC4 0828 — — CTMUIE — — — — — — — — — CRCIE U2EIE U1EIE — 0000 3 E IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000 P IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000 X X IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 X IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 M IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 C 2 IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444 0 X IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 / 5 IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004 0 X IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 A IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 N IPC8 0850 — — — — — — — — — SPI2IP<2:0> — SPI2EIP<2:0> 0044 D IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444 P  IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440 IC 201 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 24 1-2 IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040 E 0 P 13 IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400 X M IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440 X ic X ro IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444 G c hip INTCON1 08C0 NSTDIS OVAERR OVBERR — — — — — — DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 P T INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000 /M e ch INTCON3 08C4 — — — — — — — — — — DAE DOOVR — — — — 0000 C n 2 olo INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 0 g X y INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000 Inc Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. .

 TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY 2 0 1 File All d 1-20 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets sP 13 IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 IC Mic IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 33 roc IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF — — SPI2IF SPI2EIF 0000 E h P ip IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF — 0000 X Te IFS4 0808 — — CTMUIF — — — — — — — — — CRCIF U2EIF U1EIF — 0000 X chn IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000 XG o lo IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000 P g y In IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000 50 c. IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000 X, IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 d s IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 P IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE — — SPI2IE SPI2EIE 0000 IC IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — — MI2C2IE SI2C2IE — 0000 3 3 IEC4 0828 — — CTMUIE — — — — — — — — — CRCIE U2EIE U1EIE — 0000 E P IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000 X IEC6 082C — — — — — — — — — — — — — — — PWM3IE 0000 X X IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000 M IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000 C IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 2 0 IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 X / IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 5 0 IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444 X IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 A N IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004 D IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 P IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 I C IPC8 0850 — — — — — — — — — SPI2IP<2:0> — SPI2EIP<2:0> 0044 2 4 IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444 E IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440 P D X S IPC14 085C — — — — — QEI1IP<2:0> — PSEMIP<2:0> — — — — 0440 X 7 00 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 X 0 G 06 IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040 P 5 7H IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400 /M -p IPC24 0870 — — — — — — — — — — — — — PWM3IP<2:0> 4004 C a ge 6 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 20X 7

D TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY (CONTINUED) d S s 70 File All P 00 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 0 6 3 57 IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400 3 H-p IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440 EP ag IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444 X e 6 INTCON1 08C0 NSTDIS OVAERR OVBERR — — — — — — DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 X 8 X INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000 G INTCON3 08C4 — — — — — — — — — — DAE DOOVR — — — — 0000 P 5 INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 0 X INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000 , Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I C 3 3 E P X X X M C 2 0 X / 5 0 X A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY 2 0 11-20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts dsP 1 I 3 IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 C M 3 ic IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 3 roc IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 E h P ip IFS3 0806 — — — — — — — — — — — — — MI2C2IF SI2C2IF — 0000 X Te IFS4 0808 — — CTMUIF — — — — — — C1TXIF — — CRCIF U2EIF U1EIF — 0000 X ch X n IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000 G o lo IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000 P g y 5 In IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000 0 c. IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 X, IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 d s IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 P IEC3 0826 — — — — — — — — — — — — — MI2C2IE SI2C2IE — 0000 IC IEC4 0828 — — CTMUIE — — — — — — C1TXIE — — CRCIE U2EIE U1EIE — 0000 3 3 IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000 E P IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000 X IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 X X IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 M IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 C IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444 2 0 IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 X / IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004 5 0 IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 X IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 A N IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 D IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444 P IPC11 0856 — — — — — — — — — — — — — — — — 0000 IC IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440 2 4 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 E IPC17 0862 — — — — — C1TXIP<2:0> — — — — — — — — 0400 P D X S IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040 X 7 00 IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400 X 0 G 06 IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440 P 5 7H IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444 /M -p Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. C a g 2 e 6 0X 9

D TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED) d S s 70000 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts PIC 6 3 57 INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 3 H E -p INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000 P a ge 70 IINNTTCCOONN34 0088CC46 —— —— —— —— —— —— —— —— —— —— D—AE DO—OVR —— —— —— SG—HT 00000000 XXX INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000 G P Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 5 0 X , d s P I C 3 3 E P X X X M C 2 0 X / 5 0 X A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY 2 0 11-20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts dsP 1 I 3 IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 C M 3 ic IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 3 roc IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF — — SPI2IF SPI2EIF 0000 E h P ip IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF — 0000 X Te IFS4 0808 — — CTMUIF — — — — — — — — — CRCIF U2EIF U1EIF — 0000 X ch X n IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000 G o lo IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000 P g y 5 In IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000 0 c. IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000 X, IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 d s IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 P IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE — — SPI2IE SPI2EIE 0000 IC IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — — MI2C2IE SI2C2IE — 0000 3 3 IEC4 0828 — — CTMUIE — — — — — — — — — CRCIE U2EIE U1EIE — 0000 E P IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000 X IEC6 082C — — — — — — — — — — — — — — — PWM3IE 0000 X X IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000 M IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000 C IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 2 0 IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 X / IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 5 0 IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444 X IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 A N IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004 D IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 P IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 IC IPC8 0850 — — — — — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 0444 2 4 IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444 E IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440 P D X S IPC14 085C — — — — — QEI1IP<2:0> — PSEMIP<2:0> — — — — 0440 X 7 00 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 X 0 G 06 IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040 P 5 7H IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400 /M -p IPC24 0870 — — — — — — — — — — — — — PWM3IP<2:0> 0004 C a ge 7 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 20X 1

D TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY (CONTINUED) d S s 70 File All P 00 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 0 6 3 57 IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400 3 H E -p IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440 P a g IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444 X e 7 INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 X 2 X INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000 G INTCON3 08C4 — — — — — — — — — — DAE DOOVR — — — — 0000 P 5 INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 0 X INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000 , Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I C 3 3 E P X X X M C 2 0 X / 5 0 X A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY 2 0 1 File All d 1-20 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets sP 13 IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 IC Mic IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 33 roc IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 E h P ip IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF — 0000 X Te IFS4 0808 — — CTMUIF — — — — — — C1TXIF — — CRCIF U2EIF U1EIF — 0000 X chn IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000 XG o lo IFS6 080C — — — — — — — — — — — — — — — PWM3IF 0000 P g y In IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000 50 c. IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF — 0000 X, IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 d s IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 P IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 IC IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — — MI2C2IE SI2C2IE — 0000 3 3 IEC4 0828 — — CTMUIE — — — — — — C1TXIE — — CRCIE U2EIE U1EIE — 0000 E P IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000 X IEC6 082C — — — — — — — — — — — — — — — PWM3IE 0000 X X IEC7 082E — — — — — — — — — — — — — — — — 0000 M IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000 C IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE — 0000 2 0 IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 X / IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 5 0 IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 X IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444 A N IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 D IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004 P IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 I C IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 2 4 IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 E IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444 P D X S IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440 X 7 00 IPC14 085C — — — — — QEI1IP<2:0> — PSEMIP<2:0> — — — — 0440 X 0 G 06 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 P 5 7H IPC17 0862 — — — — — C1TXIP<2:0> — — — — — — — — 0400 /M -p IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040 C a ge 7 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 20X 3

D TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY (CONTINUED) d S s 7000 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts PIC 0 6 3 57 IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400 3 H E -p IPC24 0870 — — — — — — — — — — — — — PWM3IP<2:0> 0004 P a g IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400 X e 74 IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440 XX IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444 G P INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 5 INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000 0 X INTCON3 08C4 — — — — — — — — — — DAE DOOVR — — — — 0000 , d INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 s INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000 P I Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. C 3 3 E P X X X M C 2 0 X / 5 0 X A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-8: TIMER1 THROUGH TIMER5 REGISTER MAP 2 0 11-20 NSaFmRe Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 1 I 3 TMR1 0100 Timer1 Register xxxx C M 3 ic PR1 0102 Period Register 1 FFFF 3 roc T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — TSYNC TCS — 0000 E h P ip TMR2 0106 Timer2 Register xxxx X Te TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx X ch X n TMR3 010A Timer3 Register xxxx G o lo PR2 010C Period Register 2 FFFF P g y 5 In PR3 010E Period Register 3 FFFF 0 c. T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 X, T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 d s TMR4 0114 Timer4 Register xxxx P TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx IC TMR5 0118 Timer5 Register xxxx 3 3 PR4 011A Period Register 4 FFFF E P PR5 011C Period Register 5 FFFF X T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 X X T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 M Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. C 2 0 X / 5 0 X A N D P I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 7 0X 5

D TABLE 4-9: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP d S s 70 P 000 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 6 3 57 IC1CON1 0140 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 3 H E -p IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D P a ge 76 IICC11TBMUFR 00114464 InputI nCpaupt tCuraep 1tu Breu f1fe Tri mReegrister x0x0x0x0 XXX IC2CON1 0148 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 G P IC2CON2 014A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D 5 IC2BUF 014C Input Capture 2 Buffer Register xxxx 0 X IC2TMR 014E Input Capture 2 Timer 0000 , d IC3CON1 0150 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 s P IC3CON2 0152 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D I C IC3BUF 0154 Input Capture 3 Buffer Register xxxx 3 IC3TMR 0156 Input Capture 3 Timer 0000 3 E IC4CON1 0158 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 P IC4CON2 015A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D X X IC4BUF 015C Input Capture 4 Buffer Register xxxx X IC4TMR 015E Input Capture 4 Timer 0000 M C Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 0 X / 5 0 X A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-10: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 4 REGISTER MAP 2 0 11-20 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 1 I 3 OC1CON1 0900 — — OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 C M 3 ic OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C 3 roc OC1RS 0904 Output Compare 1 Secondary Register xxxx E h P ip OC1R 0906 Output Compare 1 Register xxxx X Te OC1TMR 0908 Timer Value 1 Register xxxx X ch X n OC2CON1 090A — — OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 G o lo OC2CON2 090C FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C P g y 5 In OC2RS 090E Output Compare 2 Secondary Register xxxx 0 c. OC2R 0910 Output Compare 2 Register xxxx X, OC2TMR 0912 Timer Value 2 Register xxxx d s OC3CON1 0914 — — OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 P OC3CON2 0916 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C IC OC3RS 0918 Output Compare 3 Secondary Register xxxx 3 3 OC3R 091A Output Compare 3 Register xxxx E P OC3TMR 091C Timer Value 3 Register xxxx X OC4CON1 091E — — OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 X X OC4CON2 0920 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C M OC4RS 0922 Output Compare 4 Secondary Register xxxx C OC4R 0924 Output Compare 4 Register xxxx 2 0 OC4TMR 0926 Timer Value 4 Register xxxx X / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 5 0 X A N D P I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 7 0X 7

D TABLE 4-11: PTG REGISTER MAP d S s 70 P 000 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 6 3 57 PTGCST 0AC0 PTGEN — PTGSIDL PTGTOGL — PTGSWT PTGSSEN PTGIVIS PTGSTRT PTGWTO — — — — PTGITM<1:0> 0000 3 H E -p PTGCON 0AC2 PTGCLK<2:0> PTGDIV<4:0> PTGPWD<3:0> — PTGWDT<2:0> 0000 P a ge 78 PPTTGGBHTOELD 00AACC46 ADCTS<4:1> IC4TSS IC3TSS IC2TSS PITCG1HTOSSLD<1O5:C0>4CS OC3CS OC2CS OC1CS OC4TSS OC3TSS OC2TSS OC1TSS 00000000 XXX PTGT0LIM 0AC8 PTGT0LIM<15:0> 0000 G P PTGT1LIM 0ACA PTGT1LIM<15:0> 0000 5 PTGSDLIM 0ACC PTGSDLIM<15:0> 0000 0 X PTGC0LIM 0ACE PTGC0LIM<15:0> 0000 , d PTGC1LIM 0AD0 PTGC1LIM<15:0> 0000 s P PTGADJ 0AD2 PTGADJ<15:0> 0000 I C PTGL0 0AD4 PTGL0<15:0> 0000 3 PTGQPTR 0AD6 — — — — — — — — — — — PTGQPTR<4:0> 0000 3 E PTGQUE0 0AD8 STEP1<7:0> STEP0<7:0> 0000 P PTGQUE1 0ADA STEP3<7:0> STEP2<7:0> 0000 X X PTGQUE2 0ADC STEP5<7:0> STEP4<7:0> 0000 X PTGQUE3 0ADE STEP7<7:0> STEP6<7:0> 0000 M C PTGQUE4 0AE0 STEP9<7:0> STEP8<7:0> 0000 2 PTGQUE5 0AE2 STEP11<7:0> STEP10<7:0> 0000 0 X PTGQUE6 0AE4 STEP13<7:0> STEP12<7:0> 0000 / 5 PTGQUE7 0AE6 STEP15<7:0> STEP14<7:0> 0000 0 X Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-12: PWM REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY 2 0 11-20 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 1 I 3 PTCON 0C00 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000 C M 3 ic PTCON2 0C02 — — — — — — — — — — — — — PCLKDIV<2:0> 0000 3 roc PTPER 0C04 PTPER<15:0> 00F8 E h P ip SEVTCMP 0C06 SEVTCMP<15:0> 0000 X Te MDC 0C0A MDC<15:0> 0000 X ch X n CHOP 0C1A CHPCLKEN — — — — — CHOPCLK<9:0> 0000 G o lo PWMKEY 0C1E PWMKEY<15:0> 0000 P g y 5 In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 c X . , d TABLE 4-13: PWM GENERATOR 1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY s P File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All IC Resets 3 3 PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 E IOCON1 0C22 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000 P X FCLCON1 0C24 — CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 X PDC1 0C26 PDC1<15:0> FFF8 X M PHASE1 0C28 PHASE1<15:0> 0000 C DTR1 0C2A — — DTR1<13:0> 0000 2 0 ALTDTR1 0C2C — — ALTDTR1<13:0> 0000 X TRIG1 0C32 TRGCMP<15:0> 0000 /5 0 TRGCON1 0C34 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 X LEBCON1 0C3A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 A LEBDLY1 0C3C — — — — LEB<11:0> 0000 N D AUXCON1 0C3E — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 P Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 7 0X 9

D TABLE 4-14: PWM GENERATOR 2 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY d S s 70 P 000 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 6 3 57 PWMCON2 0C40 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 3 H E -p IOCON2 0C42 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000 P a ge 80 FPCDLCC2ON2 00CC4464 — CLSRC<4:0> CLPOL PDCCL2M<1O5D:0> FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000F080 XXX PHASE2 0C48 PHASE2<15:0> 0000 G P DTR2 0C4A — — DTR2<13:0> 0000 5 ALTDTR2 0C4C — — ALTDTR2<13:0> 0000 0 X TRIG2 0C52 TRGCMP<15:0> 0000 , d TRGCON2 0C54 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 s P LEBCON2 0C5A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 I C LEBDLY2 0C5C — — — — LEB<11:0> 0000 3 AUXCON2 0C5E — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 3 E Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P X X TABLE 4-15: PWM GENERATOR 3 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY X M All C File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 2 0 X PWMCON3 0C60 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 / 5 IOCON3 0C62 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000 0 FCLCON3 0C64 — CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 00F8 X A PDC3 0C66 PDC3<15:0> 0000 N PHASE3 0C68 PHASE3<15:0> 0000 D DTR3 0C6A — — DTR3<13:0> 0000 P  ALTDTR3 0C6C — — ALTDTR3<13:0> 0000 IC 20 TRIG3 0C72 TRGCMP<15:0> 0000 2 1 4 1-2 TRGCON3 0C74 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 E 0 P 13 LEBCON3 0C7A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 X M LEBDLY3 0C7C — — — — LEB<11:0> 0000 X ic X ro AUXCON3 0C7E — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 G c h Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-16: QEI1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY 2 0 11-20 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 1 I 3 QEI1CON 01C0 QEIEN — QEISIDL PIMOD<2:0> IMV<1:0> — INTDIV<2:0> CNTPOL GATEN CCM<1:0> 0000 C M 3 ic QEI1IOC 01C2 QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA 000x 3 roc QEI1STAT 01C4 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN 0000 E h P ip POS1CNTL 01C6 POSCNT<15:0> 0000 X Te POS1CNTH 01C8 POSCNT<31:16> 0000 X ch X n POS1HLD 01CA POSHLD<15:0> 0000 G o lo VEL1CNT 01CC VELCNT<15:0> 0000 P g y 5 In INT1TMRL 01CE INTTMR<15:0> 0000 0 c. INT1TMRH 01D0 INTTMR<31:16> 0000 X, INT1HLDL 01D2 INTHLD<15:0> 0000 d s INT1HLDH 01D4 INTHLD<31:16> 0000 P I INDX1CNTL 01D6 INDXCNT<15:0> 0000 C 3 INDX1CNTH 01D8 INDXCNT<31:16> 0000 3 INDX1HLD 01DA INDXHLD<15:0> 0000 E P QEI1GECL 01DC QEIGEC<15:0> 0000 X QEI1ICL 01DC QEIIC<15:0> 0000 X X QEI1GECH 01DE QEIGEC<31:16> 0000 M QEI1ICH 01DE QEIIC<31:16> 0000 C 2 QEI1LECL 01E0 QEILEC<15:0> 0000 0 QEI1LECH 01E2 QEILEC<31:16> 0000 X / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 5 0 X A N D P I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 8 0X 1

D TABLE 4-17: I2C1 AND I2C2 REGISTER MAP d S s 70 P 000 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 6 3 57 I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 3 H E -p I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF P a ge 82 II22CC11BCROGN 00220064 I2C—EN —— I2C—SIDL SCL—REL IPM—IEN A1—0M DIS—SLW SMEN GCEN STREN ACKDBTaud RAaCtKe EGNeneratRoCrEN PEN RSEN SEN 01000000 XXX I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 G P I2C1ADD 020A — — — — — — I2C1 Address Register 0000 5 I2C1MSK 020C — — — — — — I2C1 Address Mask 0000 0 X I2C2RCV 0210 — — — — — — — — I2C2 Receive Register 0000 , d I2C2TRN 0212 — — — — — — — — I2C2 Transmit Register 00FF s P I2C2BRG 0214 — — — — — — — Baud Rate Generator 0000 I C I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 3 I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 3 E I2C2ADD 021A — — — — — — I2C2 Address Register 0000 P I2C2MSK 021C — — — — — — I2C2 Address Mask 0000 X X Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X M C TABLE 4-18: UART1 AND UART2 REGISTER MAP 2 0 X SFR All Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 / Name Resets 5 0 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 X U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 A N U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx D U1RXREG 0226 — — — — — — — UART1 Receive Register 0000 P  U1BRG 0228 Baud Rate Generator Prescaler 0000 IC 20 U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 2 1 4 1-2 U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 E 013 U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx PX M U2RXREG 0236 — — — — — — — UART2 Receive Register 0000 X icro U2BRG 0238 Baud Rate Generator Prescaler 0000 XG c h Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-19: SPI1 AND SPI2 REGISTER MAP 2 0 1 All d 1-20 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets sP 1 SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000 I 3 C M SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 3 ic 3 ro SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000 E c hip SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000 PX Te SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000 X ch SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 X n G olo SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000 P g y SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000 5 Inc Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0X . , d s P I C 3 3 E P X X X M C 2 0 X / 5 0 X A N D P I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 8 0X 3

D TABLE 4-20: ADC1 REGISTER MAP d S s 70 P 000 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 6 3 57 ADC1BUF0 0300 ADC1 Data Buffer 0 xxxx 3 H E -p ADC1BUF1 0302 ADC1 Data Buffer 1 xxxx P a ge 84 AADDCC11BBUUFF23 00330046 AADDCC11 DDaattaa BBuuffffeerr 23 xxxxxxxx XXX ADC1BUF4 0308 ADC1 Data Buffer 4 xxxx G P ADC1BUF5 030A ADC1 Data Buffer 5 xxxx 5 ADC1BUF6 030C ADC1 Data Buffer 6 xxxx 0 X ADC1BUF7 030E ADC1 Data Buffer 7 xxxx , d ADC1BUF8 0310 ADC1 Data Buffer 8 xxxx s P ADC1BUF9 0312 ADC1 Data Buffer 9 xxxx I C ADC1BUFA 0314 ADC1 Data Buffer 10 xxxx 3 ADC1BUFB 0316 ADC1 Data Buffer 11 xxxx 3 E ADC1BUFC 0318 ADC1 Data Buffer 12 xxxx P ADC1BUFD 031A ADC1 Data Buffer 13 xxxx X X ADC1BUFE 031C ADC1 Data Buffer 14 xxxx X ADC1BUFF 031E ADC1 Data Buffer 15 xxxx M C AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> SSRCG SIMSAM ASAM SAMP DONE 0000 2 AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS SMPI<4:0> BUFM ALTS 0000 0 X AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000 / 5 AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 0 X AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000 A AD1CSSH 032E CSS31 CSS30 — — — CSS26 CSS25 CSS24 — — — — — — — — 0000 N AD1CSSL 0330 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 D AD1CON4 0332 — — — — — — — ADDMAEN — — — — — DMABL<2:0> 0000 P  20 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IC2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-21: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0 OR 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY 2 0 11-20 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 1 I 3 C1CTRL1 0400 — — CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP — — WIN 0480 C M 3 ic C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000 3 roc C1VEC 0404 — — — FILHIT<4:0> — ICODE<6:0> 0040 E h P ip C1FCTRL 0406 DMABS<2:0> — — — — — — — — FSA<4:0> 0000 X Te C1FIFO 0408 — — FBP<5:0> — — FNRB<5:0> 0000 X ch X n C1INTF 040A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000 G o lo C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000 P g y 5 In C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000 0 c. C1CFG1 0410 — — — — — — — — SJW<1:0> BRP<5:0> 0000 X, C1CFG2 0412 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000 d s C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF P C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000 IC C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000 3 3 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. E P X X TABLE 4-22: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY X M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All C Resets 2 0 0400- See definition when WIN = x X 041E / 5 C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 0 X C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000 A C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000 N C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 D C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0> 0000 P I C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0> 0000 C 2 C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0> 0000 4 E C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0> xxxx P D C1RXD 0440 ECAN1 Receive Data Word xxxx X S X 7 C1TXD 0442 ECAN1 Transmit Data Word xxxx 0 X 0 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G 0 6 P 5 7H /M -p C a g 2 e 8 0X 5

D TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY d S s 70 P 000 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 6 3 57 0400- See definition when WIN = x 3 H-p 041E EP ag C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 X e 8 C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000 X 6 X C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000 G C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000 P 5 C1RXM0SID 0430 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx 0 X C1RXM0EID 0432 EID<15:8> EID<7:0> xxxx , C1RXM1SID 0434 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx d s C1RXM1EID 0436 EID<15:8> EID<7:0> xxxx P I C1RXM2SID 0438 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx C 3 C1RXM2EID 043A EID<15:8> EID<7:0> xxxx 3 C1RXF0SID 0440 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx E P C1RXF0EID 0442 EID<15:8> EID<7:0> xxxx X C1RXF1SID 0444 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X X C1RXF1EID 0446 EID<15:8> EID<7:0> xxxx M C1RXF2SID 0448 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx C 2 C1RXF2EID 044A EID<15:8> EID<7:0> xxxx 0 C1RXF3SID 044C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X / C1RXF3EID 044E EID<15:8> EID<7:0> xxxx 5 0 C1RXF4SID 0450 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C1RXF4EID 0452 EID<15:8> EID<7:0> xxxx A N C1RXF5SID 0454 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx D C1RXF5EID 0456 EID<15:8> EID<7:0> xxxx P  C1RXF6SID 0458 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx IC 20 C1RXF6EID 045A EID<15:8> EID<7:0> xxxx 2 1 4 1-2 C1RXF7SID 045C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx E 013 C1RXF7EID 045E EID<15:8> EID<7:0> xxxx PX M C1RXF8SID 0460 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X icro C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx XG c h C1RXF9SID 0464 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx P ip T C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx /M e ch C1RXF10SID 0468 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx C n 2 olo C1RXF10EID 046A EID<15:8> EID<7:0> xxxx 0 gy C1RXF11SID 046C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X Inc Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. .

 TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY (CONTINUED) 2 0 11-20 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 13 C1RXF11EID 046E EID<15:8> EID<7:0> xxxx IC M C1RXF12SID 0470 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 3 ic 3 ro C1RXF12EID 0472 EID<15:8> EID<7:0> xxxx E c hip C1RXF13SID 0474 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx PX Te C1RXF13EID 0476 EID<15:8> EID<7:0> xxxx X ch C1RXF14SID 0478 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X n G o lo C1RXF14EID 047A EID<15:8> EID<7:0> xxxx P g y In C1RXF15SID 047C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 50 c C1RXF15EID 047E EID<15:8> EID<7:0> xxxx X . , Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I C 3 3 E P X X X M C 2 0 X / 5 0 X A N D P I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 8 0X 7

D TABLE 4-24: CRC REGISTER MAP d S s 70 All P 00 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 0 6 3 57 CRCCON1 0640 CRCEN — CSIDL VWORD<4:0> CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0000 3 H E -p CRCCON2 0642 — — — DWIDTH<4:0> — — — PLEN<4:0> 0000 P a g CRCXORL 0644 X<15:1> — 0000 X e 8 CRCXORH 0646 X<31:16> 0000 X 8 X CRCDATL 0648 CRC Data Input Low Word 0000 G CRCDATH 064A CRC Data Input High Word 0000 P 5 CRCWDATL 064C CRC Result Low Word 0000 0 X CRCWDATH 064E CRC Result High Word 0000 , Legend: — = unimplemented, read as ‘0’. Shaded bits are not used in the operation of the programmable CRC module. d s P I C TABLE 4-25: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC202/502 AND PIC24EPXXXGP/MC202 3 3 DEVICES ONLY E P File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All X Name Resets X X RPOR0 0680 — — RP35R<5:0> — — RP20R<5:0> 0000 M RPOR1 0682 — — RP37R<5:0> — — RP36R<5:0> 0000 C RPOR2 0684 — — RP39R<5:0> — — RP38R<5:0> 0000 2 0 RPOR3 0686 — — RP41R<5:0> — — RP40R<5:0> 0000 X / RPOR4 0688 — — RP43R<5:0> — — RP42R<5:0> 0000 5 0 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X A N TABLE 4-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC203/503 AND PIC24EPXXXGP/MC203 D DEVICES ONLY P  IC 20 File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 2 1 Name Resets 4 1-20 RPOR0 0680 — — RP35R<5:0> — — RP20R<5:0> 0000 EP 13 RPOR1 0682 — — RP37R<5:0> — — RP36R<5:0> 0000 X M X ic RPOR2 0684 — — RP39R<5:0> — — RP38R<5:0> 0000 X roc RPOR3 0686 — — RP41R<5:0> — — RP40R<5:0> 0000 G h P ip T RPOR4 0688 — — RP43R<5:0> — — RP42R<5:0> 0000 /M e RPOR5 068A — — — — — — — — — — — — — — — — 0000 c C h n RPOR6 068C — — — — — — — — — — RP56R<5:0> 0000 2 olog Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0X y In c .

 TABLE 4-27: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC204/504 AND PIC24EPXXXGP/MC204 2 0 DEVICES ONLY 1 d 1-20 File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All sP 1 Name Resets I 3 C Mic RPOR0 0680 — — RP35R<5:0> — — RP20R<5:0> 0000 33 ro RPOR1 0682 — — RP37R<5:0> — — RP36R<5:0> 0000 E c h P ip RPOR2 0684 — — RP39R<5:0> — — RP38R<5:0> 0000 X Te RPOR3 0686 — — RP41R<5:0> — — RP40R<5:0> 0000 X chn RPOR4 0688 — — RP43R<5:0> — — RP42R<5:0> 0000 XG o lo RPOR5 068A — — RP55R<5:0> — — RP54R<5:0> 0000 P g y In RPOR6 068C — — RP57R<5:0> — — RP56R<5:0> 0000 50 c. Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X, d s TABLE 4-28: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC206/506 AND PIC24EPXXXGP/MC206 P I DEVICES ONLY C 3 3 File All Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E Name Resets P X RPOR0 0680 — — RP35R<5:0> — — RP20R<5:0> 0000 X RPOR1 0682 — — RP37R<5:0> — — RP36R<5:0> 0000 X M RPOR2 0684 — — RP39R<5:0> — — RP38R<5:0> 0000 C RPOR3 0686 — — RP41R<5:0> — — RP40R<5:0> 0000 2 RPOR4 0688 — — RP43R<5:0> — — RP42R<5:0> 0000 0 X RPOR5 068A — — RP55R<5:0> — — RP54R<5:0> 0000 /5 RPOR6 068C — — RP57R<5:0> — — RP56R<5:0> 0000 0 X RPOR7 068E — — RP97R<5:0> — — — — — — — — 0000 A RPOR8 0690 — — RP118R<5:0> — — — — — — — — 0000 N RPOR9 0692 — — — — — — — — — — RP120R<5:0> 0000 D Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 8 0X 9

D TABLE 4-29: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY d S s 70 P 000 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 6 3 57 RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 3 H E -p RPINR1 06A2 — — — — — — — — — INT2R<6:0> 0000 P a ge 90 RRPPIINNRR73 0066AAE6 —— — — — IC2R—<6:0> — — — —— TI2CC1KRR<<66:0:0>> 00000000 XXX RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000 G P RPINR11 06B6 — — — — — — — — — OCFAR<6:0> 0000 5 RPINR12 06B8 — FLT2R<6:0> — FLT1R<6:0> 0000 0 X RPINR14 06BC — QEB1R<6:0> — QEA1R<6:0> 0000 , d RPINR15 06BE — HOME1R<6:0> — INDX1R<6:0> 0000 s P RPINR18 06C4 — — — — — — — — — U1RXR<6:0> 0000 I C RPINR19 06C6 — — — — — — — — — U2RXR<6:0> 0000 3 RPINR22 06CC — SCK2INR<6:0> — SDI2R<6:0> 0000 3 E RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 P RPINR26 06D4 — — — — — — — — — — — — — — — — 0000 X X RPINR37 06EA — SYNCI1R<6:0> — — — — — — — — 0000 X RPINR38 06EC — DTCMP1R<6:0> — — — — — — — — 0000 M C RPINR39 06EE — DTCMP3R<6:0> — DTCMP2R<6:0> 0000 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 X / 5 0 TABLE 4-30: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY X A File All Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N Name Resets D RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 P  RPINR1 06A2 — — — — — — — — — INT2R<6:0> 0000 IC 20 RPINR3 06A6 — — — — — — — — — T2CKR<6:0> 0000 2 1 4 1-2 RPINR7 06AE — IC2R<6:0> — IC1R<6:0> 0000 E 0 P 13 RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000 X M RPINR11 06B6 — — — — — — — — — OCFAR<6:0> 0000 X ic X ro RPINR18 06C4 — — — — — — — — — U1RXR<6:0> 0000 G c h RPINR19 06C6 — — — — — — — — — U2RXR<6:0> 0000 P ip T RPINR22 06CC — SCK2INR<6:0> — SDI2R<6:0> 0000 /M e ch RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 C n 2 olo Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 g X y In c .

 TABLE 4-31: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY 2 0 11-20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 1 I 3 RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 C M 3 ic RPINR1 06A2 — — — — — — — — — INT2R<6:0> 0000 3 roc RPINR3 06A6 — — — — — — — — — T2CKR<6:0> 0000 E h P ip RPINR7 06AE — IC2R<6:0> — IC1R<6:0> 0000 X Te RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000 X ch X n RPINR11 06B6 — — — — — — — — — OCFAR<6:0> 0000 G o lo RPINR18 06C4 — — — — — — — — — U1RXR<6:0> 0000 P g y 5 In RPINR19 06C6 — — — — — — — — — U2RXR<6:0> 0000 0 c. RPINR22 06CC — SCK2INR<6:0> — SDI2R<6:0> 0000 X, RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 d s RPINR26 06D4 — — — — — — — — — C1RXR<6:0> 0000 P Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IC 3 3 E TABLE 4-32: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY P X All X File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets X M RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 C RPINR1 06A2 — — — — — — — — — INT2R<6:0> 0000 2 0 RPINR3 06A6 — — — — — — — — — T2CKR<6:0> 0000 X RPINR7 06AE — IC2R<6:0> — IC1R<6:0> 0000 /5 0 RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000 X RPINR11 06B6 — — — — — — — — — OCFAR<6:0> 0000 A RPINR12 06B8 — FLT2R<6:0> — FLT1R<6:0> 0000 N D RPINR14 06BC — QEB1R<6:0> — QEA1R<6:0> 0000 P RPINR15 06BE — HOME1R<6:0> — INDX1R<6:0> 0000 I C RPINR18 06C4 — — — — — — — — — U1RXR<6:0> 0000 2 RPINR19 06C6 — — — — — — — — — U2RXR<6:0> 0000 4 E RPINR22 06CC — SCK2INR<6:0> — SDI2R<6:0> 0000 P D X S RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 X 7 0 RPINR26 06D4 — — — — — — — — — C1RXR<6:0> 0000 X 0 0 G 0 RPINR37 06EA — SYNCI1R<6:0> — — — — — — — — 0000 6 P 57H RPINR38 06EC — DTCMP1R<6:0> — — — — — — — — 0000 /M -p RPINR39 06EE — DTCMP3R<6:0> — DTCMP2R<6:0> 0000 C a g Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 e 9 0X 1

D d S TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY s 70 P 00 File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All IC 0 Name Resets 6 3 57H RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 3E -p RPINR1 06A2 — — — — — — — — — INT2R<6:0> 0000 P a g X e 9 RPINR3 06A6 — — — — — — — — — T2CKR<6:0> 0000 X 2 RPINR7 06AE — IC2R<6:0> — IC1R<6:0> 0000 X G RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000 P RPINR11 06B6 — — — — — — — — — OCFAR<6:0> 0000 5 0 RPINR12 06B8 — FLT2R<6:0> — FLT1R<6:0> 0000 X RPINR14 06BC — QEB1R<6:0> — QEA1R<6:0> 0000 , d RPINR15 06BE — HOME1R<6:0> — INDX1R<6:0> 0000 s P RPINR18 06C4 — — — — — — — — — U1RXR<6:0> 0000 I C RPINR19 06C6 — — — — — — — — — U2RXR<6:0> 0000 3 RPINR22 06CC — SCK2INR<6:0> — SDI2R<6:0> 0000 3 E RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 P X RPINR37 06EA — SYNCI1R<6:0> — — — — — — — — 0000 X RPINR38 06EC — DTCMP1R<6:0> — — — — — — — — 0000 X M RPINR39 06EE — DTCMP3R<6:0> — DTCMP2R<6:0> 0000 C Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 0 X / 5 0 X A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-34: NVM REGISTER MAP 2 0 11-20 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 1 I 3 NVMCON 0728 WR WREN WRERR NVMSIDL — — — — — — — — NVMOP<3:0> 0000 C M 3 ic NVMADRL 072A NVMADR<15:0> 0000 3 roc NVMADRH 072C — — — — — — — — NVMADR<23:16> 0000 E h P ip NVMKEY 072E — — — — — — — — NVMKEY<7:0> 0000 X Te Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X ch X n G o lo P g TABLE 4-35: SYSTEM CONTROL REGISTER MAP y 5 In 0 c All X . File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets , d RCON 0740 TRAPR IOPUWR — — VREGSF — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1 s P OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK — CF — — OSWEN Note 2 I C CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 0030 3 3 PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030 E OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 P X Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note1: RCON register Reset values are dependent on the type of Reset. X 2: OSCCON register Reset values are dependent on the Configuration Fuses. M C 2 TABLE 4-36: REFERENCE CLOCK REGISTER MAP 0 X / All 5 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 X REFOCON 074E ROON — ROSSLP ROSEL RODIV<3:0> — — — — — — — — 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. N D P I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 9 0X 3

D TABLE 4-37: PMD REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY d S s 70 File All P 00 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 0 6 3 57 PMD1 0760 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — AD1MD 0000 3 H E -p PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 P a g PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000 X e 9 PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000 X 4 X PMD6 076A — — — — — — — — — — — — — — — — 0000 G DMA0MD P 5 DMA1MD 0 PMD7 076C — — — — — — — — — — — PTGMD — — — 0000 X DMA2MD , DMA3MD d s Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C 3 TABLE 4-38: PMD REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY 3 E P File All Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X Name Resets X X PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — AD1MD 0000 M PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 C PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000 2 0 PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000 X / PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 5 0 DMA0MD X DMA1MD A PMD7 076C — — — — — — — — — — — DMA2MD PTGMD — — — 0000 N D DMA3MD P  Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-39: PMD REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY 2 0 1 File All d 1-20 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets sP 13 PMD1 0760 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD AD1MD 0000 IC Mic PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 33 roc PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000 E h P ip PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000 X Te PMD6 076A — — — — — — — — — — — — — — — — 0000 X chn DMA0MD XG o lo DMA1MD P gy In PMD7 076C — — — — — — — — — — — DMA2MD PTGMD — — — 0000 50 c. DMA3MD X, Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I TABLE 4-40: PMD REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY C 3 3 File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All E Name Resets P X PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD AD1MD 0000 X PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 X M PMD3 0764 — — — — — CMPMD — — CRCMD — — — — — I2C2MD — 0000 C PMD4 0766 — — — — — — — — — — — — REFOMD CTMUMD — — 0000 2 0 PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 X DMA0MD / 5 DMA1MD 0 PMD7 076C — — — — — — — — — — — PTGMD — — — 0000 X DMA2MD A DMA3MD N D Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C 2 4 E P D X S X 7 0 X 0 0 G 0 6 P 5 7H /M -p C a g 2 e 9 0X 5

D TABLE 4-41: PMD REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY d S s 70000 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 3 57 PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — AD1MD 0000 3 H E -p PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 P a ge 96 PPMMDD34 00776646 —— —— —— —— —— CM—PMD —— —— CR—CMD —— —— —— REF—OMD CTM—UMD I2C—2MD —— 00000000 XXX PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 G P DMA0MD 5 DMA1MD 0 PMD7 076C — — — — — — — — — — — PTGMD — — — 0000 X DMA2MD , d DMA3MD s Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C 3 3 E P X X X M C 2 0 X / 5 0 X A N D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

 TABLE 4-42: OP AMP/COMPARATOR REGISTER MAP 2 0 1 All d 1-20 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets sP 13 CMSTAT 0A80 PSIDL — — — C4EVT C3EVT C2EVT C1EVT — — — — C4OUT C3OUT C2OUT C1OUT 0000 IC Mic CVRCON 0A82 — CVR2OE — — — VREFSEL — — CVREN CVR1OE CVRR CVRSS CVR<3:0> 0000 33 roc CM1CON 0A84 CON COE CPOL — — OPMODE CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000 E h P ip CM1MSKSRC 0A86 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000 X Te CM1MSKCON 0A88 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 X chn CM1FLTR 0A8A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000 XG o lo CM2CON 0A8C CON COE CPOL — — OPMODE CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000 P g y In CM2MSKSRC 0A8E — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000 50 c. CM2MSKCON 0A90 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 X, CM2FLTR 0A92 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000 d s CM3CON(1) 0A94 CON COE CPOL — — OPMODE CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000 P CM3MSKSRC(1) 0A96 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000 IC CM3MSKCON(1) 0A98 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 3 3 CM3FLTR(1) 0A9A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000 E P CM4CON 0A9C CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000 X CM4MSKSRC 0A9E — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000 X X CM4MSKCON 0AA0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 M CM4FLTR 0AA2 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000 C Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 0 Note1: These registers are unavailable on dsPIC33EPXXXGP502/MC502/MC202 and PIC24EP256GP/MC202 (28-pin) devices. X / 5 0 TABLE 4-43: CTMU REGISTER MAP X All A File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets N D CTMUCON1 033A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000 P CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> — — 0000 I C CTMUICON 033E ITRIM<5:0> IRNG<1:0> — — — — — — — — 0000 2 4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. E P D X S TABLE 4-44: JTAG INTERFACE REGISTER MAP X 7 0 X 000 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts G 6 P 5 7H JDATAH 0FF0 — — — — JDATAH<27:16> xxxx /M -pa JDATAL 0FF2 JDATAL<15:0> 0000 C g 2 e 9 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0X 7

D TABLE 4-45: DMAC REGISTER MAP d S s 70 All P 00 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 0 6 3 57 DMA0CON 0B00 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 3 H-p DMA0REQ 0B02 FORCE — — — — — — — IRQSEL<7:0> 00FF EP ag DMA0STAL 0B04 STA<15:0> 0000 X e 9 DMA0STAH 0B06 — — — — — — — — STA<23:16> 0000 X 8 DMA0STBL 0B08 STB<15:0> 0000 X G DMA0STBH 0B0A — — — — — — — — STB<23:16> 0000 P DMA0PAD 0B0C PAD<15:0> 0000 5 0 DMA0CNT 0B0E — — CNT<13:0> 0000 X DMA1CON 0B10 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 , d DMA1REQ 0B12 FORCE — — — — — — — IRQSEL<7:0> 00FF s DMA1STAL 0B14 STA<15:0> 0000 P I DMA1STAH 0B16 — — — — — — — — STA<23:16> 0000 C 3 DMA1STBL 0B18 STB<15:0> 0000 3 DMA1STBH 0B1A — — — — — — — — STB<23:16> 0000 E P DMA1PAD 0B1C PAD<15:0> 0000 X DMA1CNT 0B1E — — CNT<13:0> 0000 X DMA2CON 0B20 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 X M DMA2REQ 0B22 FORCE — — — — — — — IRQSEL<7:0> 00FF C DMA2STAL 0B24 STA<15:0> 0000 2 DMA2STAH 0B26 — — — — — — — — STA<23:16> 0000 0 X DMA2STBL 0B28 STB<15:0> 0000 / 5 DMA2STBH 0B2A — — — — — — — — STB<23:16> 0000 0 X DMA2PAD 0B2C PAD<15:0> 0000 A DMA2CNT 0B2E — — CNT<13:0> 0000 N DMA3CON 0B30 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 D DMA3REQ 0B32 FORCE — — — — — — — IRQSEL<7:0> 00FF P  DMA3STAL 0B34 STA<15:0> 0000 IC 20 DMA3STAH 0B36 — — — — — — — — STA<23:16> 0000 2 11-20 DDMMAA33SSTTBBLH 00BB33A8 — — — — — — — S—TB<15:0> STB<23:16> 00000000 4EP 13 DMA3PAD 0B3C PAD<15:0> 0000 X M X ic DMA3CNT 0B3E — — CNT<13:0> 0000 X ro DMAPWC 0BF0 — — — — — — — — — — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0 0000 G c hip DMARQC 0BF2 — — — — — — — — — — — — RQCOL3 RQCOL2 RQCOL1 RQCOL0 0000 P T DMAPPS 0BF4 — — — — — — — — — — — — PPST3 PPST2 PPST1 PPST0 0000 /M e ch DMALCA 0BF6 — — — — — — — — — — — — LSTCH<3:0> 000F C n 2 olo DSADRL 0BF8 DSADR<15:0> 0000 0 g DSADRH 0BFA — — — — — — — — DSADR<23:16> 0000 X y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-46: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY 2 0 11-20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 13 TRISA 0E00 — — — TRISA12 TRISA11 TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 — — TRISA1 TRISA0 1F93 IC M PORTA 0E02 — — — RA12 RA11 RA10 RA9 RA8 RA7 — — RA4 — — RA1 RA0 0000 3 ic 3 ro LATA 0E04 — — — LATA12 LATA11 LATA10 LATA9 LATA8 LATA7 — — LATA4 — — LA1TA1 LA0TA0 0000 E c hip ODCA 0E06 — — — ODCA12 ODCA11 ODCA10 ODCA9 ODCA8 ODCA7 — — ODCA4 — — ODCA1 ODCA0 0000 PX Te CNENA 0E08 — — — CNIEA12 CNIEA11 CNIEA10 CNIEA9 CNIEA8 CNIEA7 — — CNIEA4 — — CNIEA1 CNIEA0 0000 X ch CNPUA 0E0A — — — CNPUA12 CNPUA11 CNPUA10 CNPUA9 CNPUA8 CNPUA7 — — CNPUA4 — — CNPUA1 CNPUA0 0000 X n G o lo CNPDA 0E0C — — — CNPDA12 CNPDA11 CNPDA10 CNPDA9 CNPDA8 CNPDA7 — — CNPDA4 — — CNPDA1 CNPDA0 0000 P g y In ANSELA 0E0E — — — ANSA12 ANSA11 — — — — — — ANSA4 — — ANSA1 ANSA0 1813 50 c Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X . , d TABLE 4-47: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY s P File All IC Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 3 3 TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF E P PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx X LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx X X ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 M CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000 C CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 2 0 CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 X / ANSELB 0E1E — — — — — — — ANSB8 — — — — ANSB3 ANSB2 ANSB1 ANSB0 010F 5 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X A TABLE 4-48: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY N D File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All P Name Resets I C TRISC 0E20 TRISC15 — TRISC13 TRISC12 TRISC11 TRISC10 TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 BFFF 2 4 PORTC 0E22 RC15 — RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx E P LATC 0E24 LATC15 — LATC13 LATC12 LATC11 LATC10 LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx D X S7 ODCC 0E26 ODCC15 — ODCC13 ODCC12 ODCC11 ODCC10 ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000 X 0 X 0 CNENC 0E28 CNIEC15 — CNIEC13 CNIEC12 CNIEC11 CNIEC10 CNIEC9 CNIEC8 CNIEC7 CNIEC6 CNIEC5 CNIEC4 CNIEC3 CNIEC2 CNIEC1 CNIEC0 0000 0 G 06 CNPUC 0E2A CNPUC15 — CNPUC13 CNPUC12 CNPUC11 CNPUC10 CNPUC9 CNPUC8 CNPUC7 CNPUC6 CNPUC5 CNPUC4 CNPUC3 CNPUC2 CNPUC1 CNPUC0 0000 P 5 7H CNPDC 0E2C CNPDC15 — CNPDC13 CNPDC12 CNPDC11 CNPDC10 CNPDC9 CNPDC8 CNPDC7 CNPDC6 CNPDC5 CNPDC4 CNPDC3 CNPDC2 CNPDC1 CNPDC0 0000 /M -p ANSELC 0E2E — — — — ANSC11 — — — — — — — — ANSC2 ANSC1 ANSC0 0807 C a g 2 e 9 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0X 9

D TABLE 4-49: PORTD REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY d S s 7000 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 0 6 3 57 TRISD 0E30 — — — — — — — TRISD8 — TRISD6 TRISD5 — — — — — 0160 3 H E -p PORTD 0E32 — — — — — — — RD8 — RD6 RD5 — — — — — xxxx P a g LATD 0E34 — — — — — — — LATD8 — LATD6 LATD5 — — — — — xxxx X e 10 ODCD 0E36 — — — — — — — ODCD8 — ODCD6 ODCD5 — — — — — 0000 XX 0 CNEND 0E38 — — — — — — — CNIED8 — CNIED6 CNIED5 — — — — — 0000 G P CNPUD 0E3A — — — — — — — CNPUD8 — CNPUD6 CNPUD5 — — — — — 0000 5 CNPDD 0E3C — — — — — — — CNPDD8 — CNPDD6 CNPDD5 — — — — — 0000 0 X Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. , d s P TABLE 4-50: PORTE REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY I C File All 3 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 Name Resets E TRISE 0E40 TRISE15 TRISE14 TRISE13 TRISE12 — — — — — — — — — — — — F000 P X PORTE 0E42 RE15 RE14 RE13 RE12 — — — — — — — — — — — — xxxx X LATE 0E44 LATE15 LATE14 LATE13 LATE12 — — — — — — — — — — — — xxxx X M ODCE 0E46 ODCE15 ODCE14 ODCE13 ODCE12 — — — — — — — — — — — — 0000 C CNENE 0E48 CNIEE15 CNIEE14 CNIEE13 CNIEE12 — — — — — — — — — — — — 0000 2 CNPUE 0E4A CNPUE15 CNPUE14 CNPUE13 CNPUE12 — — — — — — — — — — — — 0000 0 X CNPDE 0E4C CNPDE15 CNPDE14 CNPDE13 CNPDE12 — — — — — — — — — — — — 0000 / 5 ANSELE 0E4E ANSE15 ANSE14 ANSE13 ANSE12 — — — — — — — — — — — — F000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X A N TABLE 4-51: PORTF REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY D P  20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC2 11-20 PTROIRSTFF 00EE5520 —— —— —— —— —— —— —— —— —— —— —— —— —— —— TRRIFS1F1 TRRIFS0F0 0x0x0x3x 4EP 13 LATF 0E54 — — — — — — — — — — — — — — LATF1 LATF0 xxxx X M ODCF 0E56 — — — — — — — — — — — — — — ODCF1 ODCF0 0000 X ic X ro CNENF 0E58 — — — — — — — — — — — — — — CNIEF1 CNIEF0 0000 G c hip CNPUF 0E5A — — — — — — — — — — — — — — CNPUF1 CNPUF0 0000 P T CNPDF 0E5C — — — — — — — — — — — — — — CNPDF1 CNPDF0 0000 /M e ch Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. C n 2 olo 0 g X y In c .

 TABLE 4-52: PORTG REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY 2 0 11-20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 1 I 3 TRISG 0E60 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — — — — — 03C0 C M 3 ic PORTG 0E62 — — — — — — RG9 RG8 RG7 RG6 — — — — — — xxxx 3 roc LATG 0E64 — — — — — — LATG9 LATG8 LATG7 LATG6 — — — — — — xxxx E h P ip ODCG 0E66 — — — — — — ODCG9 ODCG8 ODCG7 ODCG6 — — — — — — 0000 X Te CNENG 0E68 — — — — — — CNIEG9 CNIEG8 CNIEG7 CNIEG6 — — — — — — 0000 X ch X n CNPUG 0E6A — — — — — — CNPUG9 CNPUG8 CNPUG7 CNPUG6 — — — — — — 0000 G o lo CNPDG 0E6C — — — — — — CNPDG9 CNPDG8 CNPDG7 CNPDG6 — — — — — — 0000 P g y 5 In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 c X . , d s P I C 3 3 E P X X X M C 2 0 X / 5 0 X A N D P I C 2 4 E P D S X 7 X 0 0 X 0 0 G 6 5 P 7 H /M -p a C g e 2 1 0 0 X 1

D TABLE 4-53: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY d S s 70 File All P 00 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 0 6 3 57 TRISA 0E00 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F 3 H E -p PORTA 0E02 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 0000 P a g LATA 0E04 — — — — — LATA10 LATA9 LATA8 LATA7 — — LATA4 LATA3 LATA2 LA1TA1 LA0TA0 0000 X e 1 ODCA 0E06 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 X 0 X 2 CNENA 0E08 — — — — — CNIEA10 CNIEA9 CNIEA8 CNIEA7 — — CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000 G CNPUA 0E0A — — — — — CNPUA10 CNPUA9 CNPUA8 CNPUA7 — — CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000 P 5 CNPDA 0E0C — — — — — CNPDA10 CNPDA9 CNPDA8 CNPDA7 — — CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000 0 X ANSELA 0E0E — — — — — — — — — — — ANSA4 — — ANSA1 ANSA0 0013 , Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P TABLE 4-54: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY IC 3 File All 3 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets E P TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF X X PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx X LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx M C ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 2 CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000 0 X CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 / 5 CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 0 X ANSELB 0E1E — — — — — — — ANSB8 — — — — ANSB3 ANSB2 ANSB1 ANSB0 010F A Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. N D TABLE 4-55: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY P  IC 20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 2 1 4 1-20 TRISC 0E20 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF EP 13 PORTC 0E22 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx X M X ic LATC 0E24 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx X roc ODCC 0E26 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000 G h P ip CNENC 0E28 — — — — — — CNIEC9 CNIEC8 CNIEC7 CNIEC6 CNIEC5 CNIEC4 CNIEC3 CNIEC2 CNIEC1 CNIEC0 0000 T /M e CNPUC 0E2A — — — — — — CNPUC9 CNPUC8 CNPUC7 CNPUC6 CNPUC5 CNPUC4 CNPUC3 CNPUC2 CNPUC1 CNPUC0 0000 c C hn CNPDC 0E2C — — — — — — CNPDC9 CNPDC8 CNPDC7 CNPDC6 CNPDC5 CNPDC4 CNPDC3 CNPDC2 CNPDC1 CNPDC0 0000 2 olo ANSELC 0E2E — — — — — — — — — — — — — ANSC2 ANSC1 ANSC0 0007 0 g X y In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-56: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY 2 0 11-20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts dsP 13 TRISA 0E00 — — — — — — — TRISA8 — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 011F IC M PORTA 0E02 — — — — — — — RA8 — — — RA4 RA3 RA2 RA1 RA0 0000 3 ic 3 ro LATA 0E04 — — — — — — — LATA8 — — — LATA4 LATA3 LATA2 LA1TA1 LA0TA0 0000 E c hip ODCA 0E06 — — — — — — — ODCA8 — — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 PX Te CNENA 0E08 — — — — — — — CNIEA8 — — — CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000 X ch CNPUA 0E0A — — — — — — — CNPUA8 — — — CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000 X n G o lo CNPDA 0E0C — — — — — — — CNPDA8 — — — CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000 P g y In ANSELA 0E0E — — — — — — — — — — — ANSA4 — — ANSA1 ANSA0 0013 50 c Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X . , d TABLE 4-57: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY s P File All IC Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 3 3 TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF E P PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx X LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx X X ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 M CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000 C CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 2 0 CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 X / ANSELB 0E1E — — — — — — — ANSB8 — — — — ANSB3 ANSB2 ANSB1 ANSB0 010F 5 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X A TABLE 4-58: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY N D File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All P Name Resets I C TRISC 0E20 — — — — — — — TRISC8 — — — — — — TRISC1 TRISC0 0103 2 4 PORTC 0E22 — — — — — — — RC8 — — — — — — RC1 RC0 xxxx E P D LATC 0E24 — — — — — — — LATC8 — — — — — — LATC1 LATC0 xxxx S X 70 ODCC 0E26 — — — — — — — ODCC8 — — — — — — ODCC1 ODCC0 0000 X 0 X 0 CNENC 0E28 — — — — — — — CNIEC8 — — — — — — CNIEC1 CNIEC0 0000 0 G 6 5 CNPUC 0E2A — — — — — — — CNPUC8 — — — — — — CNPUC1 CNPUC0 0000 P 7 H CNPDC 0E2C — — — — — — — CNPDC8 — — — — — — CNPDC1 CNPDC0 0000 /M -p a ANSELC 0E2E — — — — — — — — — — — — — — ANSC1 ANSC0 0003 C g e 2 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 0 X 3

D TABLE 4-59: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY d S s 70000 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 3 57 TRISA 0E00 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F 3 H E -p PORTA 0E02 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 0000 P a ge 10 LOADTCAA 00EE0064 —— —— —— —— —— —— —— —— —— —— —— OLDATCAA44 OLDATCAA33 OLDATCAA22 LOAD1CTAA11 LOAD0CTAA00 00000000 XXX 4 CNENA 0E08 — — — — — — — — — — — CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000 G P CNPUA 0E0A — — — — — — — — — — — CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000 5 CNPDA 0E0C — — — — — — — — — — — CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000 0 X ANSELA 0E0E — — — — — — — — — — — ANSA4 — — ANSA1 ANSA0 0013 , d Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. s P I C TABLE 4-60: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY 3 3 File All E Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets P X TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF X X PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx M LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx C ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 2 0 CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000 X / CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 5 0 CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 X ANSELB 0E1E — — — — — — — ANSB8 — — — — ANSB3 ANSB2 ANSB1 ANSB0 010F A N Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. D P  IC 20 2 1 4 1-2 E 0 P 13 X M X ic X ro G c h P ip T /M e c C h n 2 olo 0 g X y In c .

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.4.1 PAGED MEMORY SCHEME address or Program Space Visibility (PSV) address. The Data Space Page registers are located in the The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ SFR space. 50X and PIC24EPXXXGP/MC20X architecture extends the available Data Space through a paging Construction of the EDS address is shown in scheme, which allows the available Data Space to Example4-1. When DSRPAG<9> = 0 and the base be accessed using MOV instructions in a linear address bit, EA<15>=1, the DSRPAG<8:0> bits are fashion for pre-modified and post-modified Effective concatenated onto EA<14:0> to form the 24-bit EDS Addresses (EA). The upper half of the base Data read address. Similarly, when base address bit, Space address is used in conjunction with the Data EA<15>= 1, DSWPAG<8:0> are concatenated onto Space Page registers, the 10-bit Read Page register EA<14:0> to form the 24-bit EDS write address. (DSRPAG) or the 9-bit Write Page register (DSWPAG), to form an Extended Data Space (EDS) EXAMPLE 4-1: EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION Byte 16-Bit DS EA Select EA<15> = 0 No EDS Access 0 EA (DSRPAG = Don’t care) EA<15> Generate Y PSV Address DSRPAG<9> 1 EA = 1? N Select DSRPAG 0 DSRPAG<8:0> 9 Bits 15 Bits 24-Bit EDS EA Byte Select Note: DS read access when DSRPAG = 0x000 will force an address error trap.  2011-2013 Microchip Technology Inc. DS70000657H-page 105

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X EXAMPLE 4-2: EXTENDED DATA SPACE (EDS) WRITE ADDRESS GENERATION Byte 16-Bit DS EA Select EA<15> = 0 (DSWPAG = don’t care) No EDS Access 0 EA Generate PSV Address EA<15> 1 EA DSWPAG<8:0> 9 Bits 15 Bits 24-Bit EDS EA Byte Select Note: DS read access when DSRPAG = 0x000 will force an address error trap. The paged memory scheme provides access to The Program Space (PS) can be accessed with a multiple 32-Kbyte windows in the EDS and PSV DSRPAG of 0x200 or greater. Only reads from PS are memory. The Data Space Page registers, DSxPAG, in supported using the DSRPAG. Writes to PS are not combination with the upper half of the Data Space supported, so DSWPAG is dedicated to DS, including address, can provide up to 16 Mbytes of additional EDS only. The Data Space and EDS can be read from, address space in the EDS and 8 Mbytes (DSRPAG and written to, using DSRPAG and DSWPAG, only) of PSV address space. The paged data memory respectively. space is shown in Example4-3. DS70000657H-page 106  2011-2013 Microchip Technology Inc.

 EXAMPLE 4-3: PAGED DATA MEMORY SPACE 2 0 Local Data Space EDS Program Space Table Address Space 1 d 1-20 DS_Addr<14:(0D>SRPAG<9:0>/DSWPAG<8:0>) (Instruction & Data) (TBLPAG<7:0>) sP 1 I 3 M 0x0000 Page 0 C3 ic Reserved 3 roc (Will produce an DS_Addr<15:0> E hip Technology 000xxx770FF0FF0FF0 ((aDDEdSSDdWRrSeP PsPAAsaG Gegre==r o000rxx xt00r0a000p111))) P0r(xols0gw0r_a –0m 0< 0M105e:m0>o)ry 0x0000 TT(TBBBLLMRLRlsPSDDwABHL GU //UTTs=sBBiniLLn0gWWgx0TT0LH) PXXXGP5 In 0xFFFF 0 c X . , d s DS_Addr<15:0> 0x0000 P 0x0000 EDS Page 0x1FF IC SFR Registers (DSRPAG=0x1FF) 3 (DSWPAG=0x1FF) 3 0x0FFF 0x7FFF 0x0000 E 0x1000 (TBLPAG=0x7F) P 0x0000 EDS Page 0x200 lsw Using X X Up to 8-Kbyte (DSRPAG=0x200) 0x7F_FFFF TBLRDL/TBLWTL X RAM(1) No writes allowed MSB Using M 0x7FFF TBLRDH/TBLWTH C 0x2FFF PSV 0xFFFF 2 0x3000 Program 0 0x7FFF Memory Program Memory X 0x8000 (lsw) (MSB – <23:16>) /5 32-Kbyte 0x0000 0x00_0000 0 EDS Page 0x2FF X EDS Window (DSRPAG=0x2FF) A 0xFFFF No writes allowed N 0x7FFF D 0x0000 EDS Page 0x300 P I (DSRPAG=0x300) C No writes allowed 2 0x7FFF 4 E PSV P DS Program X 7 Memory X 0 0x7F_FFFF 00 (MSB) X 0 0x0000 G 6 EDS Page 0x3FF 5 P 7H (DSRPAG=0x3FF) /M -p No writes allowed ag 0x7FFF C e 2 1 Note 1: For 64K Flash devices. RAM size and end location is dependent on device; see Section4.2 “Data Address Space” for more information. 0 0 X 7

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Allocating different Page registers for read and write In general, when an overflow is detected, the DSxPAG access allows the architecture to support data register is incremented and the EA<15> bit is set to movement between different pages in data memory. keep the base address within the EDS or PSV window. This is accomplished by setting the DSRPAG register When an underflow is detected, the DSxPAG register is value to the page from which you want to read, and decremented and the EA<15> bit is set to keep the configuring the DSWPAG register to the page to which base address within the EDS or PSV window. This it needs to be written. Data can also be moved from creates a linear EDS and PSV address space, but only different PSV to EDS pages, by configuring the when using Register Indirect Addressing modes. DSRPAG and DSWPAG registers to address PSV and Exceptions to the operation described above arise EDS space, respectively. The data can be moved when entering and exiting the boundaries of Page 0, between pages by a single instruction. EDS and PSV spaces. Table4-61 lists the effects of When an EDS or PSV page overflow or underflow overflow and underflow scenarios at different occurs, EA<15> is cleared as a result of the register boundaries. indirect EA calculation. An overflow or underflow of the In the following cases, when overflow or underflow EA in the EDS or PSV pages can occur at the page occurs, the EA<15> bit is set and the DSxPAG is not boundaries when: modified; therefore, the EA will wrap to the beginning of • The initial address prior to modification addresses the current page: an EDS or PSV page • Register Indirect with Register Offset Addressing • The EA calculation uses Pre-Modified or • Modulo Addressing Post-Modified Register Indirect Addressing; • Bit-Reversed Addressing however, this does not include Register Offset Addressing TABLE 4-61: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS and PSV SPACE BOUNDARIES(2,3,4) Before After O/U, Operation R/W DS Page DS Page DSxPAG DSxPAG EA<15> Description EA<15> Description O, DSRPAG = 0x1FF 1 EDS: Last page DSRPAG = 0x1FF 0 See Note 1 Read O, DSRPAG = 0x2FF 1 PSV: Last lsw DSRPAG = 0x300 1 PSV: First MSB [++Wn] Read page page or O, DSRPAG = 0x3FF 1 PSV: Last MSB DSRPAG = 0x3FF 0 See Note 1 [Wn++] Read page O, DSWPAG = 0x1FF 1 EDS: Last page DSWPAG = 0x1FF 0 See Note 1 Write U, DSRPAG = 0x001 1 PSV page DSRPAG = 0x001 0 See Note 1 Read [--Wn] U, DSRPAG = 0x200 1 PSV: First lsw DSRPAG = 0x200 0 See Note 1 or Read page [Wn--] U, DSRPAG = 0x300 1 PSV: First MSB DSRPAG = 0x2FF 1 PSV: Last lsw Read page page Legend: O = Overflow, U = Underflow, R = Read, W = Write Note 1: The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x8000). 2: An EDS access with DSxPAG = 0x000 will generate an address error trap. 3: Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate an address error trap. 4: Pseudo-Linear Addressing is not supported for large offsets. DS70000657H-page 108  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.4.2 EXTENDED X DATA SPACE The remaining pages, including both EDS and PSV pages, are only accessible using the DSRPAG or The lower portion of the base address space range, DSWPAG registers in combination with the upper between 0x0000 and 0x7FFF, is always accessible 32Kbytes, 0x8000 to 0xFFFF, of the base address, regardless of the contents of the Data Space Page where base address bit, EA<15> = 1. registers. It is indirectly addressable through the register indirect instructions. It can be regarded as For example, when DSRPAG = 0x001 or being located in the default EDS Page 0 (i.e., EDS DSWPAG=0x001, accesses to the upper 32 Kbytes, address range of 0x000000 to 0x007FFF with the base 0x8000 to 0xFFFF, of the Data Space will map to the address bit, EA<15> = 0, for this address range). EDS address range of 0x008000 to 0x00FFFF. When However, Page 0 cannot be accessed through the DSRPAG = 0x002 or DSWPAG = 0x002, accesses to upper 32 Kbytes, 0x8000 to 0xFFFF, of base Data the upper 32 Kbytes of the Data Space will map to the Space, in combination with DSRPAG = 0x000 or EDS address range of 0x010000 to 0x017FFF and so DSWPAG = 0x000. Consequently, DSRPAG and on, as shown in the EDS memory map in Figure4-17. DSWPAG are initialized to 0x001 at Reset. For more information on the PSV page access using Note1: DSxPAG should not be used to access Data Space Page registers, refer to the “Program Page 0. An EDS access with DSxPAG Space Visibility from Data Space” section in set to 0x000 will generate an address “Program Memory” (DS70613) of the “dsPIC33/ error trap. PIC24 Family Reference Manual”. 2: Clearing the DSxPAG in software has no effect. FIGURE 4-17: EDS MEMORY MAP EA<15:0> 0x0000 SFR/DS (PAGE 0) Conventional DS Address 0x8000 0x008000 DS PAGE 1 0xFFFF 0x010000 PAGE 2 0x018000 PAGE 3 DSRPAG<9> = 0 EDS EA Address (24 bits) (DSRPAG<8:0>, EA<14:0>) (DSWPAG<8:0>, EA<14:0>) 0xFE8000 PAGE 1FD 0xFF0000 PAGE 1FE 0xFF8000 PAGE 1FF  2011-2013 Microchip Technology Inc. DS70000657H-page 109

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.4.3 DATA MEMORY ARBITRATION AND that of the CPU maintain the same priority relationship BUS MASTER PRIORITY relative to each other. The priority schemes for bus masters with different MSTRPR values are tabulated in EDS accesses from bus masters in the system are Table4-62. arbitrated. This bus master priority control allows the user The arbiter for data memory (including EDS) arbitrates application to manipulate the real-time response of the between the CPU, the DMA and the ICD module. In the system, either statically during initialization or event of coincidental access to a bus by the bus dynamically in response to real-time events. masters, the arbiter determines which bus master access has the highest priority. The other bus masters TABLE 4-62: DATA MEMORY BUS are suspended and processed after the access of the ARBITER PRIORITY bus by the bus master with the highest priority. By default, the CPU is Bus Master 0 (M0) with the MSTRPR<15:0> Bit Setting(1) Priority highest priority and the ICD is Bus Master 4 (M4) with 0x0000 0x0020 the lowest priority. The remaining bus master (DMA Controller) is allocated to M3 (M1 and M2 are reserved M0 (highest) CPU DMA and cannot be used). The user application may raise or M1 Reserved CPU lower the priority of the DMA Controller to be above that M2 Reserved Reserved of the CPU by setting the appropriate bits in the EDS Bus Master Priority Control (MSTRPR) register. All bus M3 DMA Reserved masters with raised priorities will maintain the same M4 (lowest) ICD ICD priority relationship relative to each other (i.e., M1 Note 1: All other values of MSTRPR<15:0> are being highest and M3 being lowest, with M2 in reserved. between). Also, all the bus masters with priorities below FIGURE 4-18: ARBITER ARCHITECTURE DMA Reserved ICD CPU MSTRPR<15:0> M0 M1 M2 M3 M4 Data Memory Arbiter SRAM DS70000657H-page 110  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.4.4 SOFTWARE STACK Note1: To maintain system Stack Pointer (W15) The W15 register serves as a dedicated Software coherency, W15 is never subject to Stack Pointer (SSP) and is automatically modified by (EDS) paging, and is therefore restricted exception processing, subroutine calls and returns; to an address range of 0x0000 to however, W15 can be referenced by any instruction in 0xFFFF. The same applies to the W14 the same manner as all other W registers. This when used as a Stack Frame Pointer simplifies reading, writing and manipulating of the (SFA = 1). Stack Pointer (for example, creating stack frames). 2: As the stack can be placed in, and can Note: To protect against misaligned stack access X and Y spaces, care must be accesses, W15<0> is fixed to ‘0’ by the taken regarding its use, particularly with hardware. regard to local automatic variables in a C development environment W15 is initialized to 0x1000 during all Resets. This address ensures that the SSP points to valid RAM in all dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X FIGURE 4-19: CALL STACK FRAME and PIC24EPXXXGP/MC20X devices, and permits stack availability for non-maskable trap exceptions. 0x0000 15 0 These can occur before the SSP is initialized by the user CALL SUBR software. You can reprogram the SSP during initialization to any location within Data Space. d The Software Stack Pointer always points to the first owaress available free word and fills the software stack s Tddr wA PC<15:0> W15 (before CALL) wFstioagrcukkrie npgo4 p-1 f(9rro emialldu )s ltaoranwtdee rps ohstoot-wwin acirrtd ep mreeh-nigdtshe ceforrer maa sedtnadtcrsek s fposuers sah. ack GroHigher b‘00000<0F0r0e0e’ WPoCrd<>22:16> W15 (after CALL) St (writes). When the PC is pushed onto the stack, PC<15:0> are pushed onto the first available stack word, then PC<22:16> are pushed into the second available stack location. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, as shown in Figure4-19. During exception processing, the MSB of the PC is concatenated with the lower 8 bits of the CPU STATUS Register, SR. This allows the contents of SRL to be preserved automatically during interrupt processing.  2011-2013 Microchip Technology Inc. DS70000657H-page 111

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.5 Instruction Addressing Modes 4.5.2 MCU INSTRUCTIONS The addressing modes shown in Table4-63 form the The three-operand MCU instructions are of the form: basis of the addressing modes optimized to support the Operand 3 = Operand 1 <function> Operand 2 specific features of individual instructions. The where Operand 1 is always a working register (that is, addressing modes provided in the MAC class of the addressing mode can only be Register Direct), instructions differ from those in the other instruction which is referred to as Wb. Operand 2 can be a W reg- types. ister fetched from data memory or a 5-bit literal. The result location can either be a W register or a data 4.5.1 FILE REGISTER INSTRUCTIONS memory location. The following addressing modes are Most file register instructions use a 13-bit address field supported by MCU instructions: (f) to directly address data present in the first • Register Direct 8192bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, • Register Indirect which is denoted as WREG in these instructions. The • Register Indirect Post-Modified destination is typically either the same file register or • Register Indirect Pre-Modified WREG (with the exception of the MUL instruction), • 5-Bit or 10-Bit Literal which writes the result to a register or register pair. The Note: Not all instructions support all the MOV instruction allows additional flexibility and can addressing modes given above. Individ- access the entire Data Space. ual instructions can support different subsets of these addressing modes. TABLE 4-63: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn form the Effective Address (EA). Register Indirect Post-Modified The contents of Wn form the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. DS70000657H-page 112  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.5.3 MOVE AND ACCUMULATOR 4.5.4 MAC INSTRUCTIONS INSTRUCTIONS (dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X DEVICES Move instructions, which apply to ONLY) dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices, and the The dual source operand DSP instructions (CLR, ED, DSP accumulator class of instructions, which EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred apply to the dsPIC33EPXXXMC20X/50X and to as MAC instructions, use a simplified set of addressing dsPIC33EPXXXGP50X devices, provide a greater modes to allow the user application to effectively degree of addressing flexibility than other instructions. manipulate the Data Pointers through register indirect In addition to the addressing modes supported by most tables. MCU instructions, move and accumulator instructions The Two-Source Operand Prefetch registers must be also support Register Indirect with Register Offset members of the set: {W8, W9, W10, W11}. For data Addressing mode, also referred to as Register Indexed reads, W8 and W9 are always directed to the X RAGU, mode. and W10 and W11 are always directed to the Y AGU. Note: For the MOV instructions, the addressing The Effective Addresses generated (before and after mode specified in the instruction can differ modification) must therefore, be valid addresses within for the source and destination EA. How- X Data Space for W8 and W9, and Y Data Space for ever, the 4-bit Wb (Register Offset) field is W10 and W11. shared by both source and destination (but Note: Register Indirect with Register Offset typically only used by one). Addressing mode is available only for W9 In summary, the following addressing modes are (in X space) and W11 (in Y space). supported by move and accumulator instructions: In summary, the following addressing modes are • Register Direct supported by the MAC class of instructions: • Register Indirect • Register Indirect • Register Indirect Post-modified • Register Indirect Post-Modified by 2 • Register Indirect Pre-modified • Register Indirect Post-Modified by 4 • Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 6 • Register Indirect with Literal Offset • Register Indirect with Register Offset (Indexed) • 8-Bit Literal • 16-Bit Literal 4.5.5 OTHER INSTRUCTIONS Note: Not all instructions support all the Besides the addressing modes outlined previously, some addressing modes given above. Individual instructions use literal constants of various sizes. For instructions may support different subsets example, BRA (branch) instructions use 16-bit signed of these addressing modes. literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ULNK, the source of an operand or result is implied by the opcode itself. Certain operations, such as a NOP, do not have any operands.  2011-2013 Microchip Technology Inc. DS70000657H-page 113

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.6 Modulo Addressing 4.6.1 START AND END ADDRESS (dsPIC33EPXXXMC20X/50X and The Modulo Addressing scheme requires that a dsPIC33EPXXXGP50X Devices starting and ending address be specified, and loaded Only) into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND Modulo Addressing mode is a method of providing an (see Table4-1). automated means to support circular data buffers using hardware. The objective is to remove the need for Note: Y space Modulo Addressing EA calcula- tions assume word-sized data (LSb of software to perform data address boundary checks when executing tightly looped code, as is typical in every EA is always clear). many DSP algorithms. The length of a circular buffer is not directly specified. It Modulo Addressing can operate in either Data or Pro- is determined by the difference between the corre- gram Space (since the Data Pointer mechanism is sponding start and end addresses. The maximum essentially the same for both). One circular buffer can be possible length of the circular buffer is 32K words supported in each of the X (which also provides the point- (64Kbytes). ers into Program Space) and Y Data Spaces. Modulo 4.6.2 W ADDRESS REGISTER Addressing can operate on any W Register Pointer. How- ever, it is not advisable to use W14 or W15 for Modulo SELECTION Addressing since these two registers are used as the The Modulo and Bit-Reversed Addressing Control Stack Frame Pointer and Stack Pointer, respectively. register, MODCON<15:0>, contains enable flags as well In general, any particular circular buffer can be config- as a W register field to specify the W Address registers. ured to operate in only one direction, as there are certain The XWM and YWM fields select the registers that restrictions on the buffer start address (for incrementing operate with Modulo Addressing: buffers) or end address (for decrementing buffers), • If XWM = 1111, XRAGU and X WAGU Modulo based upon the direction of the buffer. Addressing is disabled The only exception to the usage restrictions is for • If YWM = 1111, Y AGU Modulo Addressing is buffers that have a power-of-two length. As these disabled buffers satisfy the start and end address criteria, they The X Address Space Pointer W register (XWM), to can operate in a bidirectional mode (that is, address which Modulo Addressing is to be applied, is stored in boundary checks are performed on both the lower and MODCON<3:0> (see Table4-1). Modulo Addressing is upper address boundaries). enabled for X Data Space when XWM is set to any value other than ‘1111’ and the XMODEN bit is set (MODCON<15>). The Y Address Space Pointer W register (YWM), to which Modulo Addressing is to be applied, is stored in MODCON<7:4>. Modulo Addressing is enabled for Y Data Space when YWM is set to any value other than ‘1111’ and the YMODEN bit is set at MODCON<14>. FIGURE 4-20: MODULO ADDRESSING OPERATION EXAMPLE Byte MOV #0x1100, W0 Address MOV W0, XMODSRT ;set modulo start address 0x1100 MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer 0x1163 DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location Start Addr = 0x1100 AGAIN: INC W0, W0 ;increment the fill value End Addr = 0x1163 Length = 50 words DS70000657H-page 114  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.6.3 MODULO ADDRESSING 4.7.1 BIT-REVERSED ADDRESSING APPLICABILITY IMPLEMENTATION Modulo Addressing can be applied to the Effective Bit-Reversed Addressing mode is enabled when all Address (EA) calculation associated with any W these conditions are met: register. Address boundaries check for addresses • BWMx bits (W register selection) in the MODCON equal to: register are any value other than ‘1111’ (the stack • The upper boundary addresses for incrementing cannot be accessed using Bit-Reversed buffers Addressing) • The lower boundary addresses for decrementing • The BREN bit is set in the XBREV register buffers • The addressing mode used is Register Indirect It is important to realize that the address boundaries with Pre-Increment or Post-Increment check for addresses less than, or greater than, the If the length of a bit-reversed buffer is M = 2N bytes, upper (for incrementing buffers) and lower (for the last ‘N’ bits of the data buffer start address must decrementing buffers) boundary addresses (not just be zeros. equal to). Address changes can, therefore, jump XBREV<14:0> is the Bit-Reversed Addressing modi- beyond boundaries and still be adjusted correctly. fier, or ‘pivot point’, which is typically a constant. In the Note: The modulo corrected Effective Address case of an FFT computation, its value is equal to half of is written back to the register only when the FFT data buffer size. Pre-Modify or Post-Modify Addressing Note: All bit-reversed EA calculations assume mode is used to compute the Effective word-sized data (LSb of every EA is always Address. When an address offset (such clear). The XBREVx value is scaled as [W7 + W2]) is used, Modulo accordingly to generate compatible (byte) Addressing correction is performed but addresses. the contents of the register remain unchanged. When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or Post- 4.7 Bit-Reversed Addressing Increment Addressing and word-sized data writes. It does not function for any other addressing mode or for (dsPIC33EPXXXMC20X/50X and byte-sized data and normal addresses are generated dsPIC33EPXXXGP50X Devices instead. When Bit-Reversed Addressing is active, the Only) W Address Pointer is always added to the address modifier (XBREVx) and the offset associated with the Bit-Reversed Addressing mode is intended to simplify Register Indirect Addressing mode is ignored. In data reordering for radix-2 FFT algorithms. It is addition, as word-sized data is a requirement, the LSb supported by the X AGU for data writes only. of the EA is ignored (and always clear). The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. Note: Modulo Addressing and Bit-Reversed The address source and destination are kept in normal Addressing can be enabled simultaneously order. Thus, the only operand requiring reversal is the using the same W register, but Bit- modifier. Reversed Addressing operation will always take precedence for data writes when enabled. If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer.  2011-2013 Microchip Technology Inc. DS70000657H-page 115

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 4-21: BIT-REVERSED ADDRESSING EXAMPLE Sequential Address b15 b14 b13 b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XBREV<14:0> = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-64: BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 DS70000657H-page 116  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.8 Interfacing Program and Data Table instructions allow an application to read or write Memory Spaces to small areas of the program memory. This capability makes the method ideal for accessing data tables that The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ need to be updated periodically. It also allows access 50X and PIC24EPXXXGP/MC20X architecture uses a to all bytes of the program word. The remapping 24-bit-wide Program Space (PS) and a 16-bit-wide method allows an application to access a large block of Data Space (DS). The architecture is also a modified data on a read-only basis, which is ideal for look-ups Harvard scheme, meaning that data can also be from a large table of static data. The application can present in the Program Space. To use this data suc- only access the least significant word of the program cessfully, it must be accessed in a way that preserves word. the alignment of information in both spaces. Aside from normal execution, the architecture of the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X devices provides two methods by which Program Space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the Program Space • Remapping a portion of the Program Space into the Data Space (Program Space Visibility) TABLE 4-65: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx FIGURE 4-22: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits User/Configuration Byte Select Space Select Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain word alignment of data in the Program and Data Spaces. 2: Table operations are not required to be word-aligned. Table Read operations are permitted in the configuration memory space.  2011-2013 Microchip Technology Inc. DS70000657H-page 117

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 4.8.1 DATA ACCESS FROM PROGRAM - In Byte mode, either the upper or lower byte MEMORY USING TABLE of the lower program word is mapped to the INSTRUCTIONS lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower The TBLRDL and TBLWTL instructions offer a direct byte is selected when it is ‘0’. method of reading or writing the lower word of any • TBLRDH (Table Read High): address within the Program Space without going through Data Space. The TBLRDH and TBLWTH - In Word mode, this instruction maps the entire instructions are the only method to read or write the upper word of a program address (P<23:16>) upper 8 bits of a Program Space word as data. to a data address. The ‘phantom’ byte (D<15:8>) is always ‘0’. The PC is incremented by two for each successive 24-bit - In Byte mode, this instruction maps the upper program word. This allows program memory addresses or lower byte of the program word to D<7:0> to directly map to Data Space addresses. Program mem- of the data address in the TBLRDL instruc- ory can thus be regarded as two 16-bit-wide word tion. The data is always ‘0’ when the upper address spaces, residing side by side, each with the ‘phantom’ byte is selected (Byte Select = 1). same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. In a similar fashion, two table instructions, TBLWTH TBLRDH and TBLWTH access the space that contains the and TBLWTL, are used to write individual bytes or upper data byte. words to a Program Space address. The details of their operation are explained in Section5.0 “Flash Two table instructions are provided to move byte or Program Memory”. word-sized (16-bit) data to and from Program Space. Both function as either byte or word operations. For all table operations, the area of program memory space to be accessed is determined by the Table Page • TBLRDL (Table Read Low): register (TBLPAG). TBLPAG covers the entire program - In Word mode, this instruction maps the memory space of the device, including user application lower word of the Program Space and configuration spaces. When TBLPAG<7> = 0, the location (P<15:0>) to a data address table page is located in the user memory space. When (D<15:0>) TBLPAG<7> = 1, the page is located in configuration space. FIGURE 4-23: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. DS70000657H-page 118  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 5.0 FLASH PROGRAM MEMORY alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Note1: This data sheet summarizes the Master Clear (MCLR). This allows customers to features of the dsPIC33EPXXXGP50X, manufacture boards with unprogrammed devices and dsPIC33EPXXXMC20X/50X and then program the device just before shipping the PIC24EPXXXGP/MC20X families of product. This also allows the most recent firmware or a devices. It is not intended to be a compre- custom firmware to be programmed. hensive reference source. To complement RTSP is accomplished using TBLRD (Table Read) and the information in this data sheet, refer to TBLWT (Table Write) instructions. With RTSP, the user “Flash Programming” (DS70609) in application can write program memory data a single the “dsPIC33/PIC24 Family Reference program memory word, and erase program memory in Manual”, which is available from the blocks or ‘pages’ of 1024 instructions (3072 bytes) at a Microchip web site (www.microchip.com). time. 2: Some registers and associated bits described in this section may not be 5.1 Table Instructions and Flash available on all devices. Refer to Programming Section4.0 “Memory Organization” in this data sheet for device-specific register Regardless of the method used, all programming of and bit information. Flash memory is done with the Table Read and Table Write instructions. These allow direct read and write The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ access to the program memory space from the data 50X and PIC24EPXXXGP/MC20X devices contain memory while the device is in normal operating mode. internal Flash program memory for storing and The 24-bit target address in the program memory is executing application code. The memory is readable, formed using bits<7:0> of the TBLPAG register and the writable and erasable during normal operation over the Effective Address (EA) from a W register, specified in entire VDD range. the table instruction, as shown in Figure5-1. Flash memory can be programmed in two ways: The TBLRDL and the TBLWTL instructions are used to • In-Circuit Serial Programming™ (ICSP™) read or write to bits<15:0> of program memory. programming capability TBLRDL and TBLWTL can access program memory in • Run-Time Self-Programming (RTSP) both Word and Byte modes. ICSP allows for a dsPIC33EPXXXGP50X, The TBLRDH and TBLWTH instructions are used to read dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ or write to bits<23:16> of program memory. TBLRDH MC20X device to be serially programmed while in the and TBLWTH can also access program memory in Word end application circuit. This is done with two lines for or Byte mode. programming clock and programming data (one of the FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using 0 Program Counter 0 Program Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2011-2013 Microchip Technology Inc. DS70000657H-page 119

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 5.2 RTSP Operation 5.4 Flash Memory Resources RTSP allows the user application to erase a single Many useful resources are provided on the main prod- page of memory and to program two instruction words uct page of the Microchip web site for the devices listed at a time. See the General Purpose and Motor Control in this data sheet. This product page, which can be Family tables (Table1 and Table2, respectively) for the accessed using this link, contains the latest updates page sizes of each device. and additional information. For more information on erasing and programming Note: In the event you are not able to access the Flash memory, refer to “Flash Programming” product page using the link above, enter (DS70609) in the “dsPIC33/PIC24 Family Reference this URL in your browser: Manual”. http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464 5.3 Programming Operations 5.4.1 KEY RESOURCES A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP • “Flash Programming” (DS70609) in the mode. The processor stalls (waits) until the programming “dsPIC33/PIC24 Family Reference Manual” operation is finished. • Code Samples For erase and program times, refer to ParametersD137a • Application Notes and D137b (Page Erase Time), and D138a and • Software Libraries D138b (Word Write Cycle Time) in Table30-14 in • Webinars Section30.0 “Electrical Characteristics”. • All Related “dsPIC33/PIC24 Family Reference Setting the WR bit (NVMCON<15>) starts the opera- Manual” Sections tion and the WR bit is automatically cleared when the • Development Tools operation is finished. 5.5 Control Registers 5.3.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY Four SFRs are used to erase and write the program Flash memory: NVMCON, NVMKEY, NVMADRH and Programmers can program two adjacent words NVMADRL. (24bitsx2) of program Flash memory at a time on every other word address boundary (0x000002, The NVMCON register (Register5-1) enables and 0x000006, 0x00000A, etc.). To do this, it is necessary initiates Flash memory erase and write operations. to erase the page that contains the desired address of NVMKEY (Register5-4) is a write-only register that is the location the user wants to change. used for write protection. To start a programming or For protection against accidental operations, the write erase sequence, the user application must initiate sequence for NVMKEY must be used to allow consecutively write 0x55 and 0xAA to the NVMKEY any erase or program operation to proceed. After the register. programming command has been executed, the user There are two NVM Address registers: NVMADRH and application must wait for the programming time until NVMADRL. These two registers, when concatenated, programming is complete. The two instructions follow- form the 24-bit Effective Address (EA) of the selected ing the start of the programming sequence should be word for programming operations or the selected page NOPs. for erase operations. Refer to Flash Programming” (DS70609) in the The NVMADRH register is used to hold the upper 8 bits “dsPIC33/PIC24 Family Reference Manual” for details of the EA, while the NVMADRL register is used to hold and codes examples on programming using RTSP. the lower 16 bits of the EA. DS70000657H-page 120  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR NVMSIDL(2) — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — — — — NVMOP3(3,4) NVMOP2(3,4) NVMOP1(3,4) NVMOP0(3,4) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12 NVMSIDL: NVM Stop in Idle Control bit(2) 1 = Flash voltage regulator goes into Standby mode during Idle mode 0 = Flash voltage regulator is active during Idle mode bit 11-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,3,4) 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 0011 = Memory page erase operation 0010 = Reserved 0001 = Memory double-word program operation(5) 0000 = Reserved Note 1: These bits can only be reset on a POR. 2: If this bit is set, there will be minimal power savings (IIDLE) and upon exiting Idle mode, there is a delay (TVREG) before Flash memory becomes operational. 3: All other combinations of NVMOP<3:0> are unimplemented. 4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress. 5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.  2011-2013 Microchip Technology Inc. DS70000657H-page 121

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 5-2: NVMADRH: NONVOLATILE MEMORY ADDRESS REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMADR<23:16>: Nonvolatile Memory Write Address High bits Selects the upper 8 bits of the location to program or erase in program Flash memory. This register may be read or written by the user application. REGISTER 5-3: NVMADRL: NONVOLATILE MEMORY ADDRESS REGISTER LOW R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<15:8> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 NVMADR<15:0>: Nonvolatile Memory Write Address Low bits Selects the lower 16 bits of the location to program or erase in program Flash memory. This register may be read or written by the user application. REGISTER 5-4: NVMKEY: NONVOLATILE MEMORY KEY U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70000657H-page 122  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure6-1. Note1: This data sheet summarizes the Any active source of Reset will make the SYSRST features of the dsPIC33EPXXXGP50X, signal active. On system Reset, some of the registers dsPIC33EPXXXMC20X/50X and associated with the CPU and peripherals are forced to PIC24EPXXXGP/MC20X families of a known Reset state and some are unaffected. devices. It is not intended to be a comprehensive reference source. To com- Note: Refer to the specific peripheral section or plement the information in this data sheet, Section4.0 “Memory Organization” of refer to “Reset” (DS70602) in the this manual for register Reset states. “dsPIC33/PIC24 Family Reference Man- ual”, which is available from the Microchip All types of device Reset set a corresponding status bit web site (www.microchip.com). in the RCON register to indicate the type of Reset (see Register6-1). 2: Some registers and associated bits described in this section may not be A POR clears all the bits, except for the POR and BOR available on all devices. Refer to bits (RCON<1:0>), that are set. The user application Section4.0 “Memory Organization” in can set or clear any bit at any time during code this data sheet for device-specific register execution. The RCON bits only serve as status bits. and bit information. Setting a particular Reset status bit in software does not cause a device Reset to occur. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The The RCON register also has other bits associated with following is a list of device Reset sources: the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections • POR: Power-on Reset of this manual. • BOR: Brown-out Reset Note: The status bits in the RCON register • MCLR: Master Clear Pin Reset should be cleared after they are read so • SWR: RESET Instruction that the next RCON register value after a • WDTO: Watchdog Timer Time-out Reset device Reset is meaningful. • CM: Configuration Mismatch Reset For all Resets, the default clock source is determined • TRAPR: Trap Conflict Reset by the FNOSC<2:0> bits in the FOSCSEL Configura- • IOPUWR: Illegal Condition Device Reset tion register. The value of the FNOSC<2:0> bits is - Illegal Opcode Reset loaded into NOSC<2:0> (OSCCON<10:8>) on Reset, - Uninitialized W Register Reset which in turn, initializes the system clock. - Security Reset FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR Internal Regulator SYSRST VDD VDD Rise POR Detect Trap Conflict Illegal Opcode Uninitialized W Register Security Reset Configuration Mismatch  2011-2013 Microchip Technology Inc. DS70000657H-page 123

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 6.1 Reset Resources 6.1.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Reset” (DS70602) in the “dsPIC33/PIC24 uct page of the Microchip web site for the devices listed Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464 DS70000657H-page 124  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R E GISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — VREGSF — CM VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or Uninitialized W register Reset has not occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11 VREGSF: Flash Voltage Regulator Standby During Sleep bit 1 = Flash voltage regulator is active during Sleep 0 = Flash voltage regulator goes into Standby mode during Sleep bit 10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has occurred. 0 = A Configuration Mismatch Reset has not occurred bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software RESET (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2011-2013 Microchip Technology Inc. DS70000657H-page 125

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70000657H-page 126  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 7.0 INTERRUPT CONTROLLER 7.1 Interrupt Vector Table The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ Note1: This data sheet summarizes the 50X and PIC24EPXXXGP/MC20X Interrupt Vector features of the dsPIC33EPXXXGP50X, Table (IVT), shown in Figure7-1, resides in program dsPIC33EPXXXMC20X/50X and memory starting at location, 000004h. The IVT PIC24EPXXXGP/MC20X families of contains seven non-maskable trap vectors and up to devices. It is not intended to be a 246 sources of interrupt. In general, each interrupt comprehensive reference source. To source has its own vector. Each interrupt vector complement the information in this data contains a 24-bit-wide address. The value programmed sheet, refer to “Interrupts” (DS70600) in into each interrupt vector location is the starting the “dsPIC33/PIC24 Family Reference address of the associated Interrupt Service Routine Manual”, which is available from the (ISR). Microchip web site (www.microchip.com). Interrupt vectors are prioritized in terms of their natural 2: Some registers and associated bits priority. This priority is linked to their position in the described in this section may not be vector table. Lower addresses generally have a higher available on all devices. Refer to natural priority. For example, the interrupt associated Section4.0 “Memory Organization” in with Vector 0 takes priority over interrupts at any other this data sheet for device-specific register vector address. and bit information. The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 7.2 Reset Sequence 50X and PIC24EPXXXGP/MC20X interrupt controller reduces the numerous peripheral interrupt request sig- A device Reset is not a true exception because the nals to a single interrupt request signal to the interrupt controller is not involved in the Reset process. dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ and PIC24EPXXXGP/MC20X CPU. 50X and PIC24EPXXXGP/MC20X devices clear their registers in response to a Reset, which forces the PC The interrupt controller has the following features: to zero. The device then begins program execution at • Up to eight processor exceptions and software location, 0x000000. A GOTO instruction at the Reset traps address can redirect program execution to the • Eight user-selectable priority levels appropriate start-up routine. • Interrupt Vector Table (IVT) with a unique vector Note: Any unimplemented or unused vector for each interrupt or exception source locations in the IVT should be • Fixed priority within a specified user priority level programmed with the address of a default • Fixed interrupt entry and return latencies interrupt handler routine that contains a RESET instruction.  2011-2013 Microchip Technology Inc. DS70000657H-page 127

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 7-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X INTERRUPT VECTOR TABLE Reset – GOTO Instruction 0x000000 y orit Reset – GOTO Address 0x000002 Pri Oscillator Fail Trap Vector 0x000004 er Address Error Trap Vector 0x000006 d r O Generic Hard Trap Vector 0x000008 ral Stack Error Trap Vector 0x00000A u at Math Error Trap Vector 0x00000C N g DMAC Error Trap Vector 0x00000E n si Generic Soft Trap Vector 0x000010 a e cr Reserved 0x000012 e D Interrupt Vector 0 0x000014 T Interrupt Vector 1 0x000016 V I : : : : : : Interrupt Vector 52 0x00007C Interrupt Vector 53 0x00007E Interrupt Vector 54 0x000080 See Table7-1 for : : Interrupt Vector Details : : : : Interrupt Vector 116 0x0000FC Interrupt Vector 117 0x0000FE Interrupt Vector 118 0x000100 Interrupt Vector 119 0x000102 Interrupt Vector 120 0x000104 : : : : : : Interrupt Vector 244 0x0001FC Interrupt Vector 245 0x0001FE START OF CODE 0x000200 DS70000657H-page 128  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 7-1: INTERRUPT VECTOR DETAILS Interrupt Bit Location Vector IRQ Interrupt Source IVT Address # # Flag Enable Priority Highest Natural Order Priority INT0 – External Interrupt 0 8 0 0x000014 IFS0<0> IEC0<0> IPC0<2:0> IC1 – Input Capture 1 9 1 0x000016 IFS0<1> IEC0<1> IPC0<6:4> OC1 – Output Compare 1 10 2 0x000018 IFS0<2> IEC0<2> IPC0<10:8> T1 – Timer1 11 3 0x00001A IFS0<3> IEC0<3> IPC0<14:12> DMA0 – DMA Channel 0 12 4 0x00001C IFS0<4> IEC0<4> IPC1<2:0> IC2 – Input Capture 2 13 5 0x00001E IFS0<5> IEC0<5> IPC1<6:4> OC2 – Output Compare 2 14 6 0x000020 IFS0<6> IEC0<6> IPC1<10:8> T2 – Timer2 15 7 0x000022 IFS0<7> IEC0<7> IPC1<14:12> T3 – Timer3 16 8 0x000024 IFS0<8> IEC0<8> IPC2<2:0> SPI1E – SPI1 Error 17 9 0x000026 IFS0<9> IEC0<9> IPC2<6:4> SPI1 – SPI1 Transfer Done 18 10 0x000028 IFS0<10> IEC0<10> IPC2<10:8> U1RX – UART1 Receiver 19 11 0x00002A IFS0<11> IEC0<11> IPC2<14:12> U1TX – UART1 Transmitter 20 12 0x00002C IFS0<12> IEC0<12> IPC3<2:0> AD1 – ADC1 Convert Done 21 13 0x00002E IFS0<13> IEC0<13> IPC3<6:4> DMA1 – DMA Channel 1 22 14 0x000030 IFS0<14> IEC0<14> IPC3<10:8> Reserved 23 15 0x000032 — — — SI2C1 – I2C1 Slave Event 24 16 0x000034 IFS1<0> IEC1<0> IPC4<2:0> MI2C1 – I2C1 Master Event 25 17 0x000036 IFS1<1> IEC1<1> IPC4<6:4> CM – Comparator Combined Event 26 18 0x000038 IFS1<2> IEC1<2> IPC4<10:8> CN – Input Change Interrupt 27 19 0x00003A IFS1<3> IEC1<3> IPC4<14:12> INT1 – External Interrupt 1 28 20 0x00003C IFS1<4> IEC1<4> IPC5<2:0> Reserved 29-31 21-23 0x00003E-0x000042 — — — DMA2 – DMA Channel 2 32 24 0x000044 IFS1<8> IEC1<8> IPC6<2:0> OC3 – Output Compare 3 33 25 0x000046 IFS1<9> IEC1<9> IPC6<6:4> OC4 – Output Compare 4 34 26 0x000048 IFS1<10> IEC1<10> IPC6<10:8> T4 – Timer4 35 27 0x00004A IFS1<11> IEC1<11> IPC6<14:12> T5 – Timer5 36 28 0x00004C IFS1<12> IEC1<12> IPC7<2:0> INT2 – External Interrupt 2 37 29 0x00004E IFS1<13> IEC1<13> IPC7<6:4> U2RX – UART2 Receiver 38 30 0x000050 IFS1<14> IEC1<14> IPC7<10:8> U2TX – UART2 Transmitter 39 31 0x000052 IFS1<15> IEC1<15> IPC7<14:12> SPI2E – SPI2 Error 40 32 0x000054 IFS2<0> IEC2<0> IPC8<2:0> SPI2 – SPI2 Transfer Done 41 33 0x000056 IFS2<1> IEC2<1> IPC8<6:4> C1RX – CAN1 RX Data Ready(1) 42 34 0x000058 IFS2<2> IEC2<2> IPC8<10:8> C1 – CAN1 Event(1) 43 35 0x00005A IFS2<3> IEC2<3> IPC8<14:12> DMA3 – DMA Channel 3 44 36 0x00005C IFS2<4> IEC2<4> IPC9<2:0> IC3 – Input Capture 3 45 37 0x00005E IFS2<5> IEC2<5> IPC9<6:4> IC4 – Input Capture 4 46 38 0x000060 IFS2<6> IEC2<6> IPC9<10:8> Reserved 47-56 39-48 0x000062-0x000074 — — — SI2C2 – I2C2 Slave Event 57 49 0x000076 IFS3<1> IEC3<1> IPC12<6:4> MI2C2 – I2C2 Master Event 58 50 0x000078 IFS3<2> IEC3<2> IPC12<10:8> Reserved 59-64 51-56 0x00007A-0x000084 — — — PSEM – PWM Special Event Match(2) 65 57 0x000086 IFS3<9> IEC3<9> IPC14<6:4> Note 1: This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. 2: This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.  2011-2013 Microchip Technology Inc. DS70000657H-page 129

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED) Interrupt Bit Location Vector IRQ Interrupt Source IVT Address # # Flag Enable Priority QEI1 – QEI1 Position Counter Compare(2) 66 58 0x000088 IFS3<10> IEC3<10> IPC14<10:8> Reserved 67-72 59-64 0x00008A-0x000094 — — — U1E – UART1 Error Interrupt 73 65 0x000096 IFS4<1> IEC4<1> IPC16<6:4> U2E – UART2 Error Interrupt 74 66 0x000098 IFS4<2> IEC4<2> IPC16<10:8> CRC–CRC Generator Interrupt 75 67 0x00009A IFS4<3> IEC4<3> IPC16<14:12> Reserved 76-77 68-69 0x00009C-0x00009E — — — C1TX – CAN1 TX Data Request(1) 78 70 0x000A0 IFS4<6> IEC4<6> IPC17<10:8> Reserved 79-84 71-76 0x0000A2-0x0000AC — — — CTMU – CTMU Interrupt 85 77 0x0000AE IFS4<13> IEC4<13> IPC19<6:4> Reserved 86-101 78-93 0x0000B0-0x0000CE — — — PWM1 – PWM Generator 1(2) 102 94 0x0000D0 IFS5<14> IEC5<14> IPC23<10:8> PWM2 – PWM Generator 2(2) 103 95 0x0000D2 IFS5<15> IEC5<15> IPC23<14:12> PWM3 – PWM Generator 3(2) 104 96 0x0000D4 IFS6<0> IEC6<0> IPC24<2:0> Reserved 105-149 97-141 0x0001D6-0x00012E — — — ICD–ICD Application 150 142 0x000142 IFS8<14> IEC8<14> IPC35<10:8> JTAG – JTAG Programming 151 143 0x000130 IFS8<15> IEC8<15> IPC35<14:12> Reserved 152 144 0x000134 — — — PTGSTEP – PTG Step 153 145 0x000136 IFS9<1> IEC9<1> IPC36<6:4> PTGWDT – PTG Watchdog Time-out 154 146 0x000138 IFS9<2> IEC9<2> IPC36<10:8> PTG0 – PTG Interrupt 0 155 147 0x00013A IFS9<3> IEC9<3> IPC36<14:12> PTG1 – PTG Interrupt 1 156 148 0x00013C IFS9<4> IEC9<4> IPC37<2:0> PTG2 – PTG Interrupt 2 157 149 0x00013E IFS9<5> IEC9<5> IPC37<6:4> PTG3 – PTG Interrupt 3 158 150 0x000140 IFS9<6> IEC9<6> IPC37<10:8> Reserved 159-245 151-245 0x000142-0x0001FE — — — Lowest Natural Order Priority Note 1: This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. 2: This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. DS70000657H-page 130  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 7.3 Interrupt Resources 7.4.2 IFSx Many useful resources are provided on the main prod- The IFSx registers maintain all of the interrupt request uct page of the Microchip web site for the devices listed flags. Each source of interrupt has a status bit, which is in this data sheet. This product page, which can be set by the respective peripherals or external signal and accessed using this link, contains the latest updates is cleared via software. and additional information. 7.4.3 IECx Note: In the event you are not able to access the The IECx registers maintain all of the interrupt enable product page using the link above, enter bits. These control bits are used to individually enable this URL in your browser: interrupts from the peripherals or external signals. http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464 7.4.4 IPCx 7.3.1 KEY RESOURCES The IPCx registers are used to set the Interrupt Priority Level (IPL) for each source of interrupt. Each user • “Interrupts” (DS70600) in the “dsPIC33/PIC24 interrupt source can be assigned to one of eight priority Family Reference Manual” levels. • Code Samples 7.4.5 INTTREG • Application Notes • Software Libraries The INTTREG register contains the associated • Webinars interrupt vector number and the new CPU Interrupt Priority Level, which are latched into the Vector • All Related “dsPIC33/PIC24 Family Reference Number bits (VECNUM<7:0>) and Interrupt Priority Manual” Sections Level bits (ILR<3:0>) fields in the INTTREG register. • Development Tools The new Interrupt Priority Level is the priority of the pending interrupt. 7.4 Interrupt Control and Status The interrupt sources are assigned to the IFSx, IECx Registers and IPCx registers in the same sequence as they are dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X listed in Table7-1. For example, the INT0 (External and PIC24EPXXXGP/MC20X devices implement the Interrupt 0) is shown as having Vector Number 8 and a following registers for the interrupt controller: natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IP • INTCON1 bits in the first position of IPC0 (IPC0<2:0>). • INTCON2 • INTCON3 7.4.6 STATUS/CONTROL REGISTERS • INTCON4 Although these registers are not specifically part of the • INTTREG interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. 7.4.1 INTCON1 THROUGH INTCON4 For more information on these registers refer to “CPU” Global interrupt control functions are controlled from (DS70359) in the “dsPIC33/PIC24 Family Reference INTCON1, INTCON2, INTCON3 and INTCON4. Manual”. INTCON1 contains the Interrupt Nesting Disable bit • The CPU STATUS Register, SR, contains the (NSTDIS), as well as the control and status flags for the IPL<2:0> bits (SR<7:5>). These bits indicate the processor trap sources. current CPU Interrupt Priority Level. The user software can change the current CPU Interrupt The INTCON2 register controls external interrupt Priority Level by writing to the IPLx bits. request signal behavior and also contains the Global • The CORCON register contains the IPL3 bit Interrupt Enable bit (GIE). which, together with IPL<2:0>, also indicates the INTCON3 contains the status flags for the DMA and DO current CPU priority level. IPL3 is a read-only bit stack overflow status trap sources. so that trap events cannot be masked by the user The INTCON4 register contains the software software. generated hard trap status bit (SGHT). All Interrupt registers are described in Register7-3 through Register7-7 in the following pages.  2011-2013 Microchip Technology Inc. DS70000657H-page 131

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 7-1: SR: CPU STATUS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0>(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register3-1. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1. DS70000657H-page 132  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 VAR — US1 US0 EDT DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 VAR: Variable Exception Processing Latency Control bit 1 = Variable exception processing is enabled 0 = Fixed exception processing is enabled bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less Note 1: For complete register details, see Register3-2. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.  2011-2013 Microchip Technology Inc. DS70000657H-page 133

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR(1) OVBERR(1) COVAERR(1) COVBERR(1) OVATE(1) OVBTE(1) COVTE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR(1) DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit(1) 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit(1) 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit(1) 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit(1) 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit(1) 1 = Trap overflow of Accumulator A 0 = Trap is disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit(1) 1 = Trap overflow of Accumulator B 0 = Trap is disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit(1) 1 = Trap on catastrophic overflow of Accumulator A or B is enabled 0 = Trap is disabled bit 7 SFTACERR: Shift Accumulator Error Status bit(1) 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Divide-by-Zero Error Status bit 1 = Math error trap was caused by a divide-by-zero 0 = Math error trap was not caused by a divide-by-zero bit 5 DMACERR: DMAC Trap Flag bit 1 = DMAC trap has occurred 0 = DMAC trap has not occurred Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. DS70000657H-page 134  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 4 MATHERR: Math Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.  2011-2013 Microchip Technology Inc. DS70000657H-page 135

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 GIE DISI SWTRAP — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 GIE: Global Interrupt Enable bit 1 = Interrupts and associated IE bits are enabled 0 = Interrupts are disabled, but traps are still enabled bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13 SWTRAP: Software Trap Status bit 1 = Software trap is enabled 0 = Software trap is disabled bit 12-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS70000657H-page 136  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 7-5: INTCON3: INTERRUPT CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — DAE DOOVR — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 DAE: DMA Address Error Soft Trap Status bit 1 = DMA address error soft trap has occurred 0 = DMA address error soft trap has not occurred bit 4 DOOVR: DO Stack Overflow Soft Trap Status bit 1 = DO stack overflow soft trap has occurred 0 = DO stack overflow soft trap has not occurred bit 3-0 Unimplemented: Read as ‘0’ REGISTER 7-6: INTCON4: INTERRUPT CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SGHT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 SGHT: Software Generated Hard Trap Status bit 1 = Software generated hard trap has occurred 0 = Software generated hard trap has not occurred  2011-2013 Microchip Technology Inc. DS70000657H-page 137

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 7-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VECNUM7 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7-0 VECNUM<7:0>: Vector Number of Pending Interrupt bits 11111111 = 255, Reserved; do not use • • • 00001001 = 9, IC1 – Input Capture 1 00001000 = 8, INT0 – External Interrupt 0 00000111 = 7, Reserved; do not use 00000110 = 6, Generic soft error trap 00000101 = 5, DMAC error trap 00000100 = 4, Math error trap 00000011 = 3, Stack error trap 00000010 = 2, Generic hard trap 00000001 = 1, Address error trap 00000000 = 0, Oscillator fail trap DS70000657H-page 138  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 8.0 DIRECT MEMORY ACCESS The DMA Controller transfers data between Peripheral (DMA) Data registers and Data Space SRAM In addition, DMA can access the entire data memory Note1: This data sheet summarizes the space. The Data Memory Bus Arbiter is utilized when features of the dsPIC33EPXXXGP50X, either the CPU or DMA attempts to access SRAM, dsPIC33EPXXXMC20X/50X and resulting in potential DMA or CPU stalls. PIC24EPXXXGP/MC20X families of The DMA Controller supports 4 independent channels. devices. It is not intended to be a Each channel can be configured for transfers to or from comprehensive reference source. To selected peripherals. Some of the peripherals complement the information in this data supported by the DMA Controller include: sheet, refer to “Direct Memory Access (DMA)” (DS70348) in the “dsPIC33/ • ECAN™ PIC24 Family Reference Manual”, which • Analog-to-Digital Converter (ADC) is available from the Microchip web site • Serial Peripheral Interface (SPI) (www.microchip.com). • UART 2: Some registers and associated bits • Input Capture described in this section may not be • Output Compare available on all devices. Refer to Section4.0 “Memory Organization” in Refer to Table8-1 for a complete list of supported this data sheet for device-specific register peripherals. and bit information. FIGURE 8-1: DMA CONTROLLER MODULE Data Memory PERIPHERAL DMA Arbiter (see Figure4-18) SRAM  2011-2013 Microchip Technology Inc. DS70000657H-page 139

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X In addition, DMA transfers can be triggered by timers • Peripheral Indirect Addressing mode (peripheral as well as external interrupts. Each DMA channel is generates destination address) unidirectional. Two DMA channels must be allocated to • CPU interrupt after half or full block read and write to a peripheral. If more than one channel transfer complete receives a request to transfer data, a simple fixed • Byte or word transfers priority scheme based on channel number, dictates • Fixed priority channel arbitration which channel completes the transfer and which • Manual (software) or automatic (peripheral DMA channel, or channels, are left pending. Each DMA channel moves a block of data, after which, it generates requests) transfer initiation an interrupt to the CPU to indicate that the block is • One-Shot or Auto-Repeat Block Transfer modes available for processing. • Ping-Pong mode (automatic switch between two SRAM start addresses after each block transfer is The DMA Controller provides these functional complete) capabilities: • DMA request for each channel can be selected • Four DMA channels from any supported interrupt source • Register Indirect with Post-Increment • Debug support features Addressing mode The peripherals that can utilize DMA are listed in • Register Indirect without Post-Increment Table8-1. Addressing mode TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS DMAxPAD Register DMAxPAD Register DMAxREQ Register Peripheral to DMA Association (Values to Read from (Values to Write to IRQSEL<7:0> Bits Peripheral) Peripheral) INT0 – External Interrupt 0 00000000 — — IC1 – Input Capture 1 00000001 0x0144 (IC1BUF) — IC2 – Input Capture 2 00000101 0x014C (IC2BUF) — IC3 – Input Capture 3 00100101 0x0154 (IC3BUF) — IC4 – Input Capture 4 00100110 0x015C (IC4BUF) — OC1 – Output Compare 1 00000010 — 0x0906 (OC1R) 0x0904 (OC1RS) OC2 – Output Compare 2 00000110 — 0x0910 (OC2R) 0x090E (OC2RS) OC3 – Output Compare 3 00011001 — 0x091A (OC3R) 0x0918 (OC3RS) OC4 – Output Compare 4 00011010 — 0x0924 (OC4R) 0x0922 (OC4RS) TMR2 – Timer2 00000111 — — TMR3 – Timer3 00001000 — — TMR4 – Timer4 00011011 — — TMR5 – Timer5 00011100 — — SPI1 Transfer Done 00001010 0x0248 (SPI1BUF) 0x0248 (SPI1BUF) SPI2 Transfer Done 00100001 0x0268 (SPI2BUF) 0x0268 (SPI2BUF) UART1RX – UART1 Receiver 00001011 0x0226 (U1RXREG) — UART1TX – UART1 Transmitter 00001100 — 0x0224 (U1TXREG) UART2RX – UART2 Receiver 00011110 0x0236 (U2RXREG) — UART2TX – UART2 Transmitter 00011111 — 0x0234 (U2TXREG) ECAN1 – RX Data Ready 00100010 0x0440 (C1RXD) — ECAN1 – TX Data Request 01000110 — 0x0442 (C1TXD) ADC1 – ADC1 Convert Done 00001101 0x0300 (ADC1BUF0) — DS70000657H-page 140  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 8-2: DMA CONTROLLER BLOCK DIAGRAM SRAM Peripheral Indirect Address DMA Controller DMA IRQ to DMA Arbiter MAntrol ChDaMnnAels PerRipehaedryal 1 anCdo Innttreorllreurp t Do Modules C 0 1 2 3 CPU DMA DMA X-Bus CPU Peripheral X-Bus CPU DMA CPU DMA Non-DMA DMA DMA CPU Peripheral Ready Ready Peripheral 2 Peripheral 3 IRQ to DMA and IRQ to DMA and Interrupt Controller Interrupt Controller Modules Modules Note: CPU and DMA address buses are not shown for clarity. 8.1 DMA Resources 8.2 DMAC Registers Many useful resources are provided on the main prod- Each DMAC Channel x (where x = 0 through 3) uct page of the Microchip web site for the devices listed contains the following registers: in this data sheet. This product page, which can be • 16-Bit DMA Channel Control register (DMAxCON) accessed using this link, contains the latest updates • 16-Bit DMA Channel IRQ Select register (DMAxREQ) and additional information. • 32-Bit DMA RAM Primary Start Address register Note: In the event you are not able to access the (DMAxSTA) product page using the link above, enter • 32-Bit DMA RAM Secondary Start Address register this URL in your browser: (DMAxSTB) http://www.microchip.com/wwwproducts/ • 16-Bit DMA Peripheral Address register (DMAxPAD) Devices.aspx?dDocName=en555464 • 14-Bit DMA Transfer Count register (DMAxCNT) 8.1.1 KEY RESOURCES Additional status registers (DMAPWC, DMARQC, DMAPPS, DMALCA and DSADR) are common to all • Section 22. “Direct Memory Access (DMA)” DMAC channels. These status registers provide infor- (DS70348) in the “dsPIC33/PIC24 Family mation on write and request collisions, as well as on Reference Manual” last address and channel access information. • Code Samples The interrupt flags (DMAxIF) are located in an IFSx • Application Notes register in the interrupt controller. The corresponding • Software Libraries interrupt enable control bits (DMAxIE) are located in • Webinars an IECx register in the interrupt controller, and the • All Related “dsPIC33/PIC24 Family Reference corresponding interrupt priority control bits (DMAxIP) Manual” Sections are located in an IPCx register in the interrupt • Development Tools controller.  2011-2013 Microchip Technology Inc. DS70000657H-page 141

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 8-1: DMAXCON: DMA CHANNEL X CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — AMODE1 AMODE0 — — MODE1 MODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: DMA Channel Enable bit 1 = Channel is enabled 0 = Channel is disabled bit 14 SIZE: DMA Data Transfer Size bit 1 = Byte 0 = Word bit 13 DIR: DMA Transfer Direction bit (source/destination bus select) 1 = Reads from RAM address, writes to peripheral address 0 = Reads from peripheral address, writes to RAM address bit 12 HALF: DMA Block Transfer Interrupt Select bit 1 = Initiates interrupt when half of the data has been moved 0 = Initiates interrupt when all of the data has been moved bit 11 NULLW: Null Data Peripheral Write Mode Select bit 1 = Null data write to peripheral in addition to RAM write (DIR bit must also be clear) 0 = Normal operation bit 10-6 Unimplemented: Read as ‘0’ bit 5-4 AMODE<1:0>: DMA Channel Addressing Mode Select bits 11 = Reserved 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA buffer) 10 = Continuous, Ping-Pong modes are enabled 01 = One-Shot, Ping-Pong modes are disabled 00 = Continuous, Ping-Pong modes are disabled DS70000657H-page 142  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 8-2: DMAXREQ: DMA CHANNEL X IRQ SELECT REGISTER R/S-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQSEL7 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Transfer bit(1) 1 = Forces a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request bit 14-8 Unimplemented: Read as ‘0’ bit 7-0 IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits 01000110 = ECAN1 – TX Data Request(2) 00100110 = IC4 – Input Capture 4 00100101 = IC3 – Input Capture 3 00100010 = ECAN1 – RX Data Ready(2) 00100001 = SPI2 Transfer Done 00011111 = UART2TX – UART2 Transmitter 00011110 = UART2RX – UART2 Receiver 00011100 = TMR5 – Timer5 00011011 = TMR4 – Timer4 00011010 = OC4 – Output Compare 4 00011001 = OC3 – Output Compare 3 00001101 = ADC1 – ADC1 Convert done 00001100 = UART1TX – UART1 Transmitter 00001011 = UART1RX – UART1 Receiver 00001010 = SPI1 – Transfer Done 00001000 = TMR3 – Timer3 00000111 = TMR2 – Timer2 00000110 = OC2 – Output Compare 2 00000101 = IC2 – Input Capture 2 00000010 = OC1 – Output Compare 1 00000001 = IC1 – Input Capture 1 00000000 = INT0 – External Interrupt 0 Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the forced DMA transfer is complete or the channel is disabled (CHEN = 0). 2: This selection is available in dsPIC33EPXXXGP/MC50X devices only.  2011-2013 Microchip Technology Inc. DS70000657H-page 143

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 8-3: DMAXSTAH: DMA CHANNEL X START ADDRESS REGISTER A (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 STA<23:16>: Primary Start Address bits (source or destination) REGISTER 8-4: DMAXSTAL: DMA CHANNEL X START ADDRESS REGISTER A (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STA<15:0>: Primary Start Address bits (source or destination) DS70000657H-page 144  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 8-5: DMAXSTBH: DMA CHANNEL X START ADDRESS REGISTER B (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 STB<23:16>: Secondary Start Address bits (source or destination) REGISTER 8-6: DMAXSTBL: DMA CHANNEL X START ADDRESS REGISTER B (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STB<15:0>: Secondary Start Address bits (source or destination)  2011-2013 Microchip Technology Inc. DS70000657H-page 145

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 8-7: DMAXPAD: DMA CHANNEL X PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PAD<15:0>: Peripheral Address Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 8-8: DMAXCNT: DMA CHANNEL X TRANSFER COUNT REGISTER(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CNT<13:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 CNT<13:0>: DMA Transfer Count Register bits(2) Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: The number of DMA transfers = CNT<13:0> + 1. DS70000657H-page 146  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 8-9: DSADRH: DMA MOST RECENT RAM HIGH ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 DSADR<23:16>: Most Recent DMA Address Accessed by DMA bits REGISTER 8-10: DSADRL: DMA MOST RECENT RAM LOW ADDRESS REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits  2011-2013 Microchip Technology Inc. DS70000657H-page 147

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 PWCOL3: DMA Channel 3 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 2 PWCOL2: DMA Channel 2 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 1 PWCOL1: DMA Channel 1 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 0 PWCOL0: DMA Channel 0 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected DS70000657H-page 148  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — RQCOL3 RQCOL2 RQCOL1 RQCOL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 RQCOL3: DMA Channel 3 Transfer Request Collision Flag bit 1 = User force and interrupt-based request collision is detected 0 = No request collision is detected bit 2 RQCOL2: DMA Channel 2 Transfer Request Collision Flag bit 1 = User force and interrupt-based request collision is detected 0 = No request collision is detected bit 1 RQCOL1: DMA Channel 1 Transfer Request Collision Flag bit 1 = User force and interrupt-based request collision is detected 0 = No request collision is detected bit 0 RQCOL0: DMA Channel 0 Transfer Request Collision Flag bit 1 = User force and interrupt-based request collision is detected 0 = No request collision is detected  2011-2013 Microchip Technology Inc. DS70000657H-page 149

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1 — — — — LSTCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 LSTCH<3:0>: Last DMAC Channel Active Status bits 1111 = No DMA transfer has occurred since system Reset 1110 = Reserved • • • 0100 = Reserved 0011 = Last data transfer was handled by Channel 3 0010 = Last data transfer was handled by Channel 2 0001 = Last data transfer was handled by Channel 1 0000 = Last data transfer was handled by Channel 0 DS70000657H-page 150  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 PPST3: DMA Channel 3 Ping-Pong Mode Status Flag bit 1 = DMASTB3 register is selected 0 = DMASTA3 register is selected bit 2 PPST2: DMA Channel 2 Ping-Pong Mode Status Flag bit 1 = DMASTB2 register is selected 0 = DMASTA2 register is selected bit 1 PPST1: DMA Channel 1 Ping-Pong Mode Status Flag bit 1 = DMASTB1 register is selected 0 = DMASTA1 register is selected bit 0 PPST0: DMA Channel 0 Ping-Pong Mode Status Flag bit 1 = DMASTB0 register is selected 0 = DMASTA0 register is selected  2011-2013 Microchip Technology Inc. DS70000657H-page 151

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 152  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 9.0 OSCILLATOR CONFIGURATION The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X oscillator system Note1: This data sheet summarizes the provides: features of the dsPIC33EPXXXGP50X, • On-chip Phase-Locked Loop (PLL) to boost dsPIC33EPXXXMC20X/50X and internal operating frequency on select internal and PIC24EPXXXGP/MC20X families of external oscillator sources devices. It is not intended to be a compre- • On-the-fly clock switching between various clock hensive reference source. To complement sources the information in this data sheet, refer to • Doze mode for system power savings “Oscillator” (DS70580) in the “dsPIC33/ • Fail-Safe Clock Monitor (FSCM) that detects clock PIC24 Family Reference Manual”, which is failure and permits safe application recovery or available from the Microchip web site shutdown (www.microchip.com). • Configuration bits for clock source selection 2: Some registers and associated bits A simplified diagram of the oscillator system is shown described in this section may not be in Figure9-1. available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 9-1: OSCILLATOR SYSTEM DIAGRAM DOZE<2:0> Primary Oscillator OSC1 POSCCLK XT, HS, EC S2 S3 XTPLL, HSPLL, ECPLL, ZE FCY(2) S1 PLL(1) FRCPLL, FPLLO S1/S3 DO OSC2 POSCMD<1:0> FP(2) ÷ 2 V FRC FRCCLK DI FRCDIVN FOSC Oscillator C S7 R F FRCDIV<2:0> TUN<5:0> FRCDIV16 Reference Clock Generation ÷ 16 S6 POSCCLK FRC REFCLKO S0 ÷ N FOSC RPn LPRC LPRC S5 Oscillator ROSEL RODIV<3:0> COSC<2:0> Clock Fail Clock Switch Reset WDT, PWRT, 0b000 NOSC<2:0> FNOSC<2:0> FSCM Note 1: See Figure9-2 for PLL details. 2: The term, FP, refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used with a doze ratio of 1:2 or lower.  2011-2013 Microchip Technology Inc. DS70000657H-page 153

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 9.1 CPU Clocking System Instruction execution speed or device operating frequency, FCY, is given by Equation9-1. The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ 50X and PIC24EPXXXGP/MC20X family of devices EQUATION 9-1: DEVICE OPERATING provides six system clock options: FREQUENCY • Fast RC (FRC) Oscillator FCY = Fosc/2 • FRC Oscillator with Phase Locked Loop (PLL) • FRC Oscillator with Postscaler Figure9-2 is a block diagram of the PLL module. • Primary (XT, HS or EC) Oscillator Equation9-2 provides the relationship between input • Primary Oscillator with PLL frequency (FIN) and output frequency (FPLLO). In clock • Low-Power RC (LPRC) Oscillator modes S1 and S3, when the PLL output is selected, FOSC = FPLLO. Equation9-3 provides the relationship between input frequency (FIN) and VCO frequency (FVCO). FIGURE 9-2: PLL BLOCK DIAGRAM 0.8 MHz < FPLLI(1) < 8.0 MHz FPLLO(1)  120 MHz @ +125ºC 120 MHZ < FVCO(1) < 340 MHZ FPLLO(1)  140 MHz @ +85ºC FIN FPLLI FVCO FPLLO ÷ N1 PFD VCO ÷ N2 To FOSC clock multiplexer PLLPRE<4:0> PLLPOST<1:0> ÷ M PLLDIV<8:0> Note 1: This frequency range must be met at all times. EQUATION 9-2: FPLLO CALCULATION  M   PLLDIV+2  FPLLO = FIN --------------------- = FIN ---------------------------------------------------------------------------------------- N1N2 PLLPRE+22PLLPOST+1 Where: N1 = PLLPRE + 2 N2 = 2 x (PLLPOST + 1) M = PLLDIV + 2 EQUATION 9-3: FVCO CALCULATION M PLLDIV+2 Fvco = FIN ------- = FIN ------------------------------------- N1 PLLPRE+2 DS70000657H-page 154  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION See Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Notes Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator (FRC) with Divide-by-N and Internal xx 001 1 PLL (FRCPLL) Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. 9.2 Oscillator Resources 9.2.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Oscillator” (DS70580) in the “dsPIC33/PIC24 uct page of the Microchip web site for the devices listed Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2013 Microchip Technology Inc. DS70000657H-page 155

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 9.3 Oscillator Control Registers REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y — COSC2 COSC1 COSC0 — NOSC2(2) NOSC1(2) NOSC0(2) bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0 CLKLOCK IOLOCK LOCK — CF(3) — — OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 111 = Fast RC Oscillator (FRC) with Divide-by-n 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 111 = Fast RC Oscillator (FRC) with Divide-by-n 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7 CLKLOCK: Clock Lock Enable bit 1 = If (FCKSM0=1), then clock and PLL configurations are locked; if (FCKSM0=0), then clock and PLL configurations may be modified 0 = Clock and PLL selections are not locked, configurations may be modified bit 6 IOLOCK: I/O Lock Enable bit 1 = I/O lock is active 0 = I/O lock is not active bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator” (DS70580) in the “dsPIC33/ PIC24 Family Reference Manual” (available from the Microchip web site) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes. 3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an actual oscillator failure and trigger an oscillator failure trap. DS70000657H-page 156  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit(3) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Requests oscillator switch to selection specified by the NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator” (DS70580) in the “dsPIC33/ PIC24 Family Reference Manual” (available from the Microchip web site) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes. 3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an actual oscillator failure and trigger an oscillator failure trap.  2011-2013 Microchip Technology Inc. DS70000657H-page 157

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE2(1) DOZE1(1) DOZE0(1) DOZEN(2,3) FRCDIV2 FRCDIV1 FRCDIV0 bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(1) 111 = FCY divided by 128 110 = FCY divided by 64 101 = FCY divided by 32 100 = FCY divided by 16 011 = FCY divided by 8 (default) 010 = FCY divided by 4 001 = FCY divided by 2 000 = FCY divided by 1 bit 11 DOZEN: Doze Mode Enable bit(2,3) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock and peripheral clock ratio is forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 000 = FRC divided by 1 (default) bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 11 = Output divided by 8 10 = Reserved 01 = Output divided by 4 (default) 00 = Output divided by 2 bit 5 Unimplemented: Read as ‘0’ Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to DOZE<2:0> are ignored. 2: This bit is cleared when the ROI bit is set and an interrupt occurs. 3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to set the DOZEN bit is ignored. DS70000657H-page 158  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED) bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler) 11111 = Input divided by 33 • • • 00001 = Input divided by 3 00000 = Input divided by 2 (default) Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to DOZE<2:0> are ignored. 2: This bit is cleared when the ROI bit is set and an interrupt occurs. 3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to set the DOZEN bit is ignored.  2011-2013 Microchip Technology Inc. DS70000657H-page 159

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV8 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV7 PLLDIV6 PLLDIV5 PLLDIV4 PLLDIV3 PLLDIV2 PLLDIV1 PLLDIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • • • 000110000 = 50 (default) • • • 000000010 = 4 000000001 = 3 000000000 = 2 DS70000657H-page 160  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Maximum frequency deviation of 1.453% (7.477 MHz) 011110 = Center frequency + 1.406% (7.474 MHz)    000001 = Center frequency + 0.047% (7.373 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.047% (7.367 MHz)    100001 = Center frequency – 1.453% (7.263 MHz) 100000 = Minimum frequency deviation of -1.5% (7.259 MHz)  2011-2013 Microchip Technology Inc. DS70000657H-page 161

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 9-5: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL RODIV3(1) RODIV2(1) RODIV1(1) RODIV0(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is enabled on the REFCLK pin(2) 0 = Reference oscillator output is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Run in Sleep bit 1 = Reference oscillator output continues to run in Sleep 0 = Reference oscillator output is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Oscillator crystal is used as the reference clock 0 = System clock is used as the reference clock bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1) 1111 = Reference clock divided by 32,768 1110 = Reference clock divided by 16,384 1101 = Reference clock divided by 8,192 1100 = Reference clock divided by 4,096 1011 = Reference clock divided by 2,048 1010 = Reference clock divided by 1,024 1001 = Reference clock divided by 512 1000 = Reference clock divided by 256 0111 = Reference clock divided by 128 0110 = Reference clock divided by 64 0101 = Reference clock divided by 32 0100 = Reference clock divided by 16 0011 = Reference clock divided by 8 0010 = Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock bit 7-0 Unimplemented: Read as ‘0’ Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits. 2: This pin is remappable. See Section11.4 “Peripheral Pin Select (PPS)” for more information. DS70000657H-page 162  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 10.0 POWER-SAVING FEATURES 10.1 Clock Frequency and Clock Switching Note1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ dsPIC33EPXXXMC20X/50X and 50X and PIC24EPXXXGP/MC20X devices allow a PIC24EPXXXGP/MC20X families of wide range of clock frequencies to be selected under devices. It is not intended to be a compre- application control. If the system clock configuration is hensive reference source. To complement not locked, users can choose low-power or high- the information in this data sheet, refer to precision oscillators by simply changing the NOSCx “Watchdog Timer and Power-Saving bits (OSCCON<10:8>). The process of changing a Modes” (DS70615) in the “dsPIC33/ system clock during operation, as well as limitations to PIC24 Family Reference Manual”, which the process, are discussed in more detail in is available from the Microchip web site Section9.0 “Oscillator Configuration”. (www.microchip.com). 10.2 Instruction-Based Power-Saving 2: Some registers and associated bits described in this section may not be Modes available on all devices. Refer to The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ Section4.0 “Memory Organization” in 50X and PIC24EPXXXGP/MC20X devices have two this data sheet for device-specific register special power-saving modes that are entered and bit information. through the execution of a special PWRSAV The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ instruction. Sleep mode stops clock operation and 50X and PIC24EPXXXGP/MC20X devices provide halts all code execution. Idle mode halts the CPU the ability to manage power consumption by and code execution, but allows peripheral modules selectively managing clocking to the CPU and the to continue operation. The assembler syntax of the peripherals. In general, a lower clock frequency and PWRSAV instruction is shown in Example10-1. a reduction in the number of peripherals being Note: SLEEP_MODE and IDLE_MODE are con- clocked constitutes lower consumed power. stants defined in the assembler include dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X file for the selected device. and PIC24EPXXXGP/MC20X devices can manage Sleep and Idle modes can be exited as a result of an power consumption in four ways: enabled interrupt, WDT time-out or a device Reset. When • Clock Frequency the device exits these modes, it is said to “wake-up”. • Instruction-Based Sleep and Idle modes • Software-Controlled Doze mode • Selective Peripheral Control in Software Combinations of these methods can be used to selec- tively tailor an application’s power consumption while still maintaining critical application features, such as timing-sensitive communications. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into Sleep mode PWRSAV #IDLE_MODE ; Put the device into Idle mode  2011-2013 Microchip Technology Inc. DS70000657H-page 163

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 10.2.1 SLEEP MODE 10.2.2 IDLE MODE The following occurs in Sleep mode: The following occurs in Idle mode: • The system clock source is shut down. If an • The CPU stops executing instructions. on-chip oscillator is used, it is turned off. • The WDT is automatically cleared. • The device current consumption is reduced to a • The system clock source remains active. By minimum, provided that no I/O pin is sourcing default, all peripheral modules continue to operate current. normally from the system clock source, but can • The Fail-Safe Clock Monitor does not operate, also be selectively disabled (see Section10.4 since the system clock source is disabled. “Peripheral Module Disable”). • The LPRC clock continues to run in Sleep mode if • If the WDT or FSCM is enabled, the LPRC also the WDT is enabled. remains active. • The WDT, if enabled, is automatically cleared The device wakes from Idle mode on any of these prior to entering Sleep mode. events: • Some device features or peripherals can continue • Any interrupt that is individually enabled to operate. This includes items such as the Input • Any device Reset Change Notification (ICN) on the I/O ports or • A WDT time-out peripherals that use an external clock input. • Any peripheral that requires the system clock On wake-up from Idle mode, the clock is reapplied to source for its operation is disabled. the CPU and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the The device wakes up from Sleep mode on any of these PWRSAV instruction or the first instruction in the events: Interrupt Service Routine (ISR). • Any interrupt source that is individually enabled All peripherals also have the option to discontinue • Any form of device Reset operation when Idle mode is entered to allow for • A WDT time-out increased power savings. This option is selectable in the control register of each peripheral; for example, the On wake-up from Sleep mode, the processor restarts TSIDL bit in the Timer1 Control register (T1CON<13>). with the same clock source that was active when Sleep mode was entered. 10.2.3 INTERRUPTS COINCIDENT WITH For optimal power savings, the internal regulator and POWER SAVE INSTRUCTIONS the Flash regulator can be configured to go into Any interrupt that coincides with the execution of a Standby when Sleep mode is entered by clearing the PWRSAV instruction is held off until entry into Sleep or VREGS (RCON<8>) and VREGSF (RCON<11>) bits Idle mode has completed. The device then wakes up (default configuration). from Sleep or Idle mode. If the application requires a faster wake-up time, and can accept higher current requirements, the VREGS (RCON<8>) and VREGSF (RCON<11>) bits can be set to keep the internal regulator and the Flash regulator active during Sleep mode. DS70000657H-page 164  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 10.3 Doze Mode 10.4 Peripheral Module Disable The preferred strategies for reducing power consumption The Peripheral Module Disable (PMD) registers are changing clock speed and invoking one of the power- provide a method to disable a peripheral module by saving modes. In some circumstances, this cannot be stopping all clock sources supplied to that module. practical. For example, it may be necessary for an When a peripheral is disabled using the appropriate application to maintain uninterrupted synchronous PMD control bit, the peripheral is in a minimum power communication, even while it is doing nothing else. consumption state. The control and status registers Reducing system clock speed can introduce associated with the peripheral are also disabled, so communication errors, while using a power-saving mode writes to those registers do not have effect and read can stop communications completely. values are invalid. Doze mode is a simple and effective alternative method A peripheral module is enabled only if both the to reduce power consumption while the device is still associated bit in the PMD register is cleared and the executing code. In this mode, the system clock peripheral is supported by the specific dsPIC® DSC continues to operate from the same source and at the variant. If the peripheral is present in the device, it is same speed. Peripheral modules continue to be enabled in the PMD register by default. clocked at the same speed, while the CPU clock speed Note: If a PMD bit is set, the corresponding is reduced. Synchronization between the two clock module is disabled after a delay of one domains is maintained, allowing the peripherals to instruction cycle. Similarly, if a PMD bit is access the SFRs while the CPU executes code at a cleared, the corresponding module is slower rate. enabled after a delay of one instruction Doze mode is enabled by setting the DOZEN bit cycle (assuming the module control regis- (CLKDIV<11>). The ratio between peripheral and core ters are already configured to enable clock speed is determined by the DOZE<2:0> bits module operation). (CLKDIV<14:12>). There are eight possible configu- rations, from 1:1 to 1:128, with 1:1 being the default 10.5 Power-Saving Resources setting. Programs can use Doze mode to selectively reduce Many useful resources are provided on the main prod- power consumption in event-driven applications. This uct page of the Microchip web site for the devices listed allows clock-sensitive functions, such as synchronous in this data sheet. This product page, which can be communications, to continue without interruption while accessed using this link, contains the latest updates the CPU Idles, waiting for something to invoke an and additional information. interrupt routine. An automatic return to full-speed CPU Note: In the event you are not able to access the operation on interrupts can be enabled by setting the product page using the link above, enter ROI bit (CLKDIV<15>). By default, interrupt events this URL in your browser: have no effect on Doze mode operation. http://www.microchip.com/wwwproducts/ For example, suppose the device is operating at Devices.aspx?dDocName=en555464 20MIPS and the ECAN™ module has been configured for 500 kbps, based on this device operating speed. If 10.5.1 KEY RESOURCES the device is placed in Doze mode with a clock fre- • “Watchdog Timer and Power-Saving Modes” quency ratio of 1:4, the ECAN module continues to (DS70615) in the “dsPIC33/PIC24 Family communicate at the required bit rate of 500 kbps, but Reference Manual” the CPU now starts executing instructions at a • Code Samples frequency of 5 MIPS. • Application Notes • Software Libraries • Webinars • All Related “dsPIC33/PIC24 Family Reference Manual” Sections • Development Tools  2011-2013 Microchip Technology Inc. DS70000657H-page 165

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 T5MD T4MD T3MD T2MD T1MD QEI1MD(1) PWMMD(1) — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD(2) AD1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T5MD: Timer5 Module Disable bit 1 = Timer5 module is disabled 0 = Timer5 module is enabled bit 14 T4MD: Timer4 Module Disable bit 1 = Timer4 module is disabled 0 = Timer4 module is enabled bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10 QEI1MD: QEI1 Module Disable bit(1) 1 = QEI1 module is disabled 0 = QEI1 module is enabled bit 9 PWMMD: PWM Module Disable bit(1) 1 = PWM module is disabled 0 = PWM module is enabled bit 8 Unimplemented: Read as ‘0’ bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 U2MD: UART2 Module Disable bit 1 = UART2 module is disabled 0 = UART2 module is enabled bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. DS70000657H-page 166  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 Unimplemented: Read as ‘0’ bit 1 C1MD: ECAN1 Module Disable bit(2) 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.  2011-2013 Microchip Technology Inc. DS70000657H-page 167

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — IC4MD IC3MD IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 IC4MD: Input Capture 4 Module Disable bit 1 = Input Capture 4 module is disabled 0 = Input Capture 4 module is enabled bit 10 IC3MD: Input Capture 3 Module Disable bit 1 = Input Capture 3 module is disabled 0 = Input Capture 3 module is enabled bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70000657H-page 168  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CMPMD — — bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 CRCMD — — — — — I2C2MD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Comparator Module Disable bit 1 = Comparator module is disabled 0 = Comparator module is enabled bit 9-8 Unimplemented: Read as ‘0’ bit 7 CRCMD: CRC Module Disable bit 1 = CRC module is disabled 0 = CRC module is enabled bit 6-2 Unimplemented: Read as ‘0’ bit 1 I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled bit 0 Unimplemented: Read as ‘0’ REGISTER 10-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 — — — — REFOMD CTMUMD — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 REFOMD: Reference Clock Module Disable bit 1 = Reference clock module is disabled 0 = Reference clock module is enabled bit 2 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled 0 = CTMU module is enabled bit 1-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS70000657H-page 169

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 10-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PWM3MD(1) PWM2MD(1) PWM1MD(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 PWM3MD: PWM3 Module Disable bit(1) 1 = PWM3 module is disabled 0 = PWM3 module is enabled bit 9 PWM2MD: PWM2 Module Disable bit(1) 1 = PWM2 module is disabled 0 = PWM2 module is enabled bit 8 PWM1MD: PWM1 Module Disable bit(1) 1 = PWM1 module is disabled 0 = PWM1 module is enabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is available on dsPIC33EPXXXMC50X/20X and PIC24EPXXXMC20X devices only. DS70000657H-page 170  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 10-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 DMA0MD(1) DMA1MD(1) — — — PTGMD — — — DMA2MD(1) DMA3MD(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 DMA0MD: DMA0 Module Disable bit(1) 1 = DMA0 module is disabled 0 = DMA0 module is enabled DMA1MD: DMA1 Module Disable bit(1) 1 = DMA1 module is disabled 0 = DMA1 module is enabled DMA2MD: DMA2 Module Disable bit(1) 1 = DMA2 module is disabled 0 = DMA2 module is enabled DMA3MD: DMA3 Module Disable bit(1) 1 = DMA3 module is disabled 0 = DMA3 module is enabled bit 3 PTGMD: PTG Module Disable bit 1 = PTG module is disabled 0 = PTG module is enabled bit 2-0 Unimplemented: Read as ‘0’ Note 1: This single bit enables and disables all four DMA channels.  2011-2013 Microchip Technology Inc. DS70000657H-page 171

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 172  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 11.0 I/O PORTS has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in Note1: This data sheet summarizes the which a port’s digital output can drive the input of a features of the dsPIC33EPXXXGP50X, peripheral that shares the same pin. Figure11-1 dsPIC33EPXXXMC20X/50X and illustrates how ports are shared with other peripherals PIC24EPXXXGP/MC20X families of and the associated I/O pin to which they are connected. devices. It is not intended to be a compre- When a peripheral is enabled and the peripheral is hensive reference source. To complement actively driving an associated pin, the use of the pin as a the information in this data sheet, refer to general purpose output pin is disabled. The I/O pin can “I/O Ports” (DS70598) in the “dsPIC33/ PIC24 Family Reference Manual”, which be read, but the output driver for the parallel port bit is is available from the Microchip web site disabled. If a peripheral is enabled, but the peripheral is (www.microchip.com). not actively driving a pin, that pin can be driven by a port. 2: Some registers and associated bits All port pins have eight registers directly associated with described in this section may not be their operation as digital I/O. The Data Direction register available on all devices. Refer to (TRISx) determines whether the pin is an input or an out- Section4.0 “Memory Organization” in put. If the data direction bit is a ‘1’, then the pin is an input. this data sheet for device-specific register All port pins are defined as inputs after a Reset. Reads and bit information. from the Latch register (LATx) read the latch. Writes to the Latch write the latch. Reads from the port (PORTx) read Many of the device pins are shared among the peripher- the port pins, while writes to the port pins write the latch. als and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. Any bit and its associated data and control registers that are not valid for a particular device is disabled. This means the corresponding LATx and TRISx 11.1 Parallel I/O (PIO) Ports registers and the port pin are read as zeros. Generally, a parallel I/O port that shares a pin with a When a pin is shared with another peripheral or peripheral is subservient to the peripheral. The function that is defined as an input only, it is peripheral’s output buffer data and control signals are nevertheless regarded as a dedicated port because provided to a pair of multiplexers. The multiplexers there is no other competing source of outputs. select whether the peripheral or the associated port FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + CK WR Port Data Latch Read LAT Input Data Read Port  2011-2013 Microchip Technology Inc. DS70000657H-page 173

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 11.1.1 OPEN-DRAIN CONFIGURATION 11.3 Input Change Notification (ICN) In addition to the PORTx, LATx and TRISx registers The Input Change Notification function of the I/O ports for data control, port pins can also be individually allows devices to generate interrupt requests to the configured for either digital or open-drain output. This processor in response to a Change-of-State (COS) on is controlled by the Open-Drain Control register, selected input pins. This feature can detect input ODCx, associated with each port. Setting any of the Change-of-States even in Sleep mode, when the clocks bits configures the corresponding pin to act as an are disabled. Every I/O port pin can be selected open-drain output. (enabled) for generating an interrupt request on a The open-drain feature allows the generation of Change-of-State. outputs other than VDD by using external pull-up Three control registers are associated with the Change resistors. The maximum open-drain voltage allowed Notification (CN) functionality of each I/O port. The on any pin is the same as the maximum VIH CNENx registers contain the CN interrupt enable con- specification for that particular pin. trol bits for each of the input pins. Setting any of these See the “Pin Diagrams” section for the available bits enables a CN interrupt for the corresponding pins. 5Vtolerant pins and Table30-11 for the maximum Each I/O pin also has a weak pull-up and a weak VIH specification for each pin. pull-down connected to it. The pull-ups and pull- downs act as a current source or sink source 11.2 Configuring Analog and Digital connected to the pin and eliminate the need for Port Pins external resistors when push button, or keypad devices are connected. The pull-ups and pull-downs The ANSELx register controls the operation of the are enabled separately, using the CNPUx and the analog port pins. The port pins that are to function as CNPDx registers, which contain the control bits for analog inputs or outputs must have their corresponding each of the pins. Setting any of the control bits ANSELx and TRISx bits set. In order to use port pins for enables the weak pull-ups and/or pull-downs for the I/O functionality with digital modules, such as Timers, corresponding pins. UARTs, etc., the corresponding ANSELx bit must be cleared. Note: Pull-ups and pull-downs on Change Noti- fication pins should always be disabled The ANSELx register has a default value of 0xFFFF; when the port pin is configured as a digital therefore, all pins that share analog functions are output. analog (not digital) by default. Pins with analog functions affected by the ANSELx EXAMPLE 11-1: PORT WRITE/READ registers are listed with a buffer type of analog in the EXAMPLE Pinout I/O Descriptions (see Table1-1). MOV 0xFF00, W0 ; Configure PORTB<15:8> If the TRISx bit is cleared (output) while the ANSELx bit ; as inputs is set, the digital output level (VOH or VOL) is converted MOV W0, TRISB ; and PORTB<7:0> by an analog peripheral, such as the ADC module or ; as outputs comparator module. NOP ; Delay 1 cycle When the PORTx register is read, all pins configured as BTSS PORTB, #13 ; Next Instruction analog input channels are read as cleared (a low level). Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. 11.2.1 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be a NOP, as shown in Example11-1. DS70000657H-page 174  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 11.4 Peripheral Pin Select (PPS) In comparison, some digital-only peripheral modules are never included in the Peripheral Pin Select feature. A major challenge in general purpose devices is provid- This is because the peripheral’s function requires ing the largest possible set of peripheral features while special I/O circuitry on a specific port and cannot be minimizing the conflict of features on I/O pins. The easily connected to multiple pins. These modules challenge is even greater on low pin count devices. In include I2C™ and the PWM. A similar requirement an application where more than one peripheral needs excludes all modules with analog inputs, such as the to be assigned to a single pin, inconvenient work- ADC Converter. arounds in application code, or a complete redesign, A key difference between remappable and non- may be the only option. remappable peripherals is that remappable peripherals Peripheral Pin Select configuration provides an are not associated with a default I/O pin. The peripheral alternative to these choices by enabling peripheral set must always be assigned to a specific I/O pin before it selection and their placement on a wide range of I/O can be used. In contrast, non-remappable peripherals pins. By increasing the pinout options available on a are always available on a default pin, assuming that the particular device, users can better tailor the device to peripheral is active and not conflicting with another their entire application, rather than trimming the peripheral. application to fit the device. When a remappable peripheral is active on a given I/O The Peripheral Pin Select configuration feature oper- pin, it takes priority over all other digital I/O and digital ates over a fixed subset of digital I/O pins. Users may communication peripherals associated with the pin. independently map the input and/or output of most dig- Priority is given regardless of the type of peripheral that ital peripherals to any one of these I/O pins. Hardware is mapped. Remappable peripherals never take priority safeguards are included that prevent accidental or over any analog functions associated with the pin. spurious changes to the peripheral mapping once it has been established. 11.4.3 CONTROLLING PERIPHERAL PIN SELECT 11.4.1 AVAILABLE PINS Peripheral Pin Select features are controlled through The number of available pins is dependent on the two sets of SFRs: one to map peripheral inputs and one particular device and its pin count. Pins that support the to map outputs. Because they are separately con- Peripheral Pin Select feature include the label, “RPn” or trolled, a particular peripheral’s input and output (if the “RPIn”, in their full pin designation, where “n” is the peripheral has both) can be placed on any selectable remappable pin number. “RP” is used to designate pins function pin without constraint. that support both remappable input and output functions, while “RPI” indicates pins that support The association of a peripheral to a peripheral- remappable input functions only. selectable pin is handled in two different ways, depending on whether an input or output is being 11.4.2 AVAILABLE PERIPHERALS mapped. The peripherals managed by the Peripheral Pin Select are all digital-only peripherals. These include general serial communications (UART and SPI), general pur- pose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs.  2011-2013 Microchip Technology Inc. DS70000657H-page 175

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 11.4.4 INPUT MAPPING 11.4.4.1 Virtual Connections The inputs of the Peripheral Pin Select options are dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X mapped on the basis of the peripheral. That is, a control and PIC24EPXXXGP/MC20X devices support virtual register associated with a peripheral dictates the pin it (internal) connections to the output of the op amp/ will be mapped to. The RPINRx registers are used to comparator module (see Figure25-1 in Section25.0 configure peripheral input mapping (see Register11-1 “Op Amp/Comparator Module”), and the PTG through Register11-17). Each register contains sets of module (see Section24.0 “Peripheral Trigger 7-bit fields, with each set associated with one of the Generator (PTG) Module”). remappable peripherals. Programming a given periph- In addition, dsPIC33EPXXXMC20X/50X and eral’s bit field with an appropriate 7-bit value maps the PIC24EPXXXMC20X devices support virtual connec- RPn pin with the corresponding value to that peripheral. tions to the filtered QEI module inputs: FINDX1, For any given device, the valid range of values for any FHOME1, FINDX2 and FHOME2 (see Figure17-1 bit field corresponds to the maximum number of in Section17.0 “Quadrature Encoder Interface Peripheral Pin Selections supported by the device. (QEI) Module (dsPIC33EPXXXMC20X/50X and For example, Figure11-2 illustrates remappable pin PIC24EPXXXMC20X Devices Only)”. selection for the U1RX input. Virtual connections provide a simple way of inter- peripheral connection without utilizing a physical pin. FIGURE 11-2: REMAPPABLE INPUT FOR For example, by setting the FLT1R<6:0> bits of the U1RX RPINR12 register to the value of ‘b0000001, the output of the analog comparator, C1OUT, will be U1RXR<6:0> connected to the PWM Fault 1 input, which allows the analog comparator to trigger PWM Faults without the 0 use of an actual physical pin on the device. RP0 Virtual connection to the QEI module allows 1 peripherals to be connected to the QEI digital filter RP1 input. To utilize this filter, the QEI module must be U1RX Input 2 to Peripheral enabled and its inputs must be connected to a physical RPn pin. Example11-2 illustrates how the input RP3 capture module can be connected to the QEI digital filter. n RPn Note: For input only, Peripheral Pin Select func- tionality does not have priority over TRISx settings. Therefore, when configuring an RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to ‘1’). EXAMPLE 11-2: CONNECTING IC1 TO THE HOME1 QEI1 DIGITAL FILTER INPUT ON PIN 43 OF THE dsPIC33EPXXXMC206 DEVICE RPINR15 = 0x2500; /* Connect the QEI1 HOME1 input to RP37 (pin 43) */ RPINR7 = 0x009; /* Connect the IC1 input to the digital filter on the FHOME1 input */ QEI1IOC = 0x4000; /* Enable the QEI digital filter */ QEI1CON = 0x8000; /* Enable the QEI module */ DS70000657H-page 176  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name(1) Function Name Register Configuration Bits External Interrupt 1 INT1 RPINR0 INT1R<6:0> External Interrupt 2 INT2 RPINR1 INT2R<6:0> Timer2 External Clock T2CK RPINR3 T2CKR<6:0> Input Capture 1 IC1 RPINR7 IC1R<6:0> Input Capture 2 IC2 RPINR7 IC2R<6:0> Input Capture 3 IC3 RPINR8 IC3R<6:0> Input Capture 4 IC4 RPINR8 IC4R<6:0> Output Compare Fault A OCFA RPINR11 OCFAR<6:0> PWM Fault 1(3) FLT1 RPINR12 FLT1R<6:0> PWM Fault 2(3) FLT2 RPINR12 FLT2R<6:0> QEI1 Phase A(3) QEA1 RPINR14 QEA1R<6:0> QEI1 Phase B(3) QEB1 RPINR14 QEB1R<6:0> QEI1 Index(3) INDX1 RPINR15 INDX1R<6:0> QEI1 Home(3) HOME1 RPINR15 HOM1R<6:0> UART1 Receive U1RX RPINR18 U1RXR<6:0> UART2 Receive U2RX RPINR19 U2RXR<6:0> SPI2 Data Input SDI2 RPINR22 SDI2R<6:0> SPI2 Clock Input SCK2 RPINR22 SCK2R<6:0> SPI2 Slave Select SS2 RPINR23 SS2R<6:0> CAN1 Receive(2) C1RX RPINR26 C1RXR<6:0> PWM Sync Input 1(3) SYNCI1 RPINR37 SYNCI1R<6:0> PWM Dead-Time Compensation 1(3) DTCMP1 RPINR38 DTCMP1R<6:0> PWM Dead-Time Compensation 2(3) DTCMP2 RPINR39 DTCMP2R<6:0> PWM Dead-Time Compensation 3(3) DTCMP3 RPINR39 DTCMP3R<6:0> Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. 2: This input source is available on dsPIC33EPXXXGP/MC50X devices only. 3: This input source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.  2011-2013 Microchip Technology Inc. DS70000657H-page 177

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES Peripheral Pin Peripheral Pin Input/ Input/ Select Input Pin Assignment Select Input Pin Assignment Output Output Register Value Register Value 000 0000 I VSS 010 1101 I RPI45 000 0001 I C1OUT(1) 010 1110 I RPI46 000 0010 I C2OUT(1) 010 1111 I RPI47 000 0011 I C3OUT(1) 011 0000 — — 000 0100 I C4OUT(1) 011 0001 — — 000 0101 — — 011 0010 — — 000 0110 I PTGO30(1) 011 0011 I RPI51 000 0111 I PTGO31(1) 011 0100 I RPI52 000 1000 I FINDX1(1,2) 011 0101 I RPI53 000 1001 I FHOME1(1,2) 011 0110 I/O RP54 000 1010 — — 011 0111 I/O RP55 000 1011 — — 011 1000 I/O RP56 000 1100 — — 011 1001 I/O RP57 000 1101 — — 011 1010 I RPI58 000 1110 — — 011 1011 — — 000 1111 — — 011 1100 — — 001 0000 — — 011 1101 — — 001 0001 — — 011 1110 — — 001 0010 — — 011 1111 — — 001 0011 — — 100 0000 — — 001 0100 I/O RP20 100 0001 — — 001 0101 — — 100 0010 — — 001 0110 — — 100 0011 — — 001 0111 — — 100 0100 — — 001 1000 I RPI24 100 0101 — — 001 1001 I RPI25 100 0110 — — 001 1010 — — 100 0111 — — 001 1011 I RPI27 100 1000 — — 001 1100 I RPI28 100 1001 — — 001 1101 — — 100 1010 — — 001 1110 — — 100 1011 — — 001 1111 — — 100 1100 — — 010 0000 I RPI32 100 1101 — — 010 0001 I RPI33 100 1110 — — 010 0010 I RPI34 100 1111 — — 010 0011 I/O RP35 101 0000 — — 010 0100 I/O RP36 101 0001 — — 010 0101 I/O RP37 101 0010 — — 010 0110 I/O RP38 101 0011 — — 010 0111 I/O RP39 101 0100 — — Legend: Shaded rows indicate PPS Input register values that are unimplemented. Note 1: See Section11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment. 2: These inputs are available on dsPIC33EPXXXGP/MC50X devices only. DS70000657H-page 178  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES (CONTINUED) Peripheral Pin Peripheral Pin Input/ Input/ Select Input Pin Assignment Select Input Pin Assignment Output Output Register Value Register Value 010 1000 I/O RP40 101 0101 — — 010 1001 I/O RP41 101 0110 — — 010 1010 I/O RP42 101 0111 — — 010 1011 I/O RP43 101 1000 — — 010 1100 I RPI44 101 1001 — — 101 1010 — — 110 1101 — — 101 1011 — — 110 1110 — — 101 1100 — — 110 1111 — — 101 1101 — — 111 0000 — — 101 1110 I RPI94 111 0001 — — 101 1111 I RPI95 111 0010 — — 110 0000 I RPI96 111 0011 — — 110 0001 I/O RP97 111 0100 — — 110 0010 — — 111 0101 — — 110 0011 — — 111 0110 I/O RP118 110 0100 — — 111 0111 I RPI119 110 0101 — — 111 1000 I/O RP120 110 0110 — — 111 1001 I RPI121 110 0111 — — 111 1010 — — 110 1000 — — 111 1011 — — 110 1001 — — 111 1100 — — 110 1010 — — 111 1101 — — 110 1011 — — 111 1110 — — 110 1100 — — 111 1111 — — Legend: Shaded rows indicate PPS Input register values that are unimplemented. Note 1: See Section11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment. 2: These inputs are available on dsPIC33EPXXXGP/MC50X devices only.  2011-2013 Microchip Technology Inc. DS70000657H-page 179

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 11.4.4.2 Output Mapping FIGURE 11-3: MULTIPLEXING REMAPPABLE OUTPUT FOR RPn In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In RPxR<5:0> this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Default 0 Like the RPINRx registers, each register contains sets U1TX Output of 6-bit fields, with each set associated with one RPn 1 pin (see Register11-18 through Register11-27). The SDO2 Output 2 value of the bit field corresponds to one of the periph- RPn erals and that peripheral’s output is mapped to the pin Output Data (see Table11-3 and Figure11-3). A null output is associated with the output register QEI1CCMP Output Reset value of ‘0’. This is done to ensure that remap- 48 pable outputs remain disconnected from all output pins REFCLKO Output by default. 49 11.4.4.3 Mapping Limitations The control schema of the peripheral select pins is not lim- ited to a small range of fixed peripheral configurations. There are no mutual or hardware-enforced lockouts between any of the peripheral mapping SFRs. Literally any combination of peripheral mappings across any or all of the RPn pins is possible. This includes both many-to- one and one-to-many mappings of peripheral inputs and outputs to pins. While such mappings may be technically possible from a configuration point of view, they may not be supportable from an electrical point of view. TABLE 11-3: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn) Function RPxR<5:0> Output Name Default PORT 000000 RPn tied to Default Pin U1TX 000001 RPn tied to UART1 Transmit U2TX 000011 RPn tied to UART2 Transmit SDO2 001000 RPn tied to SPI2 Data Output SCK2 001001 RPn tied to SPI2 Clock Output SS2 001010 RPn tied to SPI2 Slave Select C1TX(2) 001110 RPn tied to CAN1 Transmit OC1 010000 RPn tied to Output Compare 1 Output OC2 010001 RPn tied to Output Compare 2 Output OC3 010010 RPn tied to Output Compare 3 Output OC4 010011 RPn tied to Output Compare 4 Output C1OUT 011000 RPn tied to Comparator Output 1 C2OUT 011001 RPn tied to Comparator Output 2 C3OUT 011010 RPn tied to Comparator Output 3 SYNCO1(1) 101101 RPn tied to PWM Primary Time Base Sync Output QEI1CCMP(1) 101111 RPn tied to QEI 1 Counter Comparator Output REFCLKO 110001 RPn tied to Reference Clock Output C4OUT 110010 RPn tied to Comparator Output 4 Note 1: This function is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: This function is available in dsPIC33EPXXXGP/MC50X devices only. DS70000657H-page 180  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 11.5 I/O Helpful Tips 5. When driving LEDs directly, the I/O pin can source or sink more current than what is specified in the 1. In some cases, certain pins, as defined in VOH/IOH and VOL/IOL DC characteristic specifica- Table30-11, under “Injection Current”, have inter- tion. The respective IOH and IOL current rating only nal protection diodes to VDD and VSS. The term, applies to maintaining the corresponding output at “Injection Current”, is also referred to as “Clamp or above the VOH, and at or below the VOL levels. Current”. On designated pins, with sufficient exter- However, for LEDs, unlike digital inputs of an nal current-limiting precautions by the user, I/O pin externally connected device, they are not gov- input voltages are allowed to be greater or less erned by the same minimum VIH/VIL levels. An I/O than the data sheet absolute maximum ratings, pin output can safely sink or source any current with respect to the VSS and VDD supplies. Note less than that listed in the absolute maximum that when the user application forward biases rating section of this data sheet. For example: either of the high or low side internal input clamp diodes, that the resulting current being injected VOH = 2.4V @ IOH = -8 mA and VDD = 3.3V into the device, that is clamped internally by the The maximum output current sourced by any 8mA VDD and VSS power rails, may affect the ADC I/O pin = 12 mA. accuracy by four to six counts. LED source current < 12 mA is technically 2. I/O pins that are shared with any analog input pin permitted. Refer to the VOH/IOH graphs in (i.e., ANx) are always analog pins by default after Section30.0 “Electrical Characteristics” for any Reset. Consequently, configuring a pin as an additional information. analog input pin automatically disables the digital 6. The Peripheral Pin Select (PPS) pin mapping rules input pin buffer and any attempt to read the digital are as follows: input level by reading PORTx or LATx will always a) Only one “output” function can be active on a return a ‘0’, regardless of the digital logic level on given pin at any time, regardless if it is a ded- the pin. To use a pin as a digital I/O pin on a shared icated or remappable function (one pin, one ANx pin, the user application needs to configure the output). Analog Pin Configuration registers in the I/O ports b) It is possible to assign a “remappable output” module (i.e., ANSELx) by setting the appropriate bit function to multiple pins and externally short or that corresponds to that I/O port pin to a ‘0’. tie them together for increased current drive. Note: Although it is not possible to use a digital c) If any “dedicated output” function is enabled input pin when its analog function is on a pin, it will take precedence over any enabled, it is possible to use the digital I/O remappable “output” function. output function, TRISx = 0x0, while the d) If any “dedicated digital” (input or output) func- analog function is also enabled. However, tion is enabled on a pin, any number of “input” this is not recommended, particularly if the remappable functions can be mapped to the analog input is connected to an external same pin. analog voltage source, which would e) If any “dedicated analog” function(s) are create signal contention between the analog signal and the output pin driver. enabled on a given pin, “digital input(s)” of any kind will all be disabled, although a single “dig- 3. Most I/O pins have multiple functions. Referring to ital output”, at the user’s cautionary discretion, the device pin diagrams in this data sheet, the prior- can be enabled and active as long as there is ities of the functions allocated to any pins are no signal contention with an external analog indicated by reading the pin name from left-to-right. input signal. For example, it is possible for the The left most function name takes precedence over ADC to convert the digital output logic level, or any function to its right in the naming convention. to toggle a digital output on a comparator or For example: AN16/T2CK/T7CK/RC1. This indi- ADC input provided there is no external cates that AN16 is the highest priority in this analog input, such as for a built-in self-test. example and will supersede all other functions to its f) Any number of “input” remappable functions right in the list. Those other functions to its right, can be mapped to the same pin(s) at the same even if enabled, would not work as long as any time, including to any pin with a single output other function to its left was enabled. This rule from either a dedicated or remappable “output”. applies to all of the functions listed for a given pin. 4. Each pin has an internal weak pull-up resistor and pull-down resistor that can be configured using the CNPUx and CNPDx registers, respectively. These resistors eliminate the need for external resistors in certain applications. The internal pull-up is up to ~(VDD – 0.8), not VDD. This value is still above the minimum VIH of CMOS and TTL devices.  2011-2013 Microchip Technology Inc. DS70000657H-page 181

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X g) The TRISx registers control only the digital I/O 11.6 I/O Ports Resources output buffer. Any other dedicated or remappa- ble active “output” will automatically override Many useful resources are provided on the main prod- the TRIS setting. The TRISx register does not uct page of the Microchip web site for the devices listed control the digital logic “input” buffer. Remap- in this data sheet. This product page, which can be pable digital “inputs” do not automatically accessed using this link, contains the latest updates override TRIS settings, which means that the and additional information. TRISx bit must be set to input for pins with only Note: In the event you are not able to access the remappable input function(s) assigned product page using the link above, enter h) All analog pins are enabled by default after any this URL in your browser: Reset and the corresponding digital input http://www.microchip.com/wwwproducts/ buffer on the pin has been disabled. Only the Devices.aspx?dDocName=en555464 Analog Pin Select registers control the digital input buffer, not the TRISx register. The user 11.6.1 KEY RESOURCES must disable the analog function on a pin using • “I/O Ports” (DS70598) in the “dsPIC33/PIC24 the Analog Pin Select registers in order to use Family Reference Manual” any “digital input(s)” on a corresponding pin, no • Code Samples exceptions. • Application Notes • Software Libraries • Webinars • All Related “dsPIC33/PIC24 Family Reference Manual” Sections • Development Tools DS70000657H-page 182  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 11.7 Peripheral Pin Select Registers REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INT1R<6:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 INT1R<6:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS70000657H-page 183

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INT2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 INT2R<6:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2CKR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 T2CKR<6:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70000657H-page 184  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC2R<6:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC1R<6:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2011-2013 Microchip Technology Inc. DS70000657H-page 185

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-5: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC4R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC3R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC4R<6:0>: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC3R<6:0>: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70000657H-page 186  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — OCFAR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 OCFAR<6:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2011-2013 Microchip Technology Inc. DS70000657H-page 187

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-7: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 FLT2R<6:0>: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 FLT1R<6:0>: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70000657H-page 188  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-8: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — QEB1R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — QEA1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 QEB1R<6:0>: Assign B (QEB) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 QEA1R<6:0>: Assign A (QEA) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2011-2013 Microchip Technology Inc. DS70000657H-page 189

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-9: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — HOME1R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INDX1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 HOME1R<6:0>: Assign QEI1 HOME1 (HOME1) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IND1XR<6:0>: Assign QEI1 INDEX1 (INDX1) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70000657H-page 190  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-10: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U1RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 U1RXR<6:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS REGISTER 11-11: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U2RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 U2RXR<6:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2011-2013 Microchip Technology Inc. DS70000657H-page 191

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-12: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SCK2INR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SDI2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SCK2INR<6:0>: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 SDI2R<6:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70000657H-page 192  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-13: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SS2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 SS2R<6:0>: Assign SPI2 Slave Select (SS2) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS REGISTER 11-14: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26 (dsPIC33EPXXXGP/MC50X DEVICES ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — C1RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 C1RXR<6:0>: Assign CAN1 RX Input (CRX1) to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2011-2013 Microchip Technology Inc. DS70000657H-page 193

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-15: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37 (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SYNCI1R<6:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SYNCI1R<6:0>: Assign PWM Synchronization Input 1 to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7-0 Unimplemented: Read as ‘0’ DS70000657H-page 194  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-16: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38 (dsPIC33EPXXXMC20X AND PIC24EPXXXMC20X DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP1R<6:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP1R<6:0>: Assign PWM Dead-Time Compensation Input 1 to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS70000657H-page 195

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-17: RPINR39: PERIPHERAL PIN SELECT INPUT REGISTER 39 (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP3R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP3R<6:0>: Assign PWM Dead-Time Compensation Input 3 to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 DTCMP2R<6:0>: Assign PWM Dead-Time Compensation Input 2 to the Corresponding RPn Pin bits (see Table11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70000657H-page 196  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-18: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP35R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP20R<5:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-19: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP37R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP36R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP37R<5:0>: Peripheral Output Function is Assigned to RP37 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP36R<5:0>: Peripheral Output Function is Assigned to RP36 Output Pin bits (see Table11-3 for peripheral function numbers)  2011-2013 Microchip Technology Inc. DS70000657H-page 197

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-20: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP39R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP38R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP39R<5:0>: Peripheral Output Function is Assigned to RP39 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP38R<5:0>: Peripheral Output Function is Assigned to RP38 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-21: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP41R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP40R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP41R<5:0>: Peripheral Output Function is Assigned to RP41 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP40R<5:0>: Peripheral Output Function is Assigned to RP40 Output Pin bits (see Table11-3 for peripheral function numbers) DS70000657H-page 198  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-22: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP43R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP42R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP43R<5:0>: Peripheral Output Function is Assigned to RP43 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP42R<5:0>: Peripheral Output Function is Assigned to RP42 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-23: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP55R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP54R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP55R<5:0>: Peripheral Output Function is Assigned to RP55 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP54R<5:0>: Peripheral Output Function is Assigned to RP54 Output Pin bits (see Table11-3 for peripheral function numbers)  2011-2013 Microchip Technology Inc. DS70000657H-page 199

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-24: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP57R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP56R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP57R<5:0>: Peripheral Output Function is Assigned to RP57 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP56R<5:0>: Peripheral Output Function is Assigned to RP56 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-25: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP97R<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP97R<5:0>: Peripheral Output Function is Assigned to RP97 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-0 Unimplemented: Read as ‘0’ DS70000657H-page 200  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 11-26: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP118R<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP118R<5:0>: Peripheral Output Function is Assigned to RP118 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-0 Unimplemented: Read as ‘0’ REGISTER 11-27: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP120R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 RP120R<5:0>: Peripheral Output Function is Assigned to RP120 Output Pin bits (see Table11-3 for peripheral function numbers)  2011-2013 Microchip Technology Inc. DS70000657H-page 201

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 202  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 12.0 TIMER1 The Timer1 module can operate in one of the following modes: Note1: This data sheet summarizes the • Timer mode features of the dsPIC33EPXXXGP50X, • Gated Timer mode dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of • Synchronous Counter mode devices. It is not intended to be a • Asynchronous Counter mode comprehensive reference source. To com- In Timer and Gated Timer modes, the input clock is plement the information in this data sheet, derived from the internal instruction cycle clock (FCY). refer to “Timers” (DS70362) in the In Synchronous and Asynchronous Counter modes, “dsPIC33/PIC24 Family Reference Man- the input clock is derived from the external clock input ual”, which is available from the Microchip at the T1CK pin. web site (www.microchip.com). The Timer modes are determined by the following bits: 2: Some registers and associated bits • Timer Clock Source Control bit (TCS): T1CON<1> described in this section may not be available on all devices. Refer to • Timer Synchronization Control bit (TSYNC): Section4.0 “Memory Organization” in T1CON<2> this data sheet for device-specific register • Timer Gate Control bit (TGATE): T1CON<6> and bit information. Timer control bit setting for different operating modes are given in the Table12-1. The Timer1 module is a 16-bit timer that can operate as a free-running interval timer/counter. TABLE 12-1: TIMER MODE SETTINGS The Timer1 module has the following unique features over other timers: Mode TCS TGATE TSYNC • Can be operated in Asynchronous Counter mode Timer 0 0 x from an external clock source Gated Timer 0 1 x • The external clock input (T1CK) can optionally be Synchronous 1 x 1 synchronized to the internal device clock and the Counter clock synchronization is performed after the prescaler Asynchronous 1 x 0 A block diagram of Timer1 is shown in Figure12-1. Counter FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Gate Falling Edge 1 Sync Detect Set T1IF Flag 0 FP(1) Prescaler 10 T1CLK (/n) TGATE Reset Data 00 TMR1 Latch TCKPS<1:0> 0 CLK x1 T1CK Prescaler Sync 1 Comparator Equal (/n) CTMU Edge Control TGATE Logic TSYNC TCKPS<1:0> TCS PR1 Note 1: FP is the peripheral clock.  2011-2013 Microchip Technology Inc. DS70000657H-page 203

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 12.1 Timer1 Resources 12.1.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Timers” (DS70362) in the “dsPIC33/PIC24 uct page of the Microchip web site for the devices listed Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464 DS70000657H-page 204  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 12.2 Timer1 Control Register REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC(1) TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit(1) 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit(1) When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit(1) 1 = External clock is from pin, T1CK (on the rising edge) 0 = Internal clock (FP) bit 0 Unimplemented: Read as ‘0’ Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any attempts by user software to write to the TMR1 register are ignored.  2011-2013 Microchip Technology Inc. DS70000657H-page 205

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 206  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 13.0 TIMER2/3 AND TIMER4/5 Individually, all four of the 16-bit timers can function as synchronous timers or counters. They also offer the Note1: This data sheet summarizes the features listed previously, except for the event trigger; features of the dsPIC33EPXXXGP50X, this is implemented only with Timer2/3. The operating dsPIC33EPXXXMC20X/50X and modes and enabled features are determined by setting PIC24EPXXXGP/MC20X family of the appropriate bit(s) in the T2CON, T3CON, and devices. It is not intended to be a T4CON, T5CON registers. T2CON and T4CON are comprehensive reference source. To com- shown in generic form in Register13-1. T3CON and plement the information in this data sheet, T5CON are shown in Register13-2. refer to “Timers” (DS70362) of the For 32-bit timer/counter operation, Timer2 and Timer4 “dsPIC33/PIC24 Family Reference are the least significant word (lsw); Timer3 and Timer5 Manual”, which is available from the are the most significant word (msw) of the 32-bit timers. Microchip web site (www.microchip.com). Note: For 32-bit operation, T3CON and T5CON 2: Some registers and associated bits control bits are ignored. Only T2CON and described in this section may not be T4CON control bits are used for setup and available on all devices. Refer to control. Timer2 and Timer4 clock and gate Section4.0 “Memory Organization” in inputs are utilized for the 32-bit timer this data sheet for device-specific register modules, but an interrupt is generated and bit information. with the Timer3 and Timer5 interrupt flags. The Timer2/3 and Timer4/5 modules are 32-bit timers, A block diagram for an example 32-bit timer pair (Tim- which can also be configured as four independent er2/3 and Timer4/5) is shown in Figure13-3. 16-bit timers with selectable operating modes. Note: Only Timer2, 3, 4 and 5 can trigger a DMA As 32-bit timers, Timer2/3 and Timer4/5 operate in data transfer. three modes: • Two Independent 16-Bit Timers (e.g., Timer2 and Timer3) with all 16-Bit Operating modes (except Asynchronous Counter mode) • Single 32-Bit Timer • Single 32-Bit Synchronous Counter They also support these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation during Idle and Sleep modes • Interrupt on a 32-Bit Period Register Match • Time Base for Input Capture and Output Compare Modules (Timer2 and Timer3 only) • ADC1 Event Trigger (32-bit timer pairs, and Timer3 and Timer5 only)  2011-2013 Microchip Technology Inc. DS70000657H-page 207

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2 AND 4) Gate Falling Edge 1 Sync Detect Set TxIF Flag 0 FP(1) Prescaler 10 TxCLK (/n) TGATE Reset Data 00 TMRx Latch TCKPS<1:0> CLK TxCK Prescaler Sync x1 (/n) Equal Comparator TCKPS<1:0> TGATE TCS PRx Note 1: FP is the peripheral clock. FIGURE 13-2: TYPE C TIMER BLOCK DIAGRAM (x = 3 AND 5) Gate Falling Edge 1 Sync Detect Set TxIF Flag 0 FP(1) Prescaler 10 TxCLK (/n) TGATE Reset Data 00 TMRx Latch TCKPS<1:0> CLK TxCK Prescaler Sync x1 (/n) Equal Comparator ADC Start of Conversion Trigger(2) TCKPS<1:0> TGATE TCS PRx Note 1: FP is the peripheral clock. 2: The ADC trigger is available on TMR3 and TMR5 only. DS70000657H-page 208  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 13-3: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER) Gate Falling Edge 1 Sync Detect Set TyIF Flag PRx PRy 0 TGATE Equal ADC Comparator Data FP(1) Prescaler 10 (/n) CLK lsw msw Latch Reset 00 TMRx TMRy TCKPS<1:0> TxCK Prescaler Sync x1 (/n) TMRyHLD TCKPS<1:0> TGATE TCS Data Bus<15:0> Note 1: The ADC trigger is available on the TMR3:TMR2 andTMR5:TMR4 32-bit timer pairs. 2: Timerx is a Type B timer (x = 2 and 4). 3: Timery is a Type C timer (y = 3 and 5). 13.1 Timerx/y Resources 13.1.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Timers” (DS70362) in the “dsPIC33/PIC24 uct page of the Microchip web site for the devices listed Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/ • Development Tools wwwproducts/Devices.aspx?d DocName=en555464  2011-2013 Microchip Technology Inc. DS70000657H-page 209

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 13.2 Timer Control Registers REGISTER 13-1: TxCON: (TIMER2 AND TIMER4) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When T32 = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When T32 = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timerx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit 1 = External clock is from pin, TxCK (on the rising edge) 0 = Internal clock (FP) bit 0 Unimplemented: Read as ‘0’ DS70000657H-page 210  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 13-2: TyCON: (TIMER3 AND TIMER5) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(2) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timery Stop in Idle Mode bit(2) 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(1,3) 1 = External clock is from pin, TyCK (on the rising edge) 0 = Internal clock (FP) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through TxCON. 2: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: The TyCK pin is not available on all timers. See the “Pin Diagrams” section for the available pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 211

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 212  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 14.0 INPUT CAPTURE The input capture module is useful in applications requiring frequency (period) and pulse measurement. Note1: This data sheet summarizes the The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ features of the dsPIC33EPXXXGP50X, 50X and PIC24EPXXXGP/MC20X devices support dsPIC33EPXXXMC20X/50X and four input capture channels. PIC24EPXXXGP/MC20X families of Key features of the input capture module include: devices. It is not intended to be a comprehensive reference source. To • Hardware-configurable for 32-bit operation in all complement the information in this data modes by cascading two adjacent modules sheet, refer to “Input Capture” • Synchronous and Trigger modes of output (DS70352) in the “dsPIC33/dsPIC24 compare operation, with up to 19 user-selectable Family Reference Manual”, which is Trigger/Sync sources available available from the Microchip web site • A 4-level FIFO buffer for capturing and holding (www.microchip.com). timer values for several events 2: Some registers and associated bits • Configurable interrupt generation described in this section may not be • Up to six clock sources available for each module, available on all devices. Refer to driving a separate internal 16-bit counter Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 14-1: INPUT CAPTURE x MODULE BLOCK DIAGRAM ICM<2:0> CTMU Edge ICI<1:0> Control Logic Prescaler Edge Detect Logic Event and Set ICxIF Counter and Interrupt 1:1/4/16 Clock Synchronizer Logic ICx Pin PTG Trigger ICTSEL<2:0> Input Increment 16 IC Clock Clock ICxTMR 4-Level FIFO Buffer Sources Select 16 Trigger and Trigger and Reset 16 Sync Sources Sync Logic ICxBUF SYNCSEL<4:0> Trigger(1) ICOV, ICBNE System Bus Note 1: The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for proper ICx module operation or the Trigger/Sync source must be changed to another source option.  2011-2013 Microchip Technology Inc. DS70000657H-page 213

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 14.1 Input Capture Resources 14.1.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Input Capture” (DS70352) in the “dsPIC33/ uct page of the Microchip web site for the devices listed PIC24 Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464 DS70000657H-page 214  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 14.2 Input Capture Registers REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/HC/HS-0 R/HC/HS-0 R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Stop in Idle Control bit 1 = Input capture will Halt in CPU Idle mode 0 = Input capture will continue to operate in CPU Idle mode bit 12-10 ICTSEL<2:0>: Input Capture Timer Select bits 111 = Peripheral clock (FP) is the clock source of the ICx 110 = Reserved 101 = Reserved 100 = T1CLK is the clock source of the ICx (only the synchronous clock is supported) 011 = T5CLK is the clock source of the ICx 010 = T4CLK is the clock source of the ICx 001 = T2CLK is the clock source of the ICx 000 = T3CLK is the clock source of the ICx bit 9-7 Unimplemented: Read as ‘0’ bit 6-5 ICI<1:0>: Number of Captures per Interrupt Select bits (this field is not used if ICM<2:0>=001 or 111) 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture buffer overflow occurred 0 = No input capture buffer overflow occurred bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only in CPU Sleep and Idle modes (rising edge detect only, all other control bits are not applicable) 110 = Unused (module is disabled) 101 = Capture mode, every 16th rising edge (Prescaler Capture mode) 100 = Capture mode, every 4th rising edge (Prescaler Capture mode) 011 = Capture mode, every rising edge (Simple Capture mode) 010 = Capture mode, every falling edge (Simple Capture mode) 001 = Capture mode, every edge rising and falling (Edge Detect mode (ICI<1:0>) is not used in this mode) 000 = Input capture module is turned off  2011-2013 Microchip Technology Inc. DS70000657H-page 215

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W/HS-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG(2) TRIGSTAT(3) — SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 IC32: Input Capture 32-Bit Timer Mode Select bit (Cascade mode) 1 = Odd IC and Even IC form a single 32-bit input capture module(1) 0 = Cascade module operation is disabled bit 7 ICTRIG: Input Capture Trigger Operation Select bit(2) 1 = Input source used to trigger the input capture timer (Trigger mode) 0 = Input source used to synchronize the input capture timer to a timer of another module (Synchronization mode) bit 6 TRIGSTAT: Timer Trigger Status bit(3) 1 = ICxTMR has been triggered and is running 0 = ICxTMR has not been triggered and is being held clear bit 5 Unimplemented: Read as ‘0’ Note 1: The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode. 2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register. 3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits). It can be read, set and cleared in software. 4: Do not use the ICx module as its own Sync or Trigger source. 5: This option should only be selected as a trigger source and not as a synchronization source. 6: Each Input Capture x (ICx) module has one PTG input source. See Section24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO8 = IC1 PTGO9 = IC2 PTGO10 = IC3 PTGO11 = IC4 DS70000657H-page 216  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits(4) 11111 = No Sync or Trigger source for ICx 11110 = Reserved 11101 = Reserved 11100 = CTMU module synchronizes or triggers ICx 11011 = ADC1 module synchronizes or triggers ICx(5) 11010 = CMP3 module synchronizes or triggers ICx(5) 11001 = CMP2 module synchronizes or triggers ICx(5) 11000 = CMP1 module synchronizes or triggers ICx(5) 10111 = Reserved 10110 = Reserved 10101 = Reserved 10100 = Reserved 10011 = IC4 module synchronizes or triggers ICx 10010 = IC3 module synchronizes or triggers ICx 10001 = IC2 module synchronizes or triggers ICx 10000 = IC1 module synchronizes or triggers ICx 01111 = Timer5 synchronizes or triggers ICx 01110 = Timer4 synchronizes or triggers ICx 01101 = Timer3 synchronizes or triggers ICx (default) 01100 = Timer2 synchronizes or triggers ICx 01011 = Timer1 synchronizes or triggers ICx 01010 = PTGOx module synchronizes or triggers ICx(6) 01001 = Reserved 01000 = Reserved 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = OC4 module synchronizes or triggers ICx 00011 = OC3 module synchronizes or triggers ICx 00010 = OC2 module synchronizes or triggers ICx 00001 = OC1 module synchronizes or triggers ICx 00000 = No Sync or Trigger source for ICx Note 1: The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode. 2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register. 3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits). It can be read, set and cleared in software. 4: Do not use the ICx module as its own Sync or Trigger source. 5: This option should only be selected as a trigger source and not as a synchronization source. 6: Each Input Capture x (ICx) module has one PTG input source. See Section24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO8 = IC1 PTGO9 = IC2 PTGO10 = IC3 PTGO11 = IC4  2011-2013 Microchip Technology Inc. DS70000657H-page 217

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 218  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 15.0 OUTPUT COMPARE The output compare module can select one of seven available clock sources for its time base. The module Note1: This data sheet summarizes the features compares the value of the timer with the value of one or of the dsPIC33EPXXXGP50X, two compare registers depending on the operating dsPIC33EPXXXMC20X/50X and mode selected. The state of the output pin changes PIC24EPXXXGP/MC20X families of when the timer value matches the compare register devices. It is not intended to be a compre- value. The output compare module generates either a hensive reference source. To complement single output pulse or a sequence of output pulses, by the information in this data sheet, refer to changing the state of the output pin on the compare “Output Compare” (DS70358) in the match events. The output compare module can also “dsPIC33/PIC24 Family Reference Man- generate interrupts on compare match events and ual”, which is available from the Microchip trigger DMA data transfers. web site (www.microchip.com). Note: See “Output Compare” (DS70358) in 2: Some registers and associated bits the “dsPIC33/PIC24 Family Reference described in this section may not be Manual” for OCxR and OCxRS register available on all devices. Refer to restrictions. Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 15-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM OCxCON1 OCxCON2 OCxR CTMU Edge Rollover/Reset Control Logic OCxR Buffer OCx Pin Comparator Increment Match OC Clock Clock Event Sources Select OCFB OC Output and OCxTMR Rollover Fault Logic Reset OCFA Comparator Match Event Match Trigger and Event Trigger and Sync Sources Sync Logic OCxRS Buffer PTG Trigger Input SYNCSEL<4:0> Rollover/Reset Trigger(1) OCx Synchronization/Trigger Event OCxRS OCx Interrupt Reset Note 1: The Trigger/Sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for proper OCx module operation or the Trigger/Sync source must be changed to another source option.  2011-2013 Microchip Technology Inc. DS70000657H-page 219

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 15.1 Output Compare Resources 15.1.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Output Compare” (DS70358) in the “dsPIC33/ uct page of the Microchip web site for the devices listed PIC24 Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464 DS70000657H-page 220  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 15.2 Output Compare Control Registers REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — ENFLTB bit 15 bit 8 R/W-0 U-0 R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 ENFLTA — OCFLTB OCFLTA TRIGMODE OCM2 OCM1 OCM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit 1 = Output Compare x Halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-10 OCTSEL<2:0>: Output Compare x Clock Select bits 111 = Peripheral clock (FP) 110 = Reserved 101 = PTGOx clock(2) 100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported) 011 = T5CLK is the clock source of the OCx 010 = T4CLK is the clock source of the OCx 001 = T3CLK is the clock source of the OCx 000 = T2CLK is the clock source of the OCx bit 9 Unimplemented: Read as ‘0’ bit 8 ENFLTB: Fault B Input Enable bit 1 = Output Compare Fault B input (OCFB) is enabled 0 = Output Compare Fault B input (OCFB) is disabled bit 7 ENFLTA: Fault A Input Enable bit 1 = Output Compare Fault A input (OCFA) is enabled 0 = Output Compare Fault A input (OCFA) is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 OCFLTB: PWM Fault B Condition Status bit 1 = PWM Fault B condition on OCFB pin has occurred 0 = No PWM Fault B condition on OCFB pin has occurred bit 4 OCFLTA: PWM Fault A Condition Status bit 1 = PWM Fault A condition on OCFA pin has occurred 0 = No PWM Fault A condition on OCFA pin has occurred Note 1: OCxR and OCxRS are double-buffered in PWM mode only. 2: Each Output Compare x module (OCx) has one PTG clock source. See Section24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO4 = OC1 PTGO5 = OC2 PTGO6 = OC3 PTGO7 = OC4  2011-2013 Microchip Technology Inc. DS70000657H-page 221

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is cleared only by software bit 2-0 OCM<2:0>: Output Compare x Mode Select bits 111 = Center-Aligned PWM mode: Output set high when OCxTMR = OCxR and set low when OCxTMR= OCxRS(1) 110 = Edge-Aligned PWM mode: Output set high when OCxTMR = 0 and set low when OCxTMR = OCxR(1) 101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare mode: Compare event with OCxR, continuously toggles OCx pin 010 = Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces OCx pin low 001 = Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces OCx pin high 000 = Output compare channel is disabled Note 1: OCxR and OCxRS are double-buffered in PWM mode only. 2: Each Output Compare x module (OCx) has one PTG clock source. See Section24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO4 = OC1 PTGO5 = OC2 PTGO6 = OC3 PTGO7 = OC4 DS70000657H-page 222  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTx bit is cleared in software and a new PWM period starts 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts bit 14 FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault bit 13 FLTTRIEN: Fault Output State Select bit 1 = OCx pin is tri-stated on a Fault condition 0 = OCx pin I/O state is defined by the FLTOUT bit on a Fault condition bit 12 OCINV: Output Compare x Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted bit 11-9 Unimplemented: Read as ‘0’ bit 8 OC32: Cascade Two OCx Modules Enable bit (32-bit operation) 1 = Cascade module operation is enabled 0 = Cascade module operation is disabled bit 7 OCTRIG: Output Compare x Trigger/Sync Select bit 1 = Triggers OCx from the source designated by the SYNCSELx bits 0 = Synchronizes OCx with the source designated by the SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear bit 5 OCTRIS: Output Compare x Output Pin Direction Select bit 1 = OCx is tri-stated 0 = Output Compare x module drives the OCx pin Note 1: Do not use the OCx module as its own Synchronization or Trigger source. 2: When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module uses the OCy module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it. 3: Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO0 = OC1 PTGO1 = OC2 PTGO2 = OC3 PTGO3 = OC4  2011-2013 Microchip Technology Inc. DS70000657H-page 223

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = OCxRS compare event is used for synchronization 11110 = INT2 pin synchronizes or triggers OCx 11101 = INT1 pin synchronizes or triggers OCx 11100 = CTMU module synchronizes or triggers OCx 11011 = ADC1 module synchronizes or triggers OCx 11010 = CMP3 module synchronizes or triggers OCx 11001 = CMP2 module synchronizes or triggers OCx 11000 = CMP1 module synchronizes or triggers OCx 10111 = Reserved 10110 = Reserved 10101 = Reserved 10100 = Reserved 10011 = IC4 input capture event synchronizes or triggers OCx 10010 = IC3 input capture event synchronizes or triggers OCx 10001 = IC2 input capture event synchronizes or triggers OCx 10000 = IC1 input capture event synchronizes or triggers OCx 01111 = Timer5 synchronizes or triggers OCx 01110 = Timer4 synchronizes or triggers OCx 01101 = Timer3 synchronizes or triggers OCx 01100 = Timer2 synchronizes or triggers OCx (default) 01011 = Timer1 synchronizes or triggers OCx 01010 = PTGOx synchronizes or triggers OCx(3) 01001 = Reserved 01000 = Reserved 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = OC4 module synchronizes or triggers OCx(1,2) 00011 = OC3 module synchronizes or triggers OCx(1,2) 00010 = OC2 module synchronizes or triggers OCx(1,2) 00001 = OC1 module synchronizes or triggers OCx(1,2) 00000 = No Sync or Trigger source for OCx Note 1: Do not use the OCx module as its own Synchronization or Trigger source. 2: When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module uses the OCy module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it. 3: Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO0 = OC1 PTGO1 = OC2 PTGO2 = OC3 PTGO3 = OC4 DS70000657H-page 224  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 16.0 HIGH-SPEED PWM MODULE The high-speed PWMx module contains up to three (dsPIC33EPXXXMC20X/50X PWM generators. Each PWM generator provides two PWM outputs: PWMxH and PWMxL. The master time AND PIC24EPXXXMC20X base generator provides a synchronous signal as a DEVICES ONLY) common time base to synchronize the various PWM outputs. The individual PWM outputs are available on Note1: This data sheet summarizes the the output pins of the device. The input Fault signals features of the dsPIC33EPXXXGP50X, and current-limit signals, when enabled, can monitor dsPIC33EPXXXMC20X/50X and and protect the system by placing the PWM outputs PIC24EPXXXGP/MC20X families of into a known “safe” state. devices. It is not intended to be a Each PWMx can generate a trigger to the ADC module comprehensive reference source. To com- to sample the analog signal at a specific instance plement the information in this data sheet, during the PWM period. In addition, the high-speed refer to “High-Speed PWM” (DS70645) PWMx module also generates a Special Event Trigger in the “dsPIC33/PIC24 Family Reference to the ADC module based on either of the two master Manual”, which is available from the time bases. Microchip web site (www.microchip.com). The high-speed PWMx module can synchronize itself 2: Some registers and associated bits with an external signal or can act as a synchronizing described in this section may not be source to any external device. The SYNCI1 input pin available on all devices. Refer to that utilizes PPS, can synchronize the high-speed Section4.0 “Memory Organization” in PWMx module with an external signal. The SYNCO1 this data sheet for device-specific register pin is an output pin that provides a synchronous signal and bit information. to an external device. The dsPIC33EPXXXMC20X/50X and Figure16-1 illustrates an architectural overview of the PIC24EPXXXMC20X devices support a dedicated high-speed PWMx module and its interconnection with Pulse-Width Modulation (PWM) module with up to the CPU and other peripherals. 6outputs. The high-speed PWMx module consists of the 16.1 PWM Faults following major features: The PWMx module incorporates multiple external Fault • Three PWM generators inputs to include FLT1 and FLT2 which are re- • Two PWM outputs per PWM generator mappable using the PPS feature, FLT3 and FLT4 which • Individual period and duty cycle for each PWM pair are available only on the larger 44-pin and 64-pin • Duty cycle, dead time, phase shift and frequency packages, and FLT32 which has been implemented resolution of TCY/2 (7.14 ns at FCY = 70MHz) with Class B safety features, and is available on a fixed pin on all dsPIC33EPXXXMC20X/50X and • Independent Fault and current-limit inputs for PIC24EPXXXMC20X devices. six PWM outputs • Redundant output These Faults provide a safe and reliable way to safely shut down the PWM outputs when the Fault input is • Center-Aligned PWM mode asserted. • Output override control • Chop mode (also known as Gated mode) 16.1.1 PWM FAULTS AT RESET • Special Event Trigger During any Reset event, the PWMx module maintains • Prescaler for input clock ownership of the Class B Fault, FLT32. At Reset, this • PWMxL and PWMxH output pin swapping Fault is enabled in Latched mode to ensure the fail-safe • Independent PWM frequency, duty cycle and power-up of the application. The application software phase-shift changes for each PWM generator must clear the PWM Fault before enabling the high- speed motor control PWMx module. To clear the Fault • Dead-time compensation condition, the FLT32 pin must first be pulled low • Enhanced Leading-Edge Blanking (LEB) externally or the internal pull-down resistor in the functionality CNPDx register can be enabled. • Frequency resolution enhancement Note: The Fault mode may be changed using • PWM capture functionality the FLTMOD<1:0> bits (FCLCON<1:0>), Note: In Edge-Aligned PWM mode, the duty regardless of the state of FLT32. cycle, dead time, phase shift and frequency resolution are 8.32 ns.  2011-2013 Microchip Technology Inc. DS70000657H-page 225

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 16.1.2 WRITE-PROTECTED REGISTERS To gain write access to these locked registers, the user application must write two consecutive values of On dsPIC33EPXXXMC20X/50X and (0xABCD and 0x4321) to the PWMKEY register to PIC24EPXXXMC20X devices, write protection is perform the unlock operation. The write access to the implemented for the IOCONx and FCLCONx registers. IOCONx or FCLCONx registers must be the next SFR The write protection feature prevents any inadvertent access following the unlock process. There can be no writes to these registers. This protection feature can be other SFR accesses during the unlock process and controlled by the PWMLOCK Configuration bit subsequent write access. To write to both the IOCONx (FOSCSEL<6>). The default state of the write and FCLCONx registers requires two unlock operations. protection feature is enabled (PWMLOCK = 1). The write protection feature can be disabled by configuring, The correct unlocking sequence is described in PWMLOCK = 0. Example16-1. EXAMPLE 16-1: PWMx WRITE-PROTECTED REGISTER UNLOCK SEQUENCE ; FLT32 pin must be pulled low externally in order to clear and disable the fault ; Writing to FCLCON1 register requires unlock sequence mov #0xabcd,w10 ; Load first unlock key to w10 register mov #0x4321,w11 ; Load second unlock key to w11 register mov #0x0000,w0 ; Load desired value of FCLCON1 register in w0 mov w10, PWMKEY ; Write first unlock key to PWMKEY register mov w11, PWMKEY ; Write second unlock key to PWMKEY register mov w0,FCLCON1 ; Write desired value to FCLCON1 register ; Set PWM ownership and polarity using the IOCON1 register ; Writing to IOCON1 register requires unlock sequence mov #0xabcd,w10 ; Load first unlock key to w10 register mov #0x4321,w11 ; Load second unlock key to w11 register mov #0xF000,w0 ; Load desired value of IOCON1 register in w0 mov w10, PWMKEY ; Write first unlock key to PWMKEY register mov w11, PWMKEY ; Write second unlock key to PWMKEY register mov w0,IOCON1 ; Write desired value to IOCON1 register DS70000657H-page 226  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 16-1: HIGH-SPEED PWMx MODULE ARCHITECTURAL OVERVIEW SYNCI1 Data Bus FOSC Master Time Base SYNCO1 SynchronizationSignal PWM1Interrupt(1) PWM1H PWM Generator 1 PWM1L Fault, Current-Limit and Dead-Time Compensation SynchronizationSignal PWM2Interrupt(1) CPU PWM2H PWM Generator 2 PWM2L Fault, Current-Limit and Dead-Time Compensation SynchronizationSignal PWM3Interrupt(1) PWM3H PWM Generator 3 PWM3L Primary Trigger Fault, Current-Limit and Dead-Time Compensation ADC Module Primary Special FLT1-FLT4, FLT32 Event Trigger DTCMP1-DTCMP3 Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the given PWM generator. Refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM” (DS70645) for more information.  2011-2013 Microchip Technology Inc. DS70000657H-page 227

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 16-2: HIGH-SPEED PWMx MODULE REGISTER INTERCONNECTION DIAGRAM FOSC PTCON, PTCON2 Module Control and Timing SYNCI1 PWMKEY IOCONx and FCLCONx Unlock Register SYNCO1 PTPER SEVTCMP Special Event Compare Trigger PTG Trigger Input Special Event Comparator Comparator Postscaler Special Event Trigger Master Time Base Counter PTG Trigger Input PMTMR Clock Prescaler Primary Master Time Base MDC Master Duty Cycle Register n zatio ycle PDCx PWM Generator 1 ni C chro Duty MUX ata BusSyn Master Period Comparator PWCMo nOtruotlp Luot gMicode Bit D ster PWMCAPx User Override Logic 6- Ma ADC Trigger Dead-Time Pin PWM1H 1 Current-Limit Logic Control Override Logic Logic PWM1L PTMRx Comparator Fault Override Logic PHASEx TRIGx PTG Trigger Interrupt Fault and FLTx Input Logic(1) Current-Limit Logic DTCMP1 on FCLCONx IOCONx ALTDTRx ati z Synchroni aster Duty Cycle Master Period PAWUMXCCOONNxx, TRGCONx LLEEBBCDOLNYxx, DTRx M PWMxH PWMxL PWM Generator 2 and PWM Generator 3 FLTx DTCMPx Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the given PWM generator. Refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM” (DS70645) for more information. DS70000657H-page 228  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 16.2 PWM Resources 16.2.1 KEY RESOURCES Many useful resources are provided on the main prod- • “High-Speed PWM” (DS70645) in the uct page of the Microchip web site for the devices listed “dsPIC33/PIC24 Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2013 Microchip Technology Inc. DS70000657H-page 229

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 16.3 PWMx Control Registers REGISTER 16-1: PTCON: PWMx TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN — PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN(1) SYNCSRC2(1) SYNCSRC1(1) SYNCSRC0(1) SEVTPS3(1) SEVTPS2(1) SEVTPS1(1) SEVTPS0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWMx Module Enable bit 1 = PWMx module is enabled 0 = PWMx module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PTSIDL: PWMx Time Base Stop in Idle Mode bit 1 = PWMx time base halts in CPU Idle mode 0 = PWMx time base runs in CPU Idle mode bit 12 SESTAT: Special Event Interrupt Status bit 1 = Special event interrupt is pending 0 = Special event interrupt is not pending bit 11 SEIEN: Special Event Interrupt Enable bit 1 = Special event interrupt is enabled 0 = Special event interrupt is disabled bit 10 EIPU: Enable Immediate Period Updates bit(1) 1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWMx cycle boundaries bit 9 SYNCPOL: Synchronize Input and Output Polarity bit(1) 1 = SYNCI1/SYNCO1 polarity is inverted (active-low) 0 = SYNCI1/SYNCO1 is active-high bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1) 1 = SYNCO1 output is enabled 0 = SYNCO1 output is disabled bit 7 SYNCEN: External Time Base Synchronization Enable bit(1) 1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. 2: See Section24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection. DS70000657H-page 230  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-1: PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED) bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1) 111 = Reserved • • • 100 = Reserved 011 = PTGO17(2) 010 = PTGO16(2) 001 = Reserved 000 = SYNCI1 input from PPS bit 3-0 SEVTPS<3:0>: PWMx Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. 2: See Section24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.  2011-2013 Microchip Technology Inc. DS70000657H-page 231

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-2: PTCON2: PWMx PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCLKDIV2(1) PCLKDIV1(1) PCLKDIV0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide-by-64 101 = Divide-by-32 100 = Divide-by-16 011 = Divide-by-8 010 = Divide-by-4 001 = Divide-by-2 000 = Divide-by-1, maximum PWMx timing resolution (power-on default) Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. DS70000657H-page 232  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-3: PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PTPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PTPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits REGISTER 16-4: SEVTCMP: PWMx PRIMARY SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SEVTCMP<15:0>: Special Event Compare Count Value bits  2011-2013 Microchip Technology Inc. DS70000657H-page 233

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-5: CHOP: PWMx CHOP CLOCK GENERATOR REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 CHPCLKEN — — — — — CHOPCLK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHOPCLK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHPCLKEN: Enable Chop Clock Generator bit 1 = Chop clock generator is enabled 0 = Chop clock generator is disabled bit 14-10 Unimplemented: Read as ‘0’ bit 9-0 CHOPCLK<9:0>: Chop Clock Divider bits The frequency of the chop clock signal is given by the following expression: Chop Frequency = (FP/PCLKDIV<2:0)/(CHOPCLK<9:0> + 1) REGISTER 16-6: MDC: PWMx MASTER DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 MDC<15:0>: PWMx Master Duty Cycle Value bits DS70000657H-page 234  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-7: PWMCONx: PWMx CONTROL REGISTER HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(2) MDCS(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DTC1 DTC0 DTCP(3) — MTBS CAM(2,4) XPRES(5) IUE(2) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTSTAT: Fault Interrupt Status bit(1) 1 = Fault interrupt is pending 0 = No Fault interrupt is pending This bit is cleared by setting FLTIEN = 0. bit 14 CLSTAT: Current-Limit Interrupt Status bit(1) 1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending This bit is cleared by setting CLIEN = 0. bit 13 TRGSTAT: Trigger Interrupt Status bit 1 = Trigger interrupt is pending 0 = No trigger interrupt is pending This bit is cleared by setting TRGIEN = 0. bit 12 FLTIEN: Fault Interrupt Enable bit 1 = Fault interrupt is enabled 0 = Fault interrupt is disabled and the FLTSTAT bit is cleared bit 11 CLIEN: Current-Limit Interrupt Enable bit 1 = Current-limit interrupt is enabled 0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared bit 10 TRGIEN: Trigger Interrupt Enable bit 1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared bit 9 ITB: Independent Time Base Mode bit(2) 1 = PHASEx register provides time base period for this PWM generator 0 = PTPER register provides timing for this PWM generator bit 8 MDCS: Master Duty Cycle Register Select bit(2) 1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx register provides duty cycle information for this PWM generator Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller. 2: These bits should not be changed after the PWMx is enabled (PTEN = 1). 3: DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored. 4: The Independent Time Base (ITB=1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx register must be ‘0’.  2011-2013 Microchip Technology Inc. DS70000657H-page 235

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-7: PWMCONx: PWMx CONTROL REGISTER (CONTINUED) bit 7-6 DTC<1:0>: Dead-Time Control bits 11 = Dead-Time Compensation mode 10 = Dead-time function is disabled 01 = Negative dead time is actively applied for Complementary Output mode 00 = Positive dead time is actively applied for all output modes bit 5 DTCP: Dead-Time Compensation Polarity bit(3) When Set to ‘1’: If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened. If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened. When Set to ‘0’: If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened. If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened. bit 4 Unimplemented: Read as ‘0’ bit 3 MTBS: Master Time Base Select bit 1 = PWM generator uses the secondary master time base for synchronization and as the clock source for the PWM generation logic (if secondary time base is available) 0 = PWM generator uses the primary master time base for synchronization and as the clock source for the PWM generation logic bit 2 CAM: Center-Aligned Mode Enable bit(2,4) 1 = Center-Aligned mode is enabled 0 = Edge-Aligned mode is enabled bit 1 XPRES: External PWMx Reset Control bit(5) 1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWMx time base bit 0 IUE: Immediate Update Enable bit(2) 1 = Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are immediate 0 = Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are synchronized to the PWMx period boundary Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller. 2: These bits should not be changed after the PWMx is enabled (PTEN = 1). 3: DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored. 4: The Independent Time Base (ITB=1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx register must be ‘0’. DS70000657H-page 236  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-8: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDCx<15:0>: PWMx Generator # Duty Cycle Value bits REGISTER 16-9: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PHASEx<15:0>: PWMx Phase-Shift Value or Independent Time Base Period for the PWM Generator bits Note1: If ITB (PWMCONx<9>) = 0, the following applies based on the mode of operation: Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCON<11:10>) = 00, 01 or 10), PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs 2: If ITB (PWMCONx<9>) = 1, the following applies based on the mode of operation: Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10), PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL  2011-2013 Microchip Technology Inc. DS70000657H-page 237

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-10: DTRx: PWMx DEAD-TIME REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits REGISTER 16-11: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ALTDTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALTDTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits DS70000657H-page 238  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-12: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 TRGDIV<3:0> — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TRGSTRT<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits 1111 = Trigger output for every 16th trigger event 1110 = Trigger output for every 15th trigger event 1101 = Trigger output for every 14th trigger event 1100 = Trigger output for every 13th trigger event 1011 = Trigger output for every 12th trigger event 1010 = Trigger output for every 11th trigger event 1001 = Trigger output for every 10th trigger event 1000 = Trigger output for every 9th trigger event 0111 = Trigger output for every 8th trigger event 0110 = Trigger output for every 7th trigger event 0101 = Trigger output for every 6th trigger event 0100 = Trigger output for every 5th trigger event 0011 = Trigger output for every 4th trigger event 0010 = Trigger output for every 3rd trigger event 0001 = Trigger output for every 2nd trigger event 0000 = Trigger output for every trigger event bit 11-6 Unimplemented: Read as ‘0’ bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits(1) 111111 = Waits 63 PWM cycles before generating the first trigger event after the module is enabled • • • 000010 = Waits 2 PWM cycles before generating the first trigger event after the module is enabled 000001 = Waits 1 PWM cycle before generating the first trigger event after the module is enabled 000000 = Waits 0 PWM cycles before generating the first trigger event after the module is enabled Note 1: The secondary PWM generator cannot generate PWMx trigger interrupts.  2011-2013 Microchip Technology Inc. DS70000657H-page 239

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-13: IOCONx: PWMx I/O CONTROL REGISTER(2) R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PENH PENL POLH POLL PMOD1(1) PMOD0(1) OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PENH: PWMxH Output Pin Ownership bit 1 = PWMx module controls PWMxH pin 0 = GPIO module controls PWMxH pin bit 14 PENL: PWMxL Output Pin Ownership bit 1 = PWMx module controls PWMxL pin 0 = GPIO module controls PWMxL pin bit 13 POLH: PWMxH Output Pin Polarity bit 1 = PWMxH pin is active-low 0 = PWMxH pin is active-high bit 12 POLL: PWMxL Output Pin Polarity bit 1 = PWMxL pin is active-low 0 = PWMxL pin is active-high bit 11-10 PMOD<1:0>: PWMx # I/O Pin Mode bits(1) 11 = Reserved; do not use 10 = PWMx I/O pin pair is in the Push-Pull Output mode 01 = PWMx I/O pin pair is in the Redundant Output mode 00 = PWMx I/O pin pair is in the Complementary Output mode bit 9 OVRENH: Override Enable for PWMxH Pin bit 1 = OVRDAT<1> controls output on PWMxH pin 0 = PWMx generator controls PWMxH pin bit 8 OVRENL: Override Enable for PWMxL Pin bit 1 = OVRDAT<0> controls output on PWMxL pin 0 = PWMx generator controls PWMxL pin bit 7-6 OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits If OVERENH = 1, PWMxH is driven to the state specified by OVRDAT<1>. If OVERENL = 1, PWMxL is driven to the state specified by OVRDAT<0>. bit 5-4 FLTDAT<1:0>: Data for PWMxH and PWMxL Pins if FLTMOD is Enabled bits If Fault is active, PWMxH is driven to the state specified by FLTDAT<1>. If Fault is active, PWMxL is driven to the state specified by FLTDAT<0>. bit 3-2 CLDAT<1:0>: Data for PWMxH and PWMxL Pins if CLMOD is Enabled bits If current-limit is active, PWMxH is driven to the state specified by CLDAT<1>. If current-limit is active, PWMxL is driven to the state specified by CLDAT<0>. Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1). 2: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after the unlock sequence has been executed. DS70000657H-page 240  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-13: IOCONx: PWMx I/O CONTROL REGISTER(2) (CONTINUED) bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit 1 = PWMxH output signal is connected to PWMxL pins; PWMxL output signal is connected to PWMxH pins 0 = PWMxH and PWMxL pins are mapped to their respective pins bit 0 OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx period boundary 0 = Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock boundary Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1). 2: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after the unlock sequence has been executed.  2011-2013 Microchip Technology Inc. DS70000657H-page 241

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-14: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 TRGCMP<15:0>: Trigger Control Value bits When the primary PWMx functions in local time base, this register contains the compare values that can trigger the ADC module. DS70000657H-page 242  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL(2) CLMOD bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL(2) FLTMOD1 FLTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM Generator # bits 11111 = Fault 32 11110 = Reserved • • • 01100 = Reserved 01011 = Comparator 4 01010 = Op Amp/Comparator 3 01001 = Op Amp/Comparator 2 01000 = Op Amp/Comparator 1 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 (default) bit 9 CLPOL: Current-Limit Polarity for PWM Generator # bit(2) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high bit 8 CLMOD: Current-Limit Mode Enable for PWM Generator # bit 1 = Current-Limit mode is enabled 0 = Current-Limit mode is disabled Note 1: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after the unlock sequence has been executed. 2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results.  2011-2013 Microchip Technology Inc. DS70000657H-page 243

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER(1) bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits 11111 = Fault 32 (default) 11110 = Reserved • • • 01100 = Reserved 01011 = Comparator 4 01010 = Op Amp/Comparator 3 01001 = Op Amp/Comparator 2 01000 = Op Amp/Comparator 1 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 2 FLTPOL: Fault Polarity for PWM Generator # bit(2) 1 = The selected Fault source is active-low 0 = The selected Fault source is active-high bit 1-0 FLTMOD<1:0>: Fault Mode for PWM Generator # bits 11 = Fault input is disabled 10 = Reserved 01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle) 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition) Note 1: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after the unlock sequence has been executed. 2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. DS70000657H-page 244  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-16: LEBCONx: PWMx LEADING-EDGE BLANKING CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — BCH(1) BCL(1) BPHH BPHL BPLH BPLL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PWMxH Rising Edge Trigger Enable bit 1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxH bit 14 PHF: PWMxH Falling Edge Trigger Enable bit 1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxH bit 13 PLR: PWMxL Rising Edge Trigger Enable bit 1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxL bit 12 PLF: PWMxL Falling Edge Trigger Enable bit 1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxL bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit 1 = Leading-Edge Blanking is applied to selected Fault input 0 = Leading-Edge Blanking is not applied to selected Fault input bit 10 CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit 1 = Leading-Edge Blanking is applied to selected current-limit input 0 = Leading-Edge Blanking is not applied to selected current-limit input bit 9-6 Unimplemented: Read as ‘0’ bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1) 1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high 0 = No blanking when selected blanking signal is high bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit(1) 1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low 0 = No blanking when selected blanking signal is low bit 3 BPHH: Blanking in PWMxH High Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is high 0 = No blanking when PWMxH output is high bit 2 BPHL: Blanking in PWMxH Low Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is low 0 = No blanking when PWMxH output is low bit 1 BPLH: Blanking in PWMxL High Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is high 0 = No blanking when PWMxL output is high bit 0 BPLL: Blanking in PWMxL Low Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low 0 = No blanking when PWMxL output is low Note 1: The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.  2011-2013 Microchip Technology Inc. DS70000657H-page 245

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-17: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — LEB<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 LEB<11:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits DS70000657H-page 246  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 16-18: AUXCONx: PWMx AUXILIARY CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 BLANKSEL<3:0>: PWMx State Blank Source Select bits The selected state blank signal will block the current-limit and/or Fault input signals (if enabled via the BCH and BCL bits in the LEBCONx register). 1001 = Reserved • • • 0100 = Reserved 0011 = PWM3H selected as state blank source 0010 = PWM2H selected as state blank source 0001 = PWM1H selected as state blank source 0000 = No state blanking bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHOPSEL<3:0>: PWMx Chop Clock Source Select bits The selected signal will enable and disable (CHOP) the selected PWMx outputs. 1001 = Reserved • • • 0100 = Reserved 0011 = PWM3H selected as CHOP clock source 0010 = PWM2H selected as CHOP clock source 0001 = PWM1H selected as CHOP clock source 0000 = Chop clock generator selected as CHOP clock source bit 1 CHOPHEN: PWMxH Output Chopping Enable bit 1 = PWMxH chopping function is enabled 0 = PWMxH chopping function is disabled bit 0 CHOPLEN: PWMxL Output Chopping Enable bit 1 = PWMxL chopping function is enabled 0 = PWMxL chopping function is disabled  2011-2013 Microchip Technology Inc. DS70000657H-page 247

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 248  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 17.0 QUADRATURE ENCODER This chapter describes the Quadrature Encoder Inter- INTERFACE (QEI) MODULE face (QEI) module and associated operational modes. The QEI module provides the interface to incremental (dsPIC33EPXXXMC20X/50X encoders for obtaining mechanical position data. and PIC24EPXXXMC20X The operational features of the QEI module include: DEVICES ONLY) • 32-Bit Position Counter Note1: This data sheet summarizes the • 32-Bit Index Pulse Counter features of the dsPIC33EPXXXGP50X, • 32-Bit Interval Timer dsPIC33EPXXXMC20X/50X and • 16-Bit Velocity Counter PIC24EPXXXGP/MC20X families of • 32-Bit Position Initialization/Capture/Compare devices. It is not intended to be a High register comprehensive reference source. To com- • 32-Bit Position Compare Low register plement the information in this data sheet, • x4 Quadrature Count mode refer to “Quadrature Encoder Interface (QEI)” (DS70601) in the “dsPIC33/PIC24 • External Up/Down Count mode Family Reference Manual”, which is avail- • External Gated Count mode able from the Microchip web site • External Gated Timer mode (www.microchip.com). • Internal Timer mode 2: Some registers and associated bits Figure17-1 illustrates the QEI block diagram. described in this section may not be available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information.  2011-2013 Microchip Technology Inc. DS70000657H-page 249

D FIGURE 17-1: QEI BLOCK DIAGRAM d S s 70 P 000 FLTREN GATEN IC 6 3 57 3 H-pa HOMEx FHOMEx DIR_GATE EP g 1 X e 2  QFDIV FP COUNT COUNT_EN X 50 EXTCNT 0 XG INDXx FINDXx DIVCLK P Digital 5 Filter CCM 0X , DIR d QEBx Quadrature COUNT DIR_GATE s DLeocogdicer DIR 1’b0 CNT_DIR PI C CNTPOL 3 3 QEAx EXTCNT E P DIR_GATE X X PCHGE X M CNTCMPx PCLLE PCLLE C PCLEQ PCHEQ 2 PCHGE 32-Bit Less Than 32-Bit Greater Than 0 OUTFNC or Equal Comparator or Equal Comparator X/ 5 PCLLE PCHGE 0 X FP  INTDIV DIVCLK 32-Bit Less Than or Equal 32-Bit Greater Than or Equal A Compare Register Compare Register N COUNT_EN (QEI1LEC) (POS1CNT) (QEI1GEC)(1) D (INDX1CNT) 32-Bit Position Counter Register P  2011-2 CFNINT_DDXIRx 32IN-BDitX I1nCdeNxT CHouINnDteXr 1RCeNgiTsLter T3i2(mI-NBeTrit 1 RITneMtgeiRrsvt)aelr CNT_DIR COUNT_EN COCUNNTT__DEINR POS1CNTH POS1CNTL IC24E 0 P 13 X Microc 16-BH(IiotN lIdDn dXRe1exHg CiLsoDteu)rnter 32-BH(iotI NlIdnT tRe1erHvgLaisDl tT)eirmer C1o6(uV-nBEteiLtr 1V RCeelNogTcisi)ttyer 16-BHit( oPPlOdos SRit1ieoHgnLi sCDteo)runter QCAPEN 32C-Baitp( QItnuEirtieIa1 lRiIzCea)gt(i1oi)snte arnd XXG h P ip T /M e c C h nolo Data Bus Data Bus 20 g X y Note 1: These registers map to the same memory location. In c .

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 17.1 QEI Resources 17.1.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Quadrature Encoder Interface” (DS70601) in uct page of the Microchip web site for the devices listed the “dsPIC33/PIC24 Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2013 Microchip Technology Inc. DS70000657H-page 251

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 17.2 QEI Control Registers REGISTER 17-1: QEI1CON: QEI1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIEN — QEISIDL PIMOD2(1) PIMOD1(1) PIMOD0(1) IMV1(2) IMV0(2) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INTDIV2(3) INTDIV1(3) INTDIV0(3) CNTPOL GATEN CCM1 CCM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 QEIEN: Quadrature Encoder Interface Module Counter Enable bit 1 = Module counters are enabled 0 = Module counters are disabled, but SFRs can be read or written to bit 14 Unimplemented: Read as ‘0’ bit 13 QEISIDL: QEI Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 PIMOD<2:0>: Position Counter Initialization Mode Select bits(1) 111 = Reserved 110 = Modulo Count mode for position counter 101 = Resets the position counter when the position counter equals QEI1GEC register 100 = Second index event after home event initializes position counter with contents of QEI1IC register 011 = First index event after home event initializes position counter with contents of QEI1IC register 010 = Next index input event initializes the position counter with contents of QEI1IC register 001 = Every index input event resets the position counter 000 = Index input event does not affect position counter bit 9 IMV1: Index Match Value for Phase B bit(2) 1 = Phase B match occurs when QEB = 1 0 = Phase B match occurs when QEB = 0 bit 8 IMV0: Index Match Value for Phase A bit(2) 1 = Phase A match occurs when QEA = 1 0 = Phase A match occurs when QEA = 0 bit 7 Unimplemented: Read as ‘0’ Note 1: When CCM<1:0> = 10 or 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are ignored. 2: When CCM<1:0> = 00, and QEA and QEB values match the Index Match Value (IMV), the POSCNTH and POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits. 3: The selected clock rate should be at least twice the expected maximum quadrature count rate. DS70000657H-page 252  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 17-1: QEI1CON: QEI1 CONTROL REGISTER (CONTINUED) bit 6-4 INTDIV<2:0>: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter), velocity counter and index counter internal clock divider select)(3) 111 = 1:128 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3 CNTPOL: Position and Index Counter/Timer Direction Select bit 1 = Counter direction is negative unless modified by external up/down signal 0 = Counter direction is positive unless modified by external up/down signal bit 2 GATEN: External Count Gate Enable bit 1 = External gate signal controls position counter operation 0 = External gate signal does not affect position counter/timer operation bit 1-0 CCM<1:0>: Counter Control Mode Selection bits 11 = Internal Timer mode with optional external count is selected 10 = External clock count with optional external count is selected 01 = External clock count with external up/down direction is selected 00 = Quadrature Encoder Interface (x4 mode) Count mode is selected Note 1: When CCM<1:0> = 10 or 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are ignored. 2: When CCM<1:0> = 00, and QEA and QEB values match the Index Match Value (IMV), the POSCNTH and POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits. 3: The selected clock rate should be at least twice the expected maximum quadrature count rate.  2011-2013 Microchip Technology Inc. DS70000657H-page 253

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 17-2: QEI1IOC: QEI1 I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QCAPEN FLTREN QFDIV2 QFDIV1 QFDIV0 OUTFNC1 OUTFNC0 SWPAB bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R-x R-x R-x R-x HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 QCAPEN: QEI Position Counter Input Capture Enable bit 1 = Index match event triggers a position capture event 0 = Index match event does not trigger a position capture event bit 14 FLTREN: QEAx/QEBx/INDXx/HOMEx Digital Filter Enable bit 1 = Input pin digital filter is enabled 0 = Input pin digital filter is disabled (bypassed) bit 13-11 QFDIV<2:0>: QEAx/QEBx/INDXx/HOMEx Digital Input Filter Clock Divide Select bits 111 = 1:128 clock divide 110 = 1:64 clock divide 101 = 1:32 clock divide 100 = 1:16 clock divide 011 = 1:8 clock divide 010 = 1:4 clock divide 001 = 1:2 clock divide 000 = 1:1 clock divide bit 10-9 OUTFNC<1:0>: QEI Module Output Function Mode Select bits 11 = The CTNCMPx pin goes high when QEI1LEC  POS1CNT  QEI1GEC 10 = The CTNCMPx pin goes high when POS1CNT  QEI1LEC 01 = The CTNCMPx pin goes high when POS1CNT  QEI1GEC 00 = Output is disabled bit 8 SWPAB: Swap QEA and QEB Inputs bit 1 = QEAx and QEBx are swapped prior to quadrature decoder logic 0 = QEAx and QEBx are not swapped bit 7 HOMPOL: HOMEx Input Polarity Select bit 1 = Input is inverted 0 = Input is not inverted bit 6 IDXPOL: INDXx Input Polarity Select bit 1 = Input is inverted 0 = Input is not inverted bit 5 QEBPOL: QEBx Input Polarity Select bit 1 = Input is inverted 0 = Input is not inverted bit 4 QEAPOL: QEAx Input Polarity Select bit 1 = Input is inverted 0 = Input is not inverted bit 3 HOME: Status of HOMEx Input Pin After Polarity Control 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ DS70000657H-page 254  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 17-2: QEI1IOC: QEI1 I/O CONTROL REGISTER (CONTINUED) bit 2 INDEX: Status of INDXx Input Pin After Polarity Control 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ bit 1 QEB: Status of QEBx Input Pin After Polarity Control And SWPAB Pin Swapping 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ bit 0 QEA: Status of QEAx Input Pin After Polarity Control And SWPAB Pin Swapping 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’  2011-2013 Microchip Technology Inc. DS70000657H-page 255

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 17-3: QEI1STAT: QEI1 STATUS REGISTER U-0 U-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN bit 15 bit 8 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 PCIIRQ(1) PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN bit 7 bit 0 Legend: HS = Hardware Settable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 PCHEQIRQ: Position Counter Greater Than or Equal Compare Status bit 1 = POS1CNT ≥ QEI1GEC 0 = POS1CNT < QEI1GEC bit 12 PCHEQIEN: Position Counter Greater Than or Equal Compare Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 11 PCLEQIRQ: Position Counter Less Than or Equal Compare Status bit 1 = POS1CNT ≤ QEI1LEC 0 = POS1CNT > QEI1LEC bit 10 PCLEQIEN: Position Counter Less Than or Equal Compare Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 9 POSOVIRQ: Position Counter Overflow Status bit 1 = Overflow has occurred 0 = No overflow has occurred bit 8 POSOVIEN: Position Counter Overflow Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 7 PCIIRQ: Position Counter (Homing) Initialization Process Complete Status bit(1) 1 = POS1CNT was reinitialized 0 = POS1CNT was not reinitialized bit 6 PCIIEN: Position Counter (Homing) Initialization Process Complete interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 VELOVIRQ: Velocity Counter Overflow Status bit 1 = Overflow has occurred 0 = No overflow has not occurred bit 4 VELOVIEN: Velocity Counter Overflow Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 HOMIRQ: Status Flag for Home Event Status bit 1 = Home event has occurred 0 = No Home event has occurred Note 1: This status bit is only applicable to PIMOD<2:0> modes, ‘011’ and ‘100’. DS70000657H-page 256  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 17-3: QEI1STAT: QEI1 STATUS REGISTER (CONTINUED) bit 2 HOMIEN: Home Input Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 IDXIRQ: Status Flag for Index Event Status bit 1 = Index event has occurred 0 = No Index event has occurred bit 0 IDXIEN: Index Input Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This status bit is only applicable to PIMOD<2:0> modes, ‘011’ and ‘100’.  2011-2013 Microchip Technology Inc. DS70000657H-page 257

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R E GISTER 17-4: POS1CNTH: POSITION COUNTER 1 HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 POSCNT<31:16>: High Word Used to Form 32-Bit Position Counter Register (POS1CNT) bits REGISTER 17-5: POS1CNTL: POSITION COUNTER 1 LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 POSCNT<15:0>: Low Word Used to Form 32-Bit Position Counter Register (POS1CNT) bits REGISTER 17-6: POS1HLD: POSITION COUNTER 1 HOLD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSHLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSHLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 POSHLD<15:0>: Hold Register for Reading and Writing POS1CNTH bits DS70000657H-page 258  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R E GISTER 17-7: VEL1CNT: VELOCITY COUNTER 1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VELCNT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VELCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 VELCNT<15:0>: Velocity Counter bits REGISTER 17-8: INDX1CNTH: INDEX COUNTER 1 HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INDXCNT<31:16>: High Word Used to Form 32-Bit Index Counter Register (INDX1CNT) bits REGISTER 17-9: INDX1CNTL: INDEX COUNTER 1 LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INDXCNT<15:0>: Low Word Used to Form 32-Bit Index Counter Register (INDX1CNT) bits  2011-2013 Microchip Technology Inc. DS70000657H-page 259

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R E GISTER 17-10: INDX1HLD: INDEX COUNTER 1 HOLD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXHLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXHLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INDXHLD<15:0>: Hold Register for Reading and Writing INDX1CNTH bits REGISTER 17-11: QEI1ICH: QEI1 INITIALIZATION/CAPTURE HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIIC<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIIC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIIC<31:16>: High Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits REGISTER 17-12: QEI1ICL: QEI1 INITIALIZATION/CAPTURE LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIIC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIIC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIIC<15:0>: Low Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits DS70000657H-page 260  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R E GISTER 17-13: QEI1LECH: QEI1 LESS THAN OR EQUAL COMPARE HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEILEC<31:16>: High Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits REGISTER 17-14: QEI1LECL: QEI1 LESS THAN OR EQUAL COMPARE LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEILEC<15:0>: Low Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits  2011-2013 Microchip Technology Inc. DS70000657H-page 261

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R E GISTER 17-15: QEI1GECH: QEI1 GREATER THAN OR EQUAL COMPARE HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIGEC<31:16>: High Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits REGISTER 17-16: QEI1GECL: QEI1 GREATER THAN OR EQUAL COMPARE LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIGEC<15:0>: Low Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits DS70000657H-page 262  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 17-17: INT1TMRH: INTERVAL 1 TIMER HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTTMR<31:16>: High Word Used to Form 32-Bit Interval Timer Register (INT1TMR) bits REGISTER 17-18: INT1TMRL: INTERVAL 1 TIMER LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTTMR<15:0>: Low Word Used to Form 32-Bit Interval Timer Register (INT1TMR) bits  2011-2013 Microchip Technology Inc. DS70000657H-page 263

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 17-19: INT1HLDH: INTERVAL 1 TIMER HOLD HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTHLD<31:16>: Hold Register for Reading and Writing INT1TMRH bits REGISTER 17-20: INT1HLDL: INTERVAL 1 TIMER HOLD LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTHLD<15:0>: Hold Register for Reading and Writing INT1TMRL bits DS70000657H-page 264  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 18.0 SERIAL PERIPHERAL The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ INTERFACE (SPI) 50X and PIC24EPXXXGP/MC20X device family offers two SPI modules on a single device. These modules, Note1: This data sheet summarizes the which are designated as SPI1 and SPI2, are function- features of the dsPIC33EPXXXGP50X, ally identical. Each SPI module includes an eight-word dsPIC33EPXXXMC20X/50X and FIFO buffer and allows DMA bus connections. When PIC24EPXXXGP/MC20X families of using the SPI module with DMA, FIFO operation can be devices. It is not intended to be a disabled. comprehensive reference source. To com- Note: In this section, the SPI modules are plement the information in this data sheet, referred to together as SPIx, or separately refer to “Serial Peripheral Interface as SPI1 and SPI2. Special Function (SPI)” (DS70569) in the “dsPIC33/PIC24 Registers follow a similar notation. For Family Reference Manual”, which is avail- example, SPIxCON refers to the control able from the Microchip web site register for the SPI1 and SPI2 modules. (www.microchip.com). The SPI1 module uses dedicated pins which allow for a 2: Some registers and associated bits higher speed when using SPI1. The SPI2 module takes described in this section may not be advantage of the Peripheral Pin Select (PPS) feature to available on all devices. Refer to allow for greater flexibility in pin configuration of the SPI2 Section4.0 “Memory Organization” in module, but results in a lower maximum speed for SPI2. this data sheet for device-specific register See Section30.0 “Electrical Characteristics” for and bit information. more information. The SPI module is a synchronous serial interface, The SPIx serial interface consists of four pins, as useful for communicating with other peripheral or follows: microcontroller devices. These peripheral devices can • SDIx: Serial Data Input be serial EEPROMs, shift registers, display drivers, • SDOx: Serial Data Output ADC Converters, etc. The SPI module is compatible • SCKx: Shift Clock Input or Output with Motorola® SPI and SIOP interfaces. • SSx/FSYNCx: Active-Low Slave Select or Frame Synchronization I/O Pulse The SPIx module can be configured to operate with two, three or four pins. In 3-pin mode, SSx is not used. In 2-pin mode, neither SDOx nor SSx is used. Figure18-1 illustrates the block diagram of the SPIx module in Standard and Enhanced modes.  2011-2013 Microchip Technology Inc. DS70000657H-page 265

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FP Prescaler Prescaler SSx/FSYNCx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SDOx SPIxCON1<4:2> Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer 8-Level FIFO 8-Level FIFO Receive Buffer(1) Transmit Buffer(1) SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus Note 1: In Standard mode, the FIFO is only one level deep. DS70000657H-page 266  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 18.1 SPI Helpful Tips 18.2 SPI Resources 1. In Frame mode, if there is a possibility that the Many useful resources are provided on the main prod- master may not be initialized before the slave: uct page of the Microchip web site for the devices listed a) If FRMPOL (SPIxCON2<13>) = 1, use a in this data sheet. This product page, which can be pull-down resistor on SSx. accessed using this link, contains the latest updates and additional information. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: In the event you are not able to access the Note: This insures that the first frame product page using the link above, enter transmission after initialization is not this URL in your browser: shifted or corrupted. http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en555464 2. In Non-Framed 3-Wire mode, (i.e., not using SSx from a master): 18.2.1 KEY RESOURCES a) If CKP (SPIxCON1<6>) = 1, always place a • “Serial Peripheral Interface (SPI)” (DS70569) in pull-up resistor on SSx. the “dsPIC33/PIC24 Family Reference Manual” b) If CKP = 0, always place a pull-down • Code Samples resistor on SSx. • Application Notes Note: This will insure that during power-up and • Software Libraries initialization the master/slave will not lose • Webinars Sync due to an errant SCKx transition that would cause the slave to accumulate data • All Related “dsPIC33/PIC24 Family Reference Manual” Sections shift errors for both transmit and receive appearing as corrupted data. • Development Tools 3. FRMEN (SPIxCON2<15>) = 1 and SSEN (SPIxCON1<7>) = 1 are exclusive and invalid. In Frame mode, SCKx is continuous and the Frame Sync pulse is active on the SSx pin, which indicates the start of a data frame. Note: Not all third-party devices support Frame mode timing. Refer to the SPIx specifications in Section30.0 “Electrical Characteristics” for details. 4. In Master mode only, set the SMP bit (SPIxCON1<9>) to a ‘1’ for the fastest SPIx data rate possible. The SMP bit can only be set at the same time or after the MSTEN bit (SPIxCON1<5>) is set. To avoid invalid slave read data to the master, the user’s master software must ensure enough time for slave software to fill its write buffer before the user application initiates a master write/read cycle. It is always advisable to preload the SPIxBUF Transmit register in advance of the next master transaction cycle. SPIxBUF is transferred to the SPIx Shift register and is empty once the data transmission begins.  2011-2013 Microchip Technology Inc. DS70000657H-page 267

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 18.3 SPIx Control Registers REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 SPIEN — SPISIDL — — SPIBEC<2:0> bit 15 bit 8 R/W-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R-0, HS, HC SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables the module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Discontinues the module operation when device enters Idle mode 0 = Continues the module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPIx transfers that are pending. Slave mode: Number of SPIx transfers that are unread. bit 7 SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and Ready-To-Send or receive the data 0 = SPIx Shift register is not empty bit 6 SPIROV: SPIx Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded; the user application has not read the previous data in the SPIxBUF register 0 = No overflow has occurred bit 5 SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = RX FIFO is empty 0 = RX FIFO is not empty bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when last bit is shifted into SPIxSR and as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR and as a result, the TX FIFO has one open memory location 011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set) 010 = Interrupt when the SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in the receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read and as a result, the buffer is empty (SRXMPT bit is set) DS70000657H-page 268  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty Standard Buffer mode: Automatically set in hardware when core writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. Enhanced Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write operation. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive is complete, SPIxRXB is full 0 = Receive is incomplete, SPIxRXB is empty Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB. Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.  2011-2013 Microchip Technology Inc. DS70000657H-page 269

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN SPRE2(3) SPRE1(3) SPRE0(3) PPRE1(3) PPRE0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx Pin bit (SPIx Master modes only) 1 = Internal SPIx clock is disabled, pin functions as I/O 0 = Internal SPIx clock is enabled bit 11 DISSDO: Disable SDOx Pin bit 1 = SDOx pin is not used by the module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data is sampled at end of data output time 0 = Input data is sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(2) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by the module; pin is controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN=1). 2: This bit must be cleared when FRMEN = 1. 3: Do not set both primary and secondary prescalers to the value of 1:1. DS70000657H-page 270  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN=1). 2: This bit must be cleared when FRMEN = 1. 3: Do not set both primary and secondary prescalers to the value of 1:1.  2011-2013 Microchip Technology Inc. DS70000657H-page 271

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 18-3: SPIXCON2: SPIX CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — FRMDLY SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled (SSx pin is used as Frame Sync pulse input/output) 0 = Framed SPIx support is disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame Sync pulse input (slave) 0 = Frame Sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame Sync pulse is active-high 0 = Frame Sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame Sync pulse coincides with first bit clock 0 = Frame Sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced buffer is enabled 0 = Enhanced buffer is disabled (Standard mode) DS70000657H-page 272  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 19.0 INTER-INTEGRATED The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ CIRCUIT™ (I2C™) 50X and PIC24EPXXXGP/MC20X family of devices contains two Inter-Integrated Circuit (I2C) modules: Note1: This data sheet summarizes the I2C1 and I2C2. features of the dsPIC33EPXXXGP50X, The I2C module provides complete hardware support dsPIC33EPXXXMC20X/50X and for both Slave and Multi-Master modes of the I2C serial PIC24EPXXXGP/MC20X families of communication standard, with a 16-bit interface. devices. It is not intended to be a The I2C module has a 2-pin interface: comprehensive reference source. To com- plement the information in this data sheet, • The SCLx pin is clock refer to “Inter-Integrated Circuit™ • The SDAx pin is data (I2C™)” (DS70330) in the “dsPIC33/ The I2C module offers the following key features: PIC24 Family Reference Manual”, which • I2C interface supporting both Master and Slave is available from the Microchip web site modes of operation (www.microchip.com). • I2C Slave mode supports 7 and 10-bit addressing 2: Some registers and associated bits • I2C Master mode supports 7 and 10-bit addressing described in this section may not be • I2C port allows bidirectional transfers between available on all devices. Refer to master and slaves Section4.0 “Memory Organization” in this data sheet for device-specific register • Serial clock synchronization for I2C port can be and bit information. used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) 3: There are minimum bit rates of approxi- mately FCY/512. As a result, high • I2C supports multi-master operation, detects bus processor speeds may not support collision and arbitrates accordingly 100Kbit/second operation. See timing • Intelligent Platform Management Interface (IPMI) specifications, IM10 and IM11, and the support “Baud Rate Generator” in the “dsPIC33/ • System Management Bus (SMBus) support PIC24 Family Reference Manual”.  2011-2013 Microchip Technology Inc. DS70000657H-page 273

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 19-1: I2Cx BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Read Shift SCLx/ASCLx Clock I2CxRSR LSb SDAx/ASDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoellitseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read FP/2 DS70000657H-page 274  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 19.1 I2C Resources 19.1.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Inter-Integrated Circuit (I2C)” (DS70330) in the uct page of the Microchip web site for the devices listed “dsPIC33/PIC24 Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2013 Microchip Technology Inc. DS70000657H-page 275

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 19.2 I2C Control Registers REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN(1) A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear at the beginning of every slave data byte transmission. Hardware is clear at the end of every slave address byte reception. Hardware is clear at the end of every slave data byte reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at the beginning of every slave data byte transmission. Hardware is clear at the end of every slave address byte reception. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit(1) 1 = IPMI mode is enabled; all addresses are Acknowledged 0 = IPMI mode disabled bit 10 A10M: 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in I2CxRSR (module is enabled for reception) 0 = General call address disabled Note 1: When performing master operations, ensure that the IPMIEN bit is set to ‘0’. DS70000657H-page 276  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receives clock stretching 0 = Disables software or receives clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware is clear at the end of the master Acknowledge sequence. 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive data byte. 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of the master Stop sequence. 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Repeated Start sequence. 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start sequence. 0 = Start condition is not in progress Note 1: When performing master operations, ensure that the IPMIEN bit is set to ‘0’.  2011-2013 Microchip Technology Inc. DS70000657H-page 277

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware is set or clear at the end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No bus collision detected Hardware is set at detection of a bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when address matches general call address. Hardware is clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at the match of the 2nd byte of the matched 10-bit address. Hardware is clear at Stop detection. bit 7 IWCOL: I2Cx Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software). bit 6 I2COV: I2Cx Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register was still holding the previous byte 0 = No overflow Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at a device address match. Hardware is set by reception of a slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected. DS70000657H-page 278  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – Indicates data transfer is output from the slave 0 = Write – Indicates data transfer is input to the slave Hardware is set or clear after reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of a data transmission.  2011-2013 Microchip Technology Inc. DS70000657H-page 279

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Address Mask Select bits For 10-Bit Address: 1 = Enables masking for bit Ax of incoming message address; bit match is not required in this position 0 = Disables masking for bit Ax; bit match is required in this position For 7-Bit Address (I2CxMSK<6:0> only): 1 = Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position 0 = Disables masking for bit Ax + 1; bit match is required in this position DS70000657H-page 280  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 20.0 UNIVERSAL ASYNCHRONOUS The primary features of the UARTx module are: RECEIVER TRANSMITTER • Full-Duplex, 8 or 9-Bit Data Transmission through (UART) the UxTX and UxRX Pins • Even, Odd or No Parity Options (for 8-bit data) Note1: This data sheet summarizes the • One or Two Stop bits features of the dsPIC33EPXXXGP50X, • Hardware Flow Control Option with UxCTS and dsPIC33EPXXXMC20X/50X and UxRTS Pins PIC24EPXXXGP/MC20X families of devices. It is not intended to be a compre- • Fully Integrated Baud Rate Generator with 16-Bit hensive reference source. To complement Prescaler the information in this data sheet, refer to • Baud Rates Ranging from 4.375 Mbps to 67 bps at “UART” (DS70582) in the “dsPIC33/ 16xmode at 70 MIPS PIC24 Family Reference Manual”, which is • Baud Rates Ranging from 17.5 Mbps to 267 bps at available from the Microchip web site 4xmode at 70 MIPS (www.microchip.com). • 4-Deep First-In First-Out (FIFO) Transmit Data 2: Some registers and associated bits Buffer described in this section may not be • 4-Deep FIFO Receive Data Buffer available on all devices. Refer to • Parity, Framing and Buffer Overrun Error Detection Section4.0 “Memory Organization” in this data sheet for device-specific register • Support for 9-bit mode with Address Detect and bit information. (9th bit = 1) • Transmit and Receive Interrupts The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ • A Separate Interrupt for all UARTx Error Conditions 50X and PIC24EPXXXGP/MC20X family of devices contains two UART modules. • Loopback mode for Diagnostic Support • Support for Sync and Break Characters The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available • Support for Automatic Baud Rate Detection in the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ • IrDA® Encoder and Decoder Logic 50X and PIC24EPXXXGP/MC20X device family. The • 16x Baud Clock Output for IrDA Support UART is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal A simplified block diagram of the UARTx module is computers, LIN/J2602, RS-232 and RS-485 interfaces. shown in Figure20-1. The UARTx module consists of The module also supports a hardware flow control option these key hardware elements: with the UxCTS and UxRTS pins, and also includes an • Baud Rate Generator IrDA® encoder and decoder. • Asynchronous Transmitter Note: Hardware flow control using UxRTS and • Asynchronous Receiver UxCTS is not available on all pin count devices. See the “Pin Diagrams” section for availability. FIGURE 20-1: UARTx SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2011-2013 Microchip Technology Inc. DS70000657H-page 281

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 20.1 UART Helpful Tips 20.2 UART Resources 1. In multi-node, direct-connect UART networks, Many useful resources are provided on the main prod- UART receive inputs react to the uct page of the Microchip web site for the devices listed complementary logic level defined by the in this data sheet. This product page, which can be URXINV bit (UxMODE<4>), which defines the accessed using this link, contains the latest updates Idle state, the default of which is logic high (i.e., and additional information. URXINV = 0). Because remote devices do not Note: In the event you are not able to access the initialize at the same time, it is likely that one of product page using the link above, enter the devices, because the RX line is floating, will this URL in your browser: trigger a Start bit detection and will cause the http://www.microchip.com/wwwproducts/ first byte received, after the device has been ini- Devices.aspx?dDocName=en555464 tialized, to be invalid. To avoid this situation, the user should use a pull-up or pull-down resistor 20.2.1 KEY RESOURCES on the RX pin depending on the value of the URXINV bit. • “UART” (DS70582) in the “dsPIC33/PIC24 a) If URXINV = 0, use a pull-up resistor on the Family Reference Manual” RX pin. • Code Samples b) If URXINV = 1, use a pull-down resistor on • Application Notes the RX pin. • Software Libraries 2. The first character received on a wake-up from • Webinars Sleep mode caused by activity on the UxRX pin • All Related “dsPIC33/PIC24 Family Reference of the UARTx module will be invalid. In Sleep Manual” Sections mode, peripheral clocks are disabled. By the • Development Tools time the oscillator system has restarted and stabilized from Sleep mode, the baud rate bit sampling clock, relative to the incoming UxRX bit timing, is no longer synchronized, resulting in the first character being invalid; this is to be expected. DS70000657H-page 282  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 20.3 UARTx Control Registers REGISTER 20-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Pin Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches(3) 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used(4) 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches(4) 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by PORT latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge; bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled Note 1: Refer to the “UART” (DS70582) section in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). 3: This feature is only available on 44-pin and 64-pin devices. 4: This feature is only available on 64-pin devices.  2011-2013 Microchip Technology Inc. DS70000657H-page 283

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed bit 4 URXINV: UARTx Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: Refer to the “UART” (DS70582) section in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). 3: This feature is only available on 44-pin and 64-pin devices. 4: This feature is only available on 64-pin devices. DS70000657H-page 284  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: UARTx Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA encoded, UxTX Idle state is ‘1’ 0 = IrDA encoded, UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: UARTx Transmit Enable bit(1) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled by the PORT bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer; receive buffer has one or more characters Note 1: Refer to the “UART” (DS70582) section in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.  2011-2013 Microchip Technology Inc. DS70000657H-page 285

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed; clearing a previously set OERR bit (10 transition) resets the receiver buffer and the UxRSR to the empty state bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to the “UART” (DS70582) section in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation. DS70000657H-page 286  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 21.0 ENHANCED CAN (ECAN™) The ECAN module features are as follows: MODULE (dsPIC33EPXXXGP/ • Implementation of the CAN protocol, CAN1.2, MC50X DEVICES ONLY) CAN2.0A and CAN2.0B • Standard and extended data frames Note1: This data sheet summarizes the • 0-8 bytes data length features of the dsPIC33EPXXXGP50X, • Programmable bit rate up to 1 Mbit/sec dsPIC33EPXXXMC20X/50X and • Automatic response to remote transmission PIC24EPXXXGP/MC20X families of requests devices. It is not intended to be a comprehensive reference source. To com- • Up to eight transmit buffers with application speci- plement the information in this data sheet, fied prioritization and abort capability (each buffer refer to “Enhanced Controller Area can contain up to 8 bytes of data) Network (ECAN™)” (DS70353) in the • Up to 32 receive buffers (each buffer can contain “dsPIC33/PIC24 Family Reference Man- up to 8 bytes of data) ual”, which is available from the Microchip • Up to 16 full (Standard/Extended Identifier) web site (www.microchip.com). acceptance filters 2: Some registers and associated bits • Three full acceptance filter masks described in this section may not be • DeviceNet™ addressing support available on all devices. Refer to • Programmable wake-up functionality with Section4.0 “Memory Organization” in integrated low-pass filter this data sheet for device-specific register • Programmable Loopback mode supports self-test and bit information. operation • Signaling via interrupt capabilities for all CAN 21.1 Overview receiver and transmitter error states The Enhanced Controller Area Network (ECAN) • Programmable clock source module is a serial interface, useful for communicat- • Programmable link to Input Capture (IC2) module ing with other CAN modules or microcontroller for time-stamping and network synchronization devices. This interface/protocol was designed to • Low-power Sleep and Idle mode allow communications within noisy environments. The CAN bus module consists of a protocol engine and The dsPIC33EPXXXGP/MC50X devices contain one message buffering/control. The CAN protocol engine ECAN module. handles all functions for receiving and transmitting The ECAN module is a communication controller messages on the CAN bus. Messages are transmitted implementing the CAN 2.0 A/B protocol, as defined in by first loading the appropriate data registers. Status the BOSCH CAN specification. The module supports and errors can be checked by reading the appropriate CAN1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B registers. Any message detected on the CAN bus is Active versions of the protocol. The module implemen- checked for errors and then matched against filters to tation is a full CAN system. The CAN specification is see if it should be received and stored in one of the not covered within this data sheet. The reader can refer receive registers. to the BOSCH CAN specification for further details.  2011-2013 Microchip Technology Inc. DS70000657H-page 287

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 21-1: ECAN™ MODULE BLOCK DIAGRAM RxF15 Filter RxF14 Filter RxF13 Filter RxF12 Filter RxF11 Filter DMA Controller RxF10 Filter RxF9 Filter RxF8 Filter TRB7 TX/RX Buffer Control Register RxF7 Filter TRB6 TX/RX Buffer Control Register RxF6 Filter TRB5 TX/RX Buffer Control Register RxF5 Filter TRB4 TX/RX Buffer Control Register RxF4 Filter TRB3 TX/RX Buffer Control Register RxF3 Filter TRB2 TX/RX Buffer Control Register RxF2 Filter RxM2 Mask TRB1 TX/RX Buffer Control Register RxF1 Filter RxM1 Mask TRB0 TX/RX Buffer Control Register RxF0 Filter RxM0 Mask Transmit Byte Message Assembly Sequencer Buffer Control CPU Configuration Bus Logic CAN Protocol Engine Interrupts CxTx CxRx DS70000657H-page 288  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 21.2 Modes of Operation 21.3 ECAN Resources The ECAN module can operate in one of several Many useful resources are provided on the main prod- operation modes selected by the user. These modes uct page of the Microchip web site for the devices listed include: in this data sheet. This product page, which can be accessed using this link, contains the latest updates • Initialization mode and additional information. • Disable mode • Normal Operation mode Note: In the event you are not able to access the • Listen Only mode product page using the link above, enter • Listen All Messages mode this URL in your browser: http://www.microchip.com/wwwproducts/ • Loopback mode Devices.aspx?dDocName=en555464 Modes are requested by setting the REQOP<2:0> bits (CxCTRL1<10:8>). Entry into a mode is Acknowledged 21.3.1 KEY RESOURCES by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>). The module does not change the mode and the • “Enhanced Controller Area Network (ECAN™)” OPMODEx bits until a change in mode is acceptable, (DS70353) in the “dsPIC33/PIC24 Family generally during bus Idle time, which is defined as at least Reference Manual” 11 consecutive recessive bits. • Code Samples • Application Notes • Software Libraries • Webinars • All Related “dsPIC33/PIC24 Family Reference Manual” Sections • Development Tools  2011-2013 Microchip Technology Inc. DS70000657H-page 289

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 21.4 ECAN Control Registers REGISTER 21-1: CxCTRL1: ECANx CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — — CSIDL ABAT CANCKS REQOP2 REQOP1 REQOP0 bit 15 bit 8 R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0 OPMODE2 OPMODE1 OPMODE0 — CANCAP — — WIN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: ECANx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 ABAT: Abort All Pending Transmissions bit 1 = Signals all transmit buffers to abort transmission 0 = Module will clear this bit when all transmissions are aborted bit 11 CANCKS: ECANx Module Clock (FCAN) Source Select bit 1 = FCAN is equal to 2 * FP 0 = FCAN is equal to FP bit 10-8 REQOP<2:0>: Request Operation Mode bits 111 = Set Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Set Configuration mode 011 = Set Listen Only mode 010 = Set Loopback mode 001 = Set Disable mode 000 = Set Normal Operation mode bit 7-5 OPMODE<2:0>: Operation Mode bits 111 = Module is in Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Module is in Configuration mode 011 = Module is in Listen Only mode 010 = Module is in Loopback mode 001 = Module is in Disable mode 000 = Module is in Normal Operation mode bit 4 Unimplemented: Read as ‘0’ bit 3 CANCAP: CAN Message Receive Timer Capture Event Enable bit 1 = Enables input capture based on CAN message receive 0 = Disables CAN capture bit 2-1 Unimplemented: Read as ‘0’ bit 0 WIN: SFR Map Window Select bit 1 = Uses filter window 0 = Uses buffer window DS70000657H-page 290  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-2: CxCTRL2: ECANx CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — DNCNT4 DNCNT3 DNCNT2 DNCNT1 DNCNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compares up to Data Byte 3, bit 6 with EID<17> • • • 00001 = Compares up to Data Byte 1, bit 7 with EID<0> 00000 = Does not compare data bytes  2011-2013 Microchip Technology Inc. DS70000657H-page 291

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-3: CxVEC: ECANx INTERRUPT CODE REGISTER U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 15 bit 8 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 — ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 • • • 00001 = Filter 1 00000 = Filter 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 ICODE<6:0>: Interrupt Flag Code bits 1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt • • • 0010000-0111111 = Reserved 0001111 = RB15 buffer interrupt • • • 0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 buffer interrupt DS70000657H-page 292  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-4: CxFCTRL: ECANx FIFO CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 DMABS2 DMABS1 DMABS0 — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FSA4 FSA3 FSA2 FSA1 FSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in RAM 101 = 24 buffers in RAM 100 = 16 buffers in RAM 011 = 12 buffers in RAM 010 = 8 buffers in RAM 001 = 6 buffers in RAM 000 = 4 buffers in RAM bit 12-5 Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = Read Buffer RB31 11110 = Read Buffer RB30 • • • 00001 = TX/RX Buffer TRB1 00000 = TX/RX Buffer TRB0  2011-2013 Microchip Technology Inc. DS70000657H-page 293

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-5: CxFIFO: ECANx FIFO STATUS REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FBP5 FBP4 FBP3 FBP2 FBP1 FBP0 bit 15 bit 8 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer DS70000657H-page 294  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWAR RXWAR EWARN bit 15 bit 8 R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXBO: Transmitter in Error State Bus Off bit 1 = Transmitter is in Bus Off state 0 = Transmitter is not in Bus Off state bit 12 TXBP: Transmitter in Error State Bus Passive bit 1 = Transmitter is in Bus Passive state 0 = Transmitter is not in Bus Passive state bit 11 RXBP: Receiver in Error State Bus Passive bit 1 = Receiver is in Bus Passive state 0 = Receiver is not in Bus Passive state bit 10 TXWAR: Transmitter in Error State Warning bit 1 = Transmitter is in Error Warning state 0 = Transmitter is not in Error Warning state bit 9 RXWAR: Receiver in Error State Warning bit 1 = Receiver is in Error Warning state 0 = Receiver is not in Error Warning state bit 8 EWARN: Transmitter or Receiver in Error State Warning bit 1 = Transmitter or receiver is in Error Warning state 0 = Transmitter or receiver is not in Error Warning state bit 7 IVRIF: Invalid Message Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF<13:8>) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2011-2013 Microchip Technology Inc. DS70000657H-page 295

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER (CONTINUED) bit 1 RBIF: RX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000657H-page 296  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-7: CxINTE: ECANx INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Invalid Message Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 WAKIE: Bus Wake-up Activity Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 ERRIE: Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 RBIE: RX Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 TBIE: TX Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2011-2013 Microchip Technology Inc. DS70000657H-page 297

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-8: CxEC: ECANx TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits REGISTER 21-9: CxCFG1: ECANx BAUD RATE CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 11 1111 = TQ = 2 x 64 x 1/FCAN • • • 00 0010 = TQ = 2 x 3 x 1/FCAN 00 0001 = TQ = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN DS70000657H-page 298  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-10: CxCFG2: ECANx BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x — WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 WAKFIL: Select CAN Bus Line Filter for Wake-up bit 1 = Uses CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 13-11 Unimplemented: Read as ‘0’ bit 10-8 SEG2PH<2:0>: Phase Segment 2 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of SEG1PHx bits or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN Bus Line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 2-0 PRSEG<2:0>: Propagation Time Segment bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ  2011-2013 Microchip Technology Inc. DS70000657H-page 299

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-11: CxFEN1: ECANx ACCEPTANCE FILTER ENABLE REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FLTEN<15:0>: Enable Filter n to Accept Messages bits 1 = Enables Filter n 0 = Disables Filter n REGISTER 21-12: CxBUFPNT1: ECANx FILTER 0-3 BUFFER POINTER REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3BP<3:0> F2BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F1BP<3:0> F0BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F3BP<3:0>: RX Buffer Mask for Filter 3 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bits<15:12>) bit 7-4 F1BP<3:0>: RX Buffer Mask for Filter 1 bits (same values as bits<15:12>) bit 3-0 F0BP<3:0>: RX Buffer Mask for Filter 0 bits (same values as bits<15:12>) DS70000657H-page 300  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-13: CxBUFPNT2: ECANx FILTER 4-7 BUFFER POINTER REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP<3:0> F6BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP<3:0> F4BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F7BP<3:0>: RX Buffer Mask for Filter 7 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F6BP<3:0>: RX Buffer Mask for Filter 6 bits (same values as bits<15:12>) bit 7-4 F5BP<3:0>: RX Buffer Mask for Filter 5 bits (same values as bits<15:12>) bit 3-0 F4BP<3:0>: RX Buffer Mask for Filter 4 bits (same values as bits<15:12>) REGISTER 21-14: CxBUFPNT3: ECANx FILTER 8-11 BUFFER POINTER REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11BP<3:0> F10BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F9BP<3:0> F8BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F11BP<3:0>: RX Buffer Mask for Filter 11 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F10BP<3:0>: RX Buffer Mask for Filter 10 bits (same values as bits<15:12>) bit 7-4 F9BP<3:0>: RX Buffer Mask for Filter 9 bits (same values as bits<15:12>) bit 3-0 F8BP<3:0>: RX Buffer Mask for Filter 8 bits (same values as bits<15:12>)  2011-2013 Microchip Technology Inc. DS70000657H-page 301

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-15: CxBUFPNT4: ECANx FILTER 12-15 BUFFER POINTER REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP<3:0> F14BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP<3:0> F12BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F15BP<3:0>: RX Buffer Mask for Filter 15 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F14BP<3:0>: RX Buffer Mask for Filter 14 bits (same values as bits<15:12>) bit 7-4 F13BP<3:0>: RX Buffer Mask for Filter 13 bits (same values as bits<15:12>) bit 3-0 F12BP<3:0>: RX Buffer Mask for Filter 12 bits (same values as bits<15:12>) DS70000657H-page 302  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-16: CxRXFnSID: ECANx ACCEPTANCE FILTER n STANDARD IDENTIFIER REGISTER (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Message address bit, SIDx, must be ‘1’ to match filter 0 = Message address bit, SIDx, must be ‘0’ to match filter bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit If MIDE = 1: 1 = Matches only messages with Extended Identifier addresses 0 = Matches only messages with Standard Identifier addresses If MIDE = 0: Ignores EXIDE bit. bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Message address bit, EIDx, must be ‘1’ to match filter 0 = Message address bit, EIDx, must be ‘0’ to match filter  2011-2013 Microchip Technology Inc. DS70000657H-page 303

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-17: CxRXFnEID: ECANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTER (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Message address bit, EIDx, must be ‘1’ to match filter 0 = Message address bit, EIDx, must be ‘0’ to match filter REGISTER 21-18: CxFMSKSEL1: ECANx FILTER 7-0 MASK SELECTION REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bits 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bits (same values as bits<15:14>) bit 11-10 F5MSK<1:0>: Mask Source for Filter 5 bits (same values as bits<15:14>) bit 9-8 F4MSK<1:0>: Mask Source for Filter 4 bits (same values as bits<15:14>) bit 7-6 F3MSK<1:0>: Mask Source for Filter 3 bits (same values as bits<15:14>) bit 5-4 F2MSK<1:0>: Mask Source for Filter 2 bits (same values as bits<15:14>) bit 3-2 F1MSK<1:0>: Mask Source for Filter 1 bits (same values as bits<15:14>) bit 1-0 F0MSK<1:0>: Mask Source for Filter 0 bits (same values as bits<15:14>) DS70000657H-page 304  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-19: CxFMSKSEL2: ECANx FILTER 15-8 MASK SELECTION REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bits 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F14MSK<1:0>: Mask Source for Filter 14 bits (same values as bits<15:14>) bit 11-10 F13MSK<1:0>: Mask Source for Filter 13 bits (same values as bits<15:14>) bit 9-8 F12MSK<1:0>: Mask Source for Filter 12 bits (same values as bits<15:14>) bit 7-6 F11MSK<1:0>: Mask Source for Filter 11 bits (same values as bits<15:14>) bit 5-4 F10MSK<1:0>: Mask Source for Filter 10 bits (same values as bits<15:14>) bit 3-2 F9MSK<1:0>: Mask Source for Filter 9 bits (same values as bits<15:14>) bit 1-0 F8MSK<1:0>: Mask Source for Filter 8 bits (same values as bits<15:14>)  2011-2013 Microchip Technology Inc. DS70000657H-page 305

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-20: CxRXMnSID: ECANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER REGISTER (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Includes bit, SIDx, in filter comparison 0 = SIDx bit is a don’t care in filter comparison bit 4 Unimplemented: Read as ‘0’ bit 3 MIDE: Identifier Receive Mode bit 1 = Matches only message types (standard or extended address) that correspond to EXIDE bit in the filter 0 = Matches either standard or extended address message if filters match (i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)) bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Includes bit, EIDx, in filter comparison 0 = EIDx bit is a don’t care in filter comparison REGISTER 21-21: CxRXMnEID: ECANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER REGISTER (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Includes bit, EIDx, in filter comparison 0 = EIDx bit is a don’t care in filter comparison DS70000657H-page 306  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-22: CxRXFUL1: ECANx RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (cleared by user software) REGISTER 21-23: CxRXFUL2: ECANx RECEIVE BUFFER FULL REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (cleared by user software)  2011-2013 Microchip Technology Inc. DS70000657H-page 307

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-24: CxRXOVF1: ECANx RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition (cleared by user software) REGISTER 21-25: CxRXOVF2: ECANx RECEIVE BUFFER OVERFLOW REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition (cleared by user software) DS70000657H-page 308  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 21-26: CxTRmnCON: ECANx TX/RX BUFFER mn CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI1 TXnPRI0 bit 15 bit 8 R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENm TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm RTRENm TXmPRI1 TXmPRI0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 See Definition for bits<7:0>, Controls Buffer n bit 7 TXENm: TX/RX Buffer Selection bit 1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer bit 6 TXABTm: Message Aborted bit(1) 1 = Message was aborted 0 = Message completed transmission successfully bit 5 TXLARBm: Message Lost Arbitration bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERRm: Error Detected During Transmission bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQm: Message Send Request bit 1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent 0 = Clearing the bit to ‘0’ while set requests a message abort bit 2 RTRENm: Auto-Remote Transmit Enable bit 1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: This bit is cleared when TXREQ is set. Note: The buffers, SID, EID, DLC, Data Field, and Receive Status registers are located in DMA RAM.  2011-2013 Microchip Technology Inc. DS70000657H-page 309

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 21.5 ECAN Message Buffers ECAN Message Buffers are part of RAM memory. They are not ECAN Special Function Registers. The user application must directly write into the RAM area that is configured for ECAN Message Buffers. The location and size of the buffer area is defined by the user application. BUFFER 21-1: ECAN™ MESSAGE BUFFER WORD 0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — SID10 SID9 SID8 SID7 SID6 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-2 SID<10:0>: Standard Identifier bits bit 1 SRR: Substitute Remote Request bit When IDE = 0: 1 = Message will request remote transmission 0 = Normal message When IDE = 1: The SRR bit must be set to ‘1’. bit 0 IDE: Extended Identifier bit 1 = Message will transmit Extended Identifier 0 = Message will transmit Standard Identifier BUFFER 21-2: ECAN™ MESSAGE BUFFER WORD 1 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — — — EID17 EID16 EID15 EID14 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 EID<17:6>: Extended Identifier bits DS70000657H-page 310  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X (BUFFER 21-3: ECAN™ MESSAGE BUFFER WORD 2 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1 bit 15 bit 8 U-x U-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 EID<5:0>: Extended Identifier bits bit 9 RTR: Remote Transmission Request bit When IDE = 1: 1 = Message will request remote transmission 0 = Normal message When IDE = 0: The RTR bit is ignored. bit 8 RB1: Reserved Bit 1 User must set this bit to ‘0’ per CAN protocol. bit 7-5 Unimplemented: Read as ‘0’ bit 4 RB0: Reserved Bit 0 User must set this bit to ‘0’ per CAN protocol. bit 3-0 DLC<3:0>: Data Length Code bits BUFFER 21-4: ECAN™ MESSAGE BUFFER WORD 3 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 1 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 1<15:8>: ECAN Message Byte 1 bits bit 7-0 Byte 0<7:0>: ECAN Message Byte 0 bits  2011-2013 Microchip Technology Inc. DS70000657H-page 311

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X BUFFER 21-5: ECAN™ MESSAGE BUFFER WORD 4 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 3 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 3<15:8>: ECAN Message Byte 3 bits bit 7-0 Byte 2<7:0>: ECAN Message Byte 2 bits BUFFER 21-6: ECAN™ MESSAGE BUFFER WORD 5 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 5 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 4 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 5<15:8>: ECAN Message Byte 5 bits bit 7-0 Byte 4<7:0>: ECAN Message Byte 4 bits DS70000657H-page 312  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X BUFFER 21-7: ECAN™ MESSAGE BUFFER WORD 6 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 7 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 7<15:8>: ECAN Message Byte 7 bits bit 7-0 Byte 6<7:0>: ECAN Message Byte 6 bits BUFFER 21-8: ECAN™ MESSAGE BUFFER WORD 7 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — FILHIT4(1) FILHIT3(1) FILHIT2(1) FILHIT1(1) FILHIT0(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Code bits(1) Encodes number of filter that resulted in writing this buffer. bit 7-0 Unimplemented: Read as ‘0’ Note 1: Only written by module for receive buffers, unused for transmit buffers.  2011-2013 Microchip Technology Inc. DS70000657H-page 313

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 314  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 22.0 CHARGE TIME The Charge Time Measurement Unit is a flexible analog MEASUREMENT UNIT (CTMU) module that provides accurate differential time measure- ment between pulse sources, as well as asynchronous pulse generation. Its key features include: Note1: This data sheet summarizes the features of the dsPIC33EPXXXGP50X, • Four Edge Input Trigger Sources dsPIC33EPXXXMC20X/50X and • Polarity Control for Each Edge Source PIC24EPXXXGP/MC20X family of • Control of Edge Sequence devices. It is not intended to be a • Control of Response to Edges comprehensive reference source. To complement the information in this data • Precise Time Measurement Resolution of 1 ns sheet, refer to “Charge Time Measure- • Accurate Current Source Suitable for Capacitive ment Unit (CTMU)” (DS70661) in the Measurement “dsPIC33/PIC24 Family Reference Man- • On-Chip Temperature Measurement using a ual”, which is available on the Microchip Built-in Diode web site (www.microchip.com). Together with other on-chip analog modules, the CTMU 2: Some registers and associated bits can be used to precisely measure time, measure described in this section may not be capacitance, measure relative changes in capacitance available on all devices. Refer to or generate output pulses that are independent of the Section4.0 “Memory Organization” in system clock. this data sheet for device-specific register The CTMU module is ideal for interfacing with and bit information. capacitive-based sensors.The CTMU is controlled through three registers: CTMUCON1, CTMUCON2 and CTMUICON. CTMUCON1 and CTMUCON2 enable the module and control edge source selection, edge source polarity selection and edge sequencing. The CTMUICON register controls the selection and trim of the current source.  2011-2013 Microchip Technology Inc. DS70000657H-page 315

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 22-1: CTMU BLOCK DIAGRAM CTMUCON1 or CTMUCON2(1) CTMUICON ITRIM<5:0> IRNG<1:0> Current Source CTED1 Edge CTED2 CLoongtircol EEDDGG12SSTTAATT Current TGEN CCLoTonMgtircUol ATrnigagloegr-to-Digital Control Timer1 OC1 Pulse IC1 CTMUI to ADC(2) Generator CTPLS CMP1 CTMUP CTMU TEMP(3) CTMU C1IN1- Temperature Sensor CDelay CMP1 External Capacitor for Pulse Generation ADC CH0(5) Current Control Selection TGEN EDG1STAT, EDG2STAT CTMU TEMP 0 EDG1STAT = EDG2STAT CTMUI to ADC(2) 0 EDG1STAT  EDG2STAT CTMUP 1 EDG1STAT  EDG2STAT Internal Current Flow(4) 1 EDG1STAT = EDG2STAT Note1: When the CTMU is not actively used, set TGEN = 1, and ensure that EDG1STAT = EDG2STAT. All other settings allow current to flow into the ADC or the C1IN1- pin. If using the ADC for other purposes besides the CTMU, set IDISSEN = 0. If IDISSEN is set to ‘1’, it will short the output of the ADC CH0 MUX to VSS. 2: CTMUI connects to the output of the ADC CH0 MUX. When CTMU current is steered into this node, the current will flow out through the selected ADC channel determined by the CH0 MUX (see the CH0Sx bits in the AD1CHS0 register). 3: CTMU TEMP connects to one of the ADC CH0 inputs; see CH0SA and CH0SB (AD1CHS0<12:8,4:0). 4: If TGEN = 1 and EDG1STAT = EDG2STAT, CTMU current source is still enabled and may be shunted to VSS internally. This should be considered in low-power applications. 5: The switch connected to ADC CH0 is closed when IDISSEN (CTMUCON1<9>) = 1, and opened when IDISSEN = 0. 22.1 CTMU Resources 22.1.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Charge Time Measurement Unit (CTMU)” uct page of the Microchip web site for the devices listed (DS70661) in the “dsPIC33/PIC24 Family in this data sheet. This product page, which can be Reference Manual” accessed using this link, contains the latest updates • Code Samples and additional information. • Application Notes • Software Libraries Note: In the event you are not able to access the product page using the link above, enter • Webinars this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools DS70000657H-page 316  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 22.2 CTMU Control Registers REGISTER 22-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN(1) CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Hardware modules are used to trigger edges (TMRx, CTEDx, etc.) 0 = Software is used to trigger edges (manual set of EDGxSTAT) bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit(1) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: ADC Trigger Control bit 1 = CTMU triggers ADC start of conversion 0 = CTMU does not trigger ADC start of conversion bit 7-0 Unimplemented: Read as ‘0’ Note 1: The ADC module Sample-and-Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitance measurement must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.  2011-2013 Microchip Technology Inc. DS70000657H-page 317

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 22-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 EDG1MOD: Edge 1 Edge Sampling Mode Selection bit 1 = Edge 1 is edge-sensitive 0 = Edge 1 is level-sensitive bit 14 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response bit 13-10 EDG1SEL<3:0>: Edge 1 Source Select bits 1xxx = Reserved 01xx = Reserved 0011 = CTED1 pin 0010 = CTED2 pin 0001 = OC1 module 0000 = Timer1 module bit 9 EDG2STAT: Edge 2 Status bit Indicates the status of Edge 2 and can be written to control the edge source. 1 = Edge 2 has occurred 0 = Edge 2 has not occurred bit 8 EDG1STAT: Edge 1 Status bit Indicates the status of Edge 1 and can be written to control the edge source. 1 = Edge 1 has occurred 0 = Edge 1 has not occurred bit 7 EDG2MOD: Edge 2 Edge Sampling Mode Selection bit 1 = Edge 2 is edge-sensitive 0 = Edge 2 is level-sensitive bit 6 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = Reserved 01xx = Reserved 0100 = CMP1 module 0011 = CTED2 pin 0010 = CTED1 pin 0001 = OC1 module 0000 = IC1 module bit 1-0 Unimplemented: Read as ‘0’ DS70000657H-page 318  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 22-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current + 62% 011110 = Maximum positive change from nominal current + 60% • • • 000010 = Minimum positive change from nominal current + 4% 000001 = Minimum positive change from nominal current + 2% 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current – 2% 111110 = Minimum negative change from nominal current – 4% • • • 100010 = Maximum negative change from nominal current – 60% 100001 = Maximum negative change from nominal current – 62% bit 9-8 IRNG<1:0>: Current Source Range Select bits 11 = 100  Base Current(2) 10 = 10  Base Current(2) 01 = Base Current Level(2) 00 = 1000  Base Current(1,2) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This current range is not available to be used with the internal temperature measurement diode. 2: Refer to the CTMU Current Source Specifications (Table30-56) in Section30.0 “Electrical Characteristics” for the current range selection values.  2011-2013 Microchip Technology Inc. DS70000657H-page 319

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 320  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 23.0 10-BIT/12-BIT 23.1 Key Features ANALOG-TO-DIGITAL 23.1.1 10-BIT ADC CONFIGURATION CONVERTER (ADC) The 10-bit ADC configuration has the following key Note1: This data sheet summarizes the features: features of the dsPIC33EPXXXGP50X, • Successive Approximation (SAR) conversion dsPIC33EPXXXMC20X/50X and • Conversion speeds of up to 1.1 Msps PIC24EPXXXGP/MC20X families of • Up to 16 analog input pins devices. It is not intended to be a comprehensive reference source. To • Connections to three internal op amps complement the information in this data • Connections to the Charge Time Measurement Unit sheet, refer to “Analog-to-Digital (CTMU) and temperature measurement diode Converter (ADC)” (DS70621) in the • Channel selection and triggering can be controlled “dsPIC33/PIC24 Family Reference by the Peripheral Trigger Generator (PTG) Manual”, which is available from the • External voltage reference input pins Microchip web site (www.microchip.com). • Simultaneous sampling of: 2: Some registers and associated bits - Up to four analog input pins described in this section may not be - Three op amp outputs available on all devices. Refer to - Combinations of analog inputs and op amp Section4.0 “Memory Organization” in outputs this data sheet for device-specific register and bit information. • Automatic Channel Scan mode • Selectable conversion Trigger source The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ • Selectable Buffer Fill modes 50X and PIC24EPXXXGP/MC20X devices have one • Four result alignment options (signed/unsigned, ADC module. The ADC module supports up to fractional/integer) 16analog input channels. • Operation during CPU Sleep and Idle modes On ADC1, the AD12B bit (AD1CON1<10>) allows the ADC module to be configured by the user as either a 23.1.2 12-BIT ADC CONFIGURATION 10-bit, 4 Sample-and-Hold (S&H) ADC (default configuration) or a 12-bit, 1 S&H ADC. The 12-bit ADC configuration supports all the features listed above, with the exception of the following: Note: The ADC module needs to be disabled • In the 12-bit configuration, conversion speeds of before modifying the AD12B bit. up to 500 ksps are supported • There is only one S&H amplifier in the 12-bit configuration; therefore, simultaneous sampling of multiple channels is not supported. Depending on the particular device pinout, the ADC can have up to 16 analog input pins, designated AN0 through AN15. These analog inputs are shared with opamp inputs and outputs, comparator inputs, and external voltage references. When op amp/comparator functionality is enabled, or an external voltage refer- ence is used, the analog input that shares that pin is no longer available. The actual number of analog input pins, op amps and external voltage reference input configuration depends on the specific device. A block diagram of the ADC module is shown in Figure23-1. Figure23-2 provides a diagram of the ADC conversion clock period.  2011-2013 Microchip Technology Inc. DS70000657H-page 321

D FIGURE 23-1: ADC MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS d S s 70 P 000 TAhDisC dcioangnraemct iodne poipcttsio anlsl otof tthhee faovuari lSa&blHe 00000 Channel Scan 1 IC 657H aCmHp1l,i fCieHrs2, awnhdic Ch Ha3re. designated: CH0, OAAN10--OANA3x From CTMU CH0SA<4:0>(3) 0 33E -p The ANx analog pins or op amp outputs CTMU Temp Current Source (CTMUI) P age 322 aebCrryHes O tchtNohrneoxn u, egCSchHtF et1Rhd2e 3t oSmc oxtuh nlaettinr poCdlle H Cx0ebH-riC1sts,2H, 3c3oN CnaxHtm.ro0plSlleifxid-, Open C11H101S1x +–CH0 S&H0 CH0SB<4:0>(3C)SCNA AB CH0Sx XXXG P VREFL 0 1 CH0NA(3) A CH0Nx 50 AN0/OA2OUT/RA0 CH0NB(3) B X CH0Nx , d PGEC1/AN4/C1IN1+/RPI34/RB2 C++MP1 OPMODE 0 + S&H1 CH123SA A sP PGED1/AN5/C1IN1-/RP35/RB3 /––OA1 1 –CH1 CH123SB B CH123Sx IC OA1 CH123Sx 3 PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 3 VREFL 0x E 10 CH123NA<2:0> A CH123Nx PX AN9/RPI27/RA11 11 CH123NB<2:0> B X X AN1/C2IN1+/RA1 CH123Nx M + OPMODE 0 + S&H2 Alternate Input C 1 CH2 ALTS (MUXA/MUXB) 20 – – Selection X OA2 CH123Sx / 5 VREF+(1) AVDD VREF-(1) AVSS 0 VREFL 0x X 10 A AN10/RPI28/RA12 11 N PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 D CH123Nx  2011-2 AN8/C3INAN1+7//UC13RINT1S-//CBC4ILNK11-//RRCC12 +– OPOMAO3D(5E) CH10123Sx +–CH3 S&H3 VREFHVCFG<2:0>VREFL AAADDDCCC111BBBUUUFFF012(((444))) PIC24E 013 M AN6/OA3OUT/C4IN1+/OCFB/RC0 VREFL 0x SAR ADC PXX ic 10 X ro AN11/C1IN2-/U1CTS/RC11 11 G c hip T CH123Nx AADDCC11BBUUFFEF((44)) P/M e c Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. C h n 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 2 olo 3: These bits can be updated with Step commands from the PTG module. See Section24.0 “Peripheral Trigger Generator (PTG) Module” for more information. 0 g 4: When ADDMAEN (AD1CON4<8>) = 1, enabling DMA, only ADC1BUF0 is used. X y In 5: OA3 is not available for 28-pin devices. c .

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 23-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3<15> ADC Internal RC Clock(2) 1 TAD AD1CON3<7:0> 0 6 ADC Conversion TP(1) Clock Multiplier 1, 2, 3, 4, 5,..., 256 Note 1: TP = 1/FP. 2: See the ADC electrical specifications in Section30.0 “Electrical Characteristics” for the exact RC clock value.  2011-2013 Microchip Technology Inc. DS70000657H-page 323

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 23.2 ADC Helpful Tips 5. Enabling op amps, comparator inputs and exter- nal voltage references can limit the availability of 1. The SMPIx control bits in the AD1CON2 register: analog inputs (ANx pins). For example, when Op a) Determine when the ADC interrupt flag is Amp 2 is enabled, the pins for AN0, AN1 and AN2 set and an interrupt is generated, if are used by the op amp’s inputs and output. This enabled. negates the usefulness of Alternate Input mode b) When the CSCNA bit in the AD1CON2 reg- since the MUXA selections use AN0-AN2. isters is set to ‘1’, this determines when the Carefully study the ADC block diagram to deter- ADC analog scan channel list, defined in mine the configuration that will best suit your the AD1CSSL/AD1CSSH registers, starts application. Configuration examples are avail- over from the beginning. able in the “Analog-to-Digital Converter c) When the DMA peripheral is not used (ADC)” (DS70621) section in the “dsPIC33/ (ADDMAEN = 0), this determines when the PIC24 Family Reference Manual”. ADC Result Buffer Pointer to ADC1BUF0- ADC1BUFF gets reset back to the 23.3 ADC Resources beginning at ADC1BUF0. Many useful resources are provided on the main prod- d) When the DMA peripheral is used uct page of the Microchip web site for the devices listed (ADDMAEN = 1), this determines when the in this data sheet. This product page, which can be DMA Address Pointer is incremented after a accessed using this link, contains the latest updates sample/conversion operation. ADC1BUF0 is and additional information. the only ADC buffer used in this mode. The ADC Result Buffer Pointer to ADC1BUF0- Note: In the event you are not able to access the ADC1BUFF gets reset back to the beginning product page using the link above, enter at ADC1BUF0. The DMA address is this URL in your browser: incremented after completion of every 32nd http://www.microchip.com/wwwproducts/ sample/conversion operation. Conversion Devices.aspx?dDocName=en555464 results are stored in the ADC1BUF0 register for transfer to RAM using DMA. 23.3.1 KEY RESOURCES 2. When the DMA module is disabled • “Analog-to-Digital Converter (ADC)” (ADDMAEN= 0), the ADC has 16 result buffers. (DS70621) in the “dsPIC33/PIC24 Family ADC conversion results are stored sequentially Reference Manual” in ADC1BUF0-ADC1BUFF, regardless of which • Code Samples analog inputs are being used subject to the • Application Notes SMPIx bits and the condition described in 1c) • Software Libraries above. There is no relationship between the ANx input being measured and which ADC • Webinars buffer (ADC1BUF0-ADC1BUFF) that the • All Related “dsPIC33/PIC24 Family Reference conversion results will be placed in. Manual” Sections 3. When the DMA module is enabled • Development Tools (ADDMAEN= 1), the ADC module has only 1ADC result buffer (i.e., ADC1BUF0) per ADC peripheral and the ADC conversion result must be read, either by the CPU or DMA Controller, before the next ADC conversion is complete to avoid overwriting the previous value. 4. The DONE bit (AD1CON1<0>) is only cleared at the start of each conversion and is set at the completion of the conversion, but remains set indefinitely, even through the next sample phase until the next conversion begins. If application code is monitoring the DONE bit in any kind of software loop, the user must consider this behav- ior because the CPU code execution is faster than the ADC. As a result, in Manual Sample mode, particularly where the user’s code is set- ting the SAMP bit (AD1CON1<1>), the DONE bit should also be cleared by the user application just before setting the SAMP bit. DS70000657H-page 324  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 23.4 ADC Control Registers REGISTER 23-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC, HS R/C-0, HC, HS SSRC2 SSRC1 SSRC0 SSRCG SIMSAM ASAM SAMP DONE(3) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC1 Operating Mode bit 1 = ADC module is operating 0 = ADC is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: ADC1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 ADDMABM: DMA Buffer Build Mode bit 1 = DMA buffers are written in the order of conversion; the module provides an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer 0 = DMA buffers are written in Scatter/Gather mode; the module provides a Scatter/Gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer. bit 11 Unimplemented: Read as ‘0’ bit 10 AD12B: ADC1 10-Bit or 12-Bit Operation Mode bit 1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation bit 9-8 FORM<1:0>: Data Output Format bits For 10-Bit Operation: 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>) 00 = Integer (DOUT = 0000 00dd dddd dddd) For 12-Bit Operation: 11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>) 10 = Fractional (DOUT = dddd dddd dddd 0000) 01 = Signed integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>) 00 = Integer (DOUT = 0000 dddd dddd dddd) Note 1: See Section24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection. 2: This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 3: Do not clear the DONE bit in software if Auto-Sample is enabled (ASAM = 1).  2011-2013 Microchip Technology Inc. DS70000657H-page 325

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 23-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 7-5 SSRC<2:0>: Sample Trigger Source Select bits If SSRCG = 1: 111 = Reserved 110 = PTGO15 primary trigger compare ends sampling and starts conversion(1) 101 = PTGO14 primary trigger compare ends sampling and starts conversion(1) 100 = PTGO13 primary trigger compare ends sampling and starts conversion(1) 011 = PTGO12 primary trigger compare ends sampling and starts conversion(1) 010 = PWM Generator 3 primary trigger compare ends sampling and starts conversion(2) 001 = PWM Generator 2 primary trigger compare ends sampling and starts conversion(2) 000 = PWM Generator 1 primary trigger compare ends sampling and starts conversion(2) If SSRCG = 0: 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU ends sampling and starts conversion 101 = Reserved 100 = Timer5 compare ends sampling and starts conversion 011 = PWM primary Special Event Trigger ends sampling and starts conversion(2) 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on the INT0 pin ends sampling and starts conversion 000 = Clearing the Sample bit (SAMP) ends sampling and starts conversion (Manual mode) bit 4 SSRCG: Sample Trigger Source Group bit See SSRC<2:0> for details. bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) In 12-bit mode (AD21B = 1), SIMSAM is Unimplemented and is Read as ‘0’: 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence bit 2 ASAM: ADC1 Sample Auto-Start bit 1 = Sampling begins immediately after the last conversion; SAMP bit is auto-set 0 = Sampling begins when the SAMP bit is set bit 1 SAMP: ADC1 Sample Enable bit 1 = ADC Sample-and-Hold amplifiers are sampling 0 = ADC Sample-and-Hold amplifiers are holding If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC<2:0> = 000, software can write ‘0’ to end sampling and start conversion. If SSRC<2:0> 000, automatically cleared by hardware to end sampling and start conversion. bit 0 DONE: ADC1 Conversion Status bit(3) 1 = ADC conversion cycle has completed 0 = ADC conversion has not started or is in progress Automatically set by hardware when the ADC conversion is complete. Software can write ‘0’ to clear the DONE status bit (software is not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress. Automatically cleared by hardware at the start of a new conversion. Note 1: See Section24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection. 2: This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 3: Do not clear the DONE bit in software if Auto-Sample is enabled (ASAM = 1). DS70000657H-page 326  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 23-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 — — CSCNA CHPS1 CHPS0 bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits Value VREFH VREFL 000 AVDD Avss 001 External VREF+ Avss 010 AVDD External VREF- 011 External VREF+ External VREF- 1xx AVDD AVSS bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Input Scan Select bit 1 = Scans inputs for CH0+ during Sample MUXA 0 = Does not scan inputs bit 9-8 CHPS<1:0>: Channel Select bits In 12-bit mode (AD21B = 1), the CHPS<1:0> bits are Unimplemented and are Read as ‘0’: 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling the second half of the buffer; the user application should access data in the first half of the buffer 0 = ADC is currently filling the first half of the buffer; the user application should access data in the second half of the buffer bit 6-2 SMPI<4:0>: Increment Rate bits When ADDMAEN = 0: x1111 = Generates interrupt after completion of every 16th sample/conversion operation x1110 = Generates interrupt after completion of every 15th sample/conversion operation • • • x0001 = Generates interrupt after completion of every 2nd sample/conversion operation x0000 = Generates interrupt after completion of every sample/conversion operation When ADDMAEN = 1: 11111 = Increments the DMA address after completion of every 32nd sample/conversion operation 11110 = Increments the DMA address after completion of every 31st sample/conversion operation • • • 00001 = Increments the DMA address after completion of every 2nd sample/conversion operation 00000 = Increments the DMA address after completion of every sample/conversion operation  2011-2013 Microchip Technology Inc. DS70000657H-page 327

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 23-2: AD1CON2: ADC1 CONTROL REGISTER 2 (CONTINUED) bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts the buffer filling the first half of the buffer on the first interrupt and the second half of the buffer on next interrupt 0 = Always starts filling the buffer from the start address. bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample MUXA on first sample and Sample MUXB on next sample 0 = Always uses channel input selects for Sample MUXA DS70000657H-page 328  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 23-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC4(1) SAMC3(1) SAMC2(1) SAMC1(1) SAMC0(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7(2) ADCS6(2) ADCS5(2) ADCS4(2) ADCS3(2) ADCS2(2) ADCS1(2) ADCS0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: ADC1 Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1) 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: ADC1 Conversion Clock Select bits(2) 11111111 = TP • (ADCS<7:0> + 1) = TP •256 = TAD • • • 00000010 = TP • (ADCS<7:0> + 1) = TP •3 = TAD 00000001 = TP • (ADCS<7:0> + 1) = TP •2 = TAD 00000000 = TP • (ADCS<7:0> + 1) = TP •1 = TAD Note 1: This bit is only used if SSRC<2:0> (AD1CON1<7:5>) = 111 and SSRCG (AD1CON1<4>) = 0. 2: This bit is not used if ADRC (AD1CON3<15>) = 1.  2011-2013 Microchip Technology Inc. DS70000657H-page 329

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 23-4: AD1CON4: ADC1 CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADDMAEN bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DMABL2 DMABL1 DMABL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 ADDMAEN: ADC1 DMA Enable bit 1 = Conversion results are stored in the ADC1BUF0 register for transfer to RAM using DMA 0 = Conversion results are stored in ADC1BUF0 through ADC1BUFF registers; DMA will not be used bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input DS70000657H-page 330  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 23-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NB1 CH123NB0 CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NA1 CH123NA0 CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample MUXB bits In 12-bit mode (AD21B = 1), CH123NB is Unimplemented and is Read as ‘0’: ADC Channel Value CH1 CH2 CH3 11 AN9 AN10 AN11 10(1,2) OA3/AN6 AN7 AN8 0x VREFL VREFL VREFL bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample MUXB bit In 12-bit mode (AD21B = 1), CH123SB is Unimplemented and is Read as ‘0’: ADC Channel Value CH1 CH2 CH3 1(2) OA1/AN3 OA2/AN0 OA3/AN6 0(1,2) OA2/AN0 AN1 AN2 bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample MUXA bits In 12-bit mode (AD21B = 1), CH123NA is Unimplemented and is Read as ‘0’: ADC Channel Value CH1 CH2 CH3 11 AN9 AN10 AN11 10(1,2) OA3/AN6 AN7 AN8 0x VREFL VREFL VREFL Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure23-1 to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3. 2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1); otherwise, the ANx input is used.  2011-2013 Microchip Technology Inc. DS70000657H-page 331

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 23-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER (CONTINUED) bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample MUXA bit In 12-bit mode (AD21B = 1), CH123SA is Unimplemented and is Read as ‘0’: ADC Channel Value CH1 CH2 CH3 1(2) OA1/AN3 OA2/AN0 OA3/AN6 0(1,2) OA2/AN0 AN1 AN2 Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure23-1 to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3. 2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1); otherwise, the ANx input is used. DS70000657H-page 332  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 23-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — CH0SB4(1) CH0SB3(1) CH0SB2(1) CH0SB1(1) CH0SB0(1) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA4(1) CH0SA3(1) CH0SA2(1) CH0SA1(1) CH0SA0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for Sample MUXB bit 1 = Channel 0 negative input is AN1(1) 0 = Channel 0 negative input is VREFL bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample MUXB bits(1) 11111 = Open; use this selection with CTMU capacitive and time measurement 11110 = Channel 0 positive input is connected to the CTMU temperature measurement diode (CTMU TEMP) 11101 = Reserved 11100 = Reserved 11011 = Reserved 11010 = Channel 0 positive input is the output of OA3/AN6(2,3) 11001 = Channel 0 positive input is the output of OA2/AN0(2) 11000 = Channel 0 positive input is the output of OA1/AN3(2) 10111 = Reserved • • • 10000 = Reserved 01111 = Channel 0 positive input is AN15(3) 01110 = Channel 0 positive input is AN14(3) 01101 = Channel 0 positive input is AN13(3) • • • 00010 = Channel 0 positive input is AN2(3) 00001 = Channel 0 positive input is AN1(3) 00000 = Channel 0 positive input is AN0(3) bit 7 CH0NA: Channel 0 Negative Input Select for Sample MUXA bit 1 = Channel 0 negative input is AN1(1) 0 = Channel 0 negative input is VREFL bit 6-5 Unimplemented: Read as ‘0’ Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure23-1 to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3. 2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1); otherwise, the ANx input is used. 3: See the “Pin Diagrams” section for the available analog channels for each device.  2011-2013 Microchip Technology Inc. DS70000657H-page 333

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 23-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED) bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample MUXA bits(1) 11111 = Open; use this selection with CTMU capacitive and time measurement 11110 = Channel 0 positive input is connected to the CTMU temperature measurement diode (CTMU TEMP) 11101 = Reserved 11100 = Reserved 11011 = Reserved 11010 = Channel 0 positive input is the output of OA3/AN6(2,3) 11001 = Channel 0 positive input is the output of OA2/AN0(2) 11000 = Channel 0 positive input is the output of OA1/AN3(2) 10110 = Reserved • • • 10000 = Reserved 01111 = Channel 0 positive input is AN15(1,3) 01110 = Channel 0 positive input is AN14(1,3) 01101 = Channel 0 positive input is AN13(1,3) • • • 00010 = Channel 0 positive input is AN2(1,3) 00001 = Channel 0 positive input is AN1(1,3) 00000 = Channel 0 positive input is AN0(1,3) Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure23-1 to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3. 2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1); otherwise, the ANx input is used. 3: See the “Pin Diagrams” section for the available analog channels for each device. DS70000657H-page 334  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 23-7: AD1CSSH: ADC1 INPUT SCAN SELECT REGISTER HIGH(1) R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 CSS31 CSS30 — — — CSS26(2) CSS25(2) CSS24(2) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CSS31: ADC1 Input Scan Selection bit 1 = Selects CTMU capacitive and time measurement for input scan (Open) 0 = Skips CTMU capacitive and time measurement for input scan (Open) bit 14 CSS30: ADC1 Input Scan Selection bit 1 = Selects CTMU on-chip temperature measurement for input scan (CTMU TEMP) 0 = Skips CTMU on-chip temperature measurement for input scan (CTMU TEMP) bit 13-11 Unimplemented: Read as ‘0’ bit 10 CSS26: ADC1 Input Scan Selection bit(2) 1 = Selects OA3/AN6 for input scan 0 = Skips OA3/AN6 for input scan bit 9 CSS25: ADC1 Input Scan Selection bit(2) 1 = Selects OA2/AN0 for input scan 0 = Skips OA2/AN0 for input scan bit 8 CSS24: ADC1 Input Scan Selection bit(2) 1 = Selects OA1/AN3 for input scan 0 = Skips OA1/AN3 for input scan bit 7-0 Unimplemented: Read as ‘0’ Note 1: All AD1CSSH bits can be selected by user software. However, inputs selected for scan, without a corresponding input on the device, convert VREFL. 2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1); otherwise, the ANx input is used.  2011-2013 Microchip Technology Inc. DS70000657H-page 335

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 23-8: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CSS<15:0>: ADC1 Input Scan Selection bits 1 = Selects ANx for input scan 0 = Skips ANx for input scan Note 1: On devices with less than 16 analog inputs, all AD1CSSL bits can be selected by the user. However, inputs selected for scan, without a corresponding input on the device, convert VREFL. 2: CSSx = ANx, where x = 0-15. DS70000657H-page 336  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 24.0 PERIPHERAL TRIGGER The PTG module has the following major features: GENERATOR (PTG) MODULE • Multiple clock sources • Two 16-bit general purpose timers Note1: This data sheet summarizes the • Two 16-bit general limit counters features of the dsPIC33EPXXXGP50X, • Configurable for rising or falling edge triggering dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X families of • Generates processor interrupts to include: devices. It is not intended to be a - Four configurable processor interrupts comprehensive reference source. To - Interrupt on a Step event in Single-Step mode complement the information in this data - Interrupt on a PTG Watchdog Timer time-out sheet, refer to “Peripheral Trigger • Able to receive trigger signals from these Generator (PTG)” (DS70669) in the peripherals: “dsPIC33/PIC24 Family Reference Manual”, which is available from the - ADC Microchip web site (www.microchip.com). - PWM 2: Some registers and associated bits - Output Compare described in this section may not be - Input Capture available on all devices. Refer to - Op Amp/Comparator Section4.0 “Memory Organization” in - INT2 this data sheet for device-specific register • Able to trigger or synchronize to these and bit information. peripherals: - Watchdog Timer 24.1 Module Introduction - Output Compare The Peripheral Trigger Generator (PTG) provides a - Input Capture means to schedule complex high-speed peripheral - ADC operations that would be difficult to achieve using soft- - PWM ware. The PTG module uses 8-bit commands, called - Op Amp/Comparator “Steps”, that the user writes to the PTG Queue registers (PTGQUE0-PTGQUE7), which perform oper- ations, such as wait for input signal, generate output trigger and wait for timer.  2011-2013 Microchip Technology Inc. DS70000657H-page 337

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 24-1: PTG BLOCK DIAGRAM PTGHOLD PTGL0<15:0> PTGTxLIM<15:0> PTGCxLIM<15:0> PTGSDLIM<15:0> PTGADJ PTG General PTG Loop PTG Step Purpose Counter x Delay Timer Step Command Timerx PTGBTE<15:0> PTGCST<15:0> PTGCON<15:0> Step Command PTGDIV<4:0> s ut PTGO0 PTGCLK<2:0> utp • O • er • g Bus Trig PTGO31 a Dat FP s 16-Bit TT12CCTLLAKKD k Input  PTG Control Logic c T3CLK Clo Step Command FOSC Step Command s pt PTG0IF POOWCCM12 nputs TG Interru PTG•••3IF CMICP1x ger I P IANDTC2 Trig AD1CHS0<15:0> PTGQPTR<4:0> PTG Watchdog Timer(1) PTGWDTIF PTGQUE0 PTGQUE1 PTGQUE2 PTGQUE3 Command PTGQUE4 Decoder PTGQUE5 PTGQUE6 PTGQUE7 PTGSTEPIF Note 1: This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer. DS70000657H-page 338  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 24.2 PTG Resources 24.2.1 KEY RESOURCES Many useful resources are provided on the main prod- • “Peripheral Trigger Generator” (DS70669) in uct page of the Microchip web site for the devices listed the “dsPIC33/PIC24 Family Reference Manual” in this data sheet. This product page, which can be • Code Samples accessed using this link, contains the latest updates • Application Notes and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2013 Microchip Technology Inc. DS70000657H-page 339

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 24.3 PTG Control Registers REGISTER 24-1: PTGCST: PTG CONTROL/STATUS REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PTGEN — PTGSIDL PTGTOGL — PTGSWT(2) PTGSSEN(3) PTGIVIS bit 15 bit 8 R/W-0 HS-0 U-0 U-0 U-0 U-0 R/W-0 PTGSTRT PTGWDTO — — — — PTGITM1(1) PTGITM0(1) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTGEN: Module Enable bit 1 = PTG module is enabled 0 = PTG module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PTGSIDL: PTG Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 PTGTOGL: PTG TRIG Output Toggle Mode bit 1 = Toggle state of the PTGOx for each execution of the PTGTRIG command 0 = Each execution of the PTGTRIG command will generate a single PTGOx pulse determined by the value in the PTGPWDx bits bit 11 Unimplemented: Read as ‘0’ bit 10 PTGSWT: PTG Software Trigger bit(2) 1 = Triggers the PTG module 0 = No action (clearing this bit will have no effect) bit 9 PTGSSEN: PTG Enable Single-Step bit(3) 1 = Enables Single-Step mode 0 = Disables Single-Step mode bit 8 PTGIVIS: PTG Counter/Timer Visibility Control bit 1 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the current values of their corresponding counter/timer registers (PTGSD, PTGCx, PTGTx) 0 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the value previously written to those limit registers bit 7 PTGSTRT: PTG Start Sequencer bit 1 = Starts to sequentially execute commands (Continuous mode) 0 = Stops executing commands bit 6 PTGWDTO: PTG Watchdog Timer Time-out Status bit 1 = PTG Watchdog Timer has timed out 0 = PTG Watchdog Timer has not timed out. bit 5-2 Unimplemented: Read as ‘0’ Note 1: These bits apply to the PTGWHI and PTGWLO commands only. 2: This bit is only used with the PTGCTRL step command software trigger option. 3: Use of the PTG Single-Step mode is reserved for debugging tools only. DS70000657H-page 340  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 24-1: PTGCST: PTG CONTROL/STATUS REGISTER (CONTINUED) bit 1-0 PTGITM<1:0>: PTG Input Trigger Command Operating Mode bits(1) 11 = Single level detect with Step delay not executed on exit of command (regardless of the PTGCTRL command) 10 = Single level detect with Step delay executed on exit of command 01 = Continuous edge detect with Step delay not executed on exit of command (regardless of the PTGCTRL command) 00 = Continuous edge detect with Step delay executed on exit of command Note 1: These bits apply to the PTGWHI and PTGWLO commands only. 2: This bit is only used with the PTGCTRL step command software trigger option. 3: Use of the PTG Single-Step mode is reserved for debugging tools only.  2011-2013 Microchip Technology Inc. DS70000657H-page 341

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 24-2: PTGCON: PTG CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGCLK2 PTGCLK1 PTGCLK0 PTGDIV4 PTGDIV3 PTGDIV2 PTGDIV1 PTGDIV0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PTGPWD3 PTGPWD2 PTGPWD1 PTGPWD0 — PTGWDT2 PTGWDT1 PTGWDT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 PTGCLK<2:0>: Select PTG Module Clock Source bits 111 = Reserved 110 = Reserved 101 = PTG module clock source will be T3CLK 100 = PTG module clock source will be T2CLK 011 = PTG module clock source will be T1CLK 010 = PTG module clock source will be TAD 001 = PTG module clock source will be FOSC 000 = PTG module clock source will be FP bit 12-8 PTGDIV<4:0>: PTG Module Clock Prescaler (divider) bits 11111 = Divide-by-32 11110 = Divide-by-31 • • • 00001 = Divide-by-2 00000 = Divide-by-1 bit 7-4 PTGPWD<3:0>: PTG Trigger Output Pulse-Width bits 1111 = All trigger outputs are 16 PTG clock cycles wide 1110 = All trigger outputs are 15 PTG clock cycles wide • • • 0001 = All trigger outputs are 2 PTG clock cycles wide 0000 = All trigger outputs are 1 PTG clock cycle wide bit 3 Unimplemented: Read as ‘0’ bit 2-0 PTGWDT<2:0>: Select PTG Watchdog Timer Time-out Count Value bits 111 = Watchdog Timer will time-out after 512 PTG clocks 110 = Watchdog Timer will time-out after 256 PTG clocks 101 = Watchdog Timer will time-out after 128 PTG clocks 100 = Watchdog Timer will time-out after 64 PTG clocks 011 = Watchdog Timer will time-out after 32 PTG clocks 010 = Watchdog Timer will time-out after 16 PTG clocks 001 = Watchdog Timer will time-out after 8 PTG clocks 000 = Watchdog Timer is disabled DS70000657H-page 342  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 24-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCTS4 ADCTS3 ADCTS2 ADCTS1 IC4TSS IC3TSS IC2TSS IC1TSS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OC4CS OC3CS OC2CS OC1CS OC4TSS OC3TSS OC2TSS OC1TSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADCTS4: Sample Trigger PTGO15 for ADC bit 1 = Generates Trigger when the broadcast command is executed 0 = Does not generate Trigger when the broadcast command is executed bit 14 ADCTS3: Sample Trigger PTGO14 for ADC bit 1 = Generates Trigger when the broadcast command is executed 0 = Does not generate Trigger when the broadcast command is executed bit 13 ADCTS2: Sample Trigger PTGO13 for ADC bit 1 = Generates Trigger when the broadcast command is executed 0 = Does not generate Trigger when the broadcast command is executed bit 12 ADCTS1: Sample Trigger PTGO12 for ADC bit 1 = Generates Trigger when the broadcast command is executed 0 = Does not generate Trigger when the broadcast command is executed bit 11 IC4TSS: Trigger/Synchronization Source for IC4 bit 1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed bit 10 IC3TSS: Trigger/Synchronization Source for IC3 bit 1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed bit 9 IC2TSS: Trigger/Synchronization Source for IC2 bit 1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed bit 8 IC1TSS: Trigger/Synchronization Source for IC1 bit 1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed bit 7 OC4CS: Clock Source for OC4 bit 1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed bit 6 OC3CS: Clock Source for OC3 bit 1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed bit 5 OC2CS: Clock Source for OC2 bit 1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). 2: This register is only used with the PTGCTRL OPTION = 1111 Step command.  2011-2013 Microchip Technology Inc. DS70000657H-page 343

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 24-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) (CONTINUED) bit 4 OC1CS: Clock Source for OC1 bit 1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed bit 3 OC4TSS: Trigger/Synchronization Source for OC4 bit 1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed bit 2 OC3TSS: Trigger/Synchronization Source for OC3 bit 1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed bit 1 OC2TSS: Trigger/Synchronization Source for OC2 bit 1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed bit 0 OC1TSS: Trigger/Synchronization Source for OC1 bit 1 = Generates Trigger/Synchronization when the broadcast command is executed 0 = Does not generate Trigger/Synchronization when the broadcast command is executed Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). 2: This register is only used with the PTGCTRL OPTION = 1111 Step command. DS70000657H-page 344  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 24-4: PTGT0LIM: PTG TIMER0 LIMIT REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGT0LIM<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGT0LIM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTGT0LIM<15:0>: PTG Timer0 Limit Register bits General Purpose Timer0 Limit register (effective only with a PTGT0 Step command). Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). REGISTER 24-5: PTGT1LIM: PTG TIMER1 LIMIT REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGT1LIM<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGT1LIM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTGT1LIM<15:0>: PTG Timer1 Limit Register bits General Purpose Timer1 Limit register (effective only with a PTGT1 Step command). Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1).  2011-2013 Microchip Technology Inc. DS70000657H-page 345

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 24-6: PTGSDLIM: PTG STEP DELAY LIMIT REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGSDLIM<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGSDLIM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTGSDLIM<15:0>: PTG Step Delay Limit Register bits Holds a PTG Step delay value representing the number of additional PTG clocks between the start of a Step command and the completion of a Step command. Note 1: A base Step delay of one PTG clock is added to any value written to the PTGSDLIM register (Step Delay = (PTGSDLIM) + 1). 2: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). REGISTER 24-7: PTGC0LIM: PTG COUNTER 0 LIMIT REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGC0LIM<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGC0LIM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTGC0LIM<15:0>: PTG Counter 0 Limit Register bits May be used to specify the loop count for the PTGJMPC0 Step command or as a limit register for the General Purpose Counter 0. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). DS70000657H-page 346  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 24-8: PTGC1LIM: PTG COUNTER 1 LIMIT REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGC1LIM<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGC1LIM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTGC1LIM<15:0>: PTG Counter 1 Limit Register bits May be used to specify the loop count for the PTGJMPC1 Step command or as a limit register for the General Purpose Counter 1. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). REGISTER 24-9: PTGHOLD: PTG HOLD REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGHOLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGHOLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTGHOLD<15:0>: PTG General Purpose Hold Register bits Holds user-supplied data to be copied to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 registers with the PTGCOPY command. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1).  2011-2013 Microchip Technology Inc. DS70000657H-page 347

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 24-10: PTGADJ: PTG ADJUST REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGADJ<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGADJ<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTGADJ<15:0>: PTG Adjust Register bits This register holds user-supplied data to be added to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 registers with the PTGADD command. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). REGISTER 24-11: PTGL0: PTG LITERAL0 REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGL0<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGL0<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTGL0<15:0>: PTG Literal 0 Register bits This register holds the 16-bit value to be written to the AD1CHS0 register with the PTGCTRL Step command. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). DS70000657H-page 348  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X R EGISTER 24-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PTGQPTR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 PTGQPTR<4:0>: PTG Step Queue Pointer Register bits This register points to the currently active Step command in the Step queue. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). REGISTER 24-13: PTGQUEx: PTG STEP QUEUE REGISTER x (x = 0-7)(1,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STEP(2x + 1)<7:0>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STEP(2x)<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 STEP(2x + 1)<7:0>: PTG Step Queue Pointer Register bits(2) A queue location for storage of the STEP(2x + 1) command byte. bit 7-0 STEP(2x)<7:0>: PTG Step Queue Pointer Register bits(2) A queue location for storage of the STEP(2x) command byte. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT=1). 2: Refer to Table24-1 for the Step command encoding. 3: The Step registers maintain their values on any type of Reset.  2011-2013 Microchip Technology Inc. DS70000657H-page 349

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 24.4 Step Commands and Format TABLE 24-1: PTG STEP COMMAND FORMAT Step Command Byte: STEPx<7:0> CMD<3:0> OPTION<3:0> bit 7 bit 4 bit 3 bit 0 bit 7-4 Step CMD<3:0> Command Description Command 0000 PTGCTRL Execute control command as described by OPTION<3:0>. 0001 PTGADD Add contents of PTGADJ register to target register as described by OPTION<3:0>. PTGCOPY Copy contents of PTGHOLD register to target register as described by OPTION<3:0>. 001x PTGSTRB Copy the value contained in CMD<0>:OPTION<3:0> to the CH0SA<4:0> bits (AD1CHS0<4:0>). 0100 PTGWHI Wait for a low-to-high edge input from the selected PTG trigger input as described by OPTION<3:0>. 0101 PTGWLO Wait for a high-to-low edge input from the selected PTG trigger input as described by OPTION<3:0>. 0110 Reserved Reserved. 0111 PTGIRQ Generate individual interrupt request as described by OPTION3<:0>. 100x PTGTRIG Generate individual trigger output as described by <<CMD<0>:OPTION<3:0>>. 101x PTGJMP Copy the value indicated in <<CMD<0>:OPTION<3:0>> to the Queue Pointer (PTGQPTR) and jump to that Step queue. 110x PTGJMPC0 PTGC0 = PTGC0LIM: Increment the Queue Pointer (PTGQPTR). PTGC0  PTGC0LIM: Increment Counter 0 (PTGC0) and copy the value indicated in <<CMD<0>:OPTION<3:0>> to the Queue Pointer (PTGQPTR), and jump to that Step queue 111x PTGJMPC1 PTGC1 = PTGC1LIM: Increment the Queue Pointer (PTGQPTR). PTGC1  PTGC1LIM: Increment Counter 1 (PTGC1) and copy the value indicated in <<CMD<0>:OPTION<3:0>> to the Queue Pointer (PTGQPTR), and jump to that Step queue. Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction). 2: Refer to Table24-2 for the trigger output descriptions. 3: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. DS70000657H-page 350  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 24-1: PTG STEP COMMAND FORMAT (CONTINUED) bit 3-0 Step OPTION<3:0> Option Description Command PTGCTRL(1) 0000 Reserved. 0001 Reserved. 0010 Disable Step Delay Timer (PTGSD). 0011 Reserved. 0100 Reserved. 0101 Reserved. 0110 Enable Step Delay Timer (PTGSD). 0111 Reserved. 1000 Start and wait for the PTG Timer0 to match the Timer0 Limit Register. 1001 Start and wait for the PTG Timer1 to match the Timer1 Limit Register. 1010 Reserved. 1011 Wait for the software trigger bit transition from low-to-high before continuing (PTGSWT = 0 to 1). 1100 Copy contents of the Counter 0 register to the AD1CHS0 register. 1101 Copy contents of the Counter 1 register to the AD1CHS0 register. 1110 Copy contents of the Literal 0 register to the AD1CHS0 register. 1111 Generate triggers indicated in the Broadcast Trigger Enable register (PTGBTE). PTGADD(1) 0000 Add contents of the PTGADJ register to the Counter 0 Limit register (PTGC0LIM). 0001 Add contents of the PTGADJ register to the Counter 1 Limit register (PTGC1LIM). 0010 Add contents of the PTGADJ register to the Timer0 Limit register (PTGT0LIM). 0011 Add contents of the PTGADJ register to the Timer1 Limit register (PTGT1LIM). 0100 Add contents of the PTGADJ register to the Step Delay Limit register (PTGSDLIM). 0101 Add contents of the PTGADJ register to the Literal 0 register (PTGL0). 0110 Reserved. 0111 Reserved. PTGCOPY(1) 1000 Copy contents of the PTGHOLD register to the Counter 0 Limit register (PTGC0LIM). 1001 Copy contents of the PTGHOLD register to the Counter 1 Limit register (PTGC1LIM). 1010 Copy contents of the PTGHOLD register to the Timer0 Limit register (PTGT0LIM). 1011 Copy contents of the PTGHOLD register to the Timer1 Limit register (PTGT1LIM). 1100 Copy contents of the PTGHOLD register to the Step Delay Limit register (PTGSDLIM). 1101 Copy contents of the PTGHOLD register to the Literal 0 register (PTGL0). 1110 Reserved. 1111 Reserved. Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction). 2: Refer to Table24-2 for the trigger output descriptions. 3: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.  2011-2013 Microchip Technology Inc. DS70000657H-page 351

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 24-1: PTG STEP COMMAND FORMAT (CONTINUED) bit 3-0 Step OPTION<3:0> Option Description Command PTGWHI(1) 0000 PWM Special Event Trigger.(3) or 0001 PWM master time base synchronization output.(3) PTGWLO(1) 0010 PWM1 interrupt.(3) 0011 PWM2 interrupt.(3) 0100 PWM3 interrupt.(3) 0101 Reserved. 0110 Reserved. 0111 OC1 Trigger event. 1000 OC2 Trigger event. 1001 IC1 Trigger event. 1010 CMP1 Trigger event. 1011 CMP2 Trigger event. 1100 CMP3 Trigger event. 1101 CMP4 Trigger event. 1110 ADC conversion done interrupt. 1111 INT2 external interrupt. PTGIRQ(1) 0000 Generate PTG Interrupt 0. 0001 Generate PTG Interrupt 1. 0010 Generate PTG Interrupt 2. 0011 Generate PTG Interrupt 3. 0100 Reserved. • • • • • • 1111 Reserved. PTGTRIG(2) 00000 PTGO0. 00001 PTGO1. • • • • • • 11110 PTGO30. 11111 PTGO31. Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction). 2: Refer to Table24-2 for the trigger output descriptions. 3: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. DS70000657H-page 352  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 24-2: PTG OUTPUT DESCRIPTIONS PTG Output PTG Output Description Number PTGO0 Trigger/Synchronization Source for OC1 PTGO1 Trigger/Synchronization Source for OC2 PTGO2 Trigger/Synchronization Source for OC3 PTGO3 Trigger/Synchronization Source for OC4 PTGO4 Clock Source for OC1 PTGO5 Clock Source for OC2 PTGO6 Clock Source for OC3 PTGO7 Clock Source for OC4 PTGO8 Trigger/Synchronization Source for IC1 PTGO9 Trigger/Synchronization Source for IC2 PTGO10 Trigger/Synchronization Source for IC3 PTGO11 Trigger/Synchronization Source for IC4 PTGO12 Sample Trigger for ADC PTGO13 Sample Trigger for ADC PTGO14 Sample Trigger for ADC PTGO15 Sample Trigger for ADC PTGO16 PWM Time Base Synchronous Source for PWM(1) PTGO17 PWM Time Base Synchronous Source for PWM(1) PTGO18 Mask Input Select for Op Amp/Comparator PTGO19 Mask Input Select for Op Amp/Comparator PTGO20 Reserved PTGO21 Reserved PTGO22 Reserved PTGO23 Reserved PTGO24 Reserved PTGO25 Reserved PTGO26 Reserved PTGO27 Reserved PTGO28 Reserved PTGO29 Reserved PTGO30 PTG Output to PPS Input Selection PTGO31 PTG Output to PPS Input Selection Note 1: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.  2011-2013 Microchip Technology Inc. DS70000657H-page 353

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 354  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 25.0 OP AMP/COMPARATOR The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ MODULE 50X and PIC24EPXXXGP/MC20X devices contain up to four comparators, which can be configured in various Note1: This data sheet summarizes the ways. Comparators, CMP1, CMP2 and CMP3, also features of the dsPIC33EPXXXGP50X, have the option to be configured as op amps, with the dsPIC33EPXXXMC20X/50X and output being brought to an external pin for gain/filtering PIC24EPXXXGP/MC20X families of connections. As shown in Figure25-1, individual devices. It is not intended to be a compre- comparator options are specified by the comparator hensive reference source. To complement module’s Special Function Register (SFR) control bits. the information in this data sheet, refer to Note: Op Amp/Comparator 3 is not available on “Op Amp/Comparator” (DS70357) in the the dsPIC33EPXXXGP502/MC502/MC202 “dsPIC33/PIC24 Family Reference Man- and PIC24EP256GP/MC202 (28-pin) ual”, which is available from the Microchip devices. web site (www.microchip.com). These options allow users to: 2: Some registers and associated bits described in this section may not be • Select the edge for trigger and interrupt generation available on all devices. Refer to • Configure the comparator voltage reference Section4.0 “Memory Organization” in • Configure output blanking and masking this data sheet for device-specific register • Configure as a comparator or op amp and bit information. (CMP1, CMP2 and CMP3 only) Note: Not all op amp/comparator input/output connections are available on all devices. See the “Pin Diagrams” section for available connections. FIGURE 25-1: OP AMP/COMPARATOR x MODULE BLOCK DIAGRAM (MODULES 1, 2 AND 3) CCH<1:0> (CMxCON<1:0>) CxIN1- 00 Op Amp/Comparator(2) CXIN2-(1) 01 VIN- – Blanking Digital CxOUT(1) CMPx Function Filter CxIN1+ 0 VIN+ + (see Figure25-4) (see Figure25-5) PInTpGut Trigger CVREFIN(1) 1 OPMODE (CMxCON<10>) – RINT1 Op Ampx OAxOUT/ANx + OAx/ANx(3) (to ADC) CREF (CMxCON<4>) Note 1: This input/output is not available as a selection when configured as an op amp (OPMODE (CMxCON<10>) = 1). 2: This module can be configured either as an op amp or a comparator using the OPMODE bit. 3: When configured as an op amp (OPMODE = 1), the ADC samples the op amp output; otherwise, the ADC samples the ANx pin.  2011-2013 Microchip Technology Inc. DS70000657H-page 355

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 25-2: COMPARATOR MODULE BLOCK DIAGRAM (MODULE 4) CCH<1:0> (CM4CON<1:0>) OA1/AN3 01 OA2/AN0 10 OA3/AN6 11 C4IN1- 00 VIN- – Blanking Digital C4OUT CMP4 Function Filter C4IN1+ 1 VIN+ + (see Figure25-4) (see Figure25-5) TOruigtpguetr CVREFIN 0 CREF (CMxCON<4>) FIGURE 25-3: OP AMP/COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREFSEL (CVRCON<10>) CVRSS = 1(1) VREF+ CVRSRC CVRCON<3:0> 3210 RRRR AVDD CVRSS = 0 8R CVCVCVCV 1 CVREFIN R CVREN 0 R R R X U 16 Steps M 1 CVREF1O o- 6-t 1 R CVR1OE (CVRCON<6>) R R CVRR 8R AVDD CVREF2O(2) AVSS AVSS CVR2OE (CVRCON<14>) Note 1: In order to operate with CVRSS = 1, at least one of the comparator modules must be enabled. 2: This reference is (AVDD + AVSS)/2. DS70000657H-page 356  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 25-4: USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM SELSRCA<3:0> (CMxMSKSRC<3:0>) Comparator Output To Digital BSlaignnkainlsg MUX A MAI MAI “AND-OR” Function BlLaongkiicng Filter MBI ANDI AND SELSRCB<3:0> MCI (CMxMSKSRC<7:4) MAI HLMS (CMxMSKCON<15) BSlaignnkainlsg X B MBI MBI OR MASK U M MCI SELSRCC<3:0> (CMxMSKSRC<11:8) CMxMSKCON C Blanking X MCI Signals U M FIGURE 25-5: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM TxCLK(1,2) 1xx SYNCO1(3) 010 FP(4) 000 FOSC(4) 001 CFDIV CFSEL<2:0> CFLTREN (CMxFLTR<6:4>) (CMxFLTR<3>) From Blanking Logic Digital Filter 1 CXOUT 0 Note 1: See the Type C Timer Block Diagram (Figure13-2). 2: See the Type B Timer Block Diagram (Figure13-1). 3: See the High-Speed PWMx Module Register Interconnection Diagram (Figure16-2). 4: See the Oscillator System Diagram (Figure9-1).  2011-2013 Microchip Technology Inc. DS70000657H-page 357

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 25.1 Op Amp Application 25.1.1 OP AMP CONFIGURATION A Considerations Figure25-6 shows a typical inverting amplifier circuit taking advantage of the internal connections from the There are two configurations to take into consider- op amp output to the input of the ADC. The advantage of ation when designing with the op amp modules that this configuration is that the user does not need to con- are available in the dsPIC33EPXXXGP50X, sume another analog input (ANy) on the device, and dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ allows the user to simultaneously sample all three op MC20X devices. Configuration A (see Figure25-6) amps with the ADC module, if needed. However, the takes advantage of the internal connection to the ADC presence of the internal resistance, RINT1, adds an error module to route the output of the op amp directly to the in the feedback path. Since RINT1 is an internal resis- ADC for measurement. Configuration B (see tance, in relation to the op amp output (VOAxOUT) and Figure25-7) requires that the designer externally route ADC internal connection (VADC), RINT1 must be included the output of the op amp (OAxOUT) to a separate ana- in the numerator term of the transfer function. See log input pin (ANy) on the device. Table30-55 in Table30-53 in Section30.0 “Electrical Characteris- Section30.0 “Electrical Characteristics” describes tics” for the typical value of RINT1. Table30-60 and the performance characteristics for the op amps, distin- Table30-61 in Section30.0 “Electrical Characteris- guishing between the two configuration types where tics” describe the minimum sample time (TSAMP) applicable. requirements for the ADC module in this configuration. Figure25-6 also defines the equations that should be used when calculating the expected voltages at points, VADC and VOAXOUT. FIGURE 25-6: OP AMP CONFIGURATION A RFEEDBACK(2) R 1 CxIN1- VIN – RINT1(1) Op Ampx OAxOUT Bias CxIN1+ + (VOAXOUT) Voltage(4) VADC OAx (to ADC) ADC(3) R +R  FEEDBACK INT1 V = ---------------------------------------------------  Bias Voltage–V  ADC  R  IN 1 R  FEEDBACK V = ------------------------------  Bias Voltage–V  OAxOUT  R  IN 1 Note 1: See Table30-53 for the Typical value. 2: See Table30-53 for the Minimum value for the feedback resistor. 3: See Table30-60 and Table30-61 for the minimum sample time (TSAMP). 4: CVREF1O or CVREF2O are two options that are available for supplying bias voltage to the op amps. DS70000657H-page 358  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 25.1.2 OP AMP CONFIGURATION B 25.2 Op Amp/Comparator Resources Figure25-7 shows a typical inverting amplifier circuit Many useful resources are provided on the main prod- with the output of the op amp (OAxOUT) externally uct page of the Microchip web site for the devices listed routed to a separate analog input pin (ANy) on the in this data sheet. This product page, which can be device. This op amp configuration is slightly different in accessed using this link, contains the latest updates terms of the op amp output and the ADC input and additional information. connection, therefore, RINT1 is not included in the transfer function. However, this configuration requires Note: In the event you are not able to access the the designer to externally route the op amp output product page using the link above, enter (OAxOUT) to another analog input pin (ANy). See this URL in your browser: Table30-53 in Section30.0 “Electrical Characteris- http://www.microchip.com/wwwproducts/ tics” for the typical value of RINT1. Table30-60 and Devices.aspx?dDocName=en555464 Table30-61 in Section30.0 “Electrical Characteris- tics” describe the minimum sample time (TSAMP) 25.2.1 KEY RESOURCES requirements for the ADC module in this configuration. • “Op Amp/Comparator” (DS70357) in the Figure25-7 also defines the equation to be used to “dsPIC33/PIC24 Family Reference Manual” calculate the expected voltage at point VOAXOUT. This • Code Samples is the typical inverting amplifier equation. • Application Notes • Software Libraries • Webinars • All Related “dsPIC33/PIC24 Family Reference Manual” Sections • Development Tools FIGURE 25-7: OP AMP CONFIGURATION B RFEEDBACK(2) R 1 CxIN1- VIN – RINT1(1) OAxOUT Op Ampx CxIN1+ (VOAXOUT) Bias + Voltage(4) ANy ADC(3) R  FEEDBACK V = ------------------------------  Bias Voltage–V  OAxOUT  R  IN 1 Note 1: See Table30-53 for the Typical value. 2: See Table30-53 for the Minimum value for the feedback resistor. 3: See Table30-60 and Table30-61 for the minimum sample time (TSAMP). 4: CVREF1O or CVREF2O are two options that are available for supplying bias voltage to the op amps.  2011-2013 Microchip Technology Inc. DS70000657H-page 359

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 25.3 Op Amp/Comparator Registers REGISTER 25-1: CMSTAT: OP AMP/COMPARATOR STATUS REGISTER R/W-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 PSIDL — — — C4EVT(1) C3EVT(1) C2EVT(1) C1EVT(1) bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — C4OUT(2) C3OUT(2) C2OUT(2) C1OUT(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PSIDL: Comparator Stop in Idle Mode bit 1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all comparators in Idle mode bit 14-12 Unimplemented: Read as ‘0’ bit 11 C4EVT: Op Amp/Comparator 4 Event Status bit(1) 1 = Op amp/comparator event occurred 0 = Op amp/comparator event did not occur bit 10 C3EVT: Comparator 3 Event Status bit(1) 1 = Comparator event occurred 0 = Comparator event did not occur bit 9 C2EVT: Comparator 2 Event Status bit(1) 1 = Comparator event occurred 0 = Comparator event did not occur bit 8 C1EVT: Comparator 1 Event Status bit(1) 1 = Comparator event occurred 0 = Comparator event did not occur bit 7-4 Unimplemented: Read as ‘0’ bit 3 C4OUT: Comparator 4 Output Status bit(2) When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 2 C3OUT: Comparator 3 Output Status bit(2) When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register, CMxCON<9>. 2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON<8>. DS70000657H-page 360  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-1: CMSTAT: OP AMP/COMPARATOR STATUS REGISTER (CONTINUED) bit 1 C2OUT: Comparator 2 Output Status bit(2) When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 0 C1OUT: Comparator 1 Output Status bit(2) When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register, CMxCON<9>. 2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON<8>.  2011-2013 Microchip Technology Inc. DS70000657H-page 361

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2 OR 3) R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 CON COE(2) CPOL — — OPMODE CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF(1) — — CCH1(1) CCH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Op Amp/Comparator Enable bit 1 = Op amp/comparator is enabled 0 = Op amp/comparator is disabled bit 14 COE: Comparator Output Enable bit(2) 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-11 Unimplemented: Read as ‘0’ bit 10 OPMODE: Op Amp/Comparator Operation Mode Select bit 1 = Circuit operates as an op amp 0 = Circuit operates as a comparator bit 9 CEVT: Comparator Event bit 1 = Comparator event according to the EVPOL<1:0> settings occurred; disables future triggers and interrupts until the bit is cleared 0 = Comparator event did not occur bit 8 COUT: Comparator Output bit When CPOL = 0 (non-inverted polarity): 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1 (inverted polarity): 1 = VIN+ < VIN- 0 = VIN+ > VIN- Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available inputs for each package. 2: This output is not available when OPMODE (CMxCON<10>) = 1. DS70000657H-page 362  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2 OR 3) (CONTINUED) bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT=0) 10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator output (while CEVT=0) If CPOL = 1 (inverted polarity): Low-to-high transition of the comparator output. If CPOL = 0 (non-inverted polarity): High-to-low transition of the comparator output. 01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity-selected comparator output (while CEVT=0) If CPOL = 1 (inverted polarity): High-to-low transition of the comparator output. If CPOL = 0 (non-inverted polarity): Low-to-high transition of the comparator output 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Reference Select bit (VIN+ input)(1) 1 = VIN+ input connects to internal CVREFIN voltage(2) 0 = VIN+ input connects to CxIN1+ pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Op Amp/Comparator Channel Select bits(1) 11 = Unimplemented 10 = Unimplemented 01 = Inverting input of the comparator connects to the CxIN2- pin(2) 00 = Inverting input of the op amp/comparator connects to the CxIN1- pin Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available inputs for each package. 2: This output is not available when OPMODE (CMxCON<10>) = 1.  2011-2013 Microchip Technology Inc. DS70000657H-page 363

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-3: CM4CON: COMPARATOR 4 CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 CON COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF(1) — — CCH1(1) CCH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event according to EVPOL<1:0> settings occurred; disables future triggers and interrupts until the bit is cleared 0 = Comparator event did not occur bit 8 COUT: Comparator Output bit When CPOL = 0 (non-inverted polarity): 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1 (inverted polarity): 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT=0) 10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator output (while CEVT=0) If CPOL = 1 (inverted polarity): Low-to-high transition of the comparator output. If CPOL = 0 (non-inverted polarity): High-to-low transition of the comparator output. 01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator output (while CEVT=0) If CPOL = 1 (inverted polarity): High-to-low transition of the comparator output. If CPOL = 0 (non-inverted polarity): Low-to-high transition of the comparator output. 00 = Trigger/event/interrupt generation is disabled Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available inputs for each package. DS70000657H-page 364  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-3: CM4CON: COMPARATOR 4 CONTROL REGISTER (CONTINUED) bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Reference Select bit (VIN+ input)(1) 1 = VIN+ input connects to internal CVREFIN voltage 0 = VIN+ input connects to C4IN1+ pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits(1) 11 = VIN- input of comparator connects to OA3/AN6 10 = VIN- input of comparator connects to OA2/AN0 01 = VIN- input of comparator connects to OA1/AN3 00 = VIN- input of comparator connects to C4IN1- Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available inputs for each package.  2011-2013 Microchip Technology Inc. DS70000657H-page 365

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SELSRCC<3:0>: Mask C Input Select bits 1111 = FLT4 1110 = FLT2 1101 = PTGO19 1100 = PTGO18 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L bit 7-4 SELSRCB<3:0>: Mask B Input Select bits 1111 = FLT4 1110 = FLT2 1101 = PTGO19 1100 = PTGO18 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L DS70000657H-page 366  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT CONTROL REGISTER (CONTINUED) bit 3-0 SELSRCA<3:0>: Mask A Input Select bits 1111 = FLT4 1110 = FLT2 1101 = PTGO19 1100 = PTGO18 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L  2011-2013 Microchip Technology Inc. DS70000657H-page 367

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-5: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLMS: High or Low-Level Masking Select bits 1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating 0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating bit 14 Unimplemented: Read as ‘0’ bit 13 OCEN: OR Gate C Input Enable bit 1 = MCI is connected to OR gate 0 = MCI is not connected to OR gate bit 12 OCNEN: OR Gate C Input Inverted Enable bit 1 = Inverted MCI is connected to OR gate 0 = Inverted MCI is not connected to OR gate bit 11 OBEN: OR Gate B Input Enable bit 1 = MBI is connected to OR gate 0 = MBI is not connected to OR gate bit 10 OBNEN: OR Gate B Input Inverted Enable bit 1 = Inverted MBI is connected to OR gate 0 = Inverted MBI is not connected to OR gate bit 9 OAEN: OR Gate A Input Enable bit 1 = MAI is connected to OR gate 0 = MAI is not connected to OR gate bit 8 OANEN: OR Gate A Input Inverted Enable bit 1 = Inverted MAI is connected to OR gate 0 = Inverted MAI is not connected to OR gate bit 7 NAGS: AND Gate Output Inverted Enable bit 1 = Inverted ANDI is connected to OR gate 0 = Inverted ANDI is not connected to OR gate bit 6 PAGS: AND Gate Output Enable bit 1 = ANDI is connected to OR gate 0 = ANDI is not connected to OR gate bit 5 ACEN: AND Gate C Input Enable bit 1 = MCI is connected to AND gate 0 = MCI is not connected to AND gate bit 4 ACNEN: AND Gate C Input Inverted Enable bit 1 = Inverted MCI is connected to AND gate 0 = Inverted MCI is not connected to AND gate DS70000657H-page 368  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-5: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER (CONTINUED) bit 3 ABEN: AND Gate B Input Enable bit 1 = MBI is connected to AND gate 0 = MBI is not connected to AND gate bit 2 ABNEN: AND Gate B Input Inverted Enable bit 1 = Inverted MBI is connected to AND gate 0 = Inverted MBI is not connected to AND gate bit 1 AAEN: AND Gate A Input Enable bit 1 = MAI is connected to AND gate 0 = MAI is not connected to AND gate bit 0 AANEN: AND Gate A Input Inverted Enable bit 1 = Inverted MAI is connected to AND gate 0 = Inverted MAI is not connected to AND gate  2011-2013 Microchip Technology Inc. DS70000657H-page 369

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-6: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits 111 = T5CLK(1) 110 = T4CLK(2) 101 = T3CLK(1) 100 = T2CLK(2) 011 = Reserved 010 = SYNCO1(3) 001 = FOSC(4) 000 = FP(4) bit 3 CFLTREN: Comparator Filter Enable bit 1 = Digital filter is enabled 0 = Digital filter is disabled bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits 111 = Clock Divide 1:128 110 = Clock Divide 1:64 101 = Clock Divide 1:32 100 = Clock Divide 1:16 011 = Clock Divide 1:8 010 = Clock Divide 1:4 001 = Clock Divide 1:2 000 = Clock Divide 1:1 Note 1: See the Type C Timer Block Diagram (Figure13-2). 2: See the Type B Timer Block Diagram (Figure13-1). 3: See the High-Speed PWMx Module Register Interconnection Diagram (Figure16-2). 4: See the Oscillator System Diagram (Figure9-1). DS70000657H-page 370  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 25-7: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — CVR2OE(1) — — — VREFSEL — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVR1OE(1) CVRR CVRSS(2) CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 CVR2OE: Comparator Voltage Reference 2 Output Enable bit(1) 1 = (AVDD – AVSS)/2 is connected to the CVREF2O pin 0 = (AVDD – AVSS)/2 is disconnected from the CVREF2O pin bit 13-11 Unimplemented: Read as ‘0’ bit 10 VREFSEL: Comparator Voltage Reference Select bit 1 = CVREFIN = VREF+ 0 = CVREFIN is generated by the resistor network bit 9-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = Comparator voltage reference circuit is powered on 0 = Comparator voltage reference circuit is powered down bit 6 CVR1OE: Comparator Voltage Reference 1 Output Enable bit(1) 1 = Voltage level is output on the CVREF1O pin 0 = Voltage level is disconnected from then CVREF1O pin bit 5 CVRR: Comparator Voltage Reference Range Selection bit 1 = CVRSRC/24 step-size 0 = CVRSRC/32 step-size bit 4 CVRSS: Comparator Voltage Reference Source Selection bit(2) 1 = Comparator voltage reference source, CVRSRC = (VREF+) – (AVSS) 0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0> Comparator Voltage Reference Value Selection 0  CVR<3:0>  15 bits When CVRR = 1: CVREFIN = (CVR<3:0>/24)  (CVRSRC) When CVRR = 0: CVREFIN = (CVRSRC/4) + (CVR<3:0>/32)  (CVRSRC) Note 1: CVRxOE overrides the TRISx and the ANSELx bit settings. 2: In order to operate with CVRSS = 1, at least one of the comparator modules must be enabled.  2011-2013 Microchip Technology Inc. DS70000657H-page 371

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 372  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 26.0 PROGRAMMABLE CYCLIC The programmable CRC generator offers the following REDUNDANCY CHECK (CRC) features: GENERATOR • User-programmable (up to 32nd order) polynomial CRC equation Note1: This data sheet summarizes the • Interrupt output features of the dsPIC33EPXXXGP50X, • Data FIFO dsPIC33EPXXXMC20X/50X and The programmable CRC generator provides a PIC24EPXXXGP/MC20X families of hardware implemented method of quickly generating devices. It is not intended to be a compre- checksums for various networking and security hensive reference source. To complement applications. It offers the following features: the information in this data sheet, refer to “Programmable Cyclic Redundancy • User-programmable CRC polynomial equation, Check (CRC)” (DS70346) of the up to 32 bits “dsPIC33/PIC24 Family Reference Man- • Programmable shift direction (little or big-endian) ual”, which is available from the Microchip • Independent data and polynomial lengths website (www.microchip.com). • Configurable interrupt output 2: Some registers and associated bits • Data FIFO described in this section may not be A simplified block diagram of the CRC generator is available on all devices. Refer to shown in Figure26-1. A simple version of the CRC shift Section4.0 “Memory Organization” in engine is shown in Figure26-2. this data sheet for device-specific register and bit information. FIGURE 26-1: CRC BLOCK DIAGRAM CRCDATH CRCDATL Variable FIFO FIFO Empty Event (4x32, 8x16 or 16x8) CRCISEL 2 * FP Shift Clock Shift Buffer 1 Set CRCIF 0 0 1 LENDIAN Shift Complete Event CRC Shift Engine CRCWDATH CRCWDATL  2011-2013 Microchip Technology Inc. DS70000657H-page 373

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 26-2: CRC SHIFT ENGINE DETAIL CRCWDATH CRCWDATL Read/Write Bus X(1)(1) X(2)(1) X(n)(1) Shift Buffer Bit 0 Bit 1 Bit 2 Bit n(2) Data Note 1: Each XOR stage of the shift engine is programmable. See text for details. 2: Polynomial length n is determined by ([PLEN<4:0>] + 1). 26.1 Overview TABLE 26-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIAL The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Bit Values Polynomial length, which reflects the highest exponent CRC Control Bits 16-bit 32-bit in the equation, is selected by the PLEN<4:0> bits Polynomial Polynomial (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which PLEN<4:0> 01111 11111 exponent terms are included in the equation. Setting a X<31:16> 0000 0000 0000 0100 particular bit includes that exponent term in the 0000 000x 1100 0001 equation; functionally, this includes an XOR operation X<15:0> 0001 0000 0001 1101 on the corresponding bit in the CRC engine. Clearing 0010 000x 1011 011x the bit disables the XOR. For example, consider two CRC polynomials, one a 26.2 Programmable CRC Resources 16-bit equation and the other a 32-bit equation: Many useful resources are provided on the main prod- x16 + x12 + x5 + 1 uct page of the Microchip web site for the devices listed and in this data sheet. This product page, which can be accessed using this link, contains the latest updates x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 and additional information. + x5 + x4 + x2 + x + 1 Note: In the event you are not able to access the To program these polynomials into the CRC generator, product page using the link above, enter set the register bits as shown in Table26-1. this URL in your browser: Note that the appropriate positions are set to ‘1’ to http://www.microchip.com/wwwproducts/ indicate that they are used in the equation (for example, Devices.aspx?dDocName=en555464 X26 and X23). The 0 bit required by the equation is always XORed; thus, X0 is a don’t care. For a poly- 26.2.1 KEY RESOURCES nomial of length N, it is assumed that the Nth bit will • “Programmable Cyclic Redundancy Check always be used, regardless of the bit setting. Therefore, (CRC)” (DS70346) in the “dsPIC33/PIC24 Family for a polynomial length of 32, there is no 32nd bit in the Reference Manual” CRCxOR register. • Code Samples • Application Notes • Software Libraries • Webinars • All Related “dsPIC33/PIC24 Family Reference Manual” Sections • Development Tools DS70000657H-page 374  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 26.3 Programmable CRC Registers REGISTER 26-1: CRCCON1: CRC CONTROL REGISTER1 R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0 R-1 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CRCEN: CRC Enable bit 1 = CRC module is enabled 0 = CRC module is disabled; all state machines, pointers and CRCWDAT/CRCDAT are reset, other SFRs are not reset bit 14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<4:0> > 7 or 16 when PLEN<4:0> 7. bit 7 CRCFUL: CRC FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: CRC FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; final word of data is still shifting through CRC 0 = Interrupt on shift is complete and CRCWDAT results are ready bit 4 CRCGO: Start CRC bit 1 = Starts CRC serial shifter 0 = CRC serial shifter is turned off bit 3 LENDIAN: Data Word Little-Endian Configuration bit 1 = Data word is shifted into the CRC starting with the LSb (little endian) 0 = Data word is shifted into the CRC starting with the MSb (big endian) bit 2-0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS70000657H-page 375

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 26-2: CRCCON2: CRC CONTROL REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH<4:0>: Data Width Select bits These bits set the width of the data word (DWIDTH<4:0> + 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN<4:0>: Polynomial Length Select bits These bits set the length of the polynomial (Polynomial Length = PLEN<4:0> + 1). DS70000657H-page 376  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 26-3: CRCXORH: CRC XOR POLYNOMIAL HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 X<31:16>: XOR of Polynomial Term Xn Enable bits REGISTER 26-4: CRCXORL: CRC XOR POLYNOMIAL LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X<7:1> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’  2011-2013 Microchip Technology Inc. DS70000657H-page 377

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 378  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 27.0 SPECIAL FEATURES 27.1 Configuration Bits In dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ Note: This data sheet summarizes the 50X and PIC24EPXXXGP/MC20X devices, the features of the dsPIC33EPXXXGP50X, Configuration bytes are implemented as volatile mem- dsPIC33EPXXXMC20X/50X and ory. This means that configuration data must be PIC24EPXXXGP/MC20X families of programmed each time the device is powered up. devices. It is not intended to be a Configuration data is stored in at the top of the on-chip comprehensive reference source. To program memory space, known as the Flash Configura- complement the information in this data tion bytes. Their specific locations are shown in sheet, refer to the related section of the Table27-1. The configuration data is automatically “dsPIC33/PIC24 Family Reference loaded from the Flash Configuration bytes to the proper Manual”, which is available from the Configuration Shadow registers during device Resets. Microchip web site (www.microchip.com). Note: Configuration data is reloaded on all types dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X of device Resets. and PIC24EPXXXGP/MC20X devices include several features intended to maximize application flexibility and When creating applications for these devices, users reliability, and minimize cost through elimination of should always specifically allocate the location of the external components. These are: Flash Configuration bytes for configuration data in their • Flexible Configuration code for the compiler. This is to make certain that pro- gram code is not stored in this address when the code • Watchdog Timer (WDT) is compiled. • Code Protection and CodeGuard™ Security The upper 2 bytes of all Flash Configuration Words in • JTAG Boundary Scan Interface program memory should always be ‘1111 1111 1111 • In-Circuit Serial Programming™ (ICSP™) 1111’. This makes them appear to be NOP instructions • In-Circuit Emulation in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘1’s to these locations has no effect on device operation. Note: Performing a page erase operation on the last page of program memory clears the Flash Configuration bytes, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. The Configuration Flash bytes map is shown in Table27-1.  2011-2013 Microchip Technology Inc. DS70000657H-page 379

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 27-1: CONFIGURATION BYTE REGISTER MAP Device File Memory Address Bits 23-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Size (Kbytes) Reserved 0057EC 32 00AFEC 64 0157EC 128 — — — — — — — — — 02AFEC 256 0557EC 512 Reserved 0057EE 32 00AFEE 64 0157EE 128 — — — — — — — — — 02AFEE 256 0557EE 512 FICD 0057F0 32 00AFF0 64 0157F0 128 — Reserved(3) — JTAGEN Reserved(2) Reserved(3) — ICS<1:0> 02AFF0 256 0557F0 512 FPOR 0057F2 32 00AFF2 64 0157F2 128 — WDTWIN<1:0> ALTI2C2 ALTI2C1 Reserved(3) — — — 02AFF2 256 0557F2 512 FWDT 0057F4 32 00AFF4 64 0157F4 128 — FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0> 02AFF4 256 0557F4 512 FOSC 0057F6 32 00AFF6 64 0157F6 128 — FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0> 02AFF6 256 0557F6 512 FOSCSEL 0057F8 32 00AFF8 64 0157F8 128 — IESO PWMLOCK(1) — — — FNOSC<2:0> 02AFF8 256 0557F8 512 FGS 0057FA 32 00AFFA 64 0157FA 128 — — — — — — — GCP GWRP 02AFFA 256 0557FA 512 Reserved 0057FC 32 00AFFC 64 0157FC 128 — — — — — — — — — 02AFFC 256 0557FC 512 Reserved 057FFE 32 00AFFE 64 0157FE 128 — — — — — — — — — 02AFFE 256 0557FE 512 Legend: — = unimplemented, read as ‘1’. Note1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. 2: This bit is reserved and must be programmed as ‘0’. 3: These bits are reserved and must be programmed as ‘1’. DS70000657H-page 380  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 27-2: CONFIGURATION BITS DESCRIPTION Bit Field Description GCP General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = Code protection is enabled for the entire program memory space GWRP General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO Two-Speed Oscillator Start-up Enable bit 1 = Start up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start up device with user-selected oscillator source PWMLOCK(1) PWM Lock Enable bit 1 = Certain PWM registers may only be written after a key sequence 0 = PWM registers may be written without a key sequence FNOSC<2:0> Oscillator Selection bits 111 = Fast RC Oscillator with Divide-by-N (FRCDIVN) 110 = Fast RC Oscillator with Divide-by-16 (FRCDIV16) 101 = Low-Power RC Oscillator (LPRC) 100 = Reserved; do not use 011 = Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM<1:0> Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSCIOFNC OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is the clock output 0 = OSC2 is a general purpose digital I/O pin POSCMD<1:0> Primary Oscillator Mode Select bits 11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN Watchdog Timer Enable bit 1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect.) 0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode PLLKEN PLL Lock Enable bit 1 = PLL lock is enabled 0 = PLL lock is disabled Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. 2: When JTAGEN = 1, an internal pull-up resistor is enabled on the TMS pin. Erased devices default to JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins other than TMS for this purpose.  2011-2013 Microchip Technology Inc. DS70000657H-page 381

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 27-2: CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Description WDTPRE Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST<3:0> Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 WDTWIN<1:0> Watchdog Window Select bits 11 = WDT window is 25% of WDT period 10 = WDT window is 37.5% of WDT period 01 = WDT window is 50% of WDT period 00 = WDT window is 75% of WDT period ALTI2C1 Alternate I2C1 pin 1 = I2C1 is mapped to the SDA1/SCL1 pins 0 = I2C1 is mapped to the ASDA1/ASCL1 pins ALTI2C2 Alternate I2C2 pin 1 = I2C2 is mapped to the SDA2/SCL2 pins 0 = I2C2 is mapped to the ASDA2/ASCL2 pins JTAGEN(2) JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled ICS<1:0> ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. 2: When JTAGEN = 1, an internal pull-up resistor is enabled on the TMS pin. Erased devices default to JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins other than TMS for this purpose. DS70000657H-page 382  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X REGISTER 27-1: DEVID: DEVICE ID REGISTER R R R R R R R R DEVID<23:16>(1) bit 23 bit 16 R R R R R R R R DEVID<15:8>(1) bit 15 bit 8 R R R R R R R R DEVID<7:0>(1) bit 7 bit 0 Legend: R = Read-Only bit U = Unimplemented bit bit 23-0 DEVID<23:0>: Device Identifier bits(1) Note 1: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration Bits” (DS70663) for the list of device ID values. REGISTER 27-2: DEVREV: DEVICE REVISION REGISTER R R R R R R R R DEVREV<23:16>(1) bit 23 bit 16 R R R R R R R R DEVREV<15:8>(1) bit 15 bit 8 R R R R R R R R DEVREV<7:0>(1) bit 7 bit 0 Legend: R = Read-only bit U = Unimplemented bit bit 23-0 DEVREV<23:0>: Device Revision bits(1) Note 1: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration Bits” (DS70663) for the list of device revision values.  2011-2013 Microchip Technology Inc. DS70000657H-page 383

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 27.2 User ID Words FIGURE 27-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X REGULATOR(1,2,3) and PIC24EPXXXGP/MC20X devices contain four User ID Words, located at addresses, 0x800FF8 3.3V through 0x800FFE. The User ID Words can be used for dsPIC33E/PIC24E storing product information such as serial numbers, system manufacturing dates, manufacturing lot numbers and other application-specific information. VDD The User ID Words register map is shown in VCAP Table27-3. CEFC VSS TABLE 27-3: USER ID WORDS REGISTER MAP Note 1: These are typical operating voltages. File Name Address Bits 23-16 Bits 15-0 Refer to Table30-5 located in Section30.1 “DC Characteristics” for FUID0 0x800FF8 — UID0 the full operating ranges of VDD and VCAP. FUID1 0x800FFA — UID1 2: It is important for the low-ESR capacitor to be placed as close as possible to the FUID2 0x800FFC — UID2 VCAP pin. FUID3 0x800FFE — UID3 3: Typical VCAP pin voltage = 1.8V when Legend: — = unimplemented, read as ‘1’. VDD ≥ VDDMIN. 27.3 On-Chip Voltage Regulator 27.4 Brown-out Reset (BOR) All of the dsPIC33EPXXXGP50X, The Brown-out Reset (BOR) module is based on an dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ internal voltage reference circuit that monitors the reg- MC20X devices power their core digital logic at a ulated supply voltage, VCAP. The main purpose of the nominal 1.8V. This can create a conflict for designs that BOR module is to generate a device Reset when a are required to operate at a higher typical voltage, such brown-out condition occurs. Brown-out conditions are as 3.3V. To simplify system design, all devices in the generally caused by glitches on the AC mains (for dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X example, missing portions of the AC cycle waveform and PIC24EPXXXGP/MC20X family incorporate an on- due to bad power transmission lines or voltage sags chip regulator that allows the device to run its core logic due to excessive current draw when a large inductive from VDD. load is turned on). The regulator provides power to the core from the other A BOR generates a Reset pulse, which resets the VDD pins. A low-ESR (less than 1 Ohm) capacitor (such device. The BOR selects the clock source, based on as tantalum or ceramic) must be connected to the VCAP the device Configuration bit values (FNOSC<2:0> and pin (Figure27-1). This helps to maintain the stability of POSCMD<1:0>). the regulator. The recommended value for the filter If an oscillator mode is selected, the BOR activates the capacitor is provided in Table30-5 located in Oscillator Start-up Timer (OST). The system clock is Section30.0 “Electrical Characteristics”. held until OST expires. If the PLL is used, the clock is Note: It is important for the low-ESR capacitor to held until the LOCK bit (OSCCON<5>) is ‘1’. be placed as close as possible to the VCAP Concurrently, the PWRT Time-out (TPWRT) is applied pin. before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM is applied. The total delay in this case is TFSCM. Refer to Parameter SY35 in Table30-22 of Section30.0 “Electrical Characteristics” for specific TFSCM values. The BOR status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to oper- ate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. DS70000657H-page 384  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 27.5 Watchdog Timer (WDT) 27.5.2 SLEEP AND IDLE MODES For dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ If the WDT is enabled, it continues to run during Sleep or 50X and PIC24EPXXXGP/MC20X devices, the WDT is Idle modes. When the WDT time-out occurs, the device driven by the LPRC oscillator. When the WDT is wakes the device and code execution continues from enabled, the clock source is also enabled. where the PWRSAV instruction was executed. The corre- sponding SLEEP or IDLE bit (RCON<3,2>) needs to be 27.5.1 PRESCALER/POSTSCALER cleared in software after the device wakes up. The nominal WDT clock source from LPRC is 32kHz. 27.5.3 ENABLING WDT This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. The prescaler is set by the WDTPRE Configuration bit. With a 32kHz input, the prescaler yields a WDT Time- When the FWDTEN Configuration bit is set, the WDT is out period (TWDT), as shown in Parameter SY12 in always enabled. Table30-22. The WDT can be optionally controlled in software A variable postscaler divides down the WDT prescaler when the FWDTEN Configuration bit has been output and allows for a wide range of time-out periods. programmed to ‘0’. The WDT is enabled in software The postscaler is controlled by the WDTPOST<3:0> by setting the SWDTEN control bit (RCON<5>). The Configuration bits (FWDT<3:0>), which allow the SWDTEN control bit is cleared on any device Reset. selection of 16 settings, from 1:1 to 1:32,768. Using the The software WDT option allows the user application prescaler and postscaler, time-out periods ranging from to enable the WDT for critical code segments and 1ms to 131 seconds can be achieved. disable the WDT during non-critical segments for maximum power savings. The WDT, prescaler and postscaler are reset: The WDT flag bit, WDTO (RCON<4>), is not automatically • On any device Reset cleared following a WDT time-out. To detect subsequent • On the completion of a clock switch, whether WDT events, the flag must be cleared in software. invoked by software (i.e., setting the OSWEN bit after changing the NOSCx bits) or by hardware 27.5.4 WDT WINDOW (i.e., Fail-Safe Clock Monitor) The Watchdog Timer has an optional Windowed mode, • When a PWRSAV instruction is executed enabled by programming the WINDIS bit in the WDT (i.e., Sleep or Idle mode is entered) Configuration register (FWDT<6>). In the Windowed • When the device exits Sleep or Idle mode to mode (WINDIS = 0), the WDT should be cleared based resume normal operation on the settings in the programmable Watchdog Timer • By a CLRWDT instruction during normal execution Window select bits (WDTWIN<1:0>). Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 27-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> SWDTEN WDT FWDTEN Wake-up 1 RS RS Prescaler Postscaler LPRC Clock (Divide-by-N1) (Divide-by-N2) WDT 0 Reset WINDIS WDT Window Select WDTWIN<1:0> CLRWDT Instruction  2011-2013 Microchip Technology Inc. DS70000657H-page 385

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 27.6 JTAG Interface 27.8 In-Circuit Debugger dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X When MPLAB® ICD 3 or REAL ICE™ is selected as a and PIC24EPXXXGP/MC20X devices implement a debugger, the in-circuit debugging functionality is JTAG interface, which supports boundary scan device enabled. This function allows simple debugging func- testing. Detailed information on this interface is tions when used with MPLAB IDE. Debugging function- provided in future revisions of the document. ality is controlled through the PGECx (Emulation/ Debug Clock) and PGEDx (Emulation/Debug Data) pin Note: Refer to “Programming and Diagnostics” functions. (DS70608) in the “dsPIC33/PIC24 Family Reference Manual” for further information Any of the three pairs of debugging clock/data pins can on usage, configuration and operation of the be used: JTAG interface. • PGEC1 and PGED1 • PGEC2 and PGED2 27.7 In-Circuit Serial Programming • PGEC3 and PGED3 The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ To use the in-circuit debugger function of the device, 50X and PIC24EPXXXGP/MC20X devices can be the design must implement ICSP connections to serially programmed while in the end application circuit. MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In This is done with two lines for clock and data, and three addition, when the feature is enabled, some of the other lines for power, ground and the programming resources are not available for general use. These sequence. Serial programming allows customers to resources include the first 80 bytes of data RAM and manufacture boards with unprogrammed devices and two I/O pins (PGECx and PGEDx). then program the device just before shipping the product. Serial programming also allows the most recent 27.9 Code Protection and firmware or a custom firmware to be programmed. Refer CodeGuard™ Security to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration Bits” The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/ (DS70663) for details about In-Circuit Serial 50X, and PIC24EPXXXGP/MC20X devices offer basic Programming (ICSP). implementation of CodeGuard Security that supports only General Segment (GS) security. This feature helps Any of the three pairs of programming clock/data pins protect individual Intellectual Property. can be used: Note: Refer to “CodeGuard™ Security” • PGEC1 and PGED1 (DS70634) in the “dsPIC33/PIC24 Family • PGEC2 and PGED2 Reference Manual” for further information • PGEC3 and PGED3 on usage, configuration and operation of CodeGuard Security. DS70000657H-page 386  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 28.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: Note: This data sheet summarizes the features • The W register (with or without an address of the dsPIC33EPXXXGP50X, modifier) or file register (specified by the value of dsPIC33EPXXXMC20X/50X and ‘Ws’ or ‘f’) PIC24EPXXXGP/MC20X families of • The bit in the W register or file register (specified devices. It is not intended to be a by a literal value or indirectly by the contents of comprehensive reference source. To register ‘Wb’) complement the information in this data sheet, refer to the related section of the The literal instructions that involve data movement can “dsPIC33/PIC24 Family Reference use some of the following operands: Manual”, which is available from the • A literal value to be loaded into a W register or file Microchip web site (www.microchip.com). register (specified by ‘k’) The dsPIC33EP instruction set is almost identical to • The W register or file register where the literal that of the dsPIC30F and dsPIC33F. The PIC24EP value is to be loaded (specified by ‘Wb’ or ‘f’) instruction set is almost identical to that of the PIC24F However, literal instructions that involve arithmetic or and PIC24H. logical operations use some of the following operands: Most instructions are a single program memory word • The first source operand, which is a register ‘Wb’ (24 bits). Only three instructions require two program without any address modifier memory locations. • The second source operand, which is a literal Each single-word instruction is a 24-bit word, divided value into an 8-bit opcode, which specifies the instruction • The destination of the result (only if not the same type and one or more operands, which further specify as the first source operand), which is typically a the operation of the instruction. register ‘Wd’ with or without an address modifier The instruction set is highly orthogonal and is grouped The MAC class of DSP instructions can use some of the into five basic categories: following operands: • Word or byte-oriented operations • The accumulator (A or B) to be used (required • Bit-oriented operations operand) • Literal operations • The W registers to be used as the two operands • DSP operations • The X and Y address space prefetch operations • Control operations • The X and Y address space prefetch destinations Table28-1 lists the general symbols used in describing • The accumulator write back destination the instructions. The other DSP instructions do not involve any The dsPIC33E instruction set summary in Table28-2 multiplication and can include: lists all the instructions, along with the status flags • The accumulator to be used (required) affected by each instruction. • The source or destination operand (designated as Most word or byte-oriented W register instructions Wso or Wdo, respectively) with or without an (including barrel shift instructions) have three address modifier operands: • The amount of shift specified by a W register ‘Wn’ • The first source operand, which is typically a or a literal value register ‘Wb’ without any address modifier The control instructions can use some of the following • The second source operand, which is typically a operands: register ‘Ws’ with or without an address modifier • A program memory address • The destination of the result, which is typically a • The mode of the Table Read and Table Write register ‘Wd’ with or without an address modifier instructions However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’  2011-2013 Microchip Technology Inc. DS70000657H-page 387

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Most instructions are a single word. Certain double-word two or three cycles if the skip is performed, depending on instructions are designed to provide all the required whether the instruction being skipped is a single-word or information in these 48 bits. In the second word, the two-word instruction. Moreover, double-word moves 8MSbs are ‘0’s. If this second word is executed as an require two cycles. instruction (by itself), it executes as a NOP. Note: For more details on the instruction set, The double-word instructions execute in two instruction refer to the “16-bit MCU and DSC cycles. Programmer’s Reference Manual” Most single-word instructions are executed in a single (DS70157). instruction cycle, unless a conditional test is true, or the For more information on instructions that Program Counter is changed as a result of the instruction, take more than one instruction cycle to or a PSV or Table Read is performed, or an SFR register execute, refer to “CPU” (DS70359) in is read. In these cases, the execution takes multiple the “dsPIC33/PIC24 Family Reference instruction cycles with the additional instruction cycle(s) Manual”, particularly the “Instruction executed as a NOP. Certain instructions that involve Flow Types” section. skipping over the subsequent instruction require either TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation a  {b, c, d} a is selected from the set of values b, c, d <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write back destination address register {W13, [W13]+ = 2} bit4 4-bitbit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0x0000...0x1FFF} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0...W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } DS70000657H-page 388  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm,Wn Dividend, Divisor working register pair (direct addressing) Wm*Wm Multiplicand and Multiplier working register pair for Square instructions  {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions  {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers {W0...W15} Wnd One of 16 destination working registers {W0...W15} Wns One of 16 source working registers {W0...W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register  { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X Data Space Prefetch Address register for DSP instructions  {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7} Wy Y Data Space Prefetch Address register for DSP instructions  {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}  2011-2013 Microchip Technology Inc. DS70000657H-page 389

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 28-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 1 ADD ADD Acc(1) Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (4) None BRA GE,Expr Branch if greater than or equal 1 1 (4) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (4) None BRA GT,Expr Branch if greater than 1 1 (4) None BRA GTU,Expr Branch if unsigned greater than 1 1 (4) None BRA LE,Expr Branch if less than or equal 1 1 (4) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (4) None BRA LT,Expr Branch if less than 1 1 (4) None BRA LTU,Expr Branch if unsigned less than 1 1 (4) None BRA N,Expr Branch if Negative 1 1 (4) None BRA NC,Expr Branch if Not Carry 1 1 (4) None BRA NN,Expr Branch if Not Negative 1 1 (4) None BRA NOV,Expr Branch if Not Overflow 1 1 (4) None BRA NZ,Expr Branch if Not Zero 1 1 (4) None BRA OA,Expr(1) Branch if Accumulator A overflow 1 1 (4) None BRA OB,Expr(1) Branch if Accumulator B overflow 1 1 (4) None BRA OV,Expr(1) Branch if Overflow 1 1 (4) None BRA SA,Expr(1) Branch if Accumulator A saturated 1 1 (4) None BRA SB,Expr(1) Branch if Accumulator B saturated 1 1 (4) None BRA Expr Branch Unconditionally 1 4 None BRA Z,Expr Branch if Zero 1 1 (4) None BRA Wn Computed Branch 1 4 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None Note1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. DS70000657H-page 390  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 4 SFA CALL Wn Call indirect subroutine 1 4 SFA CALL.L Wn Call indirect subroutine (long address) 1 4 SFA 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB(1) Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit8 Compare Wb with lit8 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit8 Compare Wb with lit8, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) CPBEQ CPBEQ Wb,Wn,Expr Compare Wb with Wn, branch if = 1 1 (5) None 22 CPSGT CPSGT Wb,Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) CPBGT CPBGT Wb,Wn,Expr Compare Wb with Wn, branch if > 1 1 (5) None 23 CPSLT CPSLT Wb,Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) CPBLT CPBLT Wb,Wn,Expr Compare Wb with Wn, branch if < 1 1 (5) None 24 CPSNE CPSNE Wb,Wn Compare Wb with Wn, skip if  1 1 None (2 or 3) CPBNE CPBNE Wb,Wn,Expr Compare Wb with Wn, branch if  1 1 (5) None Note1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2013 Microchip Technology Inc. DS70000657H-page 391

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn(1) Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit15,Expr(1) Do code to PC + Expr, lit15 + 1 times 2 2 None DO Wn,Expr(1) Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd(1) Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd(1) Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 4 None GOTO Wn Go to indirect 1 4 None GOTO.L Wn Go to indirect (long address) 1 4 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 SFA 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB(1) Multiply and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(1) Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB Note1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. DS70000657H-page 392  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 None MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to 1 2 None Wd MOV.D Ws,Wnd Move Double from Ws to W(nd + 1 2 None 1):W(nd) 47 MOVPAG MOVPAG #lit10,DSRPAG Move 10-bit literal to DSRPAG 1 1 None MOVPAG #lit9,DSWPAG Move 9-bit literal to DSWPAG 1 1 None MOVPAG #lit8,TBLPAG Move 8-bit literal to TBLPAG 1 1 None MOVPAG Ws, DSRPAG Move Ws<9:0> to DSRPAG 1 1 None MOVPAG Ws, DSWPAG Move Ws<8:0> to DSWPAG 1 1 None MOVPAG Ws, TBLPAG Move Ws<7:0> to TBLPAG 1 1 None 48 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB(1) Prefetch and store accumulator 1 1 None 49 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(1) Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(1) Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 50 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(1) -(Multiply Wm by Wn) to Accumulator 1 1 None 51 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB(1) Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, SA,SB,SAB Note1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2013 Microchip Technology Inc. DS70000657H-page 393

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 52 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None signed(Ws) MUL.SS Wb,Ws,Acc(1) Accumulator = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,Ws,Acc(1) Accumulator = signed(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Acc(1) Accumulator = signed(Wb) * 1 1 None unsigned(lit5) MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None signed(Ws) MUL.US Wb,Ws,Acc(1) Accumulator = unsigned(Wb) * 1 1 None signed(Ws) MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.UU Wb,#lit5,Acc(1) Accumulator = unsigned(Wb) * 1 1 None unsigned(lit5) MUL.UU Wb,Ws,Acc(1) Accumulator = unsigned(Wb) * 1 1 None unsigned(Ws) MULW.SS Wb,Ws,Wnd Wnd = signed(Wb) * signed(Ws) 1 1 None MULW.SU Wb,Ws,Wnd Wnd = signed(Wb) * unsigned(Ws) 1 1 None MULW.US Wb,Ws,Wnd Wnd = unsigned(Wb) * signed(Ws) 1 1 None MULW.UU Wb,Ws,Wnd Wnd = unsigned(Wb) * unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None unsigned(lit5) MUL.SU Wb,#lit5,Wnd Wnd = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL.UU Wb,#lit5,Wnd Wnd = unsigned(Wb) * unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None Note1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. DS70000657H-page 394  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 53 NEG NEG Acc(1) Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 54 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 55 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd + 1) POP.S Pop Shadow Registers 1 1 All 56 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack 1 2 None (TOS) PUSH.S Push Shadow Registers 1 1 None 57 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 58 RCALL RCALL Expr Relative Call 1 4 SFA RCALL Wn Computed Call 1 4 SFA 59 REPEAT REPEAT #lit15 Repeat Next Instruction lit15 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 60 RESET RESET Software device Reset 1 1 None 61 RETFIE RETFIE Return from interrupt 1 6 (5) SFA 62 RETLW RETLW #lit10,Wn Return with literal in Wn 1 6 (5) SFA 63 RETURN RETURN Return from Subroutine 1 6 (5) SFA 64 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 65 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 66 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z 67 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 68 SAC SAC Acc,#Slit4,Wdo(1) Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo(1) Store Rounded Accumulator 1 1 None 69 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z 70 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 71 SFTAC SFTAC Acc,Wn(1) Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6(1) Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB Note1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2013 Microchip Technology Inc. DS70000657H-page 395

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 72 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 73 SUB SUB Acc(1) Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 74 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 75 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z 76 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 77 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 78 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 5 None 79 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 5 None 80 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 81 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 82 ULNK ULNK Unlink Frame Pointer 1 1 SFA 83 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 84 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N Note1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. DS70000657H-page 396  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 29.0 DEVELOPMENT SUPPORT 29.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2011-2013 Microchip Technology Inc. DS70000657H-page 397

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 29.2 MPLAB XC Compilers 29.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other related modules together relocatable object files and archives to create an exe- • Flexible creation of libraries with easy module cutable file. MPLAB XC Compiler uses the assembler listing, replacement, deletion and extraction to produce its object file. Notable features of the assembler include: 29.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 29.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS70000657H-page 398  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 29.6 MPLAB X SIM Software Simulator 29.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 29.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 29.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com- with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 29.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2011-2013 Microchip Technology Inc. DS70000657H-page 399

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 29.11 Demonstration/Development 29.12 Third-Party Development Tools Boards, Evaluation Kits and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS70000657H-page 400  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS.......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS(3)....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD3.0V(3)................................................... -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3)................................................... -0.3V to +3.6V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................300 mA Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA Maximum current sunk/sourced by any 8x I/O pin..................................................................................................25 mA Maximum current sunk by all ports(2,4).................................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table30-2). 3: See the “Pin Diagrams” section for the 5V tolerant pins. 4: Exceptions are: dsPIC33EPXXXGP502, dsPIC33EPXXXMC202/502 and PIC24EPXXXGP/MC202 devices, which have a maximum sink/source capability of 130 mA.  2011-2013 Microchip Technology Inc. DS70000657H-page 401

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 30.1 DC Characteristics TABLE 30-1: OPERATING MIPS VS. VOLTAGE Maximum MIPS Characteristic VDD Range Temp Range dsPIC33EPXXXGP50X, (in Volts) (in °C) dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X — 3.0V to 3.6V(1) -40°C to +85°C 70 — 3.0V to 3.6V(1) -40°C to +125°C 60 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. TABLE 30-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typ. Max. Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Extended Temperature Devices Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ. Max. Unit Notes Package Thermal Resistance, 64-Pin QFN JA 28.0 — °C/W 1 Package Thermal Resistance, 64-Pin TQFP 10x10 mm JA 48.3 — °C/W 1 Package Thermal Resistance, 48-Pin UQFN 6x6 mm JA 41 — °C/W 1 Package Thermal Resistance, 44-Pin QFN JA 29.0 — °C/W 1 Package Thermal Resistance, 44-Pin TQFP 10x10 mm JA 49.8 — °C/W 1 Package Thermal Resistance, 44-Pin VTLA 6x6 mm JA 25.2 — °C/W 1 Package Thermal Resistance, 36-Pin VTLA 5x5 mm JA 28.5 — °C/W 1 Package Thermal Resistance, 28-Pin QFN-S JA 30.0 — °C/W 1 Package Thermal Resistance, 28-Pin SSOP JA 71.0 — °C/W 1 Package Thermal Resistance, 28-Pin SOIC JA 69.7 — °C/W 1 Package Thermal Resistance, 28-Pin SPDIP JA 60.0 — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS70000657H-page 402  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions (see Note 1): 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. Operating Voltage DC10 VDD Supply Voltage 3.0 — 3.6 V DC16 VPOR VDD Start Voltage — — VSS V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.03 — — V/ms 0V-1V in 100 ms to Ensure Internal Power-on Reset Signal Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. TABLE 30-5: FILTER CAPACITOR (CEFC) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated): Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristics Min. Typ. Max. Units Comments No. CEFC External Filter Capacitor 4.7 10 — F Capacitor must have a low Value(1) series resistance (< 1 Ohm) Note 1: Typical VCAP voltage = 1.8 volts when VDD  VDDMIN.  2011-2013 Microchip Technology Inc. DS70000657H-page 403

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Parameter Typ. Max. Units Conditions No. Operating Current (IDD)(1) DC20d 9 15 mA -40°C DC20a 9 15 mA +25°C 3.3V 10 MIPS DC20b 9 15 mA +85°C DC20c 9 15 mA +125°C DC22d 16 25 mA -40°C DC22a 16 25 mA +25°C 3.3V 20 MIPS DC22b 16 25 mA +85°C DC22c 16 25 mA +125°C DC24d 27 40 mA -40°C DC24a 27 40 mA +25°C 3.3V 40 MIPS DC24b 27 40 mA +85°C DC24c 27 40 mA +125°C DC25d 36 55 mA -40°C DC25a 36 55 mA +25°C 3.3V 60 MIPS DC25b 36 55 mA +85°C DC25c 36 55 mA +125°C DC26d 41 60 mA -40°C DC26a 41 60 mA +25°C 3.3V 70 MIPS DC26b 41 60 mA +85°C Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU is executing while(1){NOP();} statement • JTAG is disabled DS70000657H-page 404  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA +85°C for Industrial -40°C  TA +125°C for Extended Parameter Typ. Max. Units Conditions No. Idle Current (IIDLE)(1) DC40d 3 8 mA -40°C DC40a 3 8 mA +25°C 3.3V 10 MIPS DC40b 3 8 mA +85°C DC40c 3 8 mA +125°C DC42d 6 12 mA -40°C DC42a 6 12 mA +25°C 3.3V 20 MIPS DC42b 6 12 mA +85°C DC42c 6 12 mA +125°C DC44d 11 18 mA -40°C DC44a 11 18 mA +25°C 3.3V 40 MIPS DC44b 11 18 mA +85°C DC44c 11 18 mA +125°C DC45d 17 27 mA -40°C DC45a 17 27 mA +25°C 3.3V 60 MIPS DC45b 17 27 mA +85°C DC45c 17 27 mA +125°C DC46d 20 35 mA -40°C DC46a 20 35 mA +25°C 3.3V 70 MIPS DC46b 20 35 mA +85°C Note 1: Base Idle current (IIDLE) is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • The NVMSIDL bit (NVMCON<12>) = 1 (i.e., Flash regulator is set to standby while the device is in Idle mode) • The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode) • JTAG is disabled  2011-2013 Microchip Technology Inc. DS70000657H-page 405

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Parameter Typ. Max. Units Conditions No. Power-Down Current (IPD)(1) – dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X and PIC24EP32GP/MC20X DC60d 30 100 A -40°C DC60a 35 100 A +25°C 3.3V DC60b 150 200 A +85°C DC60c 250 500 A +125°C Power-Down Current (IPD)(1) – dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X and PIC24EP64GP/MC20X DC60d 25 100 A -40°C DC60a 30 100 A +25°C 3.3V DC60b 150 350 A +85°C DC60c 350 800 A +125°C Power-Down Current (IPD)(1) – dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X and PIC24EP128GP/MC20X DC60d 30 100 A -40°C DC60a 35 100 A +25°C 3.3V DC60b 150 350 A +85°C DC60c 550 1000 A +125°C Power-Down Current (IPD)(1) – dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X and PIC24EP256GP/MC20X DC60d 35 100 A -40°C DC60a 40 100 A +25°C 3.3V DC60b 250 450 A +85°C DC60c 1000 1200 A +125°C Power-Down Current (IPD)(1) – dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X and PIC24EP512GP/MC20X DC60d 40 100 A -40°C DC60a 45 100 A +25°C 3.3V DC60b 350 800 A +85°C DC60c 1100 1500 A +125°C Note 1: IPD (Sleep) current is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • All peripheral modules are disabled (PMDx bits are all set) • The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to standby while the device is in Sleep mode) • The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode) • JTAG is disabled DS70000657H-page 406  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-9: DC CHARACTERISTICS: WATCHDOG TIMER DELTA CURRENT (IWDT)(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Parameter No. Typ. Max. Units Conditions DC61d 8 — A -40°C DC61a 10 — A +25°C 3.3V DC61b 12 — A +85°C DC61c 13 — A +125°C Note 1: The IWDT current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. All parameters are characterized but not tested during manufacturing. TABLE 30-10: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°C TA  +125°C for Extended Doze Parameter No. Typ. Max. Units Conditions Ratio Doze Current (IDOZE)(1) DC73a(2) 35 — 1:2 mA -40°C 3.3V FOSC = 140 MHz DC73g 20 30 1:128 mA DC70a(2) 35 — 1:2 mA +25°C 3.3V FOSC = 140 MHz DC70g 20 30 1:128 mA DC71a(2) 35 — 1:2 mA +85°C 3.3V FOSC = 140 MHz DC71g 20 30 1:128 mA DC72a(2) 28 — 1:2 mA +125°C 3.3V FOSC = 120 MHz DC72g 15 30 1:128 mA Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU is executing while(1) statement • JTAG is disabled 2: Parameter is characterized but not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 407

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. VIL Input Low Voltage DI10 Any I/O Pin and MCLR VSS — 0.2VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled VIH Input High Voltage DI20 I/O Pins Not 5V Tolerant 0.8VDD — VDD V (Note 3) I/O Pins 5V Tolerant and 0.8VDD — 5.5 V (Note 3) MCLR I/O Pins with SDAx, SCLx 0.8 VDD — 5.5 V SMBus disabled I/O Pins with SDAx, SCLx 2.1 — 5.5 V SMBus enabled ICNPU Change Notification Pull-up Current DI30 150 250 550 A VDD = 3.3V, VPIN = VSS ICNPD Change Notification Pull-Down Current(4) DI31 20 50 100 A VDD = 3.3V, VPIN = VDD Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 4: VIL source < (VSS – 0.3). Characterized but not tested. 5: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 6: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 7: Non-zero injection currents can affect the ADC results by approximately 4-6 counts. 8: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70000657H-page 408  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. IIL Input Leakage Current(1,2) DI50 I/O Pins 5V Tolerant(3) -1 — +1 A VSS  VPIN  VDD, Pin at high-impedance DI51 I/O Pins Not 5V Tolerant(3) -1 — +1 A VSS  VPIN  VDD, Pin at high-impedance, -40°C TA +85°C DI51a I/O Pins Not 5V Tolerant(3) -1 — +1 A Analog pins shared with external reference pins, -40°CTA  +85°C DI51b I/O Pins Not 5V Tolerant(3) -1 — +1 A VSS  VPIN  VDD, Pin at high-impedance, -40°CTA +125°C DI51c I/O Pins Not 5V Tolerant(3) -1 — +1 A Analog pins shared with external reference pins, -40°CTA +125°C DI55 MCLR -5 — +5 A VSS VPIN VDD DI56 OSC1 -5 — +5 A VSS VPIN VDD, XT and HS modes Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 4: VIL source < (VSS – 0.3). Characterized but not tested. 5: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 6: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 7: Non-zero injection currents can affect the ADC results by approximately 4-6 counts. 8: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.  2011-2013 Microchip Technology Inc. DS70000657H-page 409

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. IICL Input Low Injection Current DI60a 0 — -5(4,7) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP and RB7 IICH Input High Injection Current DI60b 0 — +5(5,6,7) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, RB7 and all 5V tolerant pins(6) IICT Total Input Injection Current DI60c (sum of all I/O and control -20(8) — +20(8) mA Absolute instantaneous sum pins) of all ± input injection cur- rents from all I/O pins (| IICL + | IICH |)  IICT Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 4: VIL source < (VSS – 0.3). Characterized but not tested. 5: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 6: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 7: Non-zero injection currents can affect the ADC results by approximately 4-6 counts. 8: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70000657H-page 410  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions DO10 VOL Output Low Voltage — — 0.4 V VDD = 3.3V, 4x Sink Driver Pins(2) IOL  6 mA, -40°C TA +85°C IOL  5 mA, +85°C TA +125°C Output Low Voltage — — 0.4 V VDD = 3.3V, 8x Sink Driver Pins(3) IOL  12 mA, -40°C TA +85°C IOL  8 mA, +85°C TA +125°C DO20 VOH Output High Voltage 2.4 — — V IOH  -10 mA, VDD = 3.3V 4x Source Driver Pins(2) Output High Voltage 2.4 — — V IOH  -15 mA, VDD = 3.3V 8x Source Driver Pins(3) DO20A VOH1 Output High Voltage 1.5(1) — — V IOH  -14 mA, VDD = 3.3V 4x Source Driver Pins(2) 2.0(1) — — IOH  -12 mA, VDD = 3.3V 3.0(1) — — IOH  -7 mA, VDD = 3.3V Output High Voltage 1.5(1) — — V IOH  -22 mA, VDD = 3.3V 8x Source Driver Pins(3) 2.0(1) — — IOH  -18 mA, VDD = 3.3V 3.0(1) — — IOH  -10 mA, VDD = 3.3V Note 1: Parameters are characterized but not tested. 2: Includes all I/O pins that are not 8x Sink Driver pins (see below). 3: Includes the following pins: For devices with less than 64 pins: RA3, RA4, RA9, RB<7:15> and RC3 For 64-pin devices: RA4, RA9, RB<7:15>, RC3 and RC15 TABLE 30-13: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic Min.(2) Typ. Max. Units Conditions No. BO10 VBOR BOR Event on VDD Transition 2.65 — 2.95 V VDD High-to-Low (Notes 2 and 3) Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. 2: Parameters are for design guidance only and are not tested in manufacturing. 3: The VBOR specification is relative to VDD.  2011-2013 Microchip Technology Inc. DS70000657H-page 411

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-14: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic Min. Typ.(1) Max. Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10,000 — — E/W -40C to +125C D131 VPR VDD for Read 3.0 — 3.6 V D132b VPEW VDD for Self-Timed Write 3.0 — 3.6 V D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated, -40C to +125C D135 IDDP Supply Current during — 10 — mA Programming(2) D136 IPEAK Instantaneous Peak Current — — 150 mA During Start-up D137a TPE Page Erase Time 17.7 — 22.9 ms TPE = 146893 FRC cycles, TA = +85°C (See Note 3) D137b TPE Page Erase Time 17.5 — 23.1 ms TPE = 146893 FRC cycles, TA = +125°C (See Note 3) D138a TWW Word Write Cycle Time 41.7 — 53.8 µs TWW = 346 FRC cycles, TA = +85°C (See Note 3) D138b TWW Word Write Cycle Time 41.2 — 54.4 µs TWW = 346 FRC cycles, TA = +125°C (See Note 3) Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: Parameter characterized but not tested in manufacturing. 3: Other conditions: FRC = 7.37 MHz, TUN<5:0> = 011111 (for Minimum), TUN<5:0> = 100000 (for Maximum). This parameter depends on the FRC accuracy (see Table30-19) and the value of the FRC Oscillator Tuning register (see Register9-4). For complete details on calculating the Minimum and Maximum time, see Section5.3 “Programming Operations”. DS70000657H-page 412  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 30.2 AC Characteristics and Timing Parameters This section defines dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X AC characteristics and timing parameters. TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS -40°C TA +125°C for Extended Operating voltage VDD range as described in Section30.1 “DC Characteristics”. FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min. Typ. Max. Units Conditions No. DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes, when external clock is used to drive OSC1 DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode  2011-2013 Microchip Technology Inc. DS70000657H-page 413

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symb Characteristic Min. Typ.(1) Max. Units Conditions No. OS10 FIN External CLKI Frequency DC — 60 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.5 — 10 MHz XT 10 — 25 MHz HS OS20 TOSC TOSC = 1/FOSC 8.33 — DC ns +125ºC TOSC = 1/FOSC 7.14 — DC ns +85ºC OS25 TCY Instruction Cycle Time(2) 16.67 — DC ns +125ºC Instruction Cycle Time(2) 14.28 — DC ns +85ºC OS30 TosL, External Clock in (OSC1) 0.45 x TOSC — 0.55 x TOSC ns EC TosH High or Low Time OS31 TosR, External Clock in (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3,4) — 5.2 — ns OS41 TckF CLKO Fall Time(3,4) — 5.2 — ns OS42 GM External Oscillator — 12 — mA/V HS, VDD = 3.3V, Transconductance(4) TA = +25ºC — 6 — mA/V XT, VDD = 3.3V, TA = +25ºC Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “Maximum” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: This parameter is characterized, but not tested in manufacturing. DS70000657H-page 414  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic Min. Typ.(1) Max. Units Conditions No. OS50 FPLLI PLL Voltage Controlled Oscillator 0.8 — 8.0 MHz ECPLL, XTPLL modes (VCO) Input Frequency Range OS51 FVCO On-Chip VCO System Frequency 120 — 340 MHz OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 ms OS53 DCLK CLKO Stability (Jitter)(2) -3 0.5 3 % Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for individual time bases, or communication clocks used by the application, use the following formula: DCLK Effective Jitter = ------------------------------------------------------------------------------------------- FOSC --------------------------------------------------------------------------------------- Time Base or Communication Clock For example, if FOSC = 120 MHz and the SPIx bit rate = 10 MHz, the effective jitter is as follows: DCLK DCLK DCLK Effective Jitter = -------------- = -------------- = -------------- 120 12 3.464 --------- 10 TABLE 30-19: INTERNAL FRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Characteristic Min. Typ. Max. Units Conditions No. Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1) F20a FRC -1.5 0.5 +1.5 % -40°C  TA -10°C VDD = 3.0-3.6V -1 0.5 +1 % -10°C  TA +85°C VDD = 3.0-3.6V F20b FRC -2 1 +2 % +85°C TA +125°C VDD = 3.0-3.6V Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift. TABLE 30-20: INTERNAL LPRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Characteristic Min. Typ. Max. Units Conditions No. LPRC @ 32.768 kHz(1) F21a LPRC -30 — +30 % -40°C TA -10°C VDD = 3.0-3.6V -20 — +20 % -10°C TA +85°C VDD = 3.0-3.6V F21b LPRC -30 — +30 % +85°C TA +125°C VDD = 3.0-3.6V Note 1: The change of LPRC frequency as VDD changes.  2011-2013 Microchip Technology Inc. DS70000657H-page 415

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure30-1 for load conditions. TABLE 30-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for Industrial -40°C  TA +125°C for Extended Param Symbol Characteristic Min. Typ.(1) Max. Units Conditions No. DO31 TIOR Port Output Rise Time — 5 10 ns DO32 TIOF Port Output Fall Time — 5 10 ns DI35 TINP INTx Pin High or Low Time (input) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. FIGURE 30-4: BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS MCLR TMCLR (SY20) BOR TBOR Various Delays (depending on configuration) (SY30) Reset Sequence CPU Starts Fetching Code DS70000657H-page 416  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions No. SY00 TPU Power-up Period — 400 600 s SY10 TOST Oscillator Start-up Time — 1024TOSC — — TOSC = OSC1 period SY12 TWDT Watchdog Timer 0.81 0.98 1.22 ms WDTPRE = 0, Time-out Period WDTPOST<3:0> = 0000, using LPRC tolerances indicated in F21 (see Table30-20) at +85ºC 3.26 3.91 4.88 ms WDTPRE = 1, WDTPOST<3:0> = 0000, using LPRC tolerances indicated in F21 (see Table30-20) at +85ºC SY13 TIOZ I/O High-Impedance 0.68 0.72 1.2 s from MCLR Low or Watchdog Timer Reset SY20 TMCLR MCLR Pulse Width (low) 2 — — s SY30 TBOR BOR Pulse Width (low) 1 — — s SY35 TFSCM Fail-Safe Clock Monitor — 500 900 s -40°C to +85°C Delay SY36 TVREG Voltage Regulator — — 30 s Standby-to-Active mode Transition Time SY37 TOSCDFRC FRC Oscillator Start-up 46 48 54 s Delay SY38 TOSCDLPRC LPRC Oscillator Start-up — — 70 s Delay Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.  2011-2013 Microchip Technology Inc. DS70000657H-page 417

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-5: TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure30-1 for load conditions. TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(2) Min. Typ. Max. Units Conditions No. TA10 TTXH T1CK High Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TA15, (TCY + 20)/N N = prescaler value (1, 8, 64, 256) Asynchronous 35 — — ns TA11 TTXL T1CK Low Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TA15, (TCY + 20)/N N = prescaler value (1, 8, 64, 256) Asynchronous 10 — — ns TA15 TTXP T1CK Input Synchronous Greater of: — — ns N = prescale value Period mode 40 or (1, 8, 64, 256) (2 TCY + 40)/N OS60 Ft1 T1CK Oscillator Input DC — 50 kHz Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) TA20 TCKEXTMRL Delay from External T1CK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: Timer1 is a Type A. 2: These parameters are characterized, but are not tested in manufacturing. DS70000657H-page 418  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X T ABLE 30-24: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Min. Typ. Max. Units Conditions No. TB10 TtxH TxCK High Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TB15, (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB11 TtxL TxCK Low Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TB15, (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB15 TtxP TxCK Synchronous Greater of: — — ns N = prescale Input mode 40 or value Period (2 TCY + 40)/N (1, 8, 64, 256) TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing. TABLE 30-25: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Min. Typ. Max. Units Conditions No. TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC15 TtxP TxCK Input Synchronous, 2 TCY + 40 — — ns N = prescale Period with prescaler value (1, 8, 64, 256) TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 419

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure30-1 for load conditions. TABLE 30-26: INPUT CAPTURE x MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol Characteristics(1) Min. Max. Units Conditions No. IC10 TCCL ICx Input Low Time Greater of — ns Must also meet 12.5 + 25 or Parameter IC15 (0.5 TCY/N) + 25 IC11 TCCH ICx Input High Time Greater of — ns Must also meet 12.5 + 25 or Parameter IC15 N = prescale value (0.5 TCY/N) + 25 (1, 4, 16) IC15 TCCP ICx Input Period Greater of — ns 25 + 50 or (1 TCY/N) + 50 Note 1: These parameters are characterized, but not tested in manufacturing. DS70000657H-page 420  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-7: OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare x or PWMx Mode) OC11 OC10 Note: Refer to Figure30-1 for load conditions. TABLE 30-27: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Min. Typ. Max. Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 30-8: OCx/PWMx MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx TABLE 30-28: OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Min. Typ. Max. Units Conditions No. OC15 TFD Fault Input to PWMx I/O — — TCY + 20 ns Change OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns Note 1: These parameters are characterized but not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 421

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) MP30 Fault Input (active-low) MP20 PWMx FIGURE 30-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) MP11 MP10 PWMx Note: Refer to Figure30-1 for load conditions. TABLE 30-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Min. Typ. Max. Units Conditions No. MP10 TFPWM PWMx Output Fall Time — — — ns See Parameter DO32 MP11 TRPWM PWMx Output Rise Time — — — ns See Parameter DO31 MP20 TFD Fault Input  to PWMx — — 15 ns I/O Change MP30 TFH Fault Input Pulse Width 15 — — ns Note 1: These parameters are characterized but not tested in manufacturing. DS70000657H-page 422  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-11: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY) QEB TQ10 TQ11 TQ15 TQ20 POSCNT TABLE 30-30: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS (dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Min. Typ. Max. Units Conditions No. TQ10 TtQH TQCK High Synchronous, Greater of 12.5 + 25 — — ns Must also meet Time with prescaler or Parameter TQ15 (0.5 TCY/N) + 25 TQ11 TtQL TQCK Low Synchronous, Greater of 12.5 + 25 — — ns Must also meet Time with prescaler or Parameter TQ15 (0.5 TCY/N) + 25 TQ15 TtQP TQCP Input Synchronous, Greater of 25 + 50 — — ns Period with prescaler or (1 TCY/N) + 50 TQ20 TCKEXTMRL Delay from External TQCK — 1 TCY — Clock Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 423

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-12: QEA/QEB INPUT CHARACTERISTICS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) TQ36 QEA (input) TQ31 TQ30 TQ35 QEB (input) TQ41 TQ40 TQ31 TQ30 TQ35 QEB Internal TABLE 30-31: QUADRATURE DECODER TIMING REQUIREMENTS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Typ.(2) Max. Units Conditions No. TQ30 TQUL Quadrature Input Low Time 6 TCY — ns TQ31 TQUH Quadrature Input High Time 6 TCY — ns TQ35 TQUIN Quadrature Input Period 12 TCY — ns TQ36 TQUP Quadrature Phase Period 3 TCY — ns TQ40 TQUFL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, 128 with Digital Filter and 256 (Note 3) TQ41 TQUFH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, 128 with Digital Filter and 256 (Note 3) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: N = Index Channel Digital Filter Clock Divide Select bits. Refer to “Quadrature Encoder Interface (QEI)” (DS70601) in the “dsPIC33/PIC24 Family Reference Manual”. Please see the Microchip web site for the latest family reference manual sections. DS70000657H-page 424  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-13: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) QEA (input) QEB (input) Ungated Index TQ51 TQ50 Index Internal TQ55 Position Counter Reset TABLE 30-32: QEI INDEX PULSE TIMING REQUIREMENTS (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(1) Min. Max. Units Conditions No. TQ50 TqiL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ51 TqiH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ55 Tqidxr Index Pulse Recognized to Position 3 TCY — ns Counter Reset (ungated index) Note 1: These parameters are characterized but not tested in manufacturing. 2: Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on the falling edge.  2011-2013 Microchip Technology Inc. DS70000657H-page 425

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-33: SPI2 MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table30-33 — — 0,1 0,1 0,1 9 MHz — Table30-34 — 1 0,1 1 9 MHz — Table30-35 — 0 0,1 1 15 MHz — — Table30-36 1 0 0 11 MHz — — Table30-37 1 1 0 15 MHz — — Table30-38 0 1 0 11 MHz — — Table30-39 0 0 0 FIGURE 30-14: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE=0) TIMING CHARACTERISTICS SCK2 (CKP = 0) SP10 SP21 SP20 SCK2 (CKP = 1) SP35 SP20 SP21 SDO2 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 426  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-15: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE=1) TIMING CHARACTERISTICS SP36 SCK2 (CKP = 0) SP10 SP21 SP20 SCK2 (CKP = 1) SP35 SP20 SP21 SDO2 MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure30-1 for load conditions. TABLE 30-34: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 FscP Maximum SCK2 Frequency — — 15 MHz (Note 3) SP20 TscF SCK2 Output Fall Time — — — ns See Parameter DO32 (Note 4) SP21 TscR SCK2 Output Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns TscL2doV SCK2 Edge SP36 TdiV2scH, SDO2 Data Output Setup to 30 — — ns TdiV2scL First SCK2 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI2 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 427

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-16: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP=1) TIMING CHARACTERISTICS SP36 SCK2 (CKP = 0) SP10 SP21 SP20 SCK2 (CKP = 1) SP35 SP20 SP21 SDO2 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDI2 MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-35: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 FscP Maximum SCK2 Frequency — — 9 MHz (Note 3) SP20 TscF SCK2 Output Fall Time — — — ns See Parameter DO32 (Note 4) SP21 TscR SCK2 Output Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns TscL2doV SCK2 Edge SP36 TdoV2sc, SDO2 Data Output Setup to 30 — — ns TdoV2scL First SCK2 Edge SP40 TdiV2scH, Setup Time of SDI2 Data 30 — — ns TdiV2scL Input to SCK2 Edge SP41 TscH2diL, Hold Time of SDI2 Data Input 30 — — ns TscL2diL to SCK2 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI2 pins. DS70000657H-page 428  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-17: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP=1) TIMING CHARACTERISTICS SCK2 (CKP = 0) SP10 SP21 SP20 SCK2 (CKP = 1) SP35SP36 SP20 SP21 SDO2 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDI2 MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-36: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 FscP Maximum SCK2 Frequency — — 9 MHz -40ºC to +125ºC (Note 3) SP20 TscF SCK2 Output Fall Time — — — ns See Parameter DO32 (Note 4) SP21 TscR SCK2 Output Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns TscL2doV SCK2 Edge SP36 TdoV2scH, SDO2 Data Output Setup to 30 — — ns TdoV2scL First SCK2 Edge SP40 TdiV2scH, Setup Time of SDI2 Data 30 — — ns TdiV2scL Input to SCK2 Edge SP41 TscH2diL, Hold Time of SDI2 Data Input 30 — — ns TscL2diL to SCK2 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI2 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 429

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-18: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SS2 SP50 SP52 SCK2 (CKP = 0) SP70 SP73 SP72 SCK2 (CKP = 1) SP36 SP35 SP72 SP73 SDO2 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDI2 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 430  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-37: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK2 Input — — Lesser MHz (Note 3) Frequency of FP or 15 SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns TscL2doV SCK2 Edge SP36 TdoV2scH, SDO2 Data Output Setup to 30 — — ns TdoV2scL First SCK2 Edge SP40 TdiV2scH, Setup Time of SDI2 Data Input 30 — — ns TdiV2scL to SCK2 Edge SP41 TscH2diL, Hold Time of SDI2 Data Input 30 — — ns TscL2diL to SCK2 Edge SP50 TssL2scH, SS2  to SCK2  or SCK2  120 — — ns TssL2scL Input SP51 TssH2doZ SS2  to SDO2 Output 10 — 50 ns (Note 4) High-Impedance SP52 TscH2ssH SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4) TscL2ssH SP60 TssL2doV SDO2 Data Output Valid after — — 50 ns SS2 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI2 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 431

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-19: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SS2 SP50 SP52 SCK2 (CKP = 0) SP70 SP73 SP72 SCK2 (CKP = 1) SP36 SP35 SP72 SP73 SDO2 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDI2 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 432  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-38: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK2 Input — — Lesser MHz (Note 3) Frequency of FP or 11 SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns TscL2doV SCK2 Edge SP36 TdoV2scH, SDO2 Data Output Setup to 30 — — ns TdoV2scL First SCK2 Edge SP40 TdiV2scH, Setup Time of SDI2 Data Input 30 — — ns TdiV2scL to SCK2 Edge SP41 TscH2diL, Hold Time of SDI2 Data Input 30 — — ns TscL2diL to SCK2 Edge SP50 TssL2scH, SS2  to SCK2  or SCK2  120 — — ns TssL2scL Input SP51 TssH2doZ SS2  to SDO2 Output 10 — 50 ns (Note 4) High-Impedance SP52 TscH2ssH SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4) TscL2ssH SP60 TssL2doV SDO2 Data Output Valid after — — 50 ns SS2 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI2 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 433

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-20: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SS2 SP50 SP52 SCK2 (CKP = 0) SP70 SP73 SP72 SCK2 (CKP = 1) SP72 SP73 SP35SP36 SDO2 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDI2 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 434  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-39: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK2 Input Frequency — — 15 MHz (Note 3) SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns TscL2doV SCK2 Edge SP36 TdoV2scH, SDO2 Data Output Setup to 30 — — ns TdoV2scL First SCK2 Edge SP40 TdiV2scH, Setup Time of SDI2 Data Input 30 — — ns TdiV2scL to SCK2 Edge SP41 TscH2diL, Hold Time of SDI2 Data Input 30 — — ns TscL2diL to SCK2 Edge SP50 TssL2scH, SS2  to SCK2  or SCK2  120 — — ns TssL2scL Input SP51 TssH2doZ SS2  to SDO2 Output 10 — 50 ns (Note 4) High-Impedance SP52 TscH2ssH SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4) TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI2 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 435

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-21: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SS2 SP50 SP52 SCK2 (CKP = 0) SP70 SP73 SP72 SCK2 (CKP = 1) SP72 SP73 SP35SP36 SDO2 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDI2 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 436  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-40: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK2 Input Frequency — — 11 MHz (Note 3) SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO31 (Note 4) SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO2 Data Output Valid after — 6 20 ns TscL2doV SCK2 Edge SP36 TdoV2scH, SDO2 Data Output Setup to 30 — — ns TdoV2scL First SCK2 Edge SP40 TdiV2scH, Setup Time of SDI2 Data Input 30 — — ns TdiV2scL to SCK2 Edge SP41 TscH2diL, Hold Time of SDI2 Data Input 30 — — ns TscL2diL to SCK2 Edge SP50 TssL2scH, SS2  to SCK2  or SCK2  120 — — ns TssL2scL Input SP51 TssH2doZ SS2  to SDO2 Output 10 — 50 ns (Note 4) High-Impedance SP52 TscH2ssH SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4) TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI2 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 437

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-41: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table30-42 — — 0,1 0,1 0,1 10 MHz — Table30-43 — 1 0,1 1 10 MHz — Table30-44 — 0 0,1 1 15 MHz — — Table30-45 1 0 0 11 MHz — — Table30-46 1 1 0 15 MHz — — Table30-47 0 1 0 11 MHz — — Table30-48 0 0 0 FIGURE 30-22: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS SCK1 (CKP = 0) SP10 SP21 SP20 SCK1 (CKP = 1) SP35 SP20 SP21 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 438  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-23: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS SP36 SCK1 (CKP = 0) SP10 SP21 SP20 SCK1 (CKP = 1) SP35 SP20 SP21 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure30-1 for load conditions. TABLE 30-42: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 FscP Maximum SCK1 Frequency — — 15 MHz (Note 3) SP20 TscF SCK1 Output Fall Time — — — ns See Parameter DO32 (Note 4) SP21 TscR SCK1 Output Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO1 Data Output Valid after — 6 20 ns TscL2doV SCK1 Edge SP36 TdiV2scH, SDO1 Data Output Setup to 30 — — ns TdiV2scL First SCK1 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI1 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 439

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-24: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCK1 (CKP = 0) SP10 SP21 SP20 SCK1 (CKP = 1) SP35 SP20 SP21 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-43: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 FscP Maximum SCK1 Frequency — — 10 MHz (Note 3) SP20 TscF SCK1 Output Fall Time — — — ns See Parameter DO32 (Note 4) SP21 TscR SCK1 Output Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO1 Data Output Valid after — 6 20 ns TscL2doV SCK1 Edge SP36 TdoV2sc, SDO1 Data Output Setup to 30 — — ns TdoV2scL First SCK1 Edge SP40 TdiV2scH, Setup Time of SDI1 Data 30 — — ns TdiV2scL Input to SCK1 Edge SP41 TscH2diL, Hold Time of SDI1 Data Input 30 — — ns TscL2diL to SCK1 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI1 pins. DS70000657H-page 440  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-25: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCK1 (CKP = 0) SP10 SP21 SP20 SCK1 (CKP = 1) SP35SP36 SP20 SP21 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDI1 MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-44: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 FscP Maximum SCK1 Frequency — — 10 MHz -40ºC to +125ºC (Note 3) SP20 TscF SCK1 Output Fall Time — — — ns See Parameter DO32 (Note 4) SP21 TscR SCK1 Output Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO1 Data Output Valid after — 6 20 ns TscL2doV SCK1 Edge SP36 TdoV2scH, SDO1 Data Output Setup to 30 — — ns TdoV2scL First SCK1 Edge SP40 TdiV2scH, Setup Time of SDI1 Data 30 — — ns TdiV2scL Input to SCK1 Edge SP41 TscH2diL, Hold Time of SDI1 Data Input 30 — — ns TscL2diL to SCK1 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI1 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 441

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-26: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SS1 SP50 SP52 SCK1 (CKP = 0) SP70 SP73 SP72 SCK1 (CKP = 1) SP36 SP35 SP72 SP73 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 442  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-45: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK1 Input — — Lesser of MHz (Note 3) Frequency FP or 15 SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO1 Data Output Valid after — 6 20 ns TscL2doV SCK1 Edge SP36 TdoV2scH, SDO1 Data Output Setup to 30 — — ns TdoV2scL First SCK1 Edge SP40 TdiV2scH, Setup Time of SDI1 Data Input 30 — — ns TdiV2scL to SCK1 Edge SP41 TscH2diL, Hold Time of SDI1 Data Input 30 — — ns TscL2diL to SCK1 Edge SP50 TssL2scH, SS1  to SCK1  or SCK1  120 — — ns TssL2scL Input SP51 TssH2doZ SS1  to SDO1 Output 10 — 50 ns (Note 4) High-Impedance SP52 TscH2ssH SS1 after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4) TscL2ssH SP60 TssL2doV SDO1 Data Output Valid after — — 50 ns SS1 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI1 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 443

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-27: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SS1 SP50 SP52 SCK1 (CKP = 0) SP70 SP73 SP72 SCK1 (CKP = 1) SP36 SP35 SP72 SP73 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 444  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-46: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK1 Input — — Lesser of MHz (Note 3) Frequency FP or 11 SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO1 Data Output Valid after — 6 20 ns TscL2doV SCK1 Edge SP36 TdoV2scH, SDO1 Data Output Setup to 30 — — ns TdoV2scL First SCK1 Edge SP40 TdiV2scH, Setup Time of SDI1 Data Input 30 — — ns TdiV2scL to SCK1 Edge SP41 TscH2diL, Hold Time of SDI1 Data Input 30 — — ns TscL2diL to SCK1 Edge SP50 TssL2scH, SS1  to SCK1  or SCK1  120 — — ns TssL2scL Input SP51 TssH2doZ SS1  to SDO1 Output 10 — 50 ns (Note 4) High-Impedance SP52 TscH2ssH, SS1 after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4) TscL2ssH SP60 TssL2doV SDO1 Data Output Valid after — — 50 ns SS1 Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI1 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 445

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-28: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SS1 SP50 SP52 SCK1 (CKP = 0) SP70 SP73 SP72 SCK1 (CKP = 1) SP72 SP73 SP35SP36 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 446  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-47: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK1 Input Frequency — — 15 MHz (Note 3) SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO1 Data Output Valid after — 6 20 ns TscL2doV SCK1 Edge SP36 TdoV2scH, SDO1 Data Output Setup to 30 — — ns TdoV2scL First SCK1 Edge SP40 TdiV2scH, Setup Time of SDI1 Data Input 30 — — ns TdiV2scL to SCK1 Edge SP41 TscH2diL, Hold Time of SDI1 Data Input 30 — — ns TscL2diL to SCK1 Edge SP50 TssL2scH, SS1  to SCK1  or SCK1  120 — — ns TssL2scL Input SP51 TssH2doZ SS1  to SDO1 Output 10 — 50 ns (Note 4) High-Impedance SP52 TscH2ssH, SS1 after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4) TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI1 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 447

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-29: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SS1 SP50 SP52 SCK1 (CKP = 0) SP70 SP73 SP72 SCK1 (CKP = 1) SP72 SP73 SP35 SP36 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. DS70000657H-page 448  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-48: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 FscP Maximum SCK1 Input Frequency — — 11 MHz (Note 3) SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32 (Note 4) SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31 (Note 4) SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32 (Note 4) SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31 (Note 4) SP35 TscH2doV, SDO1 Data Output Valid after — 6 20 ns TscL2doV SCK1 Edge SP36 TdoV2scH, SDO1 Data Output Setup to 30 — — ns TdoV2scL First SCK1 Edge SP40 TdiV2scH, Setup Time of SDI1 Data Input 30 — — ns TdiV2scL to SCK1 Edge SP41 TscH2diL, Hold Time of SDI1 Data Input 30 — — ns TscL2diL to SCK1 Edge SP50 TssL2scH, SS1  to SCK1  or SCK1  120 — — ns TssL2scL Input SP51 TssH2doZ SS1  to SDO1 Output 10 — 50 ns (Note 4) High-Impedance SP52 TscH2ssH, SS1 after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4) TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPI1 pins.  2011-2013 Microchip Technology Inc. DS70000657H-page 449

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-30: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure30-1 for load conditions. FIGURE 30-31: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM26 IM11 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure30-1 for load conditions. DS70000657H-page 450  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X T ABLE 30-49: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic(4) Min.(1) Max. Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2) — s 400 kHz mode TCY/2 (BRG + 2) — s 1 MHz mode(2) TCY/2 (BRG + 2) — s IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2) — s 400 kHz mode TCY/2 (BRG + 2) — s 1 MHz mode(2) TCY/2 (BRG + 2) — s IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) 0.2 — s IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — s Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 2) — s Repeated Start 1 MHz mode(2) TCY/2 (BRG + 2) — s condition IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — s After this period, the Hold Time 400 kHz mode TCY/2 (BRG +2) — s first clock pulse is 1 MHz mode(2) TCY/2 (BRG + 2) — s generated IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s Setup Time 400 kHz mode TCY/2 (BRG + 2) — s 1 MHz mode(2) TCY/2 (BRG + 2) — s IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s Hold Time 400 kHz mode TCY/2 (BRG + 2) — s 1 MHz mode(2) TCY/2 (BRG + 2) — s IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns From Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — 400 ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be 400 kHz mode 1.3 — s free before a new 1 MHz mode(2) 0.5 — s transmission can start IM50 CB Bus Capacitive Loading — 400 pF IM51 TPGD Pulse Gobbler Delay 65 390 ns (Note 3) Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to “Inter-Integrated Circuit (I2C™)” (DS70330) in the “dsPIC33/PIC24 Family Reference Manual”. Please see the Microchip web site for the latest family reference manual sections. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns. 4: These parameters are characterized, but not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 451

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-32: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 30-33: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS25 IS26 IS31 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70000657H-page 452  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-50: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol Characteristic(3) Min. Max. Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s 1 MHz mode(1) 0.5 — s IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4 — s Hold Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.25 s IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission 1 MHz mode(1) 0.5 — s can start IS50 CB Bus Capacitive Loading — 400 pF IS51 TPGD Pulse Gobbler Delay 65 390 ns (Note 2) Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 2: Typical value for this parameter is 130 ns. 3: These parameters are characterized, but not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 453

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-34: ECANx MODULE I/O TIMING CHARACTERISTICS CxTx Pin Old Value New Value (output) CA10, CA11 CxRx Pin (input) CA20 TABLE 30-51: ECANx MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions No. CA10 TIOF Port Output Fall Time — — — ns See Parameter DO32 CA11 TIOR Port Output Rise Time — — — ns See Parameter DO31 CA20 TCWF Pulse Width to Trigger 120 — — ns CAN Wake-up Filter Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 30-35: UARTx MODULE I/O TIMING CHARACTERISTICS UA20 UxRX MSb In Bits 1-6 LSb In UXTX UA10 TABLE 30-52: UARTx MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions No. UA10 TUABAUD UARTx Baud Time 66.67 — — ns UA11 FBAUD UARTx Baud Frequency — — 15 Mbps UA20 TCWF Start Bit Pulse Width to Trigger 500 — — ns UARTx Wake-up Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70000657H-page 454  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic Min. Typ.(2) Max. Units Conditions No. Comparator AC Characteristics CM10 TRESP Response Time(3) — 19 — ns V+ input step of 100 mV, V- input held at VDD/2 CM11 TMC2OV Comparator Mode — — 10 µs Change to Output Valid Comparator DC Characteristics CM30 VOFFSET Comparator Offset — ±10 40 mV Voltage CM31 VHYST Input Hysteresis — 30 — mV Voltage(3) CM32 TRISE/ Comparator Output Rise/ — 20 — ns 1 pF load capacitance TFALL Fall Time(3) on input CM33 VGAIN Open-Loop Voltage — 90 — db Gain(3) CM34 VICM Input Common-Mode AVSS — AVDD V Voltage Op Amp AC Characteristics CM20 SR Slew Rate(3) — 9 — V/µs 10 pF load CM21a PM Phase Margin — 55 — Degree G = 100V/V; 10 pF load (Configuration A)(3,4) CM21b PM Phase Margin — 40 — Degree G = 100V/V; 10 pF load (Configuration B)(3,5) CM22 GM Gain Margin(3) — 20 — db G = 100V/V; 10 pF load CM23a GBW Gain Bandwidth — 10 — MHz 10 pF load (Configuration A)(3,4) CM23b GBW Gain Bandwidth — 6 — MHz 10 pF load (Configuration B)(3,5) Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: Parameter is characterized but not tested in manufacturing. 4: See Figure25-6 for configuration information. 5: See Figure25-7 for configuration information. 6: Resistances can vary by ±10% between op amps.  2011-2013 Microchip Technology Inc. DS70000657H-page 455

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic Min. Typ.(2) Max. Units Conditions No. Op Amp DC Characteristics CM40 VCMR Common-Mode Input AVSS — AVDD V Voltage Range CM41 CMRR Common-Mode — 40 — db VCM = AVDD/2 Rejection Ratio(3) CM42 VOFFSET Op Amp Offset — ±5 — mV Voltage(3) CM43 VGAIN Open-Loop Voltage — 90 — db Gain(3) CM44 IOS Input Offset Current — — — — See pad leakage currents in Table30-11 CM45 IB Input Bias Current — — — — See pad leakage currents in Table30-11 CM46 IOUT Output Current — — 420 µA With minimum value of RFEEDBACK (CM48) CM48 RFEEDBACK Feedback Resistance 8 — — k Value CM49a VOADC Output Voltage AVSS + 0.077 — AVDD – 0.077 V IOUT = 420 µA Measured at OAx Using AVSS + 0.037 — AVDD – 0.037 V IOUT = 200 µA ADC(3,4) AVSS + 0.018 — AVDD – 0.018 V IOUT = 100 µA CM49b VOUT Output Voltage AVSS + 0.210 — AVDD – 0.210 V IOUT = 420 µA Measured at OAxOUT AVSS + 0.100 — AVDD – 0.100 V IOUT = 200 µA Pin(3,4,5) AVSS + 0.050 — AVDD – 0.050 V IOUT = 100 µA CM51 RINT1(6) Internal Resistance 1 198 264 317  Min = -40ºC (Configuration A Typ = +25ºC and B)(3,4,5) Max = +125ºC Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: Parameter is characterized but not tested in manufacturing. 4: See Figure25-6 for configuration information. 5: See Figure25-7 for configuration information. 6: Resistances can vary by ±10% between op amps. DS70000657H-page 456  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-54: OP AMP/COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Standard Operating Conditions (see Note 2): 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions VR310 TSET Settling Time — 1 10 s (Note 1) Note 1: Settling time is measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’. 2: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. TABLE 30-55: OP AMP/COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions (see Note 1): 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristics Min. Typ. Max. Units Conditions No. VRD310 CVRES Resolution CVRSRC/24 — CVRSRC/32 LSb VRD311 CVRAA Absolute Accuracy(2) — ±25 — mV CVRSRC = 3.3V VRD313 CVRSRC Input Reference Voltage 0 — AVDD + 0.3 V VRD314 CVROUT Buffer Output — 1.5k —  Resistance(2) Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. 2: Parameter is characterized but not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 457

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-56: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions:3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. CTMU Current Source CTMUI1 IOUT1 Base Range(1) 0.29 — 0.77 µA CTMUICON<9:8> = 01 CTMUI2 IOUT2 10x Range(1) 3.85 — 7.7 µA CTMUICON<9:8> = 10 CTMUI3 IOUT3 100x Range(1) 38.5 — 77 µA CTMUICON<9:8> = 11 CTMUI4 IOUT4 1000x Range(1) 385 — 770 µA CTMUICON<9:8> = 00 CTMUFV1 VF Temperature Diode Forward — 0.598 — V TA = +25°C, Voltage(1,2) CTMUICON<9:8> = 01 — 0.658 — V TA = +25°C, CTMUICON<9:8> = 10 — 0.721 — V TA = +25°C, CTMUICON<9:8> = 11 CTMUFV2 VFVR Temperature Diode Rate of — -1.92 — mV/ºC CTMUICON<9:8> = 01 Change(1,2,3) — -1.74 — mV/ºC CTMUICON<9:8> = 10 — -1.56 — mV/ºC CTMUICON<9:8> = 11 Note 1: Nominal value at center point of current trim range (CTMUICON<15:10> = 000000). 2: Parameters are characterized but not tested in manufacturing. 3: Measurements taken with the following conditions: • VREF+ = AVDD = 3.3V • ADC configured for 10-bit mode • ADC module configured for conversion speed of 500 ksps • All PMDx bits are cleared (PMDx = 0) • Executing a while(1) statement • Device operating from the FRC with no PLL DS70000657H-page 458  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-57: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of: — Lesser of: V VDD – 0.3 VDD + 0.3 or 3.0 or 3.6 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.5 — AVDD V VREFH = VREF+ VREFL = VREF- (Note 1) AD05a 3.0 — 3.6 V VREFH = AVDD VREFL = AVSS = 0 AD06 VREFL Reference Voltage Low AVSS — AVDD – 2.5 V (Note 1) AD06a 0 — 0 V VREFH = AVDD VREFL = AVSS = 0 AD07 VREF Absolute Reference 2.5 — 3.6 V VREF = VREFH - VREFL Voltage AD08 IREF Current Drain — — 10 A ADC off — — 600 A ADC on AD09 IAD Operating Current(2) — 5 — mA ADC operating in 10-bit mode (Note 1) — 2 — mA ADC operating in 12-bit mode (Note 1) Analog Input AD12 VINH Input Voltage Range VINL — VREFH V This voltage reflects Sample-and- VINH Hold Channels 0, 1, 2 and 3 (CH0-CH3), positive input AD13 VINL Input Voltage Range VREFL — AVSS + 1V V This voltage reflects Sample-and- VINL Hold Channels 0, 1, 2 and 3 (CH0-CH3), negative input AD17 RIN Recommended — — 200  Impedance to achieve maximum Impedance of Analog performance of ADC Voltage Source Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. 2: Parameter is characterized but not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 459

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-58: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. ADC Accuracy (12-Bit Mode) AD20a Nr Resolution 12 Data Bits bits AD21a INL Integral Nonlinearity -2.5 — 2.5 LSb -40°C TA +85°C (Note 2) -5.5 — 5.5 LSb +85°CTA +125°C (Note 2) AD22a DNL Differential Nonlinearity -1 — 1 LSb -40°C TA +85°C (Note 2) -1 — 1 LSb +85°CTA +125°C (Note 2) AD23a GERR Gain Error(3) -10 — 10 LSb -40°C TA +85°C (Note 2) -10 — 10 LSb +85°CTA +125°C (Note 2) AD24a EOFF Offset Error -5 — 5 LSb -40°C TA +85°C (Note 2) -5 — 5 LSb +85°CTA +125°C (Note 2) AD25a — Monotonicity — — — — Guaranteed Dynamic Performance (12-Bit Mode) AD30a THD Total Harmonic Distortion(3) — 75 — dB AD31a SINAD Signal to Noise and — 68 — dB Distortion(3) AD32a SFDR Spurious Free Dynamic — 80 — dB Range(3) AD33a FNYQ Input Signal Bandwidth(3) — 250 — kHz AD34a ENOB Effective Number of Bits(3) 11.09 11.3 — bits Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. 2: For all accuracy specifications, VINL = AVSS = VREFL = 0V and AVDD = VREFH = 3.6V. 3: Parameters are characterized but not tested in manufacturing. DS70000657H-page 460  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-59: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. ADC Accuracy (10-Bit Mode) AD20b Nr Resolution 10 Data Bits bits AD21b INL Integral Nonlinearity -0.625 — 0.625 LSb -40°CTA +85°C (Note 2) -1.5 — 1.5 LSb +85°CTA +125°C (Note 2) AD22b DNL Differential Nonlinearity -0.25 — 0.25 LSb -40°CTA +85°C (Note 2) -0.25 — 0.25 LSb +85°CTA +125°C (Note 2) AD23b GERR Gain Error -2.5 — 2.5 LSb -40°CTA +85°C (Note 2) -2.5 — 2.5 LSb +85°CTA +125°C (Note 2) AD24b EOFF Offset Error -1.25 — 1.25 LSb -40°CTA +85°C (Note 2) -1.25 — 1.25 LSb +85°CTA +125°C (Note 2) AD25b — Monotonicity — — — — Guaranteed Dynamic Performance (10-Bit Mode) AD30b THD Total Harmonic Distortion(3) — 64 — dB AD31b SINAD Signal to Noise and — 57 — dB Distortion(3) AD32b SFDR Spurious Free Dynamic — 72 — dB Range(3) AD33b FNYQ Input Signal Bandwidth(3) — 550 — kHz AD34b ENOB Effective Number of Bits(3) — 9.4 — bits Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. 2: For all accuracy specifications, VINL = AVSS = VREFL = 0V and AVDD = VREFH = 3.6V. 3: Parameters are characterized but not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 461

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-36: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000, SSRCG = 0) AD50 ADCLK Instruction Set SAMP Clear SAMP Execution SAMP AD61 AD60 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 9 1 – Software sets AD1CON1. SAMP to start sampling. 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 10. “Analog-to-Digital Converter (ADC)” (DS70621) in the “dsPIC33/PIC24 Family Reference Manual”. 7 – Convert bit 1. 3 – Software clears AD1CON1. SAMP to start conversion. 8 – Convert bit 0. 4 – Sampling ends, conversion sequence starts. 9 – One TAD for end of conversion. DS70000657H-page 462  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-60: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA  +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. Clock Parameters AD50 TAD ADC Clock Period 117.6 — — ns AD51 tRC ADC Internal RC Oscillator Period(2) — 250 — ns Conversion Rate AD55 tCONV Conversion Time — 14 TAD ns AD56 FCNV Throughput Rate — — 500 ksps AD57a TSAMP Sample Time when Sampling any 3 TAD — — — ANx Input AD57b TSAMP Sample Time when Sampling the Op 3 TAD — — — Amp Outputs (Configuration A and Configuration B)(4,5) Timing Parameters AD60 tPCS Conversion Start from Sample 2 TAD — 3 TAD — Auto-convert trigger is Trigger(2,3) not selected AD61 tPSS Sample Start from Setting 2 TAD — 3 TAD — Sample (SAMP) bit(2,3) AD62 tCSS Conversion Completion to — 0.5 TAD — — Sample Start (ASAM = 1)(2,3) AD63 tDPU Time to Stabilize Analog Stage — — 20 s (Note 6) from ADC Off to ADC On(2,3) Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. 2: Parameters are characterized but not tested in manufacturing. 3: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. 4: See Figure25-6 for configuration information. 5: See Figure25-7 for configuration information. 6: The parameter, tDPU, is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (ADON (AD1CON1<15>) = 1). During this time, the ADC result is indeterminate.  2011-2013 Microchip Technology Inc. DS70000657H-page 463

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X FIGURE 30-37: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000, SSRCG = 0) AD50 ADCLK Instruction Set SAMP Clear SAMP Execution SAMP AD61 AD60 TSAMP AD55 AD55 DONE AD1IF 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets AD1CON1. SAMP to start sampling. 5 – Convert bit 9. 2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 8. “Analog-to-Digital Converter (ADC)” (DS70621) in the “dsPIC33/PIC24 Family Reference Manual”. 7 – Convert bit 0. 3 – Software clears AD1CON1. SAMP to start conversion. 8 – One TAD for end of conversion. 4 – Sampling ends, conversion sequence starts. FIGURE 30-38: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010) AD50 ADCLK Instruction Set ADON Execution AD62 SAMP TSAMP AD55 AD55 TSAMP AD55 AD1IF DONE 1 2 3 4 5 6 7 3 4 5 6 8 1 – Software sets AD1CON1. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in 6 – One TAD for end of conversion. “Analog-to-Digital Converter (ADC)” (DS70621) in the “dsPIC33/PIC24 Family Reference Manual”. 7 – Begin conversion of next channel. 3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>. 4 – Convert bit 8. DS70000657H-page 464  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 30-61: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA  +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. Clock Parameters AD50 TAD ADC Clock Period 76 — — ns AD51 tRC ADC Internal RC Oscillator Period(2) — 250 — ns Conversion Rate AD55 tCONV Conversion Time — 12 TAD — — AD56 FCNV Throughput Rate — — 1.1 Msps Using simultaneous sampling AD57a TSAMP Sample Time when Sampling any 2 TAD — — — ANx Input AD57b TSAMP Sample Time when Sampling the 4 TAD — — — Op Amp Outputs (Configuration A and Configuration B)(4,5) Timing Parameters AD60 tPCS Conversion Start from Sample 2 TAD — 3 TAD — Auto-convert trigger is Trigger(2,3) not selected AD61 tPSS Sample Start from Setting 2 TAD — 3 TAD — Sample (SAMP) bit(2,3)) AD62 tCSS Conversion Completion to — 0.5 TAD — — Sample Start (ASAM = 1)(2,3) AD63 tDPU Time to Stabilize Analog Stage — — 20 s (Note 6) from ADC Off to ADC On(2,3) Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 in Table30-13 for the minimum and maximum BOR values. 2: Parameters are characterized but not tested in manufacturing. 3: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. 4: See Figure25-6 for configuration information. 5: See Figure25-7 for configuration information. 6: The parameter, tDPU, is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (ADON (AD1CON1<15>) = 1). During this time, the ADC result is indeterminate. TABLE 30-62: DMA MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Characteristic Min. Typ.(1) Max. Units Conditions No. DM1 DMA Byte/Word Transfer Latency 1 TCY(2) — — ns Note 1: These parameters are characterized, but not tested in manufacturing. 2: Because DMA transfers use the CPU data bus, this time is dependent on other functions on the bus.  2011-2013 Microchip Technology Inc. DS70000657H-page 465

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 466  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 31.0 HIGH-TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/ MC20X electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. The specifications between -40°C to +150°C are identical to those shown in Section30.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, Parameter DC10 in Section30.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10. Absolute maximum ratings for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X high-temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias(2).........................................................................................................-40°C to +150°C Storage temperature.............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(3).....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(3)..................................................... -0.3V to 3.6V Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(3)..................................................... -0.3V to 5.5V Maximum current out of VSS pin.............................................................................................................................60 mA Maximum current into VDD pin(4).............................................................................................................................60 mA Maximum junction temperature.............................................................................................................................+155°C Maximum current sourced/sunk by any 4x I/O pin..................................................................................................10 mA Maximum current sourced/sunk by any 8x I/O pin..................................................................................................15 mA Maximum current sunk by all ports combined.........................................................................................................70 mA Maximum current sourced by all ports combined(4)................................................................................................70 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which the total operating time from +125°C to +150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. 3: Refer to the “Pin Diagrams” section for 5V tolerant pins. 4: Maximum allowable current is a function of device maximum power dissipation (see Table31-2).  2011-2013 Microchip Technology Inc. DS70000657H-page 467

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 31.1 High-Temperature DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range Temperature Range dsPIC33EPXXXGP50X, (in Volts) (in °C) dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X HDC5 3.0 to 3.6V(1) -40°C to +150°C 40 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules, such as the ADC, may have degraded performance. Device functionality is tested but not characterized. TABLE 31-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit High-Temperature Devices Operating Junction Temperature Range TJ -40 — +155 °C Operating Ambient Temperature Range TA -40 — +150 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 31-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C Parameter Symbol Characteristic Min Typ Max Units Conditions No. Operating Voltage HDC10 Supply Voltage VDD — 3.0 3.3 3.6 V -40°C to +150°C DS70000657H-page 468  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C Parameter Typical Max Units Conditions No. Power-Down Current (IPD) HDC60e 1400 2500 A +150°C 3.3V Base Power-Down Current (Notes 1, 3) HDC61c 15 — A +150°C 3.3V Watchdog Timer Current: IWDT (Notes 2, 4) Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off and VREGS (RCON<8>) = 1. 2: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 3: These currents are measured on the device containing the most memory in this family. 4: These parameters are characterized, but are not tested in manufacturing. TABLE 31-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C Parameter Typical Max Units Conditions No. HDC44e 12 30 mA +150°C 3.3V 40 MIPS TABLE 31-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C Parameter Typical Max Units Conditions No. HDC20 9 15 mA +150°C 3.3V 10 MIPS HDC22 16 25 mA +150°C 3.3V 20 MIPS HDC23 30 50 mA +150°C 3.3V 40 MIPS TABLE 31-7: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C Parameter Doze Typical Max Units Conditions No. Ratio HDC72a 24 35 1:2 mA HDC72f(1) 14 — 1:64 mA +150°C 3.3V 40 MIPS HDC72g(1) 12 — 1:128 mA Note 1: Parameters with Doze ratios of 1:64 and 1:128 are characterized, but are not tested in manufacturing.  2011-2013 Microchip Technology Inc. DS70000657H-page 469

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 31-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C Param. Symbol Characteristic Min. Typ. Max. Units Conditions HDO10 VOL Output Low Voltage — — 0.4 V IOL  5mA, VDD = 3.3V 4x Sink Driver Pins(2) (Note 1) Output Low Voltage — — 0.4 V IOL  8 mA, VDD = 3.3V 8x Sink Driver Pins(3) (Note 1) HDO20 VOH Output High Voltage 2.4 — — V IOH-10mA, VDD = 3.3V 4x Source Driver Pins(2) (Note 1) Output High Voltage 2.4 — — V IOH 15mA, VDD = 3.3V 8x Source Driver Pins(3) (Note 1) HDO20A VOH1 Output High Voltage 1.5 — — V IOH-3.9 mA, VDD = 3.3V 4x Source Driver Pins(2) (Note 1) 2.0 — — IOH-3.7 mA, VDD = 3.3V (Note 1) 3.0 — — IOH-2 mA, VDD = 3.3V (Note 1) Output High Voltage 1.5 — — V IOH-7.5 mA, VDD = 3.3V 8x Source Driver Pins(3) (Note 1) 2.0 — — IOH-6.8 mA, VDD = 3.3V (Note 1) 3.0 — — IOH-3 mA, VDD = 3.3V (Note 1) Note 1: Parameters are characterized, but not tested. 2: Includes all I/O pins that are not 8x Sink Driver pins (see below). 3: Includes the following pins: For devices with less than 64 pins: RA3, RA4, RA9, RB<15:7> and RC3 For 64-pin devices: RA4, RA9, RB<15:7>, RC3 and RC15 DS70000657H-page 470  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 31.2 AC Characteristics and Timing Parameters in this section begin with an H, which denotes Parameters High temperature. For example, Parameter OS53 in Section30.2 “AC Characteristics and Timing The information contained in this section defines Parameters” is the Industrial and Extended temperature dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X equivalent of HOS53. and PIC24EPXXXGP/MC20X AC characteristics and timing parameters for high-temperature devices. However, all AC timing specifications in this section are the same as those in Section30.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section. TABLE 31-9: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C Operating voltage VDD range as described in Table31-1. FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 31-10: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C TA +150°C Param Symbol Characteristic Min Typ Max Units Conditions No. HOS53 DCLK CLKO Stability (Jitter)(1) -5 0.5 5 % Measured over 100 ms period Note 1: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula: DCLK Peripheral Clock Jitter = ------------------------------------------------------------------------  FOSC  -------------------------------------------------------------- Peripheral Bit Rate Clock For example: FOSC = 32 MHz, DCLK = 5%, SPIx bit rate clock (i.e., SCKx) is 2 MHz. DCLK 5% 5% SPI SCK Jitter = ------------------------------ = ---------- = -------- = 1.25% 32 MHz 16 4 --------------------  2 MHz  2011-2013 Microchip Technology Inc. DS70000657H-page 471

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 31-11: INTERNAL RC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°CTA+150°C Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1,2) HF21 LPRC -30 — +30 % -40°C  TA +150°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. 2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT). See Section27.5 “Watchdog Timer (WDT)” for more information. DS70000657H-page 472  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE 31-12: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C Param Symbol Characteristic Min Typ Max Units Conditions No. ADC Accuracy (12-Bit Mode)(1) HAD20a Nr Resolution(3) 12 Data Bits bits HAD21a INL Integral Nonlinearity -5.5 — 5.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD22a DNL Differential Nonlinearity -1 — 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD23a GERR Gain Error -10 — 10 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD24a EOFF Offset Error -5 — 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V Dynamic Performance (12-Bit Mode)(2) HAD33a FNYQ Input Signal Bandwidth — — 200 kHz Note 1: These parameters are characterized, but are tested at 20 ksps only. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. TABLE 31-13: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C Param Symbol Characteristic Min Typ Max Units Conditions No. ADC Accuracy (10-Bit Mode)(1) HAD20b Nr Resolution(3) 10 Data Bits bits HAD21b INL Integral Nonlinearity -1.5 — 1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD22b DNL Differential Nonlinearity -0.25 — 0.25 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD23b GERR Gain Error -2.5 — 2.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD24b EOFF Offset Error -1.25 — 1.25 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V Dynamic Performance (10-Bit Mode)(2) HAD33b FNYQ Input Signal Bandwidth — — 400 kHz Note 1: These parameters are characterized, but are tested at 20 ksps only. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.  2011-2013 Microchip Technology Inc. DS70000657H-page 473

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 474  2011-2013 Microchip Technology Inc.

 32.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS 2 0 1 d 1-20 Note: Tonhley . gTrhaep hpse rpforormvidaendc efo clhloawraincgte trhisisti cnso lties taerde h ae rsetiant iasrtiec anlo st utemsmteadr oy rb gausaerda notne ead l.i mIni tseodm neu gmrbaeprh so,f tshaem dpalteas p arensde anrtee dp mroavyid beed ofourt sdidees itghne gsupiedcainfieced oppuerpraotsinegs sP 1 I 3 range (e.g., outside specified power supply range) and therefore, outside the warranted range. C M 3 ic 3 ro E ch FIGURE 32-1: VOH – 4x DRIVER PINS FIGURE 32-3: VOL – 4x DRIVER PINS P ip X Tech --00..005500 VVOOHH ((VV)) VVOOLL(cid:3)(cid:3)((VV)) XX n 00..005500 G olog --00..004455 3.6V 00..004455 3.6V P y --00..004400 5 Inc --00..003355 3.3V 00..004400 3.3V 0X . 00..003355 , --00..003300 3V 3V d IOH(A)IOH(A) ----0000....000022225050 IOH(A)IOH(A) 000000......000000223223050050 sPIC3 -0.015 Absolute Maximum 00..001155 Absolute Maximum 3 E -0.010 0.010 P -0.005 0.005 X X 0.000 0.000 X M 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 C 2 0 X FIGURE 32-2: VOH – 8x DRIVER PINS FIGURE 32-4: VOL – 8x DRIVER PINS / 5 88XX 0 VVOOHH(cid:3)(cid:3)((VV)) VVOOLL(cid:3)(cid:3)((VV)) X --00..008800 00..008800 3.6V A 3.6V N --00..007700 00..007700 D 3.3V --00..006600 3.3V 00..006600 P 3V I C --00..005500 3V 00..005500 2 A)A) A)A) 4 H(H( --00..004400 H(H( 00..004400 E D OO OO P S II -00.003300 II 00..003300 X 70 Absolute Maximum Absolute Maximum X 0 -0.020 00.002200 X 0 0 G 65 -0.010 0.010 P 7 H-p 0.000 0.000 /M a C ge 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 2 4 0 7 X 5

D FIGURE 32-5: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 32-7: TYPICAL IDOZE CURRENT @ VDD = 3.3V d S s 70 P 00 880000..0000 IC 0 6 3 57 770000..0000 4455..0000 3 H E -p 4400..0000 P a g 660000..0000 X e 476 µA)µA) 550000..0000 mA)mA) 33330505....00000000 XXG nt (nt ( nt (nt ( 2255..0000 P urreurre 440000..0000 urreurre 2200..0000 50 CC CC X IIPDPD 330000..0000 OZEOZE 1155..0000 , d 220000..0000 ID 10.00 s P I 5.00 C 100.00 3 0.00 3 0.00 E 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 P -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 X Doze Ratio X Temperature (Celsius) X M C FIGURE 32-6: TYPICAL/MAXIMUM IDD CURRENT @ VDD = 3.3V FIGURE 32-8: TYPICAL IIDLE CURRENT @ VDD = 3.3V 2 0 X 70 / 5 0 2255..0000 X 60 A N 2200..0000 D 50 P  2011-20 I (mA)DD 3400 TMyapx.. Current (mA)Current (mA) 11110505....00000000 IC24EP 13 Mic 20 IIDLEIDLE IIDLE (EC+PLL) XXX ro 5.00 G c h P ip T 10 IIDLE (EC) /M e 0.00 c C hn 0 10 20 30 40 50 60 70 2 olog 0 0 10 20 30 40 50 60 70 80 MIPS 0X y In MIPS c .

 FIGURE 32-9: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 32-11: TYPICAL CTMU TEMPERATURE DIODE 20 FORWARD VOLTAGE 1 d 1-20 77338800 00..885500 sP 1 I 3 M 77337700 00..880000 C3 icro 77336600 00..775500 3E chip Technology Inc. FRC Frequency (kHz)FRC Frequency (kHz) 77777777777333333333331234501234500000000000 Forward Voltage (V)Forward Voltage (V) 0000000000..........566745566750505050500000000000 VVVFFF === 000...765259188 65 µA, V6F.V5R µ =A ,- 1V.5F0V6.6R m5 = Vµ -/A1ºC,. 7V4F VmRV =/º C-1.92 mV/ºC PXXXGP50X, ds P 7290 0.400 I C 7280 0.350 3 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 E P Temperature (Celsius) Temperature (Celsius) X X X FIGURE 32-10: TYPICAL LPRC FREQUENCY @ VDD = 3.3V M C 2 3333 0 X / 5 0 X A z)z) N HH 3322 kk D cy (cy ( P nn ee I uu C qq ee 2 FrFr 4 RC RC 3311 E PP P D LL S X 7 X 0 0 X 0 0 G 6 5 P 7H 30 /M -p -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 a C g e 2 4 Temperature (Celsius) 0 7 X 7

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 478  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX dsPIC33EP64GP XXXXXXXXXXXXXXXXX 502-I/SPe3 YYWWNNN 1310017 28-Lead SOIC (.300”) Example XXXXXXXXXXXXXXXXXXXX dsPIC33EP64GP XXXXXXXXXXXXXXXXXXXX 502-I/SOe3 XXXXXXXXXXXXXXXXXXXX 1310017 YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX dsPIC33EP64 XXXXXXXXXXXX GP502-I/SSe3 YYWWNNN 1310017 28-Lead QFN-S (6x6x0.9 mm) Example XXXXXXXX 33EP64GP XXXXXXXX 502-I/MM YYWWNNN 1310017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2013 Microchip Technology Inc. DS70000657H-page 479

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 33.1 Package Marking Information (Continued) 36-Lead VTLA (TLA) Example XXXXXXXXXX 33EP64GP XXXXXXXXXX 504-I/TLe3 XXXXXXXXXX 1310017 YYWWNNN 44-Lead VTLA (TLA) Example XXXXXXXXXX 33EP64GP XXXXXXXXXX 504-I/TLe3 XXXXXXXXXX 1310017 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX 33EP64GP XXXXXXXXXX 504-I/PTe3 XXXXXXXXXX 1310017 YYWWNNN 44-Lead QFN (8x8x0.9 mm) Example XXXXXXXXXXX 33EP64GP XXXXXXXXXXX 504-I/MLe3 XXXXXXXXXXX 1310017 YYWWNNN DS70000657H-page 480  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 33.1 Package Marking Information (Continued) 48-Lead UQFN (6x6x0.5 mm) Example XXXXXXXXXXX 33EP64GP XXXXXXXXXXX 504-I/MVe3 XXXXXXXXXXX 1310017 YYWWNNN 64-Lead QFN (9x9x0.9 mm) Example XXXXXXXXXXX dsPIC33EP XXXXXXXXXXX 64GP506 XXXXXXXXXXX -I/MRe3 YYWWNNN 1310017 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX dsPIC33EP XXXXXXXXXX 64GP506 XXXXXXXXXX -I/PTe3 YYWWNNN 1310017  2011-2013 Microchip Technology Inc. DS70000657H-page 481

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 33.2 Package Details (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1 DS70000657H-page 482  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS70000657H-page 483

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000657H-page 484  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS70000657H-page 485

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)#$(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)%(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)&’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)%(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1 DS70000657H-page 486  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS70000657H-page 487

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X DS70000657H-page 488  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X  2011-2013 Microchip Technology Inc. DS70000657H-page 489

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)*(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)+(cid:6)(cid:9)(cid:23),,(cid:24)(cid:9)(cid:25)(cid:9)-.-.(cid:27)’/(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)()!(cid:4)(cid:10) 0(cid:12)(cid:18)#(cid:9)(cid:27)’1(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)2(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)+(cid:18)# !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS70000657H-page 490  2011-2013 Microchip Technology Inc.

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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X DS70000657H-page 494  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 11(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)3#(cid:12)(cid:13)(cid:9)((cid:21)(cid:7)(cid:8)(cid:9))(cid:16)(cid:7)(cid:18)4(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)3(cid:24)(cid:9)(cid:25)(cid:9)5(cid:27).5(cid:27).5(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)*(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)3()(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ -(cid:20)(cid:29)@ (cid:5)@ : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)@ (cid:30)(cid:3)@ (cid:30)-@ (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)@ (cid:30)(cid:3)@ (cid:30)-@ !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A(cid:2)!(cid:7)B(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1  2011-2013 Microchip Technology Inc. DS70000657H-page 495

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000657H-page 496  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X  2011-2013 Microchip Technology Inc. DS70000657H-page 497

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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000657H-page 500  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS70000657H-page 501

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X DS70000657H-page 502  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2013 Microchip Technology Inc. DS70000657H-page 503

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000657H-page 504  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 64 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-085B  2011-2013 Microchip Technology Inc. DS70000657H-page 505

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000657H-page 506  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X APPENDIX A: REVISION HISTORY Revision A (April 2011) This is the initial released version of the document. Revision B (July 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in TableA-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Changed all pin diagrams references of VLAP to TLA. Digital Signal Controllers and Microcontrollers” Section4.0 “Memory Updated the All Resets values for CLKDIV and PLLFBD in the System Control Organization” Register Map (see Table4-35). Section5.0 “Flash Program Updated “one word” to “two words” in the first paragraph of Section5.2 “RTSP Memory” Operation”. Section9.0 “Oscillator Updated the PLL Block Diagram (see Figure9-2). Configuration” Updated the Oscillator Mode, Fast RC Oscillator (FRC) with divide-by-N and PLL (FRCPLL), by changing (FRCDIVN + PLL) to (FRCPLL). Changed (FRCDIVN + PLL) to (FRCPLL) for COSC<2:0> = 001 and NOSC<2:0>=001 in the Oscillator Control Register (see Register9-1). Changed the POR value from 0 to 1 for the DOZE<1:0> bits, from 1 to 0 for the FRCDIV<0> bit, and from 0 to 1 for the PLLPOST<0> bit; Updated the default definitions for the DOZE<2:0> and FRCDIV<2:0> bits and updated all bit definitions for the PLLPOST<1:0> bits in the Clock Divisor Register (see Register9-2). Changed the POR value from 0 to 1 for the PLLDIV<5:4> bits and updated the default definitions for all PLLDIV<8:0> bits in the PLL Feedback Division Register (see Register9-2). Section22.0 “Charge Time Updated the bit definitions for the IRNG<1:0> bits in the CTMU Current Control Measurement Unit (CTMU)” Register (see Register22-3). Section25.0 “Op amp/ Updated the voltage reference block diagrams (see Figure25-1 and Figure25-2). Comparator Module”  2011-2013 Microchip Technology Inc. DS70000657H-page 507

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section30.0 “Electrical Removed Voltage on VCAP with respect to Vss and added Note 5 in Absolute Characteristics” Maximum Ratings(1). Removed Parameter DC18 (VCORE) and Note 3 from the DC Temperature and Voltage Specifications (see Table30-4). Updated Note 1 in the DC Characteristics: Operating Current (IDD) (see Table30-6). Updated Note 1 in the DC Characteristics: Idle Current (IIDLE) (see Table30-7). Changed the Typical values for Parameters DC60a-DC60d and updated Note 1 in the DC Characteristics: Power-down Current (IPD) (see Table30-8). Updated Note 1 in the DC Characteristics: Doze Current (IDOZE) (see Table30-9). Updated Note 2 in the Electrical Characteristics: BOR (see Table30-12). Updated Parameters CM20 and CM31, and added Parameters CM44 and CM45 in the AC/DC Characteristics: Op amp/Comparator (see Table30-14). Added the Op amp/Comparator Reference Voltage Settling Time Specifications (see Table30-15). Added Op amp/Comparator Voltage Reference DC Specifications (see Table30-16). Updated Internal FRC Accuracy Parameter F20a (see Table30-21). Updated the Typical value and Units for Parameter CTMUI1, and added Parameters CTMUI4, CTMUFV1, and CTMUFV2 to the CTMU Current Source Specifications (see Table30-55). Section31.0 “Packaging Updated packages by replacing references of VLAP with TLA. Information” “Product Identification Changed VLAP to TLA. System” DS70000657H-page 508  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Revision C (December 2011) All occurrences of TLA were updated to VTLA throughout the document, with the exception of the pin This revision includes typographical and formatting diagrams (updated diagrams were not available at time changes throughout the data sheet text. of publication). In addition, where applicable, new sections were added A new chapter, Section31.0 “DC and AC Device to each peripheral chapter that provide information and Characteristics Graphs”, was added. links to related resources, as well as helpful tips. For All other major changes are referenced by their examples, see Section20.1 “UART Helpful Tips” respective section in TableA-2. and Section3.6 “CPU Resources”. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description “16-bit Microcontrollers The content on the first page of this section was extensively reworked to provide the and Digital Signal reader with the key features and functionality of this device family in an “at-a-glance” Controllers (up to format. 256-Kbyte Flash and 32-Kbyte SRAM) with High- Speed PWM, Op amps, and Advanced Analog” Section1.0 “Device Updated the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and Overview” PIC24EPXXXGP/MC20X Block Diagram (see Figure1-1), which now contains a CPU block and a reference to the CPU diagram. Updated the description and Note references in the Pinout I/O Descriptions for these pins: C1IN2-, C2IN2-, C3IN2-, OA1OUT, OA2OUT, and OA3OUT (see Table1-1). Section2.0 “Guidelines for Updated the Recommended Minimum Connection diagram (see Figure2-1). Getting Started with 16-bit Digital Signal Controllers and Microcontrollers” Section3.0 “CPU” Updated the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/MC20X CPU Block Diagram (see Figure3-1). Updated the Status register definition in the Programmer’s Model (see Figure3-2). Section4.0 “Memory Updated the Data Memory Maps (see Figure4-6 and Figure4-11). Organization” Removed the DCB<1:0> bits from the OC1CON2, OC2CON2, OC3CON2, and OC4CON2 registers in the Output Compare 1 Through Output Compare 4 Register Map (see Table4-10). Added the TRIG1 and TRGCON1 registers to the PWM Generator 1 Register Map (see Table4-13). Added the TRIG2 and TRGCON2 registers to the PWM Generator 2 Register Map (see Table4-14). Added the TRIG3 and TRGCON3 registers to the PWM Generator 3 Register Map (see Table4-15). Updated the second note in Section4.7.1 “Bit-Reversed Addressing Implementation”. Section8.0 “Direct Memory Updated the DMA Controller diagram (see Figure8-1). Access (DMA)” Section14.0 “Input Updated the bit values for the ICx clock source of the ICTSEL<12:10> bits in the Capture” ICxCON1 register (see Register14-1). Section15.0 “Output Updated the bit values for the OCx clock source of the OCTSEL<2:0> bits in the Compare” OCxCON1 register (see Register15-1). Removed the DCB<1:0> bits from the Output Compare x Control Register 2 (see Register15-2).  2011-2013 Microchip Technology Inc. DS70000657H-page 509

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section16.0 “High-Speed Updated the High-Speed PWM Module Register Interconnection Diagram (see PWM Module Figure16-2). (dsPIC33EPXXXMC20X/50X Added the TRGCONx and TRIGx registers (see Register16-12 and Register16-14, and PIC24EPXXXMC20X respectively). Devices Only)” Section21.0 “Enhanced Updated the CANCKS bit value definitions in CiCTRL1: ECAN Control Register 1 CAN (ECAN™) Module (see Register21-1). (dsPIC33EPXXXGP/MC50X Devices Only)” Section22.0 “Charge Time Updated the IRNG<1:0> bit value definitions and added Note 2 in the CTMU Current Measurement Unit (CTMU)” Control Register (see Register22-3). Section25.0 “Op amp/ Updated the Op amp/Comparator I/O Operating Modes Diagram (see Figure25-1). Comparator Module” Updated the User-programmable Blanking Function Block Diagram (see Figure25-3). Updated the Digital Filter Interconnect Block Diagram (see Figure25-4). Added Section25.1 “Op amp Application Considerations”. Added Note 2 to the Comparator Control Register (see Register25-2). Updated the bit definitions in the Comparator Mask Gating Control Register (see Register25-5). Section27.0 “Special Updated the FICD Configuration Register, updated Note 1, and added Note 3 in the Features” Configuration Byte Register Map (see Table27-1). Added Section27.2 “User ID Words”. Section30.0 “Electrical Updated the following Absolute Maximum Ratings: Characteristics” • Maximum current out of VSS pin • Maximum current into VDD pin Added Note 1 to the Operating MIPS vs. Voltage (see Table30-1). Updated all Idle Current (IIDLE) Typical and Maximum DC Characteristics values (see Table30-7). Updated all Doze Current (IDOZE) Typical and Maximum DC Characteristics values (see Table30-9). Added Note 2, removed Parameter CM24, updated the Typical values Parameters CM10, CM20, CM21, CM32, CM41, CM44, and CM45, and updated the Minimum values for CM40 and CM41, and the Maximum value for CM40 in the AC/DC Characteristics: Op amp/Comparator (see Table30-14). Updated Note 2 and the Typical value for Parameter VR310 in the Op amp/ Comparator Reference Voltage Settling Time Specifications (see Table30-15). Added Note 1, removed Parameter VRD312, and added Parameter VRD314 to the Op amp/Comparator Voltage Reference DC Specifications (see Table30-16). Updated the Minimum, Typical, and Maximum values for Internal LPRC Accuracy (see Table30-22). Updated the Minimum, Typical, and Maximum values for Parameter SY37 in the Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements (see Table30-24). The Maximum Data Rate values were updated for the SPI2 Maximum Data/Clock Rate Summary (see Table30-35) DS70000657H-page 510  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section30.0 “Electrical These SPI2 Timing Requirements were updated: Characteristics” • Maximum value for Parameter SP10 and the minimum clock period value for (Continued) SCKx in Note 3 (see Table30-36, Table30-37, and Table30-38) • Maximum value for Parameter SP70 and the minimum clock period value for SCKx in Note 3 (see Table30-40 and Table30-42) • The Maximum Data Rate values were updated for the SPI2 Maximum Data/Clock Rate Summary (see Table30-43) These SPI1 Timing Requirements were updated: • Maximum value for Parameters SP10 and the minimum clock period value for SCKx in Note 3 (see Table30-44, Table30-45, and Table30-46) • Maximum value for Parameters SP70 and the minimum clock period value for SCKx in Note 3 (see Table30-47 through Table30-50) • Minimum value for Parameters SP40 and SP41 see Table30-44 through Table30-50) Updated all Typical values for the CTMU Current Source Specifications (see Table30-55). Updated Note1, the Maximum value for Parameter AD06, the Minimum value for AD07, and the Typical values for AD09 in the ADC Module Specifications (see Table30-56). Added Note 1 to the ADC Module Specifications (12-bit Mode) (see Table30-57). Added Note 1 to the ADC Module Specifications (10-bit Mode) (see Table30-58). Updated the Minimum and Maximum values for Parameter AD21b in the 10-bit Mode ADC Module Specifications (see Table30-58). Updated Note 2 in the ADC Conversion (12-bit Mode) Timing Requirements (see Table30-59). Updated Note 1 in the ADC Conversion (10-bit Mode) Timing Requirements (see Table30-60).  2011-2013 Microchip Technology Inc. DS70000657H-page 511

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Revision D (December 2011) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in TableA-3. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description “16-bit Microcontrollers Removed the Analog Comparators column and updated the Op amps/Comparators and Digital Signal column in Table1 and Table2. Controllers (up to 512-Kbyte Flash and 48-Kbyte SRAM) with High- Speed PWM, Op amps, and Advanced Analog” Section21.0 “Enhanced Updated the CANCKS bit value definitions in CiCTRL1: ECAN Control Register 1 CAN (ECAN™) Module (see Register21-1). (dsPIC33EPXXXGP/MC50X Devices Only)” Section30.0 “Electrical Updated the VBOR specifications and/or its related note in the following electrical Characteristics” characteristics tables: • Table30-1 • Table30-4 • Table30-12 • Table30-14 • Table30-15 • Table30-16 • Table30-56 • Table30-57 • Table30-58 • Table30-59 • Table30-60 DS70000657H-page 512  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Revision E (April 2012) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in TableA-3. TABLE A-4: MAJOR SECTION UPDATES Section Name Update Description “16-bit Microcontrollers The following 512-Kbyte devices were added to the General Purpose Families table and Digital Signal (see Table1): Controllers (up to • PIC24EP512GP202 512-Kbyte Flash and • PIC24EP512GP204 48-Kbyte SRAM) with High- • PIC24EP512GP206 Speed PWM, Op amps, and Advanced Analog” • dsPIC33EP512GP502 • dsPIC33EP512GP504 • dsPIC33EP512GP506 The following 512-Kbyte devices were added to the Motor Control Families table (see Table2): • PIC24EP512MC202 • PIC24EP512MC204 • PIC24EP512MC206 • dsPIC33EP512MC202 • dsPIC33EP512MC204 • dsPIC33EP512MC206 • dsPIC33EP512MC502 • dsPIC33EP512MC504 • dsPIC33EP512MC506 Certain Pin Diagrams were updated to include the new 512-Kbyte devices. Section4.0 “Memory Added a Program Memory Map for the new 512-Kbyte devices (see Figure4-4). Organization” Added a Data Memory Map for the new dsPIC 512-Kbyte devices (see Figure4-11). Added a Data Memory Map for the new PIC24 512-Kbyte devices (see Figure4-16). Section7.0 “Interrupt Updated the VECNUM bits in the INTTREG register (see Register7-7). Controller” Section11.0 “I/O Ports” Added tip 6 to Section11.5 “I/O Helpful Tips”. Section27.0 “Special The following modifications were made to the Configuration Byte Register Map (see Features” Table27-1): • Added the column Device Memory Size (Kbytes) • Removed Notes 1 through 4 • Added addresses for the new 512-Kbyte devices Section30.0 “Electrical Updated the Minimum value for Parameter DC10 (see Table30-4). Characteristics” Added Power-Down Current (Ipd) parameters for the new 512-Kbyte devices (see Table30-8). Updated the Minimum value for Parameter CM34 (see Table30-53). Updated the Minimum and Maximum values and the Conditions for paramteer SY12 (see Table30-22).  2011-2013 Microchip Technology Inc. DS70000657H-page 513

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Revision F (November 2012) Revision G (March 2013) Removed “Preliminary” from data sheet footer. This revision includes the following global changes: • changes “FLTx” pin function to “FLTx” on all occurrences • adds Section31.0 “High-Temperature Electrical Characteristics” for high-temperature (+150°C) data This revision also includes minor typographical and formatting changes throughout the text. Other major changes are referenced by their respective section in TableA-5. TABLE A-5: MAJOR SECTION UPDATES Section Name Update Description Cover Section • Changes internal oscillator specification to 1.0% • Changes I/O sink/source values to 12 mA or 6 mA • Corrects 44-pin VTLA pin diagram (pin 32 now shows as 5V tolerant) Section4.0 “Memory • Deletes references to Configuration Shadow registers Organization” • Corrects the spelling of the JTAGIP and PTGWDTIP bits throughout • Corrects the Reset value of all IOCON registers as C000h • Adds footnote to Table4-42 to indicate the absence of Comparator 3 in 28-pin devices Section6.0 “Resets” • Removes references to cold and warm Resets, and clarifies the initial configuration of the device clock source on all Resets Section7.0 “Interrupt • Corrects the definition of GIE as “Global Interrupt Enable” (not “General”) Controller” Section9.0 “Oscillator • Clarifies the behavior of the CF bit when cleared in software Configuration” • Removes POR behavior footnotes from all control registers • Corrects the tuning range of the TUN<5:0> bits in Register 9-4 to an overall range ±1.5% Section13.0 “Timer2/3 and • Clarifies the presence of the ADC Trigger in 16-bit Timer3 and Timer5, as well as the Timer4/5” 32-bit timers Section15.0 “Output • Corrects the first trigger source for SYNCSEL<4:0> (OCxCON2<4:0>) as OCxRS Compare” match Section16.0 “High-Speed • Clarifies the source of the PWM interrupts in Figure 16-1 PWM Module” • Corrects the Reset states of IOCONx<15:14> in Register 16-13 as ‘11’ Section17.0 “Quadrature • Clarifies the operation of the IMV<1:0> bits (QEICON<9:8>) with updated text and Encoder Interface (QEI) additional notes Module” • Corrects the first prescaler value for QFVDIV<2:0> (QEI1OC<13:11>), now 1:128 Section23.0 “10-Bit/12-Bit • Adds note to Figure23-1 that Op Amp 3 is not available in 28-pin devices Analog-to-Digital Converter • Changes “sample clock” to “sample trigger” in AD1CON1 (Register23-1) (ADC)” • Clarifies footnotes on op amp usage in Registers23-5 and23-6 Section25.0 “Op Amp/ • Adds Note text to indicate that Comparator 3 is unavailable in 28-pin devices Comparator Module” • Splits Figure25-1 into two figures for clearer presentation (Figure25-1 for Op amp/ Comparators 1 through 3, Figure25-2 for Comparator 4). Subsequent figures are renumbered accordingly. • Corrects reference description in xxxxx (now (AVDD+AVSS)/2) • Changes CMSTAT<15> in Register25-1 to “PSIDL” Section27.0 “Special • Corrects the addresses of all Configuration bytes for 512 Kbyte devices Features” DS70000657H-page 514  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TABLE A-5: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section30.0 “Electrical • Throughout: qualifies all footnotes relating to the operation of analog modules below Characteristics” VDDMIN (replaces “will have” with “may have”) • Throughout: changes all references of SPI timing parameter symbol “TscP” to “FscP” • Table30-1: changes VDD range to 3.0V to 3.6V • Table30-4: removes Parameter DC12 (RAM Retention Voltage) • Table30-7: updates Maximum values at 10 and 20 MIPS • Table30-8: adds Maximum IPD values, and removes all IWDT entries • Adds new Table30-9 (Watchdog Timer Delta Current) with consolidated values removed from Table30-8. All subsequent tables are renumbered accordingly. • Table30-10: adds footnote for all parameters for 1:2 Doze ratio • Table30-11: - changes Minimum and Maximum values for D120 and D130 - adds Minimum and Maximum values for D131 - adds Minimum and Maximum values for D150 through D156, and removes Typical values • Table30-12: - reformats table for readability - changes IOL conditions for DO10 • Table30-14: adds footnote to D135 • Table30-17: changes Minimum and Maximum values for OS30 • Table30-19: - splits temperature range and adds new values for F20a - reduces temperature range for F20b to extended temperatures only • Table30-20: - splits temperature range and adds new values for F21a - reduces temperature range for F20b to extended temperatures only • Table30-53: - adds Maximum value to CM30 - adds footnote (“Parameter characterized...”) to multiple parameters • Table30-55: adds Minimum and Maximum values for all CTMUI specifications, and removes Typical values • Table30-57: adds new footnote to AD09 • Table30-58: - removes all specifications for accuracy with external voltage references - removes Typical values for AD23a and AD24a - replaces Minimum and Maximum values for AD21a, AD22a, AD23a and AD24a with new values, split by Industrial and Extended temperatures - removes Maximum value of AD30 - removes Minimum values from AD31a and AD32a - adds or changes Typical values for AD30, AD31a, AD32a and AD33a • Table30-59: - removes all specifications for accuracy with external voltage references - removes Maximum value of AD30 - removes Typical values for AD23b and AD24b - replaces Minimum and Maximum values for AD21b, AD22b, AD23b and AD24b with new values, split by Industrial and Extended temperatures - removes Minimum and Maximum values from AD31b, AD32b, AD33b and AD34b - adds or changes Typical values for AD30, AD31a, AD32a and AD33a • Table30-61: Adds footnote to AD51 Section32.0 “DC and AC • Updates Figure32-6 (Typical IDD @ 3.3V) with individual current vs. processor speed Device Characteristics curves for the different program memory sizes Graphs” Section33.0 “Packaging • Replaces drawing C04-149C (64-pin QFN, 7.15 x 7.15 exposed pad) with C04-154A Information” (64-pin QFN, 5.4 x 5.4 exposed pad)  2011-2013 Microchip Technology Inc. DS70000657H-page 515

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Revision H (August 2013) This revision includes minor typographical and formatting changes throughout the text. Other major changes are referenced by their respective section in TableA-6. TABLE A-6: MAJOR SECTION UPDATES Section Name Update Description Cover Section • Adds Peripheral Pin Select (PPS) to allow Digital Function Remapping and Change Notification Interrupts to Input/Output section • Adds heading information to 64-Pin TQFP Section4.0 “Memory • Corrects Reset values for ANSELE, TRISF, TRISC, ANSELC and TRISA Organization” • Corrects address range from 0x2FFF to 0x7FFF • Corrects DSRPAG and DSWPAG (now 3 hex digits) • Changes Call Stack Frame from <15:1> to PC<15:0> • Word length in Figure4-20 is changed to 50 words for clarity Section5.0 “Flash Program • Corrects descriptions of NVM registers Memory” Section9.0 “Oscillator • Removes resistor from Figure9-1 Configuration” • Adds Fast RC Oscillator with Divide-by-16 (FRCDIV16) row to Table9-1 • Removes incorrect information from ROI bit in Register9-2 Section14.0 “Input Capture” • Changes 31 user-selectable Trigger/Sync interrupts to 19 user-selectable Trigger/ Sync interrupts • Corrects ICTSEL<12:10> bits (now ICTSEL<2:0>) Section17.0 “Quadrature • Corrects QCAPEN bit description Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)” Section19.0 “Inter- • Adds note to clarify that 100kbit/sec operation of I2C is not possible at high processor Integrated Circuit™ (I2C™)” speeds Section22.0 “Charge Time • Clarifies Figure22-1 to accurately reflect peripheral behavior Measurement Unit (CTMU)” Section23.0 “10-Bit/12-Bit • Correct Figure23-1 (changes CH123x to CH123Sx) Analog-to-Digital Converter (ADC)” Section24.0 “Peripheral • Adds footnote to Register24-1 (In order to operate with CVRSS=1, at least one of the Trigger Generator (PTG) comparator modules must be enabled. Module” Section25.0 “Op Amp/ • Adds note to Figure25-3 (In order to operate with CVRSS=1, at least one of the Comparator Module” comparator modules must be enabled) • Adds footnote to Register25-2 (COE is not available when OPMODE (CMxCON<10>) = 1) Section27.0 “Special • Corrects the bit description for FNOSC<2:0> Features” Section30.0 “Electrical • Corrects 512K part power-down currents based on test data Characteristics” • Corrects WDT timing limits based on LPRC oscillator tolerance Section31.0 “High- • Adds Table31-5 (DC Characteristics: Idle Current (IIDLE) Temperature Electrical Characteristics” DS70000657H-page 516  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X INDEX A Timer1 External Clock Requirements.......................418 Timer2/Timer4 External Clock Requirements...........419 Absolute Maximum Ratings..............................................401 Timer3/Timer5 External Clock Requirements...........419 AC Characteristics....................................................413, 471 UARTx I/O Requirements.........................................454 10-Bit ADC Conversion Requirements.....................465 ADC 12-Bit ADC Conversion Requirements.....................463 Control Registers......................................................325 ADC Module..............................................................459 Helpful Tips...............................................................324 ADC Module (10-Bit Mode)...............................461, 473 Key Features............................................................321 ADC Module (12-Bit Mode)...............................460, 473 Resources................................................................324 Capacitive Loading Requirements on Arithmetic Logic Unit (ALU)................................................44 Output Pins.......................................................413 Assembler DMA Module Requirements......................................465 MPASM Assembler..................................................398 ECANx I/O Requirements.........................................454 External Clock...........................................................414 B High-Speed PWMx Requirements............................422 Bit-Reversed Addressing..................................................115 I/O Timing Requirements..........................................416 Example....................................................................116 I2Cx Bus Data Requirements (Master Mode)...........451 Implementation.........................................................115 I2Cx Bus Data Requirements (Slave Mode).............453 Sequence Table (16-Entry)......................................116 Input Capture x Requirements..................................420 Block Diagrams Internal FRC Accuracy..............................................415 Data Access from Program Space Internal LPRC Accuracy............................................415 Address Generation.................................117 Internal RC Accuracy................................................472 16-Bit Timer1 Module...............................................203 Load Conditions................................................413, 471 ADC Conversion Clock Period.................................323 OCx/PWMx Mode Requirements..............................421 ADC with Connection Options for ANx Pins Op Amp/Comparator Voltage Reference and Op Amps...................................................322 Settling Time Specifications..............................457 Arbiter Architecture...................................................110 Output Compare x Requirements.............................421 BEMF Voltage Measurement Using ADC...................34 PLL Clock..........................................................415, 471 Boost Converter Implementation................................32 QEI External Clock Requirements............................423 CALL Stack Frame...................................................111 QEI Index Pulse Requirements.................................425 Comparator (Module 4)............................................356 Quadrature Decoder Requirements..........................424 Connections for On-Chip Voltage Regulator............384 Reset, Watchdog Timer, Oscillator Start-up Timer, CPU Core...................................................................36 Power-up Timer Requirements.........................417 CRC Module.............................................................373 SPI1 Master Mode (Full-Duplex, CKE = 0, CKP = x, CRC Shift Engine.....................................................374 SMP = 1) Requirements...................................441 CTMU Module..........................................................316 SPI1 Master Mode (Full-Duplex, CKE = 1, CKP = x, Digital Filter Interconnect..........................................357 SMP = 1) Requirements...................................440 DMA Controller.........................................................141 SPI1 Master Mode (Half-Duplex, Transmit Only) DMA Controller Module............................................139 Requirements...................................................439 dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X SPI1 Maximum Data/Clock Rate Summary..............438 and PIC24EPXXXGP/MC20X............................25 SPI1 Slave Mode (Full-Duplex, CKE = 0, ECAN Module...........................................................288 CKP = 0, SMP = 0) Requirements....................449 EDS Read Address Generation................................105 SPI1 Slave Mode (Full-Duplex, CKE = 0, EDS Write Address Generation................................106 CKP = 1, SMP = 0) Requirements....................447 Example of MCLR Pin Connections...........................30 SPI1 Slave Mode (Full-Duplex, CKE = 1, High-Speed PWMx Architectural Overview..............227 CKP = 0, SMP = 0) Requirements....................443 High-Speed PWMx Register Interconnection...........228 SPI1 Slave Mode (Full-Duplex, CKE = 1, I2Cx Module.............................................................274 CKP = 1, SMP = 0) Requirements....................445 Input Capture x.........................................................213 SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP Interleaved PFC..........................................................34 = 1) Requirements............................................429 Multiphase Synchronous Buck Converter..................33 SPI2 Master Mode (Full-Duplex, CKE = 1, Multiplexing Remappable Output for RPn................180 CKP = x, SMP = 1) Requirements....................428 Op Amp Configuration A...........................................358 SPI2 Master Mode (Half-Duplex, Transmit Only) Op Amp Configuration B...........................................359 Requirements...................................................427 Op Amp/Comparator Voltage Reference Module.....356 SPI2 Maximum Data/Clock Rate Summary..............426 Op Amp/Comparator x (Modules 1, 2, 3)..................355 SPI2 Slave Mode (Full-Duplex, CKE = 0, Oscillator System......................................................153 CKP = 0, SMP = 0) Requirements....................437 Output Compare x Module.......................................219 SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP PLL...........................................................................154 = 0) Requirements............................................435 Programmer’s Model..................................................38 SPI2 Slave Mode (Full-Duplex, CKE = 1, PTG Module.............................................................338 CKP = 0, SMP = 0) Requirements....................431 Quadrature Encoder Interface..................................250 SPI2 Slave Mode (Full-Duplex, CKE = 1, Recommended Minimum Connection........................30 CKP = 1, SMP = 0) Requirements....................433  2011-2013 Microchip Technology Inc. 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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X Remappable Input for U1RX.....................................176 Memory Map for PIC24EP256GP/MC20X/50X Reset System............................................................123 Devices...............................................................60 Shared Port Structure...............................................173 Memory Map for PIC24EP32GP/MC20X/50X Single-Phase Synchronous Buck Converter...............33 Devices...............................................................57 SPIx Module..............................................................266 Memory Map for PIC24EP512GP/MC20X/50X Suggested Oscillator Circuit Placement......................31 Devices...............................................................61 Type B Timer (Timer2 and Timer4)...........................208 Memory Map for PIC24EP64GP/MC20X/50X Type B/Type C Timer Pair (32-Bit Timer)..................209 Devices...............................................................58 Type C Timer (Timer3 and Timer5)..........................208 Near Data Space........................................................51 UARTx Module..........................................................281 Organization, Alignment.............................................51 User-Programmable Blanking Function....................357 SFR Space.................................................................51 Watchdog Timer (WDT)............................................385 Width..........................................................................51 Brown-out Reset (BOR)....................................................384 Data Memory Arbitration and Bus Master Priority...........................110 C Data Space C Compilers Extended X...............................................................109 MPLAB XC Compilers...............................................398 Paged Memory Scheme...........................................105 Charge Time Measurement Unit. See CTMU. DC and AC Characteristics Code Examples Graphs......................................................................475 IC1 Connection to QEI1 Input on DC Characteristics Pin 43 of dsPIC33EPXXXMC206.....................176 BOR..........................................................................411 Port Write/Read........................................................174 CTMU Current Source Requirements.......................458 PWMx Write-Protected Register Doze Current (IDOZE)........................................407, 469 Unlock Sequence..............................................226 High Temperature.....................................................468 PWRSAV Instruction Syntax.....................................163 I/O Pin Input Specifications.......................................408 Code Protection........................................................379, 386 I/O Pin Output Specifications............................411, 470 CodeGuard Security..................................................379, 386 Idle Current (IIDLE)............................................405, 469 Configuration Bits..............................................................379 Op Amp/Comparator Requirements.........................455 Description................................................................381 Op Amp/Comparator Voltage Reference Configuration Byte Register Map......................................380 Requirements...................................................457 Configuring Analog and Digital Port Pins..........................174 Operating Current (IDD)....................................404, 469 CPU Operating MIPS vs. Voltage.............................402, 468 Addressing Modes......................................................35 Power-Down Current (IPD)................................406, 469 Clocking System Options..........................................154 Program Memory......................................................412 Fast RC (FRC) Oscillator..................................154 Temperature and Voltage.........................................468 FRC Oscillator with PLL....................................154 Temperature and Voltage Specifications..................403 FRC Oscillator with Postscaler.........................154 Thermal Operating Conditions..................................468 Low-Power RC (LPRC) Oscillator.....................154 Watchdog Timer Delta Current.................................407 Primary (XT, HS, EC) Oscillator........................154 Demo/Development Boards, Evaluation and Primary Oscillator with PLL...............................154 Starter Kits................................................................400 Control Registers........................................................40 Development Support.......................................................397 Data Space Addressing..............................................35 Third-Party Tools......................................................400 Instruction Set.............................................................35 DMA Controller Resources...................................................................39 Channel to Peripheral Associations..........................140 CTMU Control Registers......................................................141 Control Registers......................................................317 DMAxCNT........................................................141 Resources.................................................................316 DMAxCON........................................................141 Customer Change Notification Service.............................524 DMAxPAD........................................................141 Customer Notification Service...........................................524 DMAxREQ........................................................141 Customer Support.............................................................524 DMAxSTA.........................................................141 DMAxSTB.........................................................141 D Resources................................................................141 Data Address Space...........................................................51 Supported Peripherals..............................................139 Memory Map for dsPIC33EP128MC20X/50X, Doze Mode.......................................................................165 dsPIC33EP128GP50X Devices..........................54 DSP Engine........................................................................44 Memory Map for dsPIC33EP256MC20X/50X, E dsPIC33EP256GP50X Devices..........................55 Memory Map for dsPIC33EP32MC20X/50X, ECAN Message Buffers dsPIC33EP32GP50X Devices............................52 Word 0......................................................................310 Memory Map for dsPIC33EP512MC20X/50X, Word 1......................................................................310 dsPIC33EP512GP50X Devices..........................56 Word 2......................................................................311 Memory Map for dsPIC33EP64MC20X/50X, Word 3......................................................................311 dsPIC33EP64GP50X Devices............................53 Word 4......................................................................312 Memory Map for PIC24EP128GP/MC20X/50X Word 5......................................................................312 Devices...............................................................59 Word 6......................................................................313 Word 7......................................................................313 DS70000657H-page 518  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X ECAN Module Instruction Set Control Registers......................................................290 Overview...................................................................390 Modes of Operation..................................................289 Summary..................................................................387 Overview...................................................................287 Symbols Used in Opcode Descriptions....................388 Resources.................................................................289 Inter-Integrated Circuit (I2C).............................................273 Electrical Characteristics...................................................401 Control Registers......................................................276 AC.....................................................................413, 471 Resources................................................................275 Enhanced CAN (ECAN) Module.......................................287 Internal RC Oscillator Equations Use with WDT...........................................................385 Device Operating Frequency....................................154 Internet Address...............................................................524 FPLLO Calculation......................................................154 Interrupt Controller FVCO Calculation.......................................................154 Control and Status Registers....................................131 Errata..................................................................................23 INTCON1..........................................................131 INTCON2..........................................................131 F INTCON3..........................................................131 Filter Capacitor (CEFC) Specifications...............................403 INTCON4..........................................................131 Flash Program Memory....................................................119 INTTREG..........................................................131 Control Registers......................................................120 Interrupt Vector Details.............................................129 Programming Operations..........................................120 Interrupt Vector Table (IVT)......................................127 Resources.................................................................120 Reset Sequence.......................................................127 RTSP Operation........................................................120 Resources................................................................131 Table Instructions......................................................119 J Flexible Configuration.......................................................379 JTAG Boundary Scan Interface........................................379 G JTAG Interface.................................................................386 Guidelines for Getting Started.............................................29 M Application Examples..................................................32 Basic Connection Requirements.................................29 Memory Maps CPU Logic Filter Capacitor Connection (VCAP)..........30 Extended Data Space...............................................109 Decoupling Capacitors................................................29 Memory Organization.........................................................45 External Oscillator Pins...............................................31 Resources..................................................................62 ICSP Pins....................................................................31 Microchip Internet Web Site..............................................524 Master Clear (MCLR) Pin............................................30 Modulo Addressing...........................................................114 Oscillator Value Conditions on Start-up......................32 Applicability...............................................................115 Unused I/Os................................................................32 Operation Example...................................................114 Start and End Address.............................................114 H W Address Register Selection..................................114 High-Speed PWM.............................................................225 MPLAB Assembler, Linker, Librarian................................398 Control Registers......................................................230 MPLAB ICD 3 In-Circuit Debugger...................................399 Faults........................................................................225 MPLAB PM3 Device Programmer....................................399 Resources.................................................................229 MPLAB REAL ICE In-Circuit Emulator System................399 High-Temperature Electrical Characteristics.....................467 MPLAB X Integrated Development Absolute Maximum Ratings......................................467 Environment Software..............................................397 MPLAB X SIM Software Simulator...................................399 I MPLIB Object Librarian.....................................................398 I/O Ports............................................................................173 MPLINK Object Linker......................................................398 Helpful Tips...............................................................181 O Parallel I/O (PIO).......................................................173 Resources.................................................................182 Op Amp Write/Read Timing....................................................174 Application Considerations.......................................358 In-Circuit Debugger...........................................................386 Configuration A.................................................358 In-Circuit Emulation...........................................................379 Configuration B.................................................359 In-Circuit Serial Programming (ICSP).......................379, 386 Op Amp/Comparator.........................................................355 Input Capture....................................................................213 Control Registers......................................................360 Control Registers......................................................215 Resources................................................................359 Resources.................................................................214 Open-Drain Configuration.................................................174 Input Change Notification (ICN)........................................174 Oscillator Instruction Addressing Modes...........................................112 Control Registers......................................................156 File Register Instructions..........................................112 Resources................................................................155 Fundamental Modes Supported................................112 Output Compare...............................................................219 MAC Instructions.......................................................113 Control Registers......................................................221 MCU Instructions......................................................112 Resources................................................................220 Move and Accumulator Instructions..........................113 Other Instructions......................................................113  2011-2013 Microchip Technology Inc. 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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X P Q Packaging.........................................................................479 QEI Details.......................................................................505 Control Registers......................................................252 Marking.............................................................479, 481 Resources................................................................251 Peripheral Module Disable (PMD).....................................165 Quadrature Encoder Interface (QEI).................................249 Peripheral Pin Select (PPS)..............................................175 R Available Peripherals................................................175 Available Pins...........................................................175 Register Maps Control......................................................................175 ADC1..........................................................................84 Control Registers......................................................183 CPU Core (dsPIC33EPXXXMC20X/50X, Input Mapping...........................................................176 dsPIC33EPXXXGP50X Devices).......................63 Output Selection for Remappable Pins.....................180 CPU Core (PIC24EPXXXGP/MC20X Devices)..........65 Pin Selection for Selectable Input Sources...............178 CRC............................................................................88 Selectable Input Sources..........................................177 CTMU.........................................................................97 Peripheral Trigger Generator (PTG) Module.....................337 DMAC.........................................................................98 PICkit 3 In-Circuit Debugger/Programmer........................399 ECAN1 (When WIN (C1CTRL1) = 0 or 1) Pinout I/O Descriptions (table)............................................26 for dsPIC33EPXXXMC/GP50X Devices.............85 Power-Saving Features.....................................................163 ECAN1 (When WIN (C1CTRL1) = 0) for Clock Frequency.......................................................163 dsPIC33EPXXXMC/GP50X Devices..................85 Clock Switching.........................................................163 ECAN1 (WIN (C1CTRL1) = 1) for Instruction-Based Modes..........................................163 dsPIC33EPXXXMC/GP50X Devices..................86 Idle....................................................................164 I2C1 and I2C2............................................................82 Interrupts Coincident with Power Input Capture 1 through Input Capture 4....................76 Save Instructions......................................164 Interrupt Controller Sleep.................................................................164 (dsPIC33EPXXXGP50X Devices)......................69 Resources.................................................................165 Interrupt Controller Program Address Space.....................................................45 (dsPIC33EPXXXMC20X Devices)......................71 Construction..............................................................117 Interrupt Controller Data Access from Program Memory Using (dsPIC33EPXXXMC50X Devices)......................73 Table Instructions..............................................118 Interrupt Controller Memory Map (dsPIC33EP128GP50X, (PIC24EPXXXGP20X Devices)..........................66 dsPIC33EP128MC20X/50X, Interrupt Controller PIC24EP128GP/MC20X Devices)......................47 (PIC24EPXXXMC20X Devices).........................67 Memory Map (dsPIC33EP256GP50X, JTAG Interface...........................................................97 dsPIC33EP256MC20X/50X, NVM............................................................................93 PIC24EP256GP/MC20X Devices)......................48 Op Amp/Comparator...................................................97 Memory Map (dsPIC33EP32GP50X, Output Compare 1 through Output Compare 4..........77 dsPIC33EP32MC20X/50X, Peripheral Pin Select Input PIC24EP32GP/MC20X Devices)........................45 (dsPIC33EPXXXGP50X Devices)......................91 Memory Map (dsPIC33EP512GP50X, Peripheral Pin Select Input dsPIC33EP512MC20X/50X, (dsPIC33EPXXXMC20X Devices)......................92 PIC24EP512GP/MC20X Devices)......................49 Peripheral Pin Select Input Memory Map (dsPIC33EP64GP50X, (dsPIC33EPXXXMC50X Devices)......................91 dsPIC33EP64MC20X/50X, Peripheral Pin Select Input PIC24EP64GP/MC20X Devices)........................46 (PIC24EPXXXGP20X Devices)..........................90 Table Read High Instructions Peripheral Pin Select Input TBLRDH............................................................118 (PIC24EPXXXMC20X Devices).........................90 Table Read Low Instructions (TBLRDL)...................118 Peripheral Pin Select Output Program Memory (dsPIC33EPXXXGP/MC202/502, Organization................................................................50 PIC24EPXXXGP/MC202 Devices).....................88 Reset Vector...............................................................50 Peripheral Pin Select Output Programmable CRC Generator.........................................373 (dsPIC33EPXXXGP/MC203/503, Control Registers......................................................375 PIC24EPXXXGP/MC203 Devices).....................88 Overview...................................................................374 Peripheral Pin Select Output Resources.................................................................374 (dsPIC33EPXXXGP/MC204/504, Programmer’s Model...........................................................37 PIC24EPXXXGP/MC204 Devices).....................89 Register Descriptions..................................................37 Peripheral Pin Select Output PTG (dsPIC33EPXXXGP/MC206/506, Control Registers......................................................340 PIC24EPXXGP/MC206 Devices).......................89 Introduction...............................................................337 PMD (dsPIC33EPXXXGP50X Devices).....................95 Output Descriptions..................................................353 PMD (dsPIC33EPXXXMC20X Devices).....................96 Resources.................................................................339 PMD (dsPIC33EPXXXMC50X Devices).....................95 Step Commands and Format....................................350 PMD (PIC24EPXXXGP20X Devices).........................94 DS70000657H-page 520  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X PMD (PIC24EPXXXMC20X Devices).........................94 CMxMSKCON (Comparator x Mask PORTA (PIC24EPXXXGP/MC202, Gating Control).................................................368 dsPIC33EPXXXGP/MC202/502 Devices)........104 CMxMSKSRC (Comparator x Mask Source PORTA (PIC24EPXXXGP/MC203, Select Control)..................................................366 dsPIC33EPXXXGP/MC203/503 Devices)........103 CORCON (Core Control)....................................42, 133 PORTA (PIC24EPXXXGP/MC204, CRCCON1 (CRC Control 1).....................................375 dsPIC33EPXXXGP/MC204/504 Devices)........102 CRCCON2 (CRC Control 2).....................................376 PORTA (PIC24EPXXXGP/MC206, CRCXORH (CRC XOR Polynomial High)................377 dsPIC33EPXXXGP/MC206/506 Devices)..........99 CRCXORL (CRC XOR Polynomial Low)..................377 PORTB (PIC24EPXXXGP/MC202, CTMUCON1 (CTMU Control 1)................................317 dsPIC33EPXXXGP/MC202/502 Devices)........104 CTMUCON2 (CTMU Control 2)................................318 PORTB (PIC24EPXXXGP/MC203, CTMUICON (CTMU Current Control).......................319 dsPIC33EPXXXGP/MC203/503 Devices)........103 CVRCON (Comparator Voltage PORTB (PIC24EPXXXGP/MC204, Reference Control)...........................................371 dsPIC33EPXXXGP/MC204/504 Devices)........102 CxBUFPNT1 (ECANx Filter 0-3 PORTB (PIC24EPXXXGP/MC206, Buffer Pointer 1)...............................................300 dsPIC33EPXXXGP/MC206/506 Devices)..........99 CxBUFPNT2 (ECANx Filter 4-7 PORTC (PIC23EPXXXGP/MC203, Buffer Pointer 2)...............................................301 dsPIC33EPXXXGP/MC203/503 Devices)........103 CxBUFPNT3 (ECANx Filter 8-11 PORTC (PIC24EPXXXGP/MC204, Buffer Pointer 3)...............................................301 dsPIC33EPXXXGP/MC204/504 Devices)........102 CxBUFPNT4 (ECANx Filter 12-15 PORTC (PIC24EPXXXGP/MC206, Buffer Pointer 4)...............................................302 dsPIC33EPXXXGP/MC206/506 Devices)..........99 CxCFG1 (ECANx Baud Rate Configuration 1).........298 PORTD (PIC24EPXXXGP/MC206, CxCFG2 (ECANx Baud Rate Configuration 2).........299 dsPIC33EPXXXGP/MC206/506 Devices)........100 CxCTRL1 (ECANx Control 1)...................................290 PORTE (PIC24EPXXXGP/MC206, CxCTRL2 (ECANx Control 2)...................................291 dsPIC33EPXXXGP/MC206/506 Devices)........100 CxEC (ECANx Transmit/Receive Error Count)........298 PORTF (PIC24EPXXXGP/MC206, CxFCTRL (ECANx FIFO Control).............................293 dsPIC33EPXXXGP/MC206/506 Devices)........100 CxFEN1 (ECANx Acceptance Filter Enable 1).........300 PORTG (PIC24EPXXXGP/MC206 and CxFIFO (ECANx FIFO Status).................................294 dsPIC33EPXXXGP/MC206/506 Devices)........101 CxFMSKSEL1 (ECANx Filter 7-0 PTG.............................................................................78 Mask Selection 1).............................................304 PWM (dsPIC33EPXXXMC20X/50X, CxFMSKSEL2 (ECANx Filter 15-8 PIC24EPXXXMC20X Devices)...........................79 Mask Selection 2).............................................305 PWM Generator 1 (dsPIC33EPXXXMC20X/50X, CxINTE (ECANx Interrupt Enable)...........................297 PIC24EPXXXMC20X Devices)...........................79 CxINTF (ECANx Interrupt Flag)................................295 PWM Generator 2 (dsPIC33EPXXXMC20X/50X, CxRXFnEID (ECANx Acceptance Filter n PIC24EPXXXMC20X Devices)...........................80 Extended Identifier)..........................................304 PWM Generator 3 (dsPIC33EPXXXMC20X/50X, CxRXFnSID (ECANx Acceptance Filter n PIC24EPXXXMC20X Devices)...........................80 Standard Identifier)...........................................303 QEI1 (dsPIC33EPXXXMC20X/50X, CxRXFUL1 (ECANx Receive Buffer Full 1)..............307 PIC24EPXXXMC20X Devices)...........................81 CxRXFUL2 (ECANx Receive Buffer Full 2)..............307 Reference Clock.........................................................93 CxRXMnEID (ECANx Acceptance Filter Mask n SPI1 and SPI2............................................................83 Extended Identifier)..........................................306 System Control...........................................................93 CxRXMnSID (ECANx Acceptance Filter Mask n Time1 through Time5..................................................75 Standard Identifier)...........................................306 UART1 and UART2....................................................82 CxRXOVF1 (ECANx Receive Registers Buffer Overflow 1).............................................308 AD1CHS0 (ADC1 Input Channel 0 Select)...............333 CxRXOVF2 (ECANx Receive AD1CHS123 (ADC1 Input Buffer Overflow 2).............................................308 Channel 1, 2, 3 Select).....................................331 CxTRmnCON (ECANx TX/RX AD1CON1 (ADC1 Control 1)....................................325 Buffer mn Control)............................................309 AD1CON2 (ADC1 Control 2)....................................327 CxVEC (ECANx Interrupt Code)...............................292 AD1CON3 (ADC1 Control 3)....................................329 DEVID (Device ID)....................................................383 AD1CON4 (ADC1 Control 4)....................................330 DEVREV (Device Revision)......................................383 AD1CSSH (ADC1 Input Scan Select High)..............335 DMALCA (DMA Last Channel Active Status)...........150 AD1CSSL (ADC1 Input Scan Select Low)................336 DMAPPS (DMA Ping-Pong Status)..........................151 ALTDTRx (PWMx Alternate Dead-Time)..................238 DMAPWC (DMA Peripheral Write AUXCONx (PWMx Auxiliary Control)........................247 Collision Status)................................................148 CHOP (PWMx Chop Clock Generator).....................234 DMARQC (DMA Request Collision Status)..............149 CLKDIV (Clock Divisor).............................................158 DMAxCNT (DMA Channel x Transfer Count)...........146 CM4CON (Comparator 4 Control)............................364 DMAxCON (DMA Channel x Control).......................142 CMSTAT (Op Amp/Comparator Status)...................360 DMAxPAD (DMA Channel x CMxCON (Comparator x Control, x = 1,2,3).............362 Peripheral Address)..........................................146 CMxFLTR (Comparator x Filter Control)...................370 DMAxREQ (DMA Channel x IRQ Select).................143  2011-2013 Microchip Technology Inc. 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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X DMAxSTAH (DMA Channel x PTGCST (PTG Control/Status).................................340 Start Address A, High)......................................144 PTGHOLD (PTG Hold).............................................347 DMAxSTAL (DMA Channel x PTGL0 (PTG Literal 0)..............................................348 Start Address A, Low).......................................144 PTGQPTR (PTG Step Queue Pointer).....................349 DMAxSTBH (DMA Channel x PTGQUEx (PTG Step Queue x)...............................349 Start Address B, High)......................................145 PTGSDLIM (PTG Step Delay Limit).........................346 DMAxSTBL (DMA Channel x PTGT0LIM (PTG Timer0 Limit).................................345 Start Address B, Low).......................................145 PTGT1LIM (PTG Timer1 Limit).................................345 DSADRH (DMA Most Recent RAM PTPER (PWMx Primary Master Time High Address)...................................................147 Base Period).....................................................233 DSADRL (DMA Most Recent RAM PWMCONx (PWMx Control).....................................235 Low Address)....................................................147 QEI1CON (QEI1 Control).........................................252 DTRx (PWMx Dead-Time)........................................238 QEI1GECH (QEI1 Greater Than or Equal FCLCONx (PWMx Fault Current-Limit Control)........243 Compare High Word)........................................262 I2CxCON (I2Cx Control)...........................................276 QEI1GECL (QEI1 Greater Than or Equal I2CxMSK (I2Cx Slave Mode Address Mask)............280 Compare Low Word)........................................262 I2CxSTAT (I2Cx Status)...........................................278 QEI1ICH (QEI1 Initialization/Capture ICxCON1 (Input Capture x Control 1).......................215 High Word).......................................................260 ICxCON2 (Input Capture x Control 2).......................216 QEI1ICL (QEI1 Initialization/Capture INDX1CNTH (Index Counter 1 High Word)..............259 Low Word)........................................................260 INDX1CNTL (Index Counter 1 Low Word)................259 QEI1IOC (QEI1 I/O Control).....................................254 INDX1HLD (Index Counter 1 Hold)...........................260 QEI1LECH (QEI1 Less Than or Equal INT1HLDH (Interval 1 Timer Hold High Word)..........264 Compare High Word)........................................261 INT1HLDL (Interval 1 Timer Hold Low Word)...........264 QEI1LECL (QEI1 Less Than or Equal INT1TMRH (Interval 1 Timer High Word)..................263 Compare Low Word)........................................261 INT1TMRL (Interval 1 Timer Low Word)...................263 QEI1STAT (QEI1 Status)..........................................256 INTCON1 (Interrupt Control 1)..................................134 RCON (Reset Control)..............................................125 INTCON2 (Interrupt Control 2)..................................136 REFOCON (Reference Oscillator Control)...............162 INTCON2 (Interrupt Control 3)..................................137 RPINR0 (Peripheral Pin Select Input 0)....................183 INTCON4 (Interrupt Control 4)..................................137 RPINR1 (Peripheral Pin Select Input 1)....................184 INTTREG (Interrupt Control and Status)...................138 RPINR11 (Peripheral Pin Select Input 11)................187 IOCONx (PWMx I/O Control)....................................240 RPINR12 (Peripheral Pin Select Input 12)................188 LEBCONx (PWMx Leading-Edge RPINR14 (Peripheral Pin Select Input 14)................189 Blanking Control)..............................................245 RPINR15 (Peripheral Pin Select Input 15)................190 LEBDLYx (PWMx Leading-Edge RPINR18 (Peripheral Pin Select Input 18)................191 Blanking Delay).................................................246 RPINR19 (Peripheral Pin Select Input 19)................191 MDC (PWMx Master Duty Cycle)..............................234 RPINR22 (Peripheral Pin Select Input 22)................192 NVMADRH (Nonvolatile Memory Address High)......122 RPINR23 (Peripheral Pin Select Input 23)................193 NVMADRL (Nonvolatile Memory Address Low)........122 RPINR26 (Peripheral Pin Select Input 26)................193 NVMCON (Nonvolatile Memory (NVM) Control).......121 RPINR3 (Peripheral Pin Select Input 3)....................184 NVMKEY (Nonvolatile Memory Key)........................122 RPINR37 (Peripheral Pin Select Input 37)................194 OCxCON1 (Output Compare x Control 1)................221 RPINR38 (Peripheral Pin Select Input 38)................195 OCxCON2 (Output Compare x Control 2)................223 RPINR39 (Peripheral Pin Select Input 39)................196 OSCCON (Oscillator Control)...................................156 RPINR7 (Peripheral Pin Select Input 7)....................185 OSCTUN (FRC Oscillator Tuning)............................161 RPINR8 (Peripheral Pin Select Input 8)....................186 PDCx (PWMx Generator Duty Cycle).......................237 RPOR0 (Peripheral Pin Select Output 0)..................197 PHASEx (PWMx Primary Phase-Shift).....................237 RPOR1 (Peripheral Pin Select Output 1)..................197 PLLFBD (PLL Feedback Divisor)..............................160 RPOR2 (Peripheral Pin Select Output 2)..................198 PMD1 (Peripheral Module Disable Control 1)...........166 RPOR3 (Peripheral Pin Select Output 3)..................198 PMD2 (Peripheral Module Disable Control 2)...........168 RPOR4 (Peripheral Pin Select Output 4)..................199 PMD3 (Peripheral Module Disable Control 3)...........169 RPOR5 (Peripheral Pin Select Output 5)..................199 PMD4 (Peripheral Module Disable Control 4)...........169 RPOR6 (Peripheral Pin Select Output 6)..................200 PMD6 (Peripheral Module Disable Control 6)...........170 RPOR7 (Peripheral Pin Select Output 7)..................200 PMD7 (Peripheral Module Disable Control 7)...........171 RPOR8 (Peripheral Pin Select Output 8)..................201 POS1CNTH (Position Counter 1 High Word)...........258 RPOR9 (Peripheral Pin Select Output 9)..................201 POS1CNTL (Position Counter1 Low Word)..............258 SEVTCMP (PWMx Primary Special POS1HLD (Position Counter 1 Hold)........................258 Event Compare)...............................................233 PTCON (PWMx Time Base Control).........................230 SPIxCON1 (SPIx Control 1)......................................270 PTCON2 (PWMx Primary Master Clock SPIxCON2 (SPIx Control 2)......................................272 Divider Select 2)................................................232 SPIxSTAT (SPIx Status and Control).......................268 PTGADJ (PTG Adjust)..............................................348 SR (CPU STATUS).............................................40, 132 PTGBTE (PTG Broadcast Trigger Enable)...............343 T1CON (Timer1 Control)..........................................205 PTGC0LIM (PTG Counter 0 Limit)............................346 TRGCONx (PWMx Trigger Control).........................239 PTGC1LIM (PTG Counter 1 Limit)............................347 TRIGx (PWMx Primary Trigger Compare Value)......242 PTGCON (PTG Control)...........................................342 TxCON (Timer2 and Timer4 Control).......................210 DS70000657H-page 522  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X TyCON (Timer3 and Timer5 Control)........................211 Input Capture x (ICx)................................................420 UxMODE (UARTx Mode)..........................................283 OCx/PWMx...............................................................421 UxSTA (UARTx Status and Control).........................285 Output Compare x (OCx)..........................................421 VEL1CNT (Velocity Counter 1).................................259 QEA/QEB Input........................................................424 Resets...............................................................................123 QEI Module Index Pulse...........................................425 Brown-out Reset (BOR)............................................123 SPI1 Master Mode (Full-Duplex, CKE = 0, Configuration Mismatch Reset (CM).........................123 CKP = x, SMP = 1)...........................................441 Illegal Condition Reset (IOPUWR)............................123 SPI1 Master Mode (Full-Duplex, CKE = 1, Illegal Opcode...................................................123 CKP = x, SMP = 1)...........................................440 Security.............................................................123 SPI1 Master Mode (Half-Duplex, Transmit Only, Uninitialized W Register....................................123 CKE = 0)...........................................................438 Master Clear (MCLR) Pin Reset...............................123 SPI1 Master Mode (Half-Duplex, Transmit Only, Power-on Reset (POR).............................................123 CKE = 1)...........................................................439 RESET Instruction (SWR).........................................123 SPI1 Slave Mode (Full-Duplex, CKE = 0, Resources.................................................................124 CKP = 0, SMP = 0)...........................................448 Trap Conflict Reset (TRAPR)....................................123 SPI1 Slave Mode (Full-Duplex, CKE = 0, Watchdog Timer Time-out Reset (WDTO)................123 CKP = 1, SMP = 0)...........................................446 Resources Required for Digital PFC.............................32, 34 SPI1 Slave Mode (Full-Duplex, CKE = 1, Revision History................................................................507 CKP = 0, SMP = 0)...........................................442 SPI1 Slave Mode (Full-Duplex, CKE = 1, S CKP = 1, SMP = 0)...........................................444 Serial Peripheral Interface (SPI).......................................265 SPI2 Master Mode (Full-Duplex, CKE = 0, Software Stack Pointer (SSP)...........................................111 CKP = x, SMP = 1)...........................................429 Special Features of the CPU............................................379 SPI2 Master Mode (Full-Duplex, CKE = 1, SPI CKP = x, SMP = 1)...........................................428 Control Registers......................................................268 SPI2 Master Mode (Half-Duplex, Transmit Only, Helpful Tips...............................................................267 CKE = 0)...........................................................426 Resources.................................................................267 SPI2 Master Mode (Half-Duplex, Transmit Only, CKE = 1)...........................................................427 T SPI2 Slave Mode (Full-Duplex, CKE = 0, Temperature and Voltage Specifications CKP = 0, SMP = 0)...........................................436 AC.....................................................................413, 471 SPI2 Slave Mode (Full-Duplex, CKE = 0, Thermal Operating Conditions..........................................402 CKP = 1, SMP = 0)...........................................434 Thermal Packaging Characteristics..................................402 SPI2 Slave Mode (Full-Duplex, CKE = 1, Timer1...............................................................................203 CKP = 0, SMP = 0)...........................................430 Control Register........................................................205 SPI2 Slave Mode (Full-Duplex, CKE = 1, Resources.................................................................204 CKP = 1, SMP = 0)...........................................432 Timer2/3 and Timer4/5......................................................207 Timer1-Timer5 External Clock..................................418 Control Registers......................................................210 TimerQ (QEI Module) External Clock.......................423 Resources.................................................................209 UARTx I/O................................................................454 Timing Diagrams U 10-Bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000, Universal Asynchronous Receiver SSRCG = 0)......................................................464 Transmitter (UART)..................................................281 10-Bit ADC Conversion (CHPS<1:0> = 01, Control Registers......................................................283 SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, Helpful Tips...............................................................282 SSRCG = 0, SAMC<4:0> = 00010)..................464 Resources................................................................282 12-Bit ADC Conversion (ASAM = 0, User ID Words..................................................................384 SSRC<2:0> = 000, SSRCG = 0)......................462 V BOR and Master Clear Reset...................................416 ECANx I/O................................................................454 Voltage Regulator (On-Chip)............................................384 External Clock...........................................................414 W High-Speed PWMx Fault..........................................422 High-Speed PWMx Module.......................................422 Watchdog Timer (WDT)............................................379, 385 I/O Characteristics....................................................416 Programming Considerations...................................385 I2Cx Bus Data (Master Mode)..................................450 WWW Address.................................................................524 I2Cx Bus Data (Slave Mode)....................................452 WWW, On-Line Support.....................................................23 I2Cx Bus Start/Stop Bits (Master Mode)...................450 I2Cx Bus Start/Stop Bits (Slave Mode).....................452  2011-2013 Microchip Technology Inc. DS70000657H-page 523

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 524  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011-2013 Microchip Technology Inc. DS70000657H-page 525

DSPIC33EPXXXGP50X, DSPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 526  2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 EP 64 MC5 04 T I / PT - XXX Examples: dsPIC33EP64MC504-I/PT: Microchip Trademark dsPIC33, Enhanced Performance, 64-Kbyte Program Memory, Architecture Motor Control, 44-Pin, Flash Memory Family Industrial Temperature, TQFP package. Program Memory Size (Kbyte) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller 24 = 16-bit Microcontroller Flash Memory Family: EP = Enhanced Performance Product Group: GP = General Purpose family MC = Motor Control family Pin Count: 02 = 28-pin 03 = 36-pin 04 = 44-pin 06 = 64-pin Temperature Range: I = -40C to+85C (Industrial) E = -40C to+125C (Extended) Package: ML = Plastic Quad, No Lead Package - (44-pin) 8x8 mm body (QFN) MM = Plastic Quad, No Lead Package - (28-pin) 6x6 mm body (QFN-S) MR = Plastic Quad, No Lead Package - (64-pin) 9x9 mm body (QFN) MV = Thin Quad, No Lead Package - (48-pin) 6x6 mm body (UQFN) PT = Plastic Thin Quad Flatpack - (44-pin) 10x10 mm body (TQFP) PT = Plastic Thin Quad Flatpack - (64-pin) 10x10 mm body (TQFP) SO = Plastic Small Outline, Wide - (28-pin) 7.50 mm body (SOIC) SP = Skinny Plastic Dual In-Line - (28-pin) 300 mil body (SPDIP) SS = Plastic Shrink Small Outline - (28-pin) 5.30 mm body (SSOP) TL = Very Thin Leadless Array - (36-pin) 5x5 mm body (VTLA) TL = Very Thin Leadless Array - (44-pin) 6x6 mm body (VTLA)  2011-2013 Microchip Technology Inc. DS70000657H-page 527

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X NOTES: DS70000657H-page 528  2011-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620773949 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2011-2013 Microchip Technology Inc. DS70000657H-page 529

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