dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog Operating Conditions Timers/Output Compare/Input Capture • 3.0V to 3.6V, -40ºC to +125ºC, DC to 60 MIPS • 27 General Purpose Timers: • 3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS - Nine 16-bit and up to four 32-bit Timers/Counters - 16 OC modules configurable as Timers/Counters Core: 16-Bit dsPIC33E/PIC24E CPU - Two 32-bit Quadrature Encoder Interface (QEI) • Code-Efficient (C and Assembly) architecture modules configurable as Timers/Counters • Two 40-Bit Wide Accumulators • 16 IC modules • Single-Cycle (MAC/MPY) with Dual Data Fetch • Peripheral Pin Select (PPS) to allow Function Remap • Single-Cycle Mixed-Sign MUL Plus Hardware Divide • Real-Time Clock and Calendar (RTCC) module • 32-Bit Multiply Support Communication Interfaces Clock Management • USB 2.0 OTG-Compliant Full-Speed Interface • 2% Internal Oscillator • Four UART modules (15 Mbps) • Programmable PLLs and Oscillator Clock Sources - Supports LIN/J2602 protocols and IrDA® • Fail-Safe Clock Monitor (FSCM) • Four 4-Wire SPI modules (15 Mbps) • Independent Watchdog Timer • Two ECAN™ modules (1 Mbaud) CAN 2.0B Support • Fast Wake-up and Start-up • Two I2C modules (up to 1 Mbaud) with SMBus Support • Data Converter Interface (DCI) module with Support for Power Management I2S and Audio Codecs • Low-Power Management modes (Sleep, Idle, Doze) • PPS to allow Function Remap • Integrated Power-on Reset and Brown-out Reset • Parallel Master Port (PMP) • 1.0 mA/MHz Dynamic Current (typical) • Programmable Cyclic Redundancy Check (CRC) • 60 µA IPD Current (typical) Direct Memory Access (DMA) High-Speed PWM • 15-Channel DMA with User-Selectable • Up to Seven PWM Pairs with Independent Timing Priority Arbitration • Dead Time for Rising and Falling Edges • UART, USB, SPI, ADC, ECAN™, IC, OC, Timers, • 8.32 ns PWM Resolution DCI/I2S, PMP • PWM Support for: - DC/DC, AC/DC, Inverters, PFC, Lighting Input/Output - BLDC, PMSM, ACIM, SRM • Sink/Source 10 mA on All Pins • Programmable Fault Inputs • 5V Tolerant Pins • Flexible Trigger Configurations for ADC Conversions • Selectable Open-Drain, Pull-ups and Pull-Downs • Up to 5 mA Overvoltage Clamp Current Advanced Analog Features • External Interrupts on All I/O pins • Two Independent ADC modules: - One ADC configurable as 10-bit, 1.1 Msps with four Qualification and Class B Support S&H or 12-bit, 500 ksps with one S&H • AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) Planned - One 10-bit ADC, 1.1 Msps with four S&H • AEC-Q100 REVG (Grade 0 -40ºC to +150ºC) Planned - Eight S&H using both ADC 10-bit modules • Class B Safety Library, IEC 60730 - 24 analog channels (64-pin devices) up to 32 analog channels (100/121/144-pin devices) Debugger Development Support • Flexible and Independent ADC Trigger Sources • In-Circuit and In-Application Programming • Comparators: • Five Program and Three Complex Data Breakpoints - Up to three Analog Comparator modules • IEEE 1149.2 Compatible (JTAG) Boundary Scan - Programmable references with 32 voltage points • Trace and Run-Time Watch  2009-2012 Microchip Technology Inc. DS70616G-page 1

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table1. Their pinout diagrams appear on the following pages. TABLE 1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 CONTROLLER FAMILIES Remappable Peripherals Device Pins Packages Program Flash Memory (1)(Kbyte) (2)RAM (Kbyte) (3,4)16-Bit Timer Input Capture Output Compare (with PWM) Motor Control PWM(5)(Channels) QEI ®UART with IrDA SPI ECAN™ (6)External Interrupts DMA Controller (Channels) DCI Analog Comparators/(7)Inputs Per Comparator RTCC 2IC™ CRC Generator (8)10-Bit/12-Bit ADC USB Parallel Master Port I/O Pins QFN, 2 ADC, dsPIC33EP256MU806 64 280 28 9 16 16 8 2 4 4 2 5 15 1 3/4 1 2 1 1 Y 51 TQFP 24 ch 100 TQFP 2 ADC, dsPIC33EP256MU810 280 28 9 16 16 12 2 4 4 2 5 15 1 3/4 1 2 1 1 Y 83 121 TFBGA 32 ch TQFP, 2 ADC, dsPIC33EP256MU814 144 280 28 9 16 16 14 2 4 4 2 5 15 1 3/4 1 2 1 1 Y 122 LQFP 32 ch QFN, 2 ADC, dsPIC33EP512GP806 64 536 52 9 16 16 — — 4 4 2 5 15 1 3/4 1 2 1 — Y 53 TQFP 24 ch QFN, 2 ADC, dsPIC33EP512MC806 64 536 52 9 16 16 8 2 4 4 2 5 15 1 3/4 1 2 1 — Y 53 TQFP 24 ch 100 TQFP 2 ADC, dsPIC33EP512MU810 536 52 9 16 16 12 2 4 4 2 5 15 1 3/4 1 2 1 1 Y 83 121 TFBGA 32 ch TQFP, 2 ADC, dsPIC33EP512MU814 144 536 52 9 16 16 14 2 4 4 2 5 15 1 3/4 1 2 1 1 Y 122 LQFP 32 ch 100 TQFP 2 ADC, PIC24EP256GU810 280 28 9 16 16 0 0 4 4 2 5 15 1 3/4 1 2 1 1 Y 83 121 TFBGA 32 ch TQFP, 2 ADC, PIC24EP256GU814 144 280 28 9 16 16 0 0 4 4 2 5 15 1 3/4 1 2 1 1 Y 122 LQFP 32 ch QFN, 2 ADC, PIC24EP512GP806 64 586 52 9 16 16 — — 4 4 2 5 15 1 3/4 1 2 1 — Y 53 TQFP 24 ch 100 TQFP 2 ADC, PIC24EP512GU810 536 52 9 16 16 0 0 4 4 2 5 15 1 3/4 1 2 1 1 Y 83 121 TFBGA 32 ch TQFP,L 2 ADC, PIC24EP512GU814 144 536 52 9 16 16 0 0 4 4 2 5 15 1 3/4 1 2 1 1 Y 122 QFP 32 ch Note 1: Flash size is inclusive of 24 Kbytes of auxiliary Flash. Auxiliary Flash supports simultaneous code execution and self-erase/programming. Refer to Section 5. “Flash Programming” (DS70609) in the “dsPIC33E/PIC24E Family Reference Manual”. 2: RAM size is inclusive of 4Kbytes of DMA RAM (DPSRAM) for all devices. 3: Up to eight of these timers can be combined into four 32-bit timers. 4: Eight out of nine timers are remappable. 5: PWM Faults and Sync signals are remappable. 6: Four out of five interrupts are remappable. 7: Comparator output is remappable. 8: The ADC2 module supports 10-bit mode only. DS70616G-page 2  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams 64-Pin QFN = Pins are up to 5V tolerant 3 1 RP84/RE4RPI83/RERP82/RE2RPI81/RERP80/RE0 1/RD7 N28/PWM3L/PMD4/N27/PWM2H/PMD3/N26/PWM2L/PMD2/N25/PWM1H/PMD1/N24/PWM1L/PMD0//2RP97/RF1CMPST1/RP96/RF0CMPST DD CAP3IN1+/V3/RP7CMPST3IN2-/RP70/RD6MRD/RP69/RD5MWR/RP68/RD4MBE/RP67/RD3PH/RP66/RD2/RP65/RD1CPCON AAAAAVVVVCCPPPDV 4321098765432109 6666655555555554 AN29/PWM3H/PMD5/RP85/RE5 1 48 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN30/PWM4L/PMD6/RPI86/RE6 2 47 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN31/PWM4H/PMD7/RP87/RE7 3 46 INT0/DMH/RP64/RD0 C1IN3-/SCK2/PMA5/RP118/RG6 4 45 PMCS1/RPI75/RD11 C1IN1-/SDI2/PMA4/RPI119/RG7 5 44 ASCL1/PMCS2/RPI74/RD10 C2IN3-/SDO2/PMA3/RP120/RG8 6 43 ASDA1/DPLN/RPI73/RD9 MCLR 7 42 RTCC/DMLN/RPI72/RD8 C2IN1-/PMA2/RPI121/RG9 8 41 VSS dsPIC33EP256MU806 VSS 9 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/RPI60/RC12 AN5/C1IN1+/VBUSON/VBUSST/RPI37/RB5 11 38 VDD AN4/C1IN2-/USBOEN/RPI36/RB4 12 37 D+/RG2 AN3/C2IN1+/VPIO/RPI35/RB3 13 36 D-/RG3 AN2/C2IN2-/VMIO/RPI34/RB2 14 35 VUSB3V3 PGEC3/AN1/VREF-/RPI33/RB1 15 34 VBUS PGED3/AN0/VREF+/RPI32/RB0 16 33 USBID/RP99/RF3 7 89 01 23 45 67 89 01 2 1 11 22 22 22 22 22 33 3 67 D S8901 S D234545 BB D SBB11 S D1111FF 38/R39/RAVAV40/R41/R2/RB3/RBVV4/RB5/RB6/RB7/RB00/R01/R PGEC1/AN6/RPIPGED1/AN7/RCV/RPI AN8/PMA6/RPIAN9/PMA7//RPI/PMA13/RPI4N10/CVREFTDO/AN11/PMA12/RPI4 TCK/AN12/PMA11/RPI4TDI/AN13/PMA10/RPI4AN14/PMA1/RPI4AN15/PMA0/RPI4SDA2/PMA9/RP1SCL2/PMA8/RP1 A S/ M T Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information.  2009-2012 Microchip Technology Inc. DS70616G-page 3

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams 64-Pin QFN = Pins are up to 5V tolerant 4/RE483/RE32/RE281/RE10/RE0 P8PIP8PIP8 RRRRR N28/PWM3L/PMD4/N27/PWM2H/PMD3/N26/PWM2L/PMD2/N25/PWM1H/PMD1/N24/PWM1L/PMD0/P97/RF1P96/RF0 DD CAP3IN1+/RP71/RD73IN2-/RP70/RD6MRD/RP69/RD5MWR/RP68/RD4MBE/RP67/RD3P66/RD2P65/RD1 AAAAARRVVCCPPPRR 4321098765432109 6666655555555554 AN29/PWM3H/PMD5/RP85/RE5 1 48 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN30/PWM4L/PMD6/RPI86/RE6 2 47 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN31/PWM4H/PMD7/RP87/RE7 3 46 INT0/RP64/RD0 C1IN3-/SCK2/PMA5/RP118/RG6 4 45 PMCS1/RPI75/RD11 C1IN1-/SDI2/PMA4/RPI119/RG7 5 44 ASCL1/PMCS2/RPI74/RD10 C2IN3-/SDO2/PMA3/RP120/RG8 6 43 ASDA1/RPI73/RD9 MCLR 7 42 RTCC/RPI72/RD8 C2IN1-/PMA2/RPI121/RG9 8 41 VSS dsPIC33EP512MC806 VSS 9 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/RPI60/RC12 AN5/C1IN1+/RPI37/RB5 11 38 VDD AN4/C1IN2-/RPI36/RB4 12 37 SCLI/RG2 AN3/C2IN1+/RPI35/RB3 13 36 SDA1/RG3 AN2/C2IN2-/RPI34/RB2 14 35 RP102/RF6 PGEC3/AN1/VREF-/RPI33/RB1 15 34 RP98/RF2 PGED3/AN0/VREF+/RPI32/RB0 16 33 RP99/RF3 7 89 01 23 45 67 89 01 2 1 11 22 22 22 22 22 33 3 67 D S8901 S D234545 BB D SBB11 S D1111FF 38/R39/RAVAV40/R41/R2/RB3/RBVV4/RB5/RB6/RB7/RB00/R01/R PGEC1/AN6/RPIPGED1/AN7/RPI AN8/PMA6/RPIAN9/PMA7//RPI/PMA13/RPI4N10/CVREFTDO/AN11/PMA12/RPI4 TCK/AN12/PMA11/RPI4TDI/AN13/PMA10/RPI4AN14/PMA1/RPI4AN15/PMA0/RPI4SDA2/PMA9/RP1SCL2/PMA8/RP1 A S/ M T Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. DS70616G-page 4  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams 64-Pin QFN = Pins are up to 5V tolerant RE4RE3RE2RE1RE0 N28/PMD4/RP84/N27/PMD3/RPI83/N26/PMD2/RP82/N25/PMD1/RPI81/N24/PMD0/RP80/P97/RF1P96/RF0 DD CAP3IN1+/RP71/RD73IN2-/RP70/RD6MRD/RP69/RD5MWR/RP68/RD4MBE/RP67/RD3P66/RD2P65/RD1 AAAAARRVVCCPPPRR 4321098765432109 6666655555555554 AN29/PMD5/RP85/RE5 1 48 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN30/PMD6/RPI86/RE6 2 47 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN31/PMD7/RP87/RE7 3 46 INT0/RP64/RD0 C1IN3-/SCK2/PMA5/RP118/RG6 4 45 PMCS1/RPI75/RD11 C1IN1-/SDI2/PMA4/RPI119/RG7 5 44 ASCL1/PMCS2/RPI74/RD10 C2IN3-/SDO2/PMA3/RP120/RG8 6 43 ASDA1/RPI73/RD9 MCLR 7 42 RTCC/RPI72/RD8 C2IN1-/PMA2/RPI121/RG9 8 41 VSS dsPIC33EP512GP806 VSS 9 40 OSC2/CLKO/RC15 PIC24EP512GP806 VDD 10 39 OSC1/RPI60/RC12 AN5/C1IN1+/RPI37/RB5 11 38 VDD AN4/C1IN2-/RPI36/RB4 12 37 SCLI/RG2 AN3/C2IN1+/RPI35/RB3 13 36 SDA1/RG3 AN2/C2IN2-/RPI34/RB2 14 35 RP102/RF6 PGEC3/AN1/VREF-/RPI33/RB1 15 34 RP98/RF2 PGED3/AN0/VREF+/RPI32/RB0 16 33 RP99/RF3 7 89 01 23 45 67 89 01 2 1 11 22 22 22 22 22 33 3 67 D S8901 S D234545 BB D SBB11 S D1111FF 38/R39/RAVAV40/R41/R2/RB3/RBVV4/RB5/RB6/RB7/RB00/R01/R PGEC1/AN6/RPIPGED1/AN7/RPI AN8/PMA6/RPIAN9/PMA7//RPI/PMA13/RPI4N10/CVREFTDO/AN11/PMA12/RPI4 TCK/AN12/PMA11/RPI4TDI/AN13/PMA10/RPI4AN14/PMA1/RPI4AN15/PMA0/RPI4SDA2/PMA9/RP1SCL2/PMA8/RP1 A S/ M T Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information.  2009-2012 Microchip Technology Inc. DS70616G-page 5

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant N28/PWM3L/PMD4/RP84/RE4N27/PWM2H/PMD3/RPI83/RE3N26/PWM2L/PMD2/RP82/RE2N25/PWM1H/PMD1/RPI81/RE1N24/PWM1L/PMD0/RP80/RE02/RP97/RF1CMPST1/RP96/RF0CMPST DD CAP3IN1+/V3/RP71/RD7CMPST3IN2-/RP70/RD6MRD/RP69/RD5MWR/RP68/RD4MBE/RP67/RD3PH/RP66/RD2/RP65/RD1CPCON AAAAAVVVVCCPPPDV 4321098765432109 6666655555555554 AN29/PWM3H/PMD5/RP85/RE5 1 48 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN30/PWM4L/PMD6/RPI86/RE6 2 47 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN31/PWM4H/PMD7/RP87/RE7 3 46 INT0/DMH/RP64/RD0 C1IN3-/SCK2/PMA5/RP118/RG6 4 45 PMCS1/RPI75/RD11 C1IN1-/SDI2/PMA4/RPI119/RG7 5 44 ASCL1/PMCS2/RPI74/RD10 C2IN3-/SDO2/PMA3/RP120/RG8 6 43 ASDA1/DPLN/RPI73/RD9 MCLR 7 42 RTCC/DMLN/RPI72/RD8 C2IN1-/PMA2/RPI121/RG9 8 dsPIC33EP256MU806 41 VSS VSS 9 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/RPI60/RC12 AN5/C1IN1+/VBUSON/VBUSST/RPI37/RB5 11 38 VDD AN4/C1IN2-/USBOEN/RPI36/RB4 12 37 D+/RG2 AN3/C2IN1+/VPIO/RPI35/RB3 13 36 D-/RG3 AN2/C2IN2-/VMIO/RPI34/RB2 14 35 VUSB3V3 PGEC3/AN1/VREF-/RPI33/RB1 15 34 VBUS PGED3/AN0/VREF+/RPI32/RB0 16 33 USBID/RP99/RF3 7890123456789012 1112222222222333 67D S8901S D234545 38/RB39/RBAVDAVS40/RB41/RB2/RB13/RB1VSVD4/RB15/RB16/RB17/RB100/RF01/RF PGEC1/AN6/RPIPGED1/AN7/RCV/RPI AN8/PMA6/RPIAN9/PMA7//RPIN10/CV/PMA13/RPI4REFTDO/AN11/PMA12/RPI4 TCK/AN12/PMA11/RPI4TDI/AN13/PMA10/RPI4AN14/PMA1/RPI4AN15/PMA0/RPI4SDA2/PMA9/RP1SCL2/PMA8/RP1 A S/ M T Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. DS70616G-page 6  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant N28/PMD4/RP84/RE4N27/PMD3/RPI83/RE3N26/PMD2/RP82/RE2N25/PMD1/RPI81/RE1N24/PMD0/RP80/RE0P97/RF1P96/RF0DD CAP3IN1+/RP71/RD73IN2-/RP70/RD6MRD/RP69/RD5MWR/RP68/RD4MBE/RP67/RD3P66/RD2P65/RD1 AAAAARRVVCCPPPRR 4321098765432109 6666655555555554 AN29/PMD5/RP85/RE5 1 48 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN30/PMD6/RPI86/RE6 2 47 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN31/PMD7/RP87/RE7 3 46 INT0/RP64/RD0 C1IN3-/SCK2/PMA5/RP118/RG6 4 45 PMCS1/RPI75/RD11 C1IN1-/SDI2/PMA4/RPI119/RG7 5 44 ASCL1/PMCS2/RPI74/RD10 C2IN3-/SDO2/PMA3/RP120/RG8 6 43 ASDA1/RPI73/RD9 MCLR 7 42 RTCC/RPI72/RD8 C2IN1-/PMA2/RPI121/RG9 8 dsPIC33EP512GP806 41 VSS VSS 9 40 OSC2/CLKO/RC15 PIC24EP512GP806 VDD 10 39 OSC1/RPI60/RC12 AN5/C1IN1+/RPI37/RB5 11 38 VDD AN4/C1IN2-/RPI36/RB4 12 37 SCL1/RG2 AN3/C2IN1+/RPI35/RB3 13 36 SDA1/RG3 AN2/C2IN2-/RPI34/RB2 14 35 RP102/RF6 PGEC3/AN1/VREF-/RPI33/RB1 15 34 RP98/RF2 PGED3/AN0/VREF+/RPI32/RB0 16 33 RP99/RF3 7890123456789012 1112222222222333 67D S8901S D234545 38/RB39/RBAVDAVS40/RB41/RB2/RB13/RB1VSVD4/RB15/RB16/RB17/RB100/RF01/RF PGEC1/AN6/RPIPGED1/AN7/RPI AN8/PMA6/RPIAN9/PMA7//RPIN10/CV/PMA13/RPI4REFTDO/AN11/PMA12/RPI4 TCK/AN12/PMA11/RPI4TDI/AN13/PMA10/RPI4AN14/PMA1/RPI4AN15/PMA0/RPI4SDA2/PMA9/RP1SCL2/PMA8/RP1 A S/ M T Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information.  2009-2012 Microchip Technology Inc. DS70616G-page 7

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant P84/RE4PI83/RE3P82/RE2PI81/RE1P80/RE0 RRRRR N28/PWM3L/PMD4/N27/PWM2H/PMD3/N26/PWM2L/PMD2/N25/PWM1H/PMD1/N24/PWM1L/PMD0/P97/RF1P96/RF0DD CAP3IN1+/RP71/RD73IN2-/RP70/RD6MRD/RP69/RD5MWR/RP68/RD4MBE/RP67/RD3P66/RD2P65/RD1 AAAAARRVVCCPPPRR 4321098765432109 6666655555555554 AN29/PWM3H/PMD5/RP85/RE5 1 48 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN30/PWM4L/PMD6/RPI86/RE6 2 47 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN31/PWM4H/PMD7/RP87/RE7 3 46 INT0/RP64/RD0 C1IN3-/SCK2/PMA5/RP118/RG6 4 45 PMCS1/RPI75/RD11 C1IN1-/SDI2/PMA4/RPI119/RG7 5 44 ASCL1/PMCS2/RPI74/RD10 C2IN3-/SDO2/PMA3/RP120/RG8 6 43 ASDA1/RPI73/RD9 MCLR 7 42 RTCC/RPI72/RD8 C2IN1-/PMA2/RPI121/RG9 8 dsPIC33EP512MC806 41 VSS VSS 9 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/RPI60/RC12 AN5/C1IN1+/RPI37/RB5 11 38 VDD AN4/C1IN2-/RPI36/RB4 12 37 SCL1/RG2 AN3/C2IN1+/RPI35/RB3 13 36 SDA1/RG3 AN2/C2IN2-/RPI34/RB2 14 35 RP102/RF6 PGEC3/AN1/VREF-/RPI33/RB1 15 34 RP98/RF2 PGED3/AN0/VREF+/RPI32/RB0 16 33 RP99/RF3 7890123456789012 1112222222222333 67D S8901S D234545 38/RB39/RBAVDAVS40/RB41/RB2/RB13/RB1VSVD4/RB15/RB16/RB17/RB100/RF01/RF PGEC1/AN6/RPIPGED1/AN7/RPI AN8/PMA6/RPIAN9/PMA7//RPIN10/CV/PMA13/RPI4REFTDO/AN11/PMA12/RPI4 TCK/AN12/PMA11/RPI4TDI/AN13/PMA10/RPI4AN14/PMA1/RPI4AN15/PMA0/RPI4SDA2/PMA9/RP1SCL2/PMA8/RP1 A S/ M T Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. DS70616G-page 8  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant N28/PWM3L/PMD4/RP84/RE4N27/PWM2H/PMD3/RPI83/RE3N26/PWM2L/PMD2/RP82/RE2P125/RG13PI124/RG12P126/RG14N25/PWM1H/PMD1/RPI81/RE1N24/PWM1L/PMD0/RP80/RE0N23/RPI23/RA7N22/RPI22/RA6P112/RG0P113/RG12/RP97/RF1CMPST1/RP96/RF0CMPSTDDCAP3IN1+/V3/RP71/RD7CMPST3IN2-/RP70/RD6MRD/RP69/RD5MWR/RP68/RD4PI77/RD13PI76/RD12MBE/RP67/RD3PH/RP66/RD2/RP65/RD1CPCON AAARRRAAAARRVVVVCCPPRRPDV 0987654321098765432109876 0999999999988888888887777 1 RP127/RG15 1 75 VSS VDD 2 74 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN29/PWM3H/PMD5/RP85/RE5 3 73 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN30/PWM4L/PMD6/RPI86/RE6 4 72 INT0/DMH/RP64/RD0 AN31/PWM4H/PMD7/RP87/RE7 5 71 PMCS1/RPI75/RD11 AN16/PWM5L/RPI49/RC1 6 70 ASCL1/PMCS2/RPI74/RD10 AN17/PWM5H/RPI50/RC2 7 69 ASDA1/DPLN/RPI73/RD9 AN18/PWM6L/RPI51/RC3 8 68 RTCC/DMLN/RPI72/RD8 AN19/PWM6H/RPI52/RC4 9 67 RPI31/RA15 C1IN3-/SCK2/PMA5/RP118/RG6 10 66 RPI30/RA14 C1IN1-/SDI2/PMA4/RPI119/RG7 11 65 VSS C2IN3-/SDO2/PMA3/RP120/RG8 12 64 OSC2/CLKO/RC15 MCLR 13 dsPIC33EP512MU810 63 OSC1/RPI60/RC12 C2IN1-/PMA2/RPI121/RG9 14 dsPIC33EP256MU810 62 VDD VSS 15 61 TDO/RPI21/RA5 VDD 16 60 TDI/RPI20/RA4 TMS/RPI16/RA0 17 59 ASDA2/RPI19/RA3 AN20/RPI88/RE8 18 58 ASCL2/RPI18/RA2 AN21/RPI89/RE9 19 57 D+/RG2 AN5/C1IN1+/VBUSON//VBUSST/RPI37/RB5 20 56 D-/RG3 AN4/C1IN2-/USBOEN/RPI36/RB4 21 55 VUSB3V3 AN3/C2IN1+/VPIO/RPI35/RB3 22 54 VBUS AN2/C2IN2-/VMIO/RPI34/RB2 23 53 RP104/RF8 PGEC3/AN1/RPI33/RB1 24 52 RP98/RF2 PGED3/AN0/RPI32/RB0 25 51 USBID/RP99/RF3 6789012345678901234567890 2222333333333344444444445 PGEC1/AN6/RPI38/RB6GED1/AN7/RCV/RPI39/RB7V-/RA9REFV+/RA10REFAVDDAVSSAN8/PMA6/RPI40/RB8AN9/PMA7//RPI41/RB9CV/PMA13/RPI42/RB10REFAN11/PMA12/RPI43/RB11VSSVDDTCK/RPI17/RA1RP109/RF13RP108/RF12AN12/PMA11/RPI44/RB12AN13/PMA10/RPI45/RB13AN14/PMA1/RPI46/RB14AN15/PMA0/RPI47/RB15VSSVDDRPI78/RD14RP79/RD15SDA2/PMA9/RP100/RF4SCL2/PMA8/RP101/RF5 P 0/ 1 N A Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information.  2009-2012 Microchip Technology Inc. DS70616G-page 9

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant 7 D R N28/PMD4/RP84/RE4N27/PMD3/RPI83/RE3N26/PMD2/RP82/RE2P125/RG13PI124/RG12P126/RG14N25/PMD1/RPI81/RE1N24/PMD0/RP80/RE0N23/RPI23/RA7N22/RPI22/RA6P112/RG0P113/RG12/RP97/RF1CMPST1/RP96/RF0CMPSTDDCAP3IN1+/V3/RP71/CMPST3IN2-/RP70/RD6MRD/RP69/RD5MWR/RP68/RD4PI77/RD13PI76/RD12MBE/RP67/RD3PH/RP66/RD2/RP65/RD1CPCON AAARRRAAAARRVVVVCCPPRRPDV 0987654321098765432109876 0999999999988888888887777 1 RP127/RG15 1 75 VSS VDD 2 74 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN29/PMD5/RP85/RE5 3 73 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN30/PMD6/RPI86/RE6 4 72 INT0/DMH/RP64/RD0 AN31/PMD7/RP87/RE7 5 71 PMCS1/RPI75/RD11 AN16/RPI49/RC1 6 70 ASCL1/PMCS2/RPI74/RD10 AN17/RPI50/RC2 7 69 ASDA1/DPLN/RPI73/RD9 AN18/RPI51/RC3 8 68 RTCC/DMLN/RPI72/RD8 AN19/RPI52/RC4 9 67 RPI31/RA15 C1IN3-/SCK2/PMA5/RP118/RG6 10 66 RPI30/RA14 C1IN1-/SDI2/PMA4/RPI119/RG7 11 65 VSS C2IN3-/SDO2/PMA3/RP120/RG8 12 PIC24EP512GU810 64 OSC2/CLKO/RC15 MCLR 13 PIC24EP256GU810 63 OSC1/RPI60/RC12 C2IN1-/PMA2/RPI121/RG9 14 62 VDD VSS 15 61 TDO/RPI21/RA5 VDD 16 60 TDI/RPI20/RA4 TMS/RPI16/RA0 17 59 ASDA2/RPI19/RA3 AN20/RPI88/RE8 18 58 ASCL2/RPI18/RA2 AN21/RPI89/RE9 19 57 D+/RG2 AN5/C1IN1+/VBUSON/VBUSST/RPI37/RB5 20 56 D-/RG3 AN4/C1IN2-/USBOEN/RPI36/RB4 21 55 VUSB3V3 AN3/C2IN1+/VPIO/RPI35/RB3 22 54 VBUS AN2/C2IN2-/VMIO/RPI34/RB2 23 53 RP104/RF8 PGEC3/AN1/RPI33/RB1 24 52 RP98/RF2 PGED3/AN0/RPI32/RB0 25 51 USBID/RP99/RF3 6789012345678901234567890 2222333333333344444444445 PGEC1/AN6/RPI38/RB6GED1/AN7/RCV/RPI39/RB7V-/RA9REFV+/RA10REFAVDDAVSSAN8/PMA6/RPI40/RB8AN9/PMA7//RPI41/RB9CV/PMA13/RPI42/RB10REFAN11/PMA12/RPI43/RB11VSSVDDTCK/RPI17/RA1RP109/RF13RP108/RF12AN12/PMA11/RPI44/RB12AN13/PMA10/RPI45/RB13AN14/PMA1/RPI46/RB14AN15/PMA0/RPI47/RB15VSSVDDRPI78/RD14RP79/RD15SDA2/PMA9/RP100/RF4SCL2/PMA8/RP101/RF5 P 0/ 1 N A Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. DS70616G-page 10  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 121-Pin TFBGA(1) = Pins are up to 5V tolerant dsPIC33EP256MU810 dsPIC33EP512MU810 1 2 3 4 5 6 7 8 9 10 11 A RE4 RE3 RG13 RE0 RG0 RF1 VDD NC RD12 RD2 RD1 B NC RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14 C RE6 VDD RG12 RG14 RA6 NC RD7 RD4 NC RC13 RD11 D RC1 RE7 RE5 NC NC NC RD6 RD13 RD0 NC RD10 E RC4 RC3 RG6 RC2 NC RG1 NC RA15 RD8 RD9 RA14 F MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 G RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 H RB5 RB4 NC NC NC VDD NC VBUS VUSB3V3 RG2 RA2 J RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 K RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 L RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Note1: Refer to Table2 for full pin names.  2009-2012 Microchip Technology Inc. DS70616G-page 11

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 2: PIN NAMES: dsPIC33EP256MU810 AND dsPIC33EP512MU810 DEVICES(1,2) Pin Pin Full Pin Name Full Pin Name Number Number A1 AN28/PWM3L/PMD4/RP84/RE4 E8 RPI31/RA15 A2 AN27/PWM2H/PMD3/RPI83/RE3 E9 RTCC/DMLN/RPI72/RD8 A3 RP125/RG13 E10 ASDA1(3)/DPLN/RPI73/RD9 A4 AN24/PWM1L/PMD0/RP80/RE0 E11 RPI30/RA14 A5 RP112/RG0 F1 MCLR A6 VCMPST2/RP97/RF1 F2 C2IN3-/SDO2/PMA3/RP120/RG8 A7 VDD F3 C2IN1-/PMA2/RPI121/RG9 A8 No Connect F4 C1IN1-/SDI2/PMA4/RPI119/RG7 A9 RPI76/RD12 F5 VSS A10 DPH/RP66/RD2 F6 No Connect A11 VCPCON/RP65/RD1 F7 No Connect B1 No Connect F8 VDD B2 RP127/RG15 F9 OSC1/RPI60/RC12 B3 AN26/PWM2L/PMD2/RP82/RE2 F10 VSS B4 AN25/PWM1H/PMD1/RPI81/RE1 F11 OSC2/CLKO/RC15 B5 AN23/RPI23/RA7 G1 AN20/RPI88/RE8 B6 VCMPST1/RP96/RF0 G2 AN21/RPI89/RE9 B7 VCAP G3 TMS/RPI16/RA0 B8 PMRD/RP69/RD5 G4 No Connect B9 PMBE/RP67/RD3 G5 VDD B10 VSS G6 VSS B11 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 G7 VSS C1 AN30/PWM4L/PMD6/RPI86/RE6 G8 No Connect C2 VDD G9 TDO/RPI21/RA5 C3 RPI124/RG12 G10 ASDA2(3)/RPI19/RA3 C4 RP126/RG14 G11 TDI/RPI20/RA4 C5 AN22/RPI22/RA6 H1 AN5/C1IN1+/VBUSON/VBUSST/RPI37/RB5 C6 No Connect H2 AN4/C1IN2-/USBOEN/RPI36/RB4 C7 C3IN1+/VCMPST3/RP71/RD7 H3 No Connect C8 PMWR/RP68/RD4 H4 No Connect C9 No Connect H5 No Connect C10 PGED2/SOSCI/C3IN3-/RPI61/RC13 H6 VDD C11 PMCS1/RPI75/RD11 H7 No Connect D1 AN16/PWM5L/RPI49/RC1 H8 VBUS D2 AN31/PWM4H/PMD7/RP87/RE7 H9 VUSB3V3 D3 AN29/PWM3H/PMD5/RP85/RE5 H10 D+/RG2(4) D4 No Connect H11 ASCL2(3)/RPI18/RA2 D5 No Connect J1 AN3/C2IN1+/VPIO/RPI35/RB3 D6 No Connect J2 AN2/C2IN2-/VMIO/RPI34/RB2 D7 C3IN2-/RP70/RD6 J3 PGED1/AN7/RCV/RPI39/RB7 D8 RPI77/RD13 J4 AVDD D9 INT0/DMH/RP64/RD0 J5 AN11/PMA12/RPI43/RB11 D10 No Connect J6 TCK/RPI17/RA1 D11 ASCL1(3)/PMCS2/RPI74/RD10 J7 AN12/PMA11/RPI44/RB12 Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 4: The pin name is SCL1/RG2 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices. 5: The pin name is SDA1/RG3 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices. DS70616G-page 12  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 2: PIN NAMES: dsPIC33EP256MU810 AND dsPIC33EP512MU810 DEVICES(1,2) (CONTINUED) Pin Pin Full Pin Name Full Pin Name Number Number E1 AN19/PWM6H/RPI52/RC4 J8 No Connect E2 AN18/PWM6L/RPI51/RC3 J9 No Connect E3 C1IN3-/SCK2/PMA5/RP118/RG6 J10 RP104/RF8 E4 AN17/PWM5H/RPI50/RC2 J11 D-/RG3(5) E5 No Connect K1 PGEC3/AN1/RPI33/RB1 E6 RP113/RG1 K2 PGED3/AN0/RPI32/RB0 E7 No Connect K3 VREF+/RA10 K4 AN8/PMA6/RPI40/RB8 L3 AVSS K5 No Connect L4 AN9/PMA7//RPI41/RB9 K6 RP108/RF12 L5 AN10/CVREF/PMA13/RPI42/RB10 K7 AN14/PMA1/RPI46/RB14 L6 RP109/RF13 K8 VDD L7 AN13/PMA10/RPI45/RB13 K9 RP79/RD15 L8 AN15/PMA0/RPI47/RB15 K10 USBID/RP99/RF3 L9 RPI78/RD14 K11 RP98/RF2 L10 SDA2(3)/PMA9/RP100/RF4 L1 PGEC1/AN6/RPI38/RB6 L11 SCL2(3)/PMA8/RP101/RF5 L2 VREF-/RA9 Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 4: The pin name is SCL1/RG2 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices. 5: The pin name is SDA1/RG3 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices.  2009-2012 Microchip Technology Inc. DS70616G-page 13

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 121-Pin TFBGA(1) = Pins are up to 5V tolerant PIC24EP256GU810 PIC24EP512GU810 1 2 3 4 5 6 7 8 9 10 11 A RE4 RE3 RG13 RE0 RG0 RF1 VDD NC RD12 RD2 RD1 B NC RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14 C RE6 VDD RG12 RG14 RA6 NC RD7 RD4 NC RC13 RD11 D RC1 RE7 RE5 NC NC NC RD6 RD13 RD0 NC RD10 E RC4 RC3 RG6 RC2 NC RG1 NC RA15 RD8 RD9 RA14 F MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 G RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 H RB5 RB4 NC NC NC VDD NC VBUS VUSB3V3 RG2 RA2 J RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 K RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 L RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Note1: Refer to Table3 for full pin names. DS70616G-page 14  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 3: PIN NAMES: PIC24EP256GU810 AND PIC24EP512GU810 DEVICES(1,2) Pin Pin Full Pin Name Full Pin Name Number Number A1 AN28/PMD4/RP84/RE4 E8 RPI31/RA15 A2 AN27/PMD3/RPI83/RE3 E9 RTCC/DMLN/RPI72/RD8 A3 RP125/RG13 E10 ASDA1(3)/DPLN/RPI73/RD9 A4 AN24/PMD0/RP80/RE0 E11 RPI30/RA14 A5 RP112/RG0 F1 MCLR A6 VCMPST2/RP97/RF1 F2 C2IN3-/SDO2/PMA3/RP120/RG8 A7 VDD F3 C2IN1-/PMA2/RPI121/RG9 A8 No Connect F4 C1IN1-/SDI2/PMA4/RPI119/RG7 A9 RPI76/RD12 F5 VSS A10 DPH/RP66/RD2 F6 No Connect A11 VCPCON/RP65/RD1 F7 No Connect B1 No Connect F8 VDD B2 RP127/RG15 F9 OSC1/RPI60/RC12 B3 AN26/PMD2/RP82/RE2 F10 VSS B4 AN25/PMD1/RPI81/RE1 F11 OSC2/CLKO/RC15 B5 AN23/RPI23/RA7 G1 AN20/RPI88/RE8 B6 VCMPST1/RP96/RF0 G2 AN21/RPI89/RE9 B7 VCAP G3 TMS/RPI16/RA0 B8 PMRD/RP69/RD5 G4 No Connect B9 PMBE/RP67/RD3 G5 VDD B10 VSS G6 VSS B11 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 G7 VSS C1 AN30/PMD6/RPI86/RE6 G8 No Connect C2 VDD G9 TDO/RPI21/RA5 C3 RPI124/RG12 G10 ASDA2(3)/RPI19/RA3 C4 RP126/RG14 G11 TDI/RPI20/RA4 C5 AN22/RPI22/RA6 H1 AN5/C1IN1+/VBUSON/VBUSST/RPI37/RB5 C6 No Connect H2 AN4/C1IN2-/USBOEN/RPI36/RB4 C7 C3IN1+/VCMPST3/RP71/RD7 H3 No Connect C8 PMWR/RP68/RD4 H4 No Connect C9 No Connect H5 No Connect C10 PGED2/SOSCI/C3IN3-/RPI61/RC13 H6 VDD C11 PMCS1/RPI75/RD11 H7 No Connect D1 AN16/RPI49/RC1 H8 VBUS D2 AN31/PMD7/RP87/RE7 H9 VUSB3V3 D3 AN29/PMD5/RP85/RE5 H10 D+/RG2(4) D4 No Connect H11 ASCL2(3)/RPI18/RA2 D5 No Connect J1 AN3/C2IN1+/VPIO/RPI35/RB3 D6 No Connect J2 AN2/C2IN2-/VMIO/RPI34/RB2 D7 C3IN2-/RP70/RD6 J3 PGED1/AN7/RCV/RPI39/RB7 D8 RPI77/RD13 J4 AVDD D9 INT0/DMH/RP64/RD0 J5 AN11/PMA12/RPI43/RB11 D10 No Connect J6 TCK/RPI17/RA1 D11 ASCL1(3)/PMCS2/RPI74/RD10 J7 AN12/PMA11/RPI44/RB12 Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 4: The pin name is SCL1/RG2 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices. 5: The pin name is SDA1/RG3 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices.  2009-2012 Microchip Technology Inc. DS70616G-page 15

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 3: PIN NAMES: PIC24EP256GU810 AND PIC24EP512GU810 DEVICES(1,2) (CONTINUED) Pin Pin Full Pin Name Full Pin Name Number Number E1 AN19/RPI52/RC4 J8 No Connect E2 AN18/RPI51/RC3 J9 No Connect E3 C1IN3-/SCK2/PMA5/RP118/RG6 J10 RP104/RF8 E4 AN17/RPI50/RC2 J11 D-/RG3(5) E5 No Connect K1 PGEC3/AN1/RPI33/RB1 E6 RP113/RG1 K2 PGED3/AN0/RPI32/RB0 E7 No Connect K3 VREF+/RA10 K4 AN8/PMA6/RPI40/RB8 L3 AVSS K5 No Connect L4 AN9/PMA7/RPI41/RB9 K6 RP108/RF12 L5 AN10/CVREF/PMA13/RPI42/RB10 K7 AN14/PMA1/RPI46/RB14 L6 RP109/RF13 K8 VDD L7 AN13/PMA10/RPI45/RB13 K9 RP79/RD15 L8 AN15/PMA0/RPI47/RB15 K10 USBID/RP99/RF3 L9 RPI78/RD14 K11 RP98/RF2 L10 SDA2(3)/PMA9/RP100/RF4 L1 PGEC1/AN6/RPI38/RB6 L11 SCL2(3)/PMA8/RP101/RF5 L2 VREF-/RA9 Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 4: The pin name is SCL1/RG2 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices. 5: The pin name is SDA1/RG3 for the dsPIC33EP512(GP/MC)806 and PIC24EP512GP806 devices. DS70616G-page 16  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 144-Pin TQFP, 144-pin LQFP = Pins are up to 5V tolerant 7 AN28/PWM3L/RP84/RE4AN27/PWM2H/RPI83/RE3AN26/PWM2L/RP82/RE2VSSRP125/RG13RPI124/RG12RP126/RG14AN25/PWM1H/RPI81/RE1AN24/PWM1L/RP80/RE0PMA7/RJ7PMA6/RJ6PMA5/RJ5PMA4/RJ4AN23/RPI23/RA7AN22/RPI22/RA6RP112/RG0RP113/RG1V2/RP97/RF1CMPSTV1/RP96/RF0CMPSTVSSVDDVCAPC3IN1+/V3/RP71/RDCMPSTC3IN2-/RP70/RD6RP69/RD5RP68/RD4PMA3/RJ3PMA2/RJ2PMA1/RJ1PMA0/RJ0RPI77/RD13RPI76/RD12VDDRP67/RD3DPH/RP66/RD2V/RP65/RD1CPCON 144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109 RP127/RG15 1 108 VSS VDD 2 107 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN29/PWM3H/RP85/RE5 3 106 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN30/PWM4L/RPI86/RE6 4 105 INT0/DMH/RP64/RD0 AN31/PWM4H/RP87/RE7 5 104 RH15 PWM7L/PMA8/RJ8 6 103 RH14 PWM7H/PMA9/RJ9 7 102 RH13 PMA10/RJ10 8 101 RH12 PMA11/RJ11 9 100 RPI75/RD11 AN16/PWM5L/RPI49/RC1 10 99 ASCL1/RPI74/RD10 AN17/PWM5H/RPI50/RC2 11 98 ASDA1/DPLN/RPI73/RD9 AN18/PWM6L/RPI51/RC3 12 97 RTCC/DMLN/RPI72/RD8 AN19/PWM6H/RPI52/RC4 13 96 RPI31/RA15 PMA12/RJ12 14 95 RPI30/RA14 PMA13/RJ13 15 94 PMCS1/RK11 C1IN3-/SCK2/RP118/RG6 16 93 PMCS2/RK12 C1IN1-/SDI2/RPI119/RG7 17 dsPIC33EP512MU814 92 VSS C2IN3-/SDO2/RP120/RG8 18 91 OSC2/CLKO/RC15 MCLR 19 dsPIC33EP256MU814 90 OSC1/RPI60/RC12 C2IN1-/RPI121/RG9 20 89 VDD RJ14 21 88 TDO/RPI21/RA5 RJ15 22 87 TDI/RPI20/RA4 VSS 23 86 ASDA2/RPI19/RA3 VDD 24 85 ASCL2/RPI18/RA2 TMS/RPI16/RA0 25 84 RH11 AN20/RPI88/RE8 26 83 RH10 AN21/RPI89/RE9 27 82 RH9 RK0 28 81 RH8 RK1 29 80 D+/RG2 AN5/C1IN1+/VBUSON/VBUSST/RPI37/RB5 30 79 D-/RG3 AN4/C1IN2-/USBOEN/RPI36/RB4 31 78 VUSB3V3 AN3/C2IN1+/VPIO/RPI35/RB3 32 77 VBUS AN2/C2IN2-/VMIO/RPI34/RB2 33 76 RP104/RF8 PGEC3/AN1/RPI33/RB1 34 75 RP98/RF2 PGED3/AN0/RPI32/RB0 35 74 USBID/RP99/RF3 VSS 36 73 VSS 789012345678901234567890123456789012 333444444444455555555556666666666777 C1/AN6/RPI38/RB6N7/RCV/RPI39/RB7V-/RA9REFV+/RA10REFAVDDAVSSPMD0/RH0PMD1/RH1PMD2/RH2PMD3/RH3AN8/RPI40/RB8AN9/RPI41/RB9CV/RPI42/RB10REFAN11/RPI43/RB11VSSVDDPMRD/RK15PMWR/RK14PMBE/RK13TCK/RPI17/RA1RP109/RF13RP108/RF12AN12/RPI44/RB12AN13/RPI45/RB13AN14/RPI46/RB14AN15/RPI47/RB15VSSVDDPMD4/RH4PMD5/RH5PMD6/RH6PMD7/RH7RPI78/RD14RP79/RD15SDA2/RP100/RF4SCL2/RP101/RF5 PGEED1/A AN10/ G P Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RKx) can be used as change notification (CNAx-CNKx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information.  2009-2012 Microchip Technology Inc. DS70616G-page 17

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Pin Diagrams (Continued) 144-Pin TQFP, 144-pin LQFP = Pins are up to 5V tolerant 7 D R 1/ 7 AN28/RP84/RE4AN27/RPI83/RE3AN26/RP82/RE2VSSRP125/RG13RPI124/RG12RP126/RG14AN25/RPI81/RE1AN24/RP80/RE0PMA7/RJ7PMA6/RJ6PMA5/RJ5PMA4/RJ4AN23/RPI23/RA7AN22/RPI22/RA6RP112/RG0RP113/RG1V2/RP97/RF1CMPSTV1/RP96/RF0CMPSTVSSVDDVCAPC3IN1+/V3/RPCMPSTC3IN2-/RP70/RD6RP69/RD5RP68/RD4PMA3/RJ3PMA2/RJ2PMA1/RJ1PMA0/RJ0RPI77/RD13RPI76/RD12VDDRP67/RD3DPH/RP66/RD2V/RP65/RD1CPCON 144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109 RP127/RG15 1 108 VSS VDD 2 107 PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 AN29/RP85/RE5 3 106 PGED2/SOSCI/C3IN3-/RPI61/RC13 AN30/RPI86/RE6 4 105 INT0/DMH/RP64/RD0 AN31/RP87/RE7 5 104 RH15 PMA8/RJ8 6 103 RH14 PMA9/RJ9 7 102 RH13 PMA10/RJ10 8 101 RH12 PMA11/RJ11 9 100 RPI75/RD11 AN16/RPI49/RC1 10 99 ASCL1/RPI74/RD10 AN17/RPI50/RC2 11 98 ASDA1/DPLN/RPI73/RD9 AN18/RPI51/RC3 12 97 RTCC/DMLN/RPI72/RD8 AN19/RPI52/RC4 13 96 RPI31/RA15 PMA12/RJ12 14 95 RPI30/RA14 PMA13/RJ13 15 94 PMCS1/RK11 C1IN3-/SCK2/RP118/RG6 16 93 PMCS2/RK12 C1IN1-/SDI2/RPI119/RG7 17 92 VSS C2IN3-/SDO2/RP120/RG8 18 PIC24EP512GU814 91 OSC2/CLKO/RC15 MCLR 19 PIC24EP256GU814 90 OSC1/RPI60/RC12 C2IN1-/RPI121/RG9 20 89 VDD RJ14 21 88 TDO/RPI21/RA5 RJ15 22 87 TDI/RPI20/RA4 VSS 23 86 ASDA2/RPI19/RA3 VDD 24 85 ASCL2/RPI18/RA2 TMS/RPI16/RA0 25 84 RH11 AN20/RPI88/RE8 26 83 RH10 AN21/RPI89/RE9 27 82 RH9 RK0 28 81 RH8 RK1 29 80 D+/RG2 AN5/C1IN1+/VBUSON/VBUSST/RPI37/RB5 30 79 D-/RG3 AN4/C1IN2-/USBOEN/RPI36/RB4 31 78 VUSB3V3 AN3/C2IN1+/VPIO/RPI35/RB3 32 77 VBUS AN2/C2IN2-/VMIO/RPI34/RB2 33 76 RP104/RF8 PGEC3/AN1/RPI33/RB1 34 75 RP98/RF2 PGED3/AN0/RPI32/RB0 35 74 USBID/RP99/RF3 VSS 36 73 VSS 789012345678901234567890123456789012 333444444444455555555556666666666777 C1/AN6/RPI38/RB6N7/RCV/RPI39/RB7V-/RA9REFV+/RA10REFAVDDAVSSPMD0/RH0PMD1/RH1PMD2/RH2PMD3/RH3AN8/RPI40/RB8AN9/RPI41/RB9CV/RPI42/RB10REFAN11/RPI43/RB11VSSVDDPMRD/RK15PMWR/RK14PMBE/RK13TCK/RPI17/RA1RP109/RF13RP108/RF12AN12/RPI44/RB12AN13/RPI45/RB13AN14/RPI46/RB14AN15/RPI47/RB15VSSVDDPMD4/RH4PMD5/RH5PMD6/RH6PMD7/RH7RPI78/RD14RP79/RD15SDA2/RP100/RF4SCL2/RP101/RF5 PGEED1/A AN10/ G P Note1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section11.4 “Peripheral Pin Select” for available peripherals and for information on limitations. 2: Every I/O port pin (RAx-RKx) can be used as change notification (CNAx-CNKx). See Section11.0 “I/O Ports” for more information. 3: The availability of I2C interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. DS70616G-page 18  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Table of Contents 1.0 Device Overview........................................................................................................................................................................23 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers and Microcontrollers........................................................31 3.0 CPU............................................................................................................................................................................................37 4.0 Memory Organization.................................................................................................................................................................47 5.0 Flash Program Memory............................................................................................................................................................135 6.0 Resets .....................................................................................................................................................................................141 7.0 Interrupt Controller...................................................................................................................................................................145 8.0 Direct Memory Access (DMA)..................................................................................................................................................159 9.0 Oscillator Configuration............................................................................................................................................................177 10.0 Power-Saving Features............................................................................................................................................................191 11.0 I/O Ports...................................................................................................................................................................................207 12.0 Timer1......................................................................................................................................................................................271 13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................275 14.0 Input Capture............................................................................................................................................................................281 15.0 Output Compare.......................................................................................................................................................................287 16.0 High-Speed PWM Module (dsPIC33EPXXX(MC/MU)8XX Devices Only)...............................................................................293 17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXX(MC/MU)8XX Devices Only)...................................................321 18.0 Serial Peripheral Interface (SPI)...............................................................................................................................................337 19.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................345 20.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................353 21.0 Enhanced CAN (ECAN™) Module...........................................................................................................................................359 22.0 USB On-The-Go (OTG) Module (dsPIC33EPXXXMU8XX and PIC24EPGU8XX Devices Only)............................................385 23.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC)......................................................................................................................413 24.0 Data Converter Interface (DCI) Module....................................................................................................................................429 25.0 Comparator Module..................................................................................................................................................................437 26.0 Real-Time Clock and Calendar (RTCC) ..................................................................................................................................449 27.0 Programmable Cyclic Redundancy Check (CRC) Generator..................................................................................................461 28.0 Parallel Master Port (PMP).......................................................................................................................................................467 29.0 Special Features......................................................................................................................................................................477 30.0 Instruction Set Summary..........................................................................................................................................................485 31.0 Development Support...............................................................................................................................................................495 32.0 Electrical Characteristics..........................................................................................................................................................499 33.0 DC and AC Device Characteristics Graphs..............................................................................................................................573 34.0 Packaging Information..............................................................................................................................................................577 Appendix A: Revision History.............................................................................................................................................................597  2009-2012 Microchip Technology Inc. DS70616G-page 19

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70616G-page 20  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33E/PIC24E Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: To access the documents listed below, browse to the documentation section of the dsPIC33EP512MU814 product page on the Microchip web site (www.microchip.com). In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en554310#1 • Section 1. “Introduction” (DS70573) • Section 2. “CPU” (DS70359) • Section 3. “Data Memory” (DS70595) • Section 4. “Program Memory” (DS70613) • Section 5. “Flash Programming” (DS70609) • Section 6. “Interrupts” (DS70600) • Section 7. “Oscillator” (DS70580) • Section 8. “Reset” (DS70602) • Section 9. “Watchdog Timer and Power-Saving Modes” (DS70615) • Section 10. “I/O Ports” (DS70598) • Section 11. “Timers” (DS70362) • Section 12. “Input Capture” (DS70352) • Section 13. “Output Compare” (DS70358) • Section 14. “High-Speed PWM” (DS70645) • Section 15. “Quadrature Encoder Interface (QEI)” (DS70601) • Section 16. “Analog-to-Digital Converter (ADC)” (DS70621) • Section 17. “UART” (DS70582) • Section 18. “Serial Peripheral Interface (SPI)” (DS70569) • Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70330) • Section 20. “Data Converter Interface (DCI)” (DS70356) • Section 21. “Enhanced Controller Area Network (ECAN™)” (DS70353) • Section 22. “Direct Memory Access (DMA)” (DS70348) • Section 23. “CodeGuard™ Security” (DS70634) • Section 24. “Programming and Diagnostics” (DS70608) • Section 25. “USB On-The-Go (OTG)” (DS70571) • Section 26. “Op Amp/Comparator” (DS70357) • Section 27. “Programmable Cyclic Redundancy Check (CRC)” (DS70346) • Section 28. “Parallel Master Port (PMP)” (DS70576) • Section 29. “Real-Time Clock and Calendar (RTCC)” (DS70584) • Section 30. “Device Configuration” (DS70618)  2009-2012 Microchip Technology Inc. DS70616G-page 21

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 22  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 1.0 DEVICE OVERVIEW This document contains device-specific information for the dsPIC33EPXXX(GP/MC/MU)806/810/814 Note1: This data sheet summarizes the features and PIC24EPXXX(GP/GU)810/814 Digital Signal of the dsPIC33EPXXX(GP/MC/MU)806/ Controller (DSC) and Microcontroller (MCU) devices. 810/814 and PIC24EPXXX(GP/GU)810/ The dsPIC33EPXXX(GP/MC/MU)806/810/814 devices 814 families of devices. It is not intended contain extensive Digital Signal Processor (DSP) to be a comprehensive resource. To com- functionality with a high-performance 16-bit MCU plement the information in this data architecture. sheet, refer to the related section of the Figure 1-1 illustrates a general block diagram “dsPIC33E/PIC24E Family Reference of the core and peripheral modules in Manual”, which is available from the the dsPIC33EPXXX(GP/MC/MU)806/810/814 and Microchip web site (www.microchip.com) PIC24EPXXX(GP/GU)810/814 families of devices. 2: Some registers and associated bits Table1-1 lists the functions of the various pins shown described in this section may not be in the pinout diagrams. available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information.  2009-2012 Microchip Technology Inc. DS70616G-page 23

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 1-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 BLOCK DIAGRAM X Address Bus Y Data Bus(1) X Data Bus PORTA 16 16 16 16 Data Latch Data Latch Interrupt PSV and Table Controller Data Access 8 16 Y Data X Data PORTB 24 Control Block RAM(1) RAM Address Address 16 24 24 Latch Latch us 16 16 PORTC 24 PPCrUograPmC CHounPteCrL ess B 16 XX WRAAGGUU Stack Loop ddr Control Control A Address Latch Logic Logic Y PORTD Y AGU(1) Program Memory Data Latch 16 16 EA MUX PORTE ch 16 24 at 24 M L IR O a R at PORTF D al er 16 Lit 16 x 16 W Reg Array 16 PORTG Instruction 16 16 Decode and Control Divide PORTH Control Signals DSP Support to Various Blocks Power-up Engine(1) Timer OSC1/CLKI Timing Oscillator Generation Start-up Timer PORTJ 16-Bit ALU POR/BOR 16 16 MCLR Watchdog PORTK VDD, VSS Timer AVDD, AVSS Remappable Comparator PWM(1) RTCC ECAN1, ADC1, Input Output I2C1, Pins (3-Channel) ECAN2 ADC2 Capture Compare I2C2 CRC QEI1(1), PMP USB Timers DCI SPI1- UART1- QEI2(1) OTG(2) SPI4 UART4 Note 1: This feature or peripheral is only available on dsPIC33EPXXX(MC/MU)806/810/814 devices. 2: This feature or peripheral is only available on dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU806/810/814 devices. DS70616G-page 24  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name PPS Description Type Type AN0-AN31 I Analog No Analog input channels. CLKI I ST/ No External clock source input. Always associated with OSC1 pin function. CMOS Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. CLKO O — No Always associated with OSC2 pin function. OSC1 I ST/ No Oscillator crystal input. ST buffer when configured in RC mode; CMOS CMOS otherwise. OSC2 I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI I ST/ No 32.768 kHz low-power oscillator crystal input; CMOS otherwise. CMOS SOSCO O — No 32.768 kHz low-power oscillator crystal output. IC1-IC16 I ST Yes Capture Inputs 1 through 16. OCFA I ST Yes Compare Fault A input (for Compare channels). OCFB I ST Yes Compare Fault B input (for Compare channels). OCFC I ST Yes Compare Fault C input (for Compare channels). OC1-OC16 O — Yes Compare Outputs 1 through 16. INT0 I ST No External Interrupt 0. INT1 I ST Yes External Interrupt 1. INT2 I ST Yes External Interrupt 2. INT3 I ST Yes External Interrupt 3. INT4 I ST Yes External Interrupt 4. RA0-RA7, RA9, I/O ST No PORTA is a bidirectional I/O port. RA10, RA14, RA15 RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC1-RC4, I/O ST No PORTC is a bidirectional I/O port. RC12-RC15 RD0-RD15 I/O ST No PORTD is a bidirectional I/O port. RE0-RE9 I/O ST No PORTE is a bidirectional I/O port. RF0-RF6, RF8 I/O ST No PORTF is a bidirectional I/O port. RF12, RF13 RG0, RG1 I/O ST No PORTG is a bidirectional I/O port. RG2, RG3(3) I/O ST No PORTG is a bidirectional I/O port. RG6-RG9, I/O ST No PORTG is a bidirectional I/O port. RG12-RG15 RH0-RH15 I/O ST No PORTH is a bidirectional I/O port. RJ0-RJ15 I/O ST No PORTJ is a bidirectional I/O port. RK0-RK1, I/O ST No PORTK is a bidirectional I/O port. RK11-RK15 Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer Note 1: This pin is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. 2: AVDD must be connected at all times. 3: These pins are input only on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 4: These pins are only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 5: The availability of I2C™ interfaces varies by device. Refer to the “Pin Diagrams” section for availability. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 6: Analog functionality is activated by enabling the USB module and is not controlled by the ANSEL register.  2009-2012 Microchip Technology Inc. DS70616G-page 25

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type T1CK I ST No Timer1 external clock input. T2CK I ST Yes Timer2 external clock input. T3CK I ST Yes Timer3 external clock input. T4CK I ST Yes Timer4 external clock input. T5CK I ST Yes Timer5 external clock input. T6CK I ST Yes Timer6 external clock input. T7CK I ST Yes Timer7 external clock input. T8CK I ST Yes Timer8 external clock input. T9CK I ST Yes Timer9 external clock input. U1CTS I ST Yes UART1 Clear-to-Send. U1RTS O — Yes UART1 Ready-to-Send. U1RX I ST Yes UART1 receive. U1TX O — Yes UART1 transmit. U2CTS I ST Yes UART2 Clear-to-Send. U2RTS O — Yes UART2 Ready-to-Send. U2RX I ST Yes UART2 receive. U2TX O — Yes UART2 transmit. U3CTS I ST Yes UART3 Clear-to-Send. U3RTS O — Yes UART3 Ready-to-Send. U3RX I ST Yes UART3 receive. U3TX O — Yes UART3 transmit. U4CTS I ST Yes UART4 Clear-to-Send. U4RTS O — Yes UART4 Ready-to-Send. U4RX I ST Yes UART4 receive. U4TX O — Yes UART4 transmit. SCK1 I/O ST Yes Synchronous serial clock input/output for SPI1. SDI1 I ST Yes SPI1 data in. SDO1 O — Yes SPI1 data out. SS1 I/O ST Yes SPI1 slave synchronization or frame pulse I/O. SCK2 I/O ST No Synchronous serial clock input/output for SPI2. SDI2 I ST No SPI2 data in. SDO2 O — No SPI2 data out. SS2 I/O ST Yes SPI2 slave synchronization or frame pulse I/O. SCK3 I/O ST Yes Synchronous serial clock input/output for SPI3. SDI3 I ST Yes SPI3 data in. SDO3 O — Yes SPI3 data out. SS3 I/O ST Yes SPI3 slave synchronization or frame pulse I/O. SCK4 I/O ST Yes Synchronous serial clock input/output for SPI4. SDI4 I ST Yes SPI4 data in. SDO4 O — Yes SPI4 data out. SS4 I/O ST Yes SPI4 slave synchronization or frame pulse I/O. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer Note 1: This pin is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. 2: AVDD must be connected at all times. 3: These pins are input only on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 4: These pins are only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 5: The availability of I2C™ interfaces varies by device. Refer to the “Pin Diagrams” section for availability. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 6: Analog functionality is activated by enabling the USB module and is not controlled by the ANSEL register. DS70616G-page 26  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type SCL1(5) I/O ST No Synchronous serial clock input/output for I2C1. SDA1(5) I/O ST No Synchronous serial data input/output for I2C1. ASCL1(5) I/O ST No Alternate synchronous serial clock input/output for I2C1. ASDA1(5) I/O ST No Alternate synchronous serial data input/output for I2C1. SCL2(5) I/O ST No Synchronous serial clock input/output for I2C2. SDA2(5) I/O ST No Synchronous serial data input/output for I2C2. ASCL2(5) I/O ST No Alternate synchronous serial clock input/output for I2C2. ASDA2(5) I/O ST No Alternate synchronous serial data input/output for I2C2. TMS I ST No JTAG Test mode select pin. TCK I ST No JTAG test clock input pin. TDI I ST No JTAG test data input pin. TDO O — No JTAG test data output pin. INDX1(1) I ST Yes Quadrature Encoder Index1 pulse input. HOME1(1) I ST Yes Quadrature Encoder Home1 pulse input. QEA1(1) I ST Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary timer external clock input in Timer mode. QEB1(1) I ST Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary timer external gate input in Timer mode. CNTCMP1(1) O — Yes Quadrature Encoder Compare Output 1. INDX2(1) I ST Yes Quadrature Encoder Index2 pulse input. HOME2(1) I ST Yes Quadrature Encoder Home2 pulse input. QEA2(1) I ST Yes Quadrature Encoder Phase A input in QEI2 mode. Auxiliary timer external clock input in Timer mode. QEB2(1) I ST Yes Quadrature Encoder Phase B input in QEI2 mode. Auxiliary timer external gate input in Timer mode. CNTCMP2(1) O — Yes Quadrature Encoder Compare Output 2. COFS I/O ST Yes Data Converter Interface frame synchronization pin. CSCK I/O ST Yes Data Converter Interface serial clock input/output pin. CSDI I ST Yes Data Converter Interface serial data input pin. CSDO O — Yes Data Converter Interface serial data output pin. C1RX I ST Yes ECAN1 bus receive pin. C1TX O — Yes ECAN1 bus transmit pin. C2RX I ST Yes ECAN2 bus receive pin. C2TX O — Yes ECAN2 bus transmit pin. RTCC O — No Real-Time Clock alarm output. CVREF O Analog No Comparator voltage reference output. C1IN1+, C1IN2-, I Analog No Comparator 1 inputs C1IN1-, C1IN3- C1OUT O — Yes Comparator 1 output. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer Note 1: This pin is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. 2: AVDD must be connected at all times. 3: These pins are input only on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 4: These pins are only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 5: The availability of I2C™ interfaces varies by device. Refer to the “Pin Diagrams” section for availability. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 6: Analog functionality is activated by enabling the USB module and is not controlled by the ANSEL register.  2009-2012 Microchip Technology Inc. DS70616G-page 27

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type C2IN1+, C2IN2-, I Analog No Comparator 2 inputs. C2IN1-, C2IN3- C2OUT O — Yes Comparator 2 output. C3IN1+, C3IN2-, I Analog No Comparator 3 inputs. C2IN1-, C3IN3- C3OUT O — Yes Comparator 3 output. PMA0 I/O TTL/ST No Parallel Master Port Address Bit 0 input (Buffered Slave modes) and output (Master modes). PMA1 I/O TTL/ST No Parallel Master Port Address Bit 1 input (Buffered Slave modes) and output (Master modes). PMA2 -PMA13 O — No Parallel Master Port Address Bits 2-13 (Demultiplexed Master modes). PMBE O — No Parallel Master Port byte enable strobe. PMCS1, PMCS2 O — No Parallel Master Port Chip Select 1 and 2 strobe. PMD0-PMD7 I/O TTL/ST No Parallel Master Port data (Demultiplexed Master mode) or address/data (Multiplexed Master modes). PMRD O — No Parallel Master Port read strobe. PMWR O — No Parallel Master Port write strobe. FLT1-FLT7(1) I ST Yes PWM Fault Input 1 through 7. DTCMP1-DTCMP7(1) I ST Yes PWM dead-time compensation input. PWM1L-PWM7L(1) O — No PWM Low Output 1 through 7. PWM1H-PWM7H(1) O — No PWM High Output 1 through 7. SYNCI1, SYNCI2(1) I ST Yes PWM Synchronization Inputs 1 and 2. SYNCO1, SYNCO2(1) O — Yes PWM Synchronization Outputs 1 and 2. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer Note 1: This pin is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. 2: AVDD must be connected at all times. 3: These pins are input only on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 4: These pins are only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 5: The availability of I2C™ interfaces varies by device. Refer to the “Pin Diagrams” section for availability. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 6: Analog functionality is activated by enabling the USB module and is not controlled by the ANSEL register. DS70616G-page 28  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type VBUS(4,6) I Analog No USB bus power monitor. VUSB3V3(4) P — No USB internal transceiver supply. If the USB module is not being used, this pin must be connected to VDD. VBUSON(4) O — No USB host and On-The-Go (OTG) bus power control output. D+(4,6) I/O Analog No D+ pin of internal USB transceiver. D-(4,6) I/O Analog No D- pin of internal USB transceiver. USBID(4) I ST No USB OTG ID detect. USBOEN(4) O — No USB output enabled control (for external transceiver). VBUSST(4) I ST No USB boost controller overcurrent detection. VCPCON(4) O — No USB boost controller PWM signal. VCMPST1(4) I ST No USB External Comparator 1 input. VCMPST2(4) I ST No USB External Comparator 2 input. VCMPST3(4) I ST No USB External Comparator 3 input. VMIO(4) I/O ST No USB differential minus input/output (external transceiver). VPIO(4) I/O ST No USB differential plus input/output (external transceiver). DMH(4) O — No D- external pull-up control output. DPH(4) O — No D+ external pull-up control output. DMLN(4) O — No D- external pull-down control output. DPLN(4) O — No D+ External Pull-down Control Output. RCV(4) I ST No USB receive input (from external transceiver). PGED1 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 1. PGEC1 I ST No Clock input pin for Programming/Debugging Communication Channel 1. PGED2 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 2. PGEC2 I ST No Clock input pin for Programming/Debugging Communication Channel 2. PGED3 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 3. PGEC3 I ST No Clock input pin for Programming/Debugging Communication Channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD(2) P P No Positive supply for analog modules. This pin must be connected at all times. AVSS P P No Ground reference for analog modules. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. VSS P — No Ground reference for logic and I/O pins. VREF+ I Analog No Analog voltage reference (high) input. VREF- I Analog No Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer Note 1: This pin is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. 2: AVDD must be connected at all times. 3: These pins are input only on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 4: These pins are only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. 5: The availability of I2C™ interfaces varies by device. Refer to the “Pin Diagrams” section for availability. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. 6: Analog functionality is activated by enabling the USB module and is not controlled by the ANSEL register.  2009-2012 Microchip Technology Inc. DS70616G-page 29

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 30  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 16-BIT DIGITAL The use of decoupling capacitors on every pair of SIGNAL CONTROLLERS AND power supply pins, such as VDD, VSS, VUSB3V3, MICROCONTROLLERS AVDD and AVSS is required. Consider the following criteria when using decoupling Note 1: This data sheet summarizes capacitors: the features of the dsPIC33EPXXX(GP/MC/MU)806/810/814 • Value and type of capacitor: Recommendation of and PIC24EPXXX(GP/GU)810/814 fami- 0.1 µF (100 nF), 10-20V. This capacitor should be a lies of devices. It is not intended to be a low-ESR and have resonance frequency in the comprehensive reference source. To range of 20MHz and higher. It is recommended to complement the information in this data use ceramic capacitors. sheet, refer to the related section of the • Placement on the printed circuit board: The “dsPIC33E/PIC24E Family Reference decoupling capacitors should be placed as close to Manual”, which is available from the the pins as possible. It is recommended to place the Microchip web site (www.microchip.com) capacitors on the same side of the board as the 2: Some registers and associated bits device. If space is constricted, the capacitor can be described in this section may not be placed on another layer on the PCB using a via; available on all devices. Refer to however, ensure that the trace length from the pin to Section4.0 “Memory Organization” in this data sheet for device-specific register the capacitor is within one-quarter inch (6mm) in and bit information. length. • Handling high frequency noise: If the board is 2.1 Basic Connection Requirements experiencing high frequency noise, above tens of MHz, add a second ceramic-type capacitor in Getting started with the 16-bit DSCs and microcontrollers parallel to the above described decoupling capaci- requires attention to a minimal set of device pin tor. The value of the second capacitor can be in the connections before proceeding with development. The range of 0.01µF to 0.001µF. Place this second following is a list of pin names, which must always be capacitor next to the primary decoupling capacitor. connected: In high-speed circuit designs, consider implement- • All VDD and VSS pins (see Section2.2 ing a decade pair of capacitances as close to the “Decoupling Capacitors”) power and ground pins as possible. For example, • All AVDD and AVSS pins (regardless if ADC module 0.1 µF in parallel with 0.001 µF. is not used) (see Section2.2 “Decoupling • Maximizing performance: On the board layout Capacitors”) from the power supply circuit, run the power and • VCAP (see Section2.3 “CPU Logic Filter return traces to the decoupling capacitors first, and Capacitor Connection (VCAP)”) then to the device pins. This ensures that the • MCLR pin (see Section2.4 “Master Clear (MCLR) decoupling capacitors are first in the power chain. Pin”) Equally important is to keep the trace length • PGECx/PGEDx pins used for In-Circuit Serial between the capacitor and the power pins to a Programming™ (ICSP™) and debugging purposes minimum, thereby reducing PCB track inductance. (see Section2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VUSB3V3 pin is used when utilizing the USB module. If the USB module is not used, VUSB3V3 must be connected to VDD. • VREF+/VREF- pin is used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. The voltage difference between AVDD and VDD cannot exceed 300 mV at any time during operation or start-up.  2009-2012 Microchip Technology Inc. DS70616G-page 31

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 2-1: RECOMMENDED to ground. The type can be ceramic or tantalum. See MINIMUM CONNECTION Section32.0 “Electrical Characteristics” for additional information. 0.1 µF The placement of this capacitor should be close to the VDD Ta1n0ta µluFm Ceramic VCAP. It is recommended that the trace length not exceeds one-quarter inch (6 mm). See Section29.2 R CAP VDD VSS “On-Chip Voltage Regulator” for details. R1 V MCLR 2.4 Master Clear (MCLR) Pin C VUSB3V3(1) The MCLR pin provides two specific device dsPIC33EP/ functions: PIC24EP VSS VDD • Device Reset • Device Programming and Debugging VDD VSS 0.1 µF D S 0.1 µF During device programming and debugging, the Ceramic AVD AVS VDD VSS Ceramic resistance and capacitance that can be added to the pin must be considered. Device programmers and 0.1 µF 0.1 µF debuggers drive the MCLR pin. Consequently, Ceramic Ceramic specific voltage levels (VIH and VIL) and fast signal L1(2) transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted Note 1: If the USB module is not used, VUSB3V3 must be connected to VDD, as shown. based on the application and PCB requirements. 2: As an option, instead of a hard-wired connection, an For example, as shown in Figure2-2, it is inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor recommended that the capacitor C, be isolated from impedance should be less than 1 and the inductor the MCLR pin during programming and debugging capacity greater than 10 mA. operations. Where: Place the components as shown in Figure2-2 within f = F-----C---N----V-- (i.e., ADC conversion rate/2) one-quarter inch (6mm) from the MCLR pin. 2 1 FIGURE 2-2: EXAMPLE OF MCLR PIN f = ----------------------- 2 LC CONNECTIONS L = ----------1------------2   VDD 2f C R(1) 2.2.1 TANK CAPACITORS R1(2) MCLR On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor JP dsPIC33EP for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should C be determined based on the trace resistance that con- nects the power supply source to the device and the maximum current drawn by the device in the applica- Note 1: R 10k is recommended. A suggested tion. In other words, select the tank capacitor so that it starting value is 10k. Ensure that the meets the acceptable voltage sag at the device. Typical MCLR pin VIH and VIL specifications are met. values range from 4.7µF to 47µF. 2: R1 470 will limit any current flowing into MCLR from the external capacitor C, in the 2.3 CPU Logic Filter Capacitor event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Connection (VCAP) Overstress (EOS). Ensure that the MCLR pin A low-ESR (< 1 Ohms) capacitor is required on the VIH and VIL specifications are met. VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD and must have a capacitor greater than 4.7µF (10 µF is recommended), 16V connected DS70616G-page 32  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 2.5 ICSP Pins FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR The PGECx and PGEDx pins are used for ICSP and CIRCUIT debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP con- Main Oscillator nector is expected to experience an ESD event, a 13 series resistor is recommended, with the value in the Guard Ring 14 range of a few tens of Ohms, not to exceed 100 Ohms. 15 Pull-up resistors, series diodes and capacitors on the Guard Trace 16 PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communi- Secondary 17 cations to the device. If such discrete components are Oscillator 18 an application requirement, they should be removed 19 from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and 20 timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high 2.7 Oscillator Value Conditions on (VIH) and input low (VIL) requirements. Device Start-up Ensure that the “Communication Channel Select” (i.e., If the PLL of the target device is enabled and PGECx/PGEDx pins) programmed into the device configured for the device start-up oscillator, the matches the physical connections for the ICSP to MPLAB® PICkit™ 3, MPLAB ICD 3, or MPLAB REAL maximum oscillator source frequency must be limited to 3 MHz < FIN < 5.5 MHz to comply with device PLL ICE™. start-up conditions. This means that if the external For more information on MPLAB ICD 3 and MPLAB oscillator frequency is outside this range, the REAL ICE connection requirements, refer to the application must start-up in the FRC mode first. The following documents that are available on the default PLL settings after a POR with an oscillator Microchip web site. frequency outside this range will violate the device • “Using MPLAB® ICD 3” (poster) DS51765 operating speed. • “MPLAB® ICD 3 Design Advisory” DS51764 Once the device powers up, the application firmware • “MPLAB® REAL ICE™ In-Circuit Emulator User’s can initialize the PLL SFRs, CLKDIV and PLLDBF to a Guide” DS51616 suitable value, and then perform a clock switch to the • “Using MPLAB® REAL ICE™ In-Circuit Emulator” Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration Word. (poster) DS51749 2.8 Unused I/Os 2.6 External Oscillator Pins Unused I/O pins should be configured as outputs and Many DSCs have options for at least two oscillators: a driven to a logic-low state. high-frequency primary oscillator and a low-frequency secondary oscillator. For details, see Section9.0 Alternatively, connect a 1k to 10k resistor between VSS “Oscillator Configuration” for details. and unused pins and drive the output to logic low. The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure2-3.  2009-2012 Microchip Technology Inc. DS70616G-page 33

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 2.9 Application Examples • Speech (playback, hands-free kits, answering machines, VoIP) • Induction heating • Consumer audio • Uninterruptable Power Supplies (UPS) • Industrial and building control (security systems • DC/AC inverters and access control) • Compressor motor control • Barcode reading • Washing machine 3-phase motor control • Networking: LAN switches, gateways • BLDC motor control • Data storage device management • Automotive HVAC, cooling fans, fuel pumps • Smart cards and smart card readers • Stepper motor control Examples of typical application connections are shown • Audio and fluid sensor monitoring in Figure2-4 through Figure2-8. • Camera lens focus and stability control FIGURE 2-4: BOOST CONVERTER IMPLEMENTATION VINPUT IPFC VOUTPUT k1 k3 k FET 2 Driver ADC Channel Comparator PWM ADC Channel Output dsPIC33EP DS70616G-page 34  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 2-5: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I 5V k7 DFrEivTer k1 k2 ADC M M Comparator ADC Channel W W Channel P P dsPIC33EP FIGURE 2-6: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 3.3V Output k 6 k FET FET 7 Driver Driver ADC MM M M Channel WW W W PWM FET PP P P PWM Driver k Comparator 3 dsPIC33EP k Comparator 4 k Comparator 5 ADC Channel  2009-2012 Microchip Technology Inc. DS70616G-page 35

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 2-7: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k k 1 2 VOUT- FET FET Driver Driver Comparator PWM Comparator PWM Comparator ADC Channel dsPIC33EP ADC Channel FIGURE 2-8: BEMF VOLTAGE MEASURED USING THE ADC MODULE dsPIC33EP/PIC24EP BLDC PWM3H PWM3L PWM2H 3-Phase PWM2L Inverter PWM1H PWM1L R49 R41 R34 R36 FLTx Fault R44 AN2 R52 Demand AN3 AN4 AN5 Phase Terminal Voltage Feedback DS70616G-page 36  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 3.0 CPU 3.3 Data Space Addressing The Base Data Space can be addressed as 32K words Note1: This data sheet summarizes the features of the dsPIC33EPXXX(GP/MC/MU)806/ or 64 Kbytes and is split into two blocks, referred to as 810/814 and PIC24EPXXX(GP/GU)810/ X and Y data memory. Each memory block has its own 814 families of devices. It is not intended independent Address Generation Unit (AGU). The to be a comprehensive reference source. MCU class of instructions operate solely through the X To complement the information in this memory AGU, which accesses the entire memory map data sheet, refer to Section 2. “CPU” as one linear data space. On dsPIC33EPXXX(GP/MC/ (DS70359) in the “dsPIC33E/PIC24E MU)806/810/814 devices, certain DSP instructions Family Reference Manual”, which is operate through the X and Y AGUs to support dual available from the Microchip web site operand reads, which splits the data address space (www.microchip.com). into two parts. The X and Y data space boundary is 2: Some registers and associated bits device-specific. described in this section may not be The upper 32 Kbytes of the data space memory map available on all devices. Refer to can optionally be mapped into Program Space at any Section4.0 “Memory Organization” in 16K program word boundary. The program-to-data this data sheet for device-specific register space mapping feature, known as Program Space and bit information. Visibility (PSV), lets any instruction access Program The CPU has a 16-bit (data) modified Harvard Space as if it were data space. Moreover, the Base architecture with an enhanced instruction set, including Data Space address is used in conjunction with a read significant support for digital signal processing. The or write page register (DSRPAG or DSWPAG) to form CPU has a 24-bit instruction word, with a variable an Extended Data Space (EDS) address. The EDS can length opcode field. The Program Counter (PC) is be addressed as 8M words or 16 Mbytes. Refer to 24bits wide and addresses up to 4M x 24 bits of user Section 3. “Data Memory” (DS70595) and Section 4. program memory space. “Program Memory” (DS70613) in the “dsPIC33E/ PIC24E Family Reference Manual” for more details on An instruction prefetch mechanism helps maintain EDS, PSV and table accesses. throughput and provides predictable execution. Most instructions execute in a single-cycle effective execu- On dsPIC33EPXXX(GP/MC/MU)806/810/814 devices, tion rate, with the exception of instructions that change overhead-free circular buffers (Modulo Addressing) are the program flow, the double-word move (MOV.D) supported in both X and Y address spaces. The instruction, PSV accesses and the table instructions. Modulo Addressing removes the software boundary Overhead free program loop constructs are supported checking overhead for DSP algorithms. The X AGU using the DO and REPEAT instructions, both of which circular addressing can be used with any of the MCU are interruptible at any point. class of instructions. The X AGU also supports Bit- Reversed Addressing to greatly simplify input or output 3.1 Registers data reordering for radix-2 FFT algorithms. PIC24EPXXX(GP/GU)810/814 devices do not support Devices have sixteen 16-bit working registers in the Modulo and Bit-Reversed Addressing. programmer’s model. Each of the working registers can act as a Data, Address or Address Offset register. 3.4 Addressing Modes The 16th working register (W15) operates as a Soft- ware Stack Pointer for interrupts and calls. The working The CPU supports these addressing modes: registers, W0 through W3, and selected bits from the • Inherent (no operand) STATUS register, have shadow registers for fast • Relative context saves and restores using a single POP.S or • Literal PUSH.S instruction. • Memory Direct 3.2 Instruction Set • Register Direct • Register Indirect The dsPIC33EPXXXMU806/810/814 instruction set has two classes of instructions: the MCU class of Each instruction is associated with a predefined instructions and the DSP class of instructions. The addressing mode group, depending upon its functional PIC24EPXXX(GP/GU)810/814 instruction set has the requirements. As many as six addressing modes are MCU class of instructions and does not support DSP supported for each instruction. instructions. These two instruction classes are seam- lessly integrated into the architecture and execute from a single execution unit. The instruction set includes many addressing modes and was designed for optimum Ccompiler efficiency.  2009-2012 Microchip Technology Inc. DS70616G-page 37

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 3-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 CPU BLOCK DIAGRAM X Address Bus Y Data Bus(1) X Data Bus PORTA 16 16 16 16 Interrupt PSV and Table Data Latch Data Latch Controller Data Access 8 16 Y Data X Data PORTB 24 Control Block RAM(1) RAM Address Address 16 24 24 Latch Latch us 16 16 PORTC 24 PPCroUgraPmC CHounPteCrL ess B 16 XX WRAAGGUU Stack Loop ddr Control Control A Address Latch Logic Logic Y PORTD Y AGU(1) Program Memory Data Latch 16 16 EA MUX PORTE ch 16 24 at 24 M L IR O a R at PORTF D al er 16 Lit 16 x 16 W Reg Array 16 PORTG Instruction 16 16 Decode and Control Divide PORTH Control Signals DSP Support to Various Blocks Power-up Engine(1) Timer OSC1/CLKI Timing Oscillator Generation Start-up Timer PORTJ 16-Bit ALU POR/BOR 16 16 MCLR Watchdog PORTK VDD, VSS Timer AVDD, AVSS Remappable Comparator PWM(1) RTCC ECAN1, ADC1, Input Output I2C1, Pins (3-Channel) ECAN2 ADC2 Capture Compare I2C2 CRC QEI1(1), PMP USB Timers DCI SPI1- UART1- QEI2(1) OTG(2) SPI4 UART4 Note 1: This feature or peripheral is only available on dsPIC33EPXXX(MC/MU)806/810/814 devices. 2: This feature or peripheral is only available on dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU806/810/814 devices. DS70616G-page 38  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 3.5 Programmer’s Model In addition to the registers contained in the programmer’s model, all devices in this family The programmer’s model is shown in Figure3-2. All contain control registers for interrupts, while registers in the programmer’s model are memory thedsPIC33EPXXX(GP/MC/MU)806/810/814 devices mapped and can be manipulated directly by contain control registers for Modulo and Bit-reversed instructions. Table3-1 lists a description of each Addressing. These registers are described in register. subsequent sections of this document. All registers associated with the programmer’s model are memory mapped, as shown in Table4-1. TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS Register(s) Name Description W0 through W15 Working Register Array ACCA, ACCB 40-Bit DSP Accumulators PC 23-Bit Program Counter SR ALU and DSP Engine Status register SPLIM Stack Pointer Limit Value register TBLPAG Table Memory Page Address register DSRPAG Extended Data Space (EDS) Read Page register DSWPAG Extended Data Space (EDS) Write Page register RCOUNT REPEAT Loop Count register DCOUNT(1) DO Loop Count register DOSTARTH(1,2), DOSTARTL(1,2) DO Loop Start Address register (High and Low) DOENDH(1), DOENDL(1) DO Loop End Address register (High and Low) CORCON Contains DSP Engine, DO Loop Control and Trap Status bits Note 1: This register is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: The DOSTARTH and DOSTARTL registers are read-only.  2009-2012 Microchip Technology Inc. DS70616G-page 39

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 3-2: PROGRAMMER’S MODEL D15 D0 W0 (WREG) W1 W2 W3 W4 DSP Operand W5 Registers W6 W7 Working/Address Registers W8 W9 DSP Address Registers W10 W11 W12 W13 Frame Pointer/W14 PUSH.s and POP.s shadows Stack Pointer/W15* 0 Nested DO Stack SPLIM* 0 Stack Pointer Limit AD39 AD31 AD15 AD0 DSP ACCA Accumulators(1) ACCB PC23 PC0 0 0 Program Counter 7 0 TBLPAG Data Table Page Address 9 0 DSRPAG X Data Space Read Page Address 8 0 DSWPAG X Data Space Write Page Address 15 0 RCOUNT Repeat Loop Counter 15 0 DCOUNT DO Loop Counter and Stack(1) 23 0 0 DOSTART 0 DO Loop Start Address and Stack(1) 23 0 0 DOEND 0 DO Loop End Address and Stack(1) 15 0 CORCON CPU Core Control Register SRL OA(1)OB(1) SA(1)SB(1)OAB(1)SAB(1)DA(1) DC IPL2IPL1 IPL0 RA N OV Z C Status Register Note 1: This feature or bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. DS70616G-page 40  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 3.6 CPU Resources 3.6.1 KEY RESOURCES Many useful resources related to the CPU are provided • See Section 16. “CPU” (DS70359) in the on the main product page of the Microchip web site for “dsPIC33E/PIC24E Family Reference Manual” the devices listed in this data sheet. This product page, • Code Samples which can be accessed using this link, contains the • Application Notes latest updates and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All related “dsPIC33E/PIC24E Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en554310  2009-2012 Microchip Technology Inc. DS70616G-page 41

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 3.7 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R -0 R/W-0 OA(1) OB(1) SA(1,4) SB(1,4) OAB(1) SAB(1) DA(1) DC bit 15 bit 8 R/W-0(2,3) R/W-0(2,3) R/W-0(2,3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0> RA N OV Z C bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit C = Clearable bit -n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit(1) 1 = Accumulator A has overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit(1) 1 = Accumulator B has overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1,4) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1,4) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit(1) 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1) 1 = Accumulators A or B are saturated or have been saturated at some time 0 = Neither Accumulator A or B are saturated bit 9 DA: DO Loop Active bit(1) 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data) of the result occurred Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL<3> = 1. 3: The IPL<2:0> bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations. DS70616G-page 42  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15, user interrupts are disabled) 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL<3> = 1. 3: The IPL<2:0> bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations.  2009-2012 Microchip Technology Inc. DS70616G-page 43

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 3-2: CORCON: CORE CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 VAR — US<1:0>(1) EDT(1,2) DL<2:0>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0 SATA(1) SATB(1) SATDW(1) ACCSAT(1) IPL3(3) SFA RND(1) IF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 VAR: Variable Exception Processing Latency Control bit 1 = Variable exception processing is enabled 0 = Fixed exception processing is enabled bit 14 Unimplemented: Read as ‘0’ bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits(1) 11 = Reserved 10 = DSP engine multiplies are mixed-sign 01 = DSP engine multiplies are unsigned 00 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit(1,2) 1 = Terminates executing DO loop at end of current loop iteration 0 = No effect bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits(1) 111 = 7 DO loops are active • • • 001 = 1 DO loop is active 000 = 0 DO loops are active bit 7 SATA: ACCA Saturation Enable bit(1) 1 = Accumulator A saturation is enabled 0 = Accumulator A saturation is disabled bit 6 SATB: ACCB Saturation Enable bit(1) 1 = Accumulator B saturation is enabled 0 = Accumulator B saturation is disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit(1) 1 = Data space write saturation is enabled 0 = Data space write saturation is disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit(1) 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(3) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: This bit is always read as ‘0’. 3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70616G-page 44  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED) bit 2 SFA: Stack Frame Active Status bit 1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and DSWPAG values 0 = Stack frame is not active; W14 and W15 address of EDS or Base Data Space bit 1 RND: Rounding Mode Select bit(1) 1 = Biased (conventional) rounding is enabled 0 = Unbiased (convergent) rounding is enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit(1) 1 = Integer mode is enabled for DSP multiply 0 = Fractional mode is enabled for DSP multiply Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: This bit is always read as ‘0’. 3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.  2009-2012 Microchip Technology Inc. DS70616G-page 45

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 3.8 Arithmetic Logic Unit (ALU) 3.9 DSP Engine (dsPIC33EPXXX(GP/ MC/MU)806/810/814 Devices Only) The ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless The DSP engine consists of a high-speed 17-bit x otherwise mentioned, arithmetic operations are two’s 17-bit multiplier, a 40-bit barrel shifter and a 40-bit complement in nature. Depending on the operation, the adder/subtracter (with two target accumulators, round ALU can affect the values of the Carry (C), Zero (Z), and saturation logic). Negative (N), Overflow (OV) and Digit Carry (DC) The DSP engine can also perform inherent accumula- Status bits in the SR register. The C and DC Status bits tor-to-accumulator operations that require no additional operate as Borrow and Digit Borrow bits, respectively, data. These instructions are: ADD, SUB and NEG. for subtraction operations. The DSP engine has options selected through bits in The ALU can perform 8-bit or 16-bit operations, the CPU Core Control register (CORCON), as listed depending on the mode of the instruction that is used. below: Data for the ALU operation can come from the W register array or data memory, depending on the • Fractional or integer DSP multiply (IF) addressing mode of the instruction. Likewise, output • Signed, unsigned or mixed-sign DSP multiply (US) data from the ALU can be written to the W register array • Conventional or convergent rounding (RND) or a data memory location. • Automatic saturation on/off for ACCA (SATA) • Automatic saturation on/off for ACCB (SATB) Refer to the “16-bit MCU and DSC Programmer’s • Automatic saturation on/off for writes to data Reference Manual” (DS70157) for information on the memory (SATDW) SR bits affected by each instruction. • Accumulator Saturation mode selection The core CPU incorporates hardware support for both (ACCSAT) multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit TABLE 3-2: DSP INSTRUCTIONS divisor division. SUMMARY 3.8.1 MULTIPLIER Algebraic ACC Write Instruction Using the high-speed 17-bit x 17-bit multiplier, the ALU Operation Back supports unsigned, signed, or mixed-sign operation in CLR A = 0 Yes several MCU multiplication modes: ED A = (x – y)2 No • 16-bit x 16-bit signed EDAC A = A + (x – y)2 No • 16-bit x 16-bit unsigned • 16-bit signed x 5-bit (literal) unsigned MAC A = A + (x•y) Yes • 16-bit signed x 16-bit unsigned MAC A = A + x2 No • 16-bit unsigned x 5-bit (literal) unsigned MOVSAC No change in A Yes • 16-bit unsigned x 16-bit signed MPY A = x•y No • 8-bit unsigned x 8-bit unsigned MPY A = x2 No 3.8.2 DIVIDER MPY.N A = – x•y No The divide block supports 32-bit/16-bit and 16-bit/16-bit MSC A = A – x•y Yes signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. DS70616G-page 46  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.0 MEMORY ORGANIZATION 4.1 Program Address Space Note: This data sheet summarizes the features The device program address memory space is 4M of the dsPIC33EPXXX(GP/MC/MU)806/ instructions. The space is addressable by a 24-bit 810/814 and PIC24EPXXX(GP/GU)810/ value derived either from the 23-bit PC during program 814 families of devices. It is not intended execution, or from table operation or data space to be a comprehensive reference source. remapping as described in Section4.8 “Interfacing To complement the information in this data Program and Data Memory Spaces”. sheet, refer to Section 4. “Program User application access to the program memory space Memory” (DS70613) of the “dsPIC33E/ is restricted to the lower half of the address range PIC24E Family Reference Manual”, which (0x000000 to 0x7FFFFF). The exception is the use of is available from the Microchip web site TBLRD/TBLWT operations, which use TBLPAG<7> to (www.microchip.com). permit access to the Configuration bits and Device ID sections of the configuration memory space. The device architecture features separate program and data memory spaces and buses. This architecture also The device program memory map is shown in allows the direct access of program memory from the Figure4-1. data space during code execution. FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 DEVICES(1) dsPIC33EP256MU806/810/814 and dsPIC33EP512(GP/MC/MU)806/810/814 and PIC24EP256GU810/814 PIC24EP512(GP/GU)806/810/814 GOTO Instruction(2) GOTO Instruction(2) 0x000000 Reset Address(2) Reset Address(2) 0x000002 0x000004 Interrupt Vector Table Interrupt Vector Table 0x0001FE nt 0x000200 me User Program eg Flash Memory User Program Space neral S (87552 instructions) (175F1la0s4h i nMsetrmucotriyons) 0x02ABFE ory Ge 0x02AC00 Mem Un(iRmepaledm ‘0e’ns)ted Unimplemented 00xx00555578F00E er (Read ‘0’s) s 0x7FBFFE U nt Auxiliary Program Auxiliary Program 0x7FC000 me Flash Memory Flash Memory 0x7FFFF8 y Seg AuxiliaVreyc Itnotrerrupt AuxiliaVreyc Itnotrerrupt 0x7FFFFA xiliar GOTO Instruction(2) GOTO Instruction(2) 0x7FFFFC Au Reset Address(2) Reset Address(2) 0x7FFFFE 0x800000 Reserved Reserved 0xF7FFFE e c Device Configuration Device Configuration 0xF80000 pa Registers Registers 0xF80012 S y 0xF80014 mor Reserved Reserved Me 0xF9FFFE n 0xFA0000 nfiguratio WRreitsee Lrvaetcdh WRreitsee Lrvaetcdh 000xxxFFFAAE00F01FF0F0EE o C 0xFF0000 DEVID (2 Words) DEVID (2 Words) 0xFF0002 Reserved Reserved 0xFFFFFE Note 1: Memory areas are not shown to scale. 2: The Reset location is controlled by the Reset Target Vector Select bit, RSTPRI (FICD<2>). See Section29.0 “Special Features” for more information.  2009-2012 Microchip Technology Inc. DS70616G-page 47

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS ORGANIZATION All devices reserve the addresses between 0x00000 The program memory space is organized in word- and 0x000200 for hard-coded program execution vec- addressable blocks. Although it is treated as 24bits tors. A hardware Reset vector is provided to redirect wide, it is more appropriate to think of each address of code execution from the default value of the PC on the program memory as a lower and upper word, with device Reset to the actual start of code. A GOTO the upper byte of the upper word being unimplemented. instruction is programmed by the user application at The lower word always has an even address, while the address 0x000000 of the primary Flash memory or at upper word has an odd address (Figure4-2). address 0x7FFFFC of the auxiliary Flash memory, with the actual address for the start of code at address Program memory addresses are always word-aligned 0x000002 of the primary Flash memory or at address on the lower word and addresses are incremented or 0x7FFFFE of the auxiliary Flash memory. Reset Target decremented by two during code execution. This Vector Select bit (RSTPRI) in the FPOR Configuration arrangement provides compatibility with data memory register controls whether primary or auxiliary Flash space addressing and makes data in the program Reset location is used. memory space accessible. A more detailed discussion of the interrupt vector tables is provided in Section7.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS70616G-page 48  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The CPU has a separate 16-bit wide data memory care must be taken when mixing byte and word space. The data space is accessed using separate operations, or translating from 8-bit MCU code. If a Address Generation Units (AGUs) for read and write misaligned read or write is attempted, an address error operations. The data memory maps are shown in trap is generated. If the error occurred on a read, the Figure4-3, Figure4-4, Figure4-5 and Figure4-6. instruction underway is completed. If the error occurred All Effective Addresses (EAs) in the data memory space on a write, the instruction is executed but the write does are 16 bits wide and point to bytes within the data space. not occur. In either case, a trap is then executed, This arrangement gives a Base Data Space address allowing the system and/or user application to examine range of 64Kbytes or 32K words. the machine state prior to execution of the address Fault. The Base Data Space address is used in conjunction with a Read or Write Page register (DSRPAG or All byte loads into any W register are loaded into the DSWPAG) to form an Extended Data Space, which has LSB. The MSB is not modified. a total address range of 16 MBytes. A Sign-Extend instruction (SE) is provided to allow user dsPIC33EPXXX(GP/MC/MU)806/810/814 and applications to translate 8-bit signed data to 16-bit PIC24EPXXX(GP/GU)810/814 devices implement up signed values. Alternatively, for 16-bit unsigned data, to 56Kbytes of data memory. If an EA point to a loca- user applications can clear the MSB of any W register tion outside of this area, an all-zero word or byte is by executing a Zero-Extend (ZE) instruction on the returned. appropriate address. 4.2.1 DATA SPACE WIDTH 4.2.3 SFR SPACE The data memory space is organized in byte- The first 4Kbytes of the Near Data Space, from 0x0000 addressable, 16-bit wide blocks. Data is aligned in to 0x0FFF, is primarily occupied by Special Function data memory and registers as 16-bit words, but all data Registers (SFRs). These are used by the core and space EAs resolve to bytes. The Least Significant peripheral modules for controlling the operation of the Bytes (LSBs) of each word have even addresses, while device. the Most Significant Bytes (MSBs) have odd SFRs are distributed among the modules that they addresses. control and are generally grouped together by module. Much of the SFR space contains unused addresses; 4.2.2 DATA MEMORY ORGANIZATION these are read as ‘0’. AND ALIGNMENT Note: The actual set of peripheral features and To maintain backward compatibility with PIC® MCU interrupts varies by the device. Refer to devices and improve data space memory usage the corresponding device tables and efficiency, the device instruction set supports both word pinout diagrams for device-specific and byte operations. As a consequence of byte information. accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. 4.2.4 NEAR DATA SPACE For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] results in a The 8-Kbyte area between 0x0000 and 0x1FFF is value of Ws + 1 for byte operations and Ws + 2 for word referred to as the Near Data Space. Locations in this operations. space are directly addressable through a 13-bit abso- lute address field within all memory direct instructions. A data byte read, reads the complete word that Additionally, the whole data space is addressable using contains the byte, using the LSb of any EA to determine MOV instructions, which support Memory Direct which byte to select. The selected byte is placed onto Addressing mode with a 16-bit address field, or by the LSB of the data path. That is, data memory and using Indirect Addressing mode using a working registers are organized as two parallel byte-wide register as an Address Pointer. entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.  2009-2012 Microchip Technology Inc. DS70616G-page 49

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33EP512(GP/MC/MU)806/810/814 DEVICES WITH 52-KBYTE RAM MSB LSB Address 16 Bits Address MSB LSB 0x0000 0x0000 4-Kbyte SFR Space 8-Kbyte SFR Space 0x0FFF 0x0FFE Near Data 0x1001 0x1000 Space 0x1FFF 0x1FFE 0x2001 0x2000 X Data RAM (X) 0x7FFF 0x7FFE 0x8001 0x8000 0x8FFF 0x8FFE 0x9001 0x9000 52-Kbyte SRAM Space Y Data RAM (Y) 0xCFFF 0xCFFE 0xD001 0xD000 Far DPSRAM (Y) Optionally Data 0xDFFF 0xDFFE Mapped Space 0xE001 0xE000 into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70616G-page 50  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 4-4: DATA MEMORY MAP FOR PIC24EP512(GP/GU)806/810/814 DEVICES WITH 52-KBYTE RAM MSB LSB Address 16 Bits Address MSB LSB 0x0000 0x0000 4-Kbyte SFR Space 8-Kbyte SFR Space 0x0FFF 0x0FFE Near Data 0x1001 0x1000 Space 0x1FFF 0x1FFE 0x2001 0x2000 0x7FFF 0x7FFE 0x8001 0x8000 X Data RAM (X) 52-Kbyte SRAM Space 0xCFFF 0xCFFE 0xD001 0xD000 Far DMA Dual Port RAM (X) Optionally Data 0xDFFF 0xDFFE Mapped Space 0xE001 0xE000 into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE  2009-2012 Microchip Technology Inc. DS70616G-page 51

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33EP256MU806/810/814 DEVICES WITH 28-KBYTE RAM MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 0x0FFF 0x0FFE N8-eKabry Dteata 0x1001 0x1000 Space 0x1FFF 0x1FFE 0x2001 0x2000 X Data RAM (X) 28-Kbyte 0x4FFF 0x4FFE SRAM Space 0x5001 0x5000 Y Data RAM (Y) 0x6FFF 0x6FFE 0x7001 0x7000 DMA Dual Port RAM (Y) 0x7FFF 0x7FFE 0x8001 0x8000 Far Data Space Optionally X Data Mapped Unimplemented (X) into Program Memory 0xFFFF 0xFFFE DS70616G-page 52  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 4-6: DATA MEMORY MAP FOR PIC24EP256GU810/814 DEVICES WITH 28-KBYTE RAM MSB LSB Address 16 Bits Address MSB LSB 0x0001 0x0000 4-Kbyte SFR Space SFR Space 8-Kbyte 0x0FFF 0x0FFE Near Data 0x1001 0x1000 Space 0x1FFF 0x1FFE 0x2001 0x2000 X Data RAM (X) 28-Kbyte SRAM Space 0x6FFF 0x6FFE 0x7001 0x7000 DMA Dual Port RAM 0x7FFF 0x7FFE 0x8001 0x8000 Far Data Space Optionally Mapped X Data into Program Unimplemented (X) Memory 0xFFFF 0xFFFE  2009-2012 Microchip Technology Inc. DS70616G-page 53

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.2.5 X AND Y DATA SPACES When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the The dsPIC33EPXXX(GP/MC/MU)806/810/814 core hardware ensures that the CPU is given precedence in has two data spaces, X and Y. These data spaces can accessing the DMA RAM location. Therefore, the DMA beconsidered either separate (for some DSP RAM provides a reliable means of transferring DMA instructions), or as one unified linear address range (for data without ever having to stall the CPU. MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and Note1: DMA RAM can be used for general separate data paths. This feature allows certain purpose data storage if the DMA function instructions to concurrently fetch two words from RAM, is not required in an application. thereby enabling efficient execution of DSP algorithms 2: On PIC24EPXXX(GP/GU)806/810/814 such as Finite Impulse Response (FIR) filtering and devices, DMA RAM is located at the end Fast Fourier Transform (FFT). of X data RAM and is part of X data The PIC24EPXXX(GP/GU)806/810/814 devices do not space. have a Y data space and a Y AGU. For these devices, the entire data space is treated as X data space. 4.3 Program Memory Resources The X data space is used by all instructions and Many useful resources related to the Program Memory supports all addressing modes. X data space has are provided on the main product page of the Microchip separate read and write data buses. The X read data web site for the devices listed in this data sheet. This bus is the read data path for all instructions that view product page, which can be accessed using this link, data space as combined X and Y address space. It is contains the latest updates and additional information. also the X data prefetch path for the dual operand DSP instructions (MAC class). Note: In the event you are not able to access the The Y data space is used in concert with the X data product page using the link above, enter space by the MAC class of instructions (CLR, ED, this URL in your browser: EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide http://www.microchip.com/wwwproducts/ two concurrent data read paths. Devices.aspx?dDocName=en554310 Both the X and Y data spaces support Modulo 4.3.1 KEY RESOURCES Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed • Section 4. “Program Memory” (DS70612) in the Addressing mode is only supported for writes to X data “dsPIC33E/PIC24E Family Reference Manual” space. Modulo Addressing and Bit-Reversed • Code Samples Addressing are not present in PIC24EPXXX(GP/ • Application Notes GU)806/810/814 devices. • Software Libraries All data memory writes, including in DSP instructions, • Webinars view data space as combined X and Y address space. • All related “dsPIC33E/PIC24E Family Reference The boundary between the X and Y data spaces is Manual” Sections device-dependent and is not user-programmable. • Development Tools 4.2.6 DMA RAM 4.4 Special Function Register Maps Each dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 device contains Table4-1 through Table4-72 provide mapping tables 4Kbytes of dual ported DMA RAM located at the end for all Special Function Registers (SFRs). of Y data RAM and is part of Y data space. Memory locations in the DMA RAM space are accessible simul- taneously by the CPU and the DMA Controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various periph- erals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. DS70616G-page 54  2009-2012 Microchip Technology Inc.

 TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXX(GP/MC/MU)806/810/814 DEVICES ONLY 2 0 0 All 9 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 1 2 W0 0000 W0 (WREG) 0000 M ic W1 0002 W1 0000 d roc W2 0004 W2 0000 sP hip W3 0006 W3 0000 IC Te W4 0008 W4 0000 3 c 3 hn W5 000A W5 0000 E o P log W6 000C W6 0000 X y Inc. WW78 000001E0 WW78 00000000 XX( G W9 0012 W9 0000 P W10 0014 W10 0000 / M W11 0016 W11 0000 C W12 0018 W12 0000 /M W13 001A W13 0000 U ) W14 001C W14 0000 8 0 W15 001E W15 1000 6 / SPLIM 0020 SPLIM 0000 8 1 ACCAL 0022 ACCAL 0000 0 / ACCAH 0024 ACCAH 0000 8 1 ACCAU 0026 Sign-Extension of ACCA<39> ACCAU 0000 4 ACCBL 0028 ACCBL 0000 a n ACCBH 002A ACCBH 0000 d ACCBU 002C Sign-Extension of ACCB<39> ACCBU 0000 P I PCL 002E PCL — 0000 C 2 PCH 0030 — — — — — — — — — PCH 0000 4 E DSRPAG 0032 — — — — — — DSRPAG 0001 P DSWPAG 0034 — — — — — — — DSWPAG 0001 X X RCOUNT 0036 RCOUNT 0000 X DCOUNT 0038 DCOUNT 0000 ( G DOSTARTL 003A DOSTARTL — 0000 P D S DOSTARTH 003C — — — — — — — — — — DOSTARTH 0000 /G 7 06 DOENDL 003E DOENDL — 0000 U 1 ) 6 DOENDH 0040 — — — — — — — — — — DOENDH 0000 8 G 1 -p Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 ag /8 e 55 14

D TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXX(GP/MC/MU)806/810/814 DEVICES ONLY (CONTINUED) d S s 70 All P 61 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 3 ag CORCON 0044 VAR — US<1:0> EDT DL<2:0> SATA SATB SATDW ACCSAT IPL3 SFA RND IF 0020 E e P 5 MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 X 6 XMODSRT 0048 XMODSRT<15:1> 0 0000 X X XMODEND 004A XMODEND<15:1> 1 0001 ( G YMODSRT 004C YMODSRT<15:1> 0 0000 P YMODEND 004E YMODEND<15:1> 1 0001 /M XBREV 0050 BREN XBREV<14:0> 0000 C / DISICNT 0052 — — DISICNT<13:0> 0000 M TBLPAG 0054 — — — — — — — — TBLPAG<7:0> 0000 U ) MSTRPR 0058 MSTRPR<15:0> 0000 8 0 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-2: CPU CORE REGISTER MAP FORPIC24EPXXX(GP/GU)810/814 DEVICES ONLY 2 0 0 File All 9 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Name Resets 0 1 2 W0 0000 W0 (WREG) 0000 M ic W1 0002 W1 0000 d roc W2 0004 W2 0000 sP hip W3 0006 W3 0000 IC Te W4 0008 W4 0000 3 c 3 hn W5 000A W5 0000 E o P log W6 000C W6 0000 X y Inc. WW78 000001E0 WW78 00000000 XX( G W9 0012 W9 0000 P W10 0014 W10 0000 / M W11 0016 W11 0000 C W12 0018 W12 0000 /M W13 001A W13 0000 U ) W14 001C W14 0000 8 0 W15 001E W15 1000 6 / SPLIM 0020 SPLIM 0000 8 1 PCL 002E PCL — 0000 0 / PCH 0030 — — — — — — — — — PCH 0000 8 1 DSRPAG 0032 — — — — — — DSRPAG<9:0> 0001 4 DSWPAG 0034 — — — — — — — DSWPAG<8:0> 0001 a n RCOUNT 0036 RCOUNT<15:0> 0000 d SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000 P I CORCON 0044 VAR — — — — — — — — — — — IPL3 SFA — — 0020 C 2 DISICNT 0052 — — DISICNT<13:0> 0000 4 E TBLPAG 0054 — — — — — — — — TBLPAG<7:0> 0000 P MSTRPR 0058 MSTRPR<15:0> 0000 X X Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 57 14

D TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY d S s 70 P 616 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts IC G 3 -p IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 3 a E g e IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 P 58 IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 X X IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF QEI1IF PSEMIF C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000 X IFS4 0808 — — — — QEI2IF — PSESMIF — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 (G IFS5 080A PWM2IF PWM1IF IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF USB1IF — — U3TXIF U3RXIF U3EIF — 0000 P / IFS6 080C — — — — — — — — — — — PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF 0000 M C IFS7 080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — — 0000 / M IFS8 0810 — ICDIF IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF — DMA14IF DMA13IF DMA12IF IC12IF OC12IF 0000 U IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 ) 8 IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 0 6 IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 / 8 IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE QEI1IE PSEMIE C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000 1 0 IEC4 0828 — — — — QEI2IE — PSESMIE — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE — 0000 / 8 IEC5 082A PWM2IE PWM1IE IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE USB1IE — — U3TXIE U3RXIE U3EIE — 0000 1 4 IEC6 082C — — — — — — — — — — — PWM7IE PWM6IE PWM5IE PWM4IE PWM3IE 0000 a IEC7 082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — — 0000 n d IEC8 0830 — ICDIE IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE — DMA14IE DMA13IE DMA12IE IC12IE OC12IE 0000 P IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 I C IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 2 4 IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 E IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 4444 P X IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 X IPC5 084A — IC8IP<2:0> — IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0> 4444 X  2 IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 (G 0 P 09 IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 /G -2 IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 0 U 12 Micro IIIPPPCCC91110 000888555462 ——— OITCC657IIPIPP<<<222::00:0>>> ——— DOIMCCA46I4IPPIP<<2<2:20:0:>0>> ——— POICMC3P5IIPIPP<<<222::0:00>>> ——— DOIMCCA68I3PIPIP<<2<2:2:00:>0>> 444444444444 )810/ c 8 hip IPC12 0858 — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0> 4444 1 Te IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0> 4444 4 c hn IPC14 085C — DCIEIP<2:0> — QEI1IP<2:0> — PSEMIP<2:0> — C2IP<2:0> 4444 o lo IPC15 085E — — — — — RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0> 0444 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY (CONTINUED) 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts 0 12 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 Mic IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444 d ro IPC18 0864 — QEI2IP<2:0> — — — — — PSESMIP<2:0> — — — — 4040 s c P hip IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — — 4440 IC Te IPC21 086A — U4EIP<2:0> — USB1IP<2:0> — — — — — — — — 4400 3 c 3 hn IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0> 4444 E olog IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — IC9IP<2:0> — OC9IP<2:0> 4444 PX y Inc IIPPCC2245 00887702 —— — PWM—6IP<2:0> — —— — PWM5—IP<2:0> — —— — PWM—4IP<2:0> — —— PPWWMM37IIPP<<22::00>> 40404044 XX . ( IPC29 087A — DMA9IP<2:0> — DMA8IP<2:0> — — — — — — — — 4400 G P IPC30 087C — SPI4IP<2:0> — SPI4EIP<2:0> — DMA11IP<2:0> — DMA10IP<2:0> 4444 / M IPC31 087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0> 4444 C IPC32 0880 — DMA13IP<2:0> — DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0> 4444 / M IPC33 0882 — IC13IP<2:0> — OC13IP<2:0> — — — — — DMA14IP<2:0> 4404 U IPC34 0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0> 4444 )8 IPC35 0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0> 0444 0 6 INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 /8 1 INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 8000 0 INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — — 0000 /8 1 INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 4 INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000 a n Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 59 14

D TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY d S s 70 P 616 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts IC G 3 -p IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 3 a E g e IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 P 60 IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 X X IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF QEI1IF PSEMIF C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000 X IFS4 0808 — — — — QEI2IF — PSESMIF — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 (G IFS5 080A PWM2IF PWM1IF IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF USB1IF — — U3TXIF U3RXIF U3EIF — 0000 P / IFS6 080C — — — — — — — — — — — — PWM6IF PWM5IF PWM4IF PWM3IF 0000 M C IFS7 080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — — 0000 / M IFS8 0810 — ICDIF IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF — DMA14IF DMA13IF DMA12IF IC12IF OC12IF 0000 U IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 ) 8 IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 0 6 IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 / 8 IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE QEI1IE PSEMIE C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000 1 0 IEC4 0828 — — — — QEI2IE — PSESMIE — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE — 0000 / 8 IEC5 082A PWM2IE PWM1IE IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE USB1IE — — U3TXIE U3RXIE U3EIE — 0000 1 4 IEC6 082C — — — — — — — — — — — — PWM6IE PWM5IE PWM4IE PWM3IE 0000 a IEC7 082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — — 0000 n d IEC8 0830 — ICDIE IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE — DMA14IE DMA13IE DMA12IE IC12IE OC12IE 0000 P IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 I C IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 2 4 IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 E IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 4444 P X IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 X IPC5 084A — IC8IP<2:0> — IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0> 4444 X  2 IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 (G 0 P 09 IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 /G -2 IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 0 U 12 Micro IIIPPPCCC91110 000888555426 ——— OITCC657IIPIPP<<<222::0:00>>> ——— DOIMCCA46I4IPPIP<<2<2:2:00:>0>> ——— POICMC3P5IIPIPP<<<222:0::00>>> ——— DOIMCCA68I3PIPIP<<2<2:2:00:>0>> 444444444444 )810/ c 8 hip IPC12 0858 — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0> 4444 1 Te IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0> 4444 4 c hn IPC14 085C — DCIEIP<2:0> — QEI1IP<2:0> — PSEMIP<2:0> — C2IP<2:0> 4444 o lo IPC15 085E — — — — — RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0> 0444 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY (CONTINUED) 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts 0 12 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 Mic IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444 d ro IPC18 0864 — QEI2IP<2:0> — — — — — PSESMIP<2:0> — — — — 4040 s c P hip IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — — 4440 IC Te IPC21 086A — U4EIP<2:0> — USB1IP<2:0> — — — — — — — — 4400 3 c 3 hn IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0> 4444 E olog IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — IC9IP<2:0> — OC9IP<2:0> 4444 PX y Inc IIPPCC2249 008877A0 —— PDWMMA96IIPP<<22::00>> —— PDWMMA85IIPP<<22::00>> —— — PWM—4IP<2:0> — —— — PWM3—IP<2:0> — 44444040 XX . ( IPC30 087C — SPI4IP<2:0> — SPI4EIP<2:0> — DMA11IP<2:0> — DMA10IP<2:0> 4444 G P IPC31 087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0> 4444 / M IPC32 0880 — DMA13IP<2:0> — DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0> 4444 C IPC33 0882 — IC13IP<2:0> — OC13IP<2:0> — — — — — DMA14IP<2:0> 4404 / M IPC34 0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0> 4444 U IPC35 0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0> 0444 )8 INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 0 6 INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 8000 /8 1 INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — — 0000 0 INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 /8 1 INTTREG 08C8 — — — — — ILR<3:0> VECNUM<7:0> 0000 4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 61 14

D TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY d S s 70 P 616 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts IC G 3 -p IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 3 a E g e IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 P 62 IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 X X IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF QEI1IF PSEMIF C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000 X IFS4 0808 — — — — QEI2IF — PSESMIF — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 (G IFS5 080A PWM2IF PWM1IF IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF USB1IF — — U3TXIF U3RXIF U3EIF — 0000 P / IFS6 080C — — — — — — — — — — — — — — PWM4IF PWM3IF 0000 M C IFS7 080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — — 0000 / M IFS8 0810 — ICDIF IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF — DMA14IF DMA13IF DMA12IF IC12IF OC12IF 0000 U IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 ) 8 IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 0 6 IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 / 8 IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE QEI1IE PSEMIE C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000 1 0 IEC4 0828 — — — — QEI2IE — PSESMIE — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE — 0000 / 8 IEC5 082A PWM2IE PWM1IE IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE USB1IE — — U3TXIE U3RXIE U3EIE — 0000 1 4 IEC6 082C — — — — — — — — — — — — — — PWM4IE PWM3IE 0000 a IEC7 082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — — 0000 n d IEC8 0830 — ICDIE IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE — DMA14IE DMA13IE DMA12IE IC12IE OC12IE 0000 P IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 I C IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 2 4 IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 E IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 4444 P X IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 X IPC5 084A — IC8IP<2:0> — IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0> 4444 X  2 IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 (G 0 P 09 IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 /G -2 IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 0 U 12 Micro IIIPPPCCC91110 000888555462 ——— OITCC657IIPIPP<<<222::00:0>>> ——— DOIMCCA46I4IPPIP<<2<2:2:00:>0>> ——— POICMC3P5IIPIPP<<<222::0:00>>> ——— DOIMCCA68I3IPPIP<<2<2:2:00:>0>> 444444444444 )810/ c 8 hip IPC12 0858 — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0> 4444 1 Te IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0> 4444 4 c hn IPC14 085C — DCIEIP<2:0> — QEI1IP<2:0> — PSEMIP<2:0> — C2IP<2:0> 4444 o lo IPC15 085E — — — — — RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0> 0444 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY (CONTINUED) 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts 0 12 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 Mic IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444 d ro IPC18 0864 — QEI2IP<2:0> — — — — — PSESMIP<2:0> — — — — 4040 s c P hip IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — — 4440 IC Te IPC21 086A — U4EIP<2:0> — USB1IP<2:0> — — — — — — — — 4400 3 c 3 hn IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0> 4444 E olog IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — IC9IP<2:0> — OC9IP<2:0> 4444 PX y Inc IIPPCC2249 008877A0 —— — DMA—9IP<2:0> — —— — DMA8—IP<2:0> — —— — PWM4—IP<2:0> — —— — PWM3—IP<2:0> — 04044040 XX . ( IPC30 087C — SPI4IP<2:0> — SPI4EIP<2:0> — DMA11IP<2:0> — DMA10IP<2:0> 4444 G P IPC31 087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0> 4444 / M IPC32 0880 — DMA13IP<2:0> — DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0> 4444 C IPC33 0882 — IC13IP<2:0> — OC13IP<2:0> — — — — — DMA14IP<2:0> 4404 / M IPC34 0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0> 4444 U IPC35 0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0> 0444 )8 INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 0 6 INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 8000 /8 1 INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — — 0000 0 INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 /8 1 INTTREG 08C8 — — — — — ILR<3:0> VECNUM<7:0> 0000 4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 63 14

D TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC806 DEVICES ONLY d S s 70 P 616 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts IC G 3 -p IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 3 a E g e IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 P 64 IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 X X IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF QEI1IF PSEMIF C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000 X IFS4 0808 — — — — QEI2IF — PSESMIF — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 (G IFS5 080A PWM2IF PWM1IF IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF — — — U3TXIF U3RXIF U3EIF — 0000 P / IFS6 080C — — — — — — — — — — — — — — PWM4IF PWM3IF 0000 M C IFS7 080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — — 0000 / M IFS8 0810 — ICDIF IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF — DMA14IF DMA13IF DMA12IF IC12IF OC12IF 0000 U IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 ) 8 IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 0 6 IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 / 8 IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE QEI1IE PSEMIE C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000 1 0 IEC4 0828 — — — — QEI2IE — PSESMIE — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE — 0000 / 8 IEC5 082A PWM2IE PWM1IE IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE — — — U3TXIE U3RXIE U3EIE — 0000 1 4 IEC6 082C — — — — — — — — — — — — — — PWM4IE PWM3IE 0000 a IEC7 082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — — 0000 n d IEC8 0830 — ICDIE IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE — DMA14IE DMA13IE DMA12IE IC12IE OC12IE 0000 P IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 I C IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 2 4 IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 E IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 4444 P X IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 X IPC5 084A — IC8IP<2:0> — IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0> 4444 X  2 IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 (G 0 P 09 IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 /G -2 IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 0 U 12 Micro IIIPPPCCC91110 000888555462 ——— OITCC657IIPIPP<<<222::00:0>>> ——— DOIMCCA46I4IPPIP<<2<2:2:00:>0>> ——— POICMC3P5IIPIPP<<<222::0:00>>> ——— DOIMCCA68I3IPPIP<<2<2:2:00:>0>> 444444444444 )810/ c 8 hip IPC12 0858 — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0> 4444 1 Te IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0> 4444 4 c hn IPC14 085C — DCIEIP<2:0> — QEI1IP<2:0> — PSEMIP<2:0> — C2IP<2:0> 4444 o lo IPC15 085E — — — — — RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0> 0444 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC806 DEVICES ONLY (CONTINUED) 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts 0 12 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 Mic IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444 d ro IPC18 0864 — QEI2IP<2:0> — — — — — PSESMIP<2:0> — — — — 4040 s c P hip IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — — 4440 IC Te IPC21 086A — U4EIP<2:0> — — — — — — — — — — — — 4400 3 c 3 hn IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0> 4444 E olog IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — IC9IP<2:0> — OC9IP<2:0> 4444 PX y Inc IIPPCC2249 008877A0 —— — DMA—9IP<2:0> — —— — DMA8—IP<2:0> — —— — PWM4—IP<2:0> — —— — PWM3—IP<2:0> — 04044040 XX . ( IPC30 087C — SPI4IP<2:0> — SPI4EIP<2:0> — DMA11IP<2:0> — DMA10IP<2:0> 4444 G P IPC31 087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0> 4444 / M IPC32 0880 — DMA13IP<2:0> — DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0> 4444 C IPC33 0882 — IC13IP<2:0> — OC13IP<2:0> — — — — — DMA14IP<2:0> 4404 / M IPC34 0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0> 4444 U IPC35 0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0> 0444 )8 INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 0 6 INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 8000 /8 1 INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — — 0000 0 INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 /8 1 INTTREG 08C8 — — — — — ILR<3:0> VECNUM<7:0> 0000 4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 65 14

D TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP806 AND PIC24EPXXXGP806 DEVICES ONLY d S s 70 P 616 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts IC G 3 -p IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 3 a E g e IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 P 66 IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 X X IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF — PSEMIF C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000 X IFS4 0808 — — — — — — PSESMIF — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 (G IFS5 080A — — IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF — — — U3TXIF U3RXIF U3EIF — 0000 P / IFS6 080C — — — — — — — — — — — — — — — — 0000 M C IFS7 080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — — 0000 / M IFS8 0810 — ICDIF IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF — DMA14IF DMA13IF DMA12IF IC12IF OC12IF 0000 U IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 ) 8 IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 0 6 IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 / 8 IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE — PSEMIE C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000 1 0 IEC4 0828 — — — — — — PSESMIE — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE — 0000 / 8 IEC5 082A — — IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE — — — U3TXIE U3RXIE U3EIE — 0000 1 4 IEC6 082C — — — — — — — — — — — — — — — — 0000 a IEC7 082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — — 0000 n d IEC8 0830 — ICDIE IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE — DMA14IE DMA13IE DMA12IE IC12IE OC12IE 0000 P IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 I C IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 2 4 IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 E IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 4444 P X IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 X IPC5 084A — IC8IP<2:0> — IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0> 4444 X  2 IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 (G 0 P 09 IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 /G -2 IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 0 U 12 Micro IIIPPPCCC91110 000888555624 ——— OITCC657IIPIPP<<<222::0:00>>> ——— DOIMCCA46I4IPPIP<<2<2:2:00:>0>> ——— POICMC3P5IIPIPP<<<222::0:00>>> ——— DOIMCCA68I3IPPIP<<2<2:2:00:>0>> 444444444444 )810/ c 8 hip IPC12 0858 — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0> 4444 1 Te IPC13 085A C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0> 4444 4 c hn IPC14 085C — DCIEIP<2:0> — — — — — PSEMIP<2:0> — C2IP<2:0> 4444 o lo IPC15 085E — — — — — RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0> 0444 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP806 AND PIC24EPXXXGP806 DEVICES ONLY (CONTINUED) 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts 0 12 IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 Mic IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444 d ro IPC18 0864 — — — — — — — — — PSESMIP<2:0> — — — — 4040 s c P hip IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — — 4440 IC Te IPC21 086A — U4EIP<2:0> — — — — — — — — — — — — 4400 3 c 3 hn IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0> 4444 E olog IPC23 086E — — — — — — — — — IC9IP<2:0> — OC9IP<2:0> 4444 PX y Inc IIPPCC2249 008877A0 —— — DMA9—IP<2:0> — —— — DMA8—IP<2:0> — —— —— —— —— —— —— —— —— 04044040 XX . ( IPC30 087C — SPI4IP<2:0> — SPI4EIP<2:0> — DMA11IP<2:0> — DMA10IP<2:0> 4444 G P IPC31 087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0> 4444 / M IPC32 0880 — DMA13IP<2:0> — DMA12IP<2:0> — IC12IP<2:0> — OC12IP<2:0> 4444 C IPC33 0882 — IC13IP<2:0> — OC13IP<2:0> — — — — — DMA14IP<2:0> 4404 / M IPC34 0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0> 4444 U IPC35 0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0> 0444 )8 INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 0 6 INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 8000 /8 1 INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — — 0000 0 INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 /8 1 INTTREG 08C8 — — — — — ILR<3:0> VECNUM<7:0> 0000 4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 67 14

D TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY d S s 70 P 616 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts IC G 3 -p IFS0 0800 NVMIF DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 3 a E g e IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 P 68 IFS2 0804 T6IF DMA4IF PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 X X IFS3 0806 — RTCIF DMA5IF DCIIF DCIEIF — — C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000 X IFS4 0808 — — — — — — — — C2TXIF C1TXIF DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 (G IFS5 080A — — IC9IF OC9IF SPI3IF SPI3EIF U4TXIF U4RXIF U4EIF USB1IF — — U3TXIF U3RXIF U3EIF — 0000 P / IFS7 080E IC11IF OC11IF IC10IF OC10IF SPI4IF SPI4EIF DMA11IF DMA10IF DMA9IF DMA8IF — — — — — — 0000 M C IFS8 0810 — ICDIF IC16IF OC16IF IC15IF OC15IF IC14IF OC14IF IC13IF OC13IF — DMA14IF DMA13IF DMA12IF IC12IF OC12IF 0000 / M IEC0 0820 NVMIE DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 U IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 ) 8 IEC2 0824 T6IE DMA4IE PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 0 6 IEC3 0826 — RTCIE DMA5IE DCIIE DCIEIE — — C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000 / 8 IEC4 0828 — — — — — — — — C2TXIE C1TXIE DMA7IE DMA6IE CRCIE U2EIE U1EIE — 0000 1 0 IEC5 082A — — IC9IE OC9IE SPI3IE SPI3EIE U4TXIE U4RXIE U4EIE USB1IE — — U3TXIE U3RXIE U3EIE — 0000 / 8 IEC7 082E IC11IE OC11IE IC10IE OC10IE SPI4IE SPI4EIE DMA11IE DMA10IE DMA9IE DMA8IE — — — — — — 0000 1 4 IEC8 0830 — ICDIE IC16IE OC16IE IC15IE OC15IE IC14IE OC14IE IC13IE OC13IE — DMA14IE DMA13IE DMA12IE IC12IE OC12IE 0000 a IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 n d IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 P IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 I C IPC3 0846 — NVMIP<2:0> — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 4444 2 4 IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 E IPC5 084A — IC8IP<2:0> — IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0> 4444 P X IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 X IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 X  2 IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 (G 0 P 09 IPC9 0852 — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 4444 /G -2 IPC10 0854 — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0> — IC6IP<2:0> 4444 0 U 12 Micro IIIPPPCCC111132 000888555A68 —— C2TTR68IIXPPI<<P22<::200:>>0> ——— MDINMI2TAC442IPIIPP<<<222:0::00>>> ——— SPINI2MTCP32IIPPIP<<<222::00:0>>> ——— OTTC798IIPPIP<<<222::00:0>>> 444444444444 )810/ c 8 hip IPC14 085C — DCIEIP<2:0> — — — — — — — — — C2IP<2:0> 4004 1 Te IPC15 085E — — — — — RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0> 0444 4 c hn IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 o lo IPC17 0862 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY (CONTINUED) 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts 0 12 IPC20 0868 — U3TXIP<2:0> — U3RXIP<2:0> — U3EIP<2:0> — — — — 4440 Mic IPC21 086A — U4EIP<2:0> — USB1IP<2:0> — — — — — — — — 4400 d ro IPC22 086C — SPI3IP<2:0> — SPI3EIP<2:0> — U4TXIP<2:0> — U4RXIP<2:0> 4444 s c P hip IPC23 086E — — — — — — — — — IC9IP<2:0> — OC9IP<2:0> 0044 IC Te IPC29 087A — DMA9IP<2:0> — DMA8IP<2:0> — — — — — — — — 4400 3 c 3 hn IPC30 087C — SPI4IP<2:0> — SPI4EIP<2:0> — DMA11IP<2:0> — DMA10IP<2:0> 4444 E olog IPC31 087E — IC11IP<2:0> — OC11IP<2:0> — IC10IP<2:0> — OC10IP<2:0> 4444 PX y Inc IIPPCC3323 00888802 —— DIMCA131I3PIP<2<:20:>0> —— DOMCA1132IPIP<<22:0:0>> —— — IC12—IP<2:0> — —— DOMCA1124IPIP<<22:0:0>> 44444044 XX . ( IPC34 0884 — IC15IP<2:0> — OC15IP<2:0> — IC14IP<2:0> — OC14IP<2:0> 4444 G P IPC35 0886 — — — — — ICDIP<2:0> — IC16IP<2:0> — OC16IP<2:0> 4444 / M INTCON1 08C0 NSTDIS — — — — — — — — DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 C INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 8000 / M INTCON3 08C4 — — — — — — — — — UAE DAE DOOVR — — — — 0000 U INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000 )8 INTTREG 08C8 — — — — — ILR<3:0> VECNUM<7:0> 0000 0 6 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 69 14

D TABLE 4-9: TIMER1 THROUGH TIMER9 REGISTER MAP d S s 70 P 616 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC G 3 -p TMR1 0100 Timer1 Register xxxx 3 a E g e PR1 0102 Period Register 1 FFFF P 70 T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — TSYNC TCS — 0000 X X TMR2 0106 Timer2 Register xxxx X TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx (G TMR3 010A Timer3 Register xxxx P / PR2 010C Period Register 2 FFFF M C PR3 010E Period Register 3 FFFF / M T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 U T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 ) 8 TMR4 0114 Timer4 Register xxxx 0 6 TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx / 8 TMR5 0118 Timer5 Register xxxx 1 0 PR4 011A Period Register 4 FFFF / 8 PR5 011C Period Register 5 FFFF 1 4 T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 a T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 n d TMR6 0122 Timer6 Register xxxx P TMR7HLD 0124 Timer7 Holding Register (for 32-bit operations only) xxxx I C TMR7 0126 Timer7 Register xxxx 2 4 PR6 0128 Period Register 6 FFFF E PR7 012A Period Register 7 FFFF P X T6CON 012C TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 X T7CON 012E TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 X  2 TMR8 0130 Timer8 Register xxxx (G 0 P 09 TMR9HLD 0132 Timer9 Holding Register (for 32-bit operations only) xxxx /G -2 TMR9 0134 Timer9 Register xxxx 0 U 12 Micro PPT8RRC89ON 000111333A68 TON — TSIDL — — — — PP—eerriioodd RReeggiiss—tteerr 89 TGATE TCKPS<1:0> T32 — TCS — FF0FF0FF0FF0 )810/ c 8 hip T9CON 013C TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 1 Te Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 c h n o lo g y In c .

 TABLE 4-10: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 16 REGISTER MAP 2 0 09 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Resets 0 1 2 IC1CON1 0140 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 M ic IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D d roc IC1BUF 0144 Input Capture 1 Buffer Register xxxx sP hip IC1TMR 0146 Input Capture 1 Timer 0000 IC Te IC2CON1 0148 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 3 c 3 hn IC2CON2 014A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D E o P log IC2BUF 014C Input Capture 2 Buffer Register xxxx X y Inc. IICC23TCMORN1 001145E0 — — ICSIDL ICTSEL<2:0> — Inpu—t Capture 2— Timer ICI<1:0> ICOV ICBNE ICM<2:0> 00000000 XX( G IC3CON2 0152 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D P IC3BUF 0154 Input Capture 3 Buffer Register xxxx /M IC3TMR 0156 Input Capture 3 Timer 0000 C IC4CON1 0158 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 /M IC4CON2 015A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D U ) IC4BUF 015C Input Capture 4 Buffer Register xxxx 8 0 IC4TMR 015E Input Capture 4 Timer 0000 6 / IC5CON1 0160 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 8 1 IC5CON2 0162 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D 0 / IC5BUF 0164 Input Capture 5 Buffer Register xxxx 8 1 IC5TMR 0166 Input Capture 5 Timer 0000 4 IC6CON1 0168 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 a n IC6CON2 016A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D d IC6BUF 016C Input Capture 6 Buffer Register xxxx P I IC6TMR 016E Input Capture 6 Timer 0000 C 2 IC7CON1 0170 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 4 E IC7CON2 0172 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D P IC7BUF 0174 Input Capture 7 Buffer Register xxxx X X IC7TMR 0176 Input Capture 7 Timer 0000 X IC8CON1 0178 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 ( G IC8CON2 017A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D P D S IC8BUF 017C Input Capture 8 Buffer Register xxxx /G 7 06 IC8TMR 017E Input Capture 8 Timer 0000 U 1 ) 6 8 G 1 -p 0 ag /8 e 71 14

D TABLE 4-10: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 16 REGISTER MAP (CONTINUED) d S s 70 All P 61 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p IC9CON1 0180 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 3 a E g IC9CON2 0182 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D e P 7 IC9BUF 0184 Input Capture 9 Buffer Register xxxx X 2 X IC9TMR 0186 Input Capture 9 Timer 0000 X IC10CON1 0188 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 ( G IC10CON2 018A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D P IC10BUF 018C Input Capture 10 Buffer Register xxxx /M IC10TMR 018E Input Capture 10 Timer 0000 C / IC11CON1 0190 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 M U IC11CON2 0192 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D ) IC11BUF 0194 Input Capture 11 Buffer Register xxxx 8 0 IC11TMR 0196 Input Capture 11 Timer 0000 6 / 8 IC12CON1 0198 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 1 IC12CON2 019A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D 0 / 8 IC12BUF 019C Input Capture 12 Buffer Register xxxx 1 IC12TMR 019E Input Capture 12 Timer 0000 4 a IC13CON1 01A0 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 n IC13CON2 01A2 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D d P IC13BUF 01A4 Input Capture 13 Buffer Register xxxx I C IC13TMR 01A6 Input Capture 13 Timer 0000 2 IC14CON1 01A8 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 4 E IC14CON2 01AA — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D P IC14BUF 01AC Input Capture 14 Buffer Register xxxx X X IC14TMR 01AE Input Capture 14 Timer 0000 X  IC15CON1 01B0 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 (G 2 0 IC15CON2 01B2 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D P 09-2 IC15BUF 01B4 Input Capture 15 Buffer Register xxxx /G 0 U 1 IC15TMR 01B6 Input Capture 15 Timer 0000 2 M IC16CON1 01B8 — — ICSIDL ICTSEL<2:0> — — — ICI<1:0> ICOV ICBNE ICM<2:0> 0000 )81 icro IC16CON2 01BA — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL<4:0> 000D 0/ c 8 hip IC16BUF 01BC Input Capture 16 Buffer Register xxxx 1 T IC16TMR 01BE Input Capture 16 Timer 0000 4 e ch Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n o lo g y In c .

 TABLE 4-11: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP 2 0 09 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Resets 0 1 2 OC1CON1 0900 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 M ic OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C d roc OC1RS 0904 Output Compare 1 Secondary Register xxxx sP hip OC1R 0906 Output Compare 1 Register xxxx IC Te OC1TMR 0908 Timer Value 1 Register xxxx 3 c 3 hn OC2CON1 090A — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 E o P log OC2CON2 090C FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C X y Inc. OOCC22RRS 009901E0 OutpuOt Cutopmutp Caroem 2p aSreec 2o nRdeagryis Rteergister xxxxxxxx XX( G OC2TMR 0912 Timer Value 2 Register xxxx P OC3CON1 0914 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 /M OC3CON2 0916 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C C OC3RS 0918 Output Compare 3 Secondary Register xxxx /M OC3R 091A Output Compare 3 Register xxxx U ) OC3TMR 091C Timer Value 3 Register xxxx 8 0 OC4CON1 091E — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 6 / OC4CON2 0920 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C 8 1 OC4RS 0922 Output Compare 4 Secondary Register xxxx 0 / OC4R 0924 Output Compare 4 Register xxxx 8 1 OC4TMR 0926 Timer Value 4 Register xxxx 4 OC5CON1 0928 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 a n OC5CON2 092A FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C d OC5RS 092C Output Compare 5 Secondary Register xxxx P I OC5R 092D Output Compare 5 Register xxxx C 2 OC5TMR 0930 Timer Value 5 Register xxxx 4 E OC6CON1 0932 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 P OC6CON2 0934 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C X X OC6RS 0936 Output Compare 6 Secondary Register xxxx X OC6R 0938 Output Compare 6 Register xxxx ( G OC6TMR 093A Timer Value 6 Register xxxx P D S OC7CON1 093C — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 /G 7 0 U 6 OC7CON2 093E FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C 1 ) 6G OC7RS 0940 Output Compare 7 Secondary Register xxxx 81 -p OC7R 0942 Output Compare 7 Register xxxx 0 ag /8 e 73 OLeCg7eTnMdR: 0—94 =4 unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Timer Value 7 Register xxxx 14

D TABLE 4-11: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP (CONTINUED) d S s 70 All P 61 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p OC8CON1 0946 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 3 a E g OC8CON2 0948 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C e P 7 OC8RS 094A Output Compare 8 Secondary Register xxxx X 4 X OC8R 094C Output Compare 8 Register xxxx X OC8TMR 094E Timer Value 8 Register xxxx ( G OC9CON1 0950 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 P OC9CON2 0952 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C /M OC9RS 0954 Output Compare 9 Secondary Register xxxx C / OC9R 0956 Output Compare 9 Register xxxx M U OC9TMR 0958 Timer Value 9 Register xxxx ) OC10CON1 095A — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 8 0 OC10CON2 095C FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C 6 / 8 OC10RS 095E Output Compare 10 Secondary Register xxxx 1 OC10R 0960 Output Compare 10 Register xxxx 0 / 8 OC10TMR 0962 Timer Value 10 Register xxxx 1 OC11CON1 0964 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 4 a OC11CON2 0966 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C n OC11RS 0968 Output Compare 11 Secondary Register xxxx d P OC11R 096A Output Compare 11 Register xxxx I C OC11TMR 096C Timer Value 11 Register xxxx 2 OC12CON1 096E — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 4 E OC12CON2 0970 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C P OC12RS 0972 Output Compare 12 Secondary Register xxxx X X OC12R 0974 Output Compare 12 Register xxxx X  OC12TMR 0976 Timer Value 12 Register xxxx (G 2 0 OC13CON1 0978 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 P 09-2 OC13CON2 097A FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C /G 0 U 1 OC13RS 097C Output Compare 13 Secondary Register xxxx 2 M OC13R 097E Output Compare 13 Register xxxx )81 icro OC13TMR 0980 Timer Value 13 Register xxxx 0/ c 8 hip OC14CON1 0982 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 1 T OC14CON2 0984 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C 4 e ch OC14RS 0986 Output Compare 14 Secondary Register xxxx n olo OC14R 0988 Output Compare 14 Register xxxx gy OC14TMR 098A Timer Value 14 Register xxxx Inc Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. .

 TABLE 4-11: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 16 REGISTER MAP (CONTINUED) 2 0 09-2 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 OC15CON1 098C — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 Mic OC15CON2 098E FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C d ro OC15RS 0990 Output Compare 15 Secondary Register xxxx s c P hip OC15R 0992 Output Compare 15 Register xxxx IC Te OC15TMR 0994 Timer Value 15 Register xxxx 3 c 3 hn OC16CON1 0996 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000 E olog OC16CON2 0998 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C PX y Inc OOCC1166RRS 009999CA OutpuOt Cutopmutp Caroem 1p6a rSee 1c6o nRdeagryis Rteergister xxxxxxxx XX . ( OC16TMR 099E Timer Value 16 Register xxxx G P Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / M C / M U ) 8 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 75 14

D TABLE 4-12: PWM REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY d S s 70 P 616 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC G 3 -p PTCON 0C00 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000 3 a E g e PTCON2 0C02 — — — — — — — — — — — — — PCLKDIV<2:0> 0000 P 76 PTPER 0C04 PTPER<15:0> FFF8 X X SEVTCMP 0C06 SEVTCMP<15:0> 0000 X MDC 0C0A MDC<15:0> 0000 (G STCON 0C0E — — — SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000 P / STCON2 0C10 — — — — — — — — — — — — — PCLKDIV<2:0> 0000 M C STPER 0C12 STPER<15:0> FFF8 / M SSEVTCMP 0C14 SSEVTCMP<15:0> 0000 U CHOP 0C1A CHPCLKEN — — — — — CHOPCLK<9:0> 0000 ) 8 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 6 / 8 1 TABLE 4-13: PWM GENERATOR 1 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY 0 / 8 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 1 Resets 4 a PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 n IOCON1 0C22 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000 d P FCLCON1 0C24 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 I C PDC1 0C26 PDC1<15:0> 0000 2 PHASE1 0C28 PHASE1<15:0> 0000 4 E DTR1 0C2A — — DTR1<13:0> 0000 P ALTDTR1 0C2C — — ALTDTR1<13:0> 0000 X X SDC1 0C2E SDC1<15:0> 0000 X  SPHASE1 0C30 SPHASE1<15:0> 0000 (G 2 0 TRIG1 0C32 TRGCMP<15:0> 0000 P 09-2 TRGCON1 0C34 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 /G 0 U 1 PWMCAP1 0C38 PWMCAP1<15:0> 0000 2 M LEBCON1 0C3A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 )81 icro LEBDLY1 0C3C — — — — LEB<11:0> 0000 0/ c 8 hip AUXCON1 0C3E — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 1 T Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 e c h n o lo g y In c .

 TABLE 4-14: PWM GENERATOR 2 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY 2 0 0 All 9 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 12 PWMCON2 0C40 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 M ic IOCON2 0C42 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000 d roc FCLCON2 0C44 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 sP hip PDC2 0C46 PDC2<15:0> 0000 IC Te PHASE2 0C48 PHASE2<15:0> 0000 3 c 3 hn DTR2 0C4A — — DTR2<13:0> 0000 E o P log ALTDTR2 0C4C — — ALTDTR2<13:0> 0000 X y Inc. SSDPHCA2SE2 00CC45E0 SPSHDACS2E<21<51:05>:0> 00000000 XX( G TRIG2 0C52 TRGCMP<15:0> 0000 P TRGCON2 0C54 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 / M PWMCAP2 0C58 PWMCAP2<15:0> 0000 C LEBCON2 0C5A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 /M LEBDLY2 0C5C — — — — LEB<11:0> 0000 U AUXCON2 0C5E — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 )8 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 / 8 1 TABLE 4-15: PWM GENERATOR 3 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY 0 / 8 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 1 Resets 4 a PWMCON3 0C60 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 n IOCON3 0C62 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000 d P FCLCON3 0C64 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 I C PDC3 0C66 PDC3<15:0> 0000 2 PHASE3 0C68 PHASE3<15:0> 0000 4 E DTR3 0C6A — — DTR3<13:0> 0000 P ALTDTR3 0C6C — — ALTDTR3<13:0> 0000 X X SDC3 0C6E SDC3<15:0> 0000 X SPHASE3 0C70 SPHASE3<15:0> 0000 (G D TRIG3 0C72 TRGCMP<15:0> 0000 P S7 TRGCON3 0C74 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 /G 0 U 6 PWMCAP3 0C78 PWMCAP3<15:0> 0000 1 ) 6 8 G LEBCON3 0C7A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 1 -pag LEBDLY3 0C7C — — — — LEB<11:0> 0000 0/8 e 77 ALeUgXeCnOdN:3x =0 Cu7nEknown v—alue on Res—et, — = unim—plemented—, read as ‘0’. Reset valuBeLsA aNrKe SsEhoLw<3n: 0in> hexadecimal. — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 14

D TABLE 4-16: PWM GENERATOR 4 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY d S s 7061 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 G 3 -p PWMCON4 0C80 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 3 a E ge IOCON4 0C82 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000 P 78 FCLCON4 0C84 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 X X PDC4 0C86 PDC4<15:0> 0000 X PHASE4 0C88 PHASE4<15:0> 0000 (G DTR4 0C8A — — DTR4<13:0> 0000 P / ALTDTR4 0C8C — — ALTDTR4<13:0> 0000 M SDC4 0C8E SDC4<15:0> 0000 C / SPHASE4 0C90 SPHASE4<15:0> 0000 M U TRIG4 0C92 TRGCMP<15:0> 0000 ) 8 TRGCON4 0C94 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 0 PWMCAP4 0C98 PWMCAP4<15:0> 0000 6 / 8 LEBCON4 0C9A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 1 LEBDLY4 0C9C — — — — LEB<11:0> 0000 0 / 8 AUXCON4 0C9E — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 1 4 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n TABLE 4-17: PWM GENERATOR 5 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)810/814 DEVICES ONLY d P File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All IC Resets 2 4 PWMCON5 0CA0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 E IOCON5 0CA2 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000 P X FCLCON5 0CA4 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 X PDC5 0CA6 PDC5<15:0> 0000 X  2 PHASE5 0CA8 PHASE5<15:0> 0000 (G 009 DTR5 0CAA — — DTR5<13:0> 0000 P/G -2 ALTDTR5 0CAC — — ALTDTR5<13:0> 0000 0 U 12 M SSDPHCA5SE5 00CCABE0 SPSHDACS5E<51<51:05>:0> 00000000 )81 icro TRIG5 0CB2 TRGCMP<15:0> 0000 0/ c 8 hip TRGCON5 0CB4 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 1 Te PWMCAP5 0CB8 PWM Capture<15:0> 0000 4 c h LEBCON5 0CBA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 n o lo LEBDLY5 0CBC — — — — LEB<11:0> 0000 g y AUXCON5 0CBE — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 In c Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. .

 TABLE 4-18: PWM GENERATOR 6 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)810/814 DEVICES ONLY 2 0 0 All 9 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 12 PWMCON6 0CC0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 M ic IOCON6 0CC2 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000 d roc FCLCON6 0CC4 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 sP hip PDC6 0CC6 PDC6<15:0> 0000 IC Te PHASE6 0CC8 PHASE6<15:0> 0000 3 c 3 hn DTR6 0CCA — — DTR6<13:0> 0000 E o P log ALTDTR6 0CCC — — ALTDTR6<13:0> 0000 X y Inc. SSDPHCA6SE6 00CCCDE0 SPSHDACS6E<61<51:05>:0> 00000000 XX( G TRIG6 0CD2 TRGCMP<15:0> 0000 P TRGCON6 0CD4 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 / M PWMCAP6 0CD8 PWMCAP6<15:0> 0000 C LEBCON6 0CDA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 /M LEBDLY6 0CDC — — — — LEB<11:0> 0000 U AUXCON6 0CDE — — — — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 )8 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 / 8 TABLE 4-19: PWM GENERATOR 7 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)814 DEVICES ONLY 1 0 / All 8 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 Resets 4 PWMCON7 0CE0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000 a n IOCON7 0CE2 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000 d FCLCON7 0CE4 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000 P I PDC7 0CE6 PDC7<15:0> 0000 C 2 PHASE7 0CE8 PHASE7<15:0> 0000 4 E DTR7 0CEA — — DTR7<13:0> 0000 P ALTDTR7 0CEC — — ALTDTR7<13:0> 0000 X X SDC7 0CEE SDC7<15:0> 0000 X SPHASE7 0CF0 SPHASE7<15:0> 0000 ( G TRIG7 0CF2 TRGCMP<15:0> 0000 P D S TRGCON7 0CF4 TRGDIV<3:0> — — — — — — TRGSTRT<5:0> 0000 /G 7 06 PWMCAP7 0CF8 PWMCAP7<15:0> 0000 U 1 ) 6 LEBCON7 0CFA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 8 G 1 -p LEBDLY7 0CFC — — — — LEB<11:0> 0000 0 age 79 LAeUgXeCnOd:N7x =0 CuFnEknown v—alue on Re—set, — = unim—plemented—, read as ‘0’. Reset valueBsL aArNe KsShoEwLn< 3in:0 h>exadecimal. — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000 /814

D TABLE 4-20: QEI1 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY d S s 7061 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 G 3 -p QEI1CON 01C0 QEIEN — QEISIDL PIMOD<2:0> IMV<1:0> — INTDIV<2:0> CNTPOL GATEN CCM<1:0> 0000 3 a E ge QEI1IOC 01C2 QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA 000x P 80 QEI1STAT 01C4 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN 0000 X X POS1CNTL 01C6 POSCNT<15:0> 0000 X POS1CNTH 01C8 POSCNT<31:16> 0000 (G POS1HLD 01CA POSHLD<15:0> 0000 P / VEL1CNT 01CC VELCNT<15:0> 0000 M INT1TMRL 01CE INTTMR<15:0> 0000 C / INT1TMRH 01D0 INTTMR<31:16> 0000 M U INT1HLDL 01D2 INTHLD<15:0> 0000 ) 8 INT1HLDH 01D4 INTHLD<31:16> 0000 0 INDX1CNTL 01D6 INDXCNT<15:0> 0000 6 / 8 INDX1CNTH 01D8 INDXCNT<31:16> 0000 1 0 INDX1HLD 01DA INDXHLD<15:0> 0000 / 8 QEI1GECL 01DC QEIGEC<15:0> 0000 1 4 QEI1ICL 01DC QEIIC<15:0> 0000 a QEI1GECH 01DE QEIGEC<31:16> 0000 n d QEI1ICH 01DE QEIIC<31:16> 0000 P QEI1LECL 01E0 QEILEC<15:0> 0000 I C QEI1LECH 01E2 QEILEC<31:16> 0000 2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-21: QEI2 REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY 2 0 0 All 9 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 1 2 QEI2CON 05C0 QEIEN — QEISIDL PIMOD<2:0> IMV<1:0> — INTDIV<2:0> CNTPOL GATEN CCM<1:0> 0000 M ic QEI2IOC 05C2 QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA 000x d roc QEI2STAT 05C4 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN 0000 sP hip POS2CNTL 05C6 POSCNT<15:0> 0000 IC Te POS2CNTH 05C8 POSCNT<31:16> 0000 3 c 3 hn POS2HLD 05CA POSHLD<15:0> 0000 E o P log VEL2CNT 05CC VELCNT<15:0> 0000 X y Inc. IINNTT22TTMMRRLH 0055CDE0 IINNTTTTMMRR<<3115:1:06>> 00000000 XX( G INT2HLDL 05D2 INTHLD<15:0> 0000 P INT2HLDH 05D4 INTHLD<31:16> 0000 / M INDX2CNTL 05D6 INDXCNT<15:0> 0000 C INDX2CNTH 05D8 INDXCNT<31:16> 0000 /M INDX2HLD 05DA INDXHLD<15:0> 0000 U ) QEI2GECL 05DC QEIGEC<15:0> 0000 8 0 QEI2ICL 05DC QEIIC<15:0> 0000 6 / QEI2GECH 05DE QEIGEC<31:16> 0000 8 1 QEI2ICH 05DE QEIIC<31:16> 0000 0 / QEI2LECL 05E0 QEILEC<15:0> 0000 8 1 QEI2LECH 05E2 QEILEC<31:16> 0000 4 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 81 14

D TABLE 4-22: I2C1 and I2C2 REGISTER MAP d S s 70 P 616 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC G 3 -p I2C1RCV 0200 — — — — — — — — I2Cx Receive Register 0000 3 a E g e I2C1TRN 0202 — — — — — — — — I2Cx Transmit Register 00FF P 82 I2C1BRG 0204 — — — — — — — Baud Rate Generator 0000 X X I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 X I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 (G I2C1ADD 020A — — — — — — I2Cx Address Register 0000 P / I2C1MSK 020C — — — — — — I2Cx Address Mask 0000 M C I2C2RCV 0210 — — — — — — — — I2Cx Receive Register 0000 / M I2C2TRN 0212 — — — — — — — — I2Cx Transmit Register 00FF U I2C2BRG 0214 — — — — — — — Baud Rate Generator 0000 ) 8 I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 0 6 I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 / 8 I2C2ADD 021A — — — — — — I2Cx Address Register 0000 1 0 I2C2MSK 021C — — — — — — I2Cx Address Mask 0000 / 8 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 4 a n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-23: UART1, UART2, UART3 and UART4 REGISTER MAP 2 0 0 All 9 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 1 2 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 M ic U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 d roc U1TXREG 0224 — — — — — — — UARTx Transmit Register xxxx sP hip U1RXREG 0226 — — — — — — — UARTxReceive Register 0000 IC Te U1BRG 0228 Baud Rate Generator Prescaler 0000 3 c 3 hn U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 E o P log U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 X y Inc. UU22TRXXRREEGG 00223364 —— —— —— —— —— —— —— UUAARRTTxx TRreacnesimveit RReeggiisstteerr x0x0x0x0 XX( G U2BRG 0238 Baud Rate Generator Prescaler 0000 P U3MODE 0250 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 / M U3STA 0252 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 C U3TXREG 0254 — — — — — — — UARTx Transmit Register xxxx /M U3RXREG 0256 — — — — — — — UARTx Receive Register 0000 U ) U3BRG 0258 Baud Rate Generator Prescaler 0000 8 0 U4MODE 02B0 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 6 / U4STA 02B2 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 8 1 U4TXREG 02B4 — — — — — — — UARTx Transmit Register xxxx 0 / U4RXREG 02B6 — — — — — — — UARTx Receive Register 0000 8 1 U4BRG 02B8 Baud Rate Generator Prescaler 0000 4 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 83 14

D TABLE 4-24: SPI1, SPI2, SPI3 and SPI4 REGISTER MAP d S s 7061 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 G 3 -p SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000 3 ag SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 E e P 8 SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000 X 4 SPI1BUF 0248 SPIx Transmit and Receive Buffer Register 0000 X X SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000 ( G SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 P SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000 /M SPI2BUF 0268 SPIx Transmit and Receive Buffer Register 0000 C / SPI3STAT 02A0 SPIEN — SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000 M SPI3CON1 02A2 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 U ) SPI3CON2 02A4 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000 8 0 SPI3BUF 02A8 SPIx Transmit and Receive Buffer Register 0000 6 / SPI4STAT 02C0 SPIEN — SPISIDL — — SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000 8 1 SPI4CON1 02C2 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 0 / SPI4CON2 02C4 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000 8 1 SPI4BUF 02C8 SPIx Transmit and Receive Buffer Register 0000 4 a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-25: ADC1 and ADC2 REGISTER MAP 2 0 09 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Resets 0 1 2 ADC1BUF0 0300 ADCx Data Buffer 0 xxxx M ic ADC1BUF1 0302 ADCx Data Buffer 1 xxxx d roc ADC1BUF2 0304 ADCx Data Buffer 2 xxxx sP hip ADC1BUF3 0306 ADCx Data Buffer 3 xxxx IC Te ADC1BUF4 0308 ADCx Data Buffer 4 xxxx 3 c 3 hn ADC1BUF5 030A ADCx Data Buffer 5 xxxx E o P log ADC1BUF6 030C ADCx Data Buffer 6 xxxx X y Inc. AADDCC11BBUUFF78 003301E0 AADDCCxx DDaattaa BBuuffffeerr 78 xxxxxxxx XX( G ADC1BUF9 0312 ADCx Data Buffer 9 xxxx P ADC1BUFA 0314 ADCx Data Buffer 10 xxxx /M ADC1BUFB 0316 ADCx Data Buffer 11 xxxx C ADC1BUFC 0318 ADCx Data Buffer 12 xxxx /M ADC1BUFD 031A ADCx Data Buffer 13 xxxx U ) ADC1BUFE 031C ADCx Data Buffer 14 xxxx 8 0 ADC1BUFF 031E ADCx Data Buffer 15 xxxx 6 / AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> SSRCG SIMSAM ASAM SAMP DONE 0000 8 1 AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS SMPI<4:0> BUFM ALTS 0000 0 / AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000 8 1 AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 4 AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000 a n AD1CSSH 032E CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 CSS23(1) CSS22(1) CSS21(1) CSS20(1) CSS19(1) CSS18(1) CSS17(1) CSS16(1) 0000 d AD1CSSL 0330 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 P I AD1CON4 0332 — — — — — — — ADDMAEN — — — — — DMABL<2:0> 0000 C 2 ADC2BUF0 0340 ADCx Data Buffer 0 xxxx 4 E ADC2BUF1 0342 ADCx Data Buffer 1 xxxx P ADC2BUF2 0344 ADCx Data Buffer 2 xxxx X X ADC2BUF3 0346 ADCx Data Buffer 3 xxxx X ADC2BUF4 0348 ADCx Data Buffer 4 xxxx ( G ADC2BUF5 034A ADCx Data Buffer 5 xxxx P D S ADC2BUF6 034C ADCx Data Buffer 6 xxxx /G 7 06 ADC2BUF7 034E ADCx Data Buffer 7 xxxx U 1 ) 6G ADC2BUF8 0350 ADCx Data Buffer 8 xxxx 81 -p Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 ag Note 1: These bits are not available on dsPIC33EP256MU806 devices. /8 e 85 14

D TABLE 4-25: ADC1 and ADC2 REGISTER MAP (CONTINUED) d S s 70 All P 61 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p ADC2BUF9 0352 ADCx Data Buffer 9 xxxx 3 a E g ADC2BUFA 0354 ADCx Data Buffer 10 xxxx e P 8 ADC2BUFB 0356 ADCx Data Buffer 11 xxxx X 6 X ADC2BUFC 0358 ADCx Data Buffer 12 xxxx X ADC2BUFD 035A ADCx Data Buffer 13 xxxx ( G ADC2BUFE 035C ADCx Data Buffer 14 xxxx P ADC2BUFF 035E ADCx Data Buffer 15 xxxx /M AD2CON1 0360 ADON — ADSIDL ADDMABM — — FORM<1:0> SSRC<2:0> SSRCG SIMSAM ASAM SAMP DONE 0000 C / AD2CON2 0362 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 M U AD2CON3 0364 ADRC — — SAMC<4:0> ADCS<7:0> 0000 ) AD2CHS123 0366 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 8 0 AD2CHS0 0368 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000 6 / 8 AD2CSSL 0270 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 1 AD2CON4 0272 — — — — — — — ADDMAEN — — — — — DMABL<2:0> 0000 0 / 8 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 Note 1: These bits are not available on dsPIC33EP256MU806 devices. 4 a n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-26: DCI REGISTER MAP 2 0 0 File All 9 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Name Resets 0 12 DCICON1 0280 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST — — — COFSM<1:0> 0000 M ic DCICON2 0282 — — — — BLEN<1:0> — COFSG<3:0> — WS<3:0> 0000 d roc DCICON3 0284 — — — — BCG<11:0> 0000 sP hip DCISTAT 0286 — — — — SLOT<3:0> — — — — ROV RFUL TUNF TMPTY 0000 IC Te TSCON 0288 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000 3 c 3 hn RSCON 028C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 0000 E o P log RXBUF0 0290 DCI Receive 0 Data Register uuuu X y Inc. RRXXBBUUFF12 00229924 DDCCII RReecceeiivvee 12 DDaattaa RReeggiisstteerr uuuuuuuu XX( G RXBUF3 0296 DCI Receive 3 Data Register uuuu P TXBUF0 0298 DCI Transmit 0 Data Register 0000 / M TXBUF1 029A DCI Transmit 1 Data Register 0000 C TXBUF2 029C DCI Transmit 2 Data Register 0000 /M TXBUF3 029E DCI Transmit 3 Data Register 0000 U Legend: x = unknown value on Reset, u = unchanged, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Shaded locations indicate reserved space in the SFR map for future module )8 expansion. Read reserved locations as ‘0’s. 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 87 14

D TABLE 4-27: USB OTG REGISTER MAP FOR dsPIC33EPMU806/810/814 AND PIC24EPGU806/10/814) DEVICES ONLY d S s 70 P 616 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC G 3 -p U1OTGIR 0488 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000 3 a E g e U1OTGIE 048A — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE 0000 P 88 U1OTGSTAT 048C — — — — — — — — ID — LSTATE — SESVD SESEND — VBUSVD 0000 X X U1OTGCON 048E — — — — — — — — DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000 X U1PWRC 0490 — — — — — — — — UACTPND(4) — — USLPGRD — — USUSPND USBPWR 0000 (G U1IR(1) 04C0 — — — — — — — — STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF 0000 P / U1IR(2) 04C0 — — — — — — — — STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF 0000 M U1IE(1) 04C2 — — — — — — — — STALLIE — RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE 0000 C / U1IE(2) 04C2 — — — — — — — — STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE DETACHIE 0000 M U U1EIR(1) 04C4 — — — — — — — — BTSEF BUSACCEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0000 ) 8 U1EIR(2) 04C4 — — — — — — — — BTSEF BUSACCEF DMAEF BTOEF DFN8EF CRC16EF EOFEF PIDEF 0000 0 U1EIE(1) 04C6 — — — — — — — — BTSEE BUSACCEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0000 6/ 8 U1EIE(2) 04C6 — — — — — — — — BTSEE BUSACCEE DMAEE BTOEE DFN8EE CRC16EE EOFEE PIDEE 0000 1 0 U1STAT 04C8 — — — — — — — — ENDPT<3:0>(3) DIR PPBI — — 0000 / 8 U1CON(1) 04CA — — — — — — — — — SE0 PKTDIS — HOSTEN RESUME PPBRST USBEN 0000 1 4 U1CON(2) 04CA — — — — — — — — JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN 0000 a U1ADDR 04CC — — — — — — — — LSPDEN(1) USB Device Address (DEVADDR) 0000 n d U1BDTP1 04CE — — — — — — — — BDTPTRL<15:9> — 0000 P U1FRML 04D0 — — — — — — — — FRML<7:0> 0000 I C U1FRMH 04D2 — — — — — — — — — — — — — FRMH<2:0> 0000 2 U1TOK(3) 04D4 — — — — — — — — PID<3:0> EP<3:0> 0000 4E U1SOF(3) 04D6 — — — — — — — — CNT<7:0> 0000 P X U1BDTP2 04D8 — — — — — — — — BDTPTRH<23:16> 0000 X U1BDTP3 04DA — — — — — — — — BDTPTRU<31:24> 0000 X  2 U1CNFG1 04DC — — — — — — — — UTEYE UOEMON — USBSIDL — — — — 0000 (G 0 P 09 U1CNFG2 O4DE — — — — — — — — — — UVCMPSEL PUVBUS EXTI2CEN UVBUSDIS UVCMPDIS UTRDIS 0000 /G -2 U1EP0 04E0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 0 U 12 Micro UUU111EEEPPP123 000444EEE246 ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— EEEPPPCCCOOONNNDDDIIISSS EEEPPPRRRXXXEEENNN EEEPPPTTTXXXEEENNN EEEPPPSSSTTTAAALLLLLL EEEPPPHHHSSSHHHKKK 000000000000 )810/ c 8 hip U1EP4 04E8 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 1 Te Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 ch Note 1: This bit is available when the module is operating in Device mode. no 2: This bit is available when the module is operating in Host mode log 3: Device mode only. These bits are always read as ‘0’ in Host mode. y In 4: The Reset value for this bit is undefined. c .

 TABLE 4-27: USB OTG REGISTER MAP FOR dsPIC33EPMU806/810/814 AND PIC24EPGU806/10/814) DEVICES ONLY (CONTINUED) 2 0 09-2 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 U1EP5 04EA — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 Mic U1EP6 04EC — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 d ro U1EP7 04EE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 s c P hip U1EP8 04F0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 IC Te U1EP9 04F2 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 3 c 3 hn U1EP10 04F4 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 E olog U1EP11 04F6 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 PX y Inc UU11EEPP1123 0044FFA8 —— —— —— —— —— —— —— —— —— —— —— EEPPCCOONNDDIISS EEPPRRXXEENN EEPPTTXXEENN EEPPSSTTAALLLL EEPPHHSSHHKK 00000000 XX . ( U1EP14 04FC — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 G P U1EP15 04FE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 / M U1PWMRRS 0580 DC<7:0> PER<7:0> 0000 C U1PWMCON 0582 PWMEN — — — — — PWMPOL CNTEN — — — — — — — — 0000 / M Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. U Note 1: This bit is available when the module is operating in Device mode. ) 8 2: This bit is available when the module is operating in Host mode 0 3: Device mode only. These bits are always read as ‘0’ in Host mode. 6 4: The Reset value for this bit is undefined. /8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 89 14

D TABLE 4-28: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1 d S s 70 P 616 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC G 3 -p C1CTRL1 0400 — — CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP — — WIN 0480 3 a E g e C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000 P 90 C1VEC 0404 — — — FILHIT<4:0> — ICODE<6:0> 0040 X X C1FCTRL 0406 DMABS<2:0> — — — — — — — — FSA<4:0> 0000 X C1FIFO 0408 — — FBP<5:0> — — FNRB<5:0> 0000 (G C1INTF 040A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000 P / C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000 M C C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000 / M C1CFG1 0410 — — — — — — — — SJW<1:0> BRP<5:0> 0000 U C1CFG2 0412 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000 ) 8 C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF 0 6 C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000 / 8 C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000 1 0 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 8 1 4 TABLE 4-29: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 a n d All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets P I C — 0400- See Table4-28 — 2 041E 4 C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 E P C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000 X C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000 X X  C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 (G 20 C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0> 0000 P 09 C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0> 0000 /G -2 0 C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0> 0000 U 1 2 M C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0> xxxx )81 icro C1RXD 0440 Received Data Word xxxx 0/ chip T CLe1gTeXnDd: x0 =4 4u2nknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexaTdraencismmaitl. Data Word xxxx 814 e c h n o lo g y In c .

 TABLE 4-30: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 2 0 0 All 9 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 12 — 0400- See Table4-28 — M 041E ic d ro C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 s c P hip C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000 IC Te C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000 3 chn C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000 3E ology Inc CCC111RRRXXXMMM001ESSIIIDDD 000444333204 ESSIIIDDD<<<111500:::833>>> SSIIDD<<22::00>> ——EID<7:0>MMIIDDEE —— EEIIDD<<1177::1166>> xxxxxxxxxxxx PXXX . ( C1RXM1EID 0436 EID<15:8> EID<7:0> xxxx G C1RXM2SID 0438 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx P / M C1RXM2EID 043A EID<15:8> EID<7:0> xxxx C C1RXF0SID 0440 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx / M C1RXF0EID 0442 EID<15:8> EID<7:0> xxxx U C1RXF1SID 0444 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx ) 8 C1RXF1EID 0446 EID<15:8> EID<7:0> xxxx 0 6 C1RXF2SID 0448 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx / 8 C1RXF2EID 044A EID<15:8> EID<7:0> xxxx 1 0 C1RXF3SID 044C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx / 8 C1RXF3EID 044E EID<15:8> EID<7:0> xxxx 1 4 C1RXF4SID 0450 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx a C1RXF4EID 0452 EID<15:8> EID<7:0> xxxx n d C1RXF5SID 0454 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx P C1RXF5EID 0456 EID<15:8> EID<7:0> xxxx IC C1RXF6SID 0458 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 2 4 C1RXF6EID 045A EID<15:8> EID<7:0> xxxx E C1RXF7SID 045C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx P X C1RXF7EID 045E EID<15:8> EID<7:0> xxxx X C1RXF8SID 0460 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X ( C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx G P DS C1RXF9SID 0464 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx /G 70 C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx U 6 1 C1RXF10SID 0468 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx ) 6 8 G-p C1RXF10EID 046A EID<15:8> EID<7:0> xxxx 10 ag C1RXF11SID 046C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx /8 e 91 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 14

D TABLE 4-30: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 (CONTINUED) d S s 70 All P 61 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p C1RXF11EID 046E EID<15:8> EID<7:0> xxxx 3 a E g C1RXF12SID 0470 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx e P 9 C1RXF12EID 0472 EID<15:8> EID<7:0> xxxx X 2 X C1RXF13SID 0474 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C1RXF13EID 0476 EID<15:8> EID<7:0> xxxx ( G C1RXF14SID 0478 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx P C1RXF14EID 047A EID<15:8> EID<7:0> xxxx /M C1RXF15SID 047C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx C / C1RXF15EID 047E EID<15:8> EID<7:0> xxxx M U Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ) 8 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-31: ECAN2 REGISTER MAP WHEN WIN (C2CTRL<0>) = 0 OR 1 2 0 09 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Resets 0 1 2 C2CTRL1 0500 — — CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP — — WIN 0480 M ic C2CTRL2 0502 — — — — — — — — — — — DNCNT<4:0> 0000 d roc C2VEC 0504 — — — FILHIT<4:0> — ICODE<6:0> 0040 sP hip C2FCTRL 0506 DMABS<2:0> — — — — — — — — FSA<4:0> 0000 IC Te C2FIFO 0508 — — FBP<5:0> — — FNRB<5:0> 0000 3 c 3 hn C2INTF 050A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000 E o P log C2INTE 050C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000 X y Inc. CC22ECCFG1 005501E0 — — — TE—RRCNT<7:0—> — — — SJW<1:0> RERRCNT<7:0>BRP<5:0> 00000000 XX( G C2CFG2 0512 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000 P C2FEN1 0514 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF /M C2FMSKSEL1 0518 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000 C C2FMSKSEL2 051A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000 /M Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. U ) 8 0 6 TABLE 4-32: ECAN2 REGISTER MAP WHEN WIN (C2CTRL<0>) = 0 / 8 1 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 0 Resets / 8 1 — 0500- See Table4-31 — 4 051E a C2RXFUL1 0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 n d C2RXFUL2 0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000 P C2RXOVF1 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000 I C C2RXOVF2 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 2 4 C2TR01CON 0530 TXEN1 TXABAT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0> 0000 E C2TR23CON 0532 TXEN3 TXABAT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0> 0000 P X C2TR45CON 0534 TXEN5 TXABAT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0> 0000 X C2TR67CON 0536 TXEN7 TXABAT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0> xxxx X ( C2RXD 0540 ECAN2 Received Data Word xxxx G P D C2TXD 0542 ECAN2 Transmit Data Word xxxx S /G 7 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 93 14

D TABLE 4-33: ECAN2 REGISTER MAP WHEN WIN (C2CTRL<0>) = 1 d S s 70 All P 61 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p — 0500- See Table4-31 — 3 a 051E E g e P 9 C2BUFPNT1 0520 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 X 4 C2BUFPNT2 0522 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000 X X C2BUFPNT3 0524 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000 ( G C2BUFPNT4 0526 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000 P C2RXM0SID 0530 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx / M C2RXM0EID 0532 EID<15:8> EID<7:0> xxxx C C2RXM1SID 0534 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx /M C2RXM1EID 0536 EID<15:8> EID<7:0> xxxx U C2RXM2SID 0538 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx )8 0 C2RXM2EID 053A EID<15:8> EID<7:0> xxxx 6 C2RXF0SID 0540 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx /8 1 C2RXF0EID 0542 EID<15:8> EID<7:0> xxxx 0 / C2RXF1SID 0544 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 8 1 C2RXF1EID 0546 EID<15:8> EID<7:0> xxxx 4 C2RXF2SID 0548 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx a n C2RXF2EID 054A EID<15:8> EID<7:0> xxxx d C2RXF3SID 054C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx P I C2RXF3EID 054E EID<15:8> EID<7:0> xxxx C 2 C2RXF4SID 0550 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 4 C2RXF4EID 0552 EID<15:8> EID<7:0> xxxx E P C2RXF5SID 0554 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C2RXF5EID 0556 EID<15:8> EID<7:0> xxxx X X  C2RXF6SID 0558 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx (G 20 C2RXF6EID 055A EID<15:8> EID<7:0> xxxx P 09 C2RXF7SID 055C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx /G -2 0 C2RXF7EID 055E EID<15:8> EID<7:0> xxxx U 1 2 M C2RXF8SID 0560 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx )81 icro C2RXF8EID 0562 EID<15:8> EID<7:0> xxxx 0/ chip T CC22RRXXFF99SEIIDD 00556646 SEIIDD<<1105::38>> SID<2:0> —EID<7:0E>XIDE — EID<17:16> xxxxxxxx 814 ec C2RXF10SID 0568 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx h no C2RXF10EID 056A EID<15:8> EID<7:0> xxxx lo g C2RXF11SID 056C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx y In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-33: ECAN2 REGISTER MAP WHEN WIN (C2CTRL<0>) = 1 (CONTINUED) 2 0 09-2 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 C2RXF11EID 056E EID<15:8> EID<7:0> xxxx Mic C2RXF12SID 0570 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx d ro C2RXF12EID 0572 EID<15:8> EID<7:0> xxxx s c P hip C2RXF13SID 0574 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx IC Te C2RXF13EID 0576 EID<15:8> EID<7:0> xxxx 3 c 3 hn C2RXF14SID 0578 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx E olog C2RXF14EID 057A EID<15:8> EID<7:0> xxxx PX y Inc CC22RRXXFF1155SEIIDD 005577CE SEIIDD<<1105::38>> SID<2:0> —EID<7:0E>XIDE — EID<17:16> xxxxxxxx XX . ( Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G P / M C / M U ) 8 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 95 14

D TABLE 4-34: PARALLEL MASTER/SLAVE PORT REGISTER MAP d S s 70616 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC G 3 -p PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PTBEEN PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P BEP WRSP RDSP 0000 3 a E ge PMMODE 0602 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000 P 96 PMADDR(1) 0604 CS2 CS1 Parallel Port Address (ADDR<13:0>) 0000 X X PMDOUT1(1) 0604 Parallel Port Data Out Register 1 (Buffers Level 0 and 1) 0000 X PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers Level 2 and 3) 0000 (G PMDIN1 0608 Parallel Port Data In Register 1 (Buffers Level 0 and 1) 0000 P / PMDIN2 060A Parallel Port Data In Register 2 (Buffers Level 2 and 3) 0000 M C PMAEN 060C PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 / M PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F U Legend: — = unimplemented, read as ‘0’. Shaded bits are not used in the operation of the PMP module. ) Note 1: PMADDR and PMDOUT1 are the same physical register, but are defined differently depending on the module’s operating mode. 8 0 6 TABLE 4-35: CRC REGISTER MAP /8 1 All 0 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 / Resets 8 1 CRCCON1 0640 CRCEN — CSIDL VWORD<4:0> CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0000 4 a CRCCON2 0642 — — — DWIDTH<4:0> — — — PLEN<4:0> 0000 n CRCXORL 0644 X<15:1> — 0000 d P CRCXORH 0646 X<31:16> 0000 I C CRCDATL 0648 CRC Data Input Low Word 0000 2 CRCDATH 064A CRC Data Input High Word 0000 4 E CRCWDATL 064C CRC Result Low Word 0000 P CRCWDATH 064E CRC Result High Word 0000 X X Legend: — = unimplemented, read as ‘0’. Shaded bits are not used in the operation of the programmable CRC module. X  (G 2 0 TABLE 4-36: REAL-TIME CLOCK AND CALENDAR REGISTER MAP P 09 /G -20 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All U 1 Resets 2 Microc AALLRCMFGVRALPT 00662202 ALRMEN CHIME AMASK<3:0> Alarm ValueA LRReMgisPtTeRr W<1in:0d>ow based on ALRMPTR<1:0> ARPT<7:0> x0x0x0x0 )810/8 hip RTCVAL 0624 RTCC Value Register Window based on RTCPTR<1:0> xxxx 1 T 4 e RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR<1:0> CAL<7:0> 0000 c hn Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. o lo g y In c .

 TABLE 4-37: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 20 DEVICES ONLY 0 9 -2 File All 01 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 2 Mic RPOR0 0680 — — RP65R<5:0> — — RP64R<5:0> 0000 d ro RPOR1 0682 — — RP67R<5:0> — — RP66R<5:0> 0000 s c P hip RPOR2 0684 — — RP69R<5:0> — — RP68R<5:0> 0000 IC Te RPOR3 0686 — — RP71R<5:0> — — RP70R<5:0> 0000 3 c 3 hn RPOR4 0688 — — RP80R<5:0> — — RP79R<5:0> 0000 E olog RPOR5 068A — — RP84R<5:0> — — RP82R<5:0> 0000 PX y Inc RRPPOORR67 006688CE —— —— RRPP8977RR<<55::00>> —— —— RRPP8956RR<<55::00>> 00000000 XX . ( RPOR8 0690 — — RP99R<5:0> — — RP98R<5:0> 0000 G P RPOR9 0692 — — RP101R<5:0> — — RP100R<5:0> 0000 / M RPOR11 0696 — — RP108R<5:0> — — RP104R<5:0> 0000 C RPOR12 0698 — — RP112R<5:0> — — RP109R<5:0> 0000 / M RPOR13 069A — — RP118R<5:0> — — RP113R<5:0> 0000 U RPOR14 069C — — RP125R<5:0> — — RP120R<5:0> 0000 )8 RPOR15 069E — — RP127R<5:0> — — RP126R<5:0> 0000 0 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X ( G P D S /G 7 0 U 6 1 ) 6 8 G 1 -p 0 ag /8 e 97 14

D TABLE 4-38: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY d S s 70 File All P 61 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p RPOR0 0680 — — RP65R<5:0> — — RP64R<5:0> 0000 3 a E g RPOR1 0682 — — RP67R<5:0> — — RP66R<5:0> 0000 e P 9 RPOR2 0684 — — RP69R<5:0> — — RP68R<5:0> 0000 X 8 X RPOR3 0686 — — RP71R<5:0> — — RP70R<5:0> 0000 X RPOR4 0688 — — RP80R<5:0> — — — — — — — — 0000 ( G RPOR5 068A — — RP84R<5:0> — — RP82R<5:0> 0000 P RPOR6 068C — — RP87R<5:0> — — RP85R<5:0> 0000 /M RPOR7 068E — — RP97R<5:0> — — RP96R<5:0> 0000 C / RPOR8 0690 — — RP99R<5:0> — — — — — — — — 0000 M U RPOR9 0692 — — RP101R<5:0> — — RP100R<5:0> 0000 ) RPOR13 069A — — RP118R<5:0> — — — — — — — — 0000 8 0 RPOR14 069C — — — — — — — — — — RP120R<5:0> 0000 6 / 8 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 0 / 8 1 4 TABLE 4-39: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXX(GP/MC/MU)806 AND PIC24EPXXXGP806 a DEVICES ONLY n d File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All P Name Resets I C RPOR0 0680 — — RP65R<5:0> — — RP64R<5:0> 0000 2 4 RPOR1 0682 — — RP67R<5:0> — — RP66R<5:0> 0000 E P RPOR2 0684 — — RP69R<5:0> — — RP68R<5:0> 0000 X RPOR3 0686 — — RP71R<5:0> — — RP70R<5:0> 0000 X X RPOR4 0688 — — RP80R<5:0> — — — — — — — — 0000  (G 2 RPOR5 068A — — RP84R<5:0> — — RP82R<5:0> 0000 0 P 09 RPOR6 068C — — RP87R<5:0> — — RP85R<5:0> 0000 /G -20 RPOR7 068E — — RP97R<5:0> — — RP96R<5:0> 0000 U 1 2 Microc RRRPPPOOORRR8910 000666999024 ——— ——— — — R—RPP19091RR<<55::0—0>> — — ——— ——— RRRPPP11900802RRR<<<555:::000>>> 000000000000 )810/8 hip RPOR13 069A — — RP118R<5:0> — — — — — — — — 0000 1 T 4 e RPOR14 069C — — — — — — — — — — RP120R<5:0> 0000 c h n Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. o lo g y In c .

 TABLE 4-40: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY 2 0 09 File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Name Resets 0 1 2 RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 M ic RPINR1 06A2 — INT3R<6:0> — INT2R<6:0> 0000 d roc RPINR2 06A4 — — — — — — — — — INT4R<6:0> 0000 sP hip RPINR3 06A6 — T3CKR<6:0> — T2CKR<6:0> 0000 IC Te RPINR4 06A8 — T5CKR<6:0> — T4CKR<6:0> 0000 3 c 3 hn RPINR5 06AA — T7CKR<6:0> — T6CKR<6:0> 0000 E o P log RPINR6 06AC — T9CKR<6:0> — T8CKR<6:0> 0000 X y Inc. RRPPIINNRR87 0066ABE0 —— IICC24RR<<66::00>> —— IICC13RR<<66::00>> 00000000 XX( G RPINR9 06B2 — IC6R<6:0> — IC5R<6:0> 0000 P RPINR10 06B4 — IC8R<6:0> — IC7R<6:0> 0000 /M RPINR11 06B6 — OCFBR<6:0> — OCFAR<6:0> 0000 C RPINR12 06B8 — FLT2R<6:0> — FLT1R<6:0> 0000 /M RPINR13 06BA — FLT4R<6:0> — FLT3R<6:0> 0000 U ) RPINR14 06BC — QEB1R<6:0> — QEA1R<6:0> 0000 8 0 RPINR15 06BE — HOME1R<6:0> — INDX1R<6:0> 0000 6 / RPINR16 06C0 — QEB2R<6:0> — QEA2R<6:0> 0000 8 1 RPINR17 06C2 — HOME2R<6:0> — INDX2R<6:0> 0000 0 / RPINR18 06C4 — U1CTSR<6:0> — U1RXR<6:0> 0000 8 1 RPINR19 06C6 — U2CTSR<6:0> — U2RXR<6:0> 0000 4 RPINR20 06C8 — SCK1R<6:0> — SDI1R<6:0> 0000 a n RPINR21 06CA — — — — — — — — — SS1R<6:0> 0000 d RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 P I RPINR24 06D0 — CSCKR<6:0> — CSDIR<6:0> 0000 C 2 RPINR25 06D2 — — — — — — — — — COFSR<6:0> 0000 4 E RPINR26 06D4 — C2RXR<6:0> — C1RXR<6:0> 0000 P RPINR27 06D6 — U3CTSR<6:0> — U3RXR<6:0> 0000 X X RPINR28 06D8 — U4CTSR<6:0> — U4RXR<6:0> 0000 X RPINR29 06DA — SCK3R<6:0> — SDI3R<6:0> 0000 ( G RPINR30 06DC — — — — — — — — — SS3R<6:0> 0000 P D S RPINR31 06DE — SCK4R<6:0> — SDI4R<6:0> 0000 /G 7 06 RPINR32 06E0 — — — — — — — — — SS4R<6:0> 0000 U 1 ) 6G RPINR33 06E2 — IC10R<6:0> — IC9R<6:0> 0000 81 -p RPINR34 06E4 — IC12R<6:0> — IC11R<6:0> 0000 0 age 99 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /814

D TABLE 4-40: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY (CONTINUED) d S s 70 File All P 61 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p RPINR35 06E6 — IC14R<6:0> — IC13R<6:0> 0000 3 a E g RPINR36 06E8 — IC16R<6:0> — IC15R<6:0> 0000 e P 1 RPINR37 06EA — SYNCI1R<6:0> — OCFCR<6:0> 0000 X 0 0 X RPINR38 06EC — DTCMP1R<6:0> — SYNCI2R<6:0> 0000 X RPINR39 06EE — DTCMP3R<6:0> — DTCMP2R<6:0> 0000 ( G RPINR40 06F0 — DTCMP5R<6:0> — DTCMP4R<6:0> 0000 P RPINR41 06F2 — DTCMP7R<6:0> — DTCMP6R<6:0> 0000 /M RPINR42 06F4 — FLT6R<6:0> — FLT5R<6:0> 0000 C / RPINR43 06F6 — — — — — — — — — FLT7R<6:0> 0000 M U Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ) 8 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-41: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY 2 0 09 File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Name Resets 0 1 2 RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 M ic RPINR1 06A2 — INT3R<6:0> — INT2R<6:0> 0000 d roc RPINR2 06A4 — — — — — — — — — INT4R<6:0> 0000 sP hip RPINR3 06A6 — T3CKR<6:0> — T2CKR<6:0> 0000 IC Te RPINR4 06A8 — T5CKR<6:0> — T4CKR<6:0> 0000 3 c 3 hn RPINR5 06AA — T7CKR<6:0> — T6CKR<6:0> 0000 E o P log RPINR6 06AC — T9CKR<6:0> — T8CKR<6:0> 0000 X y Inc. RRPPIINNRR78 0066ABE0 —— IICC24RR<<66::00>> —— IICC13RR<<66::00>> 00000000 XX( G RPINR9 06B2 — IC6R<6:0> — IC5R<6:0> 0000 P RPINR10 06B4 — IC8R<6:0> — IC7R<6:0> 0000 /M RPINR11 06B6 — OCFBR<6:0> — OCFAR<6:0> 0000 C RPINR12 06B8 — FLT2R<6:0> — FLT1R<6:0> 0000 /M RPINR13 06BA — FLT4R<6:0> — FLT3R<6:0> 0000 U ) RPINR14 06BC — QEB1R<6:0> — QEA1R<6:0> 0000 8 0 RPINR15 06BE — HOME1R<6:0> — INDX1R<6:0> 0000 6 / RPINR16 06C0 — QEB2R<6:0> — QEA2R<6:0> 0000 8 1 RPINR17 06C2 — HOME2R<6:0> — INDX2R<6:0> 0000 0 / RPINR18 06C4 — U1CTSR<6:0> — U1RXR<6:0> 0000 8 1 RPINR19 06C6 — U2CTSR<6:0> — U2RXR<6:0> 0000 4 RPINR20 06C8 — SCK1R<6:0> — SDI1R<6:0> 0000 a n RPINR21 06CA — — — — — — — — — SS1R<6:0> 0000 d RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 P I RPINR24 06D0 — CSCKR<6:0> — CSDIR<6:0> 0000 C 2 RPINR25 06D2 — — — — — — — — — COFSINR<6:0> 0000 4 E RPINR26 06D4 — C2RXR<6:0> — C1RXR<6:0> 0000 P RPINR27 06D6 — U3CTSR<6:0> — U3RXR<6:0> 0000 X X RPINR28 06D8 — U4CTSR<6:0> — U4RXR<6:0> 0000 X RPINR29 06DA — SCK3R<6:0> — SDI3R<6:0> 0000 ( G D RPINR30 06DC — — — — — — — — — SS3R<6:0> 0000 P S7 RPINR31 06DE — SCK4R<6:0> — SDI4R<6:0> 0000 /G 0 61 RPINR32 06E0 — — — — — — — — — SS4R<6:0> 0000 U 6 ) G RPINR33 06E2 — IC10R<6:0> — IC9R<6:0> 0000 8 -p 1 a RPINR34 06E4 — IC12R<6:0> — IC11R<6:0> 0000 0 ge 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /81 01 4

D TABLE 4-41: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY (CONTINUED) d S s 70 File All P 61 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p RPINR35 06E6 — IC14R<6:0> — IC13R<6:0> 0000 3 a E g RPINR36 06E8 — IC16R<6:0> — IC15R<6:0> 0000 e P 1 RPINR37 06EA — SYNCI1R<6:0> — OCFCR<6:0> 0000 X 0 2 X RPINR38 06EC — DTCMP1R<6:0> — SYNCI2R<6:0> 0000 X RPINR39 06EE — DTCMP3R<6:0> — DTCMP2R<6:0> 0000 ( G RPINR40 06F0 — DTCMP5R<6:0> — DTCMP4R<6:0> 0000 P RPINR41 06F2 — — — — — — — — — DTCMP6R<6:0> 0000 /M RPINR42 06F4 — FLT6R<6:0> — FLT5R<6:0> 0000 C / RPINR43 06F6 — — — — — — — — — FLT7R<6:0> 0000 M U Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ) 8 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-42: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806 DEVICES ONLY 2 0 09 File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Name Resets 0 1 2 RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 M ic RPINR1 06A2 — INT3R<6:0> — INT2R<6:0> 0000 d roc RPINR2 06A4 — — — — — — — — — INT4R<6:0> 0000 sP hip RPINR3 06A6 — T3CKR<6:0> — T2CKR<6:0> 0000 IC Te RPINR4 06A8 — T5CKR<6:0> — T4CKR<6:0> 0000 3 c 3 hn RPINR5 06AA — T7CKR<6:0> — T6CKR<6:0> 0000 E o P log RPINR6 06AC — T9CKR<6:0> — T8CKR<6:0> 0000 X y Inc. RRPPIINNRR78 0066ABE0 —— IICC24RR<<66::00>> —— IICC13RR<<66::00>> 00000000 XX( G RPINR9 06B2 — IC6R<6:0> — IC5R<6:0> 0000 P RPINR10 06B4 — IC8R<6:0> — IC7R<6:0> 0000 /M RPINR11 06B6 — OCFBR<6:0> — OCFAR<6:0> 0000 C RPINR12 06B8 — FLT2R<6:0> — FLT1R<6:0> 0000 /M RPINR13 06BA — FLT4R<6:0> — FLT3R<6:0> 0000 U ) RPINR14 06BC — QEB1R<6:0> — QEA1R<6:0> 0000 8 0 RPINR15 06BE — HOME1R<6:0> — INDX1R<6:0> 0000 6 / RPINR16 06C0 — QEB2R<6:0> — QEA2R<6:0> 0000 8 1 RPINR17 06C2 — HOME2R<6:0> — INDX2R<6:0> 0000 0 / RPINR18 06C4 — U1CTSR<6:0> — U1RXR<6:0> 0000 8 1 RPINR19 06C6 — U2CTSR<6:0> — U2RXR<6:0> 0000 4 RPINR20 06C8 — SCK1R<6:0> — SDI1R<6:0> 0000 a n RPINR21 06CA — — — — — — — — — SS1R<6:0> 0000 d RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 P I RPINR24 06D0 — CSCKR<6:0> — CSDIR<6:0> 0000 C 2 RPINR25 06D2 — — — — — — — — — COFSINR<6:0> 0000 4 E RPINR26 06D4 — C2RXR<6:0> — C1RXR<6:0> 0000 P RPINR27 06D6 — U3CTSR<6:0> — U3RXR<6:0> 0000 X X RPINR28 06D8 — U4CTSR<6:0> — U4RXR<6:0> 0000 X RPINR29 06DA — SCK3R<6:0> — SDI3R<6:0> 0000 ( G D RPINR30 06DC — — — — — — — — — SS3R<6:0> 0000 P S7 RPINR31 06DE — SCK4R<6:0> — SDI4R<6:0> 0000 /G 0 61 RPINR32 06E0 — — — — — — — — — SS4R<6:0> 0000 U 6 ) G RPINR33 06E2 — IC10R<6:0> — IC9R<6:0> 0000 8 -p 1 a RPINR34 06E4 — IC12R<6:0> — IC11R<6:0> 0000 0 ge 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /81 03 4

D TABLE 4-42: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXX(MC/MU)806 DEVICES ONLY (CONTINUED) d S s 70 File All P 61 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p RPINR35 06E6 — IC14R<6:0> — IC13R<6:0> 0000 3 a E g RPINR36 06E8 — IC16R<6:0> — IC15R<6:0> 0000 e P 1 RPINR37 06EA — SYNCI1R<6:0> — OCFCR<6:0> 0000 X 0 4 X RPINR38 06EC — DTCMP1R<6:0> — SYNCI2R<6:0> 0000 X RPINR39 06EE — DTCMP3R<6:0> — DTCMP2R<6:0> 0000 ( G RPINR40 06F0 — — — — — — — — — DTCMP4R<6:0> 0000 P RPINR42 06F4 — FLT6R<6:0> — FLT5R<6:0> 0000 /M RPINR43 06F6 — — — — — — — — — FLT7R<6:0> 0000 C / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M U ) 8 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-43: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY 2 0 09 File All -201 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resset 2 Mic RPINR0 06A0 — INT1R<6:0> — — — — — — — — 0000 d ro RPINR1 06A2 — INT3R<6:0> — INT2R<6:0> 0000 s c P hip RPINR2 06A4 — — — — — — — — — INT4R<6:0> 0000 IC Te RPINR3 06A6 — T3CKR<6:0> — T2CKR<6:0> 0000 3 c 3 hn RPINR4 06A8 — T5CKR<6:0> — T4CKR<6:0> 0000 E olog RPINR5 06AA — T7CKR<6:0> — T6CKR<6:0> 0000 PX y Inc RRPPIINNRR76 0066AACE —— TI9CC2KRR<<66:0:0>> —— TI8CC1KRR<<66:0:0>> 00000000 XX . ( RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000 G P RPINR9 06B2 — IC6R<6:0> — IC5R<6:0> 0000 / M RPINR10 06B4 — IC8R<6:0> — IC7R<6:0> 0000 C RPINR11 06B6 — OCFBR<6:0> — OCFAR<6:0> 0000 / M RPINR18 06C4 — U1CTSR<6:0> — U1RXR<6:0> 0000 U RPINR19 06C6 — U2CTSR<6:0> — U2RXR<6:0> 0000 ) 8 RPINR20 06C8 — SCK1R<6:0> — SDI1R<6:0> 0000 0 6 RPINR21 06CA — — — — — — — — — SS1R<6:0> 0000 /8 RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000 1 0 RPINR26 06D4 — C2RXR<6:0> — C1RXR<6:0> 0000 /8 RPINR27 06D6 — U3CTSR<6:0> — U3RXR<6:0> 0000 1 4 RPINR28 06D8 — U4CTSR<6:0> — U4RXR<6:0> 0000 a n RPINR29 06DA — SCK3R<6:0> — SDI3R<6:0> 0000 d RPINR30 06DC — — — — — — — — — SS3R<6:0> 0000 P RPINR31 06DE — SCK4R<6:0> — SDI4R<6:0> 0000 IC RPINR32 06E0 — — — — — — — — — SS4R<6:0> 0000 2 4 RPINR33 06E2 — IC10R<6:0> — IC9R<6:0> 0000 E P RPINR34 06E4 — IC12R<6:0> — IC11R<6:0> 0000 X RPINR35 06E6 — IC14R<6:0> — IC13R<6:0> 0000 X X RPINR36 06E8 — IC16R<6:0> — IC15R<6:0> 0000 ( G RPINR37 06EA — — — — — — — — — OCFCR<6:0> 0000 D P S Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 7 G 0 6 U 1 6 ) G 8 -p 1 a 0 ge /8 1 1 05 4

D TABLE 4-44: REFERENCE CLOCK REGISTER MAP d S s 70616 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC G 3 -p REFOCON 074E ROON — ROSSLP ROSEL RODIV<3:0> — — — — — — — — 0000 3 a E ge Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P 1 X 0 6 X X TABLE 4-45: NVM REGISTER MAP ( G All P File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets /M NVMCON 0728 WR WREN WRERR NVMSIDL — — — — — — — — NVMOP<3:0> 0000 C / NVMADR 072A NVMADR<15:0> 0000 M U NVMADRU 072C — — — — — — — — NVMADR<23:16> 0000 ) 8 NVMKEY 072E — — — — — — — — NVMKEY<7:0> 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 / 8 1 0 TABLE 4-46: SYSTEM CONTROL REGISTER MAP /8 1 4 All File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets a n RCON 0740 TRAPR IOPUWR — — VREGSF — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1 d P OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN Note 2 I C CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 3040 2 PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030 4 E OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 P ACLKCON3 0758 ENAPLL — SELACLK AOSCMD<1:0> ASRCSEL FRCSEL — APLLPOST2<2:0> — — APLLPRE<2:0> 0000 X X ACLKDIV3 075A — — — — — — — — — — — — — APLLDIV<2:0> 0000 X  Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. (G 20 Note 1: RCON register Reset values are dependent on the type of Reset. P 09 2: OSCCON register Reset values are dependent on the Configuration Fuses and by the type of Reset. /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-47: PMD REGISTER MAP FOR dsPIC33EPXXXMU814 DEVICES ONLY 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000 Mic PMD2 0762 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 d ro PMD3 0764 T9MD T8MD T7MD T6MD — CMPMD RTCCMD PMPMD CRCMD — QEI2MD — U3MD — I2C2MD AD2MD 0000 s c P hip PMD4 0766 — — — — — — — — — — U4MD — REFOMD — — USB1MD 0000 IC Te PMD5 0768 IC16MD IC15MD IC14MD IC13MD IC12MD IC11MD IC10MD IC9MD OC16MD OC15MD OC14MD OC13MD OC12MD OC11MD OC10MD OC9MD 0000 3 c 3 hn PMD6 076A — PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — SPI4MD SPI3MD 0000 E olog — — — — — — — — DMA12MD DMA8MD DMA4MD DMA0MD — — — — 0000 PX y Inc PMD7 076C —— —— —— —— —— —— —— —— DDMMAA1143MMDD DDMMAA190MMDD DDMMAA56MMDD DDMMAA12MMDD —— —— —— —— 00000000 XX . ( — — — — — — — — — DMA11MD DMA7MD DMA3MD — — — — 0000 G P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / M C / TABLE 4-48: PMD REGISTER MAP FOR dsPIC33EPXXXMU810 DEVICES ONLY M U File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All )8 Name Resets 0 6 PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000 /8 PMD2 0762 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 1 0 PMD3 0764 T9MD T8MD T7MD T6MD — CMPMD RTCCMD PMPMD CRCMD — QEI2MD — U3MD — I2C2MD AD2MD 0000 /8 PMD4 0766 — — — — — — — — — — U4MD — REFOMD — — USB1MD 0000 1 4 PMD5 0768 IC16MD IC15MD IC14MD IC13MD IC12MD IC11MD IC10MD IC9MD OC16MD OC15MD OC14MD OC13MD OC12MD OC11MD OC10MD OC9MD 0000 a n PMD6 076A — — PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — SPI4MD SPI3MD 0000 d — — — — — — — — DMA12MD DMA8MD DMA4MD DMA0MD — — — — 0000 P — — — — — — — — DMA13MD DMA9MD DMA5MD DMA1MD — — — — 0000 IC PMD7 076C — — — — — — — — DMA14MD DMA10MD DMA6MD DMA2MD — — — — 0000 2 4 — — — — — — — — — DMA11MD DMA7MD DMA3MD — — — — 0000 E P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X X X ( G D P S / 7 G 0 6 U 1 6 ) G 8 -p 1 a 0 ge /8 1 1 07 4

D TABLE 4-49: PMD REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY d S s 70 File All P 61 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000 3 a E g PMD2 0762 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 e P 1 PMD3 0764 T9MD T8MD T7MD T6MD — CMPMD RTCCMD PMPMD CRCMD — QEI2MD — U3MD — I2C2MD AD2MD 0000 X 0 8 X PMD4 0766 — — — — — — — — — — U4MD — REFOMD — — USB1MD 0000 X PMD5 0768 IC16MD IC15MD IC14MD IC13MD IC12MD IC11MD IC10MD IC9MD OC16MD OC15MD OC14MD OC13MD OC12MD OC11MD OC10MD OC9MD 0000 ( G PMD6 076A — — — — PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — SPI4MD SPI3MD 0000 P — — — — — — — — DMA12MD DMA8MD DMA4MD DMA0MD — — — — 0000 /M — — — — — — — — DMA13MD DMA9MD DMA5MD DMA1MD — — — — 0000 C PMD7 076C / — — — — — — — — DMA14MD DMA10MD DMA6MD DMA2MD — — — — 0000 M U — — — — — — — — — DMA11MD DMA7MD DMA3MD — — — — 0000 ) Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 8 0 6 / 8 1 TABLE 4-50: PMD REGISTER MAP FOR dsPIC33EPXXXMC806 DEVICES ONLY 0 / 8 File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 1 Name Resets 4 a PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000 n PMD2 0762 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 d PMD3 0764 T9MD T8MD T7MD T6MD — CMPMD RTCCMD PMPMD CRCMD — QEI2MD — U3MD — I2C2MD AD2MD 0000 P I C PMD4 0766 — — — — — — — — — — U4MD — REFOMD — — — 0000 2 PMD5 0768 IC16MD IC15MD IC14MD IC13MD IC12MD IC11MD IC10MD IC9MD OC16MD OC15MD OC14MD OC13MD OC12MD OC11MD OC10MD OC9MD 0000 4 E PMD6 076A — — — — PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — SPI4MD SPI3MD 0000 P — — — — — — — — DMA12MD DMA8MD DMA4MD DMA0MD — — — — 0000 X X — — — — — — — — DMA13MD DMA9MD DMA5MD DMA1MD — — — — 0000 X PMD7 076C  — — — — — — — — DMA14MD DMA10MD DMA6MD DMA2MD — — — — 0000 (G 2 0 — — — — — — — — — DMA11MD DMA7MD DMA3MD — — — — 0000 P 09-2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /G 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-51: PMD REGISTER MAP FOR dsPIC33EPXXXGP8XX AND PIC24EPXXXGP8XX DEVICES ONLY 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 PMD1 0760 T5MD T4MD T3MD T2MD T1MD — — DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000 Mic PMD2 0762 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 d ro PMD3 0764 T9MD T8MD T7MD T6MD — CMPMD RTCCMD PMPMD CRCMD — — — U3MD — I2C2MD AD2MD 0000 s c P hip PMD4 0766 — — — — — — — — — — U4MD — REFOMD — — — 0000 IC Te PMD5 0768 IC16MD IC15MD IC14MD IC13MD IC12MD IC11MD IC10MD IC9MD OC16MD OC15MD OC14MD OC13MD OC12MD OC11MD OC10MD OC9MD 0000 3 c 3 hn PMD6 076A — — — — — — — — — — — — — — SPI4MD SPI3MD 0000 E olog — — — — — — — — DMA12MD DMA8MD DMA4MD DMA0MD — — — — 0000 PX y Inc PMD7 076C —— —— —— —— —— —— —— —— DDMMAA1134MMDD DDMMAA190MMDD DDMMAA56MMDD DDMMAA12MMDD —— —— —— —— 00000000 XX . ( — — — — — — — — — DMA11MD DMA7MD DMA3MD — — — — 0000 G P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / M C / TABLE 4-52: PMD REGISTER MAP FOR PIC24EPXXXGU810/814 DEVICES ONLY M U File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All )8 Name Resets 0 6 PMD1 0760 T5MD T4MD T3MD T2MD T1MD — — DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000 /8 PMD2 0762 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 1 0 PMD3 0764 T9MD T8MD T7MD T6MD — CMPMD RTCCMD PMPMD CRCMD — — — U3MD — I2C2MD AD2MD 0000 /8 PMD4 0766 — — — — — — — — — — U4MD — REFOMD — — USB1MD 0000 1 4 PMD5 0768 IC16MD IC15MD IC14MD IC13MD IC12MD IC11MD IC10MD IC9MD OC16MD OC15MD OC14MD OC13MD OC12MD OC11MD OC10MD OC9MD 0000 a n PMD6 076A — — — — — — — — — — — — — — SPI4MD SPI3MD 0000 d — — — — — — — — DMA12MD DMA8MD DMA4MD DMA0MD — — — — 0000 P — — — — — — — — DMA13MD DMA9MD DMA5MD DMA1MD — — — — 0000 IC PMD7 076C — — — — — — — — DMA14MD DMA10MD DMA6MD DMA2MD — — — — 0000 2 4 — — — — — — — — — DMA11MD DMA7MD DMA3MD — — — — 0000 E P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X X X ( G D P S / 7 G 0 6 U 1 6 ) G 8 -p 1 a 0 ge /8 1 1 09 4

D TABLE 4-53: COMPARATOR REGISTER MAP d S s 70 All P 61 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p CMSTAT 0A80 CMSIDL — — — — C3EVT C2EVT C1EVT — — — — — C3OUT C2OUT C1OUT 0000 3 a E g CVRCON 0A82 — — — — — VREFSEL BGSEL<1:0> CVREN CVROE CVRR CVRSS CVR<3:0> 0000 e P 1 CM1CON 0A84 CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000 X 1 0 X CM1MSKSRC 0A86 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000 X CM1MSKCON 0A88 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 ( G CM1FLTR 0A8A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000 P CM2CON 0A8C CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000 /M CM2MSKSRC 0A8E — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000 C / CM2MSKCON 0A90 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 M U CM2FLTR 0A92 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000 ) CM3CON 0A94 CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF — — CCH<1:0> 0000 8 0 CM3MSKSRC 0A96 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000 6 / 8 CM3MSKCON 0A98 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 1 CM3FLTR 0A9A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000 0 / 8 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 4 a n d P I C 2 4 E P X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-54: DMAC REGISTER MAP 2 0 09 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Resets 0 1 2 DMA0CON 0B00 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 M ic DMA0REQ 0B02 FORCE — — — — — — — IRQSEL<7:0> 00FF d roc DMA0STAL 0B04 STA<15:0> 0000 sP hip DMA0STAH 0B06 — — — — — — — — STA<23:16> 0000 IC Te DMA0STBL 0B08 STB<15:0> 0000 3 c 3 hn DMA0STBH 0B0A — — — — — — — — STB<23:16> 0000 E o P log DMA0PAD 0B0C PAD<15:0> 0000 X y Inc. DDMMAA01CCNOTN 00BB01E0 CH—EN S—IZE DIR HALF NULLW — — — C—NT<13:0>— AMODE<1:0> — — MODE<1:0> 00000000 XX( G DMA1REQ 0B12 FORCE — — — — — — — IRQSEL<7:0> 00FF P DMA1STAL 0B14 STA<15:0> 0000 /M DMA1STAH 0B16 — — — — — — — — STA<23:16> 0000 C DMA1STBL 0B18 STB<15:0> 0000 /M DMA1STBH 0B1A — — — — — — — — STB<23:16> 0000 U ) DMA1PAD 0B1C PAD<15:0> 0000 8 0 DMA1CNT 0B1E — — CNT<13:0> 0000 6 / DMA2CON 0B20 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 8 1 DMA2REQ 0B22 FORCE — — — — — — — IRQSEL<7:0> 00FF 0 / DMA2STAL 0B24 STA<15:0> 0000 8 1 DMA2STAH 0B26 — — — — — — — — STA<23:16> 0000 4 DMA2STBL 0B28 STB<15:0> 0000 a n DMA2STBH 0B2A — — — — — — — — STB<23:16> 0000 d DMA2PAD 0B2C PAD<15:0> 0000 P I DMA2CNT 0B2E — — CNT<13:0> 0000 C 2 DMA2CON 0B30 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 4 E DMA3REQ 0B32 FORCE — — — — — — — IRQSEL<7:0> 00FF P DMA3STAL 0B34 STA<15:0> 0000 X X DMA3STAH 0B36 — — — — — — — — STA<23:16> 0000 X DMA3STBL 0B38 STB<15:0> 0000 ( G D DMA3STBH 0B3A — — — — — — — — STB<23:16> 0000 P S7 DMA3PAD 0B3C PAD<15:0> 0000 /G 0 61 DMA3CNT 0B3E — — CNT<13:0> 0000 U 6 ) G DMA4CON 0B40 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 8 -p 1 a DMA4REQ 0B42 FORCE — — — — — — — IRQSEL<7:0> 00FF 0 ge 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /81 11 4

D TABLE 4-54: DMAC REGISTER MAP (CONTINUED) d S s 70 All P 61 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p DMA4STAL 0B44 STA<15:0> 0000 3 a E g DMA4STAH 0B46 — — — — — — — — STA<23:16> 0000 e P 1 DMA4STBL 0B48 STB<15:0> 0000 X 1 2 X DMA4STBH 0B4A — — — — — — — — STB<23:16> 0000 X DMA4PAD 0B4C PAD<15:0> 0000 ( G DMA4CNT 0B4E — — CNT<13:0> 0000 P DMA5CON 0B50 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 /M DMA5REQ 0B52 FORCE — — — — — — — IRQSEL<7:0> 00FF C / DMA5STAL 0B54 STA<15:0> 0000 M U DMA5STAH 0B56 — — — — — — — — STA<23:16> 0000 ) DMA5STBL 0B58 STB<15:0> 0000 8 0 DMA5STBH 0B5A — — — — — — — — STB<23:16> 0000 6 / 8 DMA5PAD 0B5C PAD<15:0> 0000 1 DMA5CNT 0B5E — — CNT<13:0> 0000 0 / 8 DMA6CON 0B60 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 1 DMA6REQ 0B62 FORCE — — — — — — — IRQSEL<7:0> 00FF 4 a DMA6STAL 0B64 STA<15:0> 0000 n DMA6STAH 0B66 — — — — — — — — STA<23:16> 0000 d P DMA6STBL 0B68 STB<15:0> 0000 I C DMA6STBH 0B6A — — — — — — — — STB<23:16> 0000 2 DMA6PAD 0B6C PAD<15:0> 0000 4 E DMA6CNT 0B6E — — CNT<13:0> 0000 P DMA7CON 0B70 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 X X DMA7REQ 0B72 FORCE — — — — — — — IRQSEL<7:0> 00FF X  DMA7STAL 0B74 STA<15:0> 0000 (G 2 0 DMA7STAH 0B76 — — — — — — — — STA<23:16> 0000 P 09-2 DMA7STBL 0B78 STB<15:0> 0000 /G 0 U 1 DMA7STBH 0B7A — — — — — — — — STB<23:16> 0000 2 M DMA7PAD 0B7C PAD<15:0> 0000 )81 icro DMA7CNT 0B7E — — CNT<13:0> 0000 0/ c 8 hip DMA8CON 0B80 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 1 T DMA8REQ 0B82 FORCE — — — — — — — IRQSEL<7:0> 00FF 4 e ch DMA8STAL 0B84 STA<15:0> 0000 n olo DMA8STAH 0B86 — — — — — — — — STA<23:16> 0000 gy DMA8STBL 0B88 STB<15:0> 0000 Inc Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. .

 TABLE 4-54: DMAC REGISTER MAP (CONTINUED) 2 0 09-2 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts 0 12 DMA8STBH 0B8A — — — — — — — — STB<23:16> 0000 Mic DMA8PAD 0B8C PAD<15:0> 0000 d ro DMA8CNT 0B8E — — CNT<13:0> 0000 s c P hip DMA9CON 0B90 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 IC Te DMA9REQ 0B92 FORCE — — — — — — — IRQSEL<7:0> 00FF 3 c 3 hn DMA9STAL 0B94 STA<15:0> 0000 E olog DMA9STAH 0B96 — — — — — — — — STA<23:16> 0000 PX y Inc DDMMAA99SSTTBBLH 00BB99A8 — — — — — — — S—TB<15:0> STB<23:16> 00000000 XX . ( DMA9PAD 0B9C PAD<15:0> 0000 G P DMA9CNT 0B9E — — CNT<13:0> 0000 / M DMA10CON 0BA0 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 C DMA10REQ 0BA2 FORCE — — — — — — — IRQSEL<7:0> 00FF / M DMA10STAL 0BA4 STA<15:0> 0000 U DMA10STAH 0BA6 — — — — — — — — STA<23:16> 0000 )8 DMA10STBL 0BA8 STB<15:0> 0000 0 6 DMA10STBH 0BAA — — — — — — — — STB<23:16> 0000 /8 1 DMA10PAD 0BAC PAD<15:0> 0000 0 DMA10CNT 0BAE — — CNT<13:0> 0000 /8 1 DMA11CON 0BB0 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 4 DM11AREQ 0BB2 FORCE — — — — — — — IRQSEL<7:0> 00FF a n DMA11STAL 0BB4 STA<15:0> 0000 d DMA11STAH 0BB6 — — — — — — — — STA<23:16> 0000 P DMA11STBL 0BB8 STB<15:0> 0000 IC DMA11STBH 0BBA — — — — — — — — STB<23:16> 0000 2 4 DMA11PAD 0BBC PAD<15:0> 0000 E P DMA11CNT 0BBE — — CNT<13:0> 0000 X DMA12CON 0BC0 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 X X DMA12REQ 0BC2 FORCE — — — — — — — IRQSEL<7:0> 00FF ( G DMA12STAL 0BC4 STA<15:0> 0000 D P S7 DMA12STAH 0BC6 — — — — — — — — STA<23:16> 0000 /G 0 6 DMA12STBL 0BC8 STB<15:0> 0000 U 1 6G DMA12STBH 0BCA — — — — — — — — STB<23:16> 0000 )8 -pa DMA12PAD 0BCC PAD<15:0> 0000 10 ge DMA12CNT 0BCE — — CNT<13:0> 0000 /8 1 1 13 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4

D TABLE 4-54: DMAC REGISTER MAP (CONTINUED) d S s 70 All P 61 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p DMA13CON 0BD0 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 3 a E g DMA13REQ 0BD2 FORCE — — — — — — — IRQSEL<7:0> 00FF e P 1 DMA13STAL 0BD4 STA<15:0> 0000 X 1 4 X DMA13STAH 0BD6 — — — — — — — — STA<23:16> 0000 X DMA13STBL 0BD8 STB<15:0> 0000 ( G DMA13STBH 0BDA — — — — — — — — STB<23:16> 0000 P DMA13PAD 0BDC PAD<15:0> 0000 /M DMA13CNT 0BDE — — CNT<13:0> 0000 C / DMA14CON 0BE0 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 M U DMA14REQ 0BE2 FORCE — — — — — — — IRQSEL<7:0> 00FF ) DMA14STAL 0BE4 STA<15:0> 0000 8 0 DMA14STAH 0BE6 — — — — — — — — STA<23:16> 0000 6 / 8 DMA14STBL 0BE8 STB<15:0> 0000 1 DMA14STBH 0BEA — — — — — — — — STB<23:16> 0000 0 / 8 DMA14PAD 0BEC PAD<15:0> 0000 1 DMA14CNT 0BEE — — CNT<13:0> 0000 4 a DMAPWC 0BF0 — PWCOL14 PWCOL13 PWCOL12 PWCOL11 PWCOL10 PWCOL9 PWCOL8 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 0000 n DMARQC 0BF2 — RQCOL14 RQCOL13 RQCOL12 RQCOL11 RQCOL10 RQCOL9 RQCOL8 RQCOL7 RQCOL6 RQCOL5 RQCOL4 RQCOL3 RQCOL2 RQCOL1 RQCOL0 0000 d P DMAPPS 0BF4 — PPST14 PPST13 PPST12 PPST11 PPST10 PPST9 PPST8 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0000 I C DMALCA 0BF6 — — — — — — — — — — — — LSTCH<3:0> 000F 2 DSADRL 0BF8 DSADR<15:0> 0000 4 E DSADRH 0BFA — — — — — — — — DSADR<23:16> 0000 P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-55: PORTA REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 DEVICES ONLY 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 TRISA 0E00 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF Mic PORTA 0E02 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx d ro LATA 0E04 LATA15 LATA14 — — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx s c P hip ODCA 0E06 ODCA15 ODCA14 — — — — — — — — ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 IC Te CNENA 0E08 CNIEA15 CNIEA14 — — — CNIEA10 CNIEA9 — CNIEA7 CNIEA6 CNIEA5 CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000 3 c 3 hn CNPUA 0E0A CNPUA15 CNPUA14 — — — CNPUA10 CNPUA9 — CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000 E olog CNPDA 0E0C CNPDA15 CNPDA14 — — — CNPDA10 CNPDA9 — CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000 PX y Inc ALeNgSeEnLdA: 0Ex0 =E unknow—n value on R—eset, — = —unimpleme—nted, read a—s ‘0’. ReAsNeSt vAa1lu0es aAreN sShAo9wn in h—exadecimANalS.A7 ANSA6 — — — — — — 06C0 XX . ( G TABLE 4-56: PORTB REGISTER MAP P / M File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All C Name Resets / M TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF U ) PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx 8 0 LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx 6 / ODCB 0E16 — — — — — — — — — — — — — — — — 0000 8 1 CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000 0 / CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 8 1 CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 4 ANSELB 0E1E ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9 ANSB8 ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 FFFF a n Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d P TABLE 4-57: PORTC REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 DEVICES ONLY IC 2 File All 4 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets E P TRISC 0E20 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F01E X X PORTC 0E22 RC15 RC14 RC13 RC12 — — — — — — — RC4 RC3 RC2 RC1 — xxxx X LATC 0E24 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 — xxxx (G D ODCC 0E26 — — — — — — — — — — — — — — — — 0000 P S / 7 CNENC 0E28 CNIEC15 CNIEC14 CNIEC13 CNIEC12 — — — — — — — CNIEC4 CNIEC3 CNIEC2 CNIEC1 — 0000 G 0 6 U 1 CNPUC 0E2A CNPUC15 CNPUC14 CNPUC13 CNPUC12 — — — — — — — CNPUC4 CNPUC3 CNPUC2 CNPUC1 — 0000 6 ) G CNPDC 0E2C CNPDC15 CNPDC14 CNPDC13 CNPDC12 — — — — — — — CNPDC4 CNPDC3 CNPDC2 CNPDC1 — 0000 8 -p 1 a ANSELC 0E2E — ANSC14 ANSC13 — — — — — — — — ANSC4 ANSC3 ANSC2 ANSC1 — 601E 0 ge /8 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 15 4

D TABLE 4-58: PORTC REGISTER MAP FOR dsPIC33EPXXX(GP/MC/MU)806 AND PIC24EPXXXGP806 DEVICES ONLY d S s 70 File All P 61 Name Addr, Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p TRISC 0E20 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000 3 a E g PORTC 0E22 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx e P 1 LATC 0E24 LATC15 LATC14 LATC13 LATC12 — — — — — — — — — — — — xxxx X 1 6 X ODCC 0E26 — — — — — — — — — — — — — — — — 0000 X CNENC 0E28 CNIEC15 CNIEC14 CNIEC13 CNIEC12 — — — — — — — — — — — — 0000 ( G CNPUC 0E2A CNPUC15 CNPUC14 CNPUC13 CNPUC12 — — — — — — — — — — — — 0000 P CNPDC 0E2C CNPDC15 CNPDC14 CNPDC13 CNPDC12 — — — — — — — — — — — — 0000 /M ANSELC 0E2E — ANSC14 ANSC13 — — — — — — — — — — — — — 6000 C / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M U ) TABLE 4-59: PORTD REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 DEVICES ONLY 8 0 6 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts /8 1 0 TRISD 0E30 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF / 8 PORTD 0E32 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx 1 4 LATD 0E34 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx a ODCD 0E36 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 — — ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 n d CNEND 0E38 CNIED15 CNIED14 CNIED13 CNIED12 CNIED11 CNIED10 CNIED9 CNIED8 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 0000 P CNPUD 0E3A CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000 I C CNPDD 0E3C CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000 2 4 ANSELD 0E3E — — — — — — — — ANSD7 ANSD6 — — — — — — 00C0 E Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P X X TABLE 4-60: PORTD REGISTER MAP FOR dsPIC33EPXXX(GP/MC/MU)806 AND PIC24EPXXXGP806 DEVICES ONLY X  (G 20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 09 /G -20 TRISD 0E30 — — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0FFF U 1 2 Microc PLOAODTRCDTDD 000EEE333642 ——— ——— ——— ——— OLRDATDCD1D11111 OLRDATDCD1D10100 OLRDATDCD9D99 OLRDATDCD8D88 LRA—TDD77 LRA—TDD66 OLRDATDCD5D55 OLRDATDCD4D44 OLRADTDCD3D33 OLRADTDCD2D22 OLRDATDCD1D11 OLRDATDCD0D00 xx0xx0xx0xx0 )810/8 hip CNEND 0E38 — — — — CNIED11 CNIED10 CNIED9 CNIED8 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 0000 1 T 4 e CNPUD 0E3A — — — — CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000 c hn CNPDD 0E3C — — — — CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000 o lo ANSELD 0E3E — — — — — — — — ANSD7 ANSD6 — — — — — — 00C0 g y In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-61: PORTE REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 DEVICES ONLY 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 TRISE 0E40 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF Mic PORTE 0E42 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx d ro LATE 0E44 — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx s c P hip ODCE 0E46 — — — — — — — — — — — — — — — — 0000 IC Te CNENE 0E48 — — — — — — CNIEE9 CNIEE8 CNIEE7 CNIEE6 CNIEE5 CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 0000 3 c 3 hn CNPUE 0E4A — — — — — — CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000 E olog CNPDE 0E4C — — — — — — CNPDE9 CNPDE8 CNPDE7 CNPDE6 CNPDE5 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000 PX y Inc ALeNgSeEnLdE: 0E4xE = unkn—own value o—n Reset, —— = unimplem—ented, read— as ‘0’. Rese—t values AaNreS sEh9own AinN hSeEx8adeciAmNaSl.E7 ANSE6 ANSE5 ANSE4 ANSE3 ANSE2 ANSE1 ANSE0 03FF XX . ( G TABLE 4-62: PORTE REGISTER MAP FOR dsPIC33EPXXX(GP/MC/MU)806 AND PIC24EPXXXGP806 DEVICES ONLY P / M File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All C Name Resets / M TRISE 0E40 — — — — — — — — TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF U ) PORTE 0E42 — — — — — — — — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx 8 0 LATE 0E44 — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx 6 / ODCE 0E46 — — — — — — — — — — — — — — — — 0000 8 1 CNENE 0E48 — — — — — — — — CNIEE7 CNIEE6 CNIEE5 CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 0000 0 / CNPUE 0E4A — — — — — — — — CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000 8 1 CNPDE 0E4C — — — — — — — — CNPDE7 CNPDE6 CNPDE5 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000 4 ANSELE 0E4E — — — — — — — — ANSE7 ANSE6 ANSE5 ANSE4 ANSE3 ANSE2 ANSE1 ANSE0 00FF a n Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d P TABLE 4-63: PORTF REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 DEVICES ONLY IC 2 File All 4 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets E P TRISF 0E50 — — TRISF13 TRISF12 — — — TRISF8 — — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F X X PORTF 0E52 — — RF13 RF12 — — — RF8 — — RF5 RF4 RF3 RF2 RF1 RF0 xxxx X LATF 0E54 — — LATF13 LATF12 — — — LATF8 — — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx (G D ODCF 0E56 — — ODCF13 ODCF12 — — — ODCF8 — — ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 P S / 7 CNENF 0E58 — — CNIEF13 CNIEF12 — — — CNIEF8 — — CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 0000 G 0 6 U 1 CNPUF 0E5A — — CNPUF13 CNPUF12 — — — CNPUF8 — — CNPUF5 CNPUF4 CNPUF3 CNPUF2 CNPUF1 CNPUF0 0000 6 ) G CNPDF 0E5C — — CNPDF13 CNPDF12 — — — CNPDF8 — — CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 0000 8 -p 1 a ANSELF 0E5E — — — — — — — — — — — — — — — — 0000 0 ge /8 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 17 4

D TABLE 4-64: PORTF REGISTER MAP FOR dsPIC33EPXXX(GP/MC)806 AND PIC24EPXXXGP806 DEVICES ONLY d S s 70 File All P 61 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p TRISF 0E50 — — — — — — — — — TRISG6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 003B 3 a E g PORTF 0E52 — — — — — — — — — RG6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx e P 1 LATF 0E54 — — — — — — — — — LATG6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx X 1 8 X ODCF 0E56 — — — — — — — — — ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 X CNENF 0E58 — — — — — — — — — CNIEG6 CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 0000 ( G CNPUF 0E5A — — — — — — — — — CNPUG6 CNPUF5 CNPUF4 CNPUF3 CNPUF2 CNPUF1 CNPUF0 0000 P CNPDF 0E5C — — — — — — — — — CNPDG6 CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 0000 /M ANSELF 0E5E — — — — — — — — — — — — — — — — 0000 C / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M U ) TABLE 4-65: PORTF REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY 8 0 6 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts /8 1 0 TRISF 0E50 — — — — — — — — — — TRISF5 TRISF4 TRISF3 — TRISF1 TRISF0 003B / 8 PORTF 0E52 — — — — — — — — — — RF5 RF4 RF3 — RF1 RF0 xxxx 1 4 LATF 0E54 — — — — — — — — — — LATF5 LATF4 LATF3 — LATF1 LATF0 xxxx a ODCF 0E56 — — — — — — — — — — ODCF5 ODCF4 ODCF3 — ODCF1 ODCF0 0000 n d CNENF 0E58 — — — — — — — — — — CNIEF5 CNIEF4 CNIEF3 — CNIEF1 CNIEF0 0000 P CNPUF 0E5A — — — — — — — — — — CNPUF5 CNPUF4 CNPUF3 — CNPUF1 CNPUF0 0000 I C CNPDF 0E5C — — — — — — — — — — CNPDF5 CNPDF4 CNPDF3 — CNPDF1 CNPDF0 0000 2 4 ANSELF 0E5E — — — — — — — — — — — — — — — — 0000 E Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P X X TABLE 4-66: PORTG REGISTER MAP FOR dsPIC33EPXXXMU810/814 AND PIC24EPXXXGU810/814 DEVICES ONLY X  (G 20 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 09 /G -20 TRISG 0E60 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — — — TRISG1 TRISG0 F3C3 U 12 Microc PLOAODTRCGTGG 000EEE666624 OLRDATGCGG115155 OLRDATGCGG114144 OLRDATGCGG113133 OLRDATGCGG112122 ——— ——— LRA—TGG99 LRA—TGG88 LRA—TGG77 LRA—TGG66 ——— ——— RG——3(1) RG——2(1) OLRDATGCGG111 OLRDATGCGG000 xx0xx0xx0x0x )810/8 hip CNENG 0E68 CNIEG15 CNIEG14 CNIEG13 CNIEG12 — — CNIEG9 CNIEG8 CNIEG7 CNIEG6 — — CNIEG3(1) CNIEG2(1) CNIEG1 CNIEG0 0000 1 T 4 e CNPUG 0E6A CNPUG15 CNPUG14 CNPUG13 CNPUG12 — — CNPUG9 CNPUG8 CNPUG7 CNPUG6 — — — — CNPUG1 CNPUG0 0000 c hn CNPDG 0E6C CNPDG15 CNPDG14 CNPDG13 CNPDG12 — — CNPDG9 CNPDG8 CNPDG7 CNPDG6 — — — — CNPDG1 CNPDG0 0000 o lo ANSELG 0E6E — — — — — — ANSG9 ANSG8 ANSG7 ANSG6 — — — — — — 03C0 g y Inc LNeogteend1:: xIf R= Gun2k annodw Rn Gva3l uaere o uns Rede saest ,g —en =e ruanl ipmuprpleomsee nintepdu,t sr,e tahde aVsU ‘S0B’.3 RV3e speint vmauluset sb ea rceo snhnoewctne din t oh eVxDaDd.ecimal. .

 TABLE 4-67: PORTG REGISTER MAP FOR dsPIC33EPXXX(GP/MC)806 AND PIC24EPXXXGP806 DEVICES ONLY 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 TRISG 0E60 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 — — 03C0 Mic PORTG 0E62 — — — — — — RG9 RG8 RG7 RG6 — — RG3(1) RG2(1) — — xxxx d ro LATG 0E64 — — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 — — xxxx s c P hip ODCG 0E66 — — — — — — — — — — — — ODCG3 ODCG2 — — 0000 IC Te CNENG 0E68 — — — — — — CNIEG9 CNIEG8 CNIEG7 CNIEG6 — — CNIEG3(1) CNIEG2(1) — — 0000 3 c 3 hn CNPUG 0E6A — — — — — — CNPUG9 CNPUG8 CNPUG7 CNPUG6 — — CNPUG3 CNPUG2 — — 0000 E olog CNPDG 0E6C — — — — — — CNPDG9 CNPDG8 CNPDG7 CNPDG6 — — CNPDG3 CNPDG2 — — 0000 PX y Inc ALeNgSeEnLdG: 0xE =6 Eunknow—n value on R—eset, — = un—implemente—d, read as ‘—0’. Reset v—alues arAeN sShGow9n in AhNexSaGd8ecimaAlN.SG7 ANSG6 — — — — — — 03C0 XX . ( Note 1: If RG2 and RG3 are used as general purpose inputs, the VUSB3V3 pin must be connected to VDD. G P / M TABLE 4-68: PORTG REGISTER MAP FOR dsPIC33EPXXXMU806 DEVICES ONLY C / File All M Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets U ) TRISG 0E60 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — — — — — 03C0 8 0 PORTG 0E62 — — — — — — RG9 RG8 RG7 RG6 — — RG3(1) RG2(1) — — xxxx 6 / LATG 0E64 — — — — — — LATG9 LATG8 LATG7 LATG6 — — — — — — xxxx 8 1 ODCG 0E66 — — — — — — — — — — — — — — — — 0000 0 / CNENG 0E68 — — — — — — CNIEG9 CNIEG8 CNIEG7 CNIEG6 — — CNIEG3(1) CNIEG2(1) — — 0000 81 CNPUG 0E6A — — — — — — CNPUG9 CNPUG8 CNPUG7 CNPUG6 — — — — — — 0000 4 a CNPDG 0E6C — — — — — — CNPDG9 CNPDG8 CNPDG7 CNPDG6 — — — — — — 0000 n ANSELG 0E6E — — — — — — ANSG9 ANSG8 ANSG7 ANSG6 — — — — — — 03C0 d P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I Note 1: If RG2 and RG3 are used as general purpose inputs, the VUSB3V3 pin must be connected to VDD. C 2 4 E P X X X ( G D P S / 7 G 0 6 U 1 6 ) G 8 -p 1 a 0 ge /8 1 1 19 4

D TABLE 4-69: PORTH REGISTER MAP FOR dsPIC33EPXXXMU814 AND PIC24EPXXXGU814 DEVICES ONLY d S s 70 File All P 61 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 G 3 -p TRISH 0E70 TRISH15 TRISH14 TRISH13 TRISH12 TRISH11 TRISH10 TRISH9 TRISH8 TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 FFFF 3 a E g PORTH 0E72 RH15 RH14 RH13 RH12 RH11 RH10 RH9 RH8 RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx e P 1 LATH 0E74 LATH15 LATH14 LATH13 LATH12 LATH11 LATH10 LATH9 LATH8 LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx X 2 0 X ODCH 0E76 ODCH15 ODCH14 ODCH13 ODCH12 ODCH11 ODCH10 ODCH9 ODCH8 ODCH7 ODCH6 ODCH5 ODCH4 ODCH3 ODCH2 ODCH1 ODCH0 0000 X CNENH 0E78 CNIEH15 CNIEH14 CNIEH13 CNIEH12 CNIEH11 CNIEH10 CNIEH9 CNIEH8 CNIEH7 CNIEH6 CNIEH5 CNIEH4 CNIEH3 CNIEH2 CNIEH1 CNIEH0 0000 ( G CNPUH 0E7A CNPUH15 CNPUH14 CNPUH13 CNPUH12 CNPUH11 CNPUH10 CNPUH9 CNPUH8 CNPUH7 CNPUH6 CNPUH5 CNPUH4 CNPUH3 CNPUH2 CNPUH1 CNPUH0 0000 P CNPDH 0E7C CNPDH15 CNPDH14 CNPDH13 CNPDH12 CNPDH11 CNPDH10 CNPDH9 CNPDH8 CNPDH7 CNPDH6 CNPDH5 CNPDH4 CNPDH3 CNPDH2 CNPDH1 CNPDH0 0000 /M ANSELH 0E7E — — — — — — — — — — — — — — — — 0000 C / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M U ) 8 TABLE 4-70: PORTJ REGISTER MAP FOR dsPIC33EPXXXMU814 AND PIC24EPXXXGU814 DEVICES ONLY 0 6 / File All 8 Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 1 0 / TRISJ 0E80 TRISJ15 TRISJ14 TRISJ13 TRISJ12 TRISJ11 TRISJ10 TRISJ9 TRISJ8 TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 FFFF 8 1 PORTJ 0E82 RJ15 RJ14 RJ13 RJ12 RJ12 RJ10 RJ9 RJ8 RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx 4 LATJ 0E84 LATJ15 LATJ14 LATJ13 LATJ12 LATJ11 LATJ10 LATJ9 LATJ8 LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx a n ODCJ 0E86 ODCJ15 ODCJ14 ODCJ13 ODCJ12 ODCJ11 ODCJ10 ODCJ9 ODCJ8 ODCJ7 ODCJ6 ODCJ5 ODCJ4 ODCJ3 ODCJ2 ODCJ1 ODCJ0 0000 d CNENJ 0E88 CNIEJ15 CNIEJ14 CNIEJ13 CNIEJ12 CNIEJ11 CNIEJ10 CNIEJ9 CNIEJ8 CNIEJ7 CNIEJ6 CNIEJ5 CNIEJ4 CNIEJ3 CNIEJ2 CNIEJ1 CNIEJ0 0000 P I CNPUJ 0E8A CNPUJ15 CNPUJ14 CNPUJ13 CNPUJ12 CNPUJ11 CNPUJ10 CNPUJ9 CNPUJ8 CNPUJ7 CNPUJ6 CNPUJ5 CNPUJ4 CNPUJ3 CNPUJ2 CNPUJ1 CNPUJ0 0000 C 2 CNPDJ 0E8C CNPDJ15 CNPDJ14 CNPDJ13 CNPDJ12 CNPDJ11 CNPDJ10 CNPDJ9 CNPDJ8 CNPDJ7 CNPDJ6 CNPDJ5 CNPDJ4 CNPDJ3 CNPDJ2 CNPDJ1 CNPDJ0 0000 4 ANSELJ 0E8E — — — — — — — — — — — — — — — — 0000 E P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X X X  (G 2 0 P 09 /G -2 0 U 1 2 M )81 icro 0/ c 8 hip 1 T 4 e c h n o lo g y In c .

 TABLE 4-71: PORTK REGISTER MAP FOR dsPIC33EPXXXMU814 AND PIC24EPXXXGU814 DEVICES ONLY 2 0 09-2 NFaimlee Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 12 TRISK 0E90 TRISK15 TRISK14 TRISK13 TRISK12 TRISK11 — — — — — — — — — TRISK1 TRISK0 F803 Mic PORTK 0E92 RK15 RK14 RK13 RK12 RK11 — — — — — — — — — RK1 RK0 xxxx d ro LATK 0E94 LATK15 LATK14 LATK13 LATK12 LATK11 — — — — — — — — — LATK1 LATK0 xxxx s c P hip ODCK 0E96 ODCK15 ODCK14 ODCK13 ODCK12 ODCK11 — — — — — — — — — ODCK1 ODCK0 0000 IC Te CNENK 0E98 CNIEK15 CNIEK14 CNIEK13 CNIEK12 CNIEK11 — — — — — — — — — CNIEK1 CNIEK0 0000 3 c 3 hn CNPUK 0E9A CNPUK15 CNPUK14 CNPUK13 CNPUK12 CNPUK11 — — — — — — — — — CNPUK1 CNPUK0 0000 E olog CNPDK 0E9C CNPDK15 CNPDK14 CNPDK13 CNPDK12 CNPDK11 — — — — — — — — — CNPDK1 CNPDK0 0000 PX y Inc ALeNgSeEnLdK: 0E9xE = unkno—wn value on— Reset, — = —unimplement—ed, read as ‘—0’. Reset va—lues are sh—own in hex—adecimal.— — — — — — — — 0000 XX . ( G P TABLE 4-72: PAD CONFIGURATION REGISTER MAP /M C All File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 / Resets M U PADCFG1 0EFE — — — — — — — — — — — — — — RTSECSEL PMPTTL 0000 ) 8 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X ( G D P S / 7 G 0 6 U 1 6 ) G 8 -p 1 a 0 ge /8 1 1 21 4

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.4.1 PAGED MEMORY SCHEME Construction of the EDS address is shown in Figure4-1. When DSRPAG<9> = 0 and the base address bit, The dsPIC33EPXXX(GP/MC/MU)806/810/814 and EA<15>=1, DSRPAG<8:0> is concatenated onto PIC24EPXXX(GP/GU)810/814 architecture extends EA<14:0> to form the 24-bit EDS read address. the available data space through a paging scheme, Similarly, when the base address bit, EA<15>=1, which allows the available data space to be accessed DSWPAG<8:0> is concatenated onto EA<14:0> to form using MOV instructions in a linear fashion for pre- and the 24-bit EDS write address. post-modified Effective Addresses (EA). The upper half of Base Data Space address is used in conjunction with the Data Space Page registers, the 10-Bit Read Page register (DSRPAG) or the 9-Bit Write Page register (DSWPAG), to form an Extended Data Space (EDS) address or Program Space Visibility (PSV) address. The Data Space Page registers are located in the SFR space. EXAMPLE 4-1: EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION Byte 16-Bit DS EA Select EA<15> = 0 No EDS Access 0 EA (DSRPAG = Don't Care) EA<15> Generate Y PSV Address DSRPAG<9> 1 EA = 1? N Select DSRPAG 0 DSRPAG<8:0> 9 Bits 15 Bits 24-Bit EDS EA Byte Select Note: DS read access when DSRPAG = 0x000 will force an address error trap. DS70616G-page 122  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 EXAMPLE 4-2: EXTENDED DATA SPACE (EDS) WRITE ADDRESS GENERATION Byte 16-Bit DS EA Select EA<15> = 0 (DSWPAG = Don’t Care) No EDS Access 0 EA Generate PSV Address EA<15> 1 EA DSWPAG<8:0> 9 Bits 15 Bits 24-Bit EDS EA Byte Select Note: DS read access when DSRPAG = 0x000 will force an address error trap. The paged memory scheme provides access to The Program Space (PS) can be accessed with multiple 32-Kbyte windows in the EDS and PSV DSRPAG of 0x200 or greater. Only reads from PS are memory. The Data Space Page registers DSxPAG, in supported using the DSRPAG. Writes to PS are not combination with the upper half of data space address supported, so DSWPAG is dedicated to DS, including can provide up to 16 Mbytes of additional address EDS, only. The data space and EDS can be read from space in the EDS and 12Mbytes (DSRPAG only) of and written to using DSRPAG and DSWPAG, PSV address space. The paged data memory space is respectively. shown in Example4-3.  2009-2012 Microchip Technology Inc. DS70616G-page 123

D EXAMPLE 4-3: PAGED DATA MEMORY SPACE d S s 70616 Local Data Space (DSRPAG<9:0E>D/DSSWPAG<8:0>) (InPstrrougctriaomn a Snpda Dceata) Tab(lTeB ALdPdArGe<s7s: 0S>p)ace PIC G 3 -p DS_Addr<14:0> 3 age 0x0000 Page 0 EP 1 Reserved X 24 (Will produce an DS_Addr<15:0> X 0x7FFF address error trap) 0x0000 X (TBLPAG=0x00) ( G 0x0000 EDS Page 0x001 lsw using P (DSRPAG=0x001) Pr(olsgwra –m < M15e:m0>o)ry TBLMRSDBL /uTsBinLgWTL /M 0x7FFF (DSWPAG=0x001) 0x00_0000 TBLRDH/TBLWTH C/ 0xFFFF M U ) 8 0 DS_Addr<15:0> 0x0000 6 0x0000 EDS Page 0x1FF /8 SFR Registers (DSRPAG=0x1FF) 1 (DSWPAG=0x1FF) 0 0x0FFF 0x7FFF 0x0000 /8 0x1000 (TBLPAG=0x7F) 1 0x0000 4 EDS Page 0x200 lsw using Up to 28Kbytes (DSRPAG=0x200) 0x7F_FFFF TBLRDL/TBLWTL an RAM No Writes Allowed MSB using d 0x7FFF 0x7FFF TBLRDH/TBLWTH P PSV 0xFFFF I C 0x8000 Program Program Memory 2 Memory 4 32Kbytes (lsw) (MSB – <23:16>) E EDS Window 0x0000 0x00_0000 P EDS Page 0x2FF X (DSRPAG=0x2FF) X 0xFFFF X No Writes Allowed  0x7FFF (G 20 0x0000 EDS Page 0x300 P 09-2 (DSRPAG=0x300) /G 0 No Writes Allowed U 12 M 0x7FFF PSV )81 icro Program 0/ c Memory 8 hip Tec 0x0000 EDS Page 0x3FF (MSB) 0x7F_FFFF 14 h n (DSRPAG=0x3FF) o lo No Writes Allowed g 0x7FFF y In c .

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Allocating different Page registers for read and write In general, when an overflow is detected, the DSxPAG access allows the architecture to support data register is incremented and the EA<15> bit is set to movement between different pages in data memory. keep the base address within the EDS or PSV window. This is accomplished by setting the DSRPAG register When an underflow is detected, the DSxPAG register is value to the page from which you want to read and decremented and the EA<15> bit is set to keep the configuring the DSWPAG register to the page to which base address within the EDS or PSV window. This it needs to be written. Data can also be moved from creates a linear EDS and PSV address space, but only different PSV to EDS pages, by configuring the when using Register Indirect Addressing modes. DSRPAG and DSWPAG registers to address PSV and Exceptions to the operation described above arise EDS space, respectively. The data can be moved when entering and exiting the boundaries of Page 0, between pages by a single instruction. EDS and PSV spaces. Table4-73 lists the effects of When an EDS or PSV page overflow or underflow overflow and underflow scenarios at different occurs, EA<15> is cleared as a result of the register boundaries. indirect EA calculation. An overflow or underflow of the In the following cases, when overflow or underflow EA in the EDS or PSV pages can occur at the page occurs, the EA<15> bit is set and the DSxPAG is not boundaries when: modified; therefore, the EA will wrap to the beginning of • The initial address, prior to modification, the current page: addresses an EDS or PSV page. • Register Indirect with Register Offset Addressing • The EA calculation uses Pre- or Post-Modified • Modulo Addressing Register Indirect Addressing. However, this does • Bit-Reversed Addressing not include Register Offset Addressing. TABLE 4-73: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS and PSV SPACE BOUNDARIES(2,3,4) Before After O/U, Operation R/W DS Page DS Page DSxPAG DSxPAG EA<15> Description EA<15> Description O, DSRPAG = 0x1FF 1 EDS: Last page DSRPAG = 0x1FF 0 See Note 1 Read O, DSRPAG = 0x2FF 1 PSV: Last lsw DSRPAG = 0x300 1 PSV: First MSB [++Wn] Read page page or O, DSRPAG = 0x3FF 1 PSV: Last MSB DSRPAG = 0x3FF 0 See Note 1 [Wn++] Read page O, DSWPAG = 0x1FF 1 EDS: Last page DSWPAG = 0x1FF 0 See Note 1 Write U, DSRPAG = 0x001 1 EDS page DSRPAG = 0x001 0 See Note 1 Read [--Wn] U, DSRPAG = 0x200 1 PSV: First lsw DSRPAG = 0x200 0 See Note 1 or Read page [Wn--] U, DSRPAG = 0x300 1 PSV: First MSB DSRPAG = 0x2FF 1 PSV: Last lsw Read page page Legend: O = Overflow, U = Underflow, R = Read, W = Write Note 1: Register Indirect Addressing now addresses a location in the Base Data Space (0x0000-0x8000). 2: An EDS access with DSxPAG = 0x000 will generate an address error trap. 3: Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate an address error trap. 4: Pseudo-Linear Addressing is not supported for large offsets.  2009-2012 Microchip Technology Inc. DS70616G-page 125

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.4.2 EXTENDED X DATA SPACE The remaining pages including both EDS and PSV pages are only accessible using the DSRPAG or The lower half of the base address space range, between DSWPAG registers in combination with the upper 0x0000 and 0x7FFF, is always accessible regardless of 32Kbytes, 0x8000 to 0xFFFF, of the base address, the contents of the Data Space Page registers. It is where base address bit, EA<15> = 1. indirectly addressable through the register indirect instructions. It can be regarded as being located in the For example, when DSRPAG = 0x01 or default EDS Page 0 (i.e., EDS address range of DSWPAG=0x01, accesses to the upper 32Kbytes, 0x000000 to 0x007FFF with the base address bit, 0x8000 to 0xFFFF, of the data space will map to the EA<15> = 0, for this address range). However, Page 0 EDS address range of 0x008000 to 0x00FFFF. cannot be accessed through the upper 32Kbytes When DSRPAG = 0x02 or DSWPAG = 0x02, (0x8000 to 0xFFFF) of Base Data Space, in combination accesses to the upper 32Kbytes of the data space with DSRPAG = 0x00 or DSWPAG = 0x00. will map to the EDS address range of 0x010000 to Consequently, DSRPAG and DSWPAG are initialized to 0x017FFF and so on, as shown in the EDS memory 0x001 at Reset. map in Figure4-7. Note1: DSxPAG should not be used to access For more information of the PSV page access using Page 0. An EDS access with DSxPAG Data Space Page registers refer to Section 4.5 set to 0x000 will generate an address “Program Space Visibility from Data Space” in error trap. Section 4. “Program Memory” (DS70613) of the “dsPIC33E/PIC24E Family Reference Manual”. 2: Clearing DSxPAG in software has no effect. FIGURE 4-7: EDS MEMORY MAP EA<15:0> 0x0000 SFR/DS (PAGE 0) Conventional DS Address 0x8000 0x008000 DS Page 1 0xFFFF 0x010000 Page 2 0x018000 Page 3 DSRPAG<9> = 0 EDS EA Address (24 bits) (DSRPAG<8:0>, EA<14:0>) (DSWPAG<8:0>, EA<14:0>) 0xFE8000 Page 1FD 0xFF0000 Page 1FE 0xFF8000 Page 1FF DS70616G-page 126  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.4.3 EDS ARBITRATION AND BUS respectively (M1 is reserved and cannot be used). The MASTER PRIORITY user application may raise or lower the priority of the masters to be above that of the CPU by setting the EDS accesses from bus masters in the system are appropriate bits in the EDS Bus Master Priority Control arbitrated. (MSTRPR) register. All bus masters with raised The arbiter for data memory (including EDS) arbitrates priorities will maintain the same priority relationship between the CPU, the DMA, the USB module and the relative to each other (i.e., M1 being highest and M3 ICD module. In the event of coincidental access to a being lowest, with M2 in between). Also, all the bus bus by the bus masters, the arbiter determines which masters with priorities below that of the CPU maintain bus master access has the highest priority. The other the same priority relationship relative to each other. bus masters are suspended and processed after the The priority schemes for bus masters with different access of the bus by the bus master with the highest MSTRPR values are tabulated in Table4-74. priority. This bus master priority control allows the user By default, the CPU is Bus Master 0 (M0) with the application to manipulate the real-time response of the highest priority and the ICD is Bus Master 4 (M4) with system, either statically during initialization, or the lowest priority. The remaining bus masters (USB dynamically in response to real-time events. and DMA Controllers) are allocated to M2 and M3, TABLE 4-74: EDS BUS ARBITER PRIORITY MSTRPR<15:0> Bit Setting(1) Priority 0x0000 0x0008 0x0020 0x0028 M0 (highest) CPU USB DMA USB M1 Reserved CPU CPU DMA M2 USB Reserved Reserved CPU M3 DMA DMA USB Reserved M4 (lowest) ICD ICD ICD ICD Note 1: All other values of MSTRPR<15:0> are reserved. FIGURE 4-8: EDS ARBITER ARCHITECTURE DPSRAM DMA USB ICD CPU Reserved MSTRPR<15:0> M0 M1 M2 M3 M4 EDS Arbiter SRAM  2009-2012 Microchip Technology Inc. DS70616G-page 127

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.4.4 SOFTWARE STACK FIGURE 4-9: CALL STACK FRAME The W15 register serves as a dedicated software Stack 0x0000 15 0 Pointer (SP) and is automatically modified by exception CALL SUBR processing, subroutine calls and returns; however, W15 can be referenced by any instruction in the same d manner as all other W registers. This simplifies warss reading, writing and manipulating of the Stack Pointer s Toddre (for example, creating stack frames). wA Note: Taoc cepsrsoetse,c tW 1a5g<a0in>s ti s fmixiesda litgon e‘0d’ bsyt athcek Stack GroHigher b‘00000<0FP0r0Ce0e<’ 1W5P:oC1r><d2>2:16> WW1155 ((baefteforr Ce ACLALL)L) hardware. W15 is initialized to 0x1000 during all Resets. This address ensures that the SP points to valid RAM in all dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 devices and permits stack availability for non-maskable trap exceptions. 4.5 Instruction Addressing Modes These can occur before the SP is initialized by the user The addressing modes, shown in Table4-75, form the software. You can reprogram the SP during basis of the addressing modes optimized to support the initialization to any location within data space. specific features of individual instructions. The The Stack Pointer always points to the first available addressing modes provided in the MAC class of free word and fills the software stack working from instructions differ from those in the other instruction lower toward higher addresses. Figure4-9 illustrates types. how it pre-decrements for a stack pop (read) and post-increments for a stack push (writes). 4.5.1 FILE REGISTER INSTRUCTIONS When the PC is pushed onto the stack, PC<15:0> is Most file register instructions use a 13-bit address field pushed onto the first available stack word, then (f) to directly address data present in the first PC<22:16> is pushed into the second available stack 8192bytes of data memory (Near Data Space). Most location. For a PC push during any CALL instruction, file register instructions employ a working register, W0, the MSB of the PC is zero-extended before the push, which is denoted as WREG in these instructions. The as shown in Figure4-9. During exception processing, destination is typically either the same file register or the MSB of the PC is concatenated with the lower 8 bits WREG (with the exception of the MUL instruction), of the CPU STATUS Register, SR. This allows the which writes the result to a register or register pair. The contents of SRL to be preserved automatically during MOV instruction allows additional flexibility and can interrupt processing. access the entire data space. Note1: For main system Stack Pointer (W15) 4.5.2 MCU INSTRUCTIONS coherency, W15 is never subject to (EDS) paging and is therefore, The three-operand MCU instructions are of the form: restricted to the address range of Operand 3 = Operand 1 <function> Operand 2 0x0000 to 0xFFFF. The same applies to where Operand 1 is always a working register (that is, W14 when used as a Stack Frame the addressing mode can only be Register Direct), Pointer (SFA = 1). which is referred to as Wb. Operand 2 can be a W reg- 2: As the stack can be placed in and ister, fetched from data memory, or a 5-bit literal. The across X, Y and DMA RAM spaces, result location can be either a W register or a data care must be exercised regarding its memory location. The following addressing modes are use, particularly with regard to local supported by MCU instructions: automatic variables in a C development • Register Direct environment. • Register Indirect • Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all of the addressing modes given above. Individ- ual instructions can support different subsets of these addressing modes. DS70616G-page 128  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 4-75: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.5.3 MOVE AND ACCUMULATOR 4.5.4 MAC INSTRUCTIONS INSTRUCTIONS (dsPIC33EPXXXMU806/810/814 DEVICES ONLY) Move instructions (dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814) and the DSP accumula- The dual source operand DSP instructions (CLR, ED, tor class of instructions (dsPIC33EPXXXMU806/810/ EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred 814 only) provide a greater degree of addressing to as MAC instructions, use a simplified set of addressing flexibility than other instructions. In addition to the modes to allow the user application to effectively addressing modes supported by most MCU manipulate the Data Pointers through register indirect instructions, move and accumulator instructions also tables. support Register Indirect with Register Offset The two-source operand prefetch registers must be Addressing mode, also referred to as Register Indexed members of the set {W8, W9, W10, W11}. For data mode. reads, W8 and W9 are always directed to the X RAGU, Note: For the MOV instructions, the addressing and W10 and W11 are always directed to the Y AGU. mode specified in the instruction can differ The Effective Addresses generated (before and after for the source and destination EA. modification) must, therefore, be valid addresses within However, the 4-bit Wb (Register Offset) X data space for W8 and W9 and Y data space for W10 field is shared by both source and and W11. destination (but typically only used by Note: Register Indirect with Register Offset one). Addressing mode is available only for W9 In summary, the following addressing modes are (in X space) and W11 (in Y space). supported by move and accumulator instructions: In summary, the following addressing modes are • Register Direct supported by the MAC class of instructions: • Register Indirect • Register Indirect • Register Indirect Post-modified • Register Indirect Post-Modified by 2 • Register Indirect Pre-modified • Register Indirect Post-Modified by 4 • Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 6 • Register Indirect with Literal Offset • Register Indirect with Register Offset (Indexed) • 8-Bit Literal 4.5.5 OTHER INSTRUCTIONS • 16-Bit Literal Note: Not all instructions support all the Besides the addressing modes outlined previously, some addressing modes given above. Individual instructions use literal constants of various sizes. For instructions may support different subsets example, BRA (branch) instructions use 16-bit signed of these addressing modes. literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ULNK, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands.  2009-2012 Microchip Technology Inc. DS70616G-page 129

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.6 Modulo Addressing 4.6.1 START AND END ADDRESS (dsPIC33EPXXXMU806/810/814 The Modulo Addressing scheme requires that a Devices Only) starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: Modulo Addressing mode is a method of providing an XMODSRT, XMODEND, YMODSRT and YMODEND automated means to support circular data buffers using (see Table4-1). hardware. The objective is to remove the need for software to perform data address boundary checks Note: Y space Modulo Addressing EA calcula- when executing tightly looped code, as is typical in tions assume word-sized data (LSb of many DSP algorithms. every EA is always clear). Modulo Addressing can operate in either data or The length of a circular buffer is not directly specified. It Program Space (since the Data Pointer mechanism is is determined by the difference between the essentially the same for both). One circular buffer can be corresponding start and end addresses. The maximum supported in each of the X (which also provides the point- possible length of the circular buffer is 32K words ers into Program Space) and Y data spaces. Modulo (64Kbytes). Addressing can operate on any W Register Pointer. How- ever, it is not advisable to use W14 or W15 for Modulo 4.6.2 W ADDRESS REGISTER Addressing since these two registers are used as the SELECTION Stack Frame Pointer and Stack Pointer, respectively. The Modulo and Bit-Reversed Addressing Control In general, any particular circular buffer can be config- register, MODCON<15:0>, contains enable flags as well ured to operate in only one direction as there are as a W register field to specify the W Address registers. certain restrictions on the buffer start address (for incre- The XWM and YWM fields select the registers that menting buffers), or end address (for decrementing operate with Modulo Addressing: buffers), based upon the direction of the buffer. • If XWM = 1111, XRAGU and X WAGU Modulo The only exception to the usage restrictions is for Addressing is disabled. buffers that have a power-of-two length. As these • If YWM = 1111, Y AGU Modulo Addressing is buffers satisfy the start and end address criteria, they disabled. can operate in a bidirectional mode (that is, address The X Address Space Pointer W register (XWM), to boundary checks are performed on both the lower and which Modulo Addressing is to be applied, is stored in upper address boundaries). MODCON<3:0> (see Table4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than ‘1111’ and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘1111’ and the YMODEN bit is set at MODCON<14>. FIGURE 4-10: MODULO ADDRESSING OPERATION EXAMPLE Byte MOV #0x1100, W0 Address MOV W0, XMODSRT ;set modulo start address 0x1100 MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer 0x1163 DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location Start Addr = 0x1100 AGAIN: INC W0, W0 ;increment the fill value End Addr = 0x1163 Length = 0x0032 words DS70616G-page 130  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.6.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes, APPLICABILITY the last ‘N’ bits of the data buffer start address must be zeros. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W XB<14:0> is the Bit-Reversed Address modifier, or register. Address boundaries check for addresses ‘pivot point,’ which is typically a constant. In the case of equal to: an FFT computation, its value is equal to half of the FFT data buffer size. • The upper boundary addresses for incrementing buffers Note: All bit-reversed EA calculations assume • The lower boundary addresses for decrementing word-sized data (LSb of every EA is buffers always clear). The XB value is scaled accordingly to generate compatible (byte) It is important to realize that the address boundaries addresses. check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing When enabled, Bit-Reversed Addressing is executed buffers) boundary addresses (not just equal to). only for Register Indirect with Pre-Increment or Post- Address changes can, therefore, jump beyond Increment Addressing and word-sized data writes. It boundaries and still be adjusted correctly. does not function for any other addressing mode or for byte-sized data and normal addresses are generated Note: The modulo corrected Effective Address instead. When Bit-Reversed Addressing is active, the is written back to the register only when W Address Pointer is always added to the address Pre-Modify or Post-Modify Addressing modifier (XB) and the offset associated with the mode is used to compute the Effective Register Indirect Addressing mode is ignored. In Address. When an address offset (such addition, as word-sized data is a requirement, the LSb as [W7 + W2]) is used, Modulo of the EA is ignored (and always clear). Addressing correction is performed but the contents of the register remain Note: Modulo Addressing and Bit-Reversed unchanged. Addressing can be enabled simultaneously using the same W register, but Bit- 4.7 Bit-Reversed Addressing Reversed Addressing operation will always take precedence for data writes when (dsPIC33EPXXXMU806/810/814 enabled. Devices Only) If Bit-Reversed Addressing has already been enabled Bit-Reversed Addressing mode is intended to simplify by setting the BREN (XBREV<15>) bit, a write to the data reordering for radix-2 FFT algorithms. It is XBREV register should not be immediately followed by supported by the X AGU for data writes only. an indirect read operation using the W register that has The modifier, which can be a constant value or register been designated as the Bit-Reversed Pointer. contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. 4.7.1 BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • BWMx bits (W register selection) in the MODCON register are any value other than ‘1111’ (the stack cannot be accessed using Bit-Reversed Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment  2009-2012 Microchip Technology Inc. DS70616G-page 131

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 4-11: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-76: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 DS70616G-page 132  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.8 Interfacing Program and Data Table instructions allow an application to read or write Memory Spaces to small areas of the program memory. This capability makes the method ideal for accessing data tables that The dsPIC33EPXXX(GP/MC/MU)806/810/814 and need to be updated periodically. It also allows access PIC24EPXXX(GP/GU)810/814 architecture uses a to all bytes of the program word. The remapping 24-bit wide Program Space and a 16-bit wide data method allows an application to access a large block of space. The architecture is also a modified Harvard data on a read-only basis, which is ideal for look-ups scheme, meaning that data can also be present in the from a large table of static data. The application can Program Space. To use this data successfully, it must only access the least significant word of the program be accessed in a way that preserves the alignment of word. information in both spaces. Aside from normal execution, the dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 architecture provides two methods by which Program Space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the Program Space • Remapping a portion of the Program Space into the data space (Program Space Visibility) TABLE 4-77: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx FIGURE 4-12: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.  2009-2012 Microchip Technology Inc. DS70616G-page 133

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 4.8.1 DATA ACCESS FROM PROGRAM - In Byte mode, either the upper or lower byte MEMORY USING TABLE of the lower program word is mapped to the INSTRUCTIONS lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower The TBLRDL and TBLWTL instructions offer a direct byte is selected when it is ‘0’. method of reading or writing the lower word of any • TBLRDH (Table Read High): address within the Program Space without going through data space. The TBLRDH and TBLWTH - In Word mode, this instruction maps the entire instructions are the only method to read or write the upper word of a program address (P<23:16>) upper 8bits of a Program Space word as data. to a data address. The ‘phantom’ byte (D<15:8>), is always ‘0’. The PC is incremented by two for each successive - In Byte mode, this instruction maps the upper 24-bit program word. This allows program memory or lower byte of the program word to D<7:0> addresses to directly map to data space addresses. of the data address, in the TBLRDL instruc- Program memory can thus be regarded as two 16-bit tion. The data is always ‘0’ when the upper wide word address spaces, residing side by side, each ‘phantom’ byte is selected (Byte Select = 1). with the same address range. TBLRDL and TBLWTL access the space that contains the least significant In a similar fashion, two table instructions, TBLWTH data word. TBLRDH and TBLWTH access the space that and TBLWTL, are used to write individual bytes or contains the upper data byte. words to a Program Space address. The details of their operation are explained in Section5.0 “Flash Two table instructions are provided to move byte or Program Memory”. word-sized (16-bit) data to and from Program Space. Both function as either byte or word operations. For all table operations, the area of program memory space to be accessed is determined by the Table Page • TBLRDL (Table Read Low): register (TBLPAG). TBLPAG covers the entire program - In Word mode, this instruction maps the memory space of the device, including user application lower word of the Program Space and configuration spaces. When TBLPAG<7> = 0, the location (P<15:0>) to a data address table page is located in the user memory space. When (D<15:0>). TBLPAG<7> = 1, the page is located in configuration space. FIGURE 4-13: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. DS70616G-page 134  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 5.0 FLASH PROGRAM MEMORY pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). Note1: This data sheet summarizes the features This allows customers to manufacture boards with of the dsPIC33EPXXX(GP/MC/MU)806/ unprogrammed devices and then program the device 810/814 and PIC24EPXXX(GP/GU)810/ just before shipping the product. This also allows the 814 families of devices. It is not intended most recent firmware or a custom firmware to be to be a comprehensive reference source. programmed. To complement the information in this data RTSP is accomplished using TBLRD (table read) and sheet, refer to Section 5. “Flash Pro- TBLWT (table write) instructions. With RTSP, the user gramming” (DS70609) of the “dsPIC33E/ application can write program memory data either in PIC24E Family Reference Manual”, which blocks or ‘rows’ of 128 instructions (384 bytes) at a time is available from the Microchip web site or a single program memory word, and erase program (www.microchip.com). memory in blocks or ‘pages’ of 1024 instructions 2: Some registers and associated bits (3072bytes) at a time. described in this section may not be available on all devices. Refer to 5.1 Table Instructions and Flash Section4.0 “Memory Organization” in Programming this data sheet for device-specific register and bit information. Regardless of the method used, all programming of Flash memory is done with the table read and table The dsPIC33EPXXX(GP/MC/MU)806/810/814 and write instructions. These allow direct read and write PIC24EPXXX(GP/GU)810/814 devices contain access to the program memory space from the data internal Flash program memory for storing and memory while the device is in normal operating mode. executing application code. The memory is readable, The 24-bit target address in the program memory is writable and erasable during normal operation over the formed using bits<7:0> of the TBLPAG register and the entire VDD range. Effective Address (EA) from a W register, specified in Flash memory can be programmed in two ways: the table instruction, as shown in Figure5-1. • In-Circuit Serial Programming™ (ICSP™) The TBLRDL and the TBLWTL instructions are used to programming capability read or write to bits<15:0> of program memory. • Run-Time Self-Programming (RTSP) TBLRDL and TBLWTL can access program memory in both Word and Byte modes. ICSP allows a dsPIC33EPXXX(GP/MC/MU)806/810/ 814 and PIC24EPXXX(GP/GU)810/814 device to be The TBLRDH and TBLWTH instructions are used to read serially programmed while in the end application circuit. or write to bits<23:16> of program memory. TBLRDH This is done with two lines for programming clock and and TBLWTH can also access program memory in Word programming data (one of the alternate programming or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using 0 Program Counter 0 Program Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2009-2012 Microchip Technology Inc. DS70616G-page 135

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 5.2 RTSP Operation 5.3 Programming Operations The dsPIC33EPXXX(GP/MC/MU)806/810/814 and A complete programming sequence is necessary for PIC24EPXXX(GP/GU)810/814 Flash program memory programming or erasing the internal Flash in RTSP array is organized into rows of 128 instructions or mode. The processor stalls (waits) until the 384bytes. RTSP allows the user application to erase a programming operation is finished. page of memory, which consists of eight rows The programming time depends on the FRC accuracy (1024instructions) at a time, and to program one row (see Table32-19) and the value of the FRC Oscillator or one word at a time. Table32-12 lists typical erase and Tuning register (see Register9-4). Use the following programming times. The 8-row erase pages and single formula to calculate the minimum and maximum values row write rows are edge-aligned from the beginning of for the Row Write Time, Page Erase Time and Word program memory, on boundaries of 3072 bytes and Write Cycle Time parameters (see Table32-12). 384bytes, respectively. The program memory implements holding buffers, EQUATION 5-1: PROGRAMMING TIME which are located in the write latch area, that can con- tain 128 instructions of programming data. Prior to the ------------------------------------------------------------T-------------------------------------------------------------- actual programming operation, the write data must be 7.37 MHzFRC Accuracy%FRC Tuning% loaded into the buffers sequentially. The instruction words loaded must always be from a group of For example, if the device is operating at +125°C, the 64boundary. FRC accuracy will be ±5%. If the TUN<5:0> bits (see The basic sequence for RTSP programming is to set up Register9-4) are set to ‘b111111, the minimum row a Table Pointer, then do a series of TBLWT instructions write time is equal to Equation5-2. to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total EQUATION 5-2: MINIMUM ROW WRITE of 128 TBLWTL and TBLWTH instructions are required TIME to load the instructions. All of the table write operations are single-word writes T =--------------------------------1---1---0---6---4--- -C----y---c--l--e---s--------------------------------=1.435ms (two instruction cycles) because only the buffers are RW 7.37 MHz1+0.051–0.00375 written. A programming cycle is required for program- ming each row. For more information on erasing and programming Flash memory, refer to Section 5. The maximum row write time is equal to Equation5-3. “Flash Programming” (DS70609) in the “dsPIC33E/ PIC24E Family Reference Manual”. EQUATION 5-3: MAXIMUM ROW WRITE TIME 11064 Cycles T =----------------------------------------------------------------------------------------------=1.586ms RW 7.37 MHz1–0.051–0.00375 Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. DS70616G-page 136  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 5.4 Flash Program Memory 5.5 Control Registers Resources Four SFRs are used to read and write the program Many useful resources related to Flash program Flash memory: NVMCON, NVMKEY, NVMADRU and memory are provided on the main product page of the NVMADR. Microchip web site for the devices listed in this data The NVMCON register (Register5-1) controls which sheet. This product page, which can be accessed using blocks are to be erased, which memory type is to be this link, contains the latest updates and additional programmed and the start of the programming cycle. information. NVMKEY (Register5-4) is a write-only register that is Note: In the event you are not able to access the used for write protection. To start a programming or product page using the link above, enter erase sequence, the user application must this URL in your browser: consecutively write 0x55 and 0xAA to the NVMKEY http://www.microchip.com/wwwproducts/ register. Devices.aspx?dDocName=en554310 There are two NVM Address registers: NVMADRU and NVMADR. These two registers, when concatenated, 5.4.1 KEY RESOURCES form the 24-bit Effective Address (EA) of the selected • Section 5. “Flash Programming” (DS70609) in row or word for programming operations, or the the “dsPIC33E/PIC24E Family Reference selected page for erase operations. Manual” The NVMADRU register is used to hold the upper 8 bits • Code Samples of the EA, while the NVMADR register is used to hold • Application Notes the lower 16 bits of the EA. • Software Libraries • Webinars • All related “dsPIC33E/PIC24E Family Reference Manual” Sections • Development Tools  2009-2012 Microchip Technology Inc. DS70616G-page 137

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 5-1: NVMCON: NON-VOLATILE MEMORY (NVM) CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR NVMSIDL(2) — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — — — — NVMOP<3:0>(3,4) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12 NVMSIDL: NVM Stop-in-Idle Control bit(2) 1 = Flash voltage regulator goes into Stand-by mode during Idle mode 0 = Flash voltage regulator is active during Idle mode bit 11-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,3,4) 1111 = Reserved 1110 = Reserved 1101 = Bulk erase primary program Flash memory 1100 = Reserved 1011 = Reserved 1010 = Bulk erase auxiliary program Flash memory 0011 = Memory page erase operation 0010 = Memory row program operation 0001 = Memory word program operation(5) 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on a POR. 2: If this bit is set, upon exiting Idle mode, there is a delay (TVREG) before Flash memory becomes operational. 3: All other combinations of NVMOP<3:0> are unimplemented. 4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress. 5: Two adjacent words are programmed during execution of this operation. DS70616G-page 138  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 5-2: NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADRU<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMADRU<7:0>: Nonvolatile Memory Upper Write Address bits Selects the upper 8 bits of the location to program or erase in program Flash memory. This register may be read or written by the user application. REGISTER 5-3: NVMADR: NONVOLATILE MEMORY ADDRESS REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<15:8> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 NVMADR<15:0>: Nonvolatile Memory Write Address bits Selects the lower 16 bits of the location to program or erase in program Flash memory. This register may be read or written by the user application. REGISTER 5-4: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits  2009-2012 Microchip Technology Inc. DS70616G-page 139

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 140  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 6.0 RESETS The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The Note1: This data sheet summarizes the features following is a list of device Reset sources: of the dsPIC33EPXXX(GP/MC/MU)806/ • POR: Power-on Reset 810/814 and PIC24EPXXX(GP/GU)810/ • BOR: Brown-out Reset 814 families of devices. It is not intended • MCLR: Master Clear Pin Reset to be a comprehensive reference source. • SWR: RESET Instruction To complement the information in this • WDTO: Watchdog Timer Reset data sheet, refer to Section 8. “Reset” (DS70602) of the “dsPIC33E/PIC24E • CM: Configuration Mismatch Reset Family Reference Manual”, which is • TRAPR: Trap Conflict Reset available from the Microchip web site • IOPUWR: Illegal Condition Device Reset (www.microchip.com). - Illegal Opcode Reset 2: Some registers and associated bits - Uninitialized W Register Reset described in this section may not be - Security Reset available on all devices. Refer to A simplified block diagram of the Reset module is Section4.0 “Memory Organization” in shown in Figure6-1. this data sheet for device-specific register Any active source of Reset will make the SYSRST sig- and bit information. nal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected. Note: Refer to the specific peripheral section or Section4.0 “Memory Organization” of this manual for register Reset states. FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR Internal Regulator SYSRST VDD VDD Rise POR Detect Trap Conflict Illegal Opcode Uninitialized W Register Security Reset Configuration Mismatch  2009-2012 Microchip Technology Inc. DS70616G-page 141

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 6.1 Resets Resources 6.2 RCON Control Register Many useful resources related to Resets are provided All types of device Resets set a corresponding status on the main product page of the Microchip web site for bit in the RCON register to indicate the type of Reset the devices listed in this data sheet. This product page, (see Register6-1). which can be accessed using this link, contains the A POR clears all the bits, except for the POR and BOR latest updates and additional information. bits (RCON<1:0>), that are set. The user application Note: In the event you are not able to access the can set or clear any bit at any time during code product page using the link above, enter execution. The RCON bits only serve as status bits. this URL in your browser: Setting a particular Reset status bit in software does http://www.microchip.com/wwwproducts/ not cause a device Reset to occur. Devices.aspx?dDocName=en554310 The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. 6.1.1 KEY RESOURCES The function of these bits is discussed in other sections • Section 8. “Reset” (DS70602) in the “dsPIC33E/ of this manual. PIC24E Family Reference Manual” Note: The status bits in the RCON register • Code Samples should be cleared after they are read so • Application Notes that the next RCON register value after a device Reset is meaningful. • Software Libraries • Webinars • All related “dsPIC33E/PIC24E Family Reference Manual” Sections • Development Tools DS70616G-page 142  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — VREGSF — CM VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11 VREGSF: Flash Voltage Regulator Standby During Sleep bit 1 = Flash voltage regulator is active during Sleep 0 = Flash voltage regulator goes into Standby mode during Sleep bit 10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has occurred. 0 = A Configuration Mismatch Reset has NOT occurred bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2009-2012 Microchip Technology Inc. DS70616G-page 143

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70616G-page 144  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 7.0 INTERRUPT CONTROLLER 7.1 Interrupt Vector Table The dsPIC33EPXXX(GP/MC/MU)806/810/814 and Note1: This data sheet summarizes the features PIC24EPXXX(GP/GU)810/814 Interrupt Vector Table of the dsPIC33EPXXX(GP/MC/MU)806/ (IVT), shown in Figure7-1, resides in the General 810/814 and PIC24EPXXX(GP/GU)810/ Segment of program memory, starting at location, 814 families of devices. It is not intended 0x000004, and is used when executing code from the to be a comprehensive reference source. General Segment. The IVT contains sevennon- To complement the information in this maskable trap vectors and up to 114 sources of data sheet, refer to Section 6. “Inter- interrupt. In general, each interrupt source has its own rupts” (DS70600) of the “dsPIC33E/ vector. Each interrupt vector contains a 24-bit wide PIC24E Family Reference Manual”, address. The value programmed into each interrupt which is available from the Microchip web vector location is the starting address of the associated site (www.microchip.com). Interrupt Service Routine (ISR). 2: Some registers and associated bits described in this section may not be Interrupt vectors are prioritized in terms of their natural available on all devices. Refer to priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher Section4.0 “Memory Organization” in natural priority. For example, the interrupt associated this data sheet for device-specific register with vector 0 takes priority over interrupts at any other and bit information. vector address. The dsPIC33EPXXX(GP/MC/MU)806/810/814 and Note: Any unimplemented or unused vector PIC24EPXXX(GP/GU)810/814 interrupt controller locations in the IVT should be reduces the numerous peripheral interrupt request programmed with the address of a default signals to a single interrupt request signal to interrupt handler routine that contains a the dsPIC33EPXXX(GP/MC/MU)806/810/814 and RESET instruction. PIC24EPXXX(GP/GU)810/814 CPU. The interrupt controller has the following features: 7.2 Auxiliary Interrupt Vector • Up to eight processor exceptions and software traps When code is being executed in the Auxiliary Segment, a special single interrupt vector, located at address, • Eight user-selectable priority levels 0x7FFFFA, is used for all interrupt sources and traps. • Interrupt Vector Table (IVT) with a unique vector Once vectored to this single routine, the for each interrupt or exception source VECNUM<7:0> bits (INTTREG<7:0>, Register7-7) • Fixed priority within a specified user priority level can be examined to determine the source of the • Fixed interrupt entry and return latencies interrupt or trap so that it can be properly processed. 7.3 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 devices clear their registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location, 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine. Note: Reset locations are also located in the Auxiliary Segment at the addresses 0x7FFFFC and 0x7FFFFE. The Reset Target Vector Select bit, RSTPRI (FICD<2>) controls whether the primary (General Segment) or Auxiliary Segment Reset location is used.  2009-2012 Microchip Technology Inc. DS70616G-page 145

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 7-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 INTERRUPT VECTOR TABLE Reset – GOTO Instruction(1) 0x000000 Reset – GOTO Address(1) 0x000002 Oscillator Fail Trap Vector 0x000004 y orit Address Error Trap Vector 0x000006 Pri Generic Hard Trap Vector 0x000008 der Stack Error Trap Vector 0x00000A Or Math Error Trap Vector 0x00000C al ur DMAC Error Trap Vector 0x00000E at Generic Soft Trap Vector 0x000010 N g Reserved 0x000012 n si Interrupt Vector 0 0x000014 a e cr T Interrupt Vector 1 0x000016 e V D I : : : : : : Interrupt Vector 52 0x00007C Interrupt Vector 53 0x00007E Interrupt Vector 54 0x000080 See Table7-1 for : : Interrupt Vector Details : : : : Interrupt Vector 116 0x0000FC Interrupt Vector 117 0x0000FE Interrupt Vector 118 0x000100 Interrupt Vector 119 0x000102 Interrupt Vector 120 0x000104 : : : : : : Interrupt Vector 244 0x0001FC Interrupt Vector 245 0x0001FE START OF CODE 0x000200 Note 1: Reset locations are also located in the Auxiliary Segment at the addresses 0x7FFFFC and 0x7FFFFE. The Reset Target Vector Select bit, RSTPRI (FICD<2>) controls whether the primary (General Segment) or Auxiliary Segment Reset location is used. DS70616G-page 146  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 7-1: INTERRUPT VECTOR DETAILS Interrupt Bit Location Vector IVT Interrupt Source IRQ # # Address Flag Enable Priority Highest Natural Order Priority INT0 – External Interrupt 0 8 0 0x000014 IFS0<0> IEC0<0> IPC0<2:0> IC1 – Input Capture 1 9 1 0x000016 IFS0<1> IEC0<1> IPC0<6:4> OC1 – Output Compare 1 10 2 0x000018 IFS0<2> IEC0<2> IPC0<10:8> T1 – Timer1 11 3 0x00001A IFS0<3> IEC0<3> IPC0<14:12> DMA0 – DMA Channel 0 12 4 0x00001C IFS0<4> IEC0<4> IPC1<2:0> IC2 – Input Capture 2 13 5 0x00001E IFS0<5> IEC0<5> IPC1<6:4> OC2 – Output Compare 2 14 6 0x000020 IFS0<6> IEC0<6> IPC1<10:8> T2 – Timer2 15 7 0x000022 IFS0<7> IEC0<7> IPC1<14:12> T3 – Timer3 16 8 0x000024 IFS0<8> IEC0<8> IPC2<2:0> SPI1E – SPI1 Error 17 9 0x000026 IFS0<9> IEC0<9> IPC2<6:4> SPI1 – SPI1 Transfer Done 18 10 0x000028 IFS0<10> IEC0<10> IPC2<10:8> U1RX – UART1 Receiver 19 11 0x00002A IFS0<11> IEC0<11> IPC2<14:12> U1TX – UART1 Transmitter 20 12 0x00002C IFS0<12> IEC0<12> IPC3<2:0> AD1 – ADC1 Convert Done 21 13 0x00002E IFS0<13> IEC0<13> IPC3<6:4> DMA1 – DMA Channel 1 22 14 0x000030 IFS0<14> IEC0<14> IPC3<10:8> NVM–NVM Write Complete 23 15 0x000032 IFS0<15> IEC0<15> IPC3<14:12> SI2C1 – I2C1 Slave Event 24 16 0x000034 IFS1<0> IEC1<0> IPC4<2:0> MI2C1 – I2C1 Master Event 25 17 0x000036 IFS1<1> IEC1<1> IPC4<6:4> CM – Comparator Combined Event 26 18 0x000038 IFS1<2> IEC1<2> IPC4<10:8> CN – Input Change Interrupt 27 19 0x00003A IFS1<3> IEC1<3> IPC4<14:12> INT1 – External Interrupt 1 28 20 0x00003C IFS1<4> IEC1<4> IPC5<2:0> AD2 – ADC2 Convert Done 29 21 0x00003E IFS1<5> IEC1<5> IPC5<6:4> IC7 – Input Capture 7 30 22 0x000040 IFS1<6> IEC1<6> IPC5<10:8> IC8 – Input Capture 8 31 23 0x000042 IFS1<7> IEC1<7> IPC5<14:12> DMA2 – DMA Channel 2 32 24 0x000044 IFS1<8> IEC1<8> IPC6<2:0> OC3 – Output Compare 3 33 25 0x000046 IFS1<9> IEC1<9> IPC6<6:4> OC4 – Output Compare 4 34 26 0x000048 IFS1<10> IEC1<10> IPC6<10:8> T4 – Timer4 35 27 0x00004A IFS1<11> IEC1<11> IPC6<14:12> T5 – Timer5 36 28 0x00004C IFS1<12> IEC1<12> IPC7<2:0> INT2 – External Interrupt 2 37 29 0x00004E IFS1<13> IEC1<13> IPC7<6:4> U2RX – UART2 Receiver 38 30 0x000050 IFS1<14> IEC1<14> IPC7<10:8> U2TX – UART2 Transmitter 39 31 0x000052 IFS1<15> IEC1<15> IPC7<14:12> SPI2E – SPI2 Error 40 32 0x000054 IFS2<0> IEC2<0> IPC8<2:0> SPI2 – SPI2 Transfer Done 41 33 0x000056 IFS2<1> IEC2<1> IPC8<6:4> C1RX – CAN1 RX Data Ready 42 34 0x000058 IFS2<2> IEC2<2> IPC8<10:8> C1 – CAN1 Event 43 35 0x00005A IFS2<3> IEC2<3> IPC8<14:12> DMA3 – DMA Channel 3 44 36 0x00005C IFS2<4> IEC2<4> IPC9<2:0> IC3 – Input Capture 3 45 37 0x00005E IFS2<5> IEC2<5> IPC9<6:4> IC4 – Input Capture 4 46 38 0x000060 IFS2<6> IEC2<6> IPC9<10:8> IC5 – Input Capture 5 47 39 0x000062 IFS2<7> IEC2<7> IPC9<14:12> IC6 – Input Capture 6 48 40 0x000064 IFS2<8> IEC2<8> IPC10<2:0> Note 1: This interrupt source is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. 2: This interrupt source is available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 147

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED) Interrupt Bit Location Vector IVT Interrupt Source IRQ # # Address Flag Enable Priority OC5 – Output Compare 5 49 41 0x000066 IFS2<9> IEC2<9> IPC10<6:4> OC6 – Output Compare 6 50 42 0x000068 IFS2<10> IEC2<10> IPC10<10:8> OC7 – Output Compare 7 51 43 0x00006A IFS2<11> IEC2<11> IPC10<14:12> OC8 – Output Compare 8 52 44 0x00006C IFS2<12> IEC2<12> IPC11<2:0> PMP – Parallel Master Port 53 45 0x00006E IFS2<13> IEC2<13> IPC11<6:4> DMA4 – DMA Channel 4 54 46 0x000070 IFS2<14> IEC2<14> IPC11<10:8> T6 – Timer6 55 47 0x000072 IFS2<15> IEC2<15> IPC11<14:12> T7 – Timer7 56 48 0x000074 IFS3<0> IEC3<0> IPC12<2:0> SI2C2 – I2C2 Slave Event 57 49 0x000076 IFS3<1> IEC3<1> IPC12<6:4> MI2C2 – I2C2 Master Event 58 50 0x000078 IFS3<2> IEC3<2> IPC12<10:8> T8 – Timer8 59 51 0x00007A IFS3<3> IEC3<3> IPC12<14:12> T9 – Timer9 60 52 0x00007C IFS3<4> IEC3<4> IPC13<2:0> INT3 – External Interrupt 3 61 53 0x00007E IFS3<5> IEC3<5> IPC13<6:4> INT4 – External Interrupt 4 62 54 0x000080 IFS3<6> IEC3<6> IPC13<10:8> C2RX – CAN2 RX Data Ready 63 55 0x000082 IFS3<7> IEC3<7> IPC13<14:12> C2 – CAN2 Event 64 56 0x000084 IFS3<8> IEC3<8> IPC14<2:0> PSEM – PWM Special Event Match(1) 65 57 0x000086 IFS3<9> IEC3<9> IPC14<6:4> QEI1 – QEI1 Position Counter 66 58 0x000088 IFS3<10> IEC3<10> IPC14<10:8> Compare(1) DCIE – DCI Fault Interrupt 67 59 0x00008A IFS3<11> IEC3<11> IPC14<14:12> DCI–DCI Transfer Done 68 60 0x00008C IFS3<12> IEC3<12> IPC15<2:0> DMA5 – DMA Channel 5 69 61 0x00008E IFS3<13> IEC3<13> IPC15<6:4> RTC – Real-Time Clock and Calendar 70 62 0x000090 IFS3<14> IEC3<14> IPC15<10:8> Reserved 71-72 63-64 0x000092-0x000094 — — — U1E – UART1 Error Interrupt 73 65 0x000096 IFS4<1> IEC4<1> IPC16<6:4> U2E – UART2 Error Interrupt 74 66 0x000098 IFS4<2> IEC4<2> IPC16<10:8> CRC–CRC Generator Interrupt 75 67 0x00009A IFS4<3> IEC4<3> IPC16<14:12> DMA6 – DMA Channel 6 76 68 0x00009C IFS4<4> IEC4<4> IPC17<2:0> DMA7 – DMA Channel 7 77 69 0x00009E IFS4<5> IEC4<5> IPC17<6:4> C1TX – CAN1 TX Data Request 78 70 0x0000A0 IFS4<6> IEC4<6> IPC17<10:8> C2TX – CAN2 TX Data Request 79 71 0x0000A2 IFS4<7> IEC4<7> IPC17<14:12> Reserved 80 72 0x0000A4 — — — PSESM – PWM Secondary Special 81 73 0x0000A6 IFS4<9> IEC4<9> IPC18<6:4> Event Match(1) Reserved 82 74 0x0000A8 — — — QEI2 – QEI2 Position Counter 83 75 0x0000AA IFS4<11> IEC4<11> IPC18<14:12> Compare(1) Reserved 84-88 76-80 0x0000AC-0x0000B4 — — — U3E – UART3 Error Interrupt 89 81 0x0000B6 IFS5<1> IEC5<1> IPC20<6:4> U3RX – UART3 Receiver 90 82 0x0000B8 IFS5<2> IEC5<2> IPC20<10:8> U3TX – UART3 Transmitter 91 83 0x0000BA IFS5<3> IEC5<3> IPC20<14:12> Reserved 9293 84-85 0x0000BC-0x0000BE — — — Note 1: This interrupt source is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. 2: This interrupt source is available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices only. DS70616G-page 148  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED) Interrupt Bit Location Vector IVT Interrupt Source IRQ # # Address Flag Enable Priority USB1 – USB OTG Interrupt(2) 94 86 0x0000C0 IFS5<6> IEC5<6> IPC21<10:8> U4E – UART4 Error Interrupt 95 87 0x0000C2 IFS5<7> IEC5<7> IPC21<14:12> U4RX – UART4 Receiver 96 88 0x0000C4 IFS5<8> IEC5<8> IPC22<2:0> U4TX – UART4 Transmitter 97 89 0x0000C6 IFS5<9> IEC5<9> IPC22<6:4> SPI3E – SPI3 Error 98 90 0x0000C8 IFS5<10> IEC5<10> IPC22<10:8> SPI3 – SPI3 Transfer Done 99 91 0x0000CA IFS5<11> IEC5<11> IPC22<14:12> OC9 – Output Compare 9 100 92 0x0000CC IFS5<12> IEC5<12> IPC23<2:0> IC9 – Input Capture 9 101 93 0x0000CE IFS5<13> IEC5<13> IPC23<6:4> PWM1 – PWM Generator 1(1) 102 94 0x0000D0 IFS5<14> IEC5<14> IPC23<10:8> PWM2 – PWM Generator 2(1) 103 95 0x0000D2 IFS5<15> IEC5<15> IPC23<14:12> PWM3 – PWM Generator 3(1) 104 96 0x0000D4 IFS6<0> IEC6<0> IPC24<2:0> PWM4 – PWM Generator 4(1) 105 97 0x0000D6 IFS6<1> IEC6<1> IPC24<6:4> PWM5 – PWM Generator 5(1) 106 98 0x0000D8 IFS6<2> IEC6<2> IPC24<10:8> PWM6 – PWM Generator 6(1) 107 99 0x0000DA IFS6<3> IEC6<3> IPC24<14:12> PWM7 – PWM Generator 7(1) 108 100 0x0000DC IFS6<4> IEC6<4> IPC25<2:0> Reserved 109-125 101-117 0x0000DE-0x0000FC — — — DMA8 – DMA Channel 8 126 118 0x000100 IFS7<6> IEC7<6> IPC29<10:8> DMA9 – DMA Channel 9 127 119 0x000102 IFS7<7> IEC7<7> IPC29<14:12> DMA10 – DMA Channel 10 128 120 0x000104 IFS7<8> IEC7<8> IPC30<2:0> DMA11 – DMA Channel 11 129 121 0x000106 IFS7<9> IEC7<9> IPC30<6:4> SPI4E – SPI4 Error 130 122 0x000108 IFS7<10> IEC7<10> IPC30<10:8> SPI4 – SPI4 Transfer Done 131 123 0x00010A IFS7<11> IEC7<11> IPC30<14:12> OC10 – Output Compare 10 132 124 0x00010C IFS7<12> IEC7<12> IPC31<2:0> IC10 – Input Capture 10 133 125 0x00010E IFS7<13> IEC7<13> IPC31<6:4> OC11 – Output Compare11 134 126 0x000110 IFS7<14> IEC7<14> IPC31<10:8> IC11 – Input Capture 11 135 127 0x000112 IFS7<15> IEC7<15> IPC31<14:12> OC12 – Output Compare 12 136 128 0x000114 IFS8<0> IEC8<0> IPC32<2:0> IC12 – Input Capture 12 137 129 0x000116 IFS8<1> IEC8<1> IPC32<6:4> DMA12 – DMA Channel 12 138 130 0x000118 IFS8<2> IEC8<2> IPC32<10:8> DMA13– DMA Channel 13 139 131 0x00011A IFS8<3> IEC8<3> IPC32<14:12> DMA14 – DMA Channel 14 140 132 0x00011C IFS8<4> IEC8<4> IPC33<2:0> Reserved 141 133 0x00011E — — — OC13 – Output Compare 13 142 134 0x000120 IFS8<6> IEC8<6> IPC33<10:8> IC13 – Input Capture 13 143 135 0x000122 IFS8<7> IEC8<7> IPC33<14:12> OC14 – Output Compare14 144 136 0x000124 IFS8<8> IEC8<8> IPC34<2:0> IC14 – Input Capture 14 145 137 0x000126 IFS8<9> IEC8<9> IPC34<6:4> OC15 – Output Compare 15 146 138 0x000128 IFS8<10> IEC8<10> IPC34<10:8> IC15 – Input Capture 15 147 139 0x00012A IFS8<11> IEC8<11> IPC34<14:12> OC16 – Output Compare 16 148 140 0x00012C IFS8<12> IEC8<12> IPC35<2:0> IC16 – Input Capture 16 149 141 0x00012E IFS8<13> IEC8<13> IPC35<6:4> ICD–ICD Application 150 142 0x000130 IFS8<14> IEC8<14> IPC35<10:8> Reserved 151-245 142-237 0x000130-0x0001FE — — — Lowest Natural Order Priority Note 1: This interrupt source is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. 2: This interrupt source is available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 149

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 7.4 Interrupt Resources 7.5.2 IFSx Many useful resources related to Interrupts are pro- The IFS registers maintain all of the interrupt request vided on the main product page of the Microchip web flags. Each source of interrupt has a status bit, which is site for the devices listed in this data sheet. This set by the respective peripherals or external signal and product page, which can be accessed using this link, is cleared via software. contains the latest updates and additional information. 7.5.3 IECx Note: In the event you are not able to access the The IEC registers maintain all of the interrupt enable product page using the link above, enter bits. These control bits are used to individually enable this URL in your browser: interrupts from the peripherals or external signals. http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en554310 7.5.4 IPCx 7.4.1 KEY RESOURCES The IPC registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt • Section 6. “Interrupts” (DS70600) in the source can be assigned to one of eight priority levels. “dsPIC33E/PIC24E Family Reference Manual” • Code Samples 7.5.5 INTTREG • Application Notes The INTTREG register contains the associated • Software Libraries interrupt vector number and the new CPU Interrupt • Webinars Priority Level, which are latched into the vector number (VECNUM<7:0>) and Interrupt level bit (ILR<3:0>) • All related “dsPIC33E/PIC24E Family Reference fields in the INTTREG register. The new Interrupt Manual” Sections Priority Level is the priority of the pending interrupt. • Development Tools The interrupt sources are assigned to the IFSx, IECx 7.5 Interrupt Control and Status and IPCx registers in the same sequence as they are listed in Table7-1. For example, the INT0 (External Registers Interrupt 0) is shown as having Vector Number 8 and a dsPIC33EPXXX(GP/MC/MU)806/810/814 and natural order priority of 0. Thus, the INT0IF bit is found PIC24EPXXX(GP/GU)810/814 devices implement in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IP the following registers for the interrupt controller: bits in the first position of IPC0 (IPC0<2:0>). • INTCON1-INTCON4 7.5.6 STATUS/CONTROL REGISTERS • INTTREG Although these registers are not specifically part of the 7.5.1 INTCON1 THROUGH INTCON4 interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. Global interrupt control functions are controlled from For more information on these registers refer to INTCON1, INTCON2, INTCON3 and INTCON4. Section 2. “CPU” (DS70359) in the “dsPIC33E/ INTCON1 contains the Interrupt Nesting Disable bit PIC24E Family Reference Manual”. (NSTDIS) as well as the control and status flags for the • The CPU STATUS register, SR, contains the processor trap sources. IPL<2:0> bits (SR<7:5>). These bits indicate the The INTCON2 register controls external interrupt current CPU Interrupt Priority Level. The user request signal behavior and software trap enable. This software can change the current CPU priority register also contains the Global Interrupt Enable bit level by writing to the IPL bits. (GIE). • The CORCON register contains the IPL3 bit INTCON3 contains the status flags for the USB, DMA which, together with IPL<2:0>, also indicates the and DO stack overflow status trap sources. current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user The INTCON4 register contains the software software. generated Hard Trap Status bit (SGHT). All Interrupt registers are described in Register7-3 through Register7-7 in the following pages. DS70616G-page 150  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0>(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15, user interrupts are disabled) 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register 3-1: “SR: CPU Status Register”. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL, if IPL<3> = 1. 3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.  2009-2012 Microchip Technology Inc. DS70616G-page 151

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 VAR — US<1:0> EDT DL<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 VAR: Variable Exception Processing Latency Control bit 1 = Variable exception processing is enabled 0 = Fixed exception processing is enabled bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70616G-page 152  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR(1) OVBERR(1) COVAERR(1) COVBERR(1) OVATE(1) OVBTE(1) COVTE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR(1) DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit(1) 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit(1) 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit(1) 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit(1) 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit(1) 1 = Trap overflow of Accumulator A 0 = Trap is disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit(1) 1 = Trap overflow of Accumulator B 0 = Trap is disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit(1) 1 = Trap on catastrophic overflow of Accumulator A or B is enabled 0 = Trap is disabled bit 7 SFTACERR: Shift Accumulator Error Status bit(1) 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Divide-by-Zero Error Status bit 1 = Math error trap was caused by a divide-by-zero 0 = Math error trap was not caused by a divide-by-zero bit 5 DMACERR: DMAC Trap Flag bit 1 = DMAC trap has occurred 0 = DMAC trap has not occurred Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 153

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 4 MATHERR: Math Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. DS70616G-page 154  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 GIE DISI SWTRAP — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 GIE: Global Interrupt Enable bit 1 = Interrupts and associated IE bits are enabled 0 = Interrupts are disabled, but traps are still enabled bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13 SWTRAP: Software Trap Status bit 1 = Software trap is enabled 0 = Software trap is disabled bit 12-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2009-2012 Microchip Technology Inc. DS70616G-page 155

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 7-5: INTCON3: INTERRUPT CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — UAE DAE DOOVR — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 UAE: USB Address Error Soft Trap Status bit 1 = USB address error (soft) trap has occurred 0 = USB address error (soft) trap has not occurred bit 5 DAE: DMA Address Error Soft Trap Status bit 1 = DMA address error soft trap has occurred 0 = DMA address error soft trap has not occurred bit 4 DOOVR: Do Stack Overflow Soft Trap Status bit 1 = Do stack overflow soft trap has occurred 0 = Do stack overflow soft trap has not occurred bit 3-0 Unimplemented: Read as ‘0’ REGISTER 7-6: INTCON4: INTERRUPT CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SGHT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 SGHT: Software Generated Hard Trap Status bit 1 = Software generated hard trap has occurred 0 = Software generated hard trap has not occurred DS70616G-page 156  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 7-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR<3:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VECNUM<7:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7-0 VECNUM<7:0>: Vector Number of Pending Interrupt bits(1) 11111111 = 255, Reserved • • • 00001001 = 9, IC1 – Input Capture 1 00001000 = 8, INT0 – External Interrupt 0 00000111 = 7, Reserved 00000110 = 6, Generic soft error trap 00000101 = 5, DMAC error trap 00000100 = 4, Math error trap 00000011 = 3, Stack error trap 00000010 = 2, Generic hard trap 00000001 = 1, Address error trap 00000000 = 0, Oscillator fail trap Note 1: See Table7-1 for the complete list of interrupt vector numbers.  2009-2012 Microchip Technology Inc. DS70616G-page 157

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 158  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 8.0 DIRECT MEMORY ACCESS addresses within data space without interference, such (DMA) as CPU stalls, resulting in maximized, real-time performance. Alternatively, DMA operation and data Note1: This data sheet summarizes the features transfer to/from the memory and peripherals are not of the dsPIC33EPXXX(GP/MC/MU)806/ impacted by CPU processing. For example, when a 810/814 and PIC24EPXXX(GP/GU)810/ Run-Time Self-Programming (RTSP) operation is 814 families of devices. It is not intended performed, the CPU does not execute any instructions to be a comprehensive reference source. until RTSP is finished. This condition, however, does To complement the information in this not impact data transfer to/from memory and the data sheet, refer to Section 22. “Direct peripherals. Memory Access (DMA)” (DS70348) In addition, DMA can access entire data memory space of the “dsPIC33E/PIC24E Family (SRAM and DPSRAM). The Data Memory Bus Arbiter Reference Manual”, which is available is utilized when either the CPU or DMA attempts to from the Microchip web site access non-dual ported SRAM, resulting in potential (www.microchip.com). DMA or CPU stalls. 2: Some registers and associated bits The DMA controller supports up to 15 independent described in this section may not be channels. Each channel can be configured for transfers available on all devices. Refer to to or from selected peripherals. Some of the Section4.0 “Memory Organization” in peripherals supported by the DMA controller include: this data sheet for device-specific register • ECAN™ and bit information. • Data Converter Interface (DCI) The DMA controller transfers data between • Analog-to-Digital Converter (ADC) peripheral data registers and data space SRAM. • Serial Peripheral Interface (SPI) The dsPIC33EPXXX(GP/MC/MU)806/810/814 and • UART PIC24EPXXX(GP/GU)810/814 DMA subsystem uses • Input Capture dual-ported SRAM memory (DPSRAM) and register structures that allow the DMA to operate across its • Output Compare own, independent address and data buses with no • Parallel Master Port (PMP) impact on CPU operation. This architecture eliminates Refer to Table8-1 for a complete list of supported the need for cycle stealing, which halts the CPU when peripherals. a higher priority DMA transfer is requested. Both the CPU and DMA controller can write and read to/from FIGURE 8-1: DMA CONTROLLER DPSRAM PERIPHERAL DMA Arbiter SRAM  2009-2012 Microchip Technology Inc. DS70616G-page 159

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 In addition, DMA transfers can be triggered by timers • Peripheral Indirect Addressing mode (peripheral as well as external interrupts. Each DMA channel is generates destination address) unidirectional. Two DMA channels must be allocated to • CPU Interrupt after Half or Full Block Transfer read and write to a peripheral. If more than one channel Complete receive a request to transfer data, a simple fixed priority • Byte or Word Transfers scheme, based on channel number, dictates which • Fixed Priority Channel Arbitration channel completes the transfer and which channel, or channels, are left pending. Each DMA channel moves • Manual (software) or Automatic (peripheral DMA a block of data, after which it generates an interrupt to requests) Transfer Initiation the CPU to indicate that the block is available for • One-Shot or Auto-Repeat Block Transfer modes processing. • Ping-Pong mode (automatic switch between two The DMA controller provides these functional DPSRAM start addresses after each block capabilities: transfer complete) • DMA Request for Each Channel can be Selected • Up to 15 DMA Channels from Any Supported Interrupt Source • Register Indirect With Post-Increment Addressing • Debug Support Features mode • Register Indirect Without Post-Increment The peripherals that can utilize DMA are listed in Addressing mode Table8-1. TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS DMAxPAD Register DMAxPAD Register DMAxREQ Register Peripheral to DMA Association (Values to Read from (Values to Write to IRQSEL<7:0> Bits Peripheral) Peripheral) INT0 – External Interrupt 0 00000000 — — IC1 – Input Capture 1 00000001 0x0144 (IC1BUF) — IC2 – Input Capture 2 00000101 0x014C (IC2BUF) — IC3 – Input Capture 3 00100101 0x0154 (IC3BUF) — IC4 – Input Capture 4 00100110 0x015C (IC4BUF) — OC1 – Output Compare 1 00000010 — 0x0906 (OC1R) 0x0904 (OC1RS) OC2 – Output Compare 2 00000110 — 0x0910 (OC2R) 0x090E (OC2RS) OC3 – Output Compare 3 00011001 — 0x091A (OC3R) 0x0918 (OC3RS) OC4 – Output Compare 4 00011010 — 0x0924 (OC4R) 0x0922 (OC4RS) TMR2 – Timer2 00000111 — — TMR3 – Timer3 00001000 — — TMR4 – Timer4 00011011 — — TMR5 – Timer5 00011100 — — SPI1 Transfer Done 00001010 0x0248 (SPI1BUF) 0x0248 (SPI1BUF) SPI2 Transfer Done 00100001 0x0268 (SPI2BUF) 0x0268 (SPI2BUF) SPI3 Transfer Done 01011011 0x02A8 (SPI3BUF) 0x02A8 (SPI3BUF) SPI4 Transfer Done 01111011 0x02C8 (SPI4BUF) 0x02C8 (SPI4BUF) UART1RX – UART1 Receiver 00001011 0x0226 (U1RXREG) — UART1TX – UART1 Transmitter 00001100 — 0x0224 (U1TXREG) UART2RX – UART2 Receiver 00011110 0x0236 (U2RXREG) — UART2TX – UART2 Transmitter 00011111 — 0x0234 (U2TXREG) UART3RX – UART3 Receiver 01010010 0x0256 (U3RXREG) — UART3TX – UART3 Transmitter 01010011 — 0x0254 (U3TXREG) DS70616G-page 160  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS (CONTINUED) DMAxPAD Register DMAxPAD Register DMAxREQ Register Peripheral to DMA Association (Values to Read from (Values to Write to IRQSEL<7:0> Bits Peripheral) Peripheral) UART4RX – UART4 Receiver 01011000 0x02B6 (U4RXREG) — UART4TX – UART4 Transmitter 01011001 — 0x02B4 (U4TXREG) ECAN1 – RX Data Ready 00100010 0x0440 (C1RXD) — ECAN1 – TX Data Request 01000110 — 0x0442 (C1TXD) ECAN2 – RX Data Ready 00110111 0x0540 (C2RXD) — ECAN2 – TX Data Request 01000111 — 0x0542 (C2TXD) DCI–DCI Transfer Done 00111100 0x0290 (RXBUF0) 0x0298 (TXBUF0) ADC1 – ADC1 Convert Done 00001101 0x0300 (ADC1BUF0) — ADC2 – ADC2 Convert Done 00010101 0x0340 (ADC2BUF0) — PMP–PMP Data Move 00101101 0x0608 (PMDIN1) 0x0608 (PMDIN1) FIGURE 8-2: DMA CONTROLLER TO PERIPHERAL ASSOCIATIONS BLOCK DIAGRAM SRAM Peripheral Indirect Address DMA Controller Arbiter DMA IRQ to DMA MAntrol ChDaMnnAels PerRipehaedryal 1 anCdo Innttreorllreurp t DPSRAM DCo 0 1 2 3 4 · · N Modules CPU DMA PORT 1 PORT 2 SRAM X-Bus DMA X-Bus CPU Peripheral X-Bus CPU DMA CPU DMA Non-DMA DMA DMA CPU Ready Ready Peripheral Peripheral 2 Peripheral 3 IRQ to DMA and IRQ to DMA and Interrupt Controller Interrupt Controller Modules Modules Note: CPU and DMA address buses are not shown for clarity.  2009-2012 Microchip Technology Inc. DS70616G-page 161

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 8.1 DMA Resources 8.2 DMA Control Registers Many useful resources related to DMA are provided on Each DMAC Channel x (where x = 0 through 14) the main product page of the Microchip web site for the contains the following registers: devices listed in this data sheet. This product page, • 16-Bit DMA Channel Control register (DMAxCON) which can be accessed using this link, contains the • 16-Bit DMA Channel IRQ Select register latest updates and additional information. (DMAxREQ) Note: In the event you are not able to access the • 32-Bit DMA RAM Primary Start Address register product page using the link above, enter (DMAxSTA) this URL in your browser: • 32-Bit DMA RAM Secondary Start Address http://www.microchip.com/wwwproducts/ register (DMAxSTB) Devices.aspx?dDocName=en554310 • 16-Bit DMA Peripheral Address register (DMAxPAD) 8.1.1 KEY RESOURCES • 14-Bit DMA Transfer Count register (DMAxCNT) Additional status registers (DMAPWC, DMARQC, • Section 22. “Direct Memory Access (DMA)” DMAPPS, DMALCA and DSADR) are common to all (DS70348) in the “dsPIC33E/PIC24E Family DMAC channels. These status registers provide infor- Reference Manual” mation on write and request collisions, as well as on • Code Samples last address and channel access information. • Application Notes The DMA Interrupt Flags (DMAxIF) are located in an • Software Libraries IFSx register in the interrupt controller. The • Webinars corresponding interrupt enable control bits (DMAxIE) • All related “dsPIC33E/PIC24E Family Reference are located in an IECx register in the interrupt Manual” Sections controller, and the corresponding interrupt priority • Development Tools control bits (DMAxIP) are located in an IPCx register in the interrupt controller. DS70616G-page 162  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-1: DMAXCON: DMA CHANNEL X CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — AMODE<1:0> — — MODE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: Channel Enable bit 1 = Channel is enabled 0 = Channel is disabled bit 14 SIZE: Data Transfer Size bit 1 = Byte 0 = Word bit 13 DIR: Transfer Direction bit (source/destination bus select) 1 = Reads from DPSRAM (or RAM) address, writes to peripheral address 0 = Reads from peripheral address, writes to DPSRAM (or RAM) address bit 12 HALF: Block Transfer Interrupt Select bit 1 = Initiates interrupt when half of the data has been moved 0 = Initiates interrupt when all of the data has been moved bit 11 NULLW: Null Data Peripheral Write Mode Select bit 1 = Null data write to peripheral in addition to DPSRAM (or RAM) write (DIR bit must also be clear) 0 = Normal operation bit 10-6 Unimplemented: Read as ‘0’ bit 5-4 AMODE<1:0>: DMA Channel Addressing Mode Select bits 11 = Reserved 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA buffer) 10 = Continuous, Ping-Pong modes are enabled 01 = One-Shot, Ping-Pong modes are disabled 00 = Continuous, Ping-Pong modes are disabled  2009-2012 Microchip Technology Inc. DS70616G-page 163

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-2: DMAXREQ: DMA CHANNEL X IRQ SELECT REGISTER R/S-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQSEL<7:0> bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Transfer bit(1) 1 = Forces a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request bit 14-8 Unimplemented: Read as ‘0’ bit 7-0 IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits 00000000 = INT0 – External Interrupt 0 00000001 = IC1 – Input Capture 1 00000010 = OC1 – Output Compare 1 00000101 = IC2 – Input Capture 2 00000110 = OC2 – Output Compare 2 00000111 = TMR2 – Timer2 00001000 = TMR3 – Timer3 00001010 = SPI1 – Transfer done 00001011 = UART1RX – UART1 Receiver 00001100 = UART1TX – UART1 Transmitter 00001101 = ADC1 – ADC1 convert done 00010101 = ADC2 – ADC2 convert done 00011001 = OC3 – Output Compare 3 00011010 = OC4 – Output Compare 4 00011011 = TMR4 – Timer4 00011100 = TMR5 – Timer5 00011110 = UART2RX – UART2 Receiver 00011111 = UART2TX – UART2 Transmitter 00100001 = SPI2 – Transfer done 00100010 = ECAN1 – RX data ready 00100101 = IC3 – Input Capture 3 00100110 = IC4 – Input Capture 4 00101101 = PMP Data mode 00110111 = ECAN2 – RX data ready 00111100 = DCI–DCI transfer done 01000110 = ECAN1 – TX data request 01000111 = ECAN2 – TX data request 01010010 = UART3RX – UART3 Receiver 01010011 = UART3TX – UART3 Transmitter 01011000 = UART4RX – UART4 Receiver 01011001 = UART4TX – UART4 Transmitter 01011011 = SPI3 – Transfer done 01111011 = SPI4 – Transfer done Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the forced DMA transfer is complete or the channel is disabled (CHEN = 0). DS70616G-page 164  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-3: DMAXSTAH: DMA CHANNEL X START ADDRESS REGISTER A (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 STA<23:16>: Primary Start Address bits (source or destination) REGISTER 8-4: DMAXSTAL: DMA CHANNEL X START ADDRESS REGISTER A (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STA<15:0>: Primary Start Address bits (source or destination)  2009-2012 Microchip Technology Inc. DS70616G-page 165

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-5: DMAXSTBH: DMA CHANNEL X START ADDRESS REGISTER B (HIGH) U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 STB<23:16>: Secondary Start Address bits (source or destination) REGISTER 8-6: DMAXSTBL: DMA CHANNEL X START ADDRESS REGISTER B (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STB<15:0>: Secondary Start Address bits (source or destination) DS70616G-page 166  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-7: DMAXPAD: DMA CHANNEL X PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PAD<15:0>: Peripheral Address Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 8-8: DMAXCNT: DMA CHANNEL X TRANSFER COUNT REGISTER(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CNT<13:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 CNT<13:0>: DMA Transfer Count Register bits(2) Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: The number of DMA transfers = CNT<13:0> + 1.  2009-2012 Microchip Technology Inc. DS70616G-page 167

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-9: DSADRH: MOST RECENT DMA DATA SPACE HIGH ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 DSADR<23:16>: Most Recent DMA Address Accessed by DMA bits REGISTER 8-10: DSADRL: MOST RECENT DMA DATA SPACE LOW ADDRESS REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits DS70616G-page 168  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — PWCOL14 PWCOL13 PWCOL12 PWCOL11 PWCOL10 PWCOL9 PWCOL8 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 PWCOL14: Channel 14 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 13 PWCOL13: Channel 13 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 12 PWCOL12: Channel 12 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 11 PWCOL11: Channel 11 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 10 PWCOL10: Channel 10 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 9 PWCOL9: Channel 9 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 8 PWCOL8: Channel 8 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 7 PWCOL7: Channel 7 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 6 PWCOL6: Channel 6 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 5 PWCOL5: Channel 5 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 4 PWCOL4: Channel 4 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 3 PWCOL3: Channel 3 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected  2009-2012 Microchip Technology Inc. DS70616G-page 169

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER (CONTINUED) bit 2 PWCOL2: Channel 2 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 1 PWCOL1: Channel 1 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 0 PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected DS70616G-page 170  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — RQCOL14 RQCOL13 RQCOL12 RQCOL11 RQCOL10 RQCOL9 RQCOL8 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RQCOL7 RQCOL6 RQCOL5 RQCOL4 RQCOL3 RQCOL2 RQCOL1 RQCOL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RQCOL14: Channel 14 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 13 RQCOL13: Channel 13 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 12 RQCOL12: Channel 12 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 11 RQCOL11: Channel 11 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 10 RQCOL10: Channel 10 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 9 RQCOL9: Channel 9 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 8 RQCOL8: Channel 8 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 7 RQCOL7: Channel 7 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 6 RQCOL6: Channel 6 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 5 RQCOL5: Channel 5 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 4 RQCOL4: Channel 4 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 3 RQCOL3: Channel 3 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected  2009-2012 Microchip Technology Inc. DS70616G-page 171

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER (CONTINUED) bit 2 RQCOL2: Channel 2 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 1 RQCOL1: Channel 1 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected bit 0 RQCOL0: Channel 0 Transfer Request Collision Flag bit 1 = User FORCE and interrupt-based request collision detected 0 = No request collision detected DS70616G-page 172  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1 — — — — LSTCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 LSTCH<3:0>: Last DMAC Channel Active Status bits 1111 = No DMA transfer has occurred since system Reset 1110 = Last data transfer was handled by Channel 14 1101 = Last data transfer was handled by Channel 13 1100 = Last data transfer was handled by Channel 12 1011 = Last data transfer was handled by Channel 11 1010 = Last data transfer was handled by Channel 10 1001 = Last data transfer was handled by Channel 9 1000 = Last data transfer was handled by Channel 8 0111 = Last data transfer was handled by Channel 7 0110 = Last data transfer was handled by Channel 6 0101 = Last data transfer was handled by Channel 5 0100 = Last data transfer was handled by Channel 4 0011 = Last data transfer was handled by Channel 3 0010 = Last data transfer was handled by Channel 2 0001 = Last data transfer was handled by Channel 1 0000 = Last data transfer was handled by Channel 0  2009-2012 Microchip Technology Inc. DS70616G-page 173

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — PPST14 PPST13 PPST12 PPST11 PPST10 PPST9 PPST8 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 PPST14: Channel 14 Ping-Pong Mode Status Flag bit 1 = DMASTB14 register selected 0 = DMASTA14 register selected bit 13 PPST13: Channel 13 Ping-Pong Mode Status Flag bit 1 = DMASTB13 register selected 0 = DMASTA13 register selected bit 12 PPST12: Channel 12 Ping-Pong Mode Status Flag bit 1 = DMASTB12 register selected 0 = DMASTA12 register selected bit 11 PPST11: Channel 11 Ping-Pong Mode Status Flag bit 1 = DMASTB11 register selected 0 = DMASTA11 register selected bit 10 PPST10: Channel 10 Ping-Pong Mode Status Flag bit 1 = DMASTB10 register selected 0 = DMASTA10 register selected bit 9 PPST9: Channel 9 Ping-Pong Mode Status Flag bit 1 = DMASTB9 register selected 0 = DMASTA9 register selected bit 8 PPST8: Channel 8 Ping-Pong Mode Status Flag bit 1 = DMASTB8 register selected 0 = DMASTA8 register selected bit 7 PPST7: Channel 7 Ping-Pong Mode Status Flag bit 1 = DMASTB7 register selected 0 = DMASTA7 register selected bit 6 PPST6: Channel 6 Ping-Pong Mode Status Flag bit 1 = DMASTB6 register selected 0 = DMASTA6 register selected bit 5 PPST5: Channel 5 Ping-Pong Mode Status Flag bit 1 = DMASTB5 register selected 0 = DMASTA5 register selected bit 4 PPST4: Channel 4 Ping-Pong Mode Status Flag bit 1 = DMASTB4 register selected 0 = DMASTA4 register selected bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMASTB3 register selected 0 = DMASTA3 register selected DS70616G-page 174  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER (CONTINUED) bit 2 PPST2: Channel 2 Ping-Pong Mode Status Flag bit 1 = DMASTB2 register selected 0 = DMASTA2 register selected bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMASTB1 register selected 0 = DMASTA1 register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMASTB0 register selected 0 = DMASTA0 register selected  2009-2012 Microchip Technology Inc. DS70616G-page 175

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 176  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 9.0 OSCILLATOR CONFIGURATION The oscillator system provides: • Four external and internal oscillator options Note1: This data sheet summarizes the features • Auxiliary oscillator that provides clock source to of the dsPIC33EPXXX(GP/MC/MU)806/ the USB module (if available) 810/814 and PIC24EPXXX(GP/GU)810/ 814 families of devices. It is not intended • On-chip Phase-Locked Loop (PLL) to boost to be a comprehensive reference source. internal operating frequency on select internal and To complement the information in this external oscillator sources data sheet, refer to Section 7. “Oscil- • On-the-fly clock switching between various clock lator” (DS70580) of the “dsPIC33E/ sources PIC24E Family Reference Manual”, • Doze mode for system power savings which is available from the Microchip web • Fail-Safe Clock Monitor (FSCM) that detects clock site (www.microchip.com). failure and permits safe application recovery or 2: Some registers and associated bits shutdown described in this section may not be • Nonvolatile Configuration bits for clock source available on all devices. Refer to selection Section4.0 “Memory Organization” in A simplified diagram of the oscillator system is shown this data sheet for device-specific register in Figure9-1. and bit information.  2009-2012 Microchip Technology Inc. DS70616G-page 177

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 9-1: OSCILLATOR SYSTEM DIAGRAM Primary Oscillator (POSC) DOZE<2:0> OSC1 POSCCLK XT, HS, EC S2 R(2) SS31 PLL(1) EXCTPPLLLL, ,F HRSCPPLLLL, S1/S3 OZE FCY OSC2 FVCO(1) D POSCMD<1:0> FP FRC FRCCLK DIV FRCDIVN ÷ 2 Oscillator C S7 R F FOSC FRCDIV<2:0> TUN<5:0> Reference Clock Generation FRCDIV16 ÷ 16 S6 POSCCLK FRC OLscPiRllaCtor LPRC SS05 FOSC ÷ N REFCLKO RPn Secondary Oscillator (SOSC) ROSEL RODIV<3:0> SOSC SOSCO S4 LPOSCEN SOSCI Clock Fail Clock Switch Reset WDT, PWRT, S7 NOSC<2:0> FNOSC<2:0> FSCM Auxiliary Clock Generation (dsPIC33EPXXMU8XX and Timer1 PIC24EPXXXGU8XX Devices Only) Auxiliary Oscillator POSCCLK FRCCLK FVCO(1) APLL(3) FAVCO ÷ N ACLK USB ENAPLL ASRCSEL FRCSEL ENAPLL SELACLK APLLPOST<2:0> Note 1: See Figure9-2 for PLL and FVCO details. 2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1Mmust be connected. 3: See Figure9-3 for APLL details. DS70616G-page 178  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 9.1 CPU Clocking System Instruction execution speed or device operating frequency, FCY, is given by Equation9-1. The dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 family of devices EQUATION 9-1: DEVICE OPERATING provides seven system clock options: FREQUENCY • Fast RC (FRC) Oscillator FCY = FOSC/2 • FRC Oscillator with Phase-Locked Loop (PLL) • Primary (XT, HS or EC) Oscillator Figure9-2 is a block diagram of the PLL module. • Primary Oscillator with PLL Equation9-2 provides the relation between input • Secondary (LP) Oscillator frequency (FIN) and output frequency (FOSC). • Low-Power RC (LPRC) Oscillator Equation9-3 provides the relation between input • FRC Oscillator with postscaler frequency (FIN) and VCO frequency (FVCO). FIGURE 9-2: PLL BLOCK DIAGRAM 0.8 MHz < FREF < 8.0 MHz 120 MHZ < FVCO < 340 MHZ FOSC < 120 MHz @ +125ºC FOSC < 140 MHz @ +85ºC FIN FREF FVCO FOSC ÷ N1 PFD VCO ÷ N2 PLLPRE<4:0> PLLPOST<2:0> ÷ M PLLDIV<8:0> EQUATION 9-2: FOSC CALCULATION FOSC = FIN---------M------------ = FIN-----------------------------P----L----L---D-----I--V-----+-----2------------------------------- N1N2 PLLPRE+22PLLPOST+1 Where, N1 = PLLPRE + 2 N2 = 2 x (PLLPOST + 1) M = PLLDIV + 2 EQUATION 9-3: FVCO CALCULATION FVCO = FIN--M----- = FIN---P----L----L----D-----I--V-----+-----2----- N1 PLLPRE+2  2009-2012 Microchip Technology Inc. DS70616G-page 179

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Figure9-3 illustrates a block diagram of the auxiliary PLL module. Note: The auxiliary PLL module is only avail- able on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. FIGURE 9-3: APLL BLOCK DIAGRAM 3 MHz < FAREF < 5.5 MHz 60 MHZ < FAVCO < 120 MHZ FAIN FAREF FAVCO ÷ N1 PFD VCO APLLPRE<2:0> ÷ M APLLDIV<2:0> Equation9-4 shows the relationship between the EQUATION 9-4: FAVCO CALCULATION auxiliary PLL input clock frequency (FAIN) and the AVCO frequency (FAVCO). FAVCO = FAIN--M----- N1 DS70616G-page 180  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator See Oscillator Mode POSCMD<1:0> FNOSC<2:0> Source Notes Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1 Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 — Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 — Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1 Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator (FRC) with Divide-by-N and PLL Internal xx 001 1 (FRCPLL) Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. 9.2 Oscillator Resources 9.2.1 KEY RESOURCES Many useful resources related to the Oscillator are • Section 7. “Oscillator” (DS70580) in the provided on the main product page of the Microchip “dsPIC33E/PIC24E Family Reference Manual” web site for the devices listed in this data sheet. This • Code Samples product page, which can be accessed using this link, • Application Notes contains the latest updates and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All related “dsPIC33E/PIC24E Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en554310  2009-2012 Microchip Technology Inc. DS70616G-page 181

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 9.3 Oscillator Control Registers REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y — COSC<2:0> — NOSC<2:0>(2) bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value Set from Configuration bits on POR C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 111 = Fast RC Oscillator (FRC) with Divide-by-N 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 111 = Fast RC Oscillator (FRC) with Divide-by-N 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL 000 = Fast RC Oscillator (FRC) bit 7 CLKLOCK: Clock Lock Enable bit 1 = If (FCKSM0=1), then clock and PLL configurations are locked If (FCKSM0=0), then clock and PLL configurations may be modified 0 = Clock and PLL selections are not locked, configurations may be modified bit 6 IOLOCK: I/O Lock Enable bit 1 = I/O lock is active 0 = I/O lock is not active bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70580) in the “dsPIC33E/PIC24E Family Reference Manual” (available from the Microchip web site) for details. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit- ted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register resets only on a Power-on Reset (POR). DS70616G-page 182  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enables Secondary Oscillator 0 = Disables Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Requests oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70580) in the “dsPIC33E/PIC24E Family Reference Manual” (available from the Microchip web site) for details. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit- ted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register resets only on a Power-on Reset (POR).  2009-2012 Microchip Technology Inc. DS70616G-page 183

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER(2) R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE<2:0>(3) DOZEN(1,4) FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST<1:0> — PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock and peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(3) 111 = FCY divided by 128 110 = FCY divided by 64 101 = FCY divided by 32 100 = FCY divided by 16 011 = FCY divided by 8 (default) 010 = FCY divided by 4 001 = FCY divided by 2 000 = FCY divided by 1 bit 11 DOZEN: Doze Mode Enable bit(1,4) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock and peripheral clock ratio forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 000 = FRC divided by 1 (default) bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 11 = Output divided by 8 10 = Reserved 01 = Output divided by 4 (default) 00 = Output divided by 2 bit 5 Unimplemented: Read as ‘0’ Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register resets only on a Power-on Reset (POR). 3: DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to DOZE<2:0> are ignored. 4: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to set the DOZEN bit is ignored. DS70616G-page 184  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER(2) (CONTINUED) bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler) 11111 = Input divided by 33 • • • 00001 = Input divided by 3 00000 = Input divided by 2 (default) Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register resets only on a Power-on Reset (POR). 3: DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to DOZE<2:0> are ignored. 4: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to set the DOZEN bit is ignored.  2009-2012 Microchip Technology Inc. DS70616G-page 185

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • • • 000110000 = 50 (default) • • • 000000010 = 4 000000001 = 3 000000000 = 2 Note 1: This register is reset only on a Power-on Reset (POR). DS70616G-page 186  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Center frequency + 11.625% (8.23 MHz) 011110 = Center frequency + 11.25% (8.20 MHz) • • • 000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.375% (7.345 MHz) • • • 100001 = Center frequency – 11.625% (6.52 MHz) 100000 = Center frequency – 12% (6.49 MHz) Note 1: This register resets only on a Power-on Reset (POR).  2009-2012 Microchip Technology Inc. DS70616G-page 187

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 9-5: ACLKCON3: AUXILIARY CLOCK CONTROL REGISTER 3(1,2) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 ENAPLL — SELACLK AOSCMD<1:0> ASRCSEL FRCSEL — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 APLLPOST<2:0> — — APLLPRE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Enable Auxiliary PLL (APLL) and Select APLL as USB Clock Source bit 1 = APLL is enabled, the USB clock source is the APLL output 0 = APLL is disabled, the USB clock source is the input clock to the APLL bit 14 Unimplemented: Read as ‘0’ bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit 1 = Auxiliary PLL or oscillator provides the source clock for auxiliary clock divider 0 = Primary PLL provides the source clock for auxiliary clock divider bit 12-11 AOSCMD<1:0>: Auxiliary Oscillator Mode bits 11 = EC (External Clock) Oscillator mode select 10 = XT (Crystal) Oscillator mode select 01 = HS (High-Speed) Oscillator mode select 00 = Auxiliary Oscillator disabled (default) bit 10 ASRCSEL: Select Reference Clock Source for APLL bit 1 = Primary Oscillator is the clock source for APLL 0 = Auxiliary Oscillator is the clock source for APLL bit 9 FRCSEL: Select FRC as Reference Clock Source for APLL bit 1 = FRC is the clock source for APLL 0 = Auxiliary Oscillator or Primary Oscillator is the clock source for APLL (determined by ASRCSEL bit) bit 8 Unimplemented: Read as ‘0’ bit 7-5 APLLPOST<2:0>: Select PLL VCO Output Divider bits 111 = Divided by 1 110 = Divided by 2 101 = Divided by 4 100 = Divided by 8 011 = Divided by 16 010 = Divided by 32 001 = Divided by 64 000 = Divided by 256 (default) bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 APLLPRE<2:0>: PLL Phase Detector Input Divider bits 111 = Divided by 12 110 = Divided by 10 101 = Divided by 6 100 = Divided by 5 011 = Divided by 4 010 = Divided by 3 001 = Divided by 2 000 = Divided by 1 (default) Note 1: This register resets only on a Power-on Reset (POR). 2: This register is only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices. DS70616G-page 188  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 9-6: ACLKDIV3: AUXILIARY CLOCK DIVISOR REGISTER3(1,2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — APLLDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 APLLDIV<2:0>: PLL Feedback Divisor bits (PLL Multiplier Ratio) 111 = 24 110 = 21 101 = 20 100 = 19 011 = 18 010 = 17 001 = 16 000 = 15 (default) Note 1: This register resets only on a Power-on Reset (POR). 2: This register is only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices.  2009-2012 Microchip Technology Inc. DS70616G-page 189

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 9-7: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL RODIV<3:0>(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is enabled on REFCLK pin(2) 0 = Reference oscillator output is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Run in Sleep bit 1 = Reference oscillator output continues to run in Sleep 0 = Reference oscillator output is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Oscillator crystal used as the reference clock 0 = System clock used as the reference clock bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1) 1111 = Reference clock divided by 32,768 1110 = Reference clock divided by 16,384 1101 = Reference clock divided by 8,192 1100 = Reference clock divided by 4,096 1011 = Reference clock divided by 2,048 1010 = Reference clock divided by 1,024 1001 = Reference clock divided by 512 1000 = Reference clock divided by 256 0111 = Reference clock divided by 128 0110 = Reference clock divided by 64 0101 = Reference clock divided by 32 0100 = Reference clock divided by 16 0011 = Reference clock divided by 8 0010 = Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock bit 7-0 Unimplemented: Read as ‘0’ Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits. 2: This pin is remappable. See Section11.4 “Peripheral Pin Select” for more information. DS70616G-page 190  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 10.0 POWER-SAVING FEATURES 10.2 Instruction-Based Power-Saving Modes Note1: This data sheet summarizes the features of the dsPIC33EPXXX(GP/MC/MU)806/ The dsPIC33EPXXX(GP/MC/MU)806/810/814 and 810/814 and PIC24EPXXX(GP/GU)810/ PIC24EPXXX(GP/GU)810/814 devices have two 814 families of devices. It is not intended special power-saving modes that are entered to be a comprehensive reference source. through the execution of a special PWRSAV To complement the information in this instruction. Sleep mode stops clock operation and data sheet, refer to Section 9. “Watch- halts all code execution. Idle mode halts the CPU dog Timer and Power-Saving Modes” and code execution, but allows peripheral modules (DS70615) of the “dsPIC33E/PIC24E to continue operation. The assembler syntax of the Family Reference Manual”, which is PWRSAV instruction is shown in Example10-1. available from the Microchip web site Note: SLEEP_MODE and IDLE_MODE are con- (www.microchip.com). stants defined in the assembler include 2: Some registers and associated bits file for the selected device. described in this section may not be Sleep and Idle modes can be exited as a result of an available on all devices. Refer to enabled interrupt, WDT time-out or a device Reset. When Section4.0 “Memory Organization” in the device exits these modes, it is said to wake up. this data sheet for device-specific register and bit information. 10.2.1 SLEEP MODE The dsPIC33EPXXX(GP/MC/MU)806/810/814 and The following occur in Sleep mode: PIC24EPXXX(GP/GU)810/814 devices provide the • The system clock source is shut down. If an ability to manage power consumption by selectively on-chip oscillator is used, it is turned off. managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction • The device current consumption is reduced to a in the number of circuits being clocked constitutes minimum, provided that no I/O pin is sourcing lower consumed power. current. • The Fail-Safe Clock Monitor does not operate, dsPIC33EPXXX(GP/MC/MU)806/810/814 and since the system clock source is disabled. PIC24EPXXX(GP/GU)810/814 devices can manage power consumption in four ways: • The LPRC clock continues to run in Sleep mode if the WDT is enabled. • Clock frequency • The WDT, if enabled, is automatically cleared • Instruction-based Sleep and Idle modes prior to entering Sleep mode. • Software-controlled Doze mode • Some device features or peripherals can continue • Selective peripheral control in software to operate. This includes items such as the input Combinations of these methods can be used to selec- change notification on the I/O ports, or peripherals tively tailor an application’s power consumption while that use an external clock input. still maintaining critical application features, such as • Any peripheral that requires the system clock timing-sensitive communications. source for its operation is disabled. The device wakes up from Sleep mode on any of the 10.1 Clock Frequency and Clock these events: Switching • Any interrupt source that is individually enabled The dsPIC33EPXXX(GP/MC/MU)806/810/814 and • Any form of device Reset PIC24EPXXX(GP/GU)810/814 devices allow a wide • A WDT time-out range of clock frequencies to be selected under On wake-up from Sleep mode, the processor restarts application control. If the system clock configuration is with the same clock source that was active when Sleep not locked, users can choose low-power or high- mode was entered. precision oscillators by simply changing the NOSCx bits (OSCCON<10:8>). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section9.0 “Oscillator Configuration”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2009-2012 Microchip Technology Inc. DS70616G-page 191

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 10.2.2 IDLE MODE Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core The following occur in Idle mode: clock speed is determined by the DOZE<2:0> bits • The CPU stops executing instructions. (CLKDIV<14:12>). There are eight possible configu- • The WDT is automatically cleared. rations, from 1:1 to 1:128, with 1:1 being the default • The system clock source remains active. By setting. default, all peripheral modules continue to operate Programs can use Doze mode to selectively reduce normally from the system clock source, but can power consumption in event-driven applications. This also be selectively disabled (see Section10.4 allows clock-sensitive functions, such as synchronous “Peripheral Module Disable”). communications, to continue without interruption while • If the WDT or FSCM is enabled, the LPRC also the CPU idles, waiting for something to invoke an remains active. interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the The device wakes from Idle mode on any of these ROI bit (CLKDIV<15>). By default, interrupt events events: have no effect on Doze mode operation. • Any interrupt that is individually enabled For example, suppose the device is operating at • Any device Reset 20MIPS and the ECAN module has been configured • A WDT time-out for 500 kbps based on this device operating speed. If On wake-up from Idle mode, the clock is reapplied to the device is placed in Doze mode with a clock the CPU and instruction execution will begin (2-4 clock frequency ratio of 1:4, the ECAN module continues to cycles later), starting with the instruction following the communicate at the required bit rate of 500 kbps, but PWRSAV instruction, or the first instruction in the ISR. the CPU now starts executing instructions at a frequency of 5 MIPS. 10.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS 10.4 Peripheral Module Disable Any interrupt that coincides with the execution of a The Peripheral Module Disable (PMD) registers PWRSAV instruction is held off until entry into Sleep or provide a method to disable a peripheral module by Idle mode has completed. The device then wakes up stopping all clock sources supplied to that module. from Sleep or Idle mode. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power 10.3 Doze Mode consumption state. The control and status registers associated with the peripheral are also disabled, so The preferred strategies for reducing power writes to those registers do not have effect and read consumption are changing clock speed and invoking values are invalid. one of the power-saving modes. In some circumstances, this cannot be practical. For example, it A peripheral module is enabled only if both the may be necessary for an application to maintain associated bit in the PMD register is cleared and the uninterrupted synchronous communication, even while peripheral is supported by the specific dsPIC® DSC it is doing nothing else. Reducing system clock speed variant. If the peripheral is present in the device, it is can introduce communication errors, while using a enabled in the PMD register by default. power-saving mode can stop communications Note: If a PMD bit is set, the corresponding completely. module is disabled after a delay of one Doze mode is a simple and effective alternative method instruction cycle. Similarly, if a PMD bit is to reduce power consumption while the device is still cleared, the corresponding module is executing code. In this mode, the system clock enabled after a delay of one instruction continues to operate from the same source and at the cycle (assuming the module control regis- same speed. Peripheral modules continue to be ters are already configured to enable clocked at the same speed, while the CPU clock speed module operation). is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS70616G-page 192  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 10.5 Power-Saving Resources 10.5.1 KEY RESOURCES Many useful resources related to Power-Saving • Section 9. “Watchdog Timer and features are provided on the main product page of the Power-Saving Modes” (DS70615) in the Microchip web site for the devices listed in this data “dsPIC33E/PIC24E Family Reference Manual” sheet. This product page, which can be accessed using • Code Samples this link, contains the latest updates and additional • Application Notes information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All related “dsPIC33E/PIC24E Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en554310 10.6 Special Function Registers Seven registers, PMD1: Peripheral Module Disable Control Register 1 through PMD7: Peripheral Module Disable Control Register 7, are provided for peripheral module control.  2009-2012 Microchip Technology Inc. DS70616G-page 193

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T5MD T4MD T3MD T2MD T1MD QEI1MD(1) PWMMD(1) DCIMD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T5MD: Timer5 Module Disable bit 1 = Timer5 module is disabled 0 = Timer5 module is enabled bit 14 T4MD: Timer4 Module Disable bit 1 = Timer4 module is disabled 0 = Timer4 module is enabled bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10 QEI1MD: QEI1 Module Disable bit(1) 1 = QEI1 module is disabled 0 = QEI1 module is enabled bit 9 PWMMD: PWM Module Disable bit(1) 1 = PWM module is disabled 0 = PWM module is enabled bit 8 DCIMD: DCI Module Disable bit 1 = DCI module is disabled 0 = DCI module is enabled bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 U2MD: UART2 Module Disable bit 1 = UART2 module is disabled 0 = UART2 module is enabled bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled Note 1: This bit is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. DS70616G-page 194  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 C2MD: ECAN2 Module Disable bit 1 = ECAN2 module is disabled 0 = ECAN2 module is enabled bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: This bit is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 195

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IC8MD: Input Capture 8 Module Disable bit 1 = Input Capture 8 module is disabled 0 = Input Capture 8 module is enabled bit 14 IC7MD: Input Capture 2 Module Disable bit 1 = Input Capture 7 module is disabled 0 = Input Capture 7 module is enabled bit 13 IC6MD: Input Capture 6 Module Disable bit 1 = Input Capture 6 module is disabled 0 = Input Capture 6 module is enabled bit 12 IC5MD: Input Capture 5 Module Disable bit 1 = Input Capture 5 module is disabled 0 = Input Capture 5 module is enabled bit 11 IC4MD: Input Capture 4 Module Disable bit 1 = Input Capture 4 module is disabled 0 = Input Capture 4 module is enabled bit 10 IC3MD: Input Capture 3 Module Disable bit 1 = Input Capture 3 module is disabled 0 = Input Capture 3 module is enabled bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7 OC8MD: Output Compare 8 Module Disable bit 1 = Output Compare 8 module is disabled 0 = Output Compare 8 module is enabled bit 6 OC7MD: Output Compare 7 Module Disable bit 1 = Output Compare 7 module is disabled 0 = Output Compare 7 module is enabled bit 5 OC6MD: Output Compare 6 Module Disable bit 1 = Output Compare 6 module is disabled 0 = Output Compare 6 module is enabled bit 4 OC5MD: Output Compare 5 Module Disable bit 1 = Output Compare 5 module is disabled 0 = Output Compare 5 module is enabled DS70616G-page 196  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 (CONTINUED) bit 3 OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled  2009-2012 Microchip Technology Inc. DS70616G-page 197

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 T9MD T8MD T7MD T6MD — CMPMD RTCCMD PMPMD bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 CRCMD — QEI2MD(1) — U3MD — I2C2MD AD2MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T9MD: Timer9 Module Disable bit 1 = Timer9 module is disabled 0 = Timer9 module is enabled bit 14 T8MD: Timer8 Module Disable bit 1 = Timer8 module is disabled 0 = Timer8 module is enabled bit 13 T7MD: Timer7 Module Disable bit 1 = Timer7 module is disabled 0 = Timer7 module is enabled bit 12 T6MD: Timer6 Module Disable bit 1 = Timer6 module is disabled 0 = Timer6 module is enabled bit 11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Comparator Module Disable bit 1 = Comparator module is disabled 0 = Comparator module is enabled bit 9 RTCCMD: RTCC Module Disable bit 1 = RTCC module is disabled 0 = RTCC module is enabled bit 8 PMPMD: PMP Module Disable bit 1 = PMP module is disabled 0 = PMP module is enabled bit 7 CRCMD: CRC Module Disable bit 1 = CRC module is disabled 0 = CRC module is enabled bit 6 Unimplemented: Read as ‘0’ bit 5 QEI2MD: QEI2 Module Disable bit(1) 1 = QEI2 module is disabled 0 = QEI2 module is enabled bit 4 Unimplemented: Read as ‘0’ bit 3 U3MD: UART3 Module Disable bit 1 = UART3 module is disabled 0 = UART3 module is enabled bit 2 Unimplemented: Read as ‘0’ Note 1: This bit is available in dsPIC33EPXXX(MC/MU)806/810/814 devices only. DS70616G-page 198  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 bit 1 I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled bit 0 AD2MD: ADC2 Module Disable bit 1 = ADC2 module is disabled 0 = ADC2 module is enabled Note 1: This bit is available in dsPIC33EPXXX(MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 199

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 — — U4MD — REFOMD — — USB1MD(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 U4MD: UART4 Module Disable bit 1 = UART4 module is disabled 0 = UART4 module is enabled bit 4 Unimplemented: Read as ‘0’ bit 3 REFOMD: Reference Clock Module Disable bit 1 = Reference clock module is disabled 0 = Reference clock module is enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 USB1MD: USB Module Disable bit(1) 1 = USB module is disabled 0 = USB module is enabled Note 1: This bit is only available on dsPIC33EPXXXMU8XXX and PIC24EPXXXGU8XX devices. DS70616G-page 200  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-5: PMD5: PERIPHERAL MODULE DISABLE CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC16MD IC15MD IC14MD IC13MD IC12MD IC11MD IC10MD IC9MD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OC16MD OC15MD OC14MD OC13MD OC12MD OC11MD OC10MD OC9MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IC16MD: IC16 Module Disable bit 1 = IC16 module is disabled 0 = IC16 module is enabled bit 14 IC15MD: IC15 Module Disable bit 1 = IC15 module is disabled 0 = IC15 module is enabled bit 13 IC14MD: IC14 Module Disable bit 1 = IC14 module is disabled 0 = IC14 module is enabled bit 12 IC13MD: IC13 Module Disable bit 1 = IC13 module is disabled 0 = IC13 module is enabled bit 11 IC12MD: IC12 Module Disable bit 1 = IC12 module is disabled 0 = IC12 module is enabled bit 10 IC11MD: IC11 Module Disable bit 1 = IC11 module is disabled 0 = IC11 module is enabled bit 9 IC10MD: IC10 Module Disable bit 1 = IC10 module is disabled 0 = IC10 module is enabled bit 8 IC9MD: IC9 Module Disable bit 1 = IC9 module is disabled 0 = IC9 module is enabled bit 7 OC16MD: OC16 Module Disable bit 1 = OC16 module is disabled 0 = OC16 module is enabled bit 6 OC15MD: OC15 Module Disable bit 1 = OC15 module is disabled 0 = OC15 module is enabled bit 5 OC14MD: OC14 Module Disable bit 1 = OC14 module is disabled 0 = OC14 module is enabled bit 4 OC13MD: OC13 Module Disable bit 1 = OC13 module is disabled 0 = OC13 module is enabled  2009-2012 Microchip Technology Inc. DS70616G-page 201

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-5: PMD5: PERIPHERAL MODULE DISABLE CONTROL REGISTER 5 (CONTINUED) bit 3 OC12MD: OC12 Module Disable bit 1 = OC12 module is disabled 0 = OC12 module is enabled bit 2 OC11MD: OC11 Module Disable bit 1 = OC11 module is disabled 0 = OC11 module is enabled bit 1 OC10MD: OC10 Module Disable bit 1 = OC10 module is disabled 0 = OC10 module is enabled bit 0 OC9MD: OC9 Module Disable bit 1 = OC9 module is disabled 0 = OC9 module is enabled DS70616G-page 202  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-6: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PWM7MD(1) PWM6MD(1) PWM5MD(1) PWM4MD(1) PWM3MD(1) PWM2MD(1) PWM1MD(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPI4MD SPI3MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 PWM7MD: PWM7 Module Disable bit(1) 1 = PWM7 module is disabled 0 = PWM7 module is enabled bit 13 PWM6MD: PWM6 Module Disable bit(1) 1 = PWM6 module is disabled 0 = PWM6 module is enabled bit 12 PWM5MD: PWM5 Module Disable bit(1) 1 = PWM5 module is disabled 0 = PWM5 module is enabled bit 11 PWM4MD: PWM4 Module Disable bit(1) 1 = PWM4 module is disabled 0 = PWM4 module is enabled bit 10 PWM3MD: PWM3 Module Disable bit(1) 1 = PWM3 module is disabled 0 = PWM3 module is enabled bit 9 PWM2MD: PWM2 Module Disable bit(1) 1 = PWM2 module is disabled 0 = PWM2 module is enabled bit 8 PWM1MD: PWM1 Module Disable bit(1) 1 = PWM1 module is disabled 0 = PWM1 module is enabled bit 7-2 Unimplemented: Read as ‘0’ bit 1 SPI4MD: SPI4 Module Disable bit 1 = SPI4 module is disabled 0 = SPI4 module is enabled bit 0 SPI3MD: SPI3 Module Disable bit 1 = SPI3 module is disabled 0 = SPI3 module is enabled Note 1: This bit is available in dsPIC33EPXXX(MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 203

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-7: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 DMA12MD DMA8MD DMA4MD DMA0MD DMA13MD DMA9MD DMA5MD DMA1MD — — — — DMA14MD DMA10MD DMA6MD DMA2MD — DMA11MD DMA7MD DMA3MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 DMA12MD: DMA12 Module Disable bit 1 = DMA12 module is disabled 0 = DMA12 module is enabled DMA13MD: DMA13 Module Disable bit 1 = DMA13 module is disabled 0 = DMA13 module is enabled DMA14MD: DMA14 Module Disable bit 1 = DMA14 module is disabled 0 = DMA14 module is enabled bit 6 DMA8MD: DMA3 Module Disable bit 1 = DMA8 module is disabled 0 = DMA8 module is enabled DMA9MD: DMA2 Module Disable bit 1 = DMA9 module is disabled 0 = DMA9 module is enabled DMA10MD: DMA10 Module Disable bit 1 = DMA10 module is disabled 0 = DMA10 module is enabled DMA11MD: DMA11 Module Disable bit 1 = DMA11 module is disabled 0 = DMA11 module is enabled bit 5 DMA4MD: DMA4 Module Disable bit 1 = DMA4 module is disabled 0 = DMA4 module is enabled DMA5MD: DMA5 Module Disable bit 1 = DMA5 module is disabled 0 = DMA5 module is enabled DMA6MD: DMA6 Module Disable bit 1 = DMA6 module is disabled 0 = DMA6 module is enabled DMA7MD: DMA7 Module Disable bit 1 = DMA7 module is disabled 0 = DMA7 module is enabled DS70616G-page 204  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 10-7: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 (CONTINUED) bit 4 DMA0MD: DMA0 Module Disable bit 1 = DMA0 module is disabled 0 = DMA0 module is enabled DMA1MD: DMA1 Module Disable bit 1 = DMA1 module is disabled 0 = DMA1 module is enabled DMA2MD: DMA2 Module Disable bit 1 = DMA2 module is disabled 0 = DMA2 module is enabled DMA3MD: DMA3 Module Disable bit 1 = DMA3 module is disabled 0 = DMA3 module is enabled bit 3-0 Unimplemented: Read as ‘0’  2009-2012 Microchip Technology Inc. DS70616G-page 205

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 206  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 11.0 I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as Note1: This data sheet summarizes the features a general purpose output pin is disabled. The I/O pin of the dsPIC33EPXXX(GP/MC/MU)806/ can be read, but the output driver for the parallel port bit 810/814 and PIC24EPXXX(GP/GU)810/ is disabled. If a peripheral is enabled, but the peripheral 814 families of devices. It is not intended is not actively driving a pin, that pin can be driven by a to be a comprehensive reference source. port. To complement the information in this All port pins have eight registers directly associated data sheet, refer to Section 10. “I/O with their operation as digital I/O. The Data Direction Ports” (DS70598) of the “dsPIC33E/ register (TRISx) determines whether the pin is an input PIC24E Family Reference Manual”, or an output. If the data direction bit is a ‘1’, then the pin which is available from the Microchip web is an input. All port pins are defined as inputs after a site (www.microchip.com). Reset. Reads from the latch (LATx) read the latch. 2: Some registers and associated bits Writes to the latch write the latch. Reads from the port described in this section may not be (PORTx) read the port pins, while writes to the port pins available on all devices. Refer to write the latch. Section4.0 “Memory Organization” in Any bit and its associated data and control registers this data sheet for device-specific register that are not valid for a particular device is disabled. This and bit information. means the corresponding LATx and TRISx registers and the port pin are read as zeros. All of the device pins (except VDD, VSS, MCLR and OSC1/CLKI) are shared among the peripherals and the When a pin is shared with another peripheral or parallel I/O ports. All I/O input ports feature Schmitt function that is defined as an input only, it is Trigger inputs for improved noise immunity. nevertheless regarded as a dedicated port because there is no other competing source of outputs. 11.1 Parallel I/O (PIO) Ports Generally, a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure11-1 illus- trates how ports are shared with other peripherals and the associated I/O pin to which they are connected.  2009-2012 Microchip Technology Inc. DS70616G-page 207

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + WR Port CK Data Latch Read LAT Input Data Read Port DS70616G-page 208  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 11.1.1 OPEN-DRAIN CONFIGURATION 11.3 Input Change Notification In addition to the PORT, LAT and TRIS registers for The input change notification function of the I/O ports data control, some port pins can also be individually allows the dsPIC33EPXXX(GP/MC/MU)806/810/814 configured for either digital or open-drain output. This and PIC24EPXXX(GP/GU)810/814 devices to is controlled by the Open-Drain Control register, generate interrupt requests to the processor in ODCx, associated with each port. Setting any of the response to a Change-of-State (COS) on selected input bits configures the corresponding pin to act as an pins. This feature can detect input Change-of-States open-drain output. even in Sleep mode, when the clocks are disabled. The open-drain feature allows the generation of Every I/O port pin can be selected (enabled) for outputs higher than VDD (e.g., 5V on a 5V tolerant pin) generating an interrupt request on a Change-of-State. by using external pull-up resistors. The maximum Three control registers are associated with the CN open-drain voltage allowed is the same as the functionality of each I/O port. The CNENx registers maximum VIH specification for that pin. contain the CN interrupt enable control bits for each of See the “Pin Diagrams” section for the available pins the input pins. Setting any of these bits enables a CN and their functionality. interrupt for the corresponding pins. Each I/O pin also has a weak pull-up and a weak 11.2 Configuring Analog and Digital pull-down connected to it. The pull-ups act as a Port Pins current source or sink source connected to the pin, and eliminate the need for external resistors when The ANSELx register controls the operation of the push-button or keypad devices are connected. The analog port pins. The port pins that are to function as pull-ups and pull-downs are enabled separately using analog inputs or outputs must have their corresponding the CNPUx and the CNPDx registers, which contain ANSELx and TRISx bits set. In order to use port pins for the control bits for each of the pins. Setting any of I/O functionality with digital modules, such as Timers, the control bits enables the weak pull-ups and/or UARTs, etc., the corresponding ANSELx bit must be pull-downs for the corresponding pins. cleared. Note: Pull-ups and pull-downs on change notifi- The ANSELx register has a default value of 0xFFFF; cation pins should always be disabled therefore, all pins that share analog functions are when the port pin is configured as a digital analog (not digital) by default. Refer to the Pinout I/O output. Descriptions (Table1-1 in Section1.0 “Device Overview”) for the complete list of analog pins. EXAMPLE 11-1: PORT WRITE/READ If the TRISx bit is cleared (output) while the ANSELx bit EXAMPLE is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or MOV 0xFF00, W0 ; Configure PORTB<15:8> Comparator module. ; as inputs MOV W0, TRISB ; and PORTB<7:0> When the PORT register is read, all pins configured as ; as outputs analog input channels are read as cleared (a low level). NOP ; Delay 1 cycle Pins configured as digital inputs do not convert an BTSS PORTB, #13 ; Next Instruction analog input. Analog levels on any pin defined as a digital input (including the pins defined as Analog in Table1-1 in Section1.0 “Device Overview”) can cause the input buffer to consume current that exceeds the device specifications. 11.2.1 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be an NOP, as shown in Example11-1.  2009-2012 Microchip Technology Inc. DS70616G-page 209

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 11.4 Peripheral Pin Select When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital A major challenge in general purpose devices is provid- communication peripherals associated with the pin. ing the largest possible set of peripheral features while Priority is given regardless of the type of peripheral that minimizing the conflict of features on I/O pins. The chal- is mapped. Remappable peripherals never take priority lenge is even greater on low pin-count devices. In an over any analog functions associated with the pin. application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds 11.4.3 CONTROLLING PERIPHERAL PIN in application code or a complete redesign may be the SELECT only option. Peripheral Pin Select features are controlled through Peripheral Pin Select configuration provides an two sets of SFRs: one to map peripheral inputs and one alternative to these choices by enabling peripheral set to map outputs. Because they are separately con- selection and their placement on a wide range of I/O trolled, a particular peripheral’s input and output (if the pins. By increasing the pinout options available on a peripheral has both) can be placed on any selectable particular device, users can better tailor the device to function pin without constraint. their entire application, rather than trimming the The association of a peripheral to a peripheral-selectable application to fit the device. pin is handled in two different ways, depending on The Peripheral Pin Select configuration feature oper- whether an input or output is being mapped. ates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most dig- 11.4.4 INPUT MAPPING ital peripherals to any one of these I/O pins. Peripheral The inputs of the Peripheral Pin Select options are Pin Select is performed in software and generally does mapped on the basis of the peripheral. That is, a control not require the device to be reprogrammed. Hardware register associated with a peripheral dictates the pin it safeguards are included that prevent accidental or will be mapped to. The RPINRx registers are used to spurious changes to the peripheral mapping once it has configure peripheral input mapping (see Register11-1 been established. through Register11-22). Each register contains sets of 11.4.1 AVAILABLE PINS 7-bit fields, with each set associated with one of the remappable peripherals (see Table11-1). Programming The number of available pins is dependent on the a given peripheral’s bit field with an appropriate 7-bit particular device and its pin count. Pins that support the value maps the RPn/RPIn pin with the corresponding Peripheral Pin Select feature include the designation value to that peripheral (see Table11-2). For any given “RPn” or “RPIn” in their full pin designation, where “RP” device, the valid range of values for any bit field corre- designates a remappable function for input or output sponds to the maximum number of Peripheral Pin and “RPI” designates a remappable functions for input Selections supported by the device. only, and “n” is the remappable pin number. For example, Figure11-2 illustrates remappable pin 11.4.2 AVAILABLE PERIPHERALS selection for the U1RX input. The peripherals managed by the Peripheral Pin Select FIGURE 11-2: U1RX REMAPPABLE INPUT are all digital only peripherals. These include general serial communications (UART and SPI), general pur- U1RXR<6:0> pose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change 0 inputs. RP0 In comparison, some digital-only peripheral modules are 1 never included in the Peripheral Pin Select feature. This RP1 is because the peripheral’s function requires special I/O 2 U1RX Input circuitry on a specific port and cannot be easily con- to Peripheral nected to multiple pins. These modules include I2C and RP3 the PWM. A similar requirement excludes all modules with analog inputs, such as the ADC Converter. A key difference between remappable and non- n remappable peripherals is that remappable peripherals RPn/RPIn are not associated with a default I/O pin. The peripheral Note: For input only, Peripheral Pin Select functionality must always be assigned to a specific I/O pin before it does not have priority over TRISx settings. can be used. In contrast, non-remappable peripherals Therefore, when configuring RPn/RPIn pin for are always available on a default pin, assuming that the input, the corresponding bit in the TRISx register peripheral is active and not conflicting with another must also be configured for input (set to ‘1’). peripheral. DS70616G-page 210  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name(1) Function Name Register Configuration Bits External Interrupt 1 INT1 RPINR0 INT1R<6:0> External Interrupt 2 INT2 RPINR1 INT2R<6:0> External Interrupt 3 INT3 RPINR1 INT3R<6:0> External Interrupt 4 INT4 RPINR2 INT4R<6:0> Timer2 External Clock T2CK RPINR3 T2CKR<6:0> Timer3 External Clock T3CK RPINR3 T3CKR<6:0> Timer4 External Clock T4CK RPINR4 T4CKR<6:0> Timer5 External Clock T5CK RPINR4 T5CKR<6:0> Timer6 External Clock T6CK RPINR5 T6CKR<6:0> Timer7 External Clock T7CK RPINR5 T7CKR<6:0> Timer8 External Clock T8CK RPINR6 T8CKR<6:0> Timer9 External Clock T9CK RPINR6 T9CKR<6:0> Input Capture 1 IC1 RPINR7 IC1R<6:0> Input Capture 2 IC2 RPINR7 IC2R<6:0> Input Capture 3 IC3 RPINR8 IC3R<6:0> Input Capture 4 IC4 RPINR8 IC4R<6:0> Input Capture 5 IC5 RPINR9 IC5R<6:0> Input Capture 6 IC6 RPINR9 IC6R<6:0> Input Capture 7 IC7 RPINR10 IC7R<6:0> Input Capture 8 IC8 RPINR10 IC8R<6:0> Output Compare Fault A OCFA RPINR11 OCFAR<6:0> Output Compare Fault B OCFB RPINR11 OCFBR<6:0> PMW Fault 1(2) FLT1 RPINR12 FLT1R<6:0> PMW Fault 2(2) FLT2 RPINR12 FLT2R<6:0> PMW Fault 3(2) FLT3 RPINR13 FLT3R<6:0> PMW Fault 4(2) FLT4 RPINR13 FLT4R<6:0> QEI1 Phase A(2) QEA1 RPINR14 QEA1R<6:0> QEI1 Phase A(2) QEB1 RPINR14 QEB1R<6:0> QEI1 Index(2) INDX1 RPINR15 INDX1R<6:0> QEI1 Home(2) HOME1 RPINR15 HOM1R<6:0> QEI2 Phase A(2) QEA2 RPINR16 QEA2R<6:0> QEI2 Phase A(2) QEB2 RPINR16 QEB2R<6:0> QEI2 Index(2) INDX2 RPINR17 INDX2R<6:0> QEI2 Home(2) HOME2 RPINR17 HOM2R<6:0> UART1 Receive U1RX RPINR18 U1RXR<6:0> UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<6:0> UART2 Receive U2RX RPINR19 U2RXR<6:0> UART2 Clear-to-Send U2CTS RPINR19 U2CTSR<6:0> SPI1 Data Input SDI1 RPINR20 SDI1R<6:0> SPI1 Clock Input SCK1 RPINR20 SCK1R<6:0> SPI1 Slave Select SS1 RPINR21 SS1R<6:0> SPI2 Slave Select SS2 RPINR23 SS2R<6:0> Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. 2: This input source is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 211

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) (CONTINUED) Input Name(1) Function Name Register Configuration Bits DCI Data Input CSDI RPINR24 CSDIR<6:0> DCI Clock Input CSCKIN RPINR24 CSCKR<6:0> DCI FSYNC Input COFSIN RPINR25 COFSR<6:0> CAN1 Receive C1RX RPINR26 C1RXR<6:0> CAN2 Receive C2RX RPINR26 C2RXR<6:0> UART3 Receive U3RX RPINR27 U3RXR<6:0> UART3 Clear-to-Send U3CTS RPINR27 U3CTSR<6:0> UART4 Receive U4RX RPINR28 U4RXR<6:0> UART4 Clear-to-Send U4CTS RPINR28 U4CTSR<6:0> SPI3 Data Input SDI3 RPINR29 SDI3R<6:0> SPI3 Clock Input SCK3 RPINR29 SCK3R<6:0> SPI3 Slave Select SS3 RPINR30 SS3R<6:0> SPI4 Data Input SDI4 RPINR31 SDI4R<6:0> SPI4 Clock Input SCK4 RPINR31 SCK4R<6:0> SPI4 Slave Select SS4 RPINR32 SS4R<6:0> Input Capture 9 IC9 RPINR33 IC9R<6:0> Input Capture 10 IC10 RPINR33 IC10R<6:0> Input Capture 11 IC11 RPINR34 IC11R<6:0> Input Capture 12 IC12 RPINR34 IC12R<6:0> Input Capture 13 IC13 RPINR35 IC13R<6:0> Input Capture 14 IC14 RPINR35 IC14R<6:0> Input Capture 15 IC15 RPINR36 IC15R<6:0> Input Capture 16 IC16 RPINR36 IC16R<6:0> Output Compare Fault C OCFC RPINR37 OCFCR<6:0> PWM Fault 5(2) FLT5 RPINR42 FLT5R<6:0> PWM Fault 6(2) FLT6 RPINR42 FLT6R<6:0> PWM Fault 7(2) FLT7 RPINR43 FLT7R<6:0> PWM Dead-Time DTCMP1 RPINR38 DTCMP1R<6:0> Compensation 1(2) PWM Dead-Time DTCMP2 RPINR39 DTCMP2R<6:0> Compensation 2(2) PWM Dead-Time DTCMP3 RPINR39 DTCMP3R<6:0> Compensation 3(2) PWM Dead-Time DTCMP4 RPINR40 DTCMP4R<6:0> Compensation 4(2) PWM Dead-Time DTCMP5 RPINR40 DTCMP5R<6:0> Compensation 5(2) PWM Dead-Time DTCMP6 RPINR41 DTCMP6R<6:0> Compensation 6(2) PWM Dead-Time DTCMP7 RPINR41 DTCMP7R<6:0> Compensation 7(2) PWM Synch Input 1(2) SYNCI1 RPINR37 SYNCI1R<6:0> PWM Synch Input 2(2) SYNCI2 RPINR38 SYNCI2R<6:0> Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. 2: This input source is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. DS70616G-page 212  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES Peripheral Pin Select Input/ Peripheral Pin Select Input/ Pin Assignment Pin Assignment Input Register Value Output Input Register Value Output 000 0000 I VSS 010 1101 I RPI45 000 0001 I C1OUT(1) 010 1110 I RPI46 000 0010 I C2OUT(1) 010 1111 I RPI47 000 0011 I C3OUT(1) 011 0000 — Reserved 000 0100 — Reserved 011 0001 I RPI49 000 0101 — Reserved 011 0010 I RPI50 000 0110 — Reserved 011 0011 I RPI51 000 0111 — Reserved 011 0100 I RPI52 000 1000 I FINDX1(1) 011 0101 — Reserved 000 1001 I FHOME1(1) 011 0110 — Reserved 000 1010 I FINDX2(1) 011 0111 — Reserved 000 1011 I FHOME2(1) 011 1000 — Reserved 000 1100 — Reserved 011 1001 — Reserved 000 1101 — Reserved 011 1010 — Reserved 000 1110 — Reserved 011 1011 — Reserved 000 1111 — Reserved 011 1100 I RPI60 001 0000 I RPI16 011 1101 I RPI61 001 0001 I RPI17 011 1110 I RPI62 001 0010 I RPI18 011 1111 — Reserved 001 0011 I RPI19 100 0000 I/O RP64 001 0100 I RPI20 100 0001 I/O RP65 001 0101 I RPI21 100 0010 I/O RP66 001 0110 I RPI22 100 0011 I/O RP67 001 0111 I RPI23 100 0100 I/O RP68 001 1000 — Reserved 100 0101 I/O RP69 001 1001 — Reserved 100 0110 I/O RP70 001 1010 — Reserved 100 0111 I/O RP71 001 1011 — Reserved 100 1000 I RPI72 001 1100 — Reserved 100 1001 I RPI73 001 1101 — Reserved 100 1010 I RPI74 001 1110 I RPI30 100 1011 I RPI75 001 1111 I RPI31 100 1100 I RPI76 010 0000 I RPI32 100 1101 I RPI77 010 0001 I RPI33 100 1110 I RPI78 010 0010 I RPI34 100 1111 I/O RP79 010 0011 I RPI35 101 0000 I/O RP80 010 0100 I RPI36 101 0001 I RPI81 010 0101 I RPI37 101 0010 I/O RP82 010 0110 I RPI38 101 0011 I RPI83 010 0111 I RPI39 101 0100 I/O RP84 010 1000 I RPI40 101 0101 I/O RP85 010 1001 I RPI41 101 0110 I RPI86 010 1010 I RPI42 101 0111 I/O RP87 Note 1: See Section11.4.4.2 “Virtual Connections” for more information on selecting this pin assignment.  2009-2012 Microchip Technology Inc. DS70616G-page 213

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES (CONTINUED) Peripheral Pin Select Input/ Peripheral Pin Select Input/ Pin Assignment Pin Assignment Input Register Value Output Input Register Value Output 010 1011 I RPI43 101 1000 I RPI88 010 1100 I RPI44 101 1001 I RPI89 101 1010 — Reserved 110 1101 I/O RP109 101 1011 — Reserved 110 1110 — Reserved 101 1100 — Reserved 110 1111 — Reserved 101 1101 — Reserved 111 0000 I/O RP112 101 1110 — Reserved 111 0001 I/O RP113 101 1111 — Reserved 111 0010 — Reserved 110 0000 I/O RP96 111 0011 — Reserved 110 0001 I/O RP97 111 0100 — Reserved 110 0010 I/O RP98 111 0101 — Reserved 110 0011 I/O RP99 111 0110 I/O RP118 110 0100 I/O RP100 111 0111 I RPI119 110 0101 I/O RP101 111 1000 I/O RP120 110 0110 I/O RP102 111 1001 I RPI121 110 0111 — Reserved 111 1010 — Reserved 110 1000 I/O RP104 111 1011 — Reserved 110 1001 — Reserved 111 1100 I RPI124 110 1010 — Reserved 111 1101 I/O RP125 110 1011 — Reserved 111 1110 I/O RP126 110 1100 I/O RP108 111 1111 I/O RP127 Note 1: See Section11.4.4.2 “Virtual Connections” for more information on selecting this pin assignment. DS70616G-page 214  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 11.4.4.1 Output Mapping FIGURE 11-3: MULTIPLEXING OF REMAPPABLE OUTPUT In contrast to inputs, the outputs of the Peripheral Pin FOR RPn Select options are mapped on the basis of the pin. In this case, a control register associated with a particular RPnR<5:0> pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Like the RPINRx registers, each register contains sets Default 0 of 6 bit fields, with each set associated with one RPn U1TX Output 1 pin (see Register11-44 through Register11-51). The U1RTS Output value of the bit field corresponds to one of the periph- 2 erals and that peripheral’s output is mapped to the pin RPn Output Data (see Table11-3 and Figure11-3). A null output is associated with the Output Register Reset value of ‘0’. This is done to ensure that remap- QEI2CCMP Output 48 pable outputs remain disconnected from all output pins by default. REFCLK Output 49 TABLE 11-3: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn) Function RPnR<5:0> Output Name DEFAULT PORT 000000 RPn tied to Default Pin U1TX 000001 RPn tied to UART1 Transmit U1RTS 000010 RPn tied to UART1 Ready-to-Send U2TX 000011 RPn tied to UART2 Transmit U2RTS 000100 RPn tied to UART2 Ready-to-Send SDO1 000101 RPn tied to SPI1 Data Output SCK1 000110 RPn tied to SPI1 Clock Output SS1 000111 RPn tied to SPI1 Slave Select SS2 001010 RPn tied to SPI2 Slave Select CSDO 001011 RPn tied to DCI Data Output CSCK 001100 RPn tied to DCI Clock Output COFS 001101 RPn tied to DCI FSYNC Output C1TX 001110 RPn tied to CAN1 Transmit C2TX 001111 RPn tied to CAN2 Transmit OC1 010000 RPn tied to Output Compare 1 Output OC2 010001 RPn tied to Output Compare 2 Output OC3 010010 RPn tied to Output Compare 3 Output OC4 010011 RPn tied to Output Compare 4 Output OC5 010100 RPn tied to Output Compare 5 Output OC6 010101 RPn tied to Output Compare 6 Output OC7 010110 RPn tied to Output Compare 7 Output OC8 010111 RPn tied to Output Compare 8 Output C1OUT 011000 RPn tied to Comparator Output 1 C2OUT 011001 RPn tied to Comparator Output 2 C3OUT 011010 RPn tied to Comparator Output 3 U3TX 011011 RPn tied to UART3 Transmit U3RTS 011100 RPn tied to UART3 Ready-to-Send Note 1: This function is available in dsPIC33EPXXX(MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 215

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 11-3: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn) (CONTINUED) Function RPnR<5:0> Output Name U4TX 011101 RPn tied to UART4 Transmit U4RTS 011110 RPn tied to UART4 Ready-to-Send SDO3 011111 RPn tied to SPI3 Data Output SCK3 100000 RPn tied to SPI3 Clock Output SS3 100001 RPn tied to SPI3 Slave Select SDO4 100010 RPn tied to SPI4 Data Output SCK4 100011 RPn tied to SPI4 Clock Output SS4 100100 RPn tied to SPI4 Slave Select OC9 100101 RPn tied to Output Compare 9 Output OC10 100110 RPn tied to Output Compare 10 Output OC11 100111 RPn tied to Output Compare 11 Output OC12 101000 RPn tied to Output Compare 12 Output OC13 101001 RPn tied to Output Compare 13 Output OC14 101010 RPn tied to Output Compare 14 Output OC15 101011 RPn tied to Output Compare 15 Output OC16 101100 RPn tied to Output Compare 16 Output SYNCO1(1) 101101 RPn tied to PWM Primary Time Base Sync Output SYNCO2(1) 101110 RPn tied to PWM Secondary Time Base Sync Output QEI1CCMP(1) 101111 RPn tied to QEI 1 Counter Comparator Output QEI2CCMP(1) 110000 RPn tied to QEI 2 Counter Comparator Output REFCLK 110001 RPn tied to Reference Clock Output Note 1: This function is available in dsPIC33EPXXX(MC/MU)806/810/814 devices only. DS70616G-page 216  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 11.4.4.2 Virtual Connections Virtual connection to the QEI module allows peripherals to be connected to the QEI digital filter The dsPIC33EPXXX(GP/MC/MU)806/810/814 and input. To utilize this filter, the QEI module must be PIC24EPXXX(GP/GU)810/814 devices support virtual enabled, and its inputs must be connected to a physical (internal) connections to the output of the comparator RPn/RPIn pin. Example11-2 illustrates how the input modules, CMP1OUT, CMP2OUT and CMP3OUT (see capture module can be connected to the QEI digital Figure25-1 in Section25.0 “Comparator Module”). filter. In addition, dsPIC33EPXXXMU806/810/814 devices support virtual connections to the filtered QEI module 11.4.4.3 Mapping Limitations inputs, FINDX1, FHOME1, FINDX2 and FHOME2 (see Figure17-1 in Section17.0 “Quadrature Encoder The control schema of the peripheral select pins is not Interface (QEI) Module (dsPIC33EPXXX(MC/ limited to a small range of fixed peripheral MU)8XX Devices Only)”. configurations. There are no mutual or hardware enforced lockouts between any of the peripheral Virtual connections provide a simple way of inter- mapping SFRs. Literally any combination of peripheral peripheral connection without utilizing a physical pin. mappings across any or all of the RPn/RPIn pins is For example, by setting the FLT1R<6:0> bits of the possible. This includes both many-to-one and one-to- RPINR12 register to the value of ‘b0000001, the many mappings of peripheral inputs and outputs to output of the analog comparator, CMP1OUT, will be pins. While such mappings may be technically possible connected to the PWM Fault 1 input, which allows the from a configuration point of view, they may not be analog comparator to trigger PWM Faults without the supportable from an electrical point of view. use of an actual physical pin on the device. EXAMPLE 11-2: CONNECTING IC1 TO HOME1 DIGITAL FILTER INPUT ON PIN 3 OF THE dsPIC33EP512MU810 DEVICE RPINR15 = 0x5600; /* Connect the QEI1 HOME1 input to RP86 (pin 3) */ RPINR7 = 0x009; /* Connect the IC1 input to the digital filter on the FHOME1 input */ QEI1IOC = 0x4000; /* Enable the QEI digital filter */ QEI1CON = 0x8000; /* Enable the QEI module */  2009-2012 Microchip Technology Inc. DS70616G-page 217

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 11.5 I/O Helpful Tips 4. Each pin has an internal weak pull-up resistor and pull-down resistor that can be configured using the 1. In some cases, certain pins, as defined in CNPUx and CNPDx registers, respectively. These Table32-9 in Section32.0 “Electrical Charac- resistors eliminate the need for external resistors teristics” under “Injection Current”, have internal in certain applications. The internal pull-up is up to protection diodes to VDD and VSS; the term “Injection Current” is also referred to as “Clamp ~(VDD-0.8), not VDD. This value is still above the Current”. On designated pins, with sufficient exter- minimum VIH of CMOS and TTL devices. nal current-limiting precautions by the user, I/O pin 5. When driving LEDs directly, the I/O pin can source input voltages are allowed to be greater or less or sink more current than what is specified in the than the data sheet absolute maximum ratings VOH/IOH and VOL/IOL DC characteristic specifica- with respect to the VSS and VDD supplies. Note tion. The respective IOH and IOL current rating only that when the user application forward biases applies to maintaining the corresponding output at either of the high or low side internal input clamp or above the VOH and at or below the VOL levels. diodes, that the resulting current being injected However, for LEDs, unlike digital inputs of an into the device that is clamped internally by the externally connected device, they are not gov- VDD and VSS power rails, may affect the ADC erned by the same minimum VIH/VIL levels. An I/O accuracy by four to six counts. pin output can safely sink or source any current less than that listed in the absolute maximum 2. I/O pins that are shared with any analog input pin, rating section of the data sheet. For example: (i.e., ANx, see Table1-1 in Section1.0 “Device Overview”), are always analog pins by default VOH = 2.4v @ IOH = -8 mA and VDD = 3.3V after any Reset. Consequently, configuring a pin The maximum output current sourced by any 8mA as an analog input pin, automatically disables the I/O pin = 12 mA. digital input pin buffer and any attempt to read the LED source current < 12 mA is technically digital input level by reading PORTx or LATx will permitted. Refer to the VOH/IOH graphs in always return a ‘0’, regardless of the digital logic Section32.0 “Electrical Characteristics” for level on the pin. To use a pin as a digital I/O pin on additional information. a shared analog pin (see Table1-1 in Section1.0 “Device Overview”), the user application needs 6. The Peripheral Pin Select (PPS) pin mapping rules to configure the Analog Pin Configuration registers are as follows: in the I/O ports module (i.e., ANSELx) by setting a) Only one “output” function can be active on a the appropriate bit that corresponds to that I/O port given pin at any time regardless if it is a dedi- pin to a ‘0’. cated or remappable function (one pin, one output). Note: Although it is not possible to use a digital b) It is possible to assign a “remappable output” input pin when its analog function is function to multiple pins and externally short or enabled, it is possible to use the digital I/O tie them together for increased current drive. output function, TRISx = 0x0, while the c) If any “dedicated output” function is enabled analog function is also enabled. However, on a pin, it will take precedence over any this is not recommended, particularly if the remappable “output” function. analog input is connected to an external analog voltage source, which would d) If any “dedicated digital” (input or output) create signal contention between the function is enabled on a pin, any number of analog signal and the output pin driver. “input” remappable functions can be mapped to the same pin. 3. Most I/O pins have multiple functions. Referring to e) If any “dedicated analog” function(s) are the device pin diagrams in the data sheet, the enabled on a given pin, “digital input(s)” of any priorities of the functions allocated to any pins are kind will all be disabled, although a single “dig- indicated by reading the pin name from left to right. ital output”, at the user’s cautionary discretion, The left most function name takes precedence can be enabled and active as long as there is over any function to its right in the naming conven- no signal contention with an external analog tion. For example: AN16/T2CK/T7CK/RC1; this input signal. For example, it is possible for the indicates that AN16 is the highest priority in this ADC to convert the digital output logic level, or example and will supersede all other functions to to toggle a digital output on a comparator or its right in the list. Those other functions to its right, ADC input, provided there is no external analog input, such as for a built-in self test. even if enabled, would not work as long as any other function to its left was enabled. This rule f) Any number of “input” remappable functions applies to all of the functions listed for a given pin. can be mapped to the same pin(s) at the Dedicated peripheral functions are always higher same time, including any pin with a single out- put from either a dedicated or remappable priority than remappable functions. I/O pins are “output”. always the lowest priority. DS70616G-page 218  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 g) The TRIS registers control only the digital I/O 11.6 I/O Resources output buffer. Any other dedicated or remap- pable active “output” will automatically over- Many useful resources related to I/O are provided on ride the TRIS setting. The TRIS register does the main product page of the Microchip web site for the not control the digital logic “input” buffer. devices listed in this data sheet. This product page, Remappable digital “inputs” do not automati- which can be accessed using this link, contains the cally override TRIS settings, which means latest updates and additional information. that the TRIS bit must be set to input for pins Note: In the event you are not able to access the with only remappable input function(s) product page using the link above, enter assigned. this URL in your browser: h) All analog pins are enabled by default after http://www.microchip.com/wwwproducts/ any Reset and the corresponding digital input Devices.aspx?dDocName=en554301 buffer on the pin is disabled. Only the Analog Pin Select registers control the digital input 11.6.1 KEY RESOURCES buffer, not the TRIS register. The user must disable the analog function on a pin using the • Section 10. “I/O Ports” (DS70598) in the Analog Pin Select registers in order to use any “dsPIC33E/PIC24E Family Reference Manual” “digital input(s)” on a corresponding pin, no • Code Samples exceptions. • Application Notes • Software Libraries • Webinars • All related “dsPIC33E/PIC24E Family Reference Manual” Sections • Development Tools  2009-2012 Microchip Technology Inc. DS70616G-page 219

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 11.7 Peripheral Pin Select Control Registers REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INT1R<6:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 INT1R<6:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7-0 Unimplemented: Read as ‘0’ DS70616G-page 220  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INT3R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INT2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 INT3R<6:0>: Assign External Interrupt 3 (INT3) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 INT2R<6:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 221

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INT4R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 INT4R<6:0>: Assign External Interrupt 4 (INT4) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 222  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-4: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T3CKR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2CKR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 T3CKR<6:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 T2CKR<6:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 223

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-5: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T5CKR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4CKR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 T5CKR<6:0>: Assign Timer5 External Clock (T5CK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 T4CKR<6:0>: Assign Timer4 External Clock (T4CK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 224  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-6: RPINR5: PERIPHERAL PIN SELECT INPUT REGISTER 5 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T7CKR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T6CKR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 T7CKR<6:0>: Assign Timer7 External Clock (T7CK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 T6CKR<6:0>: Assign Timer6 External Clock (T6CK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 225

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-7: RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T9CKR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T8CKR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 T9CKR<6:0>: Assign Timer9 External Clock (T9CK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 T8CKR<6:0>: Assign Timer8 External Clock (T8CK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 226  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-8: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC2R<6:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC1R<6:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 227

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-9: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC4R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC3R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC4R<6:0>: Assign Input Capture 4 (IC4) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC3R<6:0>: Assign Input Capture 3 (IC3) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 228  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-10: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC6R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC5R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC6R<6:0>: Assign Input Capture 6 (IC6) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC5R<6:0>: Assign Input Capture 5 (IC5) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 229

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-11: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC8R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC7R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC8R<6:0>: Assign Input Capture 8 (IC8) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC7R<6:0>: Assign Input Capture 7 (IC7) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 230  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-12: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — OCFBR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — OCFAR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 OCFBR<6:0>: Assign Output Compare Fault B (OCFB) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 OCFAR<6:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 231

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-13: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (dsPIC33EPXXXMU806/810/814 DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT2R<6:0>(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT1R<6:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 FLT2R<6:0>: Assign PWM Fault 2 (FLT2) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 FLT1R<6:0>: Assign PWM Fault 1 (FLT1) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS Note 1: These pins are available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. DS70616G-page 232  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-14: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 (dsPIC33EPXXXMU806/810/814 DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT4R<6:0>(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT3R<6:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 FLT4R<6:0>: Assign PWM Fault 4 (FLT4) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 FLT3R<4:0>: Assign PWM Fault 3 (FLT3) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS Note 1: These pins are available on dsPIC33EPXXX(MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 233

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-15: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14 (dsPIC33EPXXXMU806/810/814 DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — QEB1R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — QEA1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 QEB1R<6:0>: Assign B (QEB) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 QEA1R<6:0>: Assign A (QEA) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 234  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-16: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 (dsPIC33EPXXXMU806/810/814 DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — HOME1R<6:0>(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INDX1R<6:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 HOME1R<6:0>: Assign QEI1 HOME1 (HOME1) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IND1XR<6:0>: Assign QEI1 INDEX1 (INDX1) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS Note 1: These bits are available on dsPIC33EPXXX(MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 235

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-17: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 (dsPIC33EPXXXMU806/810/814 DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — QEB2R<6:0>(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — QEA2R<6:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 QEB2R<6:0>: Assign B (QEI2) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 QEA2R<6:0>: Assign A (QEI2) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS Note 1: These bits are available on dsPIC33EPXXX(MC/MU)806/810/814 devices only. DS70616G-page 236  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-18: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 (dsPIC33EPXXXMU806/810/814 DEVICES ONLY) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — HOME2R<6:0>(1) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INDX2R<6:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 HOME2R<6:0>: Assign QEI2 HOME2 (HOME2) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 INDX2R<6:0>: Assign QEI2 INDEX2 (INDX2) to the Corresponding RPn/RPIn Pin bits(1) (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS Note 1: These bits are available on dsPIC33EPXXX(MC/MU)806/810/814 devices only.  2009-2012 Microchip Technology Inc. DS70616G-page 237

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-19: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U1CTSR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U1RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 U1CTSR<6:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 U1RXR<6:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 238  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-20: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U2CTSR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U2RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 U2CTSR<6:0>: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 U2RXR<6:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 239

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-21: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SCK1R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SDI1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SCK1R<6:0>: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 SDI1R<6:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 240  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-22: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SS1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 SS1R<6:0>: Assign SPI1 Slave Select Input (SS1) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS REGISTER 11-23: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SS2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 SS2R<6:0>: Assign SPI2 Slave Select Input (SS2) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 241

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-24: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CSCKR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CSDIR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 CSCKR<6:0>: Assign DCI Clock Input (CSCK) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 CSDIR<6:0>: Assign DCI Data Input (CSDI) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 242  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-25: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — COFSR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 COFSR<6:0>: Assign DCI FSYNC Input (COFS) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 243

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-26: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — C2RXR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — C1RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 C2RXR<6:0>: Assign CAN2 RX Input (CRX2) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 C1RXR<6:0>: Assign CAN1 RX Input (CRX1) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 244  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-27: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U3CTSR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U3RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 U3CTSR<6:0>: Assign UART3 Clear-to-Send (U3CTS) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 U3RXR<6:0>: Assign UART3 Receive (U3RX) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 245

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-28: RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U4CTSR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — U4RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 U4CTSR<6:0>: Assign UART4 Clear-to-Send (U4CTS) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 U4RXR<6:0>: Assign UART4 Receive (U4RX) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 246  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-29: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SCK3R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SDI3R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SCK3R<6:0>: Assign SPI3 Clock Input (SCK3) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 SDI3R<6:0>: Assign SPI3 Data Input (SDI3) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 247

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-30: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SS3R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 SS3R<6:0>: Assign SPI3 Slave Select Input (SS3) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 248  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-31: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SCK4R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SDI4R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SCK4R<6:0>: Assign SPI4 Clock Input (SCK4) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 SDI4R<6:0>: Assign SPI4 Data Input (SDI4) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 249

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-32: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SS4R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 SS4R<6:0>: Assign SPI4 Slave Select Input (SS4) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 250  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-33: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC10R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC9R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC10R<6:0>: Assign Input Capture 10 (IC10) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC9R<6:0>: Assign Input Capture 9 (IC9) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 251

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-34: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC12R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC11R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC12R<6:0>: Assign Input Capture 12 (IC12) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC11R<6:0>: Assign Input Capture 11 (IC11) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 252  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-35: RPINR35: PERIPHERAL PIN SELECT INPUT REGISTER 35 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC14R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC13R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC14R<6:0>: Assign Input Capture 14 (IC14) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC13R<6:0>: Assign Input Capture 13 (IC13) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 253

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-36: RPINR36: PERIPHERAL PIN SELECT INPUT REGISTER 36 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC16R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC15R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC16R<6:0>: Assign Input Capture 16 (IC16) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 IC15R<6:0>: Assign Input Capture 15 (IC15) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 254  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-37: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SYNCI1R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — OCFCR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SYNCI1R<6:0>: Assign PWM Synchronization Input 1 to the Corresponding RPn/RPIn Pin bits. (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 OCFCR<6:0>: Assign Output Fault C (OCFC) to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 255

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-38: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP1R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SYNCI2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP1R<6:0>: Assign PWM Dead-Time Compensation Input 1 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 SYNCI2R<6:0>: Assign PWM Synchronization Input 2 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 256  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-39: RPINR39: PERIPHERAL PIN SELECT INPUT REGISTER 39 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP3R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP3R<6:0>: Assign PWM Dead-Time Compensation Input 3 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 DTCMP2R<6:0>: Assign PWM Dead-Time Compensation Input 2 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 257

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-40: RPINR40: PERIPHERAL PIN SELECT INPUT REGISTER 40 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP5R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP4R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP5R<6:0>: Assign PWM Dead-Time Compensation Input 5 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 DTCMP4R<6:0>: Assign PWM Dead-Time Compensation Input 4 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 258  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-41: RPINR41: PERIPHERAL PIN SELECT INPUT REGISTER 41 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP7R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DTCMP6R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP7R<6:0>: Assign PWM Dead-Time Compensation Input 7 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 DTCMP6R<6:0>: Assign PWM Dead-Time Compensation Input 6 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS  2009-2012 Microchip Technology Inc. DS70616G-page 259

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-42: RPINR42: PERIPHERAL PIN SELECT INPUT REGISTER 42 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT6R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT5R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 FLT6R<6:0>: Assign PWM Fault 6 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS bit 7 Unimplemented: Read as ‘0’ bit 6-0 FLT5R<6:0>: Assign PWM Fault 5 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS DS70616G-page 260  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-43: RPINR43: PERIPHERAL PIN SELECT INPUT REGISTER 43 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FLT7R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 FLT7R<6:0>: Assign PWM Fault 7 to the Corresponding RPn/RPIn Pin bits (see Table11-2 for input pin selection numbers) 1111111 = Input tied to RP127 . . . 0000001 = Input tied to CMP1 0000000 = Input tied to VSS REGISTER 11-44: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP65R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP64R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP65R<5:0>: Peripheral Output Function is Assigned to RP65 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP64R<5:0>: Peripheral Output Function is Assigned to RP64 Output Pin bits (see Table11-3 for peripheral function numbers)  2009-2012 Microchip Technology Inc. DS70616G-page 261

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-45: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP67R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP66R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP67R<5:0>: Peripheral Output Function is Assigned to RP67 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP66R<5:0>: Peripheral Output Function is Assigned to RP66 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-46: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP69R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP68R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP69R<5:0>: Peripheral Output Function is Assigned to RP69 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP68R<5:0>: Peripheral Output Function is Assigned to RP68 Output Pin bits (see Table11-3 for peripheral function numbers) DS70616G-page 262  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-47: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP71R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP70R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP71R<5:0>: Peripheral Output Function is Assigned to RP71 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP70R<5:0>: Peripheral Output Function is Assigned to RP70 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-48: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP80R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP79R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP80R<5:0>: Peripheral Output Function is Assigned to RP80 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP79R<5:0>: Peripheral Output Function is Assigned to RP79 Output Pin bits (see Table11-3 for peripheral function numbers)  2009-2012 Microchip Technology Inc. DS70616G-page 263

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-49: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP84R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP82R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP84R<5:0>: Peripheral Output Function is Assigned to RP84 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP82R<5:0>: Peripheral Output Function is Assigned to RP82 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-50: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP87R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP85R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP87R<5:0>: Peripheral Output Function is Assigned to RP87 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP85R<5:0>: Peripheral Output Function is Assigned to RP85 Output Pin bits (see Table11-3 for peripheral function numbers) DS70616G-page 264  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-51: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP97R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP96R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP97R<5:0>: Peripheral Output Function is Assigned to RP97 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP96R<5:0>: Peripheral Output Function is Assigned to RP96 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-52: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP99R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP98R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP99R<5:0>: Peripheral Output Function is Assigned to RP99 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP98R<5:0>: Peripheral Output Function is Assigned to RP98 Output Pin bits (see Table11-3 for peripheral function numbers)  2009-2012 Microchip Technology Inc. DS70616G-page 265

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-53: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP101R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP100R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP101R<5:0>: Peripheral Output Function is Assigned to RP101Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP100R<5:0>: Peripheral Output Function is Assigned to RP100 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-54: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP102R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 RP102R<5:0>: Peripheral Output Function is Assigned to RP102 Output Pin bits (see Table11-3 for peripheral function numbers) DS70616G-page 266  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-55: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP108R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP104R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP108R<5:0>: Peripheral Output Function is Assigned to RP108 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP104R<5:0>: Peripheral Output Function is Assigned to RP104 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-56: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP112R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP109R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP112R<5:0>: Peripheral Output Function is Assigned to RP112 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP109R<5:0>: Peripheral Output Function is Assigned to RP109 Output Pin bits (see Table11-3 for peripheral function numbers)  2009-2012 Microchip Technology Inc. DS70616G-page 267

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-57: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP118R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP113R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP118R<5:0>: Peripheral Output Function is Assigned to RP118 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP113R<5:0>: Peripheral Output Function is Assigned to RP113 Output Pin bits (see Table11-3 for peripheral function numbers) REGISTER 11-58: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP125R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP120R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP125R<5:0>: Peripheral Output Function is Assigned to RP125 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP120R<5:0>: Peripheral Output Function is Assigned to RP120 Output Pin bits (see Table11-3 for peripheral function numbers) DS70616G-page 268  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 11-59: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP127R<5:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP126R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP127R<5:0>: Peripheral Output Function is Assigned to RP127 Output Pin bits (see Table11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP126R<5:0>: Peripheral Output Function is Assigned to RP126 Output Pin bits (see Table11-3 for peripheral function numbers)  2009-2012 Microchip Technology Inc. DS70616G-page 269

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 270  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 12.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram Note1: This data sheet summarizes the features of Timer1 is shown in Figure12-1. of the dsPIC33EPXXX(GP/MC/MU)806/ The Timer1 module can operate in one of the following 810/814 and PIC24EPXXX(GP/GU)810/ modes: 814 families of devices. It is not intended to be a comprehensive reference source. • Timer mode To complement the information in this • Gated Timer mode data sheet, refer to Section 11. “Timers” • Synchronous Counter mode (DS70362) of the “dsPIC33E/PIC24E • Asynchronous Counter mode Family Reference Manual”, which is In Timer and Gated Timer modes, the input clock is available from the Microchip web site derived from the internal instruction cycle clock (FCY). (www.microchip.com). In Synchronous and Asynchronous Counter modes, 2: Some registers and associated bits the input clock is derived from the external clock input described in this section may not be at the T1CK pin. available on all devices. Refer to The Timer modes are determined by the following bits: Section4.0 “Memory Organization” in this data sheet for device-specific register • Timer Clock Source Control bit (TCS): T1CON<1> and bit information. • Timer Synchronization Control bit (TSYNC): T1CON<2> The Timer1 module is a 16-bit timer, which can serve • Timer Gate Control bit (TGATE): T1CON<6> as the time counter for the real-time clock, or operate Timer control bit setting for different operating modes as a free-running interval timer/counter. are given in the Table12-1. The Timer1 module has the following unique features over other timers: TABLE 12-1: TIMER MODE SETTINGS • Can be operated from the low-power 32 kHz Mode TCS TGATE TSYNC crystal oscillator available on the device. • Can be operated in Asynchronous Counter mode Timer 0 0 x from an external clock source. Gated Timer 0 1 x • The external clock input (T1CK) can optionally be Synchronous Counter 1 x 1 synchronized to the internal device clock and clock synchronization is performed after the prescaler. Asynchronous Counter 1 x 0 FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Gate Falling Edge 1 Sync Detect Set T1IF Flag 0 FP(1) Prescaler 10 (/n) T1CLK TGATE Data Reset 00 TMR1 Latch TCKPS<1:0> 0 CLK SOSCO/ x1 T1CK Prescaler Sync 1 Comparator Equal (/n) TGATE TSYNC SOSCI TCKPS<1:0> TCS PR1 LPOSCEN(2) Note 1: FP is the peripheral clock. 2: See Section9.0 “Oscillator Configuration” for information on enabling the Secondary Oscillator (SOSC).  2009-2012 Microchip Technology Inc. DS70616G-page 271

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 12.1 Timer Resources 12.1.1 KEY RESOURCES Many useful resources related to Timers are provided • Section 11. “Timers” (DS70362) in the on the main product page of the Microchip web site for “dsPIC33E/PIC24E Family Reference Manual” the devices listed in this data sheet. This product page, • Code Samples which can be accessed using this link, contains the • Application Notes latest updates and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All related “dsPIC33E/PIC24E Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en554310 DS70616G-page 272  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 12.2 Timer1 Control Register REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS<1:0> — TSYNC(1) TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit(1) 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0> Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit(1) When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit(1) 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FP) bit 0 Unimplemented: Read as ‘0’ Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any attempts by user software to write to the TMR1 register are ignored.  2009-2012 Microchip Technology Inc. DS70616G-page 273

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 274  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 13.0 TIMER2/3, TIMER4/5, TIMER6/7 Individually, all eight of the 16-bit timers can function as AND TIMER8/9 synchronous timers or counters. They also offer the features listed above, except for the event trigger; this is implemented only with Timer2/3. The operating Note1: This data sheet summarizes modes and enabled features are determined by setting the features of the the appropriate bit(s) in the T2CON, T3CON, T4CON, dsPIC33EPXXX(GP/MC/MU)806/810/814 T5CON, T6CON, T7CON, T8CON and T9CON and PIC24EPXXX(GP/GU)810/814 family registers. T2CON, T4CON, T6CON and T8CON are of devices. It is not intended to be a shown in generic form in Register13-1. T3CON, comprehensive reference source. To T5CON, T7CON and T9CON are shown in complement the information in this data Register13-2. sheet, refer to Section 11. “Timers” (DS70362) of the “dsPIC33E/PIC24E For 32-bit timer/counter operation, Timer2, Timer4, Family Reference Manual”, which is Timer6 or Timer8 is the least significant word; Timer3, available from the Microchip web site Timer5, Timer7 or Timer9 is the most significant word (www.microchip.com). of the 32-bit timers. 2: Some registers and associated bits Note: For 32-bit operation, T3CON, T5CON, described in this section may not be T7CON and T9CON control bits are available on all devices. Refer to ignored. Only T2CON, T4CON, T6CON Section4.0 “Memory Organization” in and T8CON control bits are used for setup this data sheet for device-specific register and control. Timer2, Timer4, Timer6 and and bit information. Timer8 clock and gate inputs are utilized for the 32-bit timer modules, but an The Timer2/3, Timer4/5, Timer6/7 and Timer8/9 interrupt is generated with the Timer3, modules are 32-bit timers, which can also be Timer5, Ttimer7 and Timer9 interrupt configured as four independent 16-bit timers with flags. selectable operating modes. As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and A block diagram for an example 32-bit timer pair is Timer8/9 operate in three modes: shown Figure13-3. • Two Independent 16-Bit Timers (e.g., Timer2 and Note: Only Timer2, 3, 4 and 5 can trigger a DMA Timer3) with all 16-Bit Operating modes (except data transfer. Asynchronous Counter mode) • Single 32-Bit Timer • Single 32-Bit Synchronous Counter They also support these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation during Idle and Sleep modes • Interrupt on a 32-Bit Period Register Match • Time Base for Input Capture and Output Compare Modules (Timer2 and Timer3 only) • ADC1 Event Trigger (Timer2/3 only) • ADC2 Event Trigger (Timer4/5 only)  2009-2012 Microchip Technology Inc. DS70616G-page 275

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 13-1: TYPE B TIMERx BLOCK DIAGRAM (x = 2, 4, 6 AND 8) Gate Falling Edge Sync Detect 1 Set TxIF Flag 0 FP(1) Prescaler 10 TGATE (/n) TxCLK Data Reset Latch TCKPS<1:0> 00 TMRx CLK TxCK Prescaler Sync x1 Equal (/n) Comparator TGATE TCKPS<1:0> TCS PRx Note 1: FP is the peripheral clock. FIGURE 13-2: TYPE C TIMERx BLOCK DIAGRAM (x = 3, 5, 7 AND 9) Gate Falling Edge Sync Detect 1 Set TxIF Flag 0 FP(1) Prescaler 10 (/n) TGATE TxCLK Data Reset TCKPS<1:0> 00 TMRx Latch CLK TxCK Prescaler Equal (/n) Sync x1 Comparator ADC Start of Conversion Trigger(2) TCKPS<1:0> TGATE PRx TCS Note 1: FP is the peripheral clock. 2: The ADC trigger is available on TMR3 and TMR5 only. DS70616G-page 276  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 13-3: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER) Gate Falling Edge 1 Sync Detect Set TyIF Flag PRx PRy 0 TGATE Equal ADC Comparator Data FP(1) Prescaler 10 (/n) CLK lsw msw Latch Reset 00 TMRx TMRy TCKPS<1:0> TxCK Prescaler Sync x1 (/n) TMRyHLD TCKPS<1:0> TGATE TCS Data Bus<15:0> Note 1: The ADC trigger is available only on the TMR3:TMR2 andTMR5:TMR4 32-bit timer pairs. 2: Timerx is a Type B timer (x = 2, 4, 6 and 8). 3: Timery is a Type C timer (x = 3, 5, 7 and 9). 13.1 Timer Resources 13.1.1 KEY RESOURCES Many useful resources related to timers are provided • Section 11. “Timers” (DS70362) in the on the main product page of the Microchip web site for “dsPIC33E/PIC24E Family Reference Manual” the devices listed in this data sheet. This product page, • Code Samples which can be accessed using this link, contains the • Application Notes latest updates and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All related “dsPIC33E/PIC24E Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en554310  2009-2012 Microchip Technology Inc. DS70616G-page 277

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 13.2 Timerx/y Control Registers REGISTER 13-1: TxCON: (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS<1:0> T32 — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When T32 = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When T32 = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timerx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(1) 1 = External clock from TxCK pin (on the rising edge) 0 = Internal clock (FP) bit 0 Unimplemented: Read as ‘0’ Note 1: The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins. DS70616G-page 278  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 13-2: TyCON: (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(2) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS<1:0>(1) — — TCS(1,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timery Stop in Idle Mode bit(2) 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(1,3) 1 = External clock from TyCK pin (on the rising edge) 0 = Internal clock (FP) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through TxCON. 2: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: The TyCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.  2009-2012 Microchip Technology Inc. DS70616G-page 279

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 280  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 14.0 INPUT CAPTURE The input capture module is useful in applications requiring frequency (period) and pulse measurement. Note1: This data sheet summarizes the features The dsPIC33EPXXX(GP/MC/MU)806/810/814 and of the dsPIC33EPXXX(GP/MC/MU)806/ PIC24EPXXX(GP/GU)810/814 devices support up to 810/814 and PIC24EPXXX(GP/GU)810/ 16 input capture channels. 814 families of devices. It is not intended Key features of the input capture module include: to be a comprehensive reference source. To complement the information in this • Hardware-configurable for 32-bit operation in all data sheet, refer to Section 12. “Input modes by cascading two adjacent modules Capture” (DS70352) of the “dsPIC33E/ • Synchronous and Trigger modes of output PIC24E Family Reference Manual”, compare operation, with up to 30 user-selectable which is available from the Microchip web Trigger/Sync sources available site (www.microchip.com). • A 4-level FIFO buffer for capturing and holding 2: Some registers and associated bits timer values for several events described in this section may not be • Configurable interrupt generation available on all devices. Refer to • Up to six clock sources available for each module, Section4.0 “Memory Organization” in driving a separate internal 16-bit counter this data sheet for device-specific register Note: Only IC1, IC2, IC3 and IC4 can trigger a and bit information. DMA data transfer. If DMA data transfers are required, the FIFO buffer size must be set to ‘1’ (ICI<1:0> = 00). FIGURE 14-1: INPUT CAPTURE MODULE BLOCK DIAGRAM ICM<2:0> ICI<1:0> Prescaler Edge Detect Logic Event and Set ICxIF Counter and Interrupt 1:1/4/16 Clock Synchronizer Logic ICx Pin ICTSEL<2:0> FP Increment T1CLK 16 Clock ICxTMR 4-Level FIFO Buffer Select 16 T5CLK Trigger and Reset 16 Trigger and Sync Logic ICxBUF SYNCSEL<4:0> Sync Sources Trigger(1) ICOV, ICBNE System Bus Note 1: The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for proper ICx module operation or the Trigger/Sync source must be changed to another source option.  2009-2012 Microchip Technology Inc. DS70616G-page 281

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 14.1 Input Capture Resources 14.1.1 KEY RESOURCES Many useful resources related to input capture are pro- • Section 12. “Input Capture” (DS70352) in the vided on the main product page of the Microchip web “dsPIC33E/PIC24E Family Reference Manual” site for the devices listed in this data sheet. This product • Code Samples page, which can be accessed using this link, contains • Application Notes the latest updates and additional information. • Software Libraries Note: In the event you are not able to access the • Webinars product page using the link above, enter • All related “dsPIC33E/PIC24E Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en554310 DS70616G-page 282  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 14.2 Input Capture Control Registers REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL<2:0> — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/HC/HS-0 R/HC/HS-0 R/W-0 R/W-0 R/W-0 — ICI<1:0> ICOV ICBNE ICM<2:0> bit 7 bit 0 Legend: R = Readable bit HC = Hardware Clearable bit HS = Hardware Settable bit ‘0’ = Bit is cleared -n = Value at POR W = Writable bit U = Unimplemented bit, read as ‘0’ bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Stop in Idle Control bit 1 = Input capture will Halt in CPU Idle mode 0 = Input capture will continue to operate in CPU Idle mode bit 12-10 ICTSEL<12:10>: Input Capture Timer Select bits 111 = Peripheral clock (FP) is the clock source of the ICx 110 = Reserved 101 = Reserved 100 = Clock source of T1CLK is the clock source of the ICx (only the synchronous clock is supported) 011 = Clock source of T5CLK is the clock source of the ICx 010 = Clock source of T4CLK is the clock source of the ICx 001 = Clock source of T2CLK is the clock source of the ICx 000 = Clock source of T3CLK is the clock source of the ICx bit 9-7 Unimplemented: Read as ‘0’ bit 6-5 ICI<1:0>: Number of Captures per Interrupt Select bits (this field is not used if ICM<2:0>=001 or 111) 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture buffer overflow occurred 0 = No input capture buffer overflow occurred bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only in CPU Sleep and Idle modes (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge (Prescaler Capture mode) 100 = Capture mode, every 4th rising edge (Prescaler Capture mode) 011 = Capture mode, every rising edge (Simple Capture mode) 010 = Capture mode, every falling edge (Simple Capture mode) 001 = Capture mode, every edge rising and falling (Edge Detect mode (ICI<1:0>) is not used in this mode) 000 = Input capture module is turned off  2009-2012 Microchip Technology Inc. DS70616G-page 283

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W/HS-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG(2) TRIGSTAT(3) — SYNCSEL<4:0>(4) bit 7 bit 0 Legend: R = Readable bit HS = Set by Hardware ‘0’ = Bit is cleared -n = Value at POR W = Writable bit U = Unimplemented bit, read as ‘0’ bit 15-9 Unimplemented: Read as ‘0’ bit 8 IC32: 32-Bit Timer Mode Select bit (Cascade mode) 1 = ODD IC and EVEN IC form a single 32-bit input capture module(1) 0 = Cascade module operation is disabled bit 7 ICTRIG: Trigger Operation Select bit(2) 1 = Input source is used to trigger the input capture timer (Trigger mode) 0 = Input source is used to synchronize the input capture timer to a timer of another module (Synchronization mode) bit 6 TRIGSTAT: Timer Trigger Status bit(3) 1 = ICxTMR has been triggered and is running 0 = ICxTMR has not been triggered and is being held clear bit 5 Unimplemented: Read as ‘0’ Note 1: The IC32 bit in both the ODD and EVEN IC must be set to enable Cascade mode. 2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register. 3: This bit is set by the selected input source (selected by the SYNCSEL<4:0> bits); it can be read, set and cleared in software. 4: Do not use the ICx module as its own Sync or Trigger source. 5: This option should only be selected as a trigger source and not as a synchronization source. DS70616G-page 284  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits(4) 11111 = No Sync or Trigger source for ICx 11110 = No Sync or Trigger source for ICx 11101 = No Sync or Trigger source for ICx 11100 = Reserved 11011 = ADC1 module synchronizes or triggers ICx(5) 11010 = CMP3 module synchronizes or triggers ICx(5) 11001 = CMP2 module synchronizes or triggers ICx(5) 11000 = CMP1 module synchronizes or triggers ICx(5) 10111 = IC8 module synchronizes or triggers ICx 10110 = IC7 module synchronizes or triggers ICx 10101 = IC6 module synchronizes or triggers ICx 10100 = IC5 module synchronizes or triggers ICx 10011 = IC4 module synchronizes or triggers ICx 10010 = IC3 module synchronizes or triggers ICx 10001 = IC2 module synchronizes or triggers ICx 10000 = IC1 module synchronizes or triggers ICx 01111 = Timer5 synchronizes or triggers ICx 01110 = Timer4 synchronizes or triggers ICx 01101 = Timer3 synchronizes or triggers ICx (default) 01100 = Timer2 synchronizes or triggers ICx 01011 = Timer1 synchronizes or triggers ICx 01010 = No Sync or Trigger source for ICx 01001 = OC9 module synchronizes or triggers ICx 01000 = OC8 module synchronizes or triggers ICx 00111 = OC7 module synchronizes or triggers ICx 00110 = OC6 module synchronizes or triggers ICx 00101 = OC5 module synchronizes or triggers ICx 00100 = OC4 module synchronizes or triggers ICx 00011 = OC3 module synchronizes or triggers ICx 00010 = OC2 module synchronizes or triggers ICx 00001 = OC1 module synchronizes or triggers ICx 00000 = No Sync or Trigger source for ICx Note 1: The IC32 bit in both the ODD and EVEN IC must be set to enable Cascade mode. 2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register. 3: This bit is set by the selected input source (selected by the SYNCSEL<4:0> bits); it can be read, set and cleared in software. 4: Do not use the ICx module as its own Sync or Trigger source. 5: This option should only be selected as a trigger source and not as a synchronization source.  2009-2012 Microchip Technology Inc. DS70616G-page 285

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dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 15.0 OUTPUT COMPARE The output compare module can select one of eight available clock sources for its time base. The module Note1: This data sheet summarizes the features compares the value of the timer with the value of one or of the dsPIC33EPXXX(GP/MC/MU)806/ two Compare registers, depending on the operating 810/814 and PIC24EPXXX(GP/GU)810/ mode selected. The state of the output pin changes 814 families of devices. It is not intended when the timer value matches the Compare register to be a comprehensive reference source. value. The output compare module generates either a To complement the information in this single output pulse, or a sequence of output pulses, by data sheet, refer to Section 13. “Output changing the state of the output pin on the compare Compare” (DS70358) of the “dsPIC33E/ match events. The output compare module can also PIC24E Family Reference Manual”, generate interrupts on compare match events. which is available from the Microchip web site (www.microchip.com). Note 1: Only OC1, OC2, OC3 and OC4 can trigger a DMA data transfer. 2: Some registers and associated bits described in this section may not be 2: See Section 13. “Output Compare” available on all devices. Refer to (DS70358) in the “dsPIC33E/PIC24E Section4.0 “Memory Organization” in Family Reference Manual” for OCxR and this data sheet for device-specific register OCxRS register restrictions. and bit information. FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM OCxCON1 OCxCON2 OCxR Rollover/Reset OCxR Buffer OCx Pin FP T1CLK Comparator Clock Increment Match Select Event OCFC OC Output and OCxTMR T5CLK Rollover Fault Logic Reset OCFB Comparator Match Event Match OCFA Trigger and Event Trigger and Sync Logic Sync Sources OCxRS Buffer SYNCSEL<4:0> Trigger(1) Rollover/Reset OCx Synchronization/Trigger Event OCxRS Reset OCx Interrupt Note 1: The Trigger/Sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for proper OCx module operation or the Trigger/Sync source must be changed to another source option.  2009-2012 Microchip Technology Inc. DS70616G-page 287

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 15.1 Output Compare Resources 15.1.1 KEY RESOURCES Many useful resources related to output compare are • Section 13. “Output Compare” (DS70358) in provided on the main product page of the Microchip the “dsPIC33E/PIC24E Family Reference web site for the devices listed in this data sheet. This Manual” product page, which can be accessed using this link, • Code Samples contains the latest updates and additional information. • Application Notes Note: In the event you are not able to access the • Software Libraries product page using the link above, enter • Webinars this URL in your browser: • All related “dsPIC33E/PIC24E Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en554310 • Development Tools DS70616G-page 288  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 15.2 Output Compare Control Registers REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OCSIDL OCTSEL<2:0> ENFLTC ENFLTB bit 15 bit 8 R/W-0 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> bit 7 bit 0 Legend: HCS = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare x in Idle Mode Control bit 1 = Output Compare x Halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-10 OCTSEL<2:0>: Output Compare x Clock Select bits 111 = Peripheral clock (FP) 110 = Reserved 101 = Reserved 100 = Clock source of T1CLK is the clock source of OCx (only the synchronous clock is supported) 011 = Clock source of T5CLK is the clock source of OCx 010 = Clock source of T4CLK is the clock source of OCx 001 = Clock source of T3CLK is the clock source of OCx 000 = Clock source of T2CLK is the clock source of OCx bit 9 ENFLTC: Fault C Input Enable bit 1 = Output Compare Fault C input (OCFC) is enabled 0 = Output Compare Fault C input (OCFC) is disabled bit 8 ENFLTB: Fault B Input Enable bit 1 = Output Compare Fault B input (OCFB) is enabled 0 = Output Compare Fault B input (OCFB) is disabled bit 7 ENFLTA: Fault A Input Enable bit 1 = Output Compare Fault A input (OCFA) is enabled 0 = Output Compare Fault A input (OCFA) is disabled bit 6 OCFLTC: PWM Fault C Condition Status bit 1 = PWM Fault C condition on OCFC pin has occurred 0 = No PWM Fault C condition on OCFC pin has occurred bit 5 OCFLTB: PWM Fault B Condition Status bit 1 = PWM Fault B condition on OCFB pin has occurred 0 = No PWM Fault B condition on OCFB pin has occurred bit 4 OCFLTA: PWM Fault A Condition Status bit 1 = PWM Fault A condition on OCFA pin has occurred 0 = No PWM Fault A condition on OCFA pin has occurred bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is cleared only by software Note 1: OCxR and OCxRS are double-buffered in PWM mode only.  2009-2012 Microchip Technology Inc. DS70616G-page 289

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = Center-Aligned PWM mode: Output set high when OCxTMR = OCxR and set low when OCxTMR = OCxRS(1) 110 = Edge-Aligned PWM mode: Output set high when OCxTMR = 0 and set low when OCxTMR = OCxR(1) 101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare mode: Compares events with OCxR, continuously toggles OCx pin 010 = Single Compare Single-Shot mode: Initializes OCx pin high, compares event with OCxR, forces OCx pin low 001 = Single Compare Single-Shot mode: Initializes OCx pin low, compares event with OCxR, forces OCx pin high 000 = Output compare channel is disabled Note 1: OCxR and OCxRS are double-buffered in PWM mode only. DS70616G-page 290  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 bit 15 bit 8 R/W-0 R/W-0 HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTx bit is cleared in software and a new PWM period starts 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts bit 14 FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault bit 13 FLTTRIEN: Fault Output State Select bit 1 = OCx pin is tri-stated on Fault condition 0 = OCx pin I/O state defined by FLTOUT bit on Fault condition bit 12 OCINV: OCMP Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted bit 11-9 Unimplemented: Read as ‘0’ bit 8 OC32: Cascade Two OCx Modules Enable bit (32-bit operation) 1 = Cascade module operation is enabled 0 = Cascade module operation is disabled bit 7 OCTRIG: OCx Trigger/Sync Select bit 1 = Triggers OCx from source designated by SYNCSELx bits 0 = Synchronizes OCx with source designated by SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear bit 5 OCTRIS: OCx Output Pin Direction Select bit 1 = OCx is tri-stated 0 = Output compare module drives the OCx pin Note 1: Do not use the OCx module as its own Sync or Trigger source. 2: When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module uses the OCy module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it.  2009-2012 Microchip Technology Inc. DS70616G-page 291

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = No Sync or Trigger source for OCx 11110 = INT2 pin synchronizes or triggers OCx 11101 = INT1 pin synchronizes or triggers OCx 11100 = Reserved 11011 = ADC1 module synchronizes or triggers OCx 11010 = CMP3 module synchronizes or triggers OCx 11001 = CMP2 module synchronizes or triggers OCx 11000 = CMP1 module synchronizes or triggers OCx 10111 = IC8 module synchronizes or triggers OCx 10110 = IC7 module synchronizes or triggers OCx 10101 = IC6 module synchronizes or triggers OCx 10100 = IC5 module synchronizes or triggers OCx 10011 = IC4 module synchronizes or triggers OCx 10010 = IC3 module synchronizes or triggers OCx 10001 = IC2 module synchronizes or triggers OCx 10000 = IC1 module synchronizes or triggers OCx 01111 = Timer5 synchronizes or triggers OCx 01110 = Timer4 synchronizes or triggers OCx 01101 = Timer3 synchronizes or triggers OCx 01100 = Timer2 synchronizes or triggers OCx (default) 01011 = Timer1 synchronizes or triggers OCx 01010 = No Sync or Trigger source for OCx 01001 = OC9 module synchronizes or triggers OCx(1,2) 01000 = OC8 module synchronizes or triggers OCx(1,2) 00111 = OC7 module synchronizes or triggers OCx(1,2) 00110 = OC6 module synchronizes or triggers OCx(1,2) 00101 = OC5 module synchronizes or triggers OCx(1,2) 00100 = OC4 module synchronizes or triggers OCx(1,2) 00011 = OC3 module synchronizes or triggers OCx(1,2) 00010 = OC2 module synchronizes or triggers OCx(1,2) 00001 = OC1 module synchronizes or triggers OCx(1,2) 00000 = No Sync or Trigger source for OCx Note 1: Do not use the OCx module as its own Sync or Trigger source. 2: When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module uses the OCy module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it. DS70616G-page 292  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 16.0 HIGH-SPEED PWM MODULE • Complementary PWM outputs (dsPIC33EPXXX(MC/MU)8XX • Push-Pull PWM outputs DEVICES ONLY) • Redundant PWM outputs • Edge-Aligned PWM mode Note1: This data sheet summarizes the features • Center-Aligned PWM mode of the dsPIC33EPXXX(GP/MC/MU)806/ • Variable Phase PWM mode 810/814 and PIC24EPXXX(GP/GU)810/ • Multi-Phase PWM mode 814 families of devices. It is not intended to be a comprehensive • Fixed Off Time PWM mode reference source. To complement the • Current-Limit PWM mode information in this data sheet, refer to • Current Reset PWM mode Section 14. “High-Speed PWM” • PWMxH and PWMxL output override control (DS70645) of the “dsPIC33E/PIC24E • PWMxH and PWMxL output pin swapping Family Reference Manual”, which is • Chopping mode (also known as Gated mode) available from the Microchip web site (www.microchip.com). • Dead-time insertion • Dead-time compensation 2: Some registers and associated bits described in this section may not be • Enhanced Leading-Edge Blanking (LEB) available on all devices. Refer to • 8 mA PWM pin output drive Section4.0 “Memory Organization” in Note: Duty cycle, dead time, phase shift and this data sheet for device-specific register frequency resolution is 16.64 ns in and bit information. Center-Aligned PWM mode. The dsPIC33EPXXX(MC/MU)806/810/814 devices The high-speed PWM module contains up to seven support a dedicated Pulse-Width Modulation (PWM) PWM generators. Each PWM generator provides two module with up to 14 outputs. PWM outputs: PWMxH and PWMxL. Two master time The high-speed PWM module consists of the following base generators provide a synchronous signal as a major features: common time base to synchronize the various PWM outputs. Each generator can operate independently or • Two master time base modules with Special in synchronization with either of the two master time Event Triggers bases. The individual PWM outputs are available on • PWM module input clock prescaler the output pins of the device. The input Fault signals • Two synchronization inputs and current-limited signals, when enabled, can monitor • Two synchronization outputs and protect the system by placing the PWM outputs into a known “safe” state. • Up to seven PWM generators • Two PWM outputs per generator (PWMxH and Each PWM can generate a trigger to the ADC module PWMxL) to sample the analog signal at a specific instance dur- ing the PWM period. In addition, the high-speed PWM • Individual period, duty cycle and phase shift for module also generates two Special Event Triggers to each PWM output the ADC module based on the two master time bases. • Period, duty cycle, phase shift and dead-time resolution of 8.32 ns The high-speed PWM module can synchronize itself with an external signal or can act as a synchronizing • Immediate update mode for PWM period, duty source to any external device. The SYNCI1 and cycle and phase shift SYNCI2 pins are the input pins, which can synchronize • Independent Fault and current-limited inputs for the high-speed PWM module with an external signal. each PWM The SYNCO1 and SYNCO2 pins are output pins that • Cycle-by-Cycle and Latched Fault modes provides a synchronous signal to an external device. • PWM time-base capture upon current limit Figure16-1 illustrates an architectural overview of the • Seven Fault inputs and three comparator outputs high-speed PWM module and its interconnection with available for Faults and current limits the CPU and other peripherals. • Programmable ADC trigger with interrupt for each PWM pair  2009-2012 Microchip Technology Inc. DS70616G-page 293

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 16-1: HIGH-SPEED PWM MODULE ARCHITECTURAL OVERVIEW SYNCI1/SYNCI2 Data Bus Primary and Secondary FOSC Master Time Base SYNCO1/SYNCO2 SynchronizationSignal PWM1Interrupt PWM1H PWM Generator 1 PWM1L Fault, Current-Limit and Dead-Time Compensation SynchronizationSignal PWM2Interrupt PWM2H PWM Generator 2 PWM2L Fault, Current-Limit and Dead-Time Compensation CPU PWM3 through PWM5 SynchronizationSignal PWM6Interrupt PWM6H PWM Generator 6 PWM6L Fault, Current-Limit and Dead-Time Compensation SynchronizationSignal PWM7Interrupt PWM7H PWM Generator 7 Primary Trigger PWM7L Primary Special Event Trigger ADC Module Fault, Current-Limit and Dead-Time Compensation Secondary Special FLT1-FLT7 and Event Trigger DTCMP1-DTCMP7 DS70616G-page 294  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 16-2: HIGH-SPEED PWM MODULE REGISTER INTERCONNECTION DIAGRAM FOSC PTCON, PTCON2 Module Control and Timing SYNCI1 SYNCI2 SYNCO1 PTPER SEVTCMP Special Event Compare Trigger Special Event Comparator Comparator Postscaler Special Event Trigger Master Time Base Counter Clock PMTMR Prescaler Primary Master Time Base SYNCO2 PTPER SEVTCMP Special Event Compare Trigger Special Event Comparator Comparator Postscaler Special Event Trigger Master Time Base Counter Clock PMTMR Prescaler Secondary Master Time Base MDC Duty Cycle Register n zatio ycle PDCx PWM Generator 1 ni C chro Duty MUX Syn Master Period Comparator PWMCAPx PWCMo nOtruotlp Luot gMicode er us Mast PTMRx ADC Trigger User Override Logic Dead-Time CoPnintrol PWM1H Data B PHASEx Comparator OCvuerrrreidnet- LLiomgiitc Logic Logic PWM1L Bit TRIGx Fault Override Logic 6- SDCx 1 Secondary PWM MUX Comparator Interrupt Fault and FLT1 Logic Current-Limit Logic DTCMP1 STMRx n o ati niz SPHASEx FCLCONx IOCONx ALTDTRx o Synchr aster Duty Cycle Master Period PWMCONx TRGCONx LEBCONx DTRx M PWMxH PWMxL PWM Generator 2 – PWM Generator 7 FLTx DTCMPx  2009-2012 Microchip Technology Inc. DS70616G-page 295

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 16.1 PWM Resources 16.1.1 KEY RESOURCES Many useful resources related to the high-speed PWM • Section 11. “High-Speed PWM” (DS70645) in are provided on the main product page of the Microchip the “dsPIC33E/PIC24E Family Reference web site for the devices listed in this data sheet. This Manual” product page, which can be accessed using this link, • Code Samples contains the latest updates and additional information. • Application Notes • Software Libraries Note: In the event you are not able to access the product page using the link above, enter • Webinars this URL in your browser: • All related “dsPIC33E/PIC24E Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en554310 • Development Tools DS70616G-page 296  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 16.2 PWM Control Registers REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 HSC-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN — PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN(1) SYNCSRC<2:0>(1) SEVTPS<3:0>(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode bit 12 SESTAT: Special Event Interrupt Status bit 1 = Special event interrupt is pending 0 = Special event interrupt is not pending bit 11 SEIEN: Special Event Interrupt Enable bit 1 = Special event interrupt is enabled 0 = Special event interrupt is disabled bit 10 EIPU: Enable Immediate Period Updates bit(1) 1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWM cycle boundaries bit 9 SYNCPOL: Synchronize Input and Output Polarity bit(1) 1 = SYNCIx/SYNCO polarity is inverted (active-low) 0 = SYNCIx/SYNCO is active-high bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1) 1 = SYNCO output is enabled 0 = SYNCO output is disabled bit 7 SYNCEN: External Time Base Synchronization Enable bit(1) 1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user application must program the Period register with a value that is slightly larger than the expected period of the external synchronization input signal.  2009-2012 Microchip Technology Inc. DS70616G-page 297

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED) bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1) 111 = Reserved • • • 010 = Reserved 001 = SYNCI2 000 = SYNCI1 bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user application must program the Period register with a value that is slightly larger than the expected period of the external synchronization input signal. DS70616G-page 298  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-2: PTCON2: PWM PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide-by-64 101 = Divide-by-32 100 = Divide-by-16 011 = Divide-by-8 010 = Divide-by-4 001 = Divide-by-2 000 = Divide-by-1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. REGISTER 16-3: PTPER: PRIMARY MASTER TIME BASE PERIOD REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PTPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PTPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits  2009-2012 Microchip Technology Inc. DS70616G-page 299

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-4: SEVTCMP: PWM PRIMARY SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SEVTCMP<15:0>: Special Event Compare Count Value bits DS70616G-page 300  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER U-0 U-0 U-0 HSC-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — SESTAT SEIEN EIPU(1) SYNCPOL SYNCOEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN SYNCSRC<2:0> SEVTPS<3:0> bit 7 bit 0 Legend: HSC = Set or Cleared in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 SESTAT: Special Event Interrupt Status bit 1 = Secondary special event interrupt is pending 0 = Secondary special event interrupt is not pending bit 11 SEIEN: Special Event Interrupt Enable bit 1 = Secondary special event interrupt is enabled 0 = Secondary special event interrupt is disabled bit 10 EIPU: Enable Immediate Period Updates bit(1) 1 = Active Secondary Period register is updated immediately 0 = Active Secondary Period register updates occur on PWM cycle boundaries bit 9 SYNCPOL: Synchronize Input and Output Polarity bit 1 = The falling edge of SYNCIN resets the SMTMR; SYNCO2 output is active-low 0 = The rising edge of SYNCIN resets the SMTMR; SYNCO2 output is active-high bit 8 SYNCOEN: Secondary Master Time Base Synchronization Enable bit 1 = SYNCO2 output is enabled 0 = SYNCO2 output is disabled bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit 1 = External synchronization of secondary time base is enabled 0 = External synchronization of secondary time base is disabled bit 6-4 SYNCSRC<2:0>: Secondary Time Base Synchronization Source Selection bits 111 = Reserved • • • 010 = Reserved 001 = SYNCI2 000 = SYNCI1 bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits 1111 = 1:16 Postcale • • • 0001 = 1:2 Postcale 0000 = 1:1 Postscale Note 1: This bit only applies to the secondary master time base period.  2009-2012 Microchip Technology Inc. DS70616G-page 301

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-6: STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide-by-64 101 = Divide-by-32 100 = Divide-by-16 011 = Divide-by-8 010 = Divide-by-4 001 = Divide-by-2 000 = Divide-by-1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. REGISTER 16-7: STPER: SECONDARY MASTER TIME BASE PERIOD REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 STPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 STPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STPER<15:0>: Secondary Master Time Base (PMTMR) Period Value bits DS70616G-page 302  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-8: SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEVTCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEVTCMP<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SSEVTCMP<15:0>: Special Event Compare Count Value bits REGISTER 16-9: CHOP: PWM CHOP CLOCK GENERATOR REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 CHPCLKEN — — — — — CHOPCLK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHOPCLK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHPCLKEN: Enable Chop Clock Generator bit 1 = Chop clock generator is enabled 0 = Chop clock generator is disabled bit 14-10 Unimplemented: Read as ‘0’ bit 9-0 CHOPCLK<9:0>: Chop Clock Divider bits The frequency of the chop clock signal is given by the following expression: Chop Frequency = FPWM/(CHOP<9:0> + 1) Where, FPWM is FP divided by the value based on the PCLKDIV settings.  2009-2012 Microchip Technology Inc. DS70616G-page 303

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-10: MDC: PWM MASTER DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 MDC<15:0>: Master PWM Duty Cycle Value bits DS70616G-page 304  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-11: PWMCONx: PWMx CONTROL REGISTER HSC-0 HSC-0 HSC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(2) MDCS(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DTC<1:0> DTCP(3) — MTBS CAM(2,4) XPRES(5) IUE(2) bit 7 bit 0 Legend: HSC = Set or Cleared in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTSTAT: Fault Interrupt Status bit(1) 1 = Fault interrupt is pending 0 = No Fault interrupt is pending This bit is cleared by setting FLTIEN = 0. bit 14 CLSTAT: Current-Limit Interrupt Status bit(1) 1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending This bit is cleared by setting CLIEN = 0. bit 13 TRGSTAT: Trigger Interrupt Status bit 1 = Trigger interrupt is pending 0 = No trigger interrupt is pending This bit is cleared by setting TRGIEN = 0. bit 12 FLTIEN: Fault Interrupt Enable bit 1 = Fault interrupt is enabled 0 = Fault interrupt is disabled and FLTSTAT bit is cleared bit 11 CLIEN: Current-Limit Interrupt Enable bit 1 = Current-limit interrupt is enabled 0 = Current-limit interrupt is disabled and CLSTAT bit is cleared bit 10 TRGIEN: Trigger Interrupt Enable bit 1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared bit 9 ITB: Independent Time Base Mode bit(2) 1 = PHASEx/SPHASEx registers provide time base period for this PWM generator 0 = PTPER register provides timing for this PWM generator bit 8 MDCS: Master Duty Cycle Register Select bit(2) 1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx and SDCx registers provide duty cycle information for this PWM generator Note 1: Software must clear the interrupt status here and in the corresponding IFS bit in the interrupt controller. 2: These bits should not be changed after the PWM is enabled (PTEN = 1). 3: DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored. 4: The Independent Time Base (ITB=1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx register must be ‘0’.  2009-2012 Microchip Technology Inc. DS70616G-page 305

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-11: PWMCONx: PWMx CONTROL REGISTER (CONTINUED) bit 7-6 DTC<1:0>: Dead-Time Control bits 11 = Dead-Time Compensation mode 10 = Dead-time function is disabled 01 = Negative dead time actively applied for Complementary Output mode 00 = Positive dead time actively applied for all output modes bit 5 DTCP: Dead-Time Compensation Polarity bit(3) When set to ‘1’: If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened. If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened. When set to ‘0’: If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened. If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened. bit 4 Unimplemented: Read as ‘0’ bit 3 MTBS: Master Time Base Select bit 1 = PWM generator uses the secondary master time base for synchronization and as the clock source for the PWM generation logic (if secondary time base is available) 0 = PWM generator uses the primary master time base for synchronization and as the clock source for the PWM generation logic bit 2 CAM: Center-Aligned Mode Enable bit(2,4) 1 = Center-Aligned mode is enabled 0 = Edge-Aligned mode is enabled bit 1 XPRES: External PWM Reset Control bit(5) 1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWM time base bit 0 IUE: Immediate Update Enable bit(2) 1 = Updates to the active MDC/PDCx/SDCx registers are immediate 0 = Updates to the active PDCx registers are synchronized to the PWM time base Note 1: Software must clear the interrupt status here and in the corresponding IFS bit in the interrupt controller. 2: These bits should not be changed after the PWM is enabled (PTEN = 1). 3: DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored. 4: The Independent Time Base (ITB=1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx register must be ‘0’. DS70616G-page 306  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-12: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDCx<15:0>: PWM Generator # Duty Cycle Value bits Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In theComplementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both the PWMxH and PWMxL. REGISTER 16-13: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SDCx<15:0>: Secondary Duty Cycle bits for PWMxL Output Pin bits Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle.  2009-2012 Microchip Technology Inc. DS70616G-page 307

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-14: PHASEx: PWMx PRIMARY PHASE SHIFT REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PHASEx<15:0>: PWM Phase Shift Value or Independent Time Base Period for the PWM Generator bits Note 1: If ITB (PWMCONx<9>) = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCON<11:10>) = 00, 01 or 10), PHASEx<15:0> = Phase shift value for PWMxH and PWMxL outputs. • True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11), PHASEx<15:0> = Phase shift value for PWMxH only. 2: If ITB (PWMCONx<9>) = 1, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10), PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL. • True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11), PHASEx<15:0> = Independent time base period value for PWMxH only. DS70616G-page 308  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-15: SPHASEx: PWMx SECONDARY PHASE SHIFT REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SPHASEx<15:0>: Secondary Phase Offset bits for PWMxL Output Pin (used in Independent PWM mode only) Note 1: If ITB (PWMCONx<9>) = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCON<11:10>) = 00, 01 or 10), SPHASEx<15:0> = Not used. • True Independent Output mode (PMOD<1:0> (IOCON<11:10>) = 11), SPHASEx<15:0> = Phase shift value for PWMxL only. 2: If ITB (PWMCONx<9>) = 1, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCON<11:10>) = 00, 01 or 10), SPHASEx<15:0> = Not used. • True Independent Output mode (PMOD<1:0> (IOCON<11:10>) = 11), SPHASEx<15:0> = Independent time base period value for PWMxL only.  2009-2012 Microchip Technology Inc. DS70616G-page 309

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-16: DTRx: PWMx DEAD-TIME REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits REGISTER 16-17: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ALTDTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALTDTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits DS70616G-page 310  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-18: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 TRGDIV<3:0> — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TRGSTRT<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits 1111 = Trigger output for every 16th trigger event 1110 = Trigger output for every 15th trigger event 1101 = Trigger output for every 14th trigger event 1100 = Trigger output for every 13th trigger event 1011 = Trigger output for every 12th trigger event 1010 = Trigger output for every 11th trigger event 1001 = Trigger output for every 10th trigger event 1000 = Trigger output for every 9th trigger event 0111 = Trigger output for every 8th trigger event 0110 = Trigger output for every 7th trigger event 0101 = Trigger output for every 6th trigger event 0100 = Trigger output for every 5th trigger event 0011 = Trigger output for every 4th trigger event 0010 = Trigger output for every 3rd trigger event 0001 = Trigger output for every 2nd trigger event 0000 = Trigger output for every trigger event bit 11-6 Unimplemented: Read as ‘0’ bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits(1) 111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled • • • 000010 = Wait 2 PWM cycles before generating the first trigger event after the module is enabled 000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled 000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled Note 1: The secondary PWM generator cannot generate PWM trigger interrupts.  2009-2012 Microchip Technology Inc. DS70616G-page 311

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-19: IOCONx: PWMx I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PENH PENL POLH POLL PMOD<1:0>(1) OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PENH: PWMxH Output Pin Ownership bit 1 = PWM module controls PWMxH pin 0 = GPIO module controls PWMxH pin bit 14 PENL: PWMxL Output Pin Ownership bit 1 = PWM module controls PWMxL pin 0 = GPIO module controls PWMxL pin bit 13 POLH: PWMxH Output Pin Polarity bit 1 = PWMxH pin is active-low 0 = PWMxH pin is active-high bit 12 POLL: PWMxL Output Pin Polarity bit 1 = PWMxL pin is active-low 0 = PWMxL pin is active-high bit 11-10 PMOD<1:0>: PWM # I/O Pin Mode bits(1) 11 = PWM I/O pin pair is in the True Independent Output mode 10 = PWM I/O pin pair is in the Push-Pull Output mode 01 = PWM I/O pin pair is in the Redundant Output mode 00 = PWM I/O pin pair is in the Complementary Output mode bit 9 OVRENH: Override Enable for PWMxH Pin bit 1 = OVRDAT<1> controls output on PWMxH pin 0 = PWM generator controls PWMxH pin bit 8 OVRENL: Override Enable for PWMxL Pin bit 1 = OVRDAT<0> controls output on PWMxL pin 0 = PWM generator controls PWMxL pin bit 7-6 OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits If OVERENH = 1, PWMxH is driven to the state specified by OVRDAT<1>. If OVERENL = 1, PWMxL is driven to the state specified by OVRDAT<0>. bit 5-4 FLTDAT<1:0>: Data for PWMxH and PWMxL Pins if FLTMOD is Enabled bits IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode: If Fault is active, PWMxH is driven to the state specified by FLTDAT<1>. If Fault is active, PWMxL is driven to the state specified by FLTDAT<0>. IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode: If current limit is active, PWMxH is driven to the state specified by FLTDAT<1>. If Fault is active, PWMxL is driven to the state specified by FLTDAT<0>. Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1). DS70616G-page 312  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-19: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: Data for PWMxH and PWMxL Pins if CLMOD is Enabled bits IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode: If current limit is active, PWMxH is driven to the state specified by CLDAT<1>. If current limit is active, PWMxL is driven to the state specified by CLDAT<0>. IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode: The CLDAT<1:0> bits are ignored. bit 1 SWAP: Swap PWMxH and PWMxL Pins bit 1 = PWMxH output signal is connected to PWMxL pins; PWMxL output signal is connected to PWMxH pins 0 = PWMxH and PWMxL pins are mapped to their respective pins bit 0 OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base 0 = Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock boundary Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1).  2009-2012 Microchip Technology Inc. DS70616G-page 313

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-20: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 TRGCMP<15:0>: PWM Primary Trigger Control Value bits When the primary PWM functions in local time base, this register contains the compare values that can trigger the ADC module. DS70616G-page 314  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-21: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFLTMOD CLSRC<4:0>(2,3) CLPOL(1) CLMOD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSRC<4:0>(2,3) FLTPOL(1) FLTMOD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IFLTMOD: Independent Fault Mode Enable bit 1 = Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output and Fault input maps FLTDAT<0> to PWMxL output; the CLDAT<1:0> bits are not used for override functions 0 = Normal Fault mode: Current-Limit mode maps CLDAT<1:0> bits to the PWMxH and PWMxL outputs; the PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs. bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM Generator # bits(2,3) 11111 = Reserved • • • 01001 = Reserved 01010 = Comparator 3 01001 = Comparator 2 01000 = Comparator 1 00111 = Reserved 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 9 CLPOL: Current-Limit Polarity bit for PWM Generator #(1) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high bit 8 CLMOD: Current-Limit Mode Enable bit for PWM Generator # 1 = Current-Limit mode is enabled 0 = Current-Limit mode is disabled Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = 01000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = 01000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.  2009-2012 Microchip Technology Inc. DS70616G-page 315

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-21: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select bits for PWM Generator #(2,3) 11111 = Reserved • • • 01011 = Reserved 01010 = Comparator 3 01001 = Comparator 2 01000 = Comparator 1 00111 = Reserved 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 2 FLTPOL: Fault Polarity bit for PWM Generator #(1) 1 = The selected Fault source is active-low 0 = The selected Fault source is active-high bit 1-0 FLTMOD<1:0>: Fault Mode bits for PWM Generator # 11 = Fault input is disabled 10 = Reserved 01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle) 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition) Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = 01000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = 01000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. DS70616G-page 316  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-22: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — BCH(1) BCL(1) BPHH BPHL BPLH BPLL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PWMxH Rising Edge Trigger Enable bit 1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxH bit 14 PHF: PWMxH Falling Edge Trigger Enable bit 1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxH bit 13 PLR: PWMxL Rising Edge Trigger Enable bit 1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxL bit 12 PLF: PWMxL Falling Edge Trigger Enable bit 1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxL bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit 1 = Leading-Edge Blanking is applied to selected Fault input 0 = Leading-Edge Blanking is not applied to selected Fault input bit 10 CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit 1 = Leading-Edge Blanking is applied to selected current-limit input 0 = Leading-Edge Blanking is not applied to selected current-limit input bit 9-6 Unimplemented: Read as ‘0’ bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1) 1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high 0 = No blanking when selected blanking signal is high bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit(1) 1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low 0 = No blanking when selected blanking signal is low bit 3 BPHH: Blanking in PWMxH High Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is high 0 = No blanking when PWMxH output is high bit 2 BPHL: Blanking in PWMxH Low Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is low 0 = No blanking when PWMxH output is low bit 1 BPLH: Blanking in PWMxL High Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is high 0 = No blanking when PWMxL output is high bit 0 BPLL: Blanking in PWMxL Low Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low 0 = No blanking when PWMxL output is low Note 1: The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.  2009-2012 Microchip Technology Inc. DS70616G-page 317

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-23: LEBDLYx: LEADING-EDGE BLANKING DELAY REGISTER x U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — LEB<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 LEB<11:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits DS70616G-page 318  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-24: AUXCONx: PWM AUXILIARY CONTROL REGISTER x U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — BLANKSEL<3:0> bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHOPSEL<3:0> CHOPHEN CHOPLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 BLANKSEL<3:0>: PWM State Blank Source Select bits The selected state blank signal will block the current-limit and/or Fault input signals (if enabled via the BCH and BCL bits in the LEBCONx register). 1001 = Reserved 1000 = Reserved 0111 = PWM7H selected as state blank source 0110 = PWM6H selected as state blank source 0101 = PWM5H selected as state blank source 0100 = PWM4H selected as state blank source 0011 = PWM3H selected as state blank source 0010 = PWM2H selected as state blank source 0001 = PWM1H selected as state blank source 0000 = No state blanking bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHOPSEL<3:0>: PWM Chop Clock Source Select bits The selected signal will enable and disable (CHOP) the selected PWM outputs. 1001 = Reserved 1000 = Reserved 0111 = PWM7H selected as CHOP clock source 0110 = PWM6H selected as CHOP clock source 0101 = PWM5H selected as CHOP clock source 0100 = PWM4H selected as CHOP clock source 0011 = PWM3H selected as CHOP clock source 0010 = PWM2H selected as CHOP clock source 0001 = PWM1H selected as CHOP clock source 0000 = Chop clock generator selected as CHOP clock source bit 1 CHOPHEN: PWMxH Output Chopping Enable bit 1 = PWMxH chopping function is enabled 0 = PWMxH chopping function is disabled bit 0 CHOPLEN: PWMxL Output Chopping Enable bit 1 = PWMxL chopping function is enabled 0 = PWMxL chopping function is disabled  2009-2012 Microchip Technology Inc. DS70616G-page 319

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 16-25: PWMCAPx: PRIMARY PWMx TIME BASE CAPTURE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<15:8>(1,2) bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<7:0>(1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PWMCAP<15:0>: Captured PWM Time Base Value bits(1,2) The value in this register represents the captured PWM time base value when a leading edge is detected on the current-limit input. Note 1: The capture feature is only available on primary output (PWMxH). 2: This feature is active only after LEB processing on the current-limit input signal is complete. DS70616G-page 320  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 17.0 QUADRATURE ENCODER This chapter describes the Quadrature Encoder Inter- INTERFACE (QEI) MODULE face (QEI) module and associated operational modes. The QEI module provides the interface to incremental (dsPIC33EPXXX(MC/MU)8XX encoders for obtaining mechanical position data. DEVICES ONLY) The operational features of the QEI module include: Note1: This data sheet summarizes the features • 32-Bit Position Counter of the dsPIC33EPXXX(GP/MC/MU)806/ • 32-Bit Index Pulse Counter 810/814 and PIC24EPXXX(GP/GU)810/ • 32-Bit Interval Timer 814 families of devices. It is not intended • 16-Bit Velocity Counter to be a comprehensive reference source. • 32-Bit Position Initialization/Capture/Compare To complement the information in this High Register data sheet, refer to Section 15. “Quadrature Encoder Interface (QEI)” • 32-Bit Position Compare Low Register (DS70601) of the “dsPIC33E/PIC24E • x4 Quadrature Count mode Family Reference Manual”, which is • External Up/Down Count mode available from the Microchip web site • External Gated Count mode (www.microchip.com). • External Gated Timer mode 2: Some registers and associated bits • Internal Timer mode described in this section may not be Figure17-1 illustrates the QEI block diagram. available on all devices. Refer to Section4.0 “Memory Organization” in Note: An ‘x’ used in the names of pins, control/ this data sheet for device-specific register status bits and registers denotes a and bit information. particular Quadrature Encoder Interface (QEI) module number (x = 1 or 2).  2009-2012 Microchip Technology Inc. DS70616G-page 321

D FIGURE 17-1: QEI BLOCK DIAGRAM d S s 70 P 61 FLTREN IC 6 GATEN G 3 -p 3 ag HOMEx FHOMEx DIR_GATE E e 322  QFDIV FP ECXOTUCNNTT 1 COUNT_EN PXX 0 X DIVCLK ( INDXx FINDXx G P Digital CCM / M Filter DIR C QEBx QDuaedcoradteurre COUNT DIR_G1A’TbE0 CNT_DIR /MU Logic DIR ) 8 CNTPOL 0 6 QEAx EXTCNT /8 1 0 DIR_GATE / 8 1 PCHGE 4 CNTCMPx PCLLE a PCLLE PCLEQ PCHEQ n PCHGE d 32-Bit Less Than 32-Bit Greater Than P OUTFNC or Equal Comparator or Equal Comparator I C PCLLE PCHGE 2 FP  INTDIV DIVCLK 4E 32-Bit Less Than or Equal 32-Bit Greater Than or Equal P COUNT_EN Com(QpaErIex LREeCg)ister 32-Bit Pos(iPtioOnS CxCouNnTte)r Register Co(mQpEaIxreG ERCeg)(i1s)ter XX (INDXxCNT) X  2 FINDXx 32-Bit Index Counter Register T3i2m-Berit RInetgeirsvtaelr COUNT_EN POSxCNTH POSxCNTL (G 009-2 CNT_DIR INDXxCNTH INDXxCNTL (INTxTMR) CNT_DIR COUNT_EN CNT_DIR P/G 0 U 1 2 M 16-Bit Index Counter 32-Bit Interval Timer 16-Bit Velocity 16-Bit Position Counter QCAPEN 32-Bit Initialization and )81 icroc H(IoNldD XRxeHgiLsDte)r H(oINldT RxeHgLiDst)er Co(uVnEteLrx RCeNgTis)ter H(oPlOd SRxeHgLisDte)r Cap(QtuEreIx RICe)g(1i)ster 0/8 hip 1 T 4 e c h n Data Bus o Data Bus lo g y In Note 1: These registers map to the same memory location. c .

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 17.1 QEI Resources 17.1.1 KEY RESOURCES Many useful resources related to QEI are provided on • Section 15. “Quadrature Encoder Interface the main product page of the Microchip web site for the (QEI)” (DS70601) in the “dsPIC33E/PIC24E devices listed in this data sheet. This product page, Family Reference Manual” which can be accessed using this link, contains the • Code Samples latest updates and additional information. • Application Notes • Software Libraries Note: In the event you are not able to access the product page using the link above, enter • Webinars this URL in your browser: • All related “dsPIC33E/PIC24E Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en554310 • Development Tools  2009-2012 Microchip Technology Inc. DS70616G-page 323

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 17.2 QEI Control Registers REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIEN — QEISIDL PIMOD<2:0>(1) IMV<1:0>(2) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — INTDIV<2:0>(3) CNTPOL GATEN CCM<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 QEIEN: Quadrature Encoder Interface Module Counter Enable bit 1 = Module counters are enabled 0 = Module counters are disabled, but SFRs can be read or written to bit 14 Unimplemented: Read as ‘0’ bit 13 QEISIDL: QEI Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 PIMOD<2:0>: Position Counter Initialization Mode Select bits(1) 111 = Reserved 110 = Modulo Count mode for position counter 101 = Resets the position counter when the position counter equals the QEIxGEC register 100 = Second index event after home event initializes position counter with contents of the QEIxIC register 011 = First index event after home event initializes position counter with contents of the QEIxIC register 010 = Next index input event initializes the position counter with contents of the QEIxIC register 001 = Every index input event resets the position counter 000 = Index input event does not affect position counter bit 9-8 IMV<1:0>: Index Match Value bits(2) 11 = Index match occurs when QEB = 1 and QEA = 1 10 = Index match occurs when QEB = 1 and QEA = 0 01 = Index match occurs when QEB = 0 and QEA = 1 00 = Index input event does not affect position counter bit 7 Unimplemented: Read as ‘0’ Note 1: When CCM = 10 or CCM = 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are ignored. 2: When CCM = 00, and QEA and QEB values match Index Match Value (IMV), the POSCNTH and POSCNTL registers are reset. 3: The selected clock rate should be at least twice the expected maximum quadrature count rate. DS70616G-page 324  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (CONTINUED) bit 6-4 INTDIV<2:0>: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter), velocity counter and index counter internal clock divider select)(3) 111 = 1:128 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3 CNTPOL: Position and Index Counter/Timer Direction Select bit 1 = Counter direction is negative unless modified by external up/down signal 0 = Counter direction is positive unless modified by external up/down signal bit 2 GATEN: External Count Gate Enable bit 1 = External gate signal controls position counter operation 0 = External gate signal does not affect position counter/timer operation bit 1-0 CCM<1:0>: Counter Control Mode Selection bits 11 = Internal Timer mode with optional external count is selected 10 = External clock count with optional external count is selected 01 = External clock count with external up/down direction is selected 00 = Quadrature Encoder Interface (x4 mode) Count mode is selected Note 1: When CCM = 10 or CCM = 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are ignored. 2: When CCM = 00, and QEA and QEB values match Index Match Value (IMV), the POSCNTH and POSCNTL registers are reset. 3: The selected clock rate should be at least twice the expected maximum quadrature count rate.  2009-2012 Microchip Technology Inc. DS70616G-page 325

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 17-2: QEIxIOC: QEIx I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R-x R-x R-x R-x HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 QCAPEN: Position Counter Input Capture Enable bit 1 = Positive edge detect of home input triggers position capture function 0 = HOMEx input event (positive edge) does not trigger a capture event bit 14 FLTREN: QEAx/QEBx/INDXx/HOMEx Digital Filter Enable bit 1 = Input pin digital filter is enabled 0 = Input pin digital filter is disabled (bypassed) bit 13-11 QFDIV<2:0>: QEAx/QEBx/INDXx/HOMEx Digital Input Filter Clock Divide Select bits 111 = 1:256 clock divide 110 = 1:64 clock divide 101 = 1:32 clock divide 100 = 1:16 clock divide 011 = 1:8 clock divide 010 = 1:4 clock divide 001 = 1:2 clock divide 000 = 1:1 clock divide bit 10-9 OUTFNC<1:0>: QEI Module Output Function Mode Select bits 11 = The CTNCMPx pin goes high when QEIxLEC  POSxCNT  QEIxGEC 10 = The CTNCMPx pin goes high when POSxCNT  QEIxLEC 01 = The CTNCMPx pin goes high when POSxCNT  QEIxGEC 00 = Output is disabled bit 8 SWPAB: Swap QEA and QEB Inputs bit 1 = QEAx and QEBx are swapped prior to quadrature decoder logic 0 = QEAx and QEBx are not swapped bit 7 HOMPOL: HOMEx Input Polarity Select bit 1 = Input is inverted 0 = Input is not inverted bit 6 IDXPOL: HOMEx Input Polarity Select bit 1 = Input is inverted 0 = Input is not inverted bit 5 QEBPOL: QEBx Input Polarity Select bit 1 = Input is inverted 0 = Input is not inverted bit 4 QEAPOL: QEAx Input Polarity Select bit 1 = Input is inverted 0 = Input is not inverted bit 3 HOME: Status of HOMEx Input Pin After Polarity Control bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ DS70616G-page 326  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 17-2: QEIxIOC: QEIx I/O CONTROL REGISTER (CONTINUED) bit 2 INDEX: Status of INDXx Input Pin After Polarity Control bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ bit 1 QEB: Status of QEBx Input Pin After Polarity Control And SWPAB Pin Swapping bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ bit 0 QEA: Status of QEAx Input Pin After Polarity Control And SWPAB Pin Swapping bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’  2009-2012 Microchip Technology Inc. DS70616G-page 327

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 17-3: QEIxSTAT: QEIx STATUS REGISTER U-0 U-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN bit 15 bit 8 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 PCIIRQ(1) PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN bit 7 bit 0 Legend: HS = Hardware Settable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 PCHEQIRQ: Position Counter Greater Than or Equal Compare Status bit 1 = POSxCNT ≥ QEIxGEC 0 = POSxCNT < QEIxGEC bit 12 PCHEQIEN: Position Counter Greater Than or Equal Compare Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 11 PCLEQIRQ: Position Counter Less Than or Equal Compare Status bit 1 = POSxCNT ≤ QEIxLEC 0 = POSxCNT > QEIxLEC bit 10 PCLEQIEN: Position Counter Less Than or Equal Compare Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 9 POSOVIRQ: Position Counter Overflow Status bit 1 = Overflow has occurred 0 = No overflow has occurred bit 8 POSOVIEN: Position Counter Overflow Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 7 PCIIRQ: Position Counter (Homing) Initialization Process Complete Status bit(1) 1 = POSxCNT was reinitialized 0 = POSxCNT was not reinitialized bit 6 PCIIEN: Position Counter (Homing) Initialization Process Complete interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 VELOVIRQ: Velocity Counter Overflow Status bit 1 = Overflow has occurred 0 = No overflow has not occurred bit 4 VELOVIEN: Velocity Counter Overflow Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 HOMIRQ: Status Flag for Home Event Status bit 1 = Home event has occurred 0 = No Home event has occurred Note 1: This status bit is only applicable to PIMOD<2:0> modes ‘011’ and ‘100’. DS70616G-page 328  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 17-3: QEIxSTAT: QEIx STATUS REGISTER (CONTINUED) bit 2 HOMIEN: Home Input Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 IDXIRQ: Status Flag for Index Event Status bit 1 = Index event has occurred 0 = No Index event has occurred bit 0 IDXIEN: Index Input Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This status bit is only applicable to PIMOD<2:0> modes ‘011’ and ‘100’.  2009-2012 Microchip Technology Inc. DS70616G-page 329

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 17-4: POSxCNTH: POSITION COUNTER x HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 POSCNT<31:16>: High Word Used to Form 32-Bit Position Counter Register (POSxCNT) bits REGISTER 17-5: POSxCNTL: POSITION COUNTER x LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 POSCNT<15:0>: Low Word Used to Form 32-Bit Position Counter Register (POSxCNT) bits REGISTER 17-6: POSxHLD: POSITION COUNTER x HOLD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSHLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSHLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 POSHLD<15:0>: Hold Register for Reading and Writing POSxCNTH bits DS70616G-page 330  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 17-7: VELxCNT: VELOCITY COUNTER x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VELCNT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VELCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 VELCNT<15:0>: Velocity Counter bits REGISTER 17-8: INDXxCNTH: INDEX COUNTER x HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INDXCNT<31:16>: High Word Used to Form 32-Bit Index Counter Register (INDXxCNT) bits REGISTER 17-9: INDXxCNTL: INDEX COUNTER x LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INDXCNT<15:0>: Low Word Used to Form 32-Bit Index Counter Register (INDXxCNT) bits  2009-2012 Microchip Technology Inc. DS70616G-page 331

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 17-10: INDXxHLD: INDEX COUNTER x HOLD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXHLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXHLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INDXHLD<15:0>: Hold Register for Reading and Writing INDXxCNTH bits REGISTER 17-11: QEIxICH: QEIx INITIALIZATION/CAPTURE HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIIC<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIIC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIIC<31:16>: QEIx High Word Used to Form 32-Bit Initialization/Capture Register (QEIxIC) bits REGISTER 17-12: QEIxICL: QEIx INITIALIZATION/CAPTURE LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIIC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIIC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIIC<15:0>: QEIx Low Word Used to Form 32-Bit Initialization/Capture Register (QEIxIC) bits DS70616G-page 332  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 17-13: QEIxLECH: QEIx LESS THAN OR EQUAL COMPARE HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEILEC<31:16>: QEIx High Word Used to Form 32-Bit Less Than or Equal Compare Register (QEIxLEC) bits REGISTER 17-14: QEIxLECL: QEIx LESS THAN OR EQUAL COMPARE LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEILEC<15:0>: QEIx Low Word Used to Form 32-Bit Less Than or Equal Compare Register (QEIxLEC) bits  2009-2012 Microchip Technology Inc. DS70616G-page 333

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R E GISTER 17-15: QEIxGECH: QEIx GREATER THAN OR EQUAL COMPARE HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIGEC<31:16>: QEIx High Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEIxGEC) bits REGISTER 17-16: QEIxGECL: QEIx GREATER THAN OR EQUAL COMPARE LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIGEC<15:0>: QEIx Low Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEIxGEC) bits REGISTER 17-17: INTxTMRH: INTERVAL TIMER x HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTTMR<31:16>: High Word Used to Form 32-Bit Interval Timer Register (INTxTMR) bits DS70616G-page 334  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 17-18: INTxTMRL: INTERVAL TIMER x LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTTMR<15:0>: Low Word Used to Form 32-Bit Interval Timer Register (INTxTMR) bits REGISTER 17-19: INTxHLDH: INTERVAL TIMER x HOLD HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTHLD<31:16>: Hold Register for Reading and Writing INTxTMRH bits REGISTER 17-20: INTxHLDL: INTERVAL TIMER x HOLD LOW WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTHLD<15:0>: Hold Register for Reading and Writing INTxTMRL bits  2009-2012 Microchip Technology Inc. DS70616G-page 335

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 336  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 18.0 SERIAL PERIPHERAL Four SPI modules are provided on a single device. INTERFACE (SPI) These modules, which are designated as SPI1, SPI2, SPI3 and SPI4, are functionally identical with the excep- Note1: This data sheet summarizes the features tion that SPI2 is not remappable. The dedicated SDI2, of the dsPIC33EPXXX(GP/MC/MU)806/ SDO2 and SCK2 connections provide improved perfor- 810/814 and PIC24EPXXX(GP/GU)810/ mance over SPI1, SPI3 and SPI4 (see Section32.0 814 families of devices. It is not intended “Electrical Characteristics”). Each SPI module to be a comprehensive reference source. includes an eight-word FIFO buffer and allows DMA bus To complement the information in this connections. When using the SPI module with DMA, data sheet, refer to Section 18. “Serial FIFO operation can be disabled. Peripheral Interface (SPI)” (DS70569) Note: In this section, the SPI modules are of the “dsPIC33E/PIC24E Family referred to together as SPIx, or separately Reference Manual”, which is available as SPI1, SPI2, SPI3 and SPI4. Special from the Microchip web site Function Registers follow a similar nota- (www.microchip.com). tion. For example, SPIxCON refers to the control register for the SPI1, SPI2, SPI3 2: Some registers and associated bits or SPI4 module. described in this section may not be available on all devices. Refer to The SPIx serial interface consists of four pins, as Section4.0 “Memory Organization” in follows: this data sheet for device-specific register • SDIx: Serial Data Input and bit information. • SDOx: Serial Data Output The SPI module is a synchronous serial interface use- • SCKx: Shift Clock Input or Output ful for communicating with other peripheral or micro- • SSx/FSYNCx: Active-Low Slave Select or Frame controller devices. These peripheral devices can be Synchronization I/O Pulse serial EEPROMs, shift registers, display drivers, ADC The SPIx module can be configured to operate with Converters, etc. The SPI module is compatible with the two, three or four pins. In 3-pin mode, SSx is not used. Motorola® SPI and SIOP interfaces. In 2-pin mode, neither SDOx nor SSx is used. Figure18-1 illustrates the block diagram of the SPI module in Standard and Enhanced modes. FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 1:1/4/16/64 FP Secondary Primary Prescaler Prescaler SSx/FSYNCx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SDOx SPIxCON1<4:2> Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer 8-Level FIFO 8-Level FIFO Receive Buffer(1) Transmit Buffer(1) SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus Note 1: In Standard mode, the FIFO is only one level deep.  2009-2012 Microchip Technology Inc. DS70616G-page 337

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 18.1 SPI Helpful Tips 18.2 SPI Resources 1. In Frame mode, if there is a possibility that the Many useful resources related to SPI are provided on master may not be initialized before the slave: the main product page of the Microchip web site for the a) If FRMPOL (SPIxCON2<13>) = 1, use a devices listed in this data sheet. This product page, pull-down resistor on SSx. which can be accessed using this link, contains the latest updates and additional information. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: In the event you are not able to access the Note: This insures that the first frame product page using the link above, enter transmission after initialization is not this URL in your browser: shifted or corrupted. http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en554301 2. In Non-Framed 3-Wire mode, (i.e., not using SSx from a master): 18.2.1 KEY RESOURCES a) If CKP (SPIxCON1<6>) = 1, always place a • Section 18. “Serial Peripheral Interface (SPI)” pull-up resistor on SSx. (DS70569) in the “dsPIC33E/PIC24E Family b) If CKP = 0, always place a pull-down Reference Manual” resistor on SSx. • Code Samples Note: This will insure that during power-up and • Application Notes initialization, the master/slave will not lose • Software Libraries synchronization due to an errant SCKx • Webinars transition that would cause the slave to • All related “dsPIC33E/PIC24E Family Reference accumulate data shift errors, for both Manual” Sections transmit and receive, appearing as corrupted data. • Development Tools 3. FRMEN (SPIxCON2<15>) = 1 and SSEN (SPIxCON1<7>) = 1 are exclusive and invalid. In Frame mode, SCKx is continuous and the Frame Sync pulse is active on the SSx pin, which indicates the start of a data frame. Note: Not all third-party devices support Frame mode timing. Refer to the SPIx electrical characteristics for details. 4. In Master mode only, set the SMP bit (SPIxCON1<9>) to a ‘1’ for the fastest SPI data rate possible. The SMP bit can only be set at the same time or after the MSTEN bit (SPIxCON1<5>) is set. To avoid invalid slave read data to the master, the user’s master software must ensure enough time for slave software to fill its write buffer before the user application initiates a master write/read cycle. It is always advisable to preload the SPIxBUF Transmit register in advance of the next master transaction cycle. SPIxBUF is transferred to the SPIx Shift register and is empty once the data transmission begins. DS70616G-page 338  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 18.3 SPI Control Registers REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 SPIEN — SPISIDL — — SPIBEC<2:0> bit 15 bit 8 R/W-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R-0, HS, HC SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ bit 15 SPIEN: SPIx Enable bit 1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables the module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Discontinues the module operation when device enters Idle mode 0 = Continues the module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPIx transfers that are pending. Slave mode: Number of SPIx transfers that are unread. bit 7 SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and Ready-to-Send or receive the data 0 = SPIx Shift register is not empty bit 6 SPIROV: SPIx Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded; the user application has not read the previous data in the SPIxBUF register 0 = No overflow has occurred bit 5 SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = RX FIFO is empty 0 = RX FIFO is not empty bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when the SPIx transmit buffer is full 110 = Interrupt when last bit is shifted into SPIxSR, and as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR, and as a result, the TX FIFO has one open memory location 011 = Interrupt when the SPIx receive buffer is full 010 = Interrupt when the SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in the receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty (SRXMPT bit is set)  2009-2012 Microchip Technology Inc. DS70616G-page 339

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIx transmit buffer is full 0 = Transmit has started, SPIx transmit buffer is empty Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIxBUF location, loading the SPIx transmit buffer. Automatically cleared in hardware when the SPIx module transfers data from the SPIx transmit buffer to SPIxSR. Enhanced Buffer Mode: Automatically set in hardware when CPU writes to the SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write operation. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIx receive buffer is full 0 = Receive is incomplete, SPIx receive buffer is empty Standard Buffer Mode: Automatically set in hardware when SPIx transfers data from SPIxSR to the SPIx receive buffer. Automatically cleared in hardware when the core reads the SPIxBUF location, reading the SPIx receive buffer. Enhanced Buffer Mode: Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. DS70616G-page 340  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP(4) CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN SPRE<2:0>(3) PPRE<1:0>(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx Pin bit (SPIx Master modes only) 1 = Internal SPIx clock is disabled, pin functions as I/O 0 = Internal SPIx clock is enabled bit 11 DISSDO: Disable SDOx Pin bit 1 = SDOx pin is not used by the module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit(4) Master mode: 1 = Input data is sampled at end of data output time 0 = Input data is sampled at middle of data output time Slave mode: The SMP bit must be cleared when SPIx module is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(2) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by module, pin is controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPIx modes. Program this bit to ‘0’ for Framed SPIx modes (FRMEN=1). 2: This bit must be cleared when FRMEN = 1. 3: Do not set both primary and secondary prescalers to a value of 1:1. 4: The SMP bit must be set only after setting the MSTEN bit. The SMP bit remains cleared if MSTEN = 0.  2009-2012 Microchip Technology Inc. DS70616G-page 341

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPIx modes. Program this bit to ‘0’ for Framed SPIx modes (FRMEN=1). 2: This bit must be cleared when FRMEN = 1. 3: Do not set both primary and secondary prescalers to a value of 1:1. 4: The SMP bit must be set only after setting the MSTEN bit. The SMP bit remains cleared if MSTEN = 0. DS70616G-page 342  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 18-3: SPIXCON2: SPIX CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — FRMDLY SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled (SSx pin is used as a Frame Sync pulse input/output) 0 = Framed SPIx support is disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame Sync pulse input (slave) 0 = Frame Sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame Sync pulse is active-high 0 = Frame Sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame Sync pulse coincides with the first bit clock 0 = Frame Sync pulse precedes the first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer is enabled 0 = Enhanced Buffer is disabled (Standard mode)  2009-2012 Microchip Technology Inc. DS70616G-page 343

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 344  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 19.0 INTER-INTEGRATED The I2C module provides complete hardware support CIRCUIT™ (I2C™) for both Slave and Multi-Master modes of the I2C serial communication standard, with a 16-bit interface. Note1: This data sheet summarizes the features The I2C module has a 2-pin interface: of the dsPIC33EPXXX(GP/MC/MU)806/ • The SCLx pin is the clock. 810/814 and PIC24EPXXX(GP/GU)810/ • The SDAx pin is the data. 814 families of devices. It is not intended to be a comprehensive reference source. The I2C module offers the following key features: To complement the information in this • I2C interface supporting both Master and Slave data sheet, refer to Section 19. “Inter- modes of operation. Integrated Circuit™ (I2C™)” • I2C Slave mode supports 7 and 10-bit addressing. (DS70330) of the “dsPIC33E/PIC24E • I2C Master mode supports 7 and 10-bit addressing. Family Reference Manual”, which is available from the Microchip web site • I2C port allows bidirectional transfers between master and slaves. (www.microchip.com). • Serial clock synchronization for I2C port can be 2: Some registers and associated bits used as a handshake mechanism to suspend and described in this section may not be resume serial transfer (SCLREL control). available on all devices. Refer to Section4.0 “Memory Organization” in • I2C supports multi-master operation, detects bus collision and arbitrates accordingly. this data sheet for device-specific register and bit information. • IPMI support • SMBus support The dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 family of devices con- tain two Inter-Integrated Circuit (I2C) modules: I2C1 and I2C2.  2009-2012 Microchip Technology Inc. DS70616G-page 345

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 19-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Read Shift SCLx/ Clock ASDLx(1) I2CxRSR LSb SDAx/ Address Match ASDAx(1) Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoelltiseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read ShiftClock Reload Control Write BRG Down Counter I2CxBRG Read FP Note 1: The availability of I2C interfaces varies by device. Refer to the “Pin Diagrams” section for availability. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section29.0 “Special Features” for more information. DS70616G-page 346  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 19.1 I2C Resources 19.1.1 KEY RESOURCES Many useful resources related to I2C are provided on • Section 19. “Inter-Integrated Circuit™ (I2C™)” the main product page of the Microchip web site for the (DS70330) in the “dsPIC33E/PIC24E Family devices listed in this data sheet. This product page, Reference Manual” which can be accessed using this link, contains the • Code Samples latest updates and additional information. • Application Notes • Software Libraries Note: In the event you are not able to access the product page using the link above, enter • Webinars this URL in your browser: • All related “dsPIC33E/PIC24E Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en554310 • Development Tools  2009-2012 Microchip Technology Inc. DS70616G-page 347

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 19.2 I2C Control Registers REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN(1) A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: The bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear at beginning of every slave data byte transmission. Hardware is clear at the end of every slave address byte reception. Hardware is clear at end of every slave data byte reception. If STREN = 0: The bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at beginning of every slave data byte transmission. Hardware is clear at the end of every slave address byte reception. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit(1) 1 = IPMI mode is enabled; all addresses Acknowledged 0 = IPMI mode is disabled bit 10 A10M: 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with the SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled Note 1: When performing master operations, ensure that the IPMIEN bit is ‘0’. DS70616G-page 348  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receives clock stretching 0 = Disables software or receives clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit. Hardware is clear at the end of a master Acknowledge sequence. 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of a master receive data byte. 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of a master Stop sequence. 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of a master Repeated Start sequence. 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of a master Start sequence. 0 = Start condition is not in progress Note 1: When performing master operations, ensure that the IPMIEN bit is ‘0’.  2009-2012 Microchip Technology Inc. DS70616G-page 349

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware is set or clear at the end of a slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at the beginning of a master transmission. Hardware is clear at the end of a slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware is set at detection of a bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when an address matches the general call address. Hardware is clear at a Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at a match of the 2nd byte of a matched 10-bit address. Hardware is clear at a Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at an occurrence of a write to I2CxTRN while busy (cleared by software). bit 6 I2COV: I2Cx Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at a device address match. Hardware is set by reception of a slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected. DS70616G-page 350  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from a slave 0 = Write – indicates data transfer is input to a slave Hardware is set or clear after reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of a data transmission.  2009-2012 Microchip Technology Inc. DS70616G-page 351

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address bit x Select bit For 10-Bit Address: 1 = Enables masking for bit Ax of incoming message address; bit match is not required in this position 0 = Disables masking for bit Ax; bit match is required in this position For 7-Bit Address (I2CxMSK<6:0> only): 1 = Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position 0 = Disable masking for bit Ax + 1; bit match is required in this position DS70616G-page 352  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 20.0 UNIVERSAL ASYNCHRONOUS The primary features of the UARTx module are: RECEIVER TRANSMITTER • Full-Duplex, 8 or 9-Bit Data Transmission through (UART) the UxTX and UxRX Pins • Even, Odd or No Parity Options (for 8-bit data) Note1: This data sheet summarizes the features • One or Two Stop bits of the dsPIC33EPXXX(GP/MC/MU)806/ • Hardware Flow Control Option with UxCTS and 810/814 and PIC24EPXXX(GP/GU)810/ UxRTS Pins 814 families of devices. It is not intended • Fully Integrated Baud Rate Generator with 16-Bit to be a comprehensive reference source. Prescaler To complement the information in this data sheet, refer to Section 17. “UART” • Baud Rates Ranging from 4.375 Mbps to 67 bps at (DS70582) of the “dsPIC33E/PIC24E 16x mode at 70 MIPS Family Reference Manual”, which is • Baud Rates Ranging from 17.5 Mbps to 267 bps at available from the Microchip web site 4x mode at 70 MIPS (www.microchip.com). • 4-Deep First-In First-Out (FIFO) Transmit Data Buffer 2: Some registers and associated bits described in this section may not be • 4-Deep FIFO Receive Data Buffer available on all devices. Refer to • Parity, Framing and Buffer Overrun Error Detection Section4.0 “Memory Organization” in • Support for 9-bit mode with Address Detect this data sheet for device-specific register (9th bit = 1) and bit information. • Transmit and Receive Interrupts The dsPIC33EPXXX(GP/MC/MU)806/810/814 and • A Separate Interrupt for All UARTx Error Conditions PIC24EPXXX(GP/GU)810/814 family of devices • Loopback mode for Diagnostic Support contains four UART modules. • Support for Sync and Break Characters The Universal Asynchronous Receiver Transmitter • Support for Automatic Baud Rate Detection (UART) module is one of the serial I/O modules • IrDA® Encoder and Decoder Logic available in the dsPIC33EPXXX(GP/MC/MU)806/810/ • 16x Baud Clock Output for IrDA Support 814 and PIC24EPXXX(GP/GU)810/814 device family. The UART is a full-duplex, asynchronous system that A simplified block diagram of the UARTx module is can communicate with peripheral devices, such as shown in Figure20-1. The UARTx module consists of personal computers, LIN/J2602, RS-232 and RS-485 these key hardware elements: interfaces. The module also supports a hardware flow • Baud Rate Generator control option with the UxCTS and UxRTS pins, and • Asynchronous Transmitter also includes an IrDA® encoder and decoder. • Asynchronous Receiver FIGURE 20-1: UARTx SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2009-2012 Microchip Technology Inc. DS70616G-page 353

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 20.1 UARTx Helpful Tips 20.2 UARTx Resources 1. In multi-node direct-connect UARTx networks, Many useful resources related to the UARTx are UARTx receive inputs react to the complemen- provided on the main product page of the Microchip tary logic level defined by the URXINV bit web site for the devices listed in this data sheet. This (UxMODE<4>), which defines the Idle state, the product page, which can be accessed using this link, default of which is logic high (i.e., URXINV = 0). contains the latest updates and additional information. Because remote devices do not initialize at the Note: In the event you are not able to access the same time, it is likely that one of the devices, product page using the link above, enter because the RX line is floating, will trigger a this URL in your browser: Start bit detection and will cause the first byte http://www.microchip.com/wwwproducts/ received, after the device has been initialized, to Devices.aspx?dDocName=en554310 be invalid. To avoid this situation, the user should use a pull-up or pull-down resistor on the 20.2.1 KEY RESOURCES RX pin depending on the value of the URXINV bit. • Section 17. “UART” (DS70582) in the a) If URXINV = 0, use a pull-up resistor on the “dsPIC33E/PIC24E Family Reference Manual” RX pin. • Code Samples b) If URXINV = 1, use a pull-down resistor on • Application Notes the RX pin. • Software Libraries 2. The first character received on a wake-up from • Webinars Sleep mode, caused by activity on the UxRX pin • All related “dsPIC33E/PIC24E Family Reference of the UARTx module, will be invalid. In Sleep Manual” Sections mode, peripheral clocks are disabled. By the • Development Tools time the oscillator system has restarted and stabilized from Sleep mode, the baud rate bit sampling clock, relative to the incoming UxRX bit timing, is no longer synchronized resulting in the first character being invalid. This is to be expected. DS70616G-page 354  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 20.3 UARTx Registers REGISTER 20-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN<1:0> bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Pin Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins are controlled by port latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx continues to sample the UxRX pin; interrupt is generated on falling edge; bit is cleared in hardware on following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement is disabled or has completed Note 1: Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for information on enabling the UARTx module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0).  2009-2012 Microchip Technology Inc. DS70616G-page 355

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for information on enabling the UARTx module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS70616G-page 356  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: UARTx Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA encoded, UxTX Idle state is ‘1’ 0 = IrDA encoded, UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: UARTx Transmit Enable bit(1) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin controlled by port bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer; receive buffer has one or more characters Note 1: Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for information on enabling the UARTx module for transmit operation.  2009-2012 Microchip Technology Inc. DS70616G-page 357

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (read/clear only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed; clearing a previously set OERR bit (10 transition) resets the receiver buffer and the UxRSR to the empty state bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for information on enabling the UARTx module for transmit operation. DS70616G-page 358  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 21.0 ENHANCED CAN (ECAN™) The ECANx module features are as follows: MODULE • Implementation of the CAN Protocol, CAN1.2, CAN2.0A and CAN2.0B Note1: This data sheet summarizes the features • Standard and Extended Data Frames of the dsPIC33EPXXX(GP/MC/MU)806/ • 0-8 Bytes Data Length 810/814 and PIC24EPXXX(GP/GU)810/ • Programmable Bit Rate up to 1 Mbit/sec 814 families of devices. It is not intended to be a comprehensive reference source. • Automatic Response to Remote Transmission To complement the information in this Requests data sheet, refer to Section 21. • Up to 8 Transmit Buffers with Application-Specific “Enhanced Controller Area Network Prioritization and Abort Capability (each buffer (ECAN™)” (DS70353) of the “dsPIC33E/ can contain up to 8 bytes of data) PIC24E Family Reference Manual”, • Up to 32 Receive Buffers (each buffer can contain which is available from the Microchip web up to 8 bytes of data) site (www.microchip.com). • Up to 16 Full (standard/extended identifier) 2: Some registers and associated bits Acceptance Filters described in this section may not be • Three Full Acceptance Filter Masks available on all devices. Refer to • DeviceNet™ Addressing Support Section4.0 “Memory Organization” in • Programmable Wake-up Functionality with this data sheet for device-specific register Integrated Low-Pass Filter and bit information. • Programmable Loopback mode Supports Self-Test Operation 21.1 Overview • Signaling via Interrupt Capabilities for all CAN The Enhanced Controller Area Network (ECAN) Receiver and Transmitter Error States module is a serial interface, useful for communicat- • Programmable Clock Source ing with other CAN modules or microcontroller • Programmable Link to Input Capture Module (IC2 devices. This interface/protocol was designed to for the ECAN1 and ECAN2 modules) for allow communications within noisy environments. Time-Stamping and Network Synchronization The dsPIC33EPXXX(GP/MC/MU)806/810/814 and • Low-Power Sleep and Idle mode PIC24EPXXX(GP/GU)810/814 devices contain two ECAN modules. The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine The ECANx module is a communication controller handles all functions for receiving and transmitting implementing the CAN 2.0 A/B protocol, as defined in messages on the CAN bus. Messages are transmitted the BOSCH CAN Specification. The module supports by first loading the appropriate data registers. Status CAN1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B and errors can be checked by reading the appropriate Active versions of the protocol. The module implemen- registers. Any message detected on the CAN bus is tation is a full CAN system. The CAN Specification is checked for errors and then matched against filters to not covered within this data sheet. The reader can refer see if it should be received and stored in one of the to the BOSCH CAN specification for further details. receive registers.  2009-2012 Microchip Technology Inc. DS70616G-page 359

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 21-1: ECANx MODULE BLOCK DIAGRAM RxF15 Filter RxF14 Filter RxF13 Filter RxF12 Filter RxF11 Filter DMA Controller RxF10 Filter RxF9 Filter RxF8 Filter TRB7 TX/RX Buffer Control Register RxF7 Filter TRB6 TX/RX Buffer Control Register RxF6 Filter TRB5 TX/RX Buffer Control Register RxF5 Filter TRB4 TX/RX Buffer Control Register RxF4 Filter TRB3 TX/RX Buffer Control Register RxF3 Filter TRB2 TX/RX Buffer Control Register RxF2 Filter RxM2 Mask TRB1 TX/RX Buffer Control Register RxF1 Filter RxM1 Mask TRB0 TX/RX Buffer Control Register RxF0 Filter RxM0 Mask Transmit Byte Message Assembly Sequencer Buffer Control CPU Configuration Bus Logic CAN Protocol Engine Interrupts CxTX CxRX Note: x = 1 or 2. DS70616G-page 360  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 21.2 Modes of Operation 21.3 ECAN Resources The ECANx module can operate in one of several Many useful resources related to ECAN are provided operation modes selected by the user. These modes on the main product page of the Microchip web site for include: the devices listed in this data sheet. This product page, • Initialization mode which can be accessed using this link, contains the latest updates and additional information. • Disable mode • Normal Operation mode Note: In the event you are not able to access the • Listen Only mode product page using the link above, enter • Listen All Messages mode this URL in your browser: http://www.microchip.com/wwwproducts/ • Loopback mode Devices.aspx?dDocName=en554310 Modes are requested by setting the REQOP<2:0> bits (CxCTRL1<10:8>). Entry into a mode is Acknowledged 21.3.1 KEY RESOURCES by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>). The module does not change the mode and the • Section 21. “Enhanced Controller Area OPMODE bits until a change in mode is acceptable, Network (ECAN™)” (DS70353) in the “dsPIC33E/PIC24E Family Reference Manual” generally during bus Idle time, which is defined as at least 11 consecutive recessive bits. • Code Samples • Application Notes • Software Libraries • Webinars • All related “dsPIC33E/PIC24E Family Reference Manual” Sections • Development Tools  2009-2012 Microchip Technology Inc. DS70616G-page 361

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 21.4 ECANx Control Registers REGISTER 21-1: CxCTRL1: ECANx CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — — CSIDL ABAT CANCKS REQOP<2:0> bit 15 bit 8 R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0 OPMODE<2:0> — CANCAP — — WIN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: ECANx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 ABAT: Abort All Pending Transmissions bit 1 = Signals all transmit buffers to abort transmission 0 = Module will clear this bit when all transmissions are aborted bit 11 CANCKS: ECANx Module Clock (FCAN) Source Select bit 1 = FCAN is equal to twice FP 0 = FCAN is equal to FP bit 10-8 REQOP<2:0>: Request Operation Mode bits 111 = Set Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Set Configuration mode 011 = Set Listen Only Mode 010 = Set Loopback mode 001 = Set Disable mode 000 = Set Normal Operation mode bit 7-5 OPMODE<2:0>: Operation Mode bits 111 = Module is in Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Module is in Configuration mode 011 = Module is in Listen Only mode 010 = Module is in Loopback mode 001 = Module is in Disable mode 000 = Module is in Normal Operation mode bit 4 Unimplemented: Read as ‘0’ bit 3 CANCAP: CAN Message Receive Timer Capture Event Enable bit 1 = Enables input capture based on CAN message receive 0 = Disables CAN capture bit 2-1 Unimplemented: Read as ‘0’ bit 0 WIN: SFR Map Window Select bit 1 = Uses filter window 0 = Uses buffer window DS70616G-page 362  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-2: CxCTRL2: ECANx CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — DNCNT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compares up to Data Byte 3, bit 6 with EID<17> • • • 00001 = Compares up to Data Byte 1, bit 7 with EID<0> 00000 = Does not compare data bytes  2009-2012 Microchip Technology Inc. DS70616G-page 363

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-3: CxVEC: ECANx INTERRUPT CODE REGISTER U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — FILHIT<4:0> bit 15 bit 8 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 — ICODE<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 • • • 00001 = Filter 1 00000 = Filter 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 ICODE<6:0>: Interrupt Flag Code bits 1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt • • • 0010000-0111111 = Reserved 0001111 = RB15 buffer interrupt • • • 0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70616G-page 364  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-4: CxFCTRL: ECANx FIFO CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 DMABS<2:0> — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FSA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM 011 = 12 buffers in DMA RAM 010 = 8 buffers in DMA RAM 001 = 6 buffers in DMA RAM 000 = 4 buffers in DMA RAM bit 12-5 Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = Read Buffer RB31 11110 = Read Buffer RB30 • • • 00001 = TX/RX Buffer TRB1 00000 = TX/RX Buffer TRB0  2009-2012 Microchip Technology Inc. DS70616G-page 365

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-5: CxFIFO: ECANx FIFO STATUS REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FBP<5:0> bit 15 bit 8 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FNRB<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer DS70616G-page 366  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWAR RXWAR EWARN bit 15 bit 8 R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXBO: Transmitter in Error State Bus Off bit 1 = Transmitter is in Bus Off state 0 = Transmitter is not in Bus Off state bit 12 TXBP: Transmitter in Error State Bus Passive bit 1 = Transmitter is in Bus Passive state 0 = Transmitter is not in Bus Passive state bit 11 RXBP: Receiver in Error State Bus Passive bit 1 = Receiver is in Bus Passive state 0 = Receiver is not in Bus Passive state bit 10 TXWAR: Transmitter in Error State Warning bit 1 = Transmitter is in Error Warning state 0 = Transmitter is not in Error Warning state bit 9 RXWAR: Receiver in Error State Warning bit 1 = Receiver is in Error Warning state 0 = Receiver is not in Error Warning state bit 8 EWARN: Transmitter or Receiver in Error State Warning bit 1 = Transmitter or Receiver is in Error State Warning state 0 = Transmitter or Receiver is not in Error State Warning state bit 7 IVRIF: Invalid Message Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF<13:8> register) 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 1 RBIF: RX Buffer Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 0 TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred  2009-2012 Microchip Technology Inc. DS70616G-page 367

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-7: CxINTE: ECANx INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Invalid Message Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 WAKIE: Bus Wake-up Activity Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 ERRIE: Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 RBIE: RX Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 TBIE: TX Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS70616G-page 368  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-8: CxEC: ECANx TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits REGISTER 21-9: CxCFG1: ECANx BAUD RATE CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW<1:0> BRP<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 11 1111 = TQ = 2 x 64 x 1/FCAN • • • 00 0010 = TQ = 2 x 3 x 1/FCAN 00 0001 = TQ = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN  2009-2012 Microchip Technology Inc. DS70616G-page 369

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-10: CxCFG2: ECANx BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x — WAKFIL — — — SEG2PH<2:0> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 WAKFIL: Select CAN Bus Line Filter for Wake-up bit 1 = Uses CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 13-11 Unimplemented: Read as ‘0’ bit 10-8 SEG2PH<2:0>: Phase Segment 2 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN Bus Line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 2-0 PRSEG<2:0>: Propagation Time Segment bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ DS70616G-page 370  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-11: CxFEN1: ECANx ACCEPTANCE FILTER ENABLE REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FLTENn: Enable Filter n to Accept Messages bits 1 = Enables Filter n 0 = Disables Filter n REGISTER 21-12: CxBUFPNT1: ECANx FILTER 0-3 BUFFER POINTER REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3BP<3:0> F2BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F1BP<3:0> F0BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F3BP<3:0>: RX Buffer Mask for Filter 3 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bit 15-12) bit 7-4 F1BP<3:0>: RX Buffer Mask for Filter 1 bits (same values as bit 15-12) bit 3-0 F0BP<3:0>: RX Buffer Mask for Filter 0 bits (same values as bit 15-12)  2009-2012 Microchip Technology Inc. DS70616G-page 371

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-13: CxBUFPNT2: ECANx FILTER 4-7 BUFFER POINTER REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP<3:0> F6BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP<3:0> F4BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F7BP<3:0>: RX Buffer Mask for Filter 7 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F6BP<3:0>: RX Buffer Mask for Filter 6 bits (same values as bit 15-12) bit 7-4 F5BP<3:0>: RX Buffer Mask for Filter 5 bits (same values as bit 15-12) bit 3-0 F4BP<3:0>: RX Buffer Mask for Filter 4 bits (same values as bit 15-12) REGISTER 21-14: CxBUFPNT3: ECANx FILTER 8-11 BUFFER POINTER REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11BP<3:0> F10BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F9BP<3:0> F8BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F11BP<3:0>: RX Buffer Mask for Filter 11 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F10BP<3:0>: RX Buffer Mask for Filter 10 bits (same values as bit 15-12) bit 7-4 F9BP<3:0>: RX Buffer Mask for Filter 9 bits (same values as bit 15-12) bit 3-0 F8BP<3:0>: RX Buffer Mask for Filter 8 bits (same values as bit 15-12) DS70616G-page 372  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-15: CxBUFPNT4: ECANx FILTER 12-15 BUFFER POINTER REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP<3:0> F14BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP<3:0> F12BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F15BP<3:0>: RX Buffer Mask for Filter 15 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F14BP<3:0>: RX Buffer Mask for Filter 14 bits (same values as bit 15-12) bit 7-4 F13BP<3:0>: RX Buffer Mask for Filter 13 bits (same values as bit 15-12) bit 3-0 F12BP<3:0>: RX Buffer Mask for Filter 12 bits (same values as bit 15-12)  2009-2012 Microchip Technology Inc. DS70616G-page 373

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-16: CxRXFnSID: ECANx ACCEPTANCE FILTER n STANDARD IDENTIFIER REGISTER n (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Message address bit, SIDx, must be ‘1’ to match filter 0 = Message address bit, SIDx, must be ‘0’ to match filter bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit If MIDE = 1: 1 = Matches only messages with extended identifier addresses 0 = Matches only messages with standard identifier addresses If MIDE = 0: Ignores EXIDE bit. bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Message address bit, EIDx, must be ‘1’ to match filter 0 = Message address bit, EIDx, must be ‘0’ to match filter DS70616G-page 374  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-17: CxRXFnEID: ECANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTER n (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Message address bit, EIDx, must be ‘1’ to match filter 0 = Message address bit, EIDx, must be ‘0’ to match filter REGISTER 21-18: CxFMSKSEL1: ECANx FILTER 7-0 MASK SELECTION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bit 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bit (same values as bit 15-14) bit 11-10 F5MSK<1:0>: Mask Source for Filter 5 bit (same values as bit 15-14) bit 9-8 F4MSK<1:0>: Mask Source for Filter 4 bit (same values as bit 15-14) bit 7-6 F3MSK<1:0>: Mask Source for Filter 3 bit (same values as bit 15-14) bit 5-4 F2MSK<1:0>: Mask Source for Filter 2 bit (same values as bit 15-14) bit 3-2 F1MSK<1:0>: Mask Source for Filter 1 bit (same values as bit 15-14) bit 1-0 F0MSK<1:0>: Mask Source for Filter 0 bit (same values as bit 15-14)  2009-2012 Microchip Technology Inc. DS70616G-page 375

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-19: CxFMSKSEL2: ECANx FILTER 15-8 MASK SELECTION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bit 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bit 15-14) bit 11-10 F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bit 15-14) bit 9-8 F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bit 15-14) bit 7-6 F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bit 15-14) bit 5-4 F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14) bit 3-2 F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14) bit 1-0 F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14) DS70616G-page 376  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-20: CxRXMnSID: ECANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER REGISTER n (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Includes bit, SIDx, in filter comparison 0 = Bit, SIDx, is a don’t care in filter comparison bit 4 Unimplemented: Read as ‘0’ bit 3 MIDE: Identifier Receive Mode bit 1 = Matches only message types (standard or extended address) that correspond to EXIDE bit in filter 0 = Matches either standard or extended address message if filters match (i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)) bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Includes bit, EIDx, in filter comparison 0 = Bit, EIDx, is a don’t care in filter comparison REGISTER 21-21: CxRXMnEID: ECANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER REGISTER n (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Includes bit, EIDx, in filter comparison 0 = Bit, EIDx, is a don’t care in filter comparison  2009-2012 Microchip Technology Inc. DS70616G-page 377

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-22: CxRXFUL1: ECANx RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (cleared by user software) REGISTER 21-23: CxRXFUL2: ECANx RECEIVE BUFFER FULL REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (cleared by user software) DS70616G-page 378  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-24: CxRXOVF1: ECANx RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition (cleared by user software) REGISTER 21-25: CxRXOVF2: ECANx RECEIVE BUFFER OVERFLOW REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition (cleared by user software)  2009-2012 Microchip Technology Inc. DS70616G-page 379

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 21-26: CxTRmnCON: ECANx TX/RX BUFFER m CONTROL REGISTER (m = 0, 2, 4, 6; n = 1, 3, 5, 7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI<1:0> bit 15 bit 8 R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENm TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm RTRENm TXmPRI<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 See definition for bits 7-0, controls Buffer n bit 7 TXENm: TX/RX Buffer Selection bit 1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer bit 6 TXABTm: Message Aborted bit(1) 1 = Message was aborted 0 = Message completed transmission successfully bit 5 TXLARBm: Message Lost Arbitration bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERRm: Error Detected During Transmission bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQm: Message Send Request bit 1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent 0 = Clearing the bit to ‘0’ while set requests a message abort bit 2 RTRENm: Auto-Remote Transmit Enable bit 1 = When a remote transmit is received, TXREQm will be set 0 = When a remote transmit is received, TXREQm will be unaffected bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: This bit is cleared when TXREQm is set. Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM. DS70616G-page 380  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 21.5 ECAN Message Buffers ECAN Message Buffers are part of DMA RAM memory. They are not ECAN Special Function Registers. The user application must directly write into the DMA RAM area that is configured for ECAN Message Buffers. The location and size of the buffer area is defined by the user application. BUFFER 21-1: ECAN™ MESSAGE BUFFER WORD 0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — SID10 SID9 SID8 SID7 SID6 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-2 SID<10:0>: Standard Identifier bits bit 1 SRR: Substitute Remote Request bit When TXIDE = 0: 1 = Message will request remote transmission 0 = Normal message When TXIDE = 1: The SRR bit must be set to ‘1’. bit 0 IDE: Extended Identifier bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier BUFFER 21-2: ECAN™ MESSAGE BUFFER WORD 1 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — — — EID17 EID16 EID15 EID14 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 EID<17:6>: Extended Identifier bits  2009-2012 Microchip Technology Inc. DS70616G-page 381

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 (BUFFER 21-3: ECAN™ MESSAGE BUFFER WORD 2 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1 bit 15 bit 8 U-x U-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 EID<5:0>: Extended Identifier bits bit 9 RTR: Remote Transmission Request bit When TXIDE = 1: 1 = Message will request remote transmission 0 = Normal message When TXIDE = 0: The RTR bit is ignored. bit 8 RB1: Reserved Bit 1 User must set this bit to ‘0’ per CAN protocol. bit 7-5 Unimplemented: Read as ‘0’ bit 4 RB0: Reserved Bit 0 User must set this bit to ‘0’ per CAN protocol. bit 3-0 DLC<3:0>: Data Length Code bits BUFFER 21-4: ECAN™ MESSAGE BUFFER WORD 3 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 1 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 1<15:8>: ECAN Message Byte 0 bit 7-0 Byte 0<7:0>: ECAN Message Byte 1 DS70616G-page 382  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 BUFFER 21-5: ECAN™ MESSAGE BUFFER WORD 4 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 3 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 3<15:8>: ECAN Message Byte 3 bit 7-0 Byte 2<7:0>: ECAN Message Byte 2 BUFFER 21-6: ECAN™ MESSAGE BUFFER WORD 5 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 5 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 4 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 5<15:8>: ECAN Message Byte 5 bit 7-0 Byte 4<7:0>: ECAN Message Byte 4  2009-2012 Microchip Technology Inc. DS70616G-page 383

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 BUFFER 21-7: ECAN™ MESSAGE BUFFER WORD 6 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 7 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 7<15:8>: ECAN Message Byte 7 bit 7-0 Byte 6<7:0>: ECAN Message Byte 6 BUFFER 21-8: ECAN™ MESSAGE BUFFER WORD 7 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — FILHIT<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Code bits(1) Encodes the number of the filter that resulted in writing this buffer. bit 7-0 Unimplemented: Read as ‘0’ Note 1: Only written by the module for receive buffers, unused for transmit buffers. DS70616G-page 384  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 22.0 USB ON-THE-GO (OTG) The USB module consists of the clock generator, the MODULE (dsPIC33EPXXXMU8XX USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), pull-up and pull-down resistors, AND PIC24EPGU8XX DEVICES and the register interface. Figure22-1 illustrates the ONLY) block diagram of the USB OTG module. Note1: This data sheet is not intended to be a The device auxiliary clock generator provides the comprehensive reference source. To com- 48MHz clock required for USB communication. The plement the information in this data sheet, voltage comparators monitor the voltage on the VBUS refer to Section 25. “USB On-The-Go pin to determine the state of the bus. The transceiver (OTG)” (DS70571) of the “dsPIC33E/ provides the analog translation between the USB bus PIC24E Family Reference Manual”, which and the digital logic. The SIE is a state machine that is available from the Microchip web site transfers data to and from the endpoint buffers and (www.microchip.com). generates the protocol for data transfers. The 2: Some registers and associated bits integrated pull-up and pull-down resistors eliminate the described in this section may not be need for external signaling components. The register available on all devices. Refer to interface allows the CPU to configure and Section4.0 “Memory Organization” in communicate with the module. this data sheet for device-specific register Note: The implementation and use of the USB and bit information. specifications and other third party specifications or technology may require a 22.1 Overview license from various entities, including, but not limited to USB Implementers The Universal Serial Bus (USB) On-The-Go (OTG) Forum, Inc. (also referred to as USB-IF). It module includes the following features: is your responsibility to obtain more • USB Full-Speed Support for Host and Device information regarding any applicable licensing obligations. • Low-Speed Host Support • USB On-The-Go Support 22.2 Clearing USB OTG Interrupts • Integrated Signaling Resistors • Integrated Analog Comparators for VBUS Unlike device level interrupts, the USB OTG interrupt Monitoring status flags are not freely writable in software. All USB • Integrated USB Transceiver OTG flag bits are implemented as hardware set-only • Hardware Performs Transaction Handshaking bits. Additionally, these bits can only be cleared in • Endpoint Buffering Anywhere in System RAM software by writing a ‘1’ to their locations (i.e., performing a BSET instruction). Writing a ‘0’ to a flag bit • Integrated DMA Controller to Access System (i.e., a BCLR instruction) has no effect. RAM • Support for all four transfer types: Note: Throughout this section, a bit that can only - Control be cleared by writing a ‘1’ to its location is - Interrupt referred to as “Write ‘1’ to clear bit”. In reg- ister descriptions, this function is indicated - Bulk Data by the descriptor, “K”. - Isochronous • Queueing of up to Four Endpoint Transfers without Servicing • USB 5V Charge Pump Controller The USB module contains the analog and digital components to provide a USB 2.0 full-speed and low- speed embedded host, full-speed device or OTG implementation with a minimum of external components.  2009-2012 Microchip Technology Inc. DS70616G-page 385

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 22-1: USB INTERFACE DIAGRAM 48 MHz USB Clock Full-Speed Pull-up from Auxiliary PLL Host Pull-down D+ Registers USB and Transceiver Control Interface D- Low-Speed Pull-up Host Pull-Down USBID USB VMIO SIE VPIO DMH DPH External Transceiver Interface DMLN DPLN RCV USBOEN System VBUSON RAM SRP Charge USB VBUS Voltage Comparators SRP Discharge VUSB3V3 VCMPST1 External VBUS VCMPST2 Comparator Interface VCMPST3 VCPCON VBUS Boost Controller VBUSST DS70616G-page 386  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 22.3 USB OTG Resources 22.3.1 KEY RESOURCES Many useful resources related to USB OTG are • Section 11. “USB On-The-Go (OTG)” provided on the main product page of the Microchip (DS70571) in the “dsPIC33E/PIC24E Family web site for the devices listed in this data sheet. This Reference Manual” product page, which can be accessed using this link, • Code Samples contains the latest updates and additional information. • Application Notes • Software Libraries Note: In the event you are not able to access the product page using the link above, enter • Webinars this URL in your browser: • All related “dsPIC33E/PIC24E Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en554310 • Development Tools  2009-2012 Microchip Technology Inc. DS70616G-page 387

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 22.4 USB Control Registers REGISTER 22-1: UxOTGSTAT: USB OTG STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC U-0 R-0, HSC U-0 R-0, HSC R-0, HSC U-0 R-0, HSC ID — LSTATE — SESVD SESEND — VBUSVD bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 ID: ID Pin State Indicator bit 1 = No cable is attached or a Type B plug has been plugged into the USB receptacle 0 = A Type A plug has been plugged into the USB receptacle bit 6 Unimplemented: Read as ‘0’ bit 5 LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1ms 0 = The USB line state has NOT been stable for the previous 1ms bit 4 Unimplemented: Read as ‘0’ bit 3 SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B device bit 2 SESEND: B-Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the B device 0 = The VBUS voltage is above VB_SESS_END on the B device bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVD: A-VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A device 0 = The VBUS voltage is below VA_VBUS_VLD on the A device DS70616G-page 388  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-2: UxOTGCON: USB ON-THE-GO CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DPPULUP DMPULUP DPPULDWN(1) DMPULDWN(1) VBUSON(1) OTGEN(1) VBUSCHG(1) VBUSDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled bit 4 DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled bit 3 VBUSON: VBUS Power-on bit(1) 1 = VBUS line is powered 0 = VBUS line is not powered bit 2 OTGEN: OTG Features Enable bit(1) 1 = USB OTG is enabled; all D+/D- pull-ups and pull-downs are enabled 0 = USB OTG is disabled; D+/D- pull-ups and pull-downs are controlled in hardware by the settings of the HOSTEN and USBEN bits (UxCON<3,0>) bit 1 VBUSCHG: VBUS Charge Selection bit(1) 1 = VBUS line is set to charge to 3.3V 0 = VBUS line is set to charge to 5V bit 0 VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line is discharged through a resistor 0 = VBUS line is not discharged Note 1: These bits are only used in Host mode; do not use in Device mode.  2009-2012 Microchip Technology Inc. DS70616G-page 389

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-3: UxPWRC: USB POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 HS, HC U-0 U-0 R/W U-0 U-0 R/W-0, HC R/W-0 UACTPND — — USLPGRD — — USUSPND USBPWR(1) bit 7 bit 0 Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires the USLPGRD bit to be set) 0 = Module may be suspended or powered down bit 6-5 Unimplemented: Read as ‘0’ bit 4 USLPGRD: USB Sleep Guard bit 1 = Indicates to the USB module that it is about to be suspended or powered down 0 = No suspend bit 3-2 Unimplemented: Read as ‘0’ bit 1 USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode 0 = Normal USB OTG operation bit 0 USBPWR: USB Operation Enable bit(1) 1 = USB OTG module is enabled 0 = USB OTG module is disabled Note 1: Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (UxCON<3,0> and UxOTGCON<2>) are also cleared. DS70616G-page 390  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-4: UxSTAT: USB STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC U-0 U-0 ENDPT<3:0>(2) DIR PPBI(1) — — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 ENDPT<3:0>: Last Endpoint Activity Number bits (represents the number of the endpoint BDT updated by the last USB transfer)(2) 1111 = Endpoint 15 1110 = Endpoint 14 • • • 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last Buffer Descriptor Direction Indicator bit 1 = The last transaction was a transmit transfer (TX) 0 = The last transaction was a receive transfer (RX) bit 2 PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit(1) 1 = The last transaction was to the ODD buffer descriptor bank 0 = The last transaction was to the EVEN buffer descriptor bank bit 1-0 Unimplemented: Read as ‘0’ Note 1: This bit is only valid for endpoints with available EVEN and ODD buffer descriptor registers. 2: In Host mode, all transactions are processed through Endpoint 0 and the Endpoint 0 BDTs. Therefore, ENDPT<3:0> will always read as ‘0000’.  2009-2012 Microchip Technology Inc. DS70616G-page 391

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-5: UxCON: USB CONTROL REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R-x, HSC R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — SE0 PKTDIS — HOSTEN(1) RESUME PPBRST USBEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected bit 5 PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing are disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing are enabled bit 4 Unimplemented: Read as ‘0’ bit 3 HOSTEN: USB Host Mode Enable bit(1) 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled bit 2 RESUME: USB Resume Signaling Enable bit 1 = Resume signaling is activated 0 = Resume signaling is disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Resets all Ping-Pong Buffer Pointers to the EVEN buffer descriptor banks 0 = Ping-Pong Buffer Pointers are not reset bit 0 USBEN: USB Module Enable bit 1 = USB module and supporting circuitry are enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry are disabled (device detached) Note 1: This bit should be ‘0’ in Device mode. DS70616G-page 392  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-6: UxCON: USB CONTROL REGISTER (HOST MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-x, HSC R-x, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 JSTATE: Live Differential Receiver J State Flag bit 1 = J state (differential ‘0’ in low-speed, differential ‘1’ in full-speed) is detected on the USB 0 = No J state is detected bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected bit 5 TOKBUSY: Token Busy Status bit 1 = Token is being executed by the USB module in On-The-Go state 0 = No token is being executed bit 4 USBRST: USB Reset bit 1 = USB Reset has been generated; for Software Reset, application must set this bit for 50ms and then clear it 0 = USB Reset is terminated bit 3 HOSTEN: USB Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled bit 2 RESUME: USB Resume Signaling Enable bit 1 = Resume signaling is activated; software must set the bit for 10ms and then clear to enable remote wake-up 0 = Resume signaling is disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Resets all Ping-Pong Buffer Pointers to the EVEN buffer descriptor banks 0 = Ping-Pong Buffer Pointers are not reset bit 0 SOFEN: USB Start-of-Frame (SOF) Enable bit 1 = Start-of-Frame token is sent every one 1 ms 0 = Start-of-Frame token is disabled  2009-2012 Microchip Technology Inc. DS70616G-page 393

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-7: UxADDR: USB ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN(1) DEVADDR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: USB Low-Speed Enable Indicator bit(1) 1 = USB module operates at low-speed 0 = USB module operates at full-speed bit 6-0 DEVADDR<6:0>: USB Device Address bits Note 1: Host mode only. In Device mode, this bit is unimplemented. REGISTER 22-8: UxTOK: USB TOKEN REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID<3:0>(1) EP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 PID<3:0>: Token Type Identifier bits(1) 1101 = SETUP (TX) token type transaction 1001 = IN (RX) token type transaction 0001 = OUT (TX) token type transaction bit 3-0 EP<3:0>: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. Note 1: All other combinations are reserved and are not to be used. DS70616G-page 394  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-9: UxSOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 CNT<7:0>: Start-of-Frame Count bits Value represents 10 + (packet size of n bytes); for example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet REGISTER 22-10: UxCNFG1: USB CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 UTEYE UOEMON(1) — USBSIDL — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled bit 6 UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive(1) bit 5 Unimplemented: Read as ‘0’ bit 4 USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 3-0 Unimplemented: Read as ‘0’ Note 1: When the UTRIS (UxCNFG2<0>) bit is set, the OE signal is active regardless of the setting of UOEMON.  2009-2012 Microchip Technology Inc. DS70616G-page 395

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-11: UxCNFG2: USB CONFIGURATION REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — UVCMPSEL PUVBUS EXTI2CEN UVBUSDIS(1) UVCMPDIS(1) UTRDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 UVCMPSEL: USB External Comparator Input Mode Select bit When UVCMPDIS is Set: 1 = Use 3-pin input for external comparators 0 = Use 2-pin input for external comparators bit 4 PUVBUS: VBUS Pull-up Enable bit 1 = Pull-up on VBUS pin is enabled 0 = Pull-up on VBUS pin is disabled bit 3 EXTI2CEN: I2C™ Interface for External Module Control Enable bit 1 = External module(s) controlled via I2C interface 0 = External module(s) controlled via dedicated pins bit 2 UVBUSDIS: USB On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder is disabled; digital output control interface is enabled 0 = On-chip boost regulator builder is active bit 1 UVCMPDIS: USB On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator is disabled; digital input status interface is enabled 0 = On-chip charge VBUS comparator is active bit 0 UTRDIS: USB On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver is disabled; digital transceiver interface is enabled 0 = On-chip transceiver is active Note 1: Do not change this bit while the USBPWR bit is set (UxPWRC<0> = 1). DS70616G-page 396  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-12: UxOTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS U-0 R/K-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state is detected 0 = No ID state change bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1ms, but different from last time 0 = USB line state has not been stable for 1ms bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS is detected 0 = No activity on the D+/D- lines or VBUS is detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_VLD (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_VLD bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device is detected; VBUS has crossed VB_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = VBUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB OTG Specification)(1) 0 = No VBUS change on A-device is detected Note 1: VBUS threshold crossings may be either rising or falling.  2009-2012 Microchip Technology Inc. DS70616G-page 397

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-13: UxOTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 Unimplemented: Read as ‘0’ bit 0 VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DS70616G-page 398  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-14: UxIR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 Unimplemented: Read as ‘0’ bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-State is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-State is observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3ms or more) 0 = No Idle condition is detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read UxSTAT register for endpoint BDT information 0 = Processing of current token is not complete; clear UxSTAT register or load next token from STAT (clearing this bit causes the the STAT FIFO to advance) bit 2 SOFIF: Start-of-Frame Token Interrupt bit 1 = A Start-of-Frame token was received by the peripheral 0 = A Start-of-Frame token has not been received by the peripheral bit 1 UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the UxEIE register can set this bit 0 = No unmasked error condition has occurred bit 0 URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred  2009-2012 Microchip Technology Inc. DS70616G-page 399

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-15: UxIR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; set if the bus state is not SE0 and there has been no bus activity for 2.5s 0 = No peripheral attachment is detected bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-State is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-State is observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3ms or more) 0 = No Idle condition is detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read USTAT register for endpoint BDT information 0 = Processing of current token is not complete; clear USTAT register or load next token from STAT bit 2 SOFIF: Start-of-Frame Token Interrupt bit 1 = Start-of-Frame threshold is reached by the host 0 = No Start-of-Frame token threshold is reached bit 1 UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the UxEIE register can set this bit 0 = No unmasked error condition has occurred bit 0 DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module 0 = No peripheral detachment has been detected DS70616G-page 400  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-16: UxIE: USB INTERRUPT ENABLE REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STALLIE — RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 RESUMEIE: Resume Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 IDLEIE: Idle Detect Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 SOFIE: Start-of-Frame Token Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 UERRIE: USB Error Condition Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 URSTIE: USB Reset Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled  2009-2012 Microchip Technology Inc. DS70616G-page 401

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-17: UxIE: USB INTERRUPT ENABLE REGISTER (HOST MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STALLIE ATTACHIE(1) RESUMEIE IDLEIE TRNIE SOFIE UERRIE DETACHIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 ATTACHIE: Peripheral Attach Interrupt bit(1) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 RESUMEIE: Resume Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 IDLEIE: Idle Detect Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 SOFIE: Start-of-Frame Token Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 UERRIE: USB Error Condition Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 DETACHIE: USB Detach Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: Unimplemented in OTG mode, read as ‘0’. DS70616G-page 402  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-18: UxEIR: USB ERROR INTERRUPT STATUS REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0,HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS BTSEF BUSACCEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error has been detected bit 6 BUSACCEF: Bus Access Error Flag bit 1 = Peripheral tried to access an unimplemented RAM location 0 = RAM location access was successful bit 5 DMAEF: DMA Error Flag bit 1 = A USB DMA error condition is detected; the data size indicated by the buffer descriptor byte count field is less than the number of received bytes; the received data is truncated 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out has occurred bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed bit 1 CRC5EF: CRC5 Host Error Flag bit 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted (no CRC5 error) bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed  2009-2012 Microchip Technology Inc. DS70616G-page 403

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-19: UxEIR: USB ERROR INTERRUPT STATUS REGISTER (HOST MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0,HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS BTSEF BUSACCEF DMAEF BTOEF DFN8EF CRC16EF EOFEF PIDEF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error has been detected bit 6 BUSACCEF: Bus Access Error Flag bit 1 = Peripheral tried to access an unimplemented RAM location 0 = RAM location access was successful bit 5 DMAEF: DMA Error Flag bit 1 = A USB DMA error condition is detected; the data size indicated by the buffer descriptor byte count field is less than the number of received bytes, the received data is truncated 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out has occurred bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed bit 1 EOFEF: End-of-Frame (EOF) Error Flag bit 1 = End-of-Frame error has occurred 0 = End-of-Frame interrupt is disabled bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed DS70616G-page 404  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-20: UxEIE: USB ERROR INTERRUPT ENABLE REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BUSACCEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 BUSACCEE: Bus Access Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled  2009-2012 Microchip Technology Inc. DS70616G-page 405

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-21: UxEIE: USB ERROR INTERRUPT ENABLE REGISTER (HOST MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BUSACCEE DMAEE BTOEE DFN8EE CRC16EE EOFEE PIDEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 BUSACCEE: Bus Access Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DS70616G-page 406  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-22: UxEPn: USB ENDPOINT n CONTROL REGISTERS (n = 0 TO 15) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD(1) RETRYDIS(1) — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPD: Low-Speed Direct Connection Enable bit (UEP0 only)(1) 1 = Direct connection to a low-speed device is enabled 0 = Direct connection to a low-speed device is disabled bit 6 RETRYDIS: Retry Disable bit (UEP0 only)(1) 1 = Retry NAK transactions is disabled 0 = Retry NAK transactions is enabled; retry done in hardware bit 5 Unimplemented: Read as ‘0’ bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXENand EPRXEN=1: 1 = Disable Endpoint n from control transfers; only TX and RX transfers are allowed 0 = Enable Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed For all other combinations of EPTXEN and EPRXEN: This bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake is enabled 0 = Endpoint handshake is disabled (typically used for isochronous endpoints) Note 1: These bits are available only for UxEP0 and only in Host mode. For all other UxEPn registers, these bits are always unimplemented and read as ‘0’.  2009-2012 Microchip Technology Inc. DS70616G-page 407

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-23: UxBDTP1: USB BUFFER DESCRIPTION TABLE REGISTER1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 BDTPTRL<15:9> — bit 7 bit 0 Legend: R = Readable bit W =Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-1 BDTPTRL<15:9>: Endpoint BDT Start Address bits Defines bits 15-9 of the 32-bit endpoint buffer descriptor table start address. bit 0 Unimplemented: Read as ‘0’ REGISTER 22-24: UxBDTP2: USB BUFFER DESCRIPTION TABLE REGISTER2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRH<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 BDTPTRH<23:16>: Endpoint BDT Start Address bits Defines bits 23-16 of the 32-bit endpoint buffer descriptor table start address. DS70616G-page 408  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-25: UxBDTP3: USB BUFFER DESCRIPTION TABLE REGISTER3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRU<31:24> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 BDTPTRU<31:24>: Endpoint BDT Start Address bits Defines bits 31-24 of the 32-bit endpoint buffer descriptor table start address. REGISTER 22-26: UxPWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 PWMEN — — — — — PWMPOL CNTEN bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in the Reset state specified by PWMPOL bit 14-10 Unimplemented: Read as ‘0’ bit 9 PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low bit 8 CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled bit 7-0 Unimplemented: Read as ‘0’  2009-2012 Microchip Technology Inc. DS70616G-page 409

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-27: UxPWMRRS: DUTY CYCLE AND PWM PERIOD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DC<7:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 DC<7:0>: Duty Cycle bits These bits select the PWM duty cycle. bit 7-0 PER<7:0>: PWM Period bits These bits select the PWM period. REGISTER 22-28: UxFRMH: USB FRAME NUMBER HIGH REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — FRM<10:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 FRM<10:8>: 11-Bit Frame Number Upper 3 bits These register bits are updated with the current frame number whenever a SOF token is received. DS70616G-page 410  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 22-29: UxFRML: USB FRAME NUMBER LOW REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FRM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 FRM<7:0>: 11-Bit Frame Number Lower 8 bits These register bits are updated with the current frame number whenever a SOF token is received.  2009-2012 Microchip Technology Inc. DS70616G-page 411

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 412  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 23.0 10-BIT/12-BIT ANALOG-TO- 23.1 Key Features DIGITAL CONVERTER (ADC) The 10-bit ADC configuration has the following key features: Note1: This data sheet summarizes the features of the dsPIC33EPXXX(GP/MC/MU)806/ • Successive Approximation (SAR) Conversion 810/814 and PIC24EPXXX(GP/GU)810/ • Conversion Speeds of up to 1.1 Msps 814 families of devices. It is not intended • Up to 32 Analog Input Pins to be a comprehensive reference source. • External Voltage Reference Input Pins To complement the information in this • Simultaneous Sampling of up to Four Analog data sheet, refer to Section 16. “Analog- Input Pins to-Digital Converter (ADC)” (DS70621) • Automatic Channel Scan mode of the “dsPIC33E/PIC24E Family Refer- ence Manual”, which is available from the • Selectable Conversion Trigger Source Microchip web site (www.microchip.com). • Selectable Buffer Fill modes 2: Some registers and associated bits • Four Result Alignment Options (signed/unsigned, described in this section may not be fractional/integer) available on all devices. Refer to • Operation during CPU Sleep and Idle modes Section4.0 “Memory Organization” in The 12-bit ADC configuration supports all the above this data sheet for device-specific register features, except: and bit information. • In the 12-bit configuration, conversion speeds of The dsPIC33EPXXX(GP/MC/MU)806/810/814 and up to 500 ksps are supported PIC24EPXXX(GP/GU)810/814 devices have two ADC • There is only one S&H amplifier in the 12-bit modules, ADC1 and ADC2. The ADC1 module configuration, so simultaneous sampling of supports up to 32 analog input channels. The ADC2 multiple channels is not supported. module supports up to 16 analog input channels. Depending on the particular device pinout, the ADC On ADC1, the AD12B bit (AD1CON1<10>) allows each can have up to 32 analog input pins, designated AN0 of the ADC modules to be configured by the user as through AN31. In addition, there are two analog input either a 10-bit, 4 Sample-and-Hold (S&H) ADC (default pins for external voltage reference connections. These configuration) or a 12-bit, 1 S&H ADC. voltage reference inputs can be shared with other ana- log input pins. The actual number of analog input pins Note: The ADC1 module needs to be disabled and external voltage reference input configuration before modifying the AD12B bit. depends on the specific device. The ADC2 module only supports 10-bit operation with A block diagram of the ADC module is shown in 4 S&H. Figure23-1. Figure23-2 provides a diagram of the ADC conversion clock period.  2009-2012 Microchip Technology Inc. DS70616G-page 413

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 23-1: ADCx MODULE BLOCK DIAGRAM AN0 ANy(3) S&H0 Channel Scan + CH0SA<4:0> CH0SB<4:0> - CH0 CSCNA AN1 VREFL CH0NA CH0NB AN0 VREF+(1) AVDD VREF-(1) AVSS AN3 S&H1 + CH123SA CH123SB - CH1(2) AN6 VCFG<2:0> AN9 ADCxBUF0(4) VREFL ADCxBUF1(4) ADCxBUF2(4) VREFH VREFL CH123NA CH123NB SAR ADC AN1 AN4 S&H2 + ADCxBUFE(4) CH123SA CH123SB - ADCxBUFF(4) CH2(2) AN7 AN10 VREFL CH123NA CH123NB AN2 AN5 S&H3 + CH123SA CH123SB CH3(2) - AN8 AN11 Note 1: VREF+, VREF- inputs can be multiplexed VREFL with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 3: For dsPIC33EPXXX(GP/MC/MU)806 and CH123NA CH123NB PIC24EPXXXGP806 devices, y=0-15 and 24-31; for ADC2, y = 15; for all others, y = 32. Alternate 4: When ADDMAEN (ADxCON4<8>)=1, Input Selection enabling DMA, only ADCxBUF0 is used. DS70616G-page 414  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 23-2: ADCx CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADxCON3<15> ADCx Internal RC Clock(1) 1 TAD ADxCON3<7:0> 0 6 ADCx Conversion TP(2) Clock Multiplier 1, 2, 3, 4, 5,..., 64 Note 1: See the ADC electrical characteristics in Section32.0 “Electrical Characteristics” for the exact RC clock value. 2: TP = 1/FP.  2009-2012 Microchip Technology Inc. DS70616G-page 415

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 23.2 ADC Helpful Tips 23.3 ADC Resources 1. The SMPIx control bits in the ADxCON2 registers: Many useful resources related to Analog-to-Digital a) Determine when the ADC interrupt flag is set conversion are provided on the main product page of and an interrupt is generated, if enabled. the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using b) When the CSCNA bit in the ADxCON2 reg- ister is set to ‘1’, this determines when the this link, contains the latest updates and additional ADC analog scan channel list, defined in information. the AD1CSSL/AD1CSSH registers, starts Note: In the event you are not able to access the over from the beginning. product page using the link above, enter c) When the DMA peripheral is not used this URL in your browser: (ADDMAEN = 0), this determines when the http://www.microchip.com/wwwproducts/ ADC Result Buffer Pointer to ADC1BUF0- Devices.aspx?dDocName=en554310 ADC1BUFF gets reset back to the beginning at ADC1BUF0. 23.3.1 KEY RESOURCES d) When the DMA peripheral is used (ADDMAEN = 1), this determines when the • Section 16. “Analog-to-Digital Converter DMA Address Pointer is incremented after a (ADC)” (DS70621) in the “dsPIC33E/PIC24E sample/conversion operation. ADC1BUF0 is Family Reference Manual” the only ADC buffer used in this mode. The • Code Samples ADC Result Buffer Pointer to ADC1BUF0- • Application Notes ADC1BUFF gets reset back to the beginning • Software Libraries at ADC1BUF0. The DMA address is incre- mented after completion of every 32nd • Webinars sample/conversion operation. Conversion • All related “dsPIC33E/PIC24E Family Reference results are stored in the ADC1BUF0 register Manual” Sections for transfer to RAM using DMA. • Development Tools 2. When the DMA module is disabled (ADDMAEN= 0), the ADC has 16 result buffers. ADC conversion results are stored sequentially in ADC1BUF0-ADC1BUFF, regardless of which analog inputs are being used subject to the SMPIx bits and the condition described in 1c) above. There is no relationship between the ANx input being measured and which ADC buffer (ADC1BUF0-ADC1BUFF) that the conversion results will be placed in. 3. When the DMA module is disabled (ADDMAEN= 1), the ADC module has only 1ADC result buffer (i.e., ADC1BUF0) per ADC peripheral and the ADC conversion result must be read, either by the CPU or DMA controller, before the next ADC conversion is complete to avoid overwriting the previous value. 4. The DONE bit (ADxCON1<0>) is only cleared at the start of each conversion and is set at the completion of the conversion, but remains set indefinitely, even through the next sample phase until the next conversion begins. If application code is monitoring the DONE bit in any kind of software loop, the user must consider this behavior because the CPU code execution is faster than the ADC. As a result, in Manual Sample mode, particularly where the user’s code is setting the SAMP bit (ADxCON1<1>), the DONE bit should also be cleared by the user application just before setting the SAMP bit. DS70616G-page 416  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 23.4 ADC Control Registers REGISTER 23-1: ADxCON1: ADCx CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B(1) FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HSC R/C-0, HSC SSRC<2:0> SSRCG SIMSAM ASAM(3) SAMP DONE(3) bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: ADC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 ADDMABM: DMA Buffer Build Mode bit 1 = DMA buffers are written in the order of conversion; the module provides an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer 0 = DMA buffers are written in Scatter/Gather mode; the module provides a Scatter/Gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer bit 11 Unimplemented: Read as ‘0’ bit 10 AD12B: ADC 10-Bit or 12-Bit Operation Mode bit(1) 1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation bit 9-8 FORM<1:0>: Data Output Format bits For 10-Bit Operation: 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>) 00 = Integer (DOUT = 0000 00dd dddd dddd) For 12-Bit Operation: 11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>) 10 = Fractional (DOUT = dddd dddd dddd 0000) 01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>) 00 = Integer (DOUT = 0000 dddd dddd dddd) Note 1: This bit is only available in the ADC1 module. In the ADC2 module, this bit is unimplemented and is read as ‘0’. 2: This setting is available in dsPIC33EPXXX(MC/MU)806/810/814 devices only. 3: Do not clear the DONE bit in software if ADC Sample Auto-Start is enabled (ASAM = 1).  2009-2012 Microchip Technology Inc. DS70616G-page 417

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 23-1: ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED) bit 7-5 SSRC<2:0>: Sample Clock Source Select bits If SSRCG = 1: 111 = Reserved 110 = PWM Generator 7 primary trigger compare ends sampling and starts conversion(2) 101 = PWM Generator 6 primary trigger compare ends sampling and starts conversion(2) 100 = PWM Generator 5 primary trigger compare ends sampling and starts conversion(2) 011 = PWM Generator 4 primary trigger compare ends sampling and starts conversion(2) 010 = PWM Generator 3 primary trigger compare ends sampling and starts conversion(2) 001 = PWM Generator 2 primary trigger compare ends sampling and starts conversion(2) 000 = PWM Generator 1 primary trigger compare ends sampling and starts conversion(2) If SSRCG = 0: 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = PWM secondary Special Event Trigger ends sampling and starts conversion(2) 100 = Timer5 compare ends sampling and starts conversion 011 = PWM primary Special Event Trigger ends sampling and starts conversion(2) 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on the INT0 pin ends sampling and starts conversion 000 = Clearing the Sample bit (SAMP) ends sampling and starts conversion (Manual mode) bit 4 SSRCG: Sample Clock Source Group bit (See bits<7-5> for details.) bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence bit 2 ASAM: ADC Sample Auto-Start bit(3) 1 = Sampling begins immediately after the last conversion; SAMP bit is auto-set 0 = Sampling begins when the SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC S&H amplifiers are sampling 0 = ADC S&H amplifiers are holding If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000, automatically cleared by hardware to end sampling and start conversion. bit 0 DONE: ADC Conversion Status bit(3) 1 = ADC conversion cycle is completed. 0 = ADC conversion has not started or is in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear the DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress. Automatically cleared by hardware at the start of a new conversion. Note 1: This bit is only available in the ADC1 module. In the ADC2 module, this bit is unimplemented and is read as ‘0’. 2: This setting is available in dsPIC33EPXXX(MC/MU)806/810/814 devices only. 3: Do not clear the DONE bit in software if ADC Sample Auto-Start is enabled (ASAM = 1). DS70616G-page 418  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 23-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG<2:0> — — CSCNA CHPS<1:0> bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS SMPI<4:0> BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits VREFH VREFL 000 AVDD Avss 001 External VREF+ Avss 010 AVDD External VREF- 011 External VREF+ External VREF- 1xx AVDD Avss bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Input Scan Select bit 1 = Scans inputs for CH0+ during Sample A bit 0 = Does not scan inputs bit 9-8 CHPS<1:0>: Channel Select bits When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’: 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling the second half of the buffer; the user application should access data in the first half of the buffer 0 = ADC is currently filling the first half of the buffer; the user application should access data in the second half of the buffer bit 6-2 SMPI<4:0>: Increment Rate bits When ADDMAEN = 0: 01111 = Generates interrupt after completion of every 16th sample/conversion operation 01110 = Generates interrupt after completion of every 15th sample/conversion operation • • • 00001 = Generates interrupt after completion of every 2nd sample/conversion operation 00000 = Generates interrupt after completion of every sample/conversion operation When ADDMAEN = 1: 11111 = Increments the DMA address after completion of every 32nd sample/conversion operation 11110 = Increments the DMA address after completion of every 31st sample/conversion operation • • • 00001 = Increments the DMA address after completion of every 2nd sample/conversion operation 00000 = Increments the DMA address after completion of every sample/conversion operation  2009-2012 Microchip Technology Inc. DS70616G-page 419

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 23-2: AD1CON2: ADC1 CONTROL REGISTER 2 (CONTINUED) bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts filling the first half of the buffer on the first interrupt and the second half of the buffer on the next interrupt 0 = Always starts filling the buffer from the Start address. bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on the first sample and Sample B on the next sample 0 = Always uses channel input selects for Sample A DS70616G-page 420  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 23-3: AD2CON2: ADC2 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG<2:0> — — CSCNA CHPS<1:0> bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI<3:0> BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits VREFH VREFL 000 AVDD Avss 001 External VREF+ Avss 010 AVDD External VREF- 011 External VREF+ External VREF- 1xx AVDD Avss bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Input Scan Select bit 1 = Scans inputs for CH0+ during Sample A bit 0 = Does not scan inputs bit 9-8 CHPS<1:0>: Channel Select bits When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’: 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling the second half of the buffer; the user application should access data in the first half of the buffer 0 = ADC is currently filling the first half of the buffer; the user application should access data in the second half of the buffer bit 6-2 SMPI<3:0>: Increment Rate bits When ADDMAEN = 0: 1111 = Generates interrupt after completion of every 16th sample/conversion operation 1110 = Generates interrupt after completion of every 15th sample/conversion operation • • • 0001 = Generates interrupt after completion of every 2nd sample/conversion operation 0000 = Generates interrupt after completion of every sample/conversion operation When ADDMAEN = 1: 1111 = Increments the DMA address after completion of every 16th sample/conversion operation 1110 = Increments the DMA address after completion of every 15th sample/conversion operation • • • 0001 = Increments the DMA address after completion of every 2nd sample/conversion operation 0000 = Increments the DMA address after completion of every sample/conversion operation  2009-2012 Microchip Technology Inc. DS70616G-page 421

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 23-3: AD2CON2: ADC2 CONTROL REGISTER 2 (CONTINUED) bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer on the next interrupt 0 = Always starts filling the buffer from the Start address bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A DS70616G-page 422  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 23-4: ADxCON3: ADCx CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC<4:0>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0>(2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock Derived From System Clock bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1) 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2,3) 11111111 = TP • (ADCS<7:0> + 1) = 256 • TCY = TAD • • • 00000010 = TP • (ADCS<7:0> + 1) = 3 • TCY = TAD 00000001 = TP • (ADCS<7:0> + 1) = 2 • TCY = TAD 00000000 = TP • (ADCS<7:0> + 1) = 1 • TCY = TAD Note 1: This bit is only used if ADxCON1<7:5> (SSRC<2:0>) = 111 and ADxCON1<4> (SSRCG) = 0. 2: This bit is not used if ADxCON3<15> (ADRC) = 1. 3: TP = 1/FP.  2009-2012 Microchip Technology Inc. DS70616G-page 423

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 23-5: ADxCON4: ADCx CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADDMAEN bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DMABL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 ADDMAEN: ADC DMA Enable bit 1 = Conversion results are stored in ADCxBUF0 register for transferring to RAM using DMA 0 = Conversion results are stored in ADCxBUF0 through ADCxBUFF registers; DMA will not be used bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input DS70616G-page 424  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 23-6: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NB<1:0> CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NA<1:0> CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’: 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 0x = CH1, CH2, CH3 negative input is VREFL bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’: 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’: 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 0x = CH1, CH2, CH3 negative input is VREFL bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’: 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2  2009-2012 Microchip Technology Inc. DS70616G-page 425

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 23-7: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — CH0SB<4:0>(1) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit Same definition as bit 7. bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits(1) Same definition as bits<4:0>. bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits(1) 11111 = Channel 0 positive input is AN31 11110 = Channel 0 positive input is AN30 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 Note 1: The AN16 through AN31 pins are not available for the ADC2 module. The AN16 through AN23 pins are not available for dsPIC33EP256MU806 (64-pin) devices. DS70616G-page 426  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 23-8: AD1CSSH: ADC1 INPUT SCAN SELECT REGISTER HIGH(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CSS<31:16>: ADC1 Input Scan Selection bits 1 = Selects ANx for input scan 0 = Skips ANx for input scan Note 1: On devices with less than 32 analog inputs, all ADxCSSH bits can be selected by user software. However, inputs selected for scan without a corresponding input on the device converts to VREFL. 2: CSSx = ANx, where x = 16-31. 3: ADC2 only supports analog inputs, AN0-AN15; therefore, no ADC2 Input Scan Select register exists. REGISTER 23-9: ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CSS<15:0>: ADC Input Scan Selection bits 1 = Selects ANx for input scan 0 = Skips ANx for input scan Note 1: On devices with less than 16 analog inputs, all ADxCSSL bits can be selected by the user. However, inputs selected for scan without a corresponding input on the device converts to VREFL. 2: CSSx = ANx, where x = 0-15.  2009-2012 Microchip Technology Inc. DS70616G-page 427

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 428  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 24.0 DATA CONVERTER 24.1 Module Introduction INTERFACE (DCI) MODULE The Data Converter Interface (DCI) module allows simple interfacing of devices, such as audio coder/ Note1: This data sheet is not intended to be a decoders (Codecs), ADC and D/A Converters. The comprehensive reference source. To following interfaces are supported: complement the information in this data sheet, refer to “Section 20. Data • Framed Synchronous Serial Transfer (Single or Converter Interface (DCI)” (DS70356) Multi-Channel) of the “dsPIC33E/PIC24E Family • Inter-IC Sound (I2S) Interface Reference Manual”, which is available • AC-Link Compliant mode from the Microchip web site General features include: (www.microchip.com). • Programmable word size up to 16 bits 2: Some registers and associated bits • Supports up to 16 time slots, for a maximum described in this section may not be frame size of 256 bits available on all devices. Refer to Section4.0 “Memory Organization” in • Data buffering for up to 4 samples without CPU this data sheet for device-specific register overhead and bit information. FIGURE 24-1: DCI MODULE BLOCK DIAGRAM BCG Control Bits SCKD Sample Rate FP CSCK Generator FSD Word Size Selection bits Frame Frame Length Selection bits Synchronization COFS DCI Mode Selection bits Generator s u B a at D Bit Receive Buffer 6- Registers w/Shadow 1 DCI Buffer Control Unit 15 0 Transmit Buffer DCI Shift Register CSDI Registers w/Shadow CSDO  2009-2012 Microchip Technology Inc. DS70616G-page 429

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 24.2 DCI Resources 24.2.1 KEY RESOURCES Many useful resources related to DCI are provided on • Section 20. “Data Converter Interface (DCI)” the main product page of the Microchip web site for the (DS70356) in the “dsPIC33E/PIC24E Family devices listed in this data sheet. This product page, Reference Manual” which can be accessed using this link, contains the • Code Samples latest updates and additional information. • Application Notes • Software Libraries Note: In the event you are not able to access the product page using the link above, enter • Webinars this URL in your browser: • All related “dsPIC33E/PIC24E Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en554310 • Development Tools DS70616G-page 430  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 24.3 DCI Control Registers REGISTER 24-1: DCICON1: DCI CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DCIEN r DCISIDL r DLOOP CSCKD CSCKE COFSD bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 UNFM CSDOM DJST r r r COFSM<1:0> bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DCIEN: DCI Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Reserved: Read as ‘0’ bit 13 DCISIDL: DCI Stop in Idle Control bit 1 = Module will halt in CPU Idle mode 0 = Module will continue to operate in CPU Idle mode bit 12 Reserved: Read as ‘0’ bit 11 DLOOP: Digital Loopback Mode Control bit 1 = Digital Loopback mode is enabled; CSDI and CSDO pins are internally connected 0 = Digital Loopback mode is disabled bit 10 CSCKD: Sample Clock Direction Control bit 1 = CSCK pin is an input when DCI module is enabled 0 = CSCK pin is an output when DCI module is enabled bit 9 CSCKE: Sample Clock Edge Control bit 1 = Data changes on serial clock falling edge, sampled on serial clock rising edge 0 = Data changes on serial clock rising edge, sampled on serial clock falling edge bit 8 COFSD: Frame Synchronization Direction Control bit 1 = COFS pin is an input when DCI module is enabled 0 = COFS pin is an output when DCI module is enabled bit 7 UNFM: Underflow Mode bit 1 = Transmits last value written to the Transmit registers on a transmit underflow 0 = Transmits ‘0’s on a transmit underflow bit 6 CSDOM: Serial Data Output Mode bit 1 = CSDO pin will be tri-stated during disabled transmit time slots 0 = CSDO pin drives ‘0’s during disabled transmit time slots bit 5 DJST: DCI Data Justification Control bit 1 = Data transmission/reception begins during the same serial clock cycle as the frame synchronization pulse 0 = Data transmission/reception begins one serial clock cycle after the frame synchronization pulse bit 4-2 Reserved: Read as ‘0’ bit 1-0 COFSM<1:0>: Frame Sync Mode bits 11 = 20-Bit AC-Link mode 10 = 16-Bit AC-Link mode 01 = I2S Frame Sync mode 00 = Multi-Channel Frame Sync mode  2009-2012 Microchip Technology Inc. DS70616G-page 431

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 24-2: DCICON2: DCI CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 r r r r BLEN<1:0> r COFSG3 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 COFSG<2:0> r WS<3:0> bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Reserved: Read as ‘0’ bit 11-10 BLEN<1:0>: Buffer Length Control bits 11 = Four data words will be buffered between interrupts 10 = Three data words will be buffered between interrupts 01 = Two data words will be buffered between interrupts 00 = One data word will be buffered between interrupts bit 9 Reserved: Read as ‘0’ bit 8-5 COFSG<3:0>: Frame Sync Generator Control bits 1111 = Data frame has 16 words • • • 0010 = Data frame has 3 words 0001 = Data frame has 2 words 0000 = Data frame has 1 word bit 4 Reserved: Read as ‘0’ bit 3-0 WS<3:0>: DCI Data Word Size bits 1111 = Data word size is 16 bits • • • 0100 = Data word size is 5 bits 0011 = Data word size is 4 bits 0010 = Invalid Selection. Do not use. Unexpected results may occur. 0001 = Invalid Selection. Do not use. Unexpected results may occur. 0000 = Invalid Selection. Do not use. Unexpected results may occur. DS70616G-page 432  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 24-3: DCICON3: DCI CONTROL REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r r BCG<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BCG<7:0> bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Reserved: Read as ‘0’ bit 11-0 BCG<11:0>: DCI Clock Generator Control bits  2009-2012 Microchip Technology Inc. DS70616G-page 433

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 24-4: DCISTAT: DCI STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 r r r r SLOT<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 r r r r ROV RFUL TUNF TMPTY bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Reserved: Read as ‘0’ bit 11-8 SLOT<3:0>: DCI Slot Status bits 1111 = Slot 15 is currently active • • • 0010 = Slot 2 is currently active 0001 = Slot 1 is currently active 0000 = Slot 0 is currently active bit 7-4 Reserved: Read as ‘0’ bit 3 ROV: Receive Overflow Status bit 1 = A receive overflow has occurred for at least one Receive register 0 = A receive overflow has not occurred bit 2 RFUL: Receive Buffer Full Status bit 1 = New data is available in the Receive registers 0 = The Receive registers have old data bit 1 TUNF: Transmit Buffer Underflow Status bit 1 = A transmit underflow has occurred for at least one Transmit register 0 = A transmit underflow has not occurred bit 0 TMPTY: Transmit Buffer Empty Status bit 1 = The Transmit registers are empty 0 = The Transmit registers are not empty DS70616G-page 434  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 R EGISTER 24-5: RSCON: DCI RECEIVE SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RSE<15:0>: Receive Slot Enable bits 1 = CSDI data is received during the individual time slot n 0 = CSDI data is ignored during the individual time slot n REGISTER 24-6: TSCON: DCI TRANSMIT SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 TSE<15:0>: Transmit Slot Enable Control bits 1 = Transmit buffer contents are sent during the individual time slot n 0 = CSDO pin is tri-stated or driven to logic ‘0’ during the individual time slot, depending on the state of the CSDOM bit  2009-2012 Microchip Technology Inc. DS70616G-page 435

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 436  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 25.0 COMPARATOR MODULE The comparator module provides three comparators that can be configured in different ways. As shown in Note1: This data sheet summarizes the features Figure25-1, individual comparator options are of the dsPIC33EPXXX(GP/MC/MU)806/ specified by the comparator module’s Special Function 810/814 and PIC24EPXXX(GP/GU)810/ Register (SFR) control bits. 814 families of devices. It is not intended These options allow users to: to be a comprehensive reference source. To complement the information in this data • Select the edge for trigger and interrupt generation sheet, refer to Section 26. “Op Amp/ • Configure the comparator voltage reference and Comparator” (DS70357) of the band gap “dsPIC33E/PIC24E Family Reference • Configure output blanking and masking Manual”, which is available from the The comparator operating mode is determined by the Microchip web site (www.microchip.com). input selections (i.e., whether the input voltage is 2: Some registers and associated bits compared to a second input voltage or to an internal described in this section may not be voltage reference). available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 25-1: COMPARATOR I/O OPERATING MODES CREF CxIN1+(1) 0 CVREFIN 1 VIN+ + Blanking Digital CMPx(1) Function Filter CxIN2-(1) 00 VIN- – (see Figure25-3) (see Figure25-4) CxOUT(1) Output Data/Control CxIN1-(1) 01 CxIN3-(1) 10 11 CCH<1:0> Comparator Voltage 2.20V 00 Reference (see Figure25-2) CVREF 0.60V 01 IVREF 0.20V 10 VREF+ 11 VREF+ VREF- AVDD AVSS BGSEL<1:0> Note 1: An ‘x’ is a pin, bit or register name and denotes Comparator 1, 2 or 3.  2009-2012 Microchip Technology Inc. DS70616G-page 437

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 25-2: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREFSEL CVRSS = 1 VREF+ CVRSRC CVRCON<3:0> 3210 RRRR AVDD CVRSS = 0 8R CVCVCVCV CVREFIN R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R CVRCON<CVROE> R R CVRR 8R CVRSS = 1 VREF– AVSS CVRSS = 0 FIGURE 25-3: USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM SELSRCA<3:0> (CMxMSKSRC<3:0>) Comparator Output To Digital BSlaignnkainlsg MUX A MAI MAI “AND-OR” Function BlLaongkiicng Filter MBI ANDI AND SELSRCB<3:0> MCI (CMxMSKSRC<7:4) MAI HLMS (CMxMSKCON<15) BSlaignnkainlsg X B MBI MBI OR MASK U M MCI SELSRCC<3:0> (CMxMSKSRC<11:8) CMxMSKCON C Blanking X MCI Signals U M DS70616G-page 438  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 25-4: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM TxCLK(1,2) SYNCOx(3) FP(4) FOSC(4)  CFDIV CFSEL<2:0> CFLTREN Digital Filter CXOUT Note 1: See the Type C Timer Block Diagram (Figure13-2). 2: See the Type B Timer Block Diagram (Figure13-1). 3: See the PWM Module Register Interconnect Diagram (Figure16-2). 4: See the Oscillator System Diagram (Figure9-1). 25.1 Comparator Resources 25.1.1 KEY RESOURCES Many useful resources related to the Comparator are • Section 26. “Op Amp/Comparator” (DS70357) provided on the main product page of the Microchip in the “dsPIC33E/PIC24E Family Reference web site for the devices listed in this data sheet. This Manual” product page, which can be accessed using this link, • Code Samples contains the latest updates and additional information. • Application Notes Note: In the event you are not able to access the • Software Libraries product page using the link above, enter • Webinars this URL in your browser: • All related “dsPIC33E/PIC24E Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en554310 • Development Tools  2009-2012 Microchip Technology Inc. DS70616G-page 439

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 25.2 Comparator Control Registers REGISTER 25-1: CMSTAT: COMPARATOR STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 CMSIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMSIDL: Comparator Stop in Idle Mode bit 1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit 1 = Comparator event occurred 0 = Comparator event did not occur bit 9 C2EVT: Comparator 2 Event Status bit 1 = Comparator event occurred 0 = Comparator event did not occur bit 8 C1EVT: Comparator 1 Event Status bit 1 = Comparator event occurred 0 = Comparator event did not occur bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 1 C2OUT: Comparator 2 Output Status bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 0 C1OUT: Comparator 1 Output Status bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- DS70616G-page 440  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 CON COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL<1:0> — CREF — — CCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event according to EVPOL<1:0> settings occurred; disables future triggers and interrupts until the bit is cleared 0 = Comparator event did not occur bit 8 COUT: Comparator Output bit When CPOL = 0 (non-inverted polarity): 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1 (inverted polarity): 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/Event/Interrupt generated on any change of the comparator output (while CEVT=0) 10 = Trigger/Event/Interrupt generated only on high-to-low transition of the polarity selected comparator output (while CEVT=0) If CPOL = 1 (inverted polarity): Low-to-high transition of the comparator output. If CPOL = 0 (non-inverted polarity): High-to-low transition of the comparator output. 01 = Trigger/Event/Interrupt generated only on low-to-high transition of the polarity selected comparator output (while CEVT=0) If CPOL = 1 (inverted polarity): High-to-low transition of the comparator output. If CPOL = 0 (non-inverted polarity): Low-to-high transition of the comparator output. 00 = Trigger/Event/Interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’  2009-2012 Microchip Technology Inc. DS70616G-page 441

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (CONTINUED) bit 4 CREF: Comparator Reference Select bit (VIN+ input) 1 = VIN+ input connects to internal CVREFIN voltage 0 = VIN+ input connects to CxIN1+ pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = VIN- input of comparator connects to IVREF 10 = VIN- input of comparator connects to CXIN3- pin 01 = VIN- input of comparator connects to CXIN1- pin 00 = VIN- input of comparator connects to CXIN2- pin DS70616G-page 442  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 25-3: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0 — — — — SELSRCC<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SELSRCB<3:0> SELSRCA<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SELSRCC<3:0>: Mask C Input Select bits 1111 = FLT4 1110 = FLT2 1101 = PWM7H 1100 = PWM7L 1011 = PWM6H 1010 = PWM6L 1001 = PWM5H 1000 = PWM5L 0111 = PWM4H 0110 = PWM4L 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L bit 7-4 SELSRCB<3:0>: Mask B Input Select bits 1111 = FLT4 1110 = FLT2 1101 = PWM7H 1100 = PWM7L 1011 = PWM6H 1010 = PWM6L 1001 = PWM5H 1000 = PWM5L 0111 = PWM4H 0110 = PWM4L 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L  2009-2012 Microchip Technology Inc. DS70616G-page 443

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 25-3: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT CONTROL REGISTER (CONTINUED) bit 3-0 SELSRCA<3:0>: Mask A Input Select bits 1111 = FLT4 1110 = FLT2 1101 = PWM7H 1100 = PWM7L 1011 = PWM6H 1010 = PWM6L 1001 = PWM5H 1000 = PWM5L 0111 = PWM4H 0110 = PWM4L 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L DS70616G-page 444  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 25-4: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLMS: High or Low-Level Masking Select bits 1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating 0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating bit 14 Unimplemented: Read as '0' bit 13 OCEN: OR Gate C Input Enable bit 1 = MCI is connected to OR gate 0 = MCI is not connected to OR gate bit 12 OCNEN: OR Gate C Input Inverted Enable bit 1 = Inverted MCI is connected to OR gate 0 = Inverted MCI is not connected to OR gate bit 11 OBEN: OR Gate B Input Enable bit 1 = MBI is connected to OR gate 0 = MBI is not connected to OR gate bit 10 OBNEN: OR Gate B Input Inverted Enable bit 1 = Inverted MBI is connected to OR gate 0 = Inverted MBI is not connected to OR gate bit 9 OAEN: OR Gate A Input Enable bit 1 = MAI is connected to OR gate 0 = MAI is not connected to OR gate bit 8 OANEN: OR Gate A Input Inverted Enable bit 1 = Inverted MAI is connected to OR gate 0 = Inverted MAI is not connected to OR gate bit 7 NAGS: AND Gate Output Inverted Enable bit 1 = Inverted ANDI is connected to OR gate 0 = Inverted ANDI is not connected to OR gate bit 6 PAGS: AND Gate Output Enable bit 1 = ANDI is connected to OR gate 0 = ANDI is not connected to OR gate bit 5 ACEN: AND Gate C Input Enable bit 1 = MCI is connected to AND gate 0 = MCI is not connected to AND gate bit 4 ACNEN: AND Gate C Input Inverted Enable bit 1 = Inverted MCI is connected to AND gate 0 = Inverted MCI is not connected to AND gate  2009-2012 Microchip Technology Inc. DS70616G-page 445

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 25-4: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER (CONTINUED) bit 3 ABEN: AND Gate B Input Enable bit 1 = MBI is connected to AND gate 0 = MBI is not connected to AND gate bit 2 ABNEN: AND Gate B Input Inverted Enable bit 1 = Inverted MBI is connected to AND gate 0 = Inverted MBI is not connected to AND gate bit 1 AAEN: AND Gate A Input Enable bit 1 = MAI is connected to AND gate 0 = MAI is not connected to AND gate bit 0 AANEN: AND Gate A Input Inverted Enable bit 1 = Inverted MAI is connected to AND gate 0 = Inverted MAI is not connected to AND gate DS70616G-page 446  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 25-5: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 I-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CFSEL<2:0> CFLTREN CFDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits 111 = T5CLK(1) 110 = T4CLK(2) 101 = T3CLK(1) 100 = T2CLK(2) 011 = SYNCO2(3) 010 = SYNCO1(3) 001 = FOSC(4) 000 = FP(4) bit 3 CFLTREN: Comparator Filter Enable bit 1 = Digital filter is enabled 0 = Digital filter is disabled bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits 111 = Clock Divide 1:128 110 = Clock Divide 1:64 101 = Clock Divide 1:32 100 = Clock Divide 1:16 011 = Clock Divide 1:8 010 = Clock Divide 1:4 001 = Clock Divide 1:2 000 = Clock Divide 1:1 Note 1: See the Type C Timer Block Diagram (Figure13-2). 2: See the Type B Timer Block Diagram (Figure13-1). 3: See the PWM Module Register Interconnect Diagram (Figure16-2). 4: See the Oscillator System Diagram (Figure9-1).  2009-2012 Microchip Technology Inc. DS70616G-page 447

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 25-6: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — VREFSEL BGSEL<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 VREFSEL: Voltage Reference Select bit 1 = CVREFIN = VREF+ 0 = CVREFIN is generated by the resistor network bit 9-8 BGSEL<1:0>: Band Gap Reference Source Select bits 11 = IVREF = VREF+(2) 10 = IVREF = 0.20V (nominal) 01 = IVREF = 0.60V (nominal) 00 = IVREF = 2.20V (nominal) bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = Comparator voltage reference circuit powered on 0 = Comparator voltage reference circuit powered down bit 6 CVROE: Comparator Voltage Reference Output Enable bit(1) 1 = Voltage level is output on CVREF pin 0 = Voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator Voltage Reference Range Selection bit 1 = CVRSRC/24 step-size 0 = CVRSRC/32 step-size bit 4 CVRSS: Comparator Voltage Reference Source Selection bit 1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-)(2) 0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0> Comparator Voltage Reference Value Selection 0  CVR<3:0>  15 bits When CVRR = 1: CVREFIN = (CVR<3:0>/24) • (CVRSRC) When CVRR = 0: CVREFIN = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC) Note 1: CVROE overrides the TRIS bit setting. 2: Selecting BGSEL<1:0> = 11 and CVRSS = 1 is invalid and will produce unpredictable results. DS70616G-page 448  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 26.0 REAL-TIME CLOCK AND Some of the key features of this module are: CALENDAR (RTCC) • Time: Hours, Minutes and Seconds • 24-Hour Format (military time) Note1: This data sheet summarizes the features • Calendar: Weekday, Date, Month and Year of the dsPIC33EPXXX(GP/MC/MU)806/ • Alarm Configurable 810/814 and PIC24EPXXX(GP/GU)810/ 814 families of devices. It is not intended • Year Range: 2000 to 2099 to be a comprehensive reference source. • Leap Year Correction To complement the information in this • BCD Format for Compact Firmware data sheet, refer to Section 29. “Real- • Optimized for Low-Power Operation Time Clock and Calendar (RTCC)” • User Calibration with Auto-Adjust (DS70584) of the “dsPIC33E/PIC24E • Calibration Range: ±2.64 Seconds Error per Month Family Reference Manual”, which is available from the Microchip web site • Requirements: External 32.768 kHz Clock Crystal (www.microchip.com). • Alarm Pulse or Seconds Clock Output on RTCC Pin 2: Some registers and associated bits The RTCC module is intended for applications where described in this section may not be accurate time must be maintained for extended periods available on all devices. Refer to with minimum to no intervention from the CPU. The Section4.0 “Memory Organization” in RTCC module is optimized for low-power usage to pro- this data sheet for device-specific register vide extended battery lifetime while keeping track of and bit information. time. This chapter discusses the Real-Time Clock and The RTCC module is a 100-year clock and calendar Calendar (RTCC) module and its operation. with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. The hours are available in 24-hour (military time) format. The clock provides a granularity of one second with half-second visibility to the user.  2009-2012 Microchip Technology Inc. DS70616G-page 449

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 26-1: RTCC BLOCK DIAGRAM dsPIC33E/PIC24E RTCPTR<1:0> RTCC Timer CAL<7:0> — YEAR 11 SOSCO 32.768 kHz 1Hz MONTH DATE 10 Prescaler Oscillator RTCVAL SOSCI WEEKDAY HOUR 01 MINUTES SECONDS 00 RTCOE RTCC Pin 1 0 Toggle RTSECSEL Set RTCIF Flag ALRMPTR<1:0> RTCC Alarm MONTH DATE 10 WEEKDAY HOUR 01 ALRMVAL MINUTES SECONDS 00 DS70616G-page 450  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 26.1 Writing to the RTCC Timer 26.2 RTCC Resources Note: To allow the RTCC module to be clocked by Many useful resources related to RTCC are provided the secondary crystal oscillator, the Sec- on the main product page of the Microchip web site for ondary Oscillator Enable (LPOSCEN) bit in the devices listed in this data sheet. This product page, the Oscillator Control (OSCCON<1>) regis- which can be accessed using this link, contains the ter must be set. For further details, refer to latest updates and additional information. Section7.“Oscillator” (DS70580) in the Note: In the event you are not able to access the “dsPIC33E/PIC24E Family Reference product page using the link above, enter Manual”. this URL in your browser: http://www.microchip.com/wwwproducts/ The user application can configure the time and Devices.aspx?dDocName=en554310 calendar by writing the desired seconds, minutes, hours, weekday, date, month and year to the RTCC 26.2.1 KEY RESOURCES registers. Under normal operation, writes to the RTCC Timer registers are not allowed. Attempted writes will • Section 29. “Real-Time Clock and Calendar appear to execute normally, but the contents of the (RTCC)” (DS70584) in the “dsPIC33E/PIC24E registers will remain unchanged. To write to the RTCC Family Reference Manual” register, the RTCWREN bit (RCFGCAL<13>) must be • Code Samples set. Setting the RTCWREN bit allows writes to the • Application Notes RTCC registers. Conversely, clearing the RTCWREN • Software Libraries bit prevents writes. • Webinars To set the RTCWREN bit, the following procedure must • All related “dsPIC33E/PIC24E Family Reference be executed. The RTCWREN bit can be cleared at any Manual” Sections time: • Development Tools 1. Write 0x55 to NVMKEY. 2. Write 0xAA to NVMKEY. 3. Set the RTCWREN bit using a single-cycle instruction. The RTCC module is enabled by setting the RTCEN bit (RCFGCAL<15>). To set or clear the RTCEN bit, the RTCWREN bit (RCFGCAL<13>) must be set. If the entire clock (hours, minutes and seconds) needs to be corrected, it is recommended that the RTCC module should be disabled to avoid coincidental write operation when the timer increments. Therefore, it stops the clock from counting while writing to the RTCC Timer register.  2009-2012 Microchip Technology Inc. DS70616G-page 451

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 26.3 RTCC Registers REGISTER 26-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVAL register can be written to by the user application 0 = RTCVAL register is locked out from being written to by the user application bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = A rollover is about to occur in 32 clock edges (approximately 1 ms) 0 = A rollover will not occur bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled bit 9-8 RTCPTR<1:0>: RTCC Value Register Pointer bits Points to the corresponding RTCC Value register when reading the RTCVAL register; the RTCPTR<1:0> value decrements on every access of the RTCVAL register until it reaches ‘00’. Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only. It is cleared when the lower half of the MINSEC register is written. DS70616G-page 452  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 26-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL<7:0>: RTCC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTCC clock pulses every one minute • • • 00000001 = Minimum positive adjustment; adds four RTCC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts four RTCC clock pulses every one minute • • • 10000000 = Maximum negative adjustment; subtracts 512 RTCC clock pulses every one minute Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only. It is cleared when the lower half of the MINSEC register is written.  2009-2012 Microchip Technology Inc. DS70616G-page 453

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 26-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 Not used by the RTCC module. Note 1: To enable the actual RTCC output, the RTCOE bit (RCFGCAL<10>) must be set. DS70616G-page 454  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 26-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0>=0x00 and CHIME=0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 0x00 to 0xFF 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 0x00 bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits 0000 =Every half second 0001 =Every second 0010 =Every 10 seconds 0011 =Every minute 0100 =Every 10 minutes 0101 =Every hour 0110 =Once a day 0111 =Once a week 1000 =Once a month 1001 =Once a year (except when configured for February 29th, once every 4 years) 101x =Reserved – do not use 11xx =Reserved – do not use bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVAL register. The ALRMPTR<1:0> value decrements on every read or write of ALRMVAL until it reaches ‘00’. bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 =Alarm will repeat 255 more times • • • 00000000 =Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to 0xFF unless CHIME=1.  2009-2012 Microchip Technology Inc. DS70616G-page 455

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 26-4: RTCVAL (WHEN RTCPTR<1:0> = 11): YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN<3:0> YRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to the YEAR register is only allowed when RTCWREN=1. REGISTER 26-5: RTCVAL (WHEN RTCPTR<1:0> = 10): MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R-x R-x R-x R-x R-x — — — MTHTEN0 MTHONE<3:0> bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN<1:0> DAYONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS70616G-page 456  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 26-6: RTCVAL (WHEN RTCPTR<1:0> = 01): WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY<2:0> bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN<1:0> HRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 26-7: RTCVAL (WHEN RTCPTR<1:0> = 00): MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN<2:0> MINONE<3:0> bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN<2:0> SECONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2009-2012 Microchip Technology Inc. DS70616G-page 457

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 26-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE<3:0> bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN<1:0> DAYONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS70616G-page 458  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 26-9: ALRMVAL (WHEN ALRMPTR<1:0> = 01): ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN<1:0> HRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1.  2009-2012 Microchip Technology Inc. DS70616G-page 459

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 26-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN<2:0> MINONE<3:0> bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN<2:0> SECONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. DS70616G-page 460  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 27.0 PROGRAMMABLE CYCLIC The programmable CRC generator offers the following REDUNDANCY CHECK (CRC) features: GENERATOR • User-Programmable (up to 32nd order) Polynomial CRC Equation Note1: This data sheet summarizes the features of • Interrupt Output the dsPIC33EPXXX(GP/MC/MU)806/810/ • Data FIFO 814 and PIC24EPXXX(GP/GU)810/814 The programmable CRC generator provides a families of devices. It is not intended to be hardware implemented method of quickly generating a comprehensive reference source. To checksums for various networking and security complement the information in this data applications. It offers the following features: sheet, refer to Section 27. “Programma- ble Cyclic Redundancy Check (CRC)” • User-Programmable CRC Polynomial Equation, (DS70346) of the “dsPIC33E/PIC24E up to 32 bits Family Reference Manual”, which is • Programmable Shift Direction (little or big-endian) available from the Microchip web site • Independent Data and Polynomial Lengths (www.microchip.com). • Configurable Interrupt Output 2: Some registers and associated bits • Data FIFO described in this section may not be available A simplified block diagram of the CRC generator is on all devices. Refer to Section4.0 “Mem- shown in Figure27-1. A simple version of the CRC shift ory Organization” in this data sheet for engine is shown in Figure27-2. device-specific register and bit information. FIGURE 27-1: PROGRAMMABLE CRC BLOCK DIAGRAM CRCDATH CRCDATL Variable FIFO FIFO Empty Event (4x32, 8x16 or 16x8) CRCISEL 2 * FP Shift Clock Shift Buffer 1 Set CRCIF 0 0 1 LENDIAN Shift Complete Event CRC Shift Engine CRCWDATH CRCWDATL FIGURE 27-2: CRC SHIFT ENGINE DETAIL CRCWDATH CRCWDATL Read/Write Bus X(1)(1) X(2)(1) X(n)(1) Shift Buffer Data Bit 0 Bit 1 Bit 2 Bit n(2) Note 1: Each XOR stage of the shift engine is programmable. See text for details. 2: Polynomial Length n is determined by ([PLEN<4:0>] + 1).  2009-2012 Microchip Technology Inc. DS70616G-page 461

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 27.1 Overview TABLE 27-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIAL The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Bit Values Polynomial length, which reflects the highest exponent CRC in the equation, is selected by the PLEN<4:0> bits Control Bits 16-Bit 32-Bit Polynomial Polynomial (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which PLEN<4:0> 01111 11111 exponent terms are included in the equation. Setting a 0000 0000 0000 0100 X<31:16> particular bit includes that exponent term in the 0000 000x 1100 0001 equation; functionally, this includes an XOR operation 0001 0000 0001 1101 on the corresponding bit in the CRC engine. Clearing X<15:0> 0010 000x 1011 011x the bit disables the XOR. For example, consider two CRC polynomials, one a 27.2 Programmable CRC Resources 16-bit equation and the other a 32-bit equation: Many useful resources related to Programmable CRC x16 + x12 + x5 + 1 are provided on the main product page of the Microchip and web site for the devices listed in this data sheet. This x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 product page, which can be accessed using this link, + x5 + x4 + x2 + x + 1 contains the latest updates and additional information. To program these polynomials into the CRC generator, Note: In the event you are not able to access the set the register bits as shown in Table27-1. product page using the link above, enter this URL in your browser: Note that the appropriate positions are set to ‘1’ to indicate http://www.microchip.com/wwwproducts/ that they are used in the equation (for example, X26 and Devices.aspx?dDocName=en554310 X23). The 0 bit required by the equation is always XORed; thus, X0 is a don’t care. For a polynomial of length, N, it is 27.2.1 KEY RESOURCES assumed that the Nth bit will always be used, regardless of the bit setting. Therefore, for a polynomial length of 32, • Section 27. “Programmable Cyclic Redundancy there is no 32nd bit in the CRCxOR register. Check (CRC)” (DS70346) in the “dsPIC33E/ PIC24E Family Reference Manual” • Code Samples • Application Notes • Software Libraries • Webinars • All related “dsPIC33E/PIC24E Family Reference Manual” Sections • Development Tools DS70616G-page 462  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 27.3 Programmable CRC Registers REGISTER 27-1: CRCCON1: CRC CONTROL REGISTER1 R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 CRCEN — CSIDL VWORD<4:0> bit 15 bit 8 R-0 R-1 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CRCEN: CRC Enable bit 1 = CRC module is enabled 0 = CRC module is disabled, all state machines, pointers and CRCWDAT/CRCDAT are reset; other SFRs are not reset bit 14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<4:0> > 7 or 16 when PLEN<4:0> 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; final word of data is still shifting through CRC 0 = Interrupt on shift is complete and CRCWDAT results are ready bit 4 CRCGO: Start CRC bit 1 = Starts CRC serial shifter 0 = CRC serial shifter is turned off bit 3 LENDIAN: Data Word Little-Endian Configuration bit 1 = Data word is shifted into the CRC starting with the LSb (little endian) 0 = Data word is shifted into the CRC starting with the MSb (big endian) bit 2-0 Unimplemented: Read as ‘0’  2009-2012 Microchip Technology Inc. DS70616G-page 463

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 27-2: CRCCON2: CRC CONTROL REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH<4:0>: Data Width Select bits These bits set the width of the data word (DWIDTH<4:0> + 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN<4:0>: Polynomial Length Select bits These bits set the length of the polynomial (Polynomial Length = PLEN<4:0> + 1). DS70616G-page 464  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 27-3: CRCXORH: CRC XOR POLYNOMIAL HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 X<31:16>: XOR of Polynomial Term Xn Enable bits REGISTER 27-4: CRCXORL: CRC XOR POLYNOMIAL LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X<7:1> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’  2009-2012 Microchip Technology Inc. DS70616G-page 465

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 466  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 28.0 PARALLEL MASTER PORT The Parallel Master Port (PMP) module is a parallel (PMP) 8-bit I/O module, specifically designed to communi- cate with a wide variety of parallel devices, such as Note1: This data sheet summarizes the features communication peripherals, LCDs, external memory of the dsPIC33EPXXX(GP/MC/MU)806/ devices and microcontrollers. Because the interface 810/814 and PIC24EPXXX(GP/GU)810/ to parallel peripherals varies significantly, the PMP is 814 families of devices. It is not intended highly configurable. to be a comprehensive reference source. Key features of the PMP module include: To complement the information in this data • Eight Data Lines sheet, refer to Section 28. “Parallel Mas- • Up to 16 Programmable Address Lines ter Port (PMP)” (DS70576) of the “dsPIC33E/PIC24E Family Reference • Up to 2 Chip Select Lines Manual”, which is available from the • Programmable Strobe Options: Microchip web site (www.microchip.com). - Individual read and write strobes, or 2: Some registers and associated bits - Read/Write strobe with enable strobe described in this section may not be • Address Auto-Increment/Auto-Decrement available on all devices. Refer to • Programmable Address/Data Multiplexing Section4.0 “Memory Organization” in • Programmable Polarity on Control Signals this data sheet for device-specific register • Legacy Parallel Slave Port (PSP) Support and bit information. • Enhanced Parallel Slave Support: - Address support - 4-byte deep auto-incrementing buffer • Programmable Wait States FIGURE 28-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES dsPIC33E/PIC24E PMA<0> PMALL Up to 16-Bit Address EEPROM PMA<1> PMALH Address Bus PMA<13:2> Data Bus Control Lines PMA<14> PMCS1 Parallel Master Port PMA<15> PMCS2 PMBE FIFO PMRD Microcontroller LCD PMRD/PMWR Buffer PMWR PMENB PMD<7:0> PMA<7:0> PMA<15:8> 8-Bit Data (with or without multiplexed addressing)  2009-2012 Microchip Technology Inc. DS70616G-page 467

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 28.1 PMP Resources 28.1.1 KEY RESOURCES Many useful resources related to PMP are provided on • Section 28. “Parallel Master Port (PMP)” the main product page of the Microchip web site for the (DS70576) in the “dsPIC33E/PIC24E Family devices listed in this data sheet. This product page, Reference Manual” which can be accessed using this link, contains the • Code Samples latest updates and additional information. • Application Notes Note: In the event you are not able to access the • Software Libraries product page using the link above, enter • Webinars this URL in your browser: • All related “dsPIC33E/PIC24E Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en554310 • Development Tools DS70616G-page 468  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 28.2 PMP Control Registers REGISTER 28-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX<1:0> PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 CSF<1:0> ALP CS2P CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = PMP module is enabled 0 = PMP module is disabled, no off-chip access is performed bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: PMP Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower eight bits of address are multiplexed on PMD<7:0> pins, upper eight bits are on PMA<15:8> 00 = Address and data appear on separate pins bit 10 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port is enabled 0 = PMBE port is disabled bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled bit 7-6 CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = PMCS1 and PMCS2 function as Chip Select 01 = PMCS2 functions as Chip Select, PMCS1 functions as Address Bit 14 00 = PMCS1 and PMCS2 function as Address Bits 15 and 14 bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 CS2P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) Note 1: These bits have no effect when their corresponding pins are used as address lines. 2: PMCS1 applies to Master mode and PMCS applies to Slave mode.  2009-2012 Microchip Technology Inc. DS70616G-page 469

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 28-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER (CONTINUED) bit 3 CS1P: Chip Select 0 Polarity bit(1) 1 = Active-high (PMCS1/PMCS)(2) 0 = Active-low (PMCS1/PMCS) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master Mode 2 (PMMODE<9:8>=00, 01, 10): 1 = Write strobe is active-high (PMWR) 0 = Write strobe is active-low (PMWR) For Master Mode 1 (PMMODE<9:8>=11): 1 = Enables strobe active-high (PMENB) 0 = Enables strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave Modes and Master Mode 2 (PMMODE<9:8>=00, 01, 10): 1 = Read strobe is active-high (PMRD) 0 = Read strobe is active-low (PMRD) For Master Mode 1 (PMMODE<9:8> = 11): 1 = Enables strobe active-high (PMRD/PMWR) 0 = Enables strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. 2: PMCS1 applies to Master mode and PMCS applies to Slave mode. DS70616G-page 470  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 28-2: PMMODE: PARALLEL MASTER PORT MODE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB<1:0>(1,2,3) WAITM<3:0> WAITE<1:0>(1,2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read/write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt is generated at the end of the read/write cycle 00 = No Interrupt is generated bit 12-11 INCM<1:0>: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrements ADDR by 1 every read/write cycle 01 = Increments ADDR by 1 every read/write cycle 00 = No increment or decrement of address bit 10 MODE16: Parallel Master Port Mode 8/16-Bit Mode bit 1 = 16-bit mode: data register is 16 bits, a read/write to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bits, a read/write to the data register invokes one 8-bit transfer bit 9-8 MODE<1:0>: Parallel Master Port Mode Select bits 11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>) 10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>) 01 = Enhanced PSP, controls signals (PMRD, PMWR, PMCSx, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, controls signals (PMRD, PMWR, PMCSx and PMD<7:0>) bit 7-6 WAITB<1:0>: Data Setup to Read/Write/Address Phase Wait State Configuration bits(1,2,3) 11 = Data wait of 4 TP (demultiplexed/multiplexed); address phase of 4 TP (multiplexed) 10 = Data wait of 3 TP (demultiplexed/multiplexed); address phase of 3 TP (multiplexed) 01 = Data wait of 2 TP (demultiplexed/multiplexed); address phase of 2 TP (multiplexed) 00 = Data wait of 1 TP (demultiplexed/multiplexed); address phase of 1 TP (multiplexed) bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TP • • • 0001 = Wait of additional 1 TP 0000 = No additional Wait cycles (operation forced into one TP) Note 1: The applied Wait state depends on whether data and address are multiplexed or demultiplexed. See Section 28.4.1.8.“Wait States” in Section 28. “Parallel Master Port (PMP)” (DS70576) in the “dsPIC33E/PIC24E Family Reference Manual” for more information. 2: WAITB<1:0> and WAITE<1:0> bits are ignored whenever WAITM<3:0> = 0000. 3: TP = 1/FP.  2009-2012 Microchip Technology Inc. DS70616G-page 471

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 28-2: PMMODE: PARALLEL MASTER PORT MODE REGISTER (CONTINUED) bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1,2,3) 11 = Wait of 4 TP 10 = Wait of 3 TP 01 = Wait of 2 TP 00 = Wait of 1 TP Note 1: The applied Wait state depends on whether data and address are multiplexed or demultiplexed. See Section 28.4.1.8.“Wait States” in Section 28. “Parallel Master Port (PMP)” (DS70576) in the “dsPIC33E/PIC24E Family Reference Manual” for more information. 2: WAITB<1:0> and WAITE<1:0> bits are ignored whenever WAITM<3:0> = 0000. 3: TP = 1/FP. DS70616G-page 472  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 28-3: PMADDR: PARALLEL MASTER PORT ADDRESS REGISTER (MASTER MODES ONLY)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 CS1 ADDR<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CS2: Chip Select 2 bit If PMCON<7:6> = 10 or 01: 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive If PMCON<7:6> = 11 or 00: Bit functions as ADDR<15>. bit 14 CS1: Chip Select 1 bit If PMCON<7:6> = 10: 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive If PMCON<7:6> = 11 or 0x: Bit functions as ADDR<14>. bit 13-0 ADDR<13:0>: Destination Address bits Note 1: In Enhanced Slave mode, PMADDR functions as PMDOUT1, one of the two Data Buffer registers.  2009-2012 Microchip Technology Inc. DS70616G-page 473

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 28-4: PMAEN: PARALLEL MASTER PORT ADDRESS ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN15: PMCS2 Strobe Enable bit 1 = PMA15 functions as either PMA<15> or PMCS2 0 = PMA15 functions as port I/O bit 14 PTEN14: PMCS1 Strobe Enable bit 1 = PMA14 functions as either PMA<14> or PMCS1 0 = PMA14 functions as port I/O bit 13-2 PTEN<13:2>: PMP Address Port Enable bits 1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 function as port I/O DS70616G-page 474  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 28-5: PMSTAT: PARALLEL MASTER PORT STATUS REGISTER (SLAVE MODE ONLY) R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable Input Buffer registers are full 0 = Some or all of the Writable Input Buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full Input Byte register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IB3F:IB0F: Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading the buffer will clear this bit) 0 = Input buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable Output Buffer registers are empty 0 = Some or all of the readable Output Buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted  2009-2012 Microchip Technology Inc. DS70616G-page 475

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 REGISTER 28-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 Not used by the PMP module. bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers DS70616G-page 476  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 29.0 SPECIAL FEATURES 29.1 Configuration Bits Note: This data sheet summarizes the features of The dsPIC33EPXXX(GP/MC/MU)806/810/814 and the dsPIC33EPXXX(GP/MC/MU)806/810/ PIC24EPXXX(GP/GU)810/814 devices provide 814 and PIC24EPXXX(GP/GU)810/814 nonvolatile memory implementation for device Configu- families of devices. It is not intended to be a ration bits. Refer to Section 30. “Device Configuration” comprehensive reference source. To (DS70618) of the “dsPIC33E/PIC24E Family Reference complement the information in this data Manual” for more information on this implementation. sheet, refer to the related section of the The Configuration bits can be programmed (read as “dsPIC33E/PIC24E Family Reference ‘0’), or left unprogrammed (read as ‘1’), to select Manual”, which is available from the various device configurations. These bits are mapped, Microchip web site (www.microchip.com). starting at program memory location, 0xF80000. dsPIC33EPXXX(GP/MC/MU)806/810/814 and The individual Configuration bit descriptions for the PIC24EPXXX(GP/GU)810/814 devices include Configuration registers are shown in Table29-2. several features intended to maximize application Note that address, 0xF80000, is beyond the user flexibility and reliability, and minimize cost through program memory space. It belongs to the configuration elimination of external components. These are: memory space (0x800000-0xFFFFFF), which can only • Flexible Configuration be accessed using table reads and table writes. • Watchdog Timer (WDT) To prevent inadvertent configuration changes during • Code Protection and CodeGuard™ Security code execution, some programmable Configuration bits are write-once. For such bits, changing a device • JTAG Boundary Scan Interface configuration requires that the device be reset. For • In-Circuit Serial Programming™ (ICSP™) other Configuration bits, the device configuration • In-Circuit Emulation changes immediately after an RTSP operation. The RTSP effect column in Table29-2 indicates when the device configuration changes after a bit is modified using RTSP. The device Configuration register map is shown in Table29-1. TABLE 29-1: DEVICE CONFIGURATION REGISTER MAP Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xF80000 Reserved — — — — — — — — 0xF80002 Reserved — — — — — — — — 0xF80004 FGS — — GSSK<1:0> — — GSS GWRP 0xF80006 FOSCSEL IESO — — — — FNOSC<2:0> 0xF80008 FOSC FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0> 0xF8000A FWDT FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0> 0xF8000C FPOR — — ALTI2C2 ALTI2C1 BOREN(2) FPWRT<2:0> 0xF8000E FICD Reserved(1) JTAGEN Reserved(1) — RSTPRI ICS<1:0> 0xF80010 FAS — — APLK<1:0> — — APL AWRP 0xF80012 FUID0 User Unit ID Byte 0 Legend: — = unimplemented bit, read as ‘0’ Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’. 2: BOR should always be enabled for proper operation (BOREN = 1).  2009-2012 Microchip Technology Inc. DS70616G-page 477

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 29-2: CONFIGURATION BITS DESCRIPTION Bit Field Register RTSP Effect Description GSSK<1:0> FGS Immediate General Segment Key bits These bits must be set to ‘00’ if GWRP = 1 and GSS = 1. These bits must be set to ‘11’ for any other value of the GWRP and GSS bits. Any mismatch between either the GWRP or GSS bits, and the GSSK bits (as described above), will result in code protection becoming enabled for the General Segment. A Flash bulk erase will be required to unlock the device. GSS FGS Immediate General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = User program memory is code-protected GWRP FGS Immediate General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO FOSCSEL Immediate Two-Speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC<2:0> FOSCSEL If clock switch Initial Oscillator Source Selection bits is enabled, the 111 = Internal Fast RC (FRC) Oscillator with Postscaler RTSP effect is 110 = Internal Fast RC (FRC) Oscillator with Divide-by-16 on any device 101 = LPRC Oscillator Reset; 100 = Secondary (LP) Oscillator otherwise, 011 = Primary (XT, HS, EC) Oscillator with PLL immediate 010 = Primary (XT, HS, EC) Oscillator 001 = Internal Fast RC (FRC) Oscillator with PLL 000 = FRC Oscillator FCKSM<1:0> FOSC Immediate Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY FOSC Immediate Peripheral Pin Select Configuration bit 1 = Allows only one reconfiguration 0 = Allows multiple reconfigurations OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is the clock output 0 = OSC2 is the general purpose digital I/O pin POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits 11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer is always enabled (LPRC Oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register has no effect.) 0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register.) Note 1: BOR should always be enabled for proper operation (BOREN = 1). 2: This register can only be modified when code protection and write protection are disabled for both the General and Auxiliary Segments (APL = 1, AWRP = 1, APLK = 0, GSS = 1, GWRP = 1 and GSSK = 0). DS70616G-page 478  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 29-2: CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description WINDIS FWDT Immediate Watchdog Timer Window Enable bit 1 = Watchdog Timer is in Non-Window mode 0 = Watchdog Timer is in Window mode PLLKEN FWDT Immediate PLL Lock Wait Enable bit 1 = Clock switches to the PLL source will wait until the PLL lock signal is valid 0 = Clock switch will not wait for PLL lock WDTPRE FWDT Immediate Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 APLK<1:0> FAS(2) Immediate Auxiliary Segment Key bits These bits must be set to ‘00’ if AWRP = 1 and APL = 1. These bits must be set to ‘11’ for any other value of the AWRP and APL bits. Any mismatch between either the AWRP or APL bits and the APLK bits (as described above), will result in code protection becoming enabled for the Auxiliary Segment. A Flash bulk erase will be required to unlock the device. APL FAS(2) Immediate Auxiliary Segment Code-Protect bit 1 = Auxiliary program memory is not code-protected 0 = Auxiliary program memory is code-protected AWRP FAS(2) Immediate Auxiliary Segment Write-Protect bit 1 = Auxiliary program memory is not write-protected 0 = Auxiliary program memory is write-protected WDTPOST<3:0> FWDT Immediate Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 FPWRT<2:0> FPOR Immediate Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled BOREN(1) FPOR Immediate Brown-out Reset (BOR) Detection Enable bit 1 = BOR is enabled 0 = BOR is disabled ALTI2C2 FPOR Immediate Alternate I2C™ pins for I2C2 bit 1 = I2C2 is mapped to the SDA2/SCL2 pins 0 = I2C2 is mapped to the ASDA2/ASCL2 pins ALTI2C1 FPOR Immediate Alternate I2C pins for I2C1 bit 1 = I2C1 is mapped to the SDA1/SCL1 pins 0 = I2C1 is mapped to the ASDA1/ASCL1 pins Note 1: BOR should always be enabled for proper operation (BOREN = 1). 2: This register can only be modified when code protection and write protection are disabled for both the General and Auxiliary Segments (APL = 1, AWRP = 1, APLK = 0, GSS = 1, GWRP = 1 and GSSK = 0).  2009-2012 Microchip Technology Inc. DS70616G-page 479

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 29-2: CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description JTAGEN FICD Immediate JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled RSTPRI FICD On any Reset Target Vector Select bit device Reset 1 = Device will reset to Primary Flash Reset location 0 = Device will reset to Auxiliary Flash Reset location ICS<1:0> FICD Immediate ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use Note 1: BOR should always be enabled for proper operation (BOREN = 1). 2: This register can only be modified when code protection and write protection are disabled for both the General and Auxiliary Segments (APL = 1, AWRP = 1, APLK = 0, GSS = 1, GWRP = 1 and GSSK = 0). DS70616G-page 480  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 29.2 On-Chip Voltage Regulator 29.3 Brown-out Reset (BOR) All of the dsPIC33EPXXX(GP/MC/MU)806/810/814 The Brown-out Reset module is based on an internal and PIC24EPXXX(GP/GU)810/814 devices power voltage reference circuit that monitors the regulated their core digital logic at a nominal 1.8V. This can create supply voltage, VCAP. The main purpose of the BOR a conflict for designs that are required to operate at a module is to generate a device Reset when a brown- higher typical voltage, such as 3.3V. To simplify system out condition occurs. Brown-out conditions are design, all devices in the dsPIC33EPXXX(GP/MC/ generally caused by glitches on the AC mains (for MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 example, missing portions of the AC cycle waveform family incorporate an on-chip regulator that allows the due to bad power transmission lines, or voltage sags device to run its core logic from VDD. due to excessive current draw when a large inductive load is turned on). The regulator provides power to the core from the other VDD pins. A low-ESR (less than 1 Ohms) capacitor A BOR generates a Reset pulse, which resets the (such as tantalum or ceramic) must be connected to the device. The BOR selects the clock source based on the VCAP pin (Figure29-1). This helps to maintain the device Configuration bit values (FNOSC<2:0> and stability of the regulator. The recommended value for POSCMD<1:0>). the filter capacitor is provided in Table32-13 located in If an oscillator mode is selected, the BOR activates the Section32.0 “Electrical Characteristics”. Oscillator Start-up Timer (OST). The system clock is Note: It is important for the low-ESR capacitor to held until OST expires. If the PLL is used, the clock is be placed as close as possible to the VCAP held until the LOCK bit (OSCCON<5>) is ‘1’. pin. Concurrently, the Power-up Timer (PWRT) Time-out (TPWRT) is applied before the internal Reset is FIGURE 29-1: CONNECTIONS FOR THE released. If TPWRT = 0 and a crystal oscillator is ON-CHIP VOLTAGE being used, then a nominal delay of TFSCM is REGULATOR(1,2,3) applied. The total delay in this case is TFSCM. Refer to ParameterSY35 in Table32-22 of Section32.0 “Electrical Characteristics” for specific TFSCM 3.3V values. dsPIC33E/PIC24E The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit, continues to oper- VDD ate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. VCAP CEFC VSS Note 1: These are typical operating voltages. Refer to Table32-13 located in Section32.1 “DC Characteristics” for the full operating ranges of VDD and VCAP. 2: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. 3: Typical VCAP pin voltage is 1.8V when VDDVDDMIN.  2009-2012 Microchip Technology Inc. DS70616G-page 481

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 29.4 Watchdog Timer (WDT) 29.4.2 SLEEP AND IDLE MODES For dsPIC33EPXXX(GP/MC/MU)806/810/814 and If the WDT is enabled, it continues to run during Sleep or PIC24EPXXX(GP/GU)810/814 devices, the WDT is Idle modes. When the WDT time-out occurs, the device driven by the LPRC Oscillator. When the WDT is wakes the device and code execution continues from enabled, the clock source is also enabled. where the PWRSAV instruction was executed. The corre- sponding SLEEP or IDLE bits (RCON<3,2>) need to be 29.4.1 PRESCALER/POSTSCALER cleared in software after the device wakes up. The nominal WDT clock source from LPRC is 32kHz. 29.4.3 ENABLING WDT This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The WDT is enabled or disabled by the FWDTEN The prescaler is set by the WDTPRE Configuration bit. Configuration bit in the FWDT Configuration register. With a 32kHz input, the prescaler yields a nominal When the FWDTEN Configuration bit is set, the WDT is WDT Time-out (TWDT) period of 1ms in 5-bit mode or always enabled. 4ms in 7-bit mode. The WDT can be optionally controlled in software A variable postscaler divides down the WDT prescaler when the FWDTEN Configuration bit has been output and allows for a wide range of time-out periods. programmed to ‘0’. The WDT is enabled in software The postscaler is controlled by the WDTPOST<3:0> by setting the SWDTEN control bit (RCON<5>). The Configuration bits (FWDT<3:0>), which allow the selec- SWDTEN control bit is cleared on any device Reset. tion of 16 settings, from 1:1 to 1:32,768. Using the The software WDT option allows the user application prescaler and postscaler, time-out periods ranging from to enable the WDT for critical code segments and 1ms to 131 seconds can be achieved. disable the WDT during non-critical segments for maximum power savings. The WDT, prescaler and postscaler are reset: Note: If the WINDIS bit (FWDT<6>) is cleared, • On any device Reset the CLRWDT instruction should be executed • On the completion of a clock switch, whether by the application software only during the invoked by software (i.e., setting the OSWEN bit last 1/4 of the WDT period. This CLRWDT after changing the NOSC bits) or by hardware instruction window can be determined by (i.e., Fail-Safe Clock Monitor) using a timer. If a CLRWDT instruction is • When a PWRSAV instruction is executed executed before this window, a WDT Reset (i.e., Sleep or Idle mode is entered) occurs. • When the device exits Sleep or Idle mode to The WDT flag bit, WDTO (RCON<4>), is not automatically resume normal operation cleared following a WDT time-out. To detect subsequent • By a CLRWDT instruction during normal execution WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 29-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> SWDTEN WDT FWDTEN Wake-up RS RS 1 Prescaler Postscaler LPRC Clock (divide-by-N1) (divide-by-N2) WDT 0 Reset WINDIS WDT Window Select CLRWDT Instruction DS70616G-page 482  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 29.5 JTAG Interface Any of the three pairs of debugging clock/data pins can be used: dsPIC33EPXXX(GP/MC/MU)806/810/814 and • PGEC1 and PGED1 PIC24EPXXX(GP/GU)810/814 devices implement a JTAG interface, which supports boundary scan device • PGEC2 and PGED2 testing. Detailed information on this interface is • PGEC3 and PGED3 provided in future revisions of the document. To use the in-circuit debugger function of the device, Note: Refer to Section 24. “Programming the design must implement ICSP connections to and Diagnostics” (DS70608) of the MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In “dsPIC33E/PIC24E Family Reference addition, when the feature is enabled, some of the Manual” for further information on usage, resources are not available for general use. These configuration and operation of the JTAG resources include the first 80 bytes of data RAM and interface. two I/O pins. 29.8 Code Protection and 29.6 In-Circuit Serial Programming CodeGuard™ Security The dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 devices can be serially The dsPIC33EPXXX(GP/MC/MU)806/810/814 and programmed while in the end application circuit. This is PIC24EPXXX(GP/GU)810/814 devices offer basic done with two lines for clock and data, and three other implementation of CodeGuard Security that supports lines for power, ground and the programming only General Segment (GS) security. This feature helps sequence. Serial programming allows customers to protect individual Intellectual Property in collaborative manufacture boards with unprogrammed devices and system designs. then program the digital signal controller just before When coupled with software encryption libraries, shipping the product. Serial programming also allows CodeGuard Security can be used to securely update the most recent firmware or a custom firmware to be Flash even when multiple IPs reside on the single chip. programmed. Refer to the “dsPIC33E/PIC24E Flash The code protection features vary depending on the Programming Specification” (DS70619) for details actual dsPIC33E implemented. The following sections about In-Circuit Serial Programming (ICSP). provide an overview of these features. Any of the three pairs of programming clock/data pins The dsPIC33EPXXX(GP/MC/MU)806/810/814 and can be used: PIC24EPXXX(GP/GU)810/814 devices do not support • PGEC1 and PGED1 Boot Segment (BS), Secure Segment (SS) and RAM protection. • PGEC2 and PGED2 • PGEC3 and PGED3 Note: Refer to Section 23. “CodeGuard™ Security” (DS70634) of the “dsPIC33E/ 29.7 In-Circuit Debugger PIC24E Family Reference Manual” for further information on usage, configuration When MPLAB® ICD 3 or REAL ICE™ is selected as a and operation of CodeGuard Security. debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emula- tion/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions.  2009-2012 Microchip Technology Inc. DS70616G-page 483

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 484  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 30.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: Note: This data sheet summarizes the features of • The W register (with or without an address the dsPIC33EPXXX(GP/MC/MU)806/810/ modifier) or file register (specified by the value of 814 and PIC24EPXXX(GP/GU)810/814 ‘Ws’ or ‘f’) families of devices. It is not intended to be a • The bit in the W register or file register (specified comprehensive reference source. To by a literal value or indirectly by the contents of complement the information in this data register ‘Wb’) sheet, refer to the related section of the “dsPIC33E/PIC24E Family Reference The literal instructions that involve data movement can Manual”, which is available from the use some of the following operands: Microchip web site (www.microchip.com). • A literal value to be loaded into a W register or file register (specified by ‘k’) The dsPIC33EP instruction set is almost identical to that of the dsPIC30F and dsPIC33F. The PIC24EP • The W register or file register where the literal instruction set is almost identical to that of the PIC24F value is to be loaded (specified by ‘Wb’ or ‘f’) and PIC24H. However, literal instructions that involve arithmetic or Most instructions are a single program memory word logical operations use some of the following operands: (24 bits). Only three instructions require two program • The first source operand, which is a register ‘Wb’ memory locations. without any address modifier Each single-word instruction is a 24-bit word, divided • The second source operand, which is a literal into an 8-bit opcode, which specifies the instruction value type and one or more operands, which further specify • The destination of the result (only if not the same the operation of the instruction. as the first source operand), which is typically a The instruction set is highly orthogonal and is grouped register ‘Wd’ with or without an address modifier into five basic categories: The MAC class of DSP instructions can use some of the • Word or byte-oriented operations following operands: • Bit-oriented operations • The accumulator (A or B) to be used (required • Literal operations operand) • DSP operations • The W registers to be used as the two operands • Control operations • The X and Y address space prefetch operations • The X and Y address space prefetch destinations Table30-1 lists the general symbols used in describing the instructions. • The accumulator write-back destination The dsPIC33E instruction set summary in Table30-2 The other DSP instructions do not involve any lists all the instructions, along with the status flags multiplication and can include: affected by each instruction. • The accumulator to be used (required) Most word or byte-oriented W register instructions • The source or destination operand (designated as (including barrel shift instructions) have three Wso or Wdo, respectively) with or without an operands: address modifier • The first source operand, which is typically a • The amount of shift specified by a W register ‘Wn’ register ‘Wb’ without any address modifier or a literal value • The second source operand, which is typically a The control instructions can use some of the following register ‘Ws’ with or without an address modifier operands: • The destination of the result, which is typically a • A program memory address register ‘Wd’ with or without an address modifier • The mode of the table read and table write However, word or byte-oriented file register instructions instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’  2009-2012 Microchip Technology Inc. DS70616G-page 485

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Most instructions are a single word. Certain double-word with the additional instruction cycle(s) executed as a instructions are designed to provide all the required NOP. Certain instructions that involve skipping over the information in these 48 bits. In the second word, the subsequent instruction require either two or three cycles 8MSbs are ‘0’s. If this second word is executed as an if the skip is performed, depending on whether the instruction (by itself), it executes as a NOP. instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two The double-word instructions execute in two instruction cycles. cycles. Most single-word instructions are executed in a single Note: For more details on the instruction set, instruction cycle, unless a conditional test is true, or the refer to the “16-bit MCU and DSC Program Counter is changed as a result of the Programmer’s Reference Manual” instruction, or a PSV or table read is performed. In these (DS70157). cases, the execution takes multiple instruction cycles TABLE 30-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation a  {b, c, d} a is selected from the set of values b, c, d <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator Write-Back Destination Address register {W13, [W13]+ = 2} bit4 4-bitbit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0x0000...0x1FFF} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0...W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor Working register pair (Direct Addressing) DS70616G-page 486  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 30-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions  {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions  {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers {W0...W15} Wnd One of 16 destination working registers {W0...W15} Wns One of 16 source working registers {W0...W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register  { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X Data Space Prefetch Address register for DSP instructions  {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7} Wy Y Data Space Prefetch Address register for DSP instructions  {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}  2009-2012 Microchip Technology Inc. DS70616G-page 487

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 30-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 1 ADD ADD Acc(1) Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (4) None BRA GE,Expr Branch if greater than or equal 1 1 (4) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (4) None BRA GT,Expr Branch if greater than 1 1 (4) None BRA GTU,Expr Branch if unsigned greater than 1 1 (4) None BRA LE,Expr Branch if less than or equal 1 1 (4) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (4) None BRA LT,Expr Branch if less than 1 1 (4) None BRA LTU,Expr Branch if unsigned less than 1 1 (4) None BRA N,Expr Branch if Negative 1 1 (4) None BRA NC,Expr Branch if Not Carry 1 1 (4) None BRA NN,Expr Branch if Not Negative 1 1 (4) None BRA NOV,Expr Branch if Not Overflow 1 1 (4) None BRA NZ,Expr Branch if Not Zero 1 1 (4) None BRA OA,Expr(1) Branch if Accumulator A overflow 1 1 (4) None BRA OB,Expr(1) Branch if Accumulator B overflow 1 1 (4) None BRA OV,Expr(1) Branch if Overflow 1 1 (4) None BRA SA,Expr(1) Branch if Accumulator A saturated 1 1 (4) None BRA SB,Expr(1) Branch if Accumulator B saturated 1 1 (4) None BRA Expr Branch Unconditionally 1 4 None BRA Z,Expr Branch if Zero 1 1 (4) None BRA Wn Computed Branch 1 4 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None Note 1: This instruction is available in dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. DS70616G-page 488  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 30-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 4 SFA CALL Wn Call indirect subroutine 1 4 SFA CALL.L Wn Call indirect subroutine (long address) 1 4 SFA 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB(1) Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit8 Compare Wb with lit8 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit8 Compare Wb with lit8, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) CPBEQ CPBEQ Wb,Wn,Expr Compare Wb with Wn, branch if = 1 1 (5) None 22 CPSGT CPSGT Wb,Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) CPBGT CPBGT Wb,Wn,Expr Compare Wb with Wn, branch if > 1 1 (5) None 23 CPSLT CPSLT Wb,Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) CPBLT CPBLT Wb,Wn,Expr Compare Wb with Wn, branch if < 1 1 (5) None 24 CPSNE CPSNE Wb,Wn Compare Wb with Wn, skip if  1 1 None (2 or 3) CPBNE CPBNE Wb,Wn,Expr Compare Wb with Wn, branch if  1 1 (5) None Note 1: This instruction is available in dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2009-2012 Microchip Technology Inc. DS70616G-page 489

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 30-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn(1) Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit15,Expr(1) Do code to PC + Expr, lit15 + 1 times 2 2 None DO Wn,Expr(1) Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd(1) Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd(1) Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 4 None GOTO Wn Go to indirect 1 4 None GOTO.L Wn Go to indirect (long address) 1 4 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 SFA 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB(1) Multiply and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(1) Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB Note 1: This instruction is available in dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. DS70616G-page 490  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 30-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 None MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVPAG MOVPAG #lit10,DSRPAG Move 10-bit literal to DSRPAG 1 1 None MOVPAG #lit9,DSWPAG Move 9-bit literal to DSWPAG 1 1 None MOVPAG #lit8,TBLPAG Move 8-bit literal to TBLPAG 1 1 None MOVPAGW Ws, DSRPAG Move Ws<9:0> to DSRPAG 1 1 None MOVPAGW Ws, DSWPAG Move Ws<8:0> to DSWPAG 1 1 None MOVPAGW Ws, TBLPAG Move Ws<7:0> to TBLPAG 1 1 None 48 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB(1) Prefetch and store accumulator 1 1 None 49 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(1) Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(1) Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 50 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(1) -(Multiply Wm by Wn) to Accumulator 1 1 None 51 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB(1) Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 52 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None signed(Ws) MUL.SS Wb,Ws,Acc(1) Accumulator = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,Ws,Acc(1) Accumulator = signed(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Acc(1) Accumulator = signed(Wb) * 1 1 None unsigned(lit5) MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None signed(Ws) MUL.US Wb,Ws,Acc(1) Accumulator = unsigned(Wb) * 1 1 None signed(Ws) MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.UU Wb,#lit5,Acc(1) Accumulator = unsigned(Wb) * 1 1 None unsigned(lit5) MUL.UU Wb,Ws,Acc(1) Accumulator = unsigned(Wb) * 1 1 None unsigned(Ws) MULW.SS Wb,Ws,Wnd Wnd = signed(Wb) * signed(Ws) 1 1 None MULW.SU Wb,Ws,Wnd Wnd = signed(Wb) * unsigned(Ws) 1 1 None MULW.US Wb,Ws,Wnd Wnd = unsigned(Wb) * signed(Ws) 1 1 None MULW.UU Wb,Ws,Wnd Wnd = unsigned(Wb) * unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None unsigned(lit5) MUL.SU Wb,#lit5,Wnd Wnd = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL.UU Wb,#lit5,Wnd Wnd = unsigned(Wb) * unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None Note 1: This instruction is available in dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2009-2012 Microchip Technology Inc. DS70616G-page 491

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 30-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 53 NEG NEG Acc(1) Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 54 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 55 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd + 1) POP.S Pop Shadow Registers 1 1 All 56 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack 1 2 None (TOS) PUSH.S Push Shadow Registers 1 1 None 57 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 58 RCALL RCALL Expr Relative Call 1 4 SFA RCALL Wn Computed Call 1 4 SFA 59 REPEAT REPEAT #lit15 Repeat Next Instruction lit15 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 60 RESET RESET Software device Reset 1 1 None 61 RETFIE RETFIE Return from interrupt 1 6 (5) SFA 62 RETLW RETLW #lit10,Wn Return with literal in Wn 1 6 (5) SFA 63 RETURN RETURN Return from Subroutine 1 6 (5) SFA 64 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 65 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 66 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z 67 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 68 SAC SAC Acc,#Slit4,Wdo(1) Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo(1) Store Rounded Accumulator 1 1 None 69 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z 70 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 71 SFTAC SFTAC Acc,Wn(1) Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6(1) Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB Note 1: This instruction is available in dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle. DS70616G-page 492  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 30-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemonic Assembly Syntax Description Words Cycles(2) Affected # 72 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 73 SUB SUB Acc(1) Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 74 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 75 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z 76 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 77 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 78 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 5 None 79 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 5 None 80 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 81 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 82 ULNK ULNK Unlink Frame Pointer 1 1 SFA 83 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 84 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N Note 1: This instruction is available in dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only. 2: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2009-2012 Microchip Technology Inc. DS70616G-page 493

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 494  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 31.0 DEVELOPMENT SUPPORT 31.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® • Integrated Development Environment operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C® for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2009-2012 Microchip Technology Inc. DS70616G-page 495

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 31.2 MPLAB C Compilers for Various 31.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 31.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 31.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 31.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70616G-page 496  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 31.7 MPLAB SIM Software Simulator 31.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 31.10 PICkit 3 In-Circuit Debugger/ Programmer and 31.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2009-2012 Microchip Technology Inc. DS70616G-page 497

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 31.11 PICkit 2 Development 31.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a applications. breakpoint, the file registers can be examined and In addition to the PICDEM™ and dsPICDEM™ demon- modified. stration/development board series of circuits, Microchip The PICkit 2 Debug Express include the PICkit 2, demo has a line of evaluation kits and demonstration software board and microcontroller, hookup cables and CDROM for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® with user’s guide, lessons, tutorial, compiler and evaluation system, Sigma-Delta ADC, flow rate MPLAB IDE software. sensing, plus many more. 31.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything needed to experience the specified device. This usually The MPLAB PM3 Device Programmer is a universal, includes a single application and debug capability, all CE compliant device programmer with programmable on one board. voltage verification at VDDMIN and VDDMAX for Check the Microchip web page (www.microchip.com) maximum reliability. It features a large LCD display for the complete list of demonstration, development (128 x 64) for menus and error messages and a modu- and evaluation kits. lar, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70616G-page 498  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 32.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings (See Note1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS.......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS(3)....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD3.0V(3)................................................... -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3)..................................................... -0.3V to 3.6V Voltage on D+ OR D- pin with respect to VUSB3V3................................................................... -0.3V to (VUSB3V3 +0.3V) Voltage on VBUS with respect to VSS........................................................................................................ -0.3V to +5.5V Maximum current out of VSS pin...........................................................................................................................320 mA Maximum current into VDD pin(2)...........................................................................................................................320 mA Maximum current sourced/sunk by any 4x I/O pin(4)..............................................................................................15 mA Maximum current sourced/sunk by any 8x I/O pin(4)..............................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table32-2). 3: See the “Pin Diagrams” section for the 5V tolerant pins. 4: Characterized but not tested.  2009-2012 Microchip Technology Inc. DS70616G-page 499

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 32.1 DC Characteristics TABLE 32-1: OPERATING MIPS VS. VOLTAGE Maximum MIPS VDD Range Temp Range Characteristic (in Volts) (in °C) dsPIC33EPXXX(GP/MC/MU)806/810/ 814 and PIC24EPXXX(GP/GU)810/814 — 2.95V-3.6V(1) -40°C to +85°C 70 — 2.95V-3.6V(1) -40°C to +125°C 60 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. TABLE 32-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typ. Max. Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Extended Temperature Devices Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 32-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ. Max. Unit Notes Package Thermal Resistance, 64-pin QFN (9x9 mm) JA 28 — °C/W 1 Package Thermal Resistance, 64-pin TQFP (10x10 mm) JA 47 — °C/W 1 Package Thermal Resistance, 100-pin TQFP (12x12 mm) JA 43 — °C/W 1 Package Thermal Resistance, 100-pin TQFP (14x14 mm) JA 43 — °C/W 1 Package Thermal Resistance, 121-pin TFBGA (10x10 mm) JA 40 — °C/W 1 Package Thermal Resistance, 144-pin LQFP (20x20 mm) JA 33 — °C/W 1 Package Thermal Resistance, 144-pin TQFP (16x16 mm) JA 33 — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS70616G-page 500  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ.(1) Max. Units Conditions Operating Voltage DC10 VDD Supply Voltage(3) 3.0 — 3.6 V DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V DC16 VPOR VDD Start Voltage — — VSS V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 1.0 — — V/ms 0-3.0V in 3 ms to Ensure Internal Power-on Reset Signal Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: This is the limit to which VDD may be lowered without losing RAM data. 3: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values.  2009-2012 Microchip Technology Inc. DS70616G-page 501

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param.(2) Typ.(3) Max. Units Conditions Operating Current (IDD)(1) DC20d 12 18 mA -40°C DC20a 12 18 mA +25°C 3.3V 10 MIPS DC20b 13 20 mA +85°C DC20c 14 21 mA +125°C DC22d 23 35 mA -40°C DC22a 24 36 mA +25°C 3.3V 20 MIPS DC22b 24 36 mA +85°C DC22c 25 38 mA +125°C DC24d 42 63 mA -40°C DC24a 43 65 mA +25°C 3.3V 40 MIPS DC24b 44 66 mA +85°C DC24c 45 68 mA +125°C DC25d 61 92 mA -40°C DC25a 62 93 mA +25°C 3.3V 60 MIPS DC25b 62 93 mA +85°C DC25c 63 95 mA +125°C DC26d 69 104 mA -40°C DC26a 70 105 mA +25°C 3.3V 70 MIPS DC26b 70 105 mA +85°C Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero and unimplemented PMDx bits are set to one) • CPU is executing while(1) statement • JTAG is disabled 2: These parameters are characterized but not tested in manufacturing. 3: Data in “Typ” column is at 3.3V, +25ºC unless otherwise stated. DS70616G-page 502  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param.(2) Typ.(3) Max. Units Conditions Idle Current (IIDLE)(1) DC40d 6 10 mA -40°C DC40a 7 12 mA +25°C 10 MIPS DC40b 8 13 mA +85°C 3.3V DC40c 9 15 mA +125°C DC42d 11 18 mA -40°C DC42a 12 20 mA +25°C 3.3V 20 MIPS DC42b 13 21 mA +85°C DC42c 15 24 mA +125°C DC44d 23 37 mA -40°C DC44a 24 39 mA +25°C 3.3V 40 MIPS DC44b 25 40 mA +85°C DC44c 27 44 mA +125°C DC45d 34 55 mA -40°C DC45a 35 56 mA +25°C 3.3V 60 MIPS DC45b 36 58 mA +85°C DC45c 38 61 mA +125°C DC46d 39 63 mA -40°C DC46a 41 66 mA +25°C 3.3V 70 MIPS DC46b 42 68 mA +85°C Note 1: Base IIDLE current is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as digital I/O inputs) • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero and unimplemented PMDx bits are set to one) • The NVMSIDL bit (NVMCON<12>) = 1 (i.e., Flash regulator is set to stand-by while the device is in Idle mode) • JTAG is disabled 2: These parameters are characterized but not tested in manufacturing. 3: Data in “Typ” column is at 3.3V, +25ºC unless otherwise stated.  2009-2012 Microchip Technology Inc. DS70616G-page 503

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Typ.(2) Max. Units Conditions Power-Down Current (IPD)(1) DC60d 50 100 A -40°C DC60a 60 200 A +25°C 3.3V Base Power-Down Current(1,4) DC60b 250 500 A +85°C DC60c 1600 3000 A +125°C DC61d 8 10 A -40°C DC61a 10 15 A +25°C 3.3V Watchdog Timer Current: IWDT(3) DC61b 12 20 A +85°C DC61c 13 25 A +125°C Note 1: IPD (Sleep) current is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as digital I/O inputs) • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled, all peripheral modules are disabled (PMDx bits are all ones) • The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to stand-by while the device is in Sleep mode) • RTCC is disabled • The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to stand-by while the device is in Sleep mode) • JTAG is disabled 2: Data in the “Typ” column is at 3.3V, +25ºC unless otherwise stated. 3: The Watchdog Timer current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family. DS70616G-page 504  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Doze Parameter Typ.(2) Max. Units Conditions Ratio DC73a 57 86 1:2 mA -40°C 3.3V 70 MIPS DC73g 40 60 1:128 mA DC70a 58 87 1:2 mA +25°C 3.3V 70 MIPS DC70g 41 62 1:128 mA DC71a 58 87 1:2 mA +85°C 3.3V 70 MIPS DC71g 42 63 1:128 mA DC72a 53 80 1:2 mA +125°C 3.3V 60 MIPS DC72g 38 57 1:128 mA Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail with Overshoot/Undershoot < 250 mV • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero and unimplemented PMDx bits are set to one) • CPU executing while(1) statement • JTAG is disabled 2: Data in the “Typ” column is at 3.3V, +25ºC unless otherwise stated.  2009-2012 Microchip Technology Inc. DS70616G-page 505

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic Min. Typ(1) Max. Units Conditions VIL Input Low Voltage DI10 I/O Pins VSS — 0.2VDD V DI11 PMP Pins VSS — 0.15VDD V PMPTTL = 1 DI15 MCLR VSS — 0.2VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.2VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled VIH Input High Voltage DI20 I/O Pins Not 5V Tolerant(4) 0.7VDD — VDD V I/O Pins 5V Tolerant(4) 0.7VDD — 5.3 V PMP Pins 0.25 VDD + 0.8 — — V PMPTTL = 1 I/O Pins with SDAx, SCLx 0.7 VDD — 5.3 V SMBus disabled I/O Pins with SDAx, SCLx 2.1 — 5.3 V SMBus enabled ICNPU Change Notification Pull-up Current DI30 50 250 400 A VDD = 3.3V, VPIN = VSS ICNPD Change Notification Pull-down Current(10) DI31 — 50 — A VDD = 3.3V, VPIN = VDD Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted, pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. 10: These parameters are characterized, but not tested. DS70616G-page 506  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic Min. Typ(1) Max. Units Conditions IIL Input Leakage Current(2,3) DI50 I/O Pins 5V Tolerant(4) — — ±1 A VSS  VPIN  VDD, Pin at high-impedance DI51 I/O Pins Not 5V Tolerant(4) — — ±1 A VSS  VPIN  VDD, Pin at high-impedance, -40°C TA +85°C DI51a I/O Pins Not 5V Tolerant(4) — — ±1 A Analog pins shared with external reference pins, -40°C TA  +85°C DI51b I/O Pins Not 5V Tolerant(4) — — ±1 A VSS  VPIN  VDD, Pin at high-impedance, -40°CTA +125°C DI51c I/O Pins Not 5V Tolerant(4) — — ±1 A Analog pins shared with external reference pins, -40°CTA +125°C DI55 MCLR — — ±1 A VSS VPIN VDD DI56 OSC1 — — ±1 A VSS VPIN VDD, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted, pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. 10: These parameters are characterized, but not tested.  2009-2012 Microchip Technology Inc. DS70616G-page 507

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic Min. Typ(1) Max. Units Conditions IICL Input Low Injection Current DI60a All pins except VDD, VSS, AVDD, AVSS, 0 — -5(5,8) mA MCLR, VCAP, RB11, SOSCI, SOSCO, D+, D-, VUSB3V3 and VBUS IICH Input High Injection Current DI60b All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, RB11, 0 — +5(6,7,4) mA SOSCI, SOSCO, D+, D-, VUSB3V3 and VBUS, and all 5V tolerant pins(7) IICT Total Input Injection Current DI60c (sum of all I/O and control -20(9) — +20(9) mA Absolute instantaneous pins) sum of all ± input injection currents from all I/O pins (| IICL + | IICH |)  IICT Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted, pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. 10: These parameters are characterized, but not tested. DS70616G-page 508  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: — — 0.4 V IOL  10 mA, VDD = 3.3V 4x Sink Driver Pins – All I/O Pins except OSC2 and SOSCO DO10 VOL Output Low Voltage I/O Pins: — — 0.4 V IOL  15 mA, VDD = 3.3V 8x Sink Driver Pins – OSC2 and SOSCO Output High Voltage I/O Pins: 2.4 — — V IOH-10 mA, VDD = 3.3V 4x Sink Driver Pins – All I/O Pins except OSC2 and SOSCO DO20 VOH Output High Voltage I/O Pins: 2.4 — — V IOH-15 mA, VDD = 3.3V 8x Sink Driver Pins – OSC2 and SOSCO Output High Voltage 1.5(1) — — IOH-14 mA, VDD = 3.3V I/O Pins: 4x Sink Driver Pins – All I/O Pins 2.0(1) — — V IOH-12 mA, VDD = 3.3V except OSC2 and SOSCO 3.0(1) — — IOH-7 mA, VDD = 3.3V DO20A VOH1 Output High Voltage 1.5(1) — — IOH-22 mA, VDD = 3.3V I/O Pins: 8x Sink Driver Pins – OSC2 and 2.0(1) — — V IOH-18 mA, VDD = 3.3V SOSCO 3.0(1) — — IOH-10 mA, VDD = 3.3V Note 1: Parameters are characterized, but not tested. TABLE 32-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 3.0V to 3.6V(2) (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min.(1) Typ. Max. Units Conditions BO10 VBOR BOR Event on VDD Transition 2.7 — 2.9 V VDD High-to-Low Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized.  2009-2012 Microchip Technology Inc. DS70616G-page 509

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ(1) Max. Units Conditions Program Flash Memory D130 EP Cell Endurance 10,000 — — E/W -40C to +125C D131 VPR VDD for Read 3.0 — 3.6 V D132b VPEW VDD for Self-Timed Write 3.0 — 3.6 V D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated, -40C to +125C D135 IDDP Supply Current during — 10 — mA Programming D136a TRW Row Write Time 1.32 — 1.74 ms TRW = 11064 FRC cycles, TA = +85°C, See Note 2 D136b TRW Row Write Time 1.28 — 1.79 ms TRW = 11064 FRC cycles, TA = +125°C, See Note 2 D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles, TA = +85°C, See Note 2 D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles, TA = +125°C, See Note 2 D138a TWW Word Write Cycle Time 42.3 — 55.9 µs TWW = 355 FRC cycles, TA = +85°C, See Note 2 D138b TWW Word Write Cycle Time 41.1 — 57.6 µs TWW = 355 FRC cycles, TA = +125°C, See Note 2 Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = 'b011111 (for Minimum), TUN<5:0> = 'b100000 (for Maximum). This parameter depends on the FRC accuracy (see Table32-20) and the value of the FRC Oscillator Tuning register (see Register9-4). For complete details on calculating the Minimum and Maximum time, see Section5.3 “Programming Operations”. TABLE 32-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated): Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristics Min. Typ Max. Units Comments — CEFC(1) External Filter Capacitor 4.7 10 — F Capacitor must have a low Value series resistance (< 1 Ohm) Note 1: Typical VCAP (CEFC) voltage = 1.8V when VDD  VDDMIN. DS70616G-page 510  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 32.2 AC Characteristics and Timing Parameters This section defines the dsPIC33EPXXX(GP/MC/ MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 AC characteristics and timing parameters. TABLE 32-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial AC CHARACTERISTICS -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Section32.1 “DC Characteristics”. FIGURE 32-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for All Pins Except OSC2 VSS 15 pF for OSC2 Output TABLE 32-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param. Symbol Characteristic Min. Typ. Max. Units Conditions DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes when external clock is used to drive OSC1 DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode  2009-2012 Microchip Technology Inc. DS70616G-page 511

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 32-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ.(1) Max. Units Conditions OS10 FIN External CLKI Frequency DC — 60 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.5 — 10 MHz XT 10 — 40 MHz HS 32.4 32.768 33.1 kHz SOSC OS20 TOSC TOSC = 1/FOSC 8.33 — DC ns +125ºC 7.14 — DC ns +85ºC OS25 TCY Instruction Cycle Time(2) 16.67 — DC ns +125ºC 14.28 — DC ns +85ºC OS30 TosL, External Clock In (OSC1) 0.375 x TOSC — 0.625 x TOSC ns EC TosH High or Low Time OS31 TosR, External Clock In (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3) — 5.2 — ns OS41 TckF CLKO Fall Time(3) — 5.2 — ns OS42 GM External Oscillator — 12 — mA/V HS, VDD = 3.3V, Transconductance(4) TA = +25ºC — 6 — mA/V XT, VDD = 3.3V, TA = +25ºC Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “Maximum” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: This parameter is characterized, but not tested in manufacturing. DS70616G-page 512  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-17: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ.(1) Max. Units Conditions OS50 FPLLI PLL Voltage Controlled 0.8 — 8.0 MHz ECPLL, XTPLL modes Oscillator (VCO) Input Frequency Range OS51 FSYS On-Chip VCO System 120 — 340 MHz Frequency OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS OS53 DCLK CLKO Stability (Jitter)(2) -5 0.5 5 % Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for individual time bases or communication clocks used by the application, use the following formula: DCLK Effective Jitter = ------------------------------------------------------------------------------------------- FOSC --------------------------------------------------------------------------------------- Time Base or Communication Clock For example, if FOSC = 120 MHz and the SPI bit rate = 10 MHz, the effective jitter is as follows: DCLK DCLK DCLK Effective Jitter = -------------- = -------------- = -------------- 120 12 3.464 --------- 10 TABLE 32-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (dsPIC33EPXXXMU8XX AND PIC24EPXXXGU8XX DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ.(1) Max. Units Conditions OS54 AFPLLI PLL Voltage Controlled 3 — 5.5 MHz ECPLL, XTPLL modes Oscillator (VCO) Input Frequency Range OS55 AFSYS On-Chip VCO System 60 — 120 MHz Frequency OS56 ATLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS OS57 ADCLK CLKO Stability (Jitter) -2 0.25 2 % Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2009-2012 Microchip Technology Inc. DS70616G-page 513

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-19: INTERNAL FRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Characteristic Min. Typ. Max. Units Conditions Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1) F20a FRC -2 — +2 % -40°C  TA +85°C VDD = 3.0-3.6V F20b FRC -5 — +5 % -40°C  TA +125°C VDD = 3.0-3.6V Note 1: Frequency calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift. TABLE 32-20: INTERNAL LPRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Characteristic Min. Typ. Max. Units Conditions LPRC @ 32.768 kHz(1) F21a LPRC -20 ±6 +20 % -40°C  TA +85°C VDD = 3.0-3.6V F21b LPRC -50 — +50 % -40°C  TA +125°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. DS70616G-page 514  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure32-1 for load conditions. TABLE 32-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ.(1) Max. Units Conditions DO31 TIOR Port Output Rise Time — 5 10 ns DO32 TIOF Port Output Fall Time — 5 10 ns DI35 TINP INTx Pin High or Low Time (input) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.  2009-2012 Microchip Technology Inc. DS70616G-page 515

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-4: POWER-ON RESET TIMING CHARACTERISTICS Power-up Timer Disabled – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR Power-up Sequence CPU Starts Fetching Code SY00 (TPU) (Note 1,2) Power-up Timer Disabled – Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR Power-up Sequence CPU Starts Fetching Code SY00 SY10 (TPU) (TOST) (Note 1,2) Power-up Timer Enabled – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR Power-up Sequence CPU Starts Fetching Code SY00 SY11 (TPU) (TPWRT) (Note 1,2) Power-up Timer Enabled – Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR Power-up Sequence CPU Starts Fetching Code SY00 Greater of (TPU) SY10 (TOST) (Note 1,2) or SY11 (TPWRT) Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VBOR). 2: The power-up period includes internal voltage regulator stabilization delay. DS70616G-page 516  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-5: BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS MCLR TMCLR (SY20) BOR TBOR Various Delays (depending on configuration) (SY30) Reset Sequence CPU Starts Fetching Code TABLE 32-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SY00 TPU Power-up Period — 400 600 s SY10 TOST Oscillator Start-up Time — 1024TOSC — — TOSC = OSC1 period SY11 TPWRT Power-up Timer Period — — — — See Section29.1 “Configuration Bits” and LPRC Parameters F21a and F21b (Table32-20) SY12 TWDT Watchdog Timer — — — — See Section29.4 “Watchdog Time-out Period Timer (WDT)” and LPRC Parameters F21a and F21b (Table32-20) SY13 TIOZ I/O High-Impedance 0.68 0.72 1.2 s from MCLR Low or Watchdog Timer Reset SY20 TMCLR MCLR Pulse Width (low) 2 — — s SY30 TBOR BOR Pulse Width (low) 1 — — s SY35 TFSCM Fail-Safe Clock Monitor — 500 900 s -40°C to +85°C Delay SY36 TVREG Voltage Regulator — — 30 µs Standby-to-Active Mode Transition Time SY37 TOSCDFRC FRC Oscillator Start-up — — 29 µs Delay SY38 TOSCDLPRC LPRC Oscillator Start-up — — 70 µs Delay Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.  2009-2012 Microchip Technology Inc. DS70616G-page 517

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-6: TIMER1-TIMER9 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure32-1 for load conditions. TABLE 32-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(2) Min. Typ. Max. Units Conditions TA10 TTXH TxCK High Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TA15, (TCY + 20)/N N = prescaler value (1, 8, 64, 256) Asynchronous 35 — — ns TA11 TTXL TxCK Low Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TA15, (TCY + 20)/N N = prescaler value (1, 8, 64, 256) Asynchronous 10 — — ns TA15 TTXP TxCK Input Synchronous Greater of: — — ns N = prescale value Period mode 40 or (1, 8, 64, 256) (2 TCY + 40)/N OS60 Ft1 SOSC1/T1CK Oscillator DC — 50 kHz Input Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) TA20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: Timer1 is a Type A. 2: These parameters are characterized, but are not tested in manufacturing. DS70616G-page 518  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 T ABLE 32-24: TIMER2, TIMER4, TIMER6, TIMER8 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions TB10 TtxH TxCK High Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TB15, (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB11 TtxL TxCK Low Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TB15, (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB15 TtxP TxCK Synchronous Greater of: — — ns N = prescale Input mode 40 or value (1, 8, 64, 256) Period (2 TCY + 40)/N TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing. TABLE 32-25: TIMER3, TIMER5, TIMER7, TIMER9 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC15 TtxP TxCK Input Synchronous, 2 TCY + 40 — — ns N = prescale value Period with Prescaler (1, 8, 64, 256) TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing.  2009-2012 Microchip Technology Inc. DS70616G-page 519

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-7: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ10 TQ11 TQ15 TQ20 POSCNT TABLE 32-26: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions TQ10 TtQH TQCK High Synchronous, [Greater of — — ns Must also meet Time with Prescaler (12.5or 0.5TCY)/N] + 25 Parameter TQ15 TQ11 TtQL TQCK Low Synchronous, [Greater of — — ns Must also meet Time with Prescaler (12.5or 0.5TCY)/N] + 25 Parameter TQ15 TQ15 TtQP TQCP Input Synchronous, [Greater of ( — — ns Period with Prescaler 25or TCY)/N] + 50 TQ20 TCKEXTMRL Delay from External TxCK — 1 TCY — Clock Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. DS70616G-page 520  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-8: INPUT CAPTURE (ICx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure32-1 for load conditions. TABLE 32-27: INPUT CAPTURE MODULE (ICx) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time [Greater of — ns Must also meet N = prescale (12.5or 0.5TCY)/N] + 25 Parameter IC15 value (1, 4, 16) IC11 TCCH ICx Input High Time [Greater of — ns Must also meet (12.5or 0.5TCY)/N] + 25 Parameter IC15 IC15 TCCP ICx Input Period [Greater of — ns (25or 1TCY)/N] + 50 Note 1: These parameters are characterized, but not tested in manufacturing.  2009-2012 Microchip Technology Inc. DS70616G-page 521

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-9: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure32-1 for load conditions. TABLE 32-28: OUTPUT COMPARE MODULE (OCx) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 32-10: OCx/PWMx MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx Active User-Specified Fault State TABLE 32-29: OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions OC15 TFD Fault Input to PWM I/O — — TCY + 20 ns Change OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns Note 1: These parameters are characterized but not tested in manufacturing. DS70616G-page 522  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-11: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS (dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY) MP30 Fault Input (active-low) MP20 PWMx FIGURE 32-12: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS (dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY) MP11 MP10 PWMx Note: Refer to Figure32-1 for load conditions. TABLE 32-30: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS (dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions MP10 TFPWM PWM Output Fall Time — — — ns See Parameter DO32 MP11 TRPWM PWM Output Rise Time — — — ns See Parameter DO31 TFD Fault Input  to PWM — — 15 ns MP20 I/O Change MP30 TFH Fault Input Pulse Width 15 — — ns Note 1: These parameters are characterized but not tested in manufacturing.  2009-2012 Microchip Technology Inc. DS70616G-page 523

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-13: QEA/QEB INPUT CHARACTERISTICS (dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY) TQ36 QEA (input) TQ31 TQ30 TQ35 QEB (input) TQ41 TQ40 TQ31 TQ30 TQ35 QEB Internal TABLE 32-31: QUADRATURE DECODER TIMING REQUIREMENTS (dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic(1) Typ.(2) Max. Units Conditions TQ30 TQUL Quadrature Input Low Time 6 TCY — ns TQ31 TQUH Quadrature Input High Time 6 TCY — ns TQ35 TQUIN Quadrature Input Period 12 TCY — ns TQ36 TQUP Quadrature Phase Period 3 TCY — ns TQ40 TQUFL Filter Time to Recognize Low 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 3) TQ41 TQUFH Filter Time to Recognize High 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 3) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 15. “Quadrature Encoder Interface (QEI)” (DS70601) in the “dsPIC33E/PIC24E Family Reference Manual”. Please see the Microchip web site for the latest family reference manual sections. DS70616G-page 524  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-14: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS (dsPIC33EPXXX(MC/MU)806/810/814 DEVICES ONLY) QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset TABLE 32-32: QEI INDEX PULSE TIMING REQUIREMENTS (dsPIC33EPXXX(MC/MU)MU806/810/814 DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic(1) Min. Max. Units Conditions TQ50 TqIL Filter Time to Recognize Low 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ51 TqiH Filter Time to Recognize High 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ55 Tqidxr Index Pulse Recognized to Position 3 TCY — ns Counter Reset (ungated index) Note 1: These parameters are characterized but not tested in manufacturing. 2: Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on the falling edge.  2009-2012 Microchip Technology Inc. DS70616G-page 525

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-33: SPI1, SPI3 AND SPI4 MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table32-33 — — 0,1 0,1 0,1 9 MHz — Table32-34 — 1 0,1 1 9 MHz — Table32-35 — 0 0,1 1 15 MHz — — Table32-36 1 0 0 11 MHz — — Table32-37 1 1 0 15 MHz — — Table32-38 0 1 0 11 MHz — — Table32-39 0 0 0 FIGURE 32-15: SPI1, SPI3 AND SPI4 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE=0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure32-1 for load conditions. DS70616G-page 526  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-16: SPI1, SPI3 AND SPI4 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE=1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure32-1 for load conditions. TABLE 32-34: SPI1, SPI3 AND SPI4 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns TdiV2scL First SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 527

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-17: SPI1, SPI3 AND SPI4 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP=1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP40 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure32-1 for load conditions. TABLE 32-35: SPI1, SPI3 AND SPI4 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 TscP Maximum SCKx Frequency — — 9 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid After — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70616G-page 528  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-18: SPI1, SPI3 AND SPI4 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP=1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35SP36 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure32-1 for load conditions. TABLE 32-36: SPI1, SPI3 AND SPI4 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 TscP Maximum SCKx Frequency — — 9 MHz -40ºC to +125ºC and see Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid After — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 529

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-19: SPI1, SPI3 AND SPI4 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP36 SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-1 for load conditions. DS70616G-page 530  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-37: SPI1, SPI3 AND SPI4 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOx Output, 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 531

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-20: SPI1, SPI3 AND SPI4 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP70 SP73 SP72 SCKx SP36 (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-1 for load conditions. DS70616G-page 532  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-38: SPI1, SPI3 AND SPI4 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOx Output, 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 533

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-21: SPI1, SPI3 AND SPI4 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SP36 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-1 for load conditions. DS70616G-page 534  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-39: SPI1, SPI3 AND SPI4 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 535

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-22: SPI1, SPI3 AND SPI4 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35SP36 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-1 for load conditions. DS70616G-page 536  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-40: SPI1, SPI3 AND SPI4 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 537

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-41: SPI2 MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table32-42 — — 0,1 0,1 0,1 10 MHz — Table32-43 — 1 0,1 1 10 MHz — Table32-44 — 0 0,1 1 15 MHz — — Table32-45 1 0 0 11 MHz — — Table32-46 1 1 0 15 MHz — — Table32-47 0 1 0 11 MHz — — Table32-48 0 0 0 FIGURE 32-23: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure32-1 for load conditions. DS70616G-page 538  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-24: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure32-1 for load conditions. TABLE 32-42: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns TdiV2scL First SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 539

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-25: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure32-1 for load conditions. TABLE 32-43: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 TscP Maximum SCKx Frequency — — 10 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70616G-page 540  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-26: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35SP36 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure32-1 for load conditions. TABLE 32-44: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP10 TscP Maximum SCKx Frequency — — 10 MHz -40ºC to +125ºC and see Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 541

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-27: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP36 SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-1 for load conditions. DS70616G-page 542  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-45: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOx Output, 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 543

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-28: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP36 SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-1 for load conditions. DS70616G-page 544  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-46: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOx Output, 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH, SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 545

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-29: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35SP36 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-1 for load conditions. DS70616G-page 546  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-47: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOx Output, 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH, SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 547

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-30: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SP36 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-1 for load conditions. DS70616G-page 548  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-48: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOx Output, 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH, SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2012 Microchip Technology Inc. DS70616G-page 549

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-31: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure32-1 for load conditions. FIGURE 32-32: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM26 IM30 IM31 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure32-1 for load conditions. DS70616G-page 550  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 T ABLE 32-49: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic(4) Min.(1) Max. Units Conditions IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2) — s 400 kHz mode TCY/2 (BRG + 2) — s 1 MHz mode(2) TCY/2 (BRG + 2) — s IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2) — s 400 kHz mode TCY/2 (BRG + 2) — s 1 MHz mode(2) TCY/2 (BRG + 2) — s IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) 0.2 — s IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — s Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 2) — s Repeated Start 1 MHz mode(2) TCY/2 (BRG + 2) — s condition IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — s After this period, the Hold Time 400 kHz mode TCY/2 (BRG +2) — s first clock pulse is 1 MHz mode(2) TCY/2 (BRG + 2) — s generated IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s Setup Time 400 kHz mode TCY/2 (BRG + 2) — s 1 MHz mode(2) TCY/2 (BRG + 2) — s IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s Hold Time 400 kHz mode TCY/2 (BRG + 2) — s 1 MHz mode(2) TCY/2 (BRG + 2) — s IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns From Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — 400 ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be 400 kHz mode 1.3 — s free before a new 1 MHz mode(2) 0.5 — s transmission can start IM50 CB Bus Capacitive Loading — 400 pF IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3 Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70330) in the “dsPIC33E/PIC24E Family Reference Manual”. Please see the Microchip web site for the latest family reference manual sections. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns. 4: These parameters are characterized, but not tested in manufacturing.  2009-2012 Microchip Technology Inc. DS70616G-page 551

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-33: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 32-34: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS26 IS30 IS25 IS31 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70616G-page 552  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-50: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic(3) Min. Max. Units Conditions IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s 1 MHz mode(1) 0.5 — s IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4 — s Hold Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.25 s IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission 1 MHz mode(1) 0.5 — s can start IS50 CB Bus Capacitive Loading — 400 pF IS51 TPGD Pulse Gobbler Delay 65 390 ns See Note 2 Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 2: The typical value for this parameter is 130 ns. 3: These parameters are characterized, but not tested in manufacturing.  2009-2012 Microchip Technology Inc. DS70616G-page 553

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-35: ECAN™ MODULE I/O TIMING CHARACTERISTICS CxTx Pin Old Value New Value (output) CA10 CA11 CxRx Pin (input) CA20 TABLE 32-51: ECAN™ MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions CA10 TioF Port Output Fall Time — — — ns See Parameter DO32 CA11 TioR Port Output Rise Time — — — ns See Parameter DO31 CA20 TCWF Pulse Width to Trigger 120 — — ns CAN Wake-up Filter Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 32-36: UARTx MODULE I/O TIMING CHARACTERISTICS UA20 UxRX MSb In Bit 6-1 LSb In UXTX UA10 TABLE 32-52: UARTx MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions UA10 TUABAUD UARTx Baud Time 66.67 — — ns UA11 FBAUD UARTx Baud Frequency — — 15 mbps UA20 TCWF Start Bit Pulse Width to Trigger 500 — — ns UARTx Wake-up Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70616G-page 554  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-53: USB OTG MODULE SPECIFICATIONS (dsPIC33EPXXXMU8XX AND PIC24EPXXXGU8XX DEVICES ONLY) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristics(1) Min. Typ. Max. Units Conditions USB313 VUSB3V3(2) USB Voltage 3.0 — 3.6 V Voltage on bus must be in this range for proper USB operation USB315 VILUSB Input Low Voltage for USB — — 0.8 V Buffer USB316 VIHUSB Input High Voltage for USB 2.0 — — V Buffer USB318 VDIFS Differential Input Sensitivity — — 0.2 V USB319 VCM Differential Common-Mode 0.8 — 2.5 V The difference between D+ and Range D- must be within this range while VCM is met USB320 ZOUT Driver Output Impedance 28.0 — 44.0  USB321 VOL Voltage Output Low 0.0 — 0.3 V 14.25 k load connected to 3.6V USB322 VOH Voltage Output High 2.8 — 3.6 V 14.25 k load connected to ground Note 1: These parameters are characterized but not tested in manufacturing. 2: If the USB module is not being used, this pin must be connected to VDD.  2009-2012 Microchip Technology Inc. DS70616G-page 555

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-54: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (see Note 3) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions Device Supply AD01 AVDD(2) Module VDD Supply Greater of — Lesser of V VDD – 0.3 VDD + 0.3 or 3.0 or 3.6 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.5 — AVDD V See Note 1, VREFH = VREF+, VREFL = VREF- AD05a 3.0 — 3.6 V VREFH = AVDD, VREFL = AVSS = 0 AD06 VREFL Reference Voltage Low AVSS — AVDD – 2.5 V See Note 1 AD06a 0 — 0 V VREFH = AVDD, VREFL = AVSS = 0 AD07 VREF Absolute Reference 2.5 — 3.6 V VREF = VREFH – VREFL Voltage AD08 IREF Current Drain — — 10 A ADC off — — 600 A ADC on AD09 IAD Operating Current — 9.0 — mA ADC operating in 10-bit mode, see Note 1 — 3.2 — mA ADC operating in 12-bit mode, see Note 1 Analog Input AD12 VINH Input Voltage Range, VINH VINL — VREFH V This voltage reflects Sample & Hold Channels 0, 1, 2 and 3 (CH0-CH3), positive input AD13 VINL Input Voltage Range, VINL VREFL — AVSS + 1V V This voltage reflects Sample & Hold Channels 0, 1, 2 and 3 (CH0-CH3), negative input AD17 RIN Recommended Impedance — — 200  of Analog Voltage Source Note 1: These parameters are not characterized or tested in manufacturing. 2: The voltage difference between AVDD and VDD cannot exceed 300 mV at any time during operation or start-up. 3: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. DS70616G-page 556  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-55: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (see Note 1) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions ADC Accuracy (12-Bit Mode) – Measurements with External VREF+/VREF- AD20a Nr Resolution 12 Data Bits bits AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22a DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23a GERR Gain Error 1.25 1.5 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24a EOFF Offset Error 1.25 1.52 2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25a — Monotonicity — — — — Guaranteed(2) ADC Accuracy (12-Bit Mode) – Measurements with Internal VREF+/VREF- AD20a Nr Resolution 12 data bits bits AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = 0V, AVDD = 3.6V AD22a DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD23a GERR Gain Error 2 3 7 LSb VINL = AVSS = 0V, AVDD = 3.6V AD24a EOFF Offset Error 2 3 5 LSb VINL = AVSS = 0V, AVDD = 3.6V AD25a — Monotonicity — — — — Guaranteed(2) Dynamic Performance (12-Bit Mode) AD30a THD Total Harmonic Distortion — — -75 dB AD31a SINAD Signal to Noise and 68.5 69.5 — dB Distortion AD32a SFDR Spurious Free Dynamic 80 — — dB Range AD33a FNYQ Input Signal Bandwidth — — 250 kHz AD34a ENOB Effective Number of Bits 11.09 11.3 — bits Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. 2: The Analog-to-Digital conversion result never decreases with an increase in input voltage and has no missing codes.  2009-2012 Microchip Technology Inc. DS70616G-page 557

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-56: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (see Note 1) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions ADC Accuracy (10-Bit Mode) – Measurements with External VREF+/VREF- AD20b Nr Resolution 10 data bits bits AD21b INL Integral Nonlinearity -1 — +1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23b GERR Gain Error 1 3 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24b EOFF Offset Error 1 2 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25b — Monotonicity — — — — Guaranteed(2) ADC Accuracy (10-Bit Mode) – Measurements with Internal VREF+/VREF- AD20b Nr Resolution 10 data bits bits AD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = 0V, AVDD = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD23b GERR Gain Error 1 5 6 LSb VINL = AVSS = 0V, AVDD = 3.6V AD24b EOFF Offset Error 1 2 5 LSb VINL = AVSS = 0V, AVDD = 3.6V AD25b — Monotonicity — — — — Guaranteed(2) Dynamic Performance (10-Bit Mode) AD30b THD Total Harmonic Distortion — — -64 dB AD31b SINAD Signal to Noise and 57 58.5 — dB Distortion AD32b SFDR Spurious Free Dynamic 72 — — dB Range AD33b FNYQ Input Signal Bandwidth — — 550 kHz AD34b ENOB Effective Number of Bits 9.16 9.4 — bits Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. 2: The Analog-to-Digital conversion result never decreases with an increase in input voltage and has no missing codes. DS70616G-page 558  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-37: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000, SSRCG = 0) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 9 1 – Software sets AD1CON1. SAMP to start sampling. 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 10. Section 16. “Analog-to-Digital Converter (ADC)” (DS70621) of the “dsPIC33E/PIC24E Family Reference Manual”. 7 – Convert bit 1. 3 – Software clears AD1CON1. SAMP to start conversion. 8 – Convert bit 0. 4 – Sampling ends, conversion sequence starts. 9 – One TAD for end of conversion.  2009-2012 Microchip Technology Inc. DS70616G-page 559

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-57: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (see Note 4) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ.(2) Max. Units Conditions Clock Parameters AD50 TAD ADC Clock Period 117.6 — — ns AD51 tRC ADC Internal RC Oscillator — 250 — ns Period Conversion Rate AD55 tCONV Conversion Time — 14 TAD ns AD56 FCNV Throughput Rate — — 500 Ksps AD57 TSAMP Sample Time 3 TAD — — — Timing Parameters AD60 tPCS Conversion Start from Sample 2 TAD — 3 TAD — Auto-Convert Trigger Trigger(1) not selected AD61 tPSS Sample Start from Setting 2 TAD — 3 TAD — Sample (SAMP) bit(1) AD62 tCSS Conversion Completion to — 0.5 TAD — — Sample Start (ASAM = 1)(1) AD63 tDPU Time to Stabilize Analog Stage — — 20 s See Note 3 from ADC Off to ADC On(1) Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. 2: These parameters are characterized but not tested in manufacturing. 3: The tDPU parameter is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (ADON (ADxCON1<15>) = 1). During this time, the ADC result is indeterminate. 4: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. DS70616G-page 560  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-38: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000, SSRCG = 0) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 AD55 DONE ADxIF 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADx1CON1. SAMP to start sampling. 5 – Convert bit 9. 2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 8. Section 16. “Analog-to-Digital Converter (ADC)” (DS70621) of the “dsPIC33E/PIC24E Family Reference Manual”. 7 – Convert bit 0. 3 – Software clears ADxCON1. SAMP to start conversion. 8 – One TAD for end of conversion. 4 – Sampling ends, conversion sequence starts. FIGURE 32-39: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010) AD50 ADCLK Instruction Set ADON Execution AD62 SAMP TSAMP AD55 AD55 TSAMP AD55 ADxIF DONE 1 2 3 4 5 6 7 3 4 5 6 8 1 – Software sets ADxCON1. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in 6 – One TAD for end of conversion. Section 16. “Analog-to-Digital Converter (ADC)” (DS70621) of the “dsPIC33E/PIC24E Family Reference Manual”. 7 – Begin conversion of next channel. 3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>. 4 – Convert bit 8.  2009-2012 Microchip Technology Inc. DS70616G-page 561

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-58: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (see Note 4) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ.(1) Max. Units Conditions Clock Parameters AD50 TAD ADC Clock Period 76 — — ns AD51 tRC ADC Internal RC Oscillator Period — 250 — ns Conversion Rate AD55 tCONV Conversion Time — 12 TAD — — AD56 FCNV Throughput Rate — — 1.1 Msps Using sequential sampling AD57 TSAMP Sample Time 2 TAD — — — Timing Parameters AD60 tPCS Conversion Start from Sample 2 TAD — 3 TAD — Auto-Convert Trigger Trigger(2) not selected AD61 tPSS Sample Start from Setting 2 TAD — 3 TAD — Sample (SAMP) bit(2) AD62 tCSS Conversion Completion to — 0.5 TAD — — Sample Start (ASAM = 1)(2) AD63 tDPU Time to Stabilize Analog Stage — — 20 s See Note 3 from ADC Off to ADC On(2) Note 1: These parameters are characterized but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. 3: The tDPU parameter is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (ADON (ADxCON1<15>) = 1). During this time, the ADC result is indeterminate. 4: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. DS70616G-page 562  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-40: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CSCK (SCKE = 1) CS20 CS21 COFS CS55CS56 CS35 CS51 CS50 70 CSDO High-Z MSb LSb High-Z CS30 CS31 CSDI MSb In LSb In CS40 CS41 Note: Refer to Figure32-1 for load conditions.  2009-2012 Microchip Technology Inc. DS70616G-page 563

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 T ABLE 32-59: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°C TA  +125°C for Extended Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions CS10 TCSCKL CSCK Input Low Time TCY/2 + 20 — — ns (CSCK pin is an input) CSCK Output Low Time(3) 30 — — ns (CSCK pin is an output) CS11 TCSCKH CSCK Input High Time TCY/2 + 20 — — ns (CSCK pin is an input) CSCK Output High Time(3) 30 — — ns (CSCK pin is an output) CS20 TCSCKF CSCK Output Fall Time — — — ns See Parameter DO32 (CSCK pin is an output) CS21 TCSCKR CSCK Output Rise Time — — — ns See Parameter DO31 (CSCK pin is an output) CS30 TCSDOF CSDO Data Output Fall Time — — — ns See Parameter DO32 CS31 TCSDOR CSDO Data Output Rise Time — — — ns See Parameter DO31 CS35 TDV Clock Edge to CSDO Data Valid — — 10 ns CS36 TDIV Clock Edge to CSDO Tri-Stated 10 — 20 ns CS40 TCSDI Setup Time of CSDI Data Input 20 — — ns to CSCK Edge (CSCK pin is input or output) CS41 THCSDI Hold Time of CSDI Data Input to 20 — — ns CSCK Edge (CSCK pin is input or output) CS50 TCOFSF COFS Fall Time — — — ns See Parameter DO32 (COFS pin is output) CS51 TCOFSR COFS Rise Time — — — ns See Parameter DO31 (COFS pin is output) CS55 TSCOFS Setup Time of COFS Data Input 20 — — ns to CSCK Edge (COFS pin is input) CS56 THCOFS Hold Time of COFS Data Input to 20 — — ns CSCK Edge (COFS pin is input) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. DS70616G-page 564  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-41: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 SDOx (CSDO) LSb MSb LSb CS76 CS75 SDIx MSb In (CSDI) CS65 CS66  2009-2012 Microchip Technology Inc. DS70616G-page 565

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 T ABLE 32-60: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C TA  +125°C for Extended Param. Symbol Characteristic(1,2) Min. Typ.(3) Max. Units Conditions CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns CS62 TBCLK BIT_CLK Period — 81.4 — ns Bit clock is input CS65 TSACL Input Setup Time to — — 10 ns Falling Edge of BIT_CLK CS66 THACL Input Hold Time from — — 10 ns Falling Edge of BIT_CLK CS70 TSYNCLO Sync Data Output Low Time — 19.5 — s CS71 TSYNCHI Sync Data Output High Time — 1.3 — s CS72 TSYNC Sync Data Output Period — 20.8 — s CS77 TRACL Rise Time, Sync, SDATA_OUT — — — ns See Parameter DO32 CS78 TFACL Fall Time, Sync, SDATA_OUT — — — ns See Parameter DO31 CS80 TOVDACL Output Valid Delay from Rising — — 15 ns Edge of BIT_CLK Note 1: These parameters are characterized but not tested in manufacturing. 2: These values assume the BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70616G-page 566  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-61: COMPARATOR TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (see Note 3) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions 300 TRESP Response Time(2) — 150 400 ns 301 TMC2OV Comparator Mode Change — — 10 s to Output Valid Note 1: Parameters are characterized but not tested. 2: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. 3: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. TABLE 32-62: COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (see Note 2) (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions D300 VIOFF Input Offset Voltage — ±10 — mV D301 VICM Input Common-Mode Voltage AVSS — AVDD V D302 CMRR Common-Mode Rejection Ratio -54 — — dB D305 IVREF Internal Voltage Reference 0.19 0.20 0.21 V BGSEL<1:0> = 10 0.57 0.60 0.63 V BGSEL<1:0> = 01 1.14 1.20 1.26 V BGSEL<1:0> = 00 Note 1: Parameters are characterized but not tested. 2: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values.  2009-2012 Microchip Technology Inc. DS70616G-page 567

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE 32-63: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (see Note 3) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(2) Min. Typ. Max. Units Conditions VR310 TSET Settling Time(1) — — 10 s Note 1: Setting time measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’. 2: These parameters are characterized, but not tested in manufacturing. 3: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. TABLE 32-64: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (see Note 2) (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions VRD310 CVRES Resolution CVRSRC/24 — CVRSRC/32 LSb VRD311 CVRAA Absolute Accuracy — — 0.5 LSb VRD312 CVRL Maximum Load on CVREF — — 0.75 A AVDD = 3.6V, Output Pin CVRSS = 0, CVRR = 0, CVR<3:0> = 1111 Note 1: These parameters are characterized, but not tested in manufacturing. 2: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, Comparator and DAC will have degraded performance. Device functionality is tested but not characterized. Refer to Parameter BO10 in Table32-11 for the minimum and maximum BOR values. DS70616G-page 568  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-42: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 32-65: PARALLEL SLAVE PORT TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Symbol Characteristic(1) Min. Typ. Max. Units Conditions PS1 TdtV2wrH Data In Valid Before WR or CS 20 — — ns Inactive (setup time) PS2 TwrH2dtI WR or CS Inactive to Data In 20 — — ns Invalid (hold time) PS3 TrdL2dtV RD and CS to Active Data Out — — 80 ns Valid PS4 TrdH2dtI RD or CS Inactive to Data Out 10 — 30 ns Invalid PS5 Tcs CS Active Time 33.33 — — ns PS6 Twr RD Active Time 33.33 — — ns PS7 Trd WR Active Time 33.33 — — ns Note 1: These parameters are characterized, but not tested in manufacturing.  2009-2012 Microchip Technology Inc. DS70616G-page 569

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-43: PARALLEL MASTER PORT READ TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock PMA<13:8> Address PMD<7:0> Address <7:0> Data PM6 PM7 PM2 PM3 PMRD PM5 PMWR PMALL/PMALH PM1 PMCS1 TABLE 32-66: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Characteristic(1) Min. Typ. Max. Units Conditions PM1 PMALL/PMALH Pulse Width — 0.5 TCY — ns PM2 Address Out Valid to PMALL/PMALH Invalid — 1 TCY — ns (address setup time) PM3 PMALL/PMALH Invalid to Address Out Invalid — 0.5 TCY — ns (address hold time) PM5 PMRD Pulse Width — 0.5 TCY — ns PM6 PMRD or PMENB Active to Data In Valid (data 150 — — ns setup time) PM7 PMRD or PMENB Inactive to Data In Invalid — — 5 ns (data hold time) Note 1: These parameters are characterized, but not tested in manufacturing. DS70616G-page 570  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 FIGURE 32-44: PARALLEL MASTER PORT WRITE TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock PMA<13:8> Address PMD<7:0> Address <7:0> Data Data PM12 PM13 PMRD PMWR PM11 PMALL/PMALH PMCS1 PM16 TABLE 32-67: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Characteristic(1) Min. Typ. Max. Units Conditions PM11 PMWR Pulse Width — 0.5 TCY — ns PM12 Data Out Valid Before PMWR or PMENB — 1 TCY — ns goes Inactive (data setup time) PM13 PMWR or PMEMB Invalid to Data Out Invalid — 0.5 TCY — ns (data hold time) PM16 PMCSx Pulse Width TCY - 5 — — ns ADRMUX<1:0> = 00 (demultiplexed address) Note 1: These parameters are characterized, but not tested in manufacturing. TABLE 32-68: DMA MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param. Characteristic(1) Min. Typ. Max. Units Conditions DM1 DMA Byte/Word Transfer Latency 1 TCY — — ns Note 1: These parameters are characterized, but not tested in manufacturing.  2009-2012 Microchip Technology Inc. DS70616G-page 571

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 572  2009-2012 Microchip Technology Inc.

 33.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS 2 0 0 9 Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes -20 only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating 1 2 range (e.g., outside specified power supply range) and therefore, outside the warranted range. M ic d ro s c FIGURE 33-1: VOH – 4x DRIVER PINS @ +85ºC FIGURE 33-3: VOL – 4x DRIVER PINS @ +85ºC P hip IC Techn --00..005500 VVOOHH ((VV)) 00..005500 VVOOLL(cid:2)(cid:2)((VV)) 33E olog --00..004455 3.6V 00..004455 3.6V PX y Inc. ----0000....000043430505 3.3V 0000....000034345050 3.3V XX( --00..003300 3V 3V G IOH(A)IOH(A) ----0000....000022225050 IOH(A)IOH(A) 000000......000000223223050050 P/MC / -0.015 Absolute Maximum 00..001155 Absolute Maximum M U -0.010 0.010 ) 8 -0.005 0.005 0 6 0.000 0.000 / 8 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 1 0 / 8 1 4 FIGURE 33-2: VOH – 8x DRIVER PINS @ +85ºC FIGURE 33-4: VOL – 8x DRIVER PINS @ +85ºC a 88XX n VVOOHH(cid:2)(cid:2)((VV)) VVOOLL(cid:2)(cid:2)((VV)) d --00..008800 00..008800 3.6V P 3.6V I C --00..007700 00..007700 3.3V 2 3.3V 4 --00..006600 00..006600 E 3V P --00..005500 3V 00..005500 X A)A) A)A) X H(H( --00..004400 H(H( 00..004400 X OO OO ( II -00.003300 II 00..003300 G D Absolute Maximum Absolute Maximum P S7 -0.020 00.002200 /G 0 61 -0.010 0.010 U 6 ) G 8 -p 0.000 0.000 1 a 0 ge 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 /8 5 1 73 4

D FIGURE 33-5: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 33-7: TYPICAL IDOZE CURRENT @ VDD = 3.3V d S s 70 P 61 11,,880000 IC 6 80 G 3 -p 11,,660000 3 ag 70 E e 11,,440000 P 5 X 74 11,,220000 60 X X A)A) 11,,000000 50 (G IPD (µIPD (µ 880000 (mA)E 40 P/M OZ C 660000 ID 30 /M 440000 20 U ) 8 200 10 0 6 / 8 0 0 1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 1:1 1:2 1:64 1:128 0 Doze Ratio / 8 Temperature (Celsius) 1 4 a n FIGURE 33-6: TYPICAL IDD CURRENT – VDD = 3.3V @ +85ºC FIGURE 33-8: TYPICAL IIDLE CURRENT – VDD = 3.3V @ +85ºC d P I 80.00 C 45.00 2 4 70.00 40.00 E P 60.00 35.00 X X  2009-2 urrent (mA) 4500..0000 urrent (mA) 223050...000000 X(GP/G 0 C 30.00 C U 1 2 Micro IDDD 20.00 ILEIDL 111505..000000 )810/ c 8 hip 10.00 5.00 1 T 4 ec 0.00 0.00 h no 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 lo gy MIPS MIPS In c .

 FIGURE 33-9: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 33-10: TYPICAL LPRC FREQUENCY @ VDD = 3.3V 2 00 77440000 9 3333..22 -2 0 1 2 77338800 3333..00 M ic d rochip kHz)kHz) 77336600 kHz)kHz) 3322..88 sPIC Te cy (cy ( cy (cy ( 3322..66 3 c nn nn 3 hn ueue 77334400 ueue E o qq qq P log FreFre FreFre 3322..44 X y Inc FRC FRC 77332200 PRC PRC 3322..22 XX . LL ( G 7300 32.0 P / M C 7280 31.8 / M -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 U Temperature (Celsius) Temperature (Celsius) ) 8 0 6 / 8 1 0 / 8 1 4 a n d P I C 2 4 E P X X X ( G D P S / 7 G 0 6 U 1 6 ) G 8 -p 1 a 0 ge /8 5 1 75 4

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 576  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 34.0 PACKAGING INFORMATION 34.1 Package Marking Information 64-Lead QFN (9x9x0.9 mm) Example XXXXXXXXXX 33EP256MU XXXXXXXXXX 806-I/MR e3 YYWWNNN 0610017 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX dsPIC33EP XXXXXXXXXX 256MU806 XXXXXXXXXX -I/PTe3 YYWWNNN 0510017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX dsPIC33EP256 XXXXXXXXXXXX MU810-I/PT e3 YYWWNNN 0510017 100-Lead TQFP (14x14x1 mm) Example XXXXXXXXXXXX dsPIC33EP256 XXXXXXXXXXXX MU810-I/PF e3 YYWWNNN 0510017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2009-2012 Microchip Technology Inc. DS70616G-page 577

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 34.1 Package Marking Information (Continued) 121-Lead TFBGA (10x10x1.2 mm) Example XXXXXXXXXX 33EP256MU XXXXXXXXXX 810-I/BG e3 YYWWNNN 0610017 144-Lead LQFP (20x20x1.4 mm) Example XXXXXXXXXXXX dsPIC33EP256 XXXXXXXXXXXX MU814-I/PL e3 YYWWNNN 0510017 144-Lead TQFP (16x16x1 mm) Example XXXXXXXXXXXX dsPIC33EP256 XXXXXXXXXXXX MU814-I/PH e3 YYWWNNN 0510017 DS70616G-page 578  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 34.2 Package Details Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc. DS70616G-page 579

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70616G-page 580  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc. DS70616G-page 581

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 64 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-085B DS70616G-page 582  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc. DS70616G-page 583

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E E1 N b NOTE 1 123 NOTE 2 α c A φ β L A1 L1 A2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 100 Lead Pitch e 0.40 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 14.00 BSC Overall Length D 14.00 BSC Molded Package Width E1 12.00 BSC Molded Package Length D1 12.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.13 0.18 0.23 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-100B DS70616G-page 584  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc. DS70616G-page 585

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 100-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E1 E b N α NOTE 1 123 NOTE 2 A φ c A2 β A1 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 100 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 16.00 BSC Overall Length D 16.00 BSC Molded Package Width E1 14.00 BSC Molded Package Length D1 14.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-110B DS70616G-page 586  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc. DS70616G-page 587

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 DS70616G-page 588  2009-2012 Microchip Technology Inc.

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dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 144-Lead Plastic Low Profile Quad Flatpack (PL) – 20x20x1.40 mm Body, with 2.00 mm Footprint [LQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc. DS70616G-page 591

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 144-Lead Plastic Low Profile Quad Flatpack (PL) – 20x20x1.40 mm Body, with 2.00 mm Footprint [LQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70616G-page 592  2009-2012 Microchip Technology Inc.

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dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70616G-page 594  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2012 Microchip Technology Inc. DS70616G-page 595

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70616G-page 596  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 APPENDIX A: REVISION HISTORY Revision A (December 2009) This is the initial released version of this document. Revision B (July 2010) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in TableA-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Removed reference to dual triggers for Motor Control Peripherals. Signal Controllers and Relocated the VBUSST pin in all pin diagrams (see “Pin Diagrams”, Table2 Microcontrollers” and Table3). Added SCK2, SDI2, SDO2 pins in pin location 4,5 and 6 respectively in 64-pin QFN. Added SCK2, SDI2, SDO2 pins in pin location 4,5 and 6 respectively in 64-pin TQFP. Added SCK2, SDI2, SDO2 pins in pin location 10,11 and 12 respectively in 100-pin TQFP. Added SCK2, SDI2, SDO2 pins in Table2 and Table3. Moved the RP30 pin to pin location 95, and the RP31 pin to pin location 96 in the 144-pin TQFP and 144-pin LQFP pin diagrams. Section1.0 “Device Overview” Removed the SCL1 and SDA1 pins from the Pinout I/O Descriptions (see Table1-1). Section2.0 “Guidelines for Removed Section2.8 “Configuration of Analog and Digital Pins During ICSP Getting Started with 16-bit Digital Operations” Signal Controllers and Microcontrollers” Section3.0 “CPU” Added Note 4 to the CPU Status Register (SR) in Register3-1. Added the VAR bit (CORCON<15>) to Register3-2.  2009-2012 Microchip Technology Inc. DS70616G-page 597

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section4.0 “Memory Added the Write Latch and Auxiliary Interrupt Vector to the Program Memory Organization” Map (see Figure4-1). Updated the All Resets value for the DSRPAG and DSWPAG registers in the CPU Core Register Maps (see Table4-1 and Table4-2). Updated the All Resets value for the INTCON2 register in the Interrupt Controller Register Maps (see Table4-3 through Table4-6). Updated the All Resets values for all registers in the Output Compare 1 - Output Compare 16 Register Map, with the exception of the OCxTMR and OCxCON1 registers (see Table4-9). Removed the DTM bit (TRGCON1<7> from all PWM Generator # Register Maps (see Table4-11 through Table4-17). Updated the All Resets value for the QEI1IOC register in the QEI1 Register Map (see Table4-18). Updated the All Resets value for the QEI2IOC register in the QEI1 Register Map (see Table4-19). Added Note 4 to the USB OTG Register Map (see Table4-25) Updated all addresses in the Real-Time Clock and Calendar Register Map (see Table4-34). Removed RPINR22 from Table4-37 through Table4-40. Updated the All Resets values for all registers in the Peripheral Pin Select Input Register Maps and modified the RPIN37-RPINR43 registers (see Table4-37 through Table4-40). Added the VREGSF bit (RCON<11>) to the System Control Register Map (see Table4-43). Added the REFOMD bit (PMD4<3>) to the PMD Register Maps (see Table4-44 through Table4-47). Changed the bit range for CNT from <15:0> to <13:0> for all DMAxCNT registers in the DMAC Register Map (see Table4-49). Updated the All Resets value and removed the ANSC15 and ANSC12 bits in the ANSLEC registers in the PORTC Register Maps (see Table4-52 and Table4-53). Updated DSxPAG and Page Description of O, Read and U, Read in Table4-66. Added Note to the Table4-67. Updated Arbiter Architecture in Figure4-8. Updated the Unimplemented value and removed the LATG3 and LATG2 bits in the LATG registers and the CNPUG3 and CNPUG2 bits from the CNPUG registers in the PORTG Register Maps (see Table4-60 and Table4-61) Updated the All Resets value and removed the TRISG3 and TRISG2 bits in the TRISG registers and the ODCG3 and ODCG2 bits from the ODCG registers in the PORTG Register Maps (see Table4-60 and Table4-61). Section5.0 “Flash Program Updated the NVMOP<3:0> = 1110 definition to Reserved and added Note 6 to Memory” the Nonvolatile Memory (NVM) Control Register (see Register5-1). Section6.0 “Resets” Added the VREGSF bit (RCON<11>) to the Reset Control Register (see Register6-1). DS70616G-page 598  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section7.0 “Interrupt Controller” Added the VAR bit (CORCON<15>) to the Core Control Register (see Register7-2) Changed the default POR value for the GIE bit (INTCON2<15) to R/W-1 (see Register7-4). Changed the VECNUM<7:0> = 11111111 pending interrupt vector number to 263 in the Interrupt Control and Status Register (see Register7-7). Section8.0 “Direct Memory Updated Section8.1 “DMAC Registers”. Access (DMA)” Updated DMA Controller in Figure8-1. Added Note 1 to the DMA Channel x Peripheral Address Register (see Register8-7). Added Note 1 and Note 2 to the DMA Channel x Transfer Count Register (see Register8-8). Updated all RQCOLx bit definitions, changing Peripheral Write to Transfer Request in the DMA Request Collision Status Register (see Register8-12). Section9.0 “Oscillator Added the Reference Oscillator Control Register (see Register9-7). Configuration” Added Note 3 and 4 to the CLKDIV Register (see Register9-2) Section10.0 “Power-Saving Added the DCIMD and C2MD bits to the Peripheral Module Disable Control Features” Register 1 (see Register10-1) Added the IC6MD, IC5MD, IC4MD, IC3MD, OC8MD, OC7MD, OC6MD, and OC5MD bits to the Peripheral Module Disable Control Register 2 (see Register10-2) Added the T9MD, T8MD, T7MD, and T6MD bits and removed the DSC1MD bit in the Peripheral Module Disable Control Register 3 (see Register10-3). Added the REFOMD bit (PMD4<3>) to the Peripheral Module Disable Control Register 4 (see Register10-4). Section11.0 “I/O Ports” Updated the first paragraph of Section11.2 “Configuring Analog and Digital Port Pins”. Updated the PWM Fault, Dead-Time Compensation, and Synch Input register numbers of the Selectable Input Sources (see Table11-2). Removed RPINR22 register. Bit names and definitions were modified in the following registers: • Peripheral Pin Select Input Register 37 (see Register11-37) • Peripheral Pin Select Input Register 38 (see Register11-38) • Peripheral Pin Select Input Register 39 (see Register11-39) • Peripheral Pin Select Input Register 40 (see Register11-40) • Peripheral Pin Select Input Register 41 (see Register11-41) • Peripheral Pin Select Input Register 42 (see Register11-42) • Peripheral Pin Select Input Register 43 (see Register11-43) Section12.0 “Timer1” Added Note in Register12-1. Section14.0 “Input Capture” Added Note 1 to the Input Capture Block Diagram (see Figure14-1). Section15.0 “Output Compare” Added Note 1 to the Output Compare Module Block Diagram (see Figure15-1). Added Note 2 to the Output Compare x Control Register 2 (see Register15-2). Section16.0 “High-Speed PWM Added Comparator bit values for the CLSRC<4:0> and FLTSRC<4:0> bits in Module (dsPIC33EPXXXMU806/ the PWM Fault Current-Limit Control Register (see Register16-21). 810/814 Devices Only)”  2009-2012 Microchip Technology Inc. DS70616G-page 599

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section17.0 “Quadrature Reordered the bit values for the OUTFNC<1:0> bits and updated the default Encoder Interface (QEI) Module POR bit value to ‘x’ for the HOME, INDEX, QEB, and QEA bits in the QEI I/O (dsPIC33EPXXXMU806/810/814 Control Register (see Register17-2). Devices Only)” Section23.0 “10-bit/12-bit Updated VREFL in the ADC1 and ADC2 Module Block Diagram (see Analog-to-Digital Converter Figure23-1). (ADC)” Section25.0 “Comparator Added Note 1 to the Comparator I/O Operating Modes (see Figure25-1). Module” Removed the CLPWR bit (CMxCON<12>) (see Register25-2). Section29.0 “Special Features” Added a new first paragraph to Section29.1 “Configuration Bits” Section30.0 “Instruction Set The following instructions have been updated (see Table30-2): Summary” • BRA • CALL • CPBEQ • CPBGT • CPBLT • CPBNE • GOTO • MOVPAG • MUL • RCALL • RETFIE • RETLW • RETURN • TBLRDH • TBLRDL Section32.0 “Electrical Updated the Typical and Maximum values for DC Characteristics: Operating Characteristics” Current (IDD) (see Table32-5). Updated the Typical and Maximum values for DC Characteristics: Idle Current (IIDLE) (see Table32-6). Updated the Maximum values for DC Characteristics: Power-down Current (IPD) (see Table32-7). Updated the Maximum values for DC Characteristics: Doze Current (IDOZE) (see Table32-8). Updated the parameter numbers for Internal FRC Accuracy (see Table32-19). Updated the parameter numbers and the Typical value for parameter F21b for Internal RC Accuracy (see Table32-20). Updated the Minimum value for PM6 and the Typical and Maximum values for PM7 in Parallel Master Port Read Requirements (see Table32-52). Added DMA Module Timing Requirements (see Table32-54). DS70616G-page 600  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Revision C (May 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. These global changes were implemented: • All instances of VDDCORE have been removed. • References to remappable pins have been updated to clarify output-only pins (RPn) versus input/output pins (RPIn). • The minimum VDD value was changed from 2.7V to 3.0V to adhere to the current BOR specification. The major changes are referenced by their respective section in TableA-2. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description High-Performance, 16-bit Digital Removed the shading for D+/RG2 and D-/RG3 pin designations in all pin Signal Controllers and diagrams, as these pins are not 5V tolerant. Microcontrollers References to remappable pins have been updated to clarify input/output pins (RPn) and input-only pins (RPIn). Section2.0 “Guidelines for Add information on the VUSB pin in Section2.1 “Basic Connection Getting Started with 16-bit Digital Requirements”. Signal Controllers and Updated the title of Section 2.3 to Section2.3 “CPU Logic Filter Capacitor Microcontrollers” Connection (VCAP)” and modified the first paragraph. Section3.0 “CPU” Added Note 2 to the Programmer’s Model Register Descriptions (see Table3-1). Section4.0 “Memory Added the CANCKS bit (CxCTRL1<11>) to the ECAN1 and ECAN 2 Register Organization” Maps (see Table4-26 and Table4-29). Added the SBOREN bit (RCON<13>) to the System Control Register Map (see Table4-43). Added Note 1 to the PORTG Register maps (see Table4-60 and Table4-61). Updated the Page Description for DSRPAG = 0x1FF and DSRPAG = 0x200 in Table4-66. Updated the second paragraph of Section4.2.9 “EDS Arbitration and Bus Master Priority”. Updated the last note box in Section4.2.10 “Software Stack”. Section5.0 “Flash Program Updated the equation formatting in Section5.3 “Programming Operations”. Memory” Added the Non-Volatile Memory Upper Address (NVMADRU) and Non-Volatile Memory Address (NVMADR) registers (see Register5-2 and Register5-3). Section6.0 “Resets” Added Security Reset to the Reset System Block Diagram (see Figure6-1). Added the SBOREN bit (RCON<13>) and Notes 3 and 4 to the Reset Control register (see Register6-1). Section11.0 “I/O Ports” References to remappable pins have been updated to clarify input/output pins (RPn) and input-only pins (RPIn). Added the new column, Input/Output, to Input Pin Selection for Selectable Input Sources (see Table11-2). Section17.0 “Quadrature Updated the definition for the INTHLD<31:0> bits (see Register17-19 and Encoder Interface (QEI) Module Register17-20). (dsPIC33EPXXXMU806/810/814 Devices Only)”  2009-2012 Microchip Technology Inc. DS70616G-page 601

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section21.0 “Enhanced CAN Added the CANCKS bit to the ECAN Control Register 1 (CiCTRL1) (ECAN™) Module” (see Register21-1). Section22.0 “USB On-The-Go Removed the USB 3.3V Regulator logic from the USB Interface Diagram (OTG) Module” (see Figure22-1). Section23.0 “10-bit/12-bit Updated the ADC Conversion Clock Period Block Diagram (see Figure23-2). Analog-to-Digital Converter (ADC)” Section29.0 “Special Features” Updated the last paragraph of Section29.1 “Configuration Bits” Added a note box after the last paragraph of Section29.3 “BOR: Brown-out Reset (BOR)”. Added the RTSP Effect column to the Configuration Bits Description (see Table29-2). Section30.0 “Instruction Set Updated all Status Flags Affected to None for the MOV instruction and added Summary” Note 2 (see Table30-2). Section32.0 “Electrical Updated the Absolute Maximum Ratings (see page 457). Characteristics” Added Note 1 to the Operating MIPS vs. Voltage (see Table32-1). Added parameter DI31 (ICNPD) to the I/O Pin Input Specifications (see Table32-9). Updated the Minimum value for parameter DO26 in the I/O Pin Output Specifications (see Table32-10). Updated the Minimum value for parameter D132b and the Minimum and Maximum values for parameters D136a, D136b, D137a, D137b, D138a, and D138b in the Program Memory specification (see Table32-12). Updated the Minimum, Typical, and Maximum values for parameter OS10 (Oscillator Crystal Frequency: SOSC) in the External Clock Timing Requirements (see Table32-16). Added Note 2 to the PLL Clock Timing Specifications (see Table32-17). Updated all Timer1 External Clock Timing Requirements (see Table32-23). Replaced Table 32-34 with Timer2, Timer4, Timer6, Timer8 External Clock Timing Requirements and Timer3, Timer5, Timer7, Timer9 External Clock Timing Requirements (see Table32-24 and Table32-25, respectively). Updated the Maximum value for parameter OC15 and the Minimum value for parameter OC20 in the OC/PWM Mode Timing Requirements (see Table32-29). Updated the Operating Temperature in the ECAN Module I/O Timing Requirements and USB OTG Timing Requirements (see Table32-51 and Table32-53, respectively). Updated all SPI specifications (see Figure32-15 through Figure32-30 and Table32-33 through Table32-48). Removed Note 4 from the DCI Module Timing Requirements (see Table32-59). Updated the Standard Operating Conditions voltage for the Comparator Specifications (see Table32-61 through Table32-64). DS70616G-page 602  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Revision D (August 2011) The following pin name changes were implemented throughout the document: This revision includes minor typographical and • C1INA renamed to C1IN1+ formatting changes throughout the data sheet text. • C1INB renamed to C1IN2- The Data Converter Interface (DCI) module is available • C1INC renamed to C1IN1- on all dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 devices. References • C1IND renamed to C1IN3- throughout the document have been updated • C2INA renamed to C2IN1+ accordingly. • C2INB renamed to C2IN2- • C2INC renamed to C2IN1- • C2IND renamed to C2IN3- • C3INA renamed to C3IN1+ • C3INB renamed to C3IN2- • C3INC renamed to C3IN1- • C3IND renamed to C3IN3- The other major changes are referenced by their respective section in TableA-3. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description Section1.0 “Device Overview” Added Section1.1 “Referenced Sources”. Section2.0 “Guidelines for Getting Updated the Note in Section2.1 “Basic Connection Requirements”. Started with 16-bit Digital Signal Controllers and Microcontrollers” Section3.0 “CPU” Updated Section3.1 “Registers”. Section4.0 “Memory Organization” Updated FIGURE 4-3: “Data Memory Map for dsPIC33EP512MU810/814 Devices with 52 KB RAM” and FIGURE 4-5: “Data Memory Map for dsPIC33EP256MU806/810/814 Devices with 28 KB RAM”. Updated the IFS3, IEC3, IPC14, and IPC15 SFRs in the Interrupt Controller Register Map (see Table4-6). Updated the SMPI bits for the AD1CON2 and AD2CON2 SFRs in the ADC1 and ADC2 Register Map (see Table4-23). Updated the All Resets values for the CLKDIV and PLLFBD SFRs and removed the SBOREN bit in the System Control Register Map (see Table4-43). Section6.0 “Resets” Removed the SBOREN bit and Notes 3 and 4 from the Reset Control Register (see Register6-1). Section8.0 “Direct Memory Access Removed Note 2 from the DMA Channel x IRQ Select Register (see (DMA)” Register8-2). Section9.0 “Oscillator Updated the PLL Block Diagram (see Figure9-2). Configuration” Updated the value at PORT and the default designations for the DOZE<2:0>, FRCDIV<2:0>, and PLLPOST<1:0> bits in the Clock Divisor Register and the PLLDIV<8:0> bits in the PLLFBD register (see Register9-2 and Register9-3). Section23.0 “10-bit/12-bit Analog- Added Note 4 and updated the ADC Buffer names in the ADCx Module to-Digital Converter (ADC)” Block Diagram (see Figure23-1). Added Note 3 to the ADCx Control Register 1 (see Register23-1). Added the new ADC2 Control Register 2 (see Register23-3). Updated the SMPI<4:0> bit value definitions in the ADC1 Control Register 2 (see Register23-2).  2009-2012 Microchip Technology Inc. DS70616G-page 603

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 TABLE A-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section25.0 “Comparator Module” Updated the Comparator I/O Operating Modes diagram (see Figure25-1). Added Note 2 to the Comparator Voltage Reference Control Register (see Register25-6). Section29.0 “Special Features” Added Note 3 to the Connections for the On-chip Voltage Regulator (see Figure29-1). Section32.0 “Electrical Removed the Voltage on VCAP with respect to VSS from the Absolute Characteristics” Maximum Ratings(1). Removed Note 3 and parameter DC18 from the DC Temperature and Voltage Specifications (see Table32-4). Updated the notes in the DC Characteristics: Operating Current (IDD) (see Table32-5). Updated the notes in the DC Characteristics: Idle Current (IIDLE) (see Table32-6). Updated the Typical and Maximum values for parameter DC60c and the notes in the DC Characteristics: Power-down Current (IPD) (see Table32-7). Updated the notes in the DC Characteristics: Doze Current (IDOZE) (see Table32-8). Updated the conditions for parameters DI60a and DI60b (see Table32-9). Updated the conditions for parameter BO10 in the BOR Electrical Characteristics (see Table32-10). Added Note 1 to the Internal Voltage Regulator Specifications (see Table32-13). Updated the Minimum and Maximum values for parameter OS53 in the PLL Clock Timing Specifications (see Table32-17). Updated the Minimum and Maximum values for parameter F21b in the Internal LPRC Accuracy specifications (see Table32-20). Added Note 2 to the ADC Module Specifications (see Table32-54). DS70616G-page 604  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Revision E (August 2011) This revision includes the following updates to Section32.0 “Electrical Characteristics”: • The maximum HS value for parameter OS10 was updated (see Table32-16) • The OC/PWM Module Timing Characteristics for OCx were updated (see Figure32-10) • The Maximum Data Rate values were updated for the SPI1, SPI3, and SPI4 Maximum Data/Clock Rate Summary (see Table32-33) • These SPI1, SPI3, and SPI4 Timing Requirements were updated: - Maximum value for parameter SP10 and the minimum clock period value for SCKx in Note 3 (see Table32-34, Table32-35, and Table32-36) - Maximum value for parameter SP70 and the minimum clock period value for SCKx in Note 3 (see Table32-38 and Table32-40) • The Maximum Data Rate values were updated for the SPI2 Maximum Data/Clock Rate Summary (see Table32-41) • These SPI2 Timing Requirements were updated: - Maximum value for parameter SP10 and the minimum clock period value for SCKx in Note 3 (see Table32-42, Table32-43, and Table32-44) - Maximum value for parameter SP70 and the minimum clock period value for SCKx in Note 3 (see Table32-45 through Table32-48) - Minimum value for parameters SP40 and SP41 see Table32-43 through Table32-48) • These ADC Module Specifications were updated (see Table32-54): - Minimum value for parameter AD05 - Maximum value for parameter AD06 - Minimum value for parameter AD07  2009-2012 Microchip Technology Inc. DS70616G-page 605

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Revision F (February 2012) In addition, where applicable, new sections were added to each peripheral chapter that provide information and This revision includes typographical and formatting links to related resources, as well as helpful tips. For changes throughout the data sheet text. examples, see Section18.1 “SPI Helpful Tips” and Throughout the document, references to the package Section18.2 “SPI Resources”. The major changes formerly known as XBGA where changed to TFBGA. are referenced by their respective section in TableA-4. TABLE A-4: MAJOR SECTION UPDATES Section Name Update Description “16-Bit Microcontrollers and The content on the first page of this section was extensively reworked to Digital Signal Controllers with provide the reader with the key features and functionality of this device family in High-Speed PWM, USB and an “at-a-glance” format. Advanced Analog” The following devices were added to the Controller Families table (see Table1 and the “Pin Diagrams” section): • dsPIC33EP512MC806 • dsPIC33EP512GP806 • PIC24EP512GP806 Section2.0 “Guidelines for Added Section2.9 “Application Examples” Getting Started with 16-Bit Digital Signal Controllers and Microcontrollers” Section3.0 “CPU” Updated the Status Register information in the Programmer’s Model (see Figure3-2). Section4.0 “Memory Added Interrupt Controller Register Maps (see Table4-6 and Table4-7). Organization” Added Peripheral Pin Select Output Register Map (see Table4-39). Added PMD Register Maps (see Table4-50 and Table4-51). Added PORTF Register Map (see Table4-64). Added PORTG Register Map (see Table4-67). Updated the second note in Section4.7 “Bit-Reversed Addressing (dsPIC33EPXXXMU806/810/814 Devices Only)”. Section11.0 “I/O Ports” Added RPOR10: Peripheral Pin Select Output Register 10 (see Register11-54). Section14.0 “Input Capture” Updated the Input Capture Module Block Diagram (see Figure14-1). Section15.0 “Output Compare” Updated the Output Compare Module Block Diagram (see Figure15-1). Section25.0 “Comparator Updated the User-programmable Blanking Function Block Diagram (see Module” Figure25-3). Updated the bit definitions in the Comparator Mask Gating Control Register (see Register25-4). Section29.0 “Special Features” Added Note 3 to the Configuration Bits Description (see Table29-2). Section32.0 “Electrical Updated the I/O pin Absolute Maximum Ratings. Characteristics” Updated Note 1 in the DC Characteristics: Operating Current (see Table32-5). Updated Note 1 in the DC Characteristics: Idle Current (see Table32-6). Updated Note 1 in the DC Characteristics: Power-down Current (see Table32-7). Updated Note 1 in the DC Characteristics: Doze Current (see Table32-8). Removed parameters DO16 and DO26, added parameter DO26a, updated parameters DO10 and DO20, and added Note 1 in the DC Characteristics: I/O Pin Output Specifications (see Table32-10). DS70616G-page 606  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Revision G (October 2012) This revision includes updates to the packaging diagrams in Section34.0 “Packaging Information”. Preliminary has been removed and there are minor text edits throughout the document.  2009-2012 Microchip Technology Inc. DS70616G-page 607

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 608  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 INDEX A Type B Timerx (Timer2, Timer4, Timer6, Timer8)....276 Type B, Type C Timer Pair (32-Bit Timer)................277 AC Characteristics............................................................511 Type C Timerx (Timer3, Timer5, Timer7, Timer9)....276 Capacitive Loading Requirements on U1RX Remappable Input..........................................210 Output Pins.......................................................511 UARTx Module.........................................................353 Comparator...............................................................567 USB Interface...........................................................386 Comparator Reference Voltage Settling Time..........568 User-Programmable Blanking Function....................438 I/O Timing Requirements..........................................515 Watchdog Timer (WDT)............................................482 Internal FRC Accuracy..............................................514 Brown-out Reset (BOR)....................................................481 Internal LPRC Accuracy............................................514 Load Conditions........................................................511 C Temperature and Voltage Specifications..................511 C Compilers ADC MPLAB C18..............................................................496 Control Registers......................................................417 Code Examples Helpful Tips...............................................................416 Connecting IC1 to HOME1 Digital Filter Input Key Features.............................................................413 on Pin 3............................................................217 Resources.................................................................416 Port Write/Read........................................................209 Analog-to-Digital Converter (ADC)....................................413 PWRSAV Instruction Syntax....................................191 Arithmetic Logic Unit (ALU).................................................46 Code Protection................................................................483 Assembler CodeGuard Security.........................................................483 MPASM Assembler...................................................496 Comparator B Control Registers......................................................440 Resources................................................................439 Bit-Reversed Addressing..................................................131 Configuration Bits.............................................................477 Example....................................................................132 Description................................................................478 Implementation.........................................................131 Configuration Register Map..............................................477 Sequence Table (16-Entry).......................................132 CPU Block Diagrams Addressing Modes......................................................37 16-Bit Timer1 Module................................................271 Control Registers........................................................42 ADCx Conversion Clock Period................................415 Data Space Addressing..............................................37 ADCx Module............................................................414 Instruction Set.............................................................37 APLL Module............................................................180 Resources..................................................................41 Comparator I/O Operating Modes.............................437 CRC Comparator Voltage Reference................................438 Overview...................................................................462 Connections for On-Chip Voltage Regulator.............481 Registers..................................................................463 CPU Core....................................................................38 Resources................................................................462 CRC Shift Engine......................................................461 Customer Change Notification Service.............................616 DCI Module...............................................................429 Customer Notification Service..........................................616 Digital Filter Interconnect..........................................439 Customer Support.............................................................616 DMA Controller.........................................................159 DMA Controller to Peripheral Associations...............161 D dsPIC33EPXXX(GP/MC/MU)806/810/814 and Data Address Space...........................................................49 PIC24EPXXX(GP/GU)810/814...........................24 Memory Map for dsPIC33EP256MU806/810/814 ECAN Module...........................................................360 Devices with 28-Kbyte RAM....................................52 EDS Arbiter Architecture...........................................127 Memory Map for dsPIC33EP512(GP/MC/MU)806/810/814 EDS Read Address Generation................................122 Devices with 52-Kbyte RAM....................................50 EDS Write Address Generation................................123 Memory Map for PIC24EP256GU810/814 Devices High-Speed PWM Architectural Overview................294 with 28-Kbyte RAM..................................................53 High-Speed PWM Register Interconnection.............295 Memory Map for PIC24EP512(GP/GU)806/810/814 I2C Module................................................................346 Devices with 52-Kbyte RAM.................................51 Input Capture Module...............................................281 Near Data Space........................................................49 Multiplexing of Remappable Output for RPn.............215 Organization and Alignment.......................................49 Oscillator System......................................................178 SFR............................................................................49 Output Compare Module...........................................287 Width..........................................................................49 PLL Module...............................................................179 Data Converter Interface (DCI) Module............................429 PMP Module Pinout, Connections to Data Memory External Devices...............................................467 Paged Space............................................................124 Programmable CRC Module.....................................461 Data Space Quadrature Encoder Interface Module......................322 Extended X...............................................................126 Reset System............................................................141 DC and AC Characteristics RTCC Module...........................................................450 Graphs and Tables...................................................573 Shared Port Structure...............................................208 SPIx module..............................................................337  2009-2012 Microchip Technology Inc. DS70616G-page 609

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 DC Characteristics I Brown-out Reset (BOR)............................................509 I/O Ports............................................................................207 Comparator...............................................................567 Configuring Analog Port Pins....................................209 Comparator Reference Voltage................................568 Helpful Tips...............................................................218 Doze Current (IDOZE)................................................505 Input Change Notification.........................................209 I/O Pin Input Specifications.......................................506 Input Pin Selection....................................................213 I/O Pin Output Specifications....................................509 Open-Drain Configuration.........................................209 Idle Current (IIDLE)....................................................503 Output Selection for Remappable Pins (RPn)..........215 Internal Voltage Regulator Specifications.................510 Parallel I/O (PIO)......................................................207 Operating Current (IDD).............................................502 Peripheral Pin Select (PPS)......................................210 Operating MIPS vs. Voltage......................................500 Resources................................................................219 Power-Down Current (IPD)........................................504 Selectable Input Sources..........................................211 Program Memory......................................................510 Write/Read Timing....................................................209 Temperature and Voltage Specifications..................501 I2C Thermal Operating Conditions..................................500 Control Registers......................................................348 DCI Resources................................................................347 Control Registers......................................................431 In-Circuit Debugger...........................................................483 Introduction...............................................................429 In-Circuit Serial Programming (ICSP)...............................483 Resources.................................................................430 Input Capture....................................................................281 Development Support.......................................................495 Control Registers......................................................283 DMA Controller Resources................................................................282 Control Registers......................................................162 Instruction Addressing Modes..........................................128 Registers File Register Instructions..........................................128 DMA Channel IRQ Select.................................162 Fundamental Modes Supported...............................129 DMA Peripheral Address..................................162 MAC Instructions......................................................129 DMA RAM Primary Start Address.....................162 MCU Instructions......................................................128 DMA RAM Secondary Start Address................162 Move and Accumulator Instructions..........................129 DMA Transfer Count.........................................162 Other Instructions.....................................................129 DMAxCON........................................................162 Instruction Set Resources.................................................................162 Overview...................................................................488 Supported Peripherals..............................................159 Summary..................................................................485 DSP Engine.........................................................................46 Inter-Integrated Circuit (I2C).............................................345 E Internal RC Oscillator Use with WDT...........................................................482 ECAN Module Internet Address...............................................................616 Control Registers......................................................362 Interrupt Control and Status Registers.............................150 Message Buffers.......................................................381 IECx..........................................................................150 Modes of Operation..................................................361 IFSx..........................................................................150 Overview...................................................................359 INTCON1-INTCON4.................................................150 Resources.................................................................361 INTTREG..................................................................150 Electrical Characteristics...................................................499 IPCx..........................................................................150 Absolute Maximum Ratings......................................499 Interrupt Controller AC.............................................................................511 Auxiliary Interrupt Vector..........................................145 Enhanced CAN Module.....................................................359 Interrupt Vector Table (IVT)......................................145 Equations Reset Sequence.......................................................145 Device Operating Frequency....................................179 Resources................................................................150 FAVCO Calculation.....................................................180 Maximum Row Write Time........................................136 J Minimum Row Write Time.........................................136 JTAG Interface..................................................................483 Programming Time...................................................136 Errata..................................................................................20 M F Memory Maps EDS..........................................................................126 Flash Program Memory.....................................................135 Memory Organization.........................................................47 Control Registers......................................................137 Message Buffers Operations................................................................136 ECAN Word 0...........................................................381 RTSP Operation........................................................136 ECAN Word 1...........................................................381 Table Instructions......................................................135 ECAN Word 2...........................................................382 H ECAN Word 7...........................................................384 Microchip Internet Web Site..............................................616 High-Speed PWM.............................................................293 Resources.................................................................296 DS70616G-page 610  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 Modulo Addressing...........................................................130 PWM Applicability...............................................................131 Control Registers......................................................297 Operation Example...................................................130 Q Start and End Address..............................................130 W Address Register Selection..................................130 QEI MPLAB ASM30 Assembler, Linker, Librarian...................496 Control Registers......................................................324 MPLAB Integrated Development Environment Quadrature Encoder Interface (QEI).................................321 Software....................................................................495 Resources................................................................323 MPLAB PM3 Device Programmer....................................498 R MPLAB REAL ICE In-Circuit Emulator System.................497 MPLINK Object Linker/MPLIB Object Librarian................496 RCON Control Register........................................................142 O Reader Response.............................................................617 Oscillator Real-Time Clock and Calender (RTCC)...........................449 Control Registers......................................................182 Register Maps Oscillator Configuration.....................................................177 ADC1 and ADC2........................................................85 Bit Values for Clock Selection...................................181 Comparator...............................................................110 CPU Clocking System...............................................179 CPU Core (dsPIC33EPXXX(GP/MC/MU)806/810/814 Resources.................................................................181 Devices Only)...........................................................55 Output Compare...............................................................287 CPU Core (PIC24EPXXX(GP/GU)810/814 Resources.................................................................288 Devices Only)......................................................57 CRC............................................................................96 P DCI.............................................................................87 Packaging.........................................................................577 DMAC.......................................................................111 Details.......................................................................582 ECAN1 (WIN (C1CTRL) = 0 or 1)...............................90 Marking.............................................................577, 578 ECAN1 (WIN (C1CTRL) = 0)......................................90 Parallel Master Port (PMP)...............................................467 ECAN1 (WIN (C1CTRL) = 1)......................................91 Peripheral Module Disable (PMD)....................................192 ECAN2 (WIN (C2CTRL) = 0 or 1)...............................93 Peripheral Pin Select ECAN2 (WIN (C2CTRL) = 0)......................................93 Control Registers......................................................220 I2C1 and I2C2............................................................82 Peripherals Supported by DMA........................................159 Input Capture 1 through Input Capture 16..................71 Pinout I/O Descriptions (table)............................................25 Interrupt Controller (dsPIC33EPXXXGP806 and PMP PIC24EPXXXGP806 Devices Only).......................66 Control Registers......................................................469 Interrupt Controller (dsPIC33EPXXXMC806 Resources.................................................................468 Devices Only)...........................................................64 Power-Saving Features....................................................191 Interrupt Controller (dsPIC33EPXXXMU806 Clock Frequency, Clock Switching............................191 Devices Only)...........................................................62 Doze Mode................................................................192 Interrupt Controller (dsPIC33EPXXXMU810 Instruction-Based Modes..........................................191 Devices Only)...........................................................60 Idle....................................................................192 Interrupt Controller (dsPIC33EPXXXMU814 Sleep.................................................................191 Devices Only)...........................................................58 Interrupts Coincident with Power Interrupt Controller (PIC24EPXXXGU810/814 Save Instructions..............................................192 Devices Only)...........................................................68 Resources.................................................................193 NVM..........................................................................106 Special Function Registers.......................................193 Output Compare 1 through Output Compare 16........73 Program Address Space.....................................................47 Pad Configuration.....................................................121 Construction..............................................................133 Parallel Master/Slave Port..........................................96 Data Access from Address Generation.....................133 Peripheral Pin Select Input (dsPIC33EPXXX(MC/MU)806 Data Access from Program Memory Using Devices Only).........................................................103 Table Instructions.............................................134 Peripheral Pin Select Input (dsPIC33EPXXXMU810 Memory Map...............................................................47 Devices Only).........................................................101 Table Read Instructions Peripheral Pin Select Input (dsPIC33EPXXXMU814 TBLRDH...........................................................134 Devices Only)...........................................................99 TBLRDL............................................................134 Peripheral Pin Select Input (PIC24EPXXXGU810/814 Program Memory Devices Only).........................................................105 Interrupt and Trap Vectors..........................................48 Peripheral Pin Select Output (dsPIC33EPXXX(GP/MC/ Organization................................................................48 MU)806 and PIC24EPXXXGP806 Reset Vector...............................................................48 Devices Only)...........................................................98 Resources...................................................................54 Peripheral Pin Select Output (dsPIC33EPXXXMU806 Programmable Cyclic Redundancy Check (CRC) Devices Only)...........................................................98 Generator..................................................................461 Peripheral Pin Select Output (dsPIC33EPXXXMU810/814 Programmer’s Model...........................................................39 and PIC24EPXXXGU810/814 Devices Only)........97 Register Description....................................................39  2009-2012 Microchip Technology Inc. DS70616G-page 611

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 PMD (dsPIC33EPXXXGP8XX and UART1, UART2, UART3 and UART4.........................83 PIC24EPXXXGP8XX Devices Only).................109 USB OTG (dsPIC33EPMU806/810/814 and PMD (dsPIC33EPXXXMC806 Devices Only)...........108 PIC24EPGU806/810/814 Devices Only)............88 PMD (dsPIC33EPXXXMU806 Devices Only)...........108 Registers PMD (dsPIC33EPXXXMU810 Devices Only)...........107 ACLKCON3 (Auxiliary Clock Control 3)....................188 PMD (dsPIC33EPXXXMU814 Devices Only)...........107 ACLKDIV3 (Auxiliary Clock Divisor 3)......................189 PMD (PIC24EPXXXGU810/814 Devices Only)........109 AD1CON2 (ADC1 Control 2)....................................419 PORTA (dsPIC33EPXXXMU810/814 and AD1CSSH (ADC1 Input Scan Select High)..............427 PIC24EPXXXGU810/814 Devices Only)..........115 AD2CON2 (ADC2 Control 2)....................................421 PORTB......................................................................115 ADxCHS0 (ADCx Input Channel 0 Select)...............426 PORTC (dsPIC33EPXXX(GP/MC/MU)806 and ADxCHS123 (ADCx Input Channel 1, 2, 3 PIC24EPXXXGP806 Devices Only).................116 Select)..............................................................425 PORTC (dsPIC33EPXXXMU810/814 and ADxCON1 (ADCx Control 1).....................................417 PIC24EPXXXGU810/814 Devices Only)..........115 ADxCON3 (ADCx Control 3).....................................423 PORTD (dsPIC33EPXXX(GP/MC/MU)806 and ADxCON4 (ADCx Control 4).....................................424 PIC24EPXXXGP806 Devices Only).................116 ADxCSSL (ADCx Input Scan Select Low)................427 PORTD (dsPIC33EPXXXMU810/814 and ALCFGRPT (Alarm Configuration)...........................455 PIC24EPXXXGU810/814 Devices Only)..........116 ALRMVAL (Alarm Minutes and Seconds, PORTE (dsPIC33EPXXX(GP/MC/MU)806 and ALRMPTR = 00)...............................................460 PIC24EPXXXGP806 Devices Only).................117 ALRMVAL (Alarm Month and Day Value, PORTE (dsPIC33EPXXXMU810/814 and ALRMPTR = 10)...............................................458 PIC24EPXXXGU810/814 Devices Only)..........117 ALRMVAL (Alarm Weekday and Hours, PORTF (dsPIC33EPXXX(GP/MC)806 and ALRMPTR = 01)...............................................459 PIC24EPXXXGP806 Devices Only).................118 ALTDTRx (PWMx Alternate Dead-Time)..................310 PORTF (dsPIC33EPXXXMU806 Devices Only).......118 AUXCONx (PWM Auxiliary Control x)......................319 PORTF (dsPIC33EPXXXMU810/814 and CHOP (PWM Chop Clock Generator)......................303 PIC24EPXXXGU810/814 Devices Only)..........117 CLKDIV (Clock Divisor)............................................184 PORTG (dsPIC33EPXXX(GP/MC)806 and CMSTAT (Comparator Status).................................440 PIC24EPXXXGP806 Devices Only).................119 CMxCON (Comparator x Control).............................441 PORTG (dsPIC33EPXXXMU806 Devices Only)......119 CMxFLTR (Comparator x Filter Control)...................447 PORTG (dsPIC33EPXXXMU810/814 and CMxMSKCON (Comparator x Mask Gating PIC24EPXXXGU810/814 Devices Only)..........118 Control).............................................................445 PORTH (dsPIC33EPXXXMU814 and CMxMSKSRC (Comparator x Mask Source PIC24EPXXXGU814 Devices Only).................120 Select Control)..................................................443 PORTJ (dsPIC33EPXXXMU814 and CORCON (Core Control)....................................44, 152 PIC24EPXXXGU814 Devices Only).................120 CRCCON1 (CRC Control 1).....................................463 PORTK (dsPIC33EPXXXMU814 and CRCCON2 (CRC Control 2).....................................464 PIC24EPXXXGU814 Devices Only).................121 CRCXORH (CRC XOR Polynomial High).................465 PWM (dsPIC33EPXXX(MC/MU)806/810/814 CRCXORL (CRC XOR Polynomial Low)..................465 Devices Only)...........................................................76 CVRCON (Comparator Voltage PWM Generator 1 (dsPIC33EPXXX(MC/MU)806/810/814 Reference Control)...........................................448 Devices Only)...........................................................76 CxBUFPNT1 (ECANx Filter 0-3 Buffer Pointer)........371 PWM Generator 2 (dsPIC33EPXXX(MC/MU)806/810/814 CxBUFPNT2 (ECANx Filter 4-7 Buffer Pointer)........372 Devices Only)...........................................................77 CxBUFPNT3 (ECANx Filter 8-11 Buffer Pointer)......372 PWM Generator 3 (dsPIC33EPXXX(MC/MU)806/810/814 CxBUFPNT4 (ECANx Filter 12-15 Devices Only)...........................................................77 Buffer Pointer)..................................................373 PWM Generator 4 (dsPIC33EPXXX(MC/MU)806/810/814 CxCFG1 (ECANx Baud Rate Configuration 1).........369 Devices Only)...........................................................78 CxCFG2 (ECANx Baud Rate Configuration 2).........370 PWM Generator 5 (dsPIC33EPXXX(MC/MU)810/814 CxCTRL1 (ECANx Control 1)...................................362 Devices Only)...........................................................78 CxCTRL2 (ECANx Control 2)...................................363 PWM Generator 6 (dsPIC33EPXXX(MC/MU)810/814 CxEC (ECANx Transmit/Receive Error Count).........369 Devices Only)...........................................................79 CxFCTRL (ECANx FIFO Control).............................365 PWM Generator 7 (dsPIC33EPXXX(MC/MU)814 CxFEN1 (ECANx Acceptance Filter Enable)............371 Devices Only)...........................................................79 CxFIFO (ECANx FIFO Status)..................................366 QEI1 (dsPIC33EPXXX(MC/MU)806/810/814 CxFMSKSEL1 (ECANx Filter 7-0 Devices Only)...........................................................80 Mask Selection)................................................375 QEI2 (dsPIC33EPXXX(MC/MU)806/810/814 CxFMSKSEL2 (ECANx Filter 15-8 Devices Only)...........................................................81 Mask Selection)................................................376 Real-Time Clock and Calendar (RTCC)......................96 CxINTE (ECANx Interrupt Enable)...........................368 Reference Clock.......................................................106 CxINTF (ECANx Interrupt Flag)................................367 SPI1, SPI2, SPI3 and SPI4.........................................84 CxRXFnEID (ECANx Acceptance Filter n System Control.........................................................106 Extended Identifier)..........................................375 Timer1 through Timer9...............................................70 DS70616G-page 612  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 CxRXFnSID (ECANx Acceptance Filter n OCxCON2 (Output Compare x Control 2)................291 Standard Identifier)...........................................374 OSCCON (Oscillator Control)...................................182 CxRXFUL1 (ECANx Receive Buffer Full 1)..............378 OSCTUN (FRC Oscillator Tuning)............................187 CxRXFUL2 (ECANx Receive Buffer Full 2)..............378 PADCFG1 (Pad Configuration Control)............454, 476 CxRXMnEID (ECANx Acceptance Filter Mask n PDCx (PWMx Generator Duty Cycle).......................307 Extended Identifier)...........................................377 PHASEx (PWMx Primary Phase Shift).....................308 CxRXMnSID (ECANx Acceptance Filter Mask n PLLFBD (PLL Feedback Divisor).............................186 Standard Identifier)...........................................377 PMADDR (Parallel Master Port Address).................473 CxRXOVF1 (ECANx Receive Buffer Overflow 1).....379 PMAEN (Parallel Master Port Address Enable).......474 CxRXOVF2 (ECANx Receive Buffer Overflow 2).....379 PMCON (Parallel Master Port Control).....................469 CxTRmnCON (ECANx TX/RX Buffer m Control)......380 PMD1 (Peripheral Module Disable Control 1)..........194 CxVEC (ECANx Interrupt Code)...............................364 PMD2 (Peripheral Module Disable Control 2)..........196 DCICON1 (DCI Control 1).........................................431 PMD3 (Peripheral Module Disable Control 3)..........198 DCICON2 (DCI Control 2).........................................432 PMD4 (Peripheral Module Disable Control 4)..........200 DCICON3 (DCI Control 3).........................................433 PMD5 (Peripheral Module Disable Control 5)..........201 DCISTAT (DCI Status)..............................................434 PMD6 (Peripheral Module Disable Control 6)..........203 DMAPPS (DMA Ping-Pong Status)..........................174 PMD7 (Peripheral Module Disable Control 7)..........204 DMAPWC (DMA Peripheral Write PMMODE (Parallel Master Port Mode)....................471 Collision Status)................................................169 PMSTAT (Parallel Master Port Status).....................475 DMARQC (DMA Request Collision Status)..............171 POSxCNTH (Position Counter x High Word)...........330 DMAxCNT (DMA Channel x Transfer Count)...........167 POSxCNTL (Position Counter x Low Word).............330 DMAxCON (DMA Channel x Control).......................163 POSxHLD (Position Counter x Hold)........................330 DMAxPAD (DMA Channel x Peripheral Address).....167 PTCON (PWM Time Base Control)..........................297 DMAxREQ (DMA Channel x IRQ Select).................164 PTCON2 (Primary Master Clock DMAxSTAH (DMA Channel x Start Divider Select 2)...............................................299 Address A, High)...............................................165 PTPER (Primary Master Time Base Period)............299 DMAxSTAL (DMA Channel x Start PWMCAPx (Primary PWMx Time Base Capture)....320 Address A, Low)...............................................165 PWMCONx (PWMx Control)....................................305 DMAxSTBH (DMA Channel x Start QEIxCON (QEIx Control)..........................................324 Address B, High)...............................................166 QEIxGECH (QEIx Greater Than or Equal Compare DMAxSTBL (DMA Channel x Start High Word).............................................................334 Address B, Low)...............................................166 QEIxGECL (QEIx Greater Than or Equal Compare DSADRH (Most Recent DMA Data Space Low Word)..............................................................334 High Address)...................................................168 QEIxICH (QEIx Initialization/Capture High Word)....332 DSADRL (Most Recent DMA Data Space QEIxICL (QEIx Initialization/Capture Low Word)......332 Low Address)....................................................168 QEIxIOC (QEIx I/O Control).....................................326 DTRx (PWMx Dead-Time)........................................310 QEIxLECH (QEIx Less Than or Equal Compare FCLCONx (PWMx Fault Current-Limit Control)........315 High Word).............................................................333 I2CxCON (I2Cx Control)...........................................348 QEIxLECL (QEIx Less Than or Equal Compare I2CxMSK (I2Cx Slave Mode Address Mask)............352 Low Word)..............................................................333 I2CxSTAT (I2Cx Status)...........................................350 QEIxSTAT (QEIx Status)..........................................328 ICxCON1 (Input Capture x Control 1).......................283 RCFGCAL (RTCC Calibration and ICxCON2 (Input Capture x Control 2).......................284 Configuration)...................................................452 INDXxCNTH (Index Counter x High Word)...............331 RCON (Reset Control)..............................................143 INDXxCNTL (Index Counter x Low Word)................331 REFOCON (Reference Oscillator Control)...............190 INDXxHLD (Index Counter x Hold)...........................332 RPINR0 (Peripheral Pin Select Input 0)...................220 INTCON1 (Interrupt Control 1)..................................153 RPINR1 (Peripheral Pin Select Input 1)...................221 INTCON2 (Interrupt Control 2)..................................155 RPINR10 (Peripheral Pin Select Input 10)...............230 INTCON3 (Interrupt Control 3)..................................156 RPINR11 (Peripheral Pin Select Input 11)...............231 INTCON4 (Interrupt Control 4)..................................156 RPINR12 (Peripheral Pin Select Input 12)...............232 INTTREG (Interrupt Control and Status)...................157 RPINR13 (Peripheral Pin Select Input 13)...............233 INTxHLDH (Interval Timer x Hold High Word)..........335 RPINR14 (Peripheral Pin Select Input 14)...............234 INTxHLDL (Interval Timer x Hold Low Word)...........335 RPINR15 (Peripheral Pin Select Input 15)...............235 INTxTMRH (Interval Timer x High Word)..................334 RPINR16 (Peripheral Pin Select Input 16)...............236 INTxTMRL (Interval Timer x Low Word)...................335 RPINR17 (Peripheral Pin Select Input 17)...............237 IOCONx (PWMx I/O Control)....................................312 RPINR18 (Peripheral Pin Select Input 18)...............238 LEBCONx (Leading-Edge Blanking Control)............317 RPINR19 (Peripheral Pin Select Input 19)...............239 LEBDLYx (Leading-Edge Blanking Delay x).............318 RPINR2 (Peripheral Pin Select Input 2)...................222 MDC (PWM Master Duty Cycle)...............................304 RPINR20 (Peripheral Pin Select Input 20)...............240 NVMADR (Nonvolatile Memory Address).................139 RPINR21 (Peripheral Pin Select Input 21)...............241 NVMADRU (Nonvolatile Memory RPINR23 (Peripheral Pin Select Input 23)...............241 Upper Address).................................................139 RPINR24 (Peripheral Pin Select Input 24)...............242 NVMCON (Nonvolatile Memory (NVM) Control).......138 RPINR25 (Peripheral Pin Select Input 25)...............243 NVMKEY (Nonvolatile Memory Key)........................139 RPINR26 (Peripheral Pin Select Input 26)...............244 OCxCON1 (Output Compare x Control 1)................289 RPINR27 (Peripheral Pin Select Input 27)...............245  2009-2012 Microchip Technology Inc. DS70616G-page 613

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 RPINR28 (Peripheral Pin Select Input 28)................246 TxCON (T2CON, T4CON, T6CON or T8CON) RPINR29 (Peripheral Pin Select Input 29)................247 Control).............................................................278 RPINR3 (Peripheral Pin Select Input 3)....................223 TyCON (T3CON, T5CON, T7CON or T9CON) RPINR30 (Peripheral Pin Select Input 30)................248 Control).............................................................279 RPINR31 (Peripheral Pin Select Input 31)................249 UxADDR (USB Address)..........................................394 RPINR32 (Peripheral Pin Select Input 32)................250 UxBDTP1 (USB Buffer Description Table 1)............408 RPINR33 (Peripheral Pin Select Input 33)................251 UxBDTP2 (USB Buffer Description Table 2)............408 RPINR34 (Peripheral Pin Select Input 34)................252 UxBDTP3 (USB Buffer Description Table 3)............409 RPINR35 (Peripheral Pin Select Input 35)................253 UxCNFG1 (USB Configuration 1).............................395 RPINR36 (Peripheral Pin Select Input 36)................254 UxCNFG2 (USB Configuration 2).............................396 RPINR37 (Peripheral Pin Select Input 37)................255 UxCON (USB Control, Device Mode).......................392 RPINR38 (Peripheral Pin Select Input 38)................256 UxCON (USB Control, Host Mode)...........................393 RPINR39 (Peripheral Pin Select Input 39)................257 UxEIE (USB Error Interrupt Enable, RPINR4 (Peripheral Pin Select Input 4)....................224 Device Mode)...................................................405 RPINR40 (Peripheral Pin Select Input 40)................258 UxEIE (USB Error Interrupt Enable, Host Mode)......406 RPINR41 (Peripheral Pin Select Input 41)................259 UxEIR (USB Error Interrupt Status, RPINR42 (Peripheral Pin Select Input 42)................260 Device Mode)...................................................403 RPINR43 (Peripheral Pin Select Input 43)................261 UxEIR (USB Error Interrupt Status, Host Mode).......404 RPINR5 (Peripheral Pin Select Input 5)....................225 UxEPn (USB Endpoint n Control).............................407 RPINR6 (Peripheral Pin Select Input 6)....................226 UxFRMH (USB Frame Number High).......................410 RPINR7 (Peripheral Pin Select Input 7)....................227 UxFRML (USB Frame Number Low)........................411 RPINR8 (Peripheral Pin Select Input 8)....................228 UxIE (USB Interrupt Enable, Device Mode)..............401 RPINR9 (Peripheral Pin Select Input 9)....................229 UxIE (USB Interrupt Enable, Host Mode).................402 RPOR0 (Peripheral Pin Select Output 0)..................261 UxIR (USB Interrupt Status, Device Mode Only)......399 RPOR1 (Peripheral Pin Select Output 1)..................262 UxIR (USB Interrupt Status, Host Mode Only)..........400 RPOR10 (Peripheral Pin Select Output 10)..............266 UxMODE (UARTx Mode)..........................................355 RPOR11 (Peripheral Pin Select Output 11)..............267 UxOTGCON (USB OTG Control).............................389 RPOR12 (Peripheral Pin Select Output 12)..............267 UxOTGIE (USB OTG Interrupt Enable, RPOR13 (Peripheral Pin Select Output 13)..............268 Host Mode Only)...............................................398 RPOR14 (Peripheral Pin Select Output 14)..............268 UxOTGIR (USB OTG Interrupt Status, RPOR15 (Peripheral Pin Select Output 15)..............269 Host Mode Only)...............................................397 RPOR2 (Peripheral Pin Select Output 2)..................262 UxOTGSTAT (USB OTG Status)..............................388 RPOR3 (Peripheral Pin Select Output 3)..................263 UxPWMCON (USB VBUS PWM RPOR4 (Peripheral Pin Select Output 4)..................263 Generator Control)............................................409 RPOR5 (Peripheral Pin Select Output 5)..................264 UxPWMRRS (Duty Cycle and PWM Period)............410 RPOR6 (Peripheral Pin Select Output 6)..................264 UxPWRC (USB Power Control)................................390 RPOR7 (Peripheral Pin Select Output 7)..................265 UxSOF (USB OTG Start-of-Token Threshold, RPOR8 (Peripheral Pin Select Output 8)..................265 Host Mode Only)...............................................395 RPOR9 (Peripheral Pin Select Output 9)..................266 UxSTA (UARTx Status and Control).........................357 RSCON (DCI Receive Slot Control)..........................435 UxSTAT (USB Status)..............................................391 RTCVAL (Minutes and Seconds Value, UxTOK (USB Token, Host Mode Only)....................394 RTCPTR = 00)..................................................457 VELxCNT (Velocity Counter x).................................331 RTCVAL (Month and Day Value, Resets...............................................................................141 RTCPTR = 10)..................................................456 Brown-out Reset (BOR)............................................141 RTCVAL (Weekday and Hours Value, Configuration Mismatch Reset (CM).........................141 RTCPTR = 01)..................................................457 Illegal Condition Device Reset (IOPUWR)................141 RTCVAL (Year Value Register, RTCPTR = 11)........456 Illegal Opcode...........................................................141 SDCx (PWMx Secondary Duty Cycle)......................307 Master Clear Pin Reset (MCLR................................141 SEVTCMP (PWM Primary Special Power-on Reset (POR).............................................141 Event Compare)................................................300 RESET Instruction (SWR)........................................141 SPHASEx (PWMx Secondary Phase Shift)..............309 Security Reset..........................................................141 SPIxCON1 (SPIx Control 1)......................................341 Trap Conflict Reset (TRAPR)...................................141 SPIxCON2 (SPIx Control 2)......................................343 Uninitialized W Register............................................141 SPIxSTAT (SPIx Status and Control).......................339 Watchdog Timer Reset (WDTO)...............................141 SR (CPU Status).................................................42, 151 Resources Required for Digital PFC.............................34, 36 SSEVTCMP (PWM Secondary Special Revision History................................................................597 Event Compare)................................................303 RTCC STCON (PWM Secondary Master Time Base Resources................................................................451 Control).............................................................301 Writing to the Timer..................................................451 STCON2 (PWM Secondary Clock Divider Select 2)................................................302 T1CON (Timer1 Control)...........................................273 TRGCONx (PWMx Trigger Control)..........................311 TRIGx (PWM Primary Trigger Compare Value)........314 TSCON (DCI Transmit Slot Control).........................435 DS70616G-page 614  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 S SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0)................................536 Serial Peripheral Interface (SPI).......................................337 SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, Software Simulator (MPLAB SIM).....................................497 CKE = 0, CKP = 1, SMP = 0)................................534 Software Stack Pointer, Frame Pointer SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, CALL Stack Frame....................................................128 CKE = 1, CKP = 0, SMP = 0)................................530 Special Features SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, Code Protection........................................................477 CKE = 1, CKP = 1, SMP = 0)................................532 CodeGuard Security.................................................477 SPI2 Master Mode (Full-Duplex, CKE = 0, Flexible Configuration...............................................477 CKP = x, SMP = 1)................................................541 In-Circuit Emulation...................................................477 SPI2 Master Mode (Full-Duplex, CKE = 1, In-Circuit Serial Programming (ICSP).......................477 CKP = x, SMP = 1)................................................540 JTAG Boundary Scan Interface................................477 SPI2 Master Mode (Half-Duplex, Transmit Only, Watchdog Timer (WDT)............................................477 CKE = 0)................................................................538 Special Features of the CPU............................................477 SPI2 Master Mode (Half-Duplex, Transmit Only, SPI CKE = 1)................................................................539 Control Registers......................................................339 SPI2 Slave Mode (Full-Duplex, CKE = 0, Helpful Tips...............................................................338 CKP = 0, SMP = 0)................................................548 Resources.................................................................338 SPI2 Slave Mode (Full-Duplex, CKE = 0, Symbols Used in Opcode Descriptions.............................486 CKP = 1, SMP = 0)................................................546 T SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0)................................................542 Timer1...............................................................................271 SPI2 Slave Mode (Full-Duplex, CKE = 1, Control Register........................................................273 CKP = 1, SMP = 0)................................................544 Timer2/3, Timer4/5, Timer6/7 and Timer8/9.....................275 Timer1-Timer9 External Clock..................................518 Timerx/y TimerQ (QEI Module) External Clock.......................520 Control Registers......................................................278 UARTx I/O................................................................554 Timing Diagrams Timing Specifications 10-Bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, 10-Bit ADC Conversion Requirements.....................562 ASAM = 0, SSRC<2:0> = 000, SSRCG = 0).......561 12-Bit Mode ADC Conversion Requirements...........560 10-Bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, ADC..........................................................................556 ASAM = 1, SSRC<2:0> = 111, SSRCG = 0, ADC (10-Bit Mode)...................................................558 SAMC<4:0> = 00010)............................................561 ADC (12-Bit Mode)...................................................557 12-Bit ADC Conversion (12-Bit Mode, ASAM = 0, Auxiliary PLL Clock...................................................513 SSRC<2:0> = 000, SSRCG = 0)...........................559 DCI AC-Link Mode....................................................566 BOR and Master Clear Reset...................................517 DCI AC-Link Mode....................................................565 DCI Multi-Channel, I2S Modes.................................564 DCI Multi -Channel, I2S Modes.................................563 DMA Module.............................................................571 ECAN I/O..................................................................554 ECAN I/O..................................................................554 External Clock...........................................................512 External Clock Requirements...................................512 High-Speed PWMx (dsPIC33EPXXX(MC/MU)806/ High-Speed PWMx Requirements (dsPIC33EPXXX (MC/MU)806/810/814 Devices)........................523 810/814 Devices)...................................................523 I2Cx Bus Data Requirements (Master Mode)...........551 High-Speed PWMx Fault (dsPIC33EPXXX(MC/MU) 806/810/814 Devices)............................................523 I2Cx Bus Data Requirements (Slave Mode).............553 I/O Pins.....................................................................515 Input Capture (ICx) Requirements............................521 OCx/PWMx Mode Requirements.............................522 I2Cx Bus Data (Master Mode)..................................550 I2Cx Bus Data (Slave Mode)....................................552 Output Compare (OCx) Requirements.....................522 I2Cx Bus Start/Stop Bits (Master Mode)...................550 Parallel Master Port Read........................................570 I2Cx Bus Start/Stop Bits (Slave Mode).....................552 Parallel Master Port Write.........................................571 Parallel Slave Port....................................................569 Input Capture (ICx)...................................................521 OCx/PWMx...............................................................522 PLL Clock.................................................................513 Output Compare (OCx).............................................522 QEI External Clock Requirements............................520 Parallel Master Port Read.........................................570 QEI Index Pulse Requirements................................525 Quadrature Decoder Requirements.........................524 Parallel Master Port Write.........................................571 Parallel Slave Port....................................................569 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-on Reset........................................................516 Power-up Timer Requirements.............................517 SPI1, SPI3 and SPI4 Master Mode (Full-Duplex, QEA/QEB Input.........................................................524 CKE = 0, CKP = x, SMP = 1)................................529 QEI Module Index Pulse...........................................525 SPI1, SPI3 and SPI4 Master Mode (Full-Duplex, SPI1, SPI3 and SPI4 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1)............................529 CKE = 1, CKP = x, SMP = 1)................................528 SPI1, SPI3 and SPI4 Master Mode (Half-Duplex, SPI1, SPI3 and SPI4 Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1)............................528 Transmit Only).......................................................527 SPI1, SPI3 and SPI4 Master Mode (Half-Duplex, SPI1, SPI3 and SPI4 Maximum Data/Clock Transmit Only, CKE = 0)...................................526 Rate Summary.......................................................526 SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, SPI1, SPI3 and SPI4 Master Mode (Half-Duplex, Transmit Only, CKE = 1)...................................527 CKE = 0, CKP = 0, SMP = 0)................................537  2009-2012 Microchip Technology Inc. DS70616G-page 615

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, U CKE = 0, CKP = 1, SMP = 0).................................535 UARTx SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, Control Registers......................................................355 CKE = 1, CKP = 0, SMP = 0).................................531 Helpful Tips...............................................................354 SPI1, SPI3 and SPI4 Slave Mode (Full-Duplex, Resources................................................................354 CKE = 1, CKP = 1, SMP = 0).................................533 Universal Asynchronous Receiver SPI2 Master Mode (Full-Duplex, CKE = 0, Transmitter (UART)..................................................353 CKP = x, SMP = 1).................................................541 USB On-The-Go (OTG)....................................................385 SPI2 Master Mode (Full-Duplex, CKE = 1, Clearing Interrupts....................................................385 CKP = x, SMP = 1).................................................540 Control Registers......................................................388 SPI2 Master Mode (Half-Duplex, Transmit Only)...........539 Overview...................................................................385 SPI2 Slave Mode (Full-Duplex, CKE = 0, Resources................................................................387 CKP = 0, SMP = 0).................................................549 SPI2 Slave Mode (Full-Duplex, CKE = 0, V CKP = 1, SMP = 0).................................................547 Voltage Regulator (On-Chip)............................................481 SPI2 Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0).................................................543 W SPI2 Slave Mode (Full-Duplex, CKE = 1, Watchdog Timer (WDT)....................................................482 CKP = 1, SMP = 0).................................................545 Programming Considerations...................................482 Timer1 External Clock Requirements.............................518 WWW Address.................................................................616 Timer2, Timer4, Timer6, Timer8 External WWW, On-Line Support.....................................................20 Clock Requirements...............................................519 Timer3, Timer5, Timer7, Timer9 External Clock Requirements...............................................519 UARTx I/O.......................................................................554 USB OTG (dsPIC33EPXXXMU8XX, PIC24EPXXXGU8XX Devices).............................555 DS70616G-page 616  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design • Development Systems Information Line resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQs), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2009-2012 Microchip Technology Inc. DS70616G-page 617

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC33EPXXX(GP/MC/MU)806/810/814 and Literature Number: DS70616G PIC24EPXXX(GP/GU)810/814 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70616G-page 618  2009-2012 Microchip Technology Inc.

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 EP 512 MU8 14 T -E / PH - XXX Examples: a) dsPIC33EP512MU814T-E/PH: Microchip Trademark Motor Control with USB dsPIC33, 512KB program memory, 144-pin, Architecture Extended temperature, TQFP package. Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller 24 = 16-bit Microcontroller Flash Memory Family: EP = Enhanced Performance Product Group: MU8 = Motor Control family with USB GU8 = General Purpose family with USB Pin Count: 06 = 64-pin 10 = 100-pin, 121-pin 14 = 144-pin Temperature Range: I = -40C to+85C (Industrial) E = -40C to+125C (Extended) Package: PT = 10x10 or 12x12 mm TQFP (Thin Quad Flatpack) PF = 14x14 mm TQFP (Thin Quad Flatpack) MR = 9x9 mm QFN (Plastic Quad Flatpack) BG = 10x10 mm TFBGA (Plastic Thin Profile Ball Grid Array ) PH = 16x16 mm TQFP (Thin Quad Flatpack) PL = 20x20 mm LQFP (Low-Profile Quad Flatpack)  2009-2012 Microchip Technology Inc. DS70616G-page 619

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814 NOTES: DS70616G-page 620  2009-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2009-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-624-8 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2009-2012 Microchip Technology Inc. DS70616G-page 621

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC24EP256GU810-E/BG PIC24EP256GU810-I/BG PIC24EP256GU810T-I/BG PIC24EP512GU810-E/BG PIC24EP512GU810-I/BG PIC24EP512GU810T-I/BG dsPIC33EP256MU810-I/PF dsPIC33EP512MU810-I/PT dsPIC33EP512MU814-I/PH dsPIC33EP512MU814-I/PL PIC24EP256GU810-E/PF PIC24EP256GU810-E/PT PIC24EP256GU810-I/PF PIC24EP256GU810-I/PT PIC24EP256GU810T-I/PF PIC24EP256GU810T-I/PT PIC24EP256GU814-E/PH PIC24EP256GU814-E/PL PIC24EP256GU814-I/PH PIC24EP256GU814-I/PL PIC24EP512GU810-E/PF PIC24EP512GU810-E/PT PIC24EP512GU810-I/PF PIC24EP512GU810-I/PT PIC24EP512GU810T-I/PF PIC24EP512GU810T-I/PT PIC24EP512GU814-E/PH PIC24EP512GU814-E/PL PIC24EP512GU814-I/PH PIC24EP512GU814-I/PL dsPIC33EP512GP806-E/MR dsPIC33EP512GP806-E/PT dsPIC33EP512GP806-I/MR dsPIC33EP512GP806-I/PT dsPIC33EP512GP806T-E/MR dsPIC33EP512GP806T-E/PT dsPIC33EP512GP806T-I/MR dsPIC33EP512GP806T-I/PT dsPIC33EP512MC806-E/MR dsPIC33EP512MC806-E/PT dsPIC33EP512MC806-I/MR dsPIC33EP512MC806-I/PT dsPIC33EP512MC806T-E/MR dsPIC33EP512MC806T-E/PT dsPIC33EP512MC806T-I/MR dsPIC33EP512MC806T-I/PT PIC24EP512GP806-E/MR PIC24EP512GP806-E/PT PIC24EP512GP806-I/MR PIC24EP512GP806-I/PT PIC24EP512GP806T-E/MR PIC24EP512GP806T-E/PT PIC24EP512GP806T-I/MR PIC24EP512GP806T-I/PT dsPIC33EP256MU810T-E/PF dsPIC33EP256MU810T-E/PT dsPIC33EP256MU810T-E/BG DSPIC33EP256MU810-E/PF DSPIC33EP256MU810-E/PT DSPIC33EP256MU810-I/PF DSPIC33EP256MU810-I/PT DSPIC33EP256MU810T-I/PF DSPIC33EP256MU810T-I/PT DSPIC33EP256MU814- E/PH DSPIC33EP256MU814-E/PL DSPIC33EP256MU814-I/PH DSPIC33EP256MU814-I/PL DSPIC33EP512MU810- E/PF DSPIC33EP512MU810-E/PT DSPIC33EP512MU810-I/PF DSPIC33EP512MU810-I/PT DSPIC33EP512MU810T-I/PF DSPIC33EP512MU810T-I/PT DSPIC33EP512MU814-E/PH DSPIC33EP512MU814- E/PL DSPIC33EP512MU814-I/PH DSPIC33EP512MU814-I/PL DSPIC33EP256MU810-E/BG DSPIC33EP256MU810- I/BG DSPIC33EP256MU810T-I/BG DSPIC33EP512MU810-E/BG DSPIC33EP512MU810-I/BG DSPIC33EP512MU810T-I/BG DSPIC33EP512GP806-E/MR DSPIC33EP512GP806-E/PT DSPIC33EP512GP806- I/MR DSPIC33EP512GP806-I/PT DSPIC33EP512GP806T-E/MR DSPIC33EP512GP806T-E/PT DSPIC33EP512GP806T-I/MR DSPIC33EP512GP806T-I/PT DSPIC33EP512MC806-E/MR DSPIC33EP512MC806- E/PT DSPIC33EP512MC806-I/MR DSPIC33EP512MC806-I/PT DSPIC33EP512MC806T-E/MR DSPIC33EP512MC806T-E/PT DSPIC33EP512MC806T-I/MR DSPIC33EP512MC806T-I/PT DSPIC33EP256MU810T- E/BG