PIC18F66K80 FAMILY 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ XLP Technology Power-Managed Modes: ECAN Bus Module Features (Continued): • Run: CPU on, Peripherals on • 16 Full, 29-Bit Acceptance Filters with Dynamic • Idle: CPU off, Peripherals on Association • Sleep: CPU off, Peripherals off • Three Full, 29-Bit Acceptance Masks • Two-Speed Oscillator Start-up • Automatic Remote Frame Handling • Fail-Safe Clock Monitor (FSCM) • Advanced Error Management Features • Power-Saving Peripheral Module Disable (PMD) Special Microcontroller Features: • Ultra Low-Power Wake-up • Operating Voltage Range: 1.8V to 5.5V • Fast Wake-up, 1 s, Typical • On-Chip 3.3V Regulator • Low-Power WDT, 300 nA, Typical • Operating Speed up to 64 MHz • Run mode Currents Down to Very Low 3.8 A, Typical • Up to 64Kbytes On-Chip Flash Program Memory: • Idle mode Currents Down to Very Low 880 nA, Typical - 10,000 erase/write cycle, typical • Sleep mode Current Down to Very Low 13 nA, Typical - 20 years minimum retention, typical ECAN Bus Module Features: • 1,024 Bytes of Data EEPROM: - 100,000 Erase/write cycle data EEPROM • Conforms to CAN 2.0B Active Specification memory, typical • Three Operating modes: • 3.6 Kbytes of General Purpose Registers (SRAM) - Legacy mode (full backward compatibility with • Three Internal Oscillators: LF-INTOSC (31KHz), existing PIC18CXX8/FXX8 CAN modules) MF-INTOSC (500kHz) and HF-INTOSC (16MHz) - Enhanced mode • Self-Programmable under Software Control - FIFO mode or programmable TX/RX buffers • Priority Levels for Interrupts • Message Bit Rates up to 1Mbps • 8 x 8 Single-Cycle Hardware Multiplier • DeviceNet™ Data Byte Filter Support • Extended Watchdog Timer (WDT): • Six Programmable Receive/Transmit Buffers - Programmable period from 4ms to 4,194s • In-Circuit Serial Programming™ (ICSP™) via Two Pins • Three Dedicated Transmit Buffers with Prioritization • In-Circuit Debug via Two Pins • Two Dedicated Receive Buffers • Programmable BOR • Programmable LVD TABLE 1: DEVICE COMPARISON s D Device PMreomgroarmy M(BeDymatteoasr )y D(Baytate EsE) Pins I/O CTMU 12-Bit A/DChannels CCP/ECCP Timers8-Bit/16-Bit EUSART Comparator ECAN™ MSSP BORMV/LV DSM PIC18F25K80 32Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No PIC18LF25K80 32Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No PIC18F26K80 64Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No PIC18LF26K80 64Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No PIC18F45K80 32Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No PIC18LF45K80 32Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No PIC18F46K80 64Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No PIC18LF46K80 64Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No PIC18F65K80 32Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes PIC18LF65K80 32Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes PIC18F66K80 64Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes PIC18LF66K80 64Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes  2010-2017 Microchip Technology Inc. DS30009977G-page 1

PIC18F66K80 FAMILY Peripheral Highlights: • High-Current Sink/Source 25mA/25mA (PORTB and PORTC) • Five CCP/ECCP modules: • Up to Four External Interrupts - Four Capture/Compare/PWM (CCP) modules • One Master Synchronous Serial Port - One Enhanced Capture/Compare/PWM (MSSP) module: (ECCP) module - 3/4-wire SPI (supports all four SPI modes) • Five 8/16-Bit Timer/Counter modules: - I2C™ Master and Slave modes - Timer0: 8/16-bit timer/counter with 8-bit • Two Enhanced Addressable USART modules: programmable prescaler - LIN/J2602 support - Timer1, Timer3: 16-bit timer/counter - Auto-Baud Detect (ABD) - Timer2, Timer4: 8-bit timer/counter • 12-Bit A/D Converter with up to 11 Channels: • Two Analog Comparators - Auto-acquisition and Sleep operation • Configurable Reference Clock Output - Differential Input mode of operation • Charge Time Measurement Unit (CTMU): • Data Signal Modulator module: - Capacitance measurement - Select modulator and carrier sources from - Time measurement with 1ns typical resolution various module outputs - Integrated voltage reference • Integrated Voltage Reference DS30009977G-page 2  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY Pin Diagrams 28-Pin QFN(1) 0 BI K S/ L P T C BI3 BI1 1A/ K K P PWU DT2/ KBI2 CP5/ CP1/ AN1 CV/AN0/ULREF R/RE3 PGD/T3G/RX2/ PGC/TX2/CK2/ T0CKI/T3CKI/C AN9/C2INA/EC A1/ A0/ CL B7/ B6/ B5/ B4/ R R M R R R R 8 76 54 3 2 2 22 22 2 2 RA2/VREF-/AN2 1 21 RB3/CANRX/C2OUT/P1D/CTED2/INT3 RA3/VREF+/AN3 2 20 RB2/CANTX/C1OUT/P1C/CTED1/INT2 VDDCORE/VCAP 3 19 RB1/AN8/C1INB/P1B/CTDIN/INT1 PIC18F2XK80 RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI 4 18 RB0/AN10/C1INA/FLT0/INT0 PIC18LF2XK80 VSS 5 17 VDD OSC1/CLKIN/RA7 6 16 VSS OSC2/CLKOUT/RA6 7 15 RC7/CANRX/RX1/DT1/CCP4 0 1 2 3 4 8 91 1 1 1 1 RC0/SOSCO/SCLKI RC1/SOSCI RC2/T1G/CCP2 RC3/REFO/SCL/SCK RC4/SDA/SDI RC5/SDO ANTX/TX1/CK1/CCP3 C 6/ C R Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.  2010-2017 Microchip Technology Inc. DS30009977G-page 3

PIC18F66K80 FAMILY Pin Diagrams (Continued) 28-Pin SSOP/SPDIP/SOIC MCLR/RE3 1 28 RB7/PGD/T3G/RX2/DT2/KBI3 RA0/CVREF/AN0/ULPWU 2 27 RB6/PGC/TX2/CK2/KBI2 RA1/AN1 3 26 RB5/T0CKI/T3CKI/CCP5/KBI1 RA2/VREF-/AN2 4 25 RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0 RA3/VREF+/AN3 5 24 RB3/CANRX/C2OUT/P1D/CTED2/INT3 VDDCORE/VCAP 6 23 RB2/CANTX/C1OUT/P1C/CTED1/INT2 RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI 7 PIC18F2XK80 22 RB1/AN8/C1INB/P1B/CTDIN/INT1 VSS 8 PIC18LF2XK80 21 RB0/AN10/C1INA/FLT0/INT0 OSC1/CLKIN/RA7 9 20 VDD OSC2/CLKOUT/RA6 10 19 VSS RC0/SOSCO/SCLKI 11 18 RC7/CANRX/RX1/DT1/CCP4 RC1/ISOSCI 12 17 RC6/CANTX/TX1/CK1/CCP3 RC2/T1G/CCP2 13 16 RC5/SDO RC3/REFO/SCL/SCK 14 15 RC4/SDA/SDI 40-Pin PDIP MCLR/RE3 1 40 RB7/PGD/T3G/KBI3 RA0/CVREF/AN0/ULPWU 2 39 RB6/PGC/KBI2 RA1/AN1/C1INC 3 38 RB5/T0CKI/T3CKI/CCP5/KBI1 RA2/VREF-/AN2/C2INC 4 37 RB4/AN9/CTPLS/KBI0 RA3/VREF+/AN3 5 36 RB3/CANRX/CTED2/INT3 VDDCORE/VCAP 6 35 RB2/CANTX/CTED1/INT2 RA5/AN4/HLVDIN/T1CKI/SS 7 34 RB1/AN8/CTDIN/INT1 RE0/AN5/RD 8 33 RB0/AN10/FLT0/INT0 RE1/AN6/C1OUT/WR 9 32 VDD RE2/AN7/C2OUT/CS 10 PIC18F4XK80 31 VSS VDD 11 PIC18LF4XK80 30 RD7/RX2/DT2/P1D/PSP7 VSS 12 29 RD6/TX2/CK2/P1C/PSP6 OSC1/CLKIN/RA7 13 28 RD5/P1B/PSP5 OSC2/CLKOUT/RA6 14 27 RD4/ECCP1/P1A/PSP4 RC0/SOSCO/SCLKI 15 26 RC7/CANRX/RX1/DT1/CCP4 RC1/SOSCI 16 25 RC6/CANTX/TX1/CK1/CCP3 RC2/T1G/CCP2 17 24 RC5/SDO RC3/REFO/SCL/SCK 18 23 RC4/SDA/SDI RD0/C1INA/PSP0 19 22 RD3/C2INB/CTMUI/PSP3 RD1/C1INB/PSP1 20 21 RD2/C2INA/PSP2 DS30009977G-page 4  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY Pin Diagrams (Continued) 44-Pin TQFP 3 P C 3 C P K1/ PS K ANTX/TX1/C DO DA/SDI 2INB/CTMUI/ 2INA/PSP2 1INB/PSP1 1INA/PSP0 EFO/SCL/SC 1G/CCP2 OSCI C S S C C C C R T S C6/ C5/ C4/ D3/ D2/ D1/ D0/ C3/ C2/ C1/ C R R R R R R R R R R N/ 4 3 2 10 9 8765 4 4 4 4 44 3 3333 3 RC7/CANRX/RX1/DT1/CCP4 1 33 N/C RD4/ECCP1/P1A/PSP4 2 32 RC0/SOSCO/SCLKI RD5/P1B/PSP5 3 31 OSC2/CLKOUT/RA6 RD6/TX2/CK2/P1C/PSP6 4 30 OSC1/CLKIN/RA7 RD7/RX2/DT2/P1D/PSP7 5 PIC18F4XK80 29 VSS VSS 6 PIC18LF4XK80 28 VDD VDD 7 27 RE2/AN7/C2OUT/CS RB0/AN10/FLT0/INT0 8 26 RE1/AN6/C1OUT/WR RB1/AN8/CTDIN/INT1 9 25 RE0/AN5/RD RB2/CANTX/CTED1/INT2 10 24 RA5/AN4/HLVDIN/T1CKI/SS RB3/CANRX/CTED2/INT3 11 23 VDDCORE/VCAP 2 3 456 7 89 01 2 1 1 111 1 11 22 2 C C 0 1 2 3 3 U C C 3 N/ N/ RB4/AN9/CTPLS/KBI T0CKI/T3CKI/CCP5/KBI RB6/PGC/KBI RB7/PGD/T3G/KBI MCLR/RE RA0/CV/AN0/ULPWREF RA1/AN1/C1IN RA2/V-/AN2/C2INREF RA3/V+/ANREF 5/ B R  2010-2017 Microchip Technology Inc. DS30009977G-page 5

PIC18F66K80 FAMILY Pin Diagrams (Continued) 44-Pin QFN(1) 3 P C 3 C P K1/ PS K ANTX/TX1/C DO DA/SDI 2INB/CTMUI/ 2INA/PSP2 1INB/PSP1 1INA/PSP0 EFO/SCL/SC 1G/CCP2 OSCI C S S C C C C R T S C6/ C5/ C4/ D3/ D2/ D1/ D0/ C3/ C2/ C1/ C R R R R R R R R R R N/ 4 3 2 10 9 87 65 4 4 4 4 44 3 33 33 3 RC7/CANRX/RX1/DT1/CCP4 1 33 N/C RD4/ECCP1/P1A/PSP4 2 32 RC0/SOSCO/SCLKI RD5/P1B/PSP5 3 31 OSC2/CLKOUT/RA6 RD6/TX2/CK2/P1C/PSP6 4 30 OSC1/CLKIN/RA7 RD7/RX2/DT2/P1D/PSP7 5 PIC18F4XK80 29 VSS VSS 6 PIC18LF4XK80 28 VDD VDD 7 27 RE2/AN7/C2OUT/CS RB0/AN10/FLT0/INT0 8 26 RE1/AN6/C1OUT/WR RB1/AN8/CTDIN/INT1 9 25 RE0/AN5/RD RB2/CANTX/CTED1/INT2 10 24 RA5/AN4/HLVDIN/T1CKI/SS RB3/CANRX/CTED2/INT3 11 23 VDDCORE/VCAP 2 3 4 5 6 7 8 90 1 2 1 1 1 1 1 1 1 12 2 2 C C 0 1 2 3 3 U C C 3 N/ N/ RB4/AN9/CTPLS/KBI T0CKI/T3CKI/CCP5/KBI RB6/PGC/KBI RB7/PGD/T3G/KBI MCLR/RE RA0/CV/AN0/ULPWREF RA1/AN1/C1IN RA2/V-/AN2/C2INREF RA3/V+/ANREF 5/ B R Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS. DS30009977G-page 6  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY Pin Diagrams (Continued) 64-Pin QFN(1)/TQFP 3 P S P K CP3 DO DA/SDI X2/CK2 X2/DT2 2INB/CTMUI/ 2INA/PSP2 1INB/PSP1 1INA/PSP0 DOUT EFO/SCL/SC 1G/CCP2 OSCI C S S T R C C C C M R T S C6/ C5/ C4/ E7/ E6/ D3/ D2/ DD SS D1/ D0/ F7 F6/ C3/ C2/ C1/ R R R R R R R V V R R R R R R R 4 3 2 10 9 87 65 4 3 210 9 6 6 6 66 5 55 55 5 5 555 4 48 RC0/SOSCO/SCLKI RC7/CCP4 1 47 OSC2/CLKOUT/RA6 RD4/ECCP1/P1A/PSP4 2 46 OSC1/CLKIN/RA7 RD5/P1B/PSP5 3 45 RF5 RD6/P1C/PSP6 4 44 RF4/MDCIN2 RD7/P1D/PSP7 5 43 VSS RG0/RX1/DT1 6 42 AVSS RG1/CANTX2 7 PIC18F6XK80 41 VDD VSS 8 PIC18LF6XK80 40 AVDD AVDD 9 39 RE2/AN7/C2OUT/CS VDD 10 RG2/T3CKI 11 38 RE1/AN6/C1OUT/WR RG3/TX1/CK1 12 37 RE0/AN5/RD RB0/AN10/FLT0/INT0 13 36 RF3 RB1/AN8/CTDIN/INT1 14 35 RF2/MDCIN1 RB2/CANTX/CTED1/INT2 15 34 RA5/AN4/HLVDIN/T1CKI/SS RB3/CANRX/CTED2/INT3 16 33 VDDCORE/VCAP 7 8 90 12 34 567 89 012 1 1 12 22 22 222 22 333 RF0/MDMIN RG4/T0CKI RF1 RB4/AN9/CTPLS/KBI0 T0CKI/T3CKI/CCP5/KBI1 RB6/PGC/KBI2 RB7/PGD/T3G/KBI3 RE5/CANTX VDD VSS RE4/CANRX MCLR/RE3 A0/CV/AN0/ULPWUREF RA1/AN1/C1INC RA2/V-/AN2/C2INCREF RA3/V+/AN3REF 5/ R B R Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.  2010-2017 Microchip Technology Inc. DS30009977G-page 7

PIC18F66K80 FAMILY Table of Contents 1.0 Device Overview........................................................................................................................................................................10 2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers.........................................................................................43 3.0 Oscillator Configurations............................................................................................................................................................48 4.0 Power-Managed Modes.............................................................................................................................................................61 5.0 Reset..........................................................................................................................................................................................75 6.0 Memory Organization.................................................................................................................................................................97 7.0 Flash Program Memory............................................................................................................................................................125 8.0 Data EEPROM Memory...........................................................................................................................................................134 9.0 8 x 8 Hardware Multiplier..........................................................................................................................................................140 10.0 Interrupts..................................................................................................................................................................................142 11.0 I/O Ports...................................................................................................................................................................................165 12.0 Data Signal Modulator..............................................................................................................................................................189 13.0 Timer0 Module.........................................................................................................................................................................199 14.0 Timer1 Module.........................................................................................................................................................................202 15.0 Timer2 Module.........................................................................................................................................................................214 16.0 Timer3 Module.........................................................................................................................................................................217 17.0 Timer4 Modules........................................................................................................................................................................227 18.0 Charge Time Measurement Unit (CTMU)................................................................................................................................229 19.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................247 20.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................259 21.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................281 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................326 23.0 12-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................350 24.0 Comparator Module..................................................................................................................................................................365 25.0 Comparator Voltage Reference Module...................................................................................................................................373 26.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................376 27.0 ECAN Module...........................................................................................................................................................................382 28.0 Special Features of the CPU....................................................................................................................................................447 29.0 Instruction Set Summary..........................................................................................................................................................473 30.0 Development Support...............................................................................................................................................................523 31.0 Electrical Characteristics..........................................................................................................................................................527 32.0 Packaging Information..............................................................................................................................................................571 Appendix A: Revision History.............................................................................................................................................................590 Appendix B: Migration to PIC18F66K80 Family.................................................................................................................................591 The Microchip Web Site.....................................................................................................................................................................593 Customer Change Notification Service..............................................................................................................................................593 Customer Support..............................................................................................................................................................................593 Product Identification System.............................................................................................................................................................595 DS30009977G-page 8  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010-2017 Microchip Technology Inc. DS30009977G-page 9

PIC18F66K80 FAMILY 1.0 DEVICE OVERVIEW • A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes which This document contains device-specific information for allows clock speeds of up to 64MHz. PLL can the following devices: also be used with the internal oscillator. • PIC18F25K80 • PIC18LF25K80 • An internal oscillator block that provides a 16 MHz clock (±2% accuracy) and an INTOSC source • PIC18F26K80 • PIC18LF26K80 (approximately 31kHz, stable over temperature • PIC18F45K80 • PIC18LF45K80 and VDD) • PIC18F46K80 • PIC18LF46K80 - Operates as HF-INTOSC or MF-INTOSC • PIC18F65K80 • PIC18LF65K80 when block is selected for 16MHz or • PIC18F66K80 • PIC18LF66K80 500kHz This family combines the traditional advantages of all - Frees the two oscillator pins for use as PIC18 microcontrollers – namely, high computational additional general purpose I/O performance and a rich feature set – with an extremely The internal oscillator block provides a stable reference competitive price point. These features make the source that gives the family additional features for PIC18F66K80 family a logical choice for many robust operation: high-performance applications where price is a primary consideration. • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference 1.1 Core Features signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the 1.1.1 TECHNOLOGY internal oscillator, allowing for continued low-speed All of the devices in the PIC18F66K80 family incorpo- operation or a safe application shutdown. rate a range of features that can significantly reduce • Two-Speed Start-up: This option allows the power consumption during operation. Key items include: internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep • Alternate Run Modes: By clocking the controller mode, until the primary clock source is available. from the Timer1 source or the Internal RC oscilla- tor, power consumption during code execution 1.1.3 MEMORY OPTIONS can be reduced. The PIC18F66K80 family provides ample room for • Multiple Idle Modes: The controller can also run application code, from 32Kbytes to 64Kbytes of code with its CPU core disabled but the peripherals still space. The Flash cells for program memory are rated active. In these states, power consumption can be to last up to 10,000 erase/write cycles. Data retention reduced even further. without refresh is conservatively estimated to be • On-the-Fly Mode Switching: The power-managed greater than 20 years. modes are invoked by user code during operation, The Flash program memory is readable and writable. allowing the user to incorporate power-saving ideas During normal operation, the PIC18F66K80 family also into their application’s software design. provides plenty of room for dynamic application data • XLP: An extra low-power BOR and low-power with up to 3.6Kbytes of data RAM. Watchdog timer 1.1.4 EXTENDED INSTRUCTION SET 1.1.2 OSCILLATOR OPTIONS AND FEATURES The PIC18F66K80 family implements the optional extension to the PIC18 instruction set, adding eight All of the devices in the PIC18F66K80 family offer new instructions and an Indexed Addressing mode. different oscillator options, allowing users a range of Enabled as a device configuration option, the extension choices in developing application hardware. These has been specifically designed to optimize re-entrant include: application code originally developed in high-level • External Resistor/Capacitor (RC); RA6 available languages, such as ‘C’. • External Resistor/Capacitor with Clock Out (RCIO) • Three External Clock modes: - External Clock (EC); RA6 available - External Clock with Clock Out (ECIO) - External Crystal (XT, HS, LP) DS30009977G-page 10  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 1.1.5 EASY MIGRATION • Charge Time Measurement Unit (CTMU): The CTMU is a flexible analog module that provides Regardless of the memory size, all devices share the accurate differential time measurement between same rich set of peripherals, allowing for a smooth pulse sources, as well as asynchronous pulse migration path as applications grow and evolve. generation. The consistent pinout scheme used throughout the Together with other on-chip analog modules, the entire family also aids in migrating to the next larger CTMU can precisely measure time, measure device. This is true when moving between the 28-pin, capacitance or relative changes in capacitance, or 40-pin, 44-pin and 64-pin members, or even jumping generate output pulses that are independent of the from smaller to larger memory devices. system clock. The PIC18F66K80 family is also largely pin compatible • LP Watchdog Timer (WDT): This enhanced with other PIC18 families, such as the PIC18F4580, version incorporates a 22-bit prescaler, allowing PIC18F4680 and PIC18F8680 families of microcontrol- an extended time-out range that is stable across lers with an ECAN module. This allows a new dimen- operating voltage and temperature. See sion to the evolution of applications, allowing Section31.0 “Electrical Characteristics” for developers to select different price points within time-out periods. Microchip’s PIC18 portfolio, while maintaining a similar feature set. 1.3 Details on Individual Family Members 1.2 Other Special Features Devices in the PIC18F66K80 family are available in • Communications: The PIC18F66K80 family incor- 28-pin, 40/44-pin and 64-pin packages. Block diagrams porates a range of serial communication peripherals, for each package are shown in Figure1-1, Figure1-2 including two Enhanced USARTs that support and Figure1-3, respectively. LIN/J2602, one Master SSP module capable of both SPI and I2C™ (Master and Slave) modes of The devices are differentiated from each other in these ways: operation and an Enhanced CAN module. • CCP Modules: PIC18F66K80 family devices • Flash Program Memory: incorporate four Capture/Compare/PWM (CCP) - PIC18FX5K80 (PIC18F25K80, PIC18F45K80 modules. Up to four different time bases can be and PIC18F45K80) – 32Kbytes used to perform several different operations at - PIC18FX6K80 (PIC18F26K80, PIC18F46K80 once. and PIC18F66K80) – 64Kbytes • ECCP Modules: The PIC18F66K80 family has • I/O Ports: one Enhanced CCP (ECCP) module to maximize - PIC18F2XK80 (28-pin devices) – flexibility in control applications: Three bidirectional ports - Up to four different time bases for performing - PIC18F4XK80 (40/44-pin devices) – several different operations at once Five bidirectional ports - Up to four PWM outputs - PIC18F6XK80 (64-pin devices) – - Other beneficial features, such as polarity Seven bidirectional ports selection, programmable dead time, All other features for devices in this family are identical. auto-shutdown and restart, and Half-Bridge These are summarized in Table1-1, Table1-2 and and Full-Bridge Output modes Table1-3. • 12-Bit A/D Converter: The PIC18F66K80 family has a differential A/D. It incorporates The pinouts for all devices are listed in Table1-4, programmable acquisition time, allowing for a Table1-5 and Table1-6. channel to be selected and a conversion to be initiated without waiting for a sampling period, and thus, reducing code overhead.  2010-2017 Microchip Technology Inc. DS30009977G-page 11

PIC18F66K80 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XK80 (28-PIN DEVICES) Features PIC18F25K80 PIC18F26K80 Operating Frequency DC – 64 MHz Program Memory (Bytes) 32K 64K Program Memory (Instructions) 16,384 32,768 Data Memory (Bytes) 3.6K Interrupt Sources 31 I/O Ports Ports A, B, C Parallel Communications Parallel Slave Port (PSP) Timers Five Comparators Two CTMU Yes Capture/Compare/PWM (CCP) Four Modules Enhanced CCP (ECCP) Modules One Serial Communications One MSSP and Two Enhanced USARTs (EUSART) 12-Bit Analog-to-Digital Module Eight Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 28-Pin QFN-S, SOIC, SPDIP and SSOP TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XK80 (40/44-PIN DEVICES) Features PIC18F45K80 PIC18F46K80 Operating Frequency DC – 64 MHz Program Memory (Bytes) 32K 64K Program Memory (Instructions) 16,384 32,768 Data Memory (Bytes) 3.6K Interrupt Sources 32 I/O Ports Ports A, B, C, D, E Parallel Communications Parallel Slave Port (PSP) Timers Five Comparators Two CTMU Yes Capture/Compare/PWM (CCP) Four Modules Enhanced CCP (ECCP) Modules One Serial Communications One MSSP and Two Enhanced USARTs (EUSART) 12-Bit Analog-to-Digital Module Eleven Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 40-Pin PDIP and 44-Pin QFN and TQFP DS30009977G-page 12  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC18F6XK80 (64-PIN DEVICES) Features PIC18F65K80 PIC18F66K80 Operating Frequency DC – 64 MHz Program Memory (Bytes) 32K 64K Program Memory (Instructions) 16,384 32,768 Data Memory (Bytes) 3.6K Interrupt Sources 32 I/O Ports Ports A, B, C, D, E, F, G Parallel Communications Parallel Slave Port (PSP) Timers Five Comparators Two CTMU Yes Capture/Compare/PWM (CCP) Four Modules Enhanced CCP (ECCP) Modules One DSM Yes Yes Serial Communications One MSSP and Two Enhanced USARTs (EUSART) 12-Bit Analog-to-Digital Module Eleven Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled Packages 64-Pin QFN and TQFP  2010-2017 Microchip Technology Inc. DS30009977G-page 13

PIC18F66K80 FAMILY FIGURE 1-1: PIC18F2XK80 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA inc/dec logic 8 8 Data Latch RAR<A7<:35:>0(>1,2) Data Memory (2/4 Kbytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB<7:0>(1) 31-Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank FSR1 Data Latch FSR2 12 PORTC inc/dec RC<7:0>(1) 8 logic Table Latch Address ROM Latch Instruction Bus<16> Decode PORTE RE3(1,3) IR 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL 8 x 8 Multiply OSC2/CLKO GeTnimeriantgion Power-up 3 8 OSC1/CLKI Timer BITOP W OINsTciOllaStCor StaOrts-cuipll aTtoimrer 8 8 8 16 MHz Oscillator Power-on 8 8 Reset Precision ALU<8> Band Gap Watchdog Reference Timer 8 BOR and Voltage LVD Regulator VDDCORE/VCAP VDD, VSS MCLR Timer0 Timer1 Timer 2/4 Timer 3 CTMU A/D Comparator 12-Bit 1/2 CCP2/3/4/5 ECCP1 EUSART1 EUSART2 MSSP ECAN Note 1: See Table1-4 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section3.0 “Oscillator Configurations”. 3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0). DS30009977G-page 14  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 1-2: PIC18F4XK80 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch RA<3:0> inc/dec logic 8 8 RA<7:5>(1,2) Data Memory (2/4 Kbytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB<7:0>(1) 31-Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank FSR1 Data Latch FSR2 12 PORTC inc/dec RC7:0>(1) 8 logic Table Latch Address ROM Latch Instruction Bus<16> Decode PORTD IR RD<7:0>(1) 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTE RE<3:0>(1,3) 8 x 8 Multiply OSC2/CLKO GeTnimeriantgion Power-up 3 8 OSC1/CLKI Timer BITOP W OINsTciOllaStCor StaOrts-cuipll aTtoimrer 8 8 8 16 MHz Oscillator Power-on 8 8 Reset Precision ALU<8> Band Gap Watchdog Reference Timer 8 BOR and Voltage LVD Regulator VDDCORE/VCAP VDD, VSS MCLR Timer0 Timer1 Timer2/4 Timer3 CTMU A/D Comparator 12-Bit 1/2 CCP 2/3/4/5 ECCP1 EUSART1 EUSART2 MSSP ECAN PSP Note 1: See Table1-5 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section3.0 “Oscillator Configurations”. 3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).  2010-2017 Microchip Technology Inc. DS30009977G-page 15

PIC18F66K80 FAMILY FIGURE 1-3: PIC18F6XK80 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch RA<3:0> inc/dec logic 8 8 RA<7:5>(1,2) Data Memory (2/4 Kbytes) 21 PCLAT U PCLATH 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB<7:0>(1) 31-Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank FSR1 Data Latch FSR2 12 PORTC inc/dec RC<7:0>(1) 8 logic Table Latch Address ROM Latch Instruction Bus<16> Decode PORTD IR RD<7:0>(1) 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTE RE<7:0>(1,3) 8 x 8 Multiply OSC2/CLKO GeTnimeriantgion Power-up 3 8 OSC1/CLKI Timer BITOP W OINsTciOllaStCor StaOrts-cuipll aTtoimrer 8 8 8 16 MHz PORTF Oscillator Power-on 8 8 Reset RF<7:0>(1) Precision ALU<8> Band Gap Watchdog Reference Timer 8 BOR and Voltage LVD Regulator PORTG RG<4:0>(1) VDDCORE/VCAP VDD, VSS MCLR Timer0 Timer1 Timer2/4 Timer3 CTMU A/D Comparator 12-Bit 1/2 CCP2/3/4/5 ECCP1 EUSART1 EUSART2 MSSP ECAN PSP DSM Note 1: See Table1-6 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section3.0 “Oscillator Configurations”. 3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0). DS30009977G-page 16  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name SSOP/ Description Type Type QFN SPDIP /SOIC MCLR/RE3 26 1 MCLR I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. RE3 I ST General purpose, input only pin. OSC1/CLKIN/RA7 6 9 OSC1 I ST Oscillator crystal input. CLKIN I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O ST/ General purpose I/O pin. CMOS OSC2/CLKOUT/RA6 7 10 OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKOUT O — In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O ST/ General purpose I/O pin. CMOS Legend: CMOS= CMOS compatible input or output I2C™ = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 17

PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SSOP/ Description Type Type QFN SPDIP /SOIC PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ULPWU 27 2 RA0 I/O ST/ General purpose I/O pin. CMOS CVREF O Analog Comparator reference voltage output. AN0 I Analog Analog Input 0. ULPWU I Analog Ultra Low-Power Wake-up input. RA1/AN1 28 3 RA1 I/O ST/ Digital I/O. CMOS AN1 I Analog Analog Input 1. RA2/VREF-/AN2 1 4 RA2 I/O ST/ Digital I/O. CMOS VREF- I Analog A/D reference voltage (low) input. AN2 I Analog Analog Input 2. RA3/VREF+/AN3 2 5 RA3 I/O ST/ Digital I/O. CMOS VREF+ I Analog A/D reference voltage (high) input. AN3 I Analog Analog Input 3. RA5/AN4/C2INB/HLVDIN/ 4 7 T1CKI/SS/CTMUI RA5 I/O ST/ Digital I/O. CMOS AN4 I Analog Analog Input 4. C2INB I Analog Comparator 2 Input B. HLVDIN I Analog High/Low-Voltage Detect input. T1CKI I ST Timer1 clock input. SS I ST SPI slave select input. CTMUI CTMU pulse generator charger for the C2INB. Legend: CMOS= CMOS compatible input or output I2C™ = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 18  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SSOP/ Description Type Type QFN SPDIP /SOIC PORTB is a bidirectional I/O port. RB0/AN10/C1INA/FLT0/ 18 21 INT0 RB0 I/O ST/ Digital I/O. CMOS AN10 I Analog Analog Input 10. C1INA I Analog Comparator 1 Input A. FLT0 I ST Enhanced PWM Fault input for ECCP1. INT0 I ST External Interrupt 0. RB1/AN8/C1INB/P1B/ 19 22 CTDIN/INT1 RB1 I/O ST/ Digital I/O. CMOS AN8 I Analog Analog Input 8. C1INB I Analog Comparator 1 Input B. P1B O CMOS Enhanced PWM1 Output B. CTDIN I ST CTMU pulse delay input. INT1 I ST External Interrupt 1. RB2/CANTX/C1OUT/ 20 23 P1C/CTED1/INT2 RB2 I/O ST/ Digital I/O. CMOS CANTX O CMOS CAN bus TX. C1OUT O CMOS Comparator 1 output. P1C O CMOS Enhanced PWM1 Output C. CTED1 I ST CTMU Edge 1 input. INT2 I ST External Interrupt 2. RB3/CANRX/C2OUT/ 21 24 P1D/CTED2/INT3 RB3 I/O ST/ Digital I/O. CMOS CANRX I ST CAN bus RX. C2OUT O CMOS Comparator 2 output. P1D O CMOS Enhanced PWM1 Output D. CTED2 I ST CTMU Edge 2 input. INT3 I ST External Interrupt 3. Legend: CMOS= CMOS compatible input or output I2C™ = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 19

PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SSOP/ Description Type Type QFN SPDIP /SOIC RB4/AN9/C2INA/ECCP1/ 22 25 P1A/CTPLS/KBI0 RB4 I/O ST/ Digital I/O. CMOS AN9 I Analog Analog Input 9. C2INA I Analog Comparator 2 Input A. ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O CMOS Enhanced PWM1 Output A. CTPLS O ST CTMU pulse generator output. KBI0 I ST Interrupt-on-change pin. RB5/T0CKI/T3CKI/CCP5/ 23 26 KBI1 RB5 I/O ST/ Digital I/O. CMOS T0CKI I ST Timer0 external clock input. T3CKI I ST Timer3 external clock input. CCP5 I/O ST/ Capture 5 input/Compare 5 output/PWM5 output. CMOS KBI1 I ST Interrupt-on-change pin. RB6/PGC/TX2/CK2/KBI2 24 27 RB6 I/O ST/ Digital I/O. CMOS PGC I ST In-Circuit Debugger and ICSP™ programming clock input pin. TX2 O CMOS EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock. (See related RX2/DT2.) KBI2 I ST Interrupt-on-change pin. RB7/PGD/T3G/RX2/DT2/ 25 28 KBI3 RB7 I/O ST/ Digital I/O. CMOS PGD I/O ST In-Circuit Debugger and ICSP programming data pin. T3G I ST Timer3 external clock gate input. RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data. (See related TX2/CK2.) KBI3 I ST Interrupt-on-change pin. Legend: CMOS= CMOS compatible input or output I2C™ = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 20  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SSOP/ Description Type Type QFN SPDIP /SOIC PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI 8 11 RC0 I/O ST/ Digital I/O. CMOS SOSCO I ST Timer1 oscillator output. SCLKI I ST Digital SOSC input. RC1/SOSCI 9 12 RC1 I/O ST/ Digital I/O. CMOS SOSCI I CMOS SOSC oscillator input. RC2/T1G/CCP2 10 13 RC2 I/O ST/ Digital I/O. CMOS T1G I ST Timer1 external clock gate input. CCP2 I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC3/REFO/SCL/SCK 11 14 RC3 I/O ST/ Digital I/O. CMOS REFO O — Reference clock out. SCL I/O I2C Synchronous serial clock input/output for I2C mode. SCK I/O ST Synchronous serial clock input/output for SPI mode. RC4/SDA/SDI 12 15 RC4 I/O ST/ Digital I/O. CMOS SDA I/O I2C I2C data input/output. SDI I ST SPI data in. RC5/SDO 13 16 RC5 I/O ST/ Digital I/O. CMOS SDO O CMOS SPI data out. RC6/CANTX/TX1/CK1/ 14 17 CCP3 RC6 I/O ST/ Digital I/O. CMOS CANTX O CMOS CAN bus TX. TX1 O CMOS EUSART asynchronous transmit. CK1 I/O ST EUSART synchronous clock. (See related RX1/DT1.) CCP3 I/O ST/ Capture 3 input/Compare 3 output/PWM3 output. CMOS Legend: CMOS= CMOS compatible input or output I2C™ = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 21

PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SSOP/ Description Type Type QFN SPDIP /SOIC RC7/CANRX/RX1/DT1/ 15 18 CCP4 RC7 I/O ST/ Digital I/O. CMOS CANRX I ST CAN bus RX. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data. (See related TX2/CK2.) CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output. CMOS VSS 5 8 P VSS Ground reference for logic and I/O pins. VSS 16 19 VSS Ground reference for logic and I/O pins. VDDCORE/VCAP 3 6 P VDDCORE External filter capacitor connection. VCAP External filter capacitor connection VDD 17 20 P VDD Positive supply for logic and I/O pins. Legend: CMOS= CMOS compatible input or output I2C™ = I2C/SMBus input buffer ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 22  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP MCLR/RE3 1 18 MCLR I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. RE3 I ST General purpose, input only pin. OSC1/CLKIN/RA7 13 30 OSC1 I ST Oscillator crystal input. CLKIN I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O ST/ General purpose I/O pin. CMOS OSC2/CLKOUT/RA6 14 31 OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKOUT O — In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O ST/ General purpose I/O pin. CMOS Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 23

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ULPWU 2 19 RA0 I/O ST/ General purpose I/O pin. CMOS CVREF O Analog Comparator reference voltage output. AN0 I Analog Analog Input 0. ULPWU I Analog Ultra Low-Power Wake-up input. RA1/AN1/C1INC 3 20 RA1 I/O ST/ Digital I/O. CMOS AN1 I Analog Analog Input 1. C1INC I Analog Comparator 1 Input C. RA2/VREF-/AN2/C2INC 4 21 RA2 I/O ST/ Digital I/O. CMOS VREF- I Analog A/D reference voltage (low) input. AN2 I Analog Analog Input 2. C2INC I Analog Comparator 2 Input C. RA3/VREF+/AN3 5 22 RA3 I/O ST/ Digital I/O. CMOS VREF+ I Analog A/D reference voltage (high) input. AN3 I Analog Analog Input 3. RA5/AN4/HLVDIN/T1CKI/ 7 24 SS RA5 I/O ST/ Digital I/O. CMOS AN4 I Analog Analog Input 4. HLVDIN I Analog High/Low-Voltage Detect input. T1CKI I ST Timer1 clock input. SS I ST SPI slave select input. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 24  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP PORTB is a bidirectional I/O port. RB0/AN10/FLT0/INT0 33 8 RB0 I/O ST/ Digital I/O. CMOS AN10 I Analog Analog Input 10. FLT0 I ST Enhanced PWM Fault input for ECCP1. INT0 I ST External Interrupt 0. RB1/AN8/CTDIN/INT1 34 9 RB1 I/O ST/ Digital I/O. CMOS AN8 I Analog Analog Input 8. CTDIN I ST CTMU pulse delay input. INT1 I ST External Interrupt 1. RB2/CANTX/CTED1/ 35 10 INT2 RB2 I/O ST/ Digital I/O. CMOS CANTX O CMOS CAN bus TX. CTED1 I ST CTMU Edge 1 input. INT2 I ST External Interrupt 2. RB3/CANRX/CTED2/ 36 11 INT3 RB3 I/O ST/ Digital I/O. CMOS CANRX I ST CAN bus RX. CTED2 I ST CTMU Edge 2 input. INT3 I ST External Interrupt 3. RB4/AN9/CTPLS/KBI0 37 14 RB4 I/O ST/ Digital I/O. CMOS AN9 I Analog Analog Input 9. CTPLS O ST CTMU pulse generator output. KBI0 I ST Interrupt-on-change pin. RB5/T0CKI/T3CKI/CCP5/ 38 15 KBI1 RB5 I/O ST/ Digital I/O. CMOS T0CKI I ST Timer0 external clock input. T3CKI I ST Timer3 external clock input. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM5 output. KBI1 I ST Interrupt-on-change pin. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 25

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP RB6/PGC/KBI2 39 16 RB6 I/O ST/ Digital I/O. CMOS PGC I ST In-Circuit Debugger and ICSP™ programming clock input pin. KBI2 I ST Interrupt-on-change pin. RB7/PGD/T3G/KBI3 40 17 RB7 I/O ST/ Digital I/O. CMOS PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. T3G I ST Timer3 external clock gate input. KBI3 I ST Interrupt-on-change pin. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 26  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI 15 32 RC0 I/O ST/ Digital I/O. CMOS SOSCO I ST SOSC oscillator output. SCLKI I ST Digital SOSC input. RC1/SOSCI 16 35 RC1 I/O ST/ Digital I/O. CMOS SOSCI I CMOS SOSC oscillator input. RC2/T1G/CCP2 17 36 RC2 I/O ST/ Digital I/O. CMOS T1G I ST Timer1 external clock gate input. CCP2 I/O ST/ Capture 2 input/Compare 2 output/PWM2 output. CMOS RC3/REFO/SCL/SCK 18 37 RC3 I/O ST/ Digital I/O. CMOS REFO O CMOS Reference clock out. SCL I/O I2C Synchronous serial clock input/output for I2C mode. SCK I/O ST Synchronous serial clock input/output for SPI mode. RC4/SDA/SDI 23 42 RC4 I/O ST/ Digital I/O. CMOS SDA I/O I2C I2C data input/output. SDI I ST SPI data in. RC5/SDO 24 43 RC5 I/O ST/ Digital I/O. CMOS SDO O CMOS SPI data out. RC6/CANTX/TX1/CK1/ 25 44 CCP3 RC6 I/O ST/ Digital I/O. CMOS CANTX O CMOS CAN bus TX. TX1 O CMOS EUSART synchronous transmit. CK1 I/O ST EUSART synchronous clock. (See related RX2/DT2.) CCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 27

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP RC7/CANRX/RX1/DT1/ 26 1 CCP4 RC7 I/O ST/ Digital I/O. CMOS CANRX I ST CAN bus RX. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data. (See related TX2/CK2.) CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 28  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP PORTD is a bidirectional I/O port. RD0/C1INA/PSP0 19 38 RD0 I/O ST/ Digital I/O. CMOS C1INA I Analog Comparator 1 Input A. PSP0 I/O ST/ Parallel Slave Port data. CMOS RD1/C1INB/PSP1 20 39 RD1 I/O ST/ Digital I/O. CMOS C1INB I Analog Comparator 1 Input B. PSP1 I/O ST/ Parallel Slave Port data. CMOS RD2/C2INA/PSP2 21 40 RD2 I/O ST/ Digital I/O. CMOS C2INA I Analog Comparator 2 Input A. PSP2 I/O ST/ Parallel Slave Port data. CMOS RD3/C2INB/CTMUI/ 22 41 PSP3 RD3 I/O ST/ Digital I/O. CMOS C2INB I Analog Comparator 2 Input B. CTMUI CTMU pulse generator charger for the C2INB. PSP3 I/O ST/ Parallel Slave Port data. CMOS RD4/ECCP1/P1A/PSP4 27 2 RD4 I/O ST/ Digital I/O. CMOS ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O CMOS Enhanced PWM1 Output A. PSP4 I/O ST/ Parallel Slave Port data. CMOS RD5/P1B/PSP5 28 3 RD5 I/O ST/ Digital I/O. CMOS P1B O CMOS Enhanced PWM1 Output B. PSP5 I/O ST/ Parallel Slave Port data. CMOS Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 29

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP RD6/TX2/CK2/P1C/PSP6 29 4 RD6 I/O ST/ Digital I/O. CMOS TX2 I ST EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock. (See related RX2/DT2.) P1C O CMOS Enhanced PWM1 Output C. PSP6 I/O ST/ Parallel Slave Port data. CMOS RD7/RX2/DT2/P1D/PSP7 30 5 RD7 I/O ST/ Digital I/O. CMOS RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data. (See related TX2/CK2.) P1D O CMOS Enhanced PWM1 Output D. PSP7 I/O ST/ Parallel Slave Port data. CMOS RE0/AN5/RD 8 25 RE0 I/O ST/ Digital I/O. CMOS AN5 I Analog Analog Input 5. RD I ST Parallel Slave Port read strobe. RE1/AN6/C1OUT/WR 9 26 RE1 I/O ST/ Digital I/O. CMOS AN6 I Analog Analog Input 6. C1OUT O CMOS Comparator 1 output. WR I ST Parallel Slave Port write strobe. RE2/AN7/C2OUT/CS 10 27 RE2 I/O ST/ Digital I/O. CMOS AN7 I Analog Analog Input 7. C2OUT O CMOS Comparator 2 output. CS I ST Parallel Slave Port chip select. RE3 See the MCLR/RE3 pin. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 30  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description QFN/ Type Type PDIP TQFP VSS 12 29 P VSS Ground reference for logic and I/O pins. VSS 31 6 VSS Ground reference for logic and I/O pins. VDDCORE/VCAP 6 23 P VDDCORE External filter capacitor connection VCAP External filter capacitor connection VDD 11 28 P VDD Positive supply for logic and I/O pins. VDD 32 7 P VDD Positive supply for logic and I/O pins. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 31

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS Pin Pin Buffer Pin Name Description Num Type Type MCLR/RE3 28 MCLR I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. RE3 I ST General purpose, input only pin. OSC1/CLKIN/RA7 46 OSC1 I ST Oscillator crystal input. CLKIN I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O ST/ General purpose I/O pin. CMOS OSC2/CLKOUT/RA6 47 OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKOUT O — In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O ST/ General purpose I/O pin. CMOS Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 32  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ 29 ULPWU RA0 I/O ST/ General purpose I/O pin. CMOS CVREF O Analog Comparator reference voltage output. AN0 I Analog Analog Input 0. ULPWU I Analog Ultra Low-Power Wake-up input. RA1/AN1/C1INC 30 RA1 I/O ST/ Digital I/O. CMOS AN1 I Analog Analog Input 1. C1INC I Analog Comparator 1 Input C. RA2/VREF-/AN2/C2INC 31 RA2 I/O ST/ Digital I/O. CMOS VREF- I Analog A/D reference voltage (low) input. AN2 I Analog Analog Input 2. C2INC I Analog Comparator 2 Input C. RA3/VREF+/AN3 32 RA3 I/O ST/ Digital I/O. CMOS VREF+ I Analog A/D reference voltage (high) input. AN3 I Analog Analog Input 3. RA5/AN4/HLVDIN/ 34 T1CKI/SS RA5 I/O ST/ Digital I/O. CMOS AN4 I Analog Analog Input 4. HLVDIN I Analog High/Low-Voltage Detect input. T1CKI I ST Timer1 clock input. SS I ST SPI slave select input. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 33

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type PORTB is a bidirectional I/O port. RB0/AN10/FLT0/INT0 13 RB0 I/O ST/ Digital I/O. CMOS AN10 I Analog Analog Input 10. FLT0 I ST Enhanced PWM Fault input for ECCP1. INT0 I ST External Interrupt 0. RB1/AN8/CTDIN/INT1 14 RB1 I/O ST/ Digital I/O. CMOS AN8 I Analog Analog Input 8. CTDIN I ST CTMU pulse delay input. INT1 I ST External Interrupt 1. RB2/CANTX/CTED1/ 15 INT2 RB2 I/O ST/ Digital I/O. CMOS CANTX O CMOS CAN bus TX. CTED1 I ST CTMU Edge 1 input. INT2 I ST External Interrupt 2. RB3/CANRX/CTED2/ 16 INT3 RB3 I/O ST/ Digital I/O. CMOS CANRX I ST CAN bus RX. CTED2 I ST CTMU Edge 2 input. INT3 I ST External Interrupt 3. RB4/AN9/CTPLS/KBI0 20 RB4 I/O ST/ Digital I/O. CMOS AN9 I Analog Analog Input 9. CTPLS O ST CTMU pulse generator output. KBI0 I ST Interrupt-on-change pin. RB5/T0CKI/T3CKI/CCP5/ 21 KBI1 RB5 I/O ST/ Digital I/O. CMOS T0CKI I ST Timer0 external clock input. T3CKI I ST Timer3 external clock input. CCP5 I/O ST/ Capture 5 input/Compare 5 output/PWM5 output. CMOS KBI1 I ST Interrupt-on-change pin. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 34  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type RB6/PGC/KBI2 22 RB6 I/O ST/ Digital I/O. CMOS PGC I ST In-Circuit Debugger and ICSP™ programming clock input pin. KBI2 I ST Interrupt-on-change pin. RB7/PGD/T3G/KBI3 23 RB7 I/O ST/ Digital I/O. CMOS PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. T3G I ST Timer3 external clock gate input. KBI3 I ST Interrupt-on-change pin. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 35

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI 48 RC0 I/O ST/ Digital I/O. CMOS SOSCO I ST Timer1 oscillator output. SCLKI I ST Digital SOSC input. RC1/SOSCI 49 RC1 I/O ST/ Digital I/O. CMOS SOSCI I CMOS SOSC oscillator input. RC2/T1G/CCP2 50 RC2 I/O ST/ Digital I/O. CMOS T1G I ST Timer1 external clock gate input. CCP2 I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC3/REFO/SCL/SCK 51 RC3 I/O ST/ Digital I/O. CMOS REFO O CMOS Reference clock out. SCL I/O I2C Synchronous serial clock input/output for I2C mode. SCK I/O ST Synchronous serial clock input/output for SPI mode. RC4/SDA/SDI 62 RC4 I/O ST/ Digital I/O. CMOS SDA I/O I2C I2C data input/output. SDI I ST SPI data in. RC5/SDO 63 RC5 I/O ST/ Digital I/O. CMOS SDO O CMOS SPI data out. RC6/CCP3 64 RC6 I/O ST/ Digital I/O. CMOS CCP3 I/O ST/ Capture 3 input/Compare 3 output/PWM3 output. CMOS RC7/CCP4 1 RC7 I/O ST/ Digital I/O. CMOS CCP4 I/O ST/ Capture 4 input/Compare 4 output/PWM4 output. CMOS Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 36  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type PORTD is a bidirectional I/O port. RD0/C1INA/PSP0 54 RD0 I/O ST/ Digital I/O. CMOS C1INA I Analog Comparator 1 Input A. PSP0 I/O ST/ Parallel Slave Port data. CMOS RD1/C1INB/PSP1 55 RD1 I/O ST/ Digital I/O. CMOS C1INB I Analog Comparator 1 Input B. PSP1 I/O ST/ Parallel Slave Port data. CMOS RD2/C2INA/PSP2 58 RD2 I/O ST/ Digital I/O. CMOS C2INA I Analog Comparator 2 Input A. PSP2 I/O ST/ Parallel Slave Port data. CMOS RD3/C2INB/CTMUI/ 59 PSP3 RD3 I/O ST/ Digital I/O. CMOS C2INB I Analog Comparator 2 Input B. CTMUI O CMOS CTMU pulse generator charger for the C2INB. PSP3 I/O ST/ Parallel Slave Port data. CMOS RD4/ECCP1/P1A/PSP4 2 RD4 I/O ST/ Digital I/O. CMOS ECCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O CMOS Enhanced PWM1 Output A. PSP4 I/O ST/ Parallel Slave Port data. CMOS RD5/P1B/PSP5 3 RD5 I/O ST/ Digital I/O. CMOS P1B O CMOS Enhanced PWM1 Output B. PSP5 I/O ST/ Parallel Slave Port data. CMOS Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 37

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type RD6/P1C/PSP6 4 RD6 I/O ST/ Digital I/O. CMOS P1C O CMOS Enhanced PWM1 Output C. PSP6 I/O ST/ Parallel Slave Port data. CMOS RD7/P1D/PSP7 5 RD7 I/O ST/ Digital I/O. CMOS P1D O CMOS Enhanced PWM1 Output D. PSP7 I/O ST/ Parallel Slave Port data. CMOS Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 38  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type PORTE is a bidirectional I/O port. RE0/AN5/RD 37 RE0 I/O ST/ Digital I/O. CMOS AN5 I Analog Analog Input 5. RD I ST Parallel Slave Port read strobe. RE1/AN6/C1OUT/WR 38 RE1 I/O ST/ Digital I/O. CMOS AN6 I Analog Analog Input 6. C1OUT O CMOS Comparator 1 output. WR I ST Parallel Slave Port write strobe. RE2/AN7/C2OUT/CS 39 RE2 I/O ST/ Digital I/O. CMOS AN7 I Analog Analog Input 7. C2OUT O CMOS Comparator 2 output. CS I ST Parallel Slave Port chip select. RE3 See the MCLR/RE3 pin. RE4/CANRX 27 RE4 I/O ST/ Digital I/O. CMOS CANRX I ST CAN bus RX. RE5/CANTX 24 RE5 I/O ST/ Digital I/O. CMOS CANTX O CMOS CAN bus TX. RE6/RX2/DT2 60 RE6 I/O ST/ Digital I/O. CMOS RX2 I ST EUSART asynchronous receive. DT2 I/O ST EUSART synchronous data. (See related TX2/CK2.) RE7/TX2/CK2 61 RE7 I/O ST/ Digital I/O. CMOS TX2 O CMOS EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock. (See related RX2/DT2.) Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 39

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type PORTF is a bidirectional I/O port. RF0/MDMIN 17 RF0 I/O ST/ Digital I/O. CMOS MDMIN I CMOS Modulator source input. RF1 19 RF1 I/O ST/ Digital I/O. CMOS RF2/MDCIN1 35 RF2 I/O ST/ Digital I/O. CMOS MDCIN1 I ST Modulator Carrier Input 1. RF3 36 RF3 I/O ST/ Digital I/O. CMOS RF4/MDCIN2 44 RF4 I/O ST/ Digital I/O. CMOS MDCIN2 I ST Modulator Carrier Input 2. RF5 45 RF5 I/O ST/ Digital I/O. CMOS RF6/MDOUT 52 RF6 I/O ST/ Digital I/O. CMOS MDOUT O CMOS Modulator output. RF7 53 RF7 I/O ST/ Digital I/O. CMOS Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 40  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type PORTG is a bidirectional I/O port. RG0/RX1/DT1 6 RG0 I/O ST/ Digital I/O. CMOS RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data. (See related TX2/CK2.) RG1/CANTX2 7 RG1 I/O ST/ Digital I/O. CMOS CANTX2 O CMOS CAN bus complimentary transmit output or CAN bus time clock. RG2/T3CKI 11 RG2 I/O ST/ Digital I/O. CMOS T3CKI I ST Timer3 clock input. RG3/TX1/CK1 12 RG3 I/O ST/ Digital I/O. CMOS TX1 O CMOS EUSART asynchronous transmit. CK1 I/O ST EUSART synchronous clock. (See related RX2/DT2.) RG4/T0CKI 18 RG4 I/O ST/ Digital I/O. CMOS T0CKI I ST Timer0 external clock input. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power  2010-2017 Microchip Technology Inc. DS30009977G-page 41

PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Pin Buffer Pin Name Description Num Type Type VSS 8 P VSS Ground reference for logic and I/O pins. VSS 26 P VSS Ground reference for logic and I/O pins. AVSS 42 P AVSS Ground reference for analog modules. VSS 43 P VSS Ground reference for logic and I/O pins. VSS 56 P VSS Ground reference for logic and I/O pins. AVDD 9 P AVDD Positive supply for analog modules. VDD 10 P VDD Positive supply for logic and I/O pins. VDD 25 P VDD Positive supply for logic and I/O pins. VDDCORE/VCAP 33 P VDDCORE External filter capacitor connection. VCAP External filter capacitor connection. AVDD 40 P AVDD Positive supply for analog modules. VDD 41 P VDD Positive supply for logic and I/O pins. VDD 57 P VDD Positive supply for logic and I/O pins. Legend: I2C™= I2C/SMBus input buffer CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power DS30009977G-page 42  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH PIC18FXXKXX MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F66K80 family family of R1 DD SS (1)(1) 8-bit microcontrollers requires attention to a minimal R2 V V set of device pin connections before proceeding with MCLR ENVREG development. VCAP/VDDCORE C1 The following pins must always be connected: C7(2) PIC18FXXKXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section2.4 “Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)”) Key (all values are recommendations): These pins must also be connected if they are being C1 through C6: 0.1 F, 20V ceramic used in the end application: R1: 10 kΩ • PGC/PGD pins used for In-Circuit Serial R2: 100Ω to 470Ω Programming™ (ICSP™) and debugging purposes Note 1: See Section2.4 “Voltage Regulator Pins (see Section2.5 “ICSP Pins”) (ENVREG and VCAP/VDDCORE)” for • OSCI and OSCO pins when an external oscillator explanation of ENVREG pin connections. source is used 2: The example shown is for a PIC18F device (see Section2.6 “External Oscillator Pins”) with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; Additionally, the following pins may be required: adjust the number of decoupling capacitors • VREF+/VREF- pins are used when external voltage appropriately. reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2010-2017 Microchip Technology Inc. DS30009977G-page 43

PIC18F66K80 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: Device Reset, and Device Programming The use of decoupling capacitors on every pair of and Debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 F (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented, depending on the should be a low-ESR device, with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must be considered. Device programmers and debuggers decoupling capacitors should be placed as close drive the MCLR pin. Consequently, specific voltage to the pins as possible. It is recommended to place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1F in parallel with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC18FXXKXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1 10k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10k. Ensure that the On boards with power traces running longer than MCLR pin VIH and VIL specifications are met. sixinches in length, it is suggested to use a tank capac- 2: R2470 will limit any current flowing into itor for integrated circuits, including microcontrollers, to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS30009977G-page 44  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 2.4 Voltage Regulator Pins (ENVREG Some PIC18FXXKXX families, or some devices within and VCAP/VDDCORE) a family, do not provide the option of enabling or disabling the on-chip voltage regulator: The on-chip voltage regulator enable pin, ENVREG, • Some devices (with the name, PIC18LFXXKXX) must always be connected directly to either a supply permanently disable the voltage regulator. voltage or to ground. Tying ENVREG to VDD enables These devices do not have the ENVREG pin and the regulator, while tying it to ground disables the require a 0.1 F capacitor on the VCAP/VDDCORE regulator. Refer to Section28.3 “On-Chip Voltage pin. The VDD level of these devices must comply Regulator” for details on connecting and using the with the “voltage regulator disabled” specification on-chip regulator. for Parameter D001, in Section31.0 “Electrical When the regulator is enabled, a low-ESR (<5Ω) Characteristics”. capacitor is required on the VCAP/VDDCORE pin to • Some devices permanently enable the voltage stabilize the voltage regulator output voltage. The regulator. VCAP/VDDCORE pin must not be connected to VDD and These devices also do not have the ENVREG pin. must use a capacitor of 10 µF connected to ground. The The 10 F capacitor is still required on the type can be ceramic or tantalum. Suitable examples of VCAP/VDDCORE pin. capacitors are shown in Table2-1. Capacitors with equivalent specifications can be used. FIGURE 2-3: FREQUENCY vs. ESR Designers may use Figure2-3 to evaluate ESR PERFORMANCE FOR equivalence of candidate devices. SUGGESTED VCAP It is recommended that the trace length not exceed 10 0.25inch (6mm). Refer to Section31.0 “Electrical Characteristics” for additional information. 1 When the regulator is disabled, the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. ) Refer to Section31.0 “Electrical Characteristics” for R ( 0.1 information on VDD and VDDCORE. ES 0.01 0.001 0.01 0.1 1 10 100 1000 10,000 Frequency (MHz) Note: Typical data measurement at 25°C, 0V DC bias. . TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Nominal Make Part # Base Tolerance Rated Voltage Temp. Range Capacitance TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC  2010-2017 Microchip Technology Inc. DS30009977G-page 45

PIC18F66K80 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITORS CAPACITANCE CHARACTERISTICS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic %) 10 e ( 0 capacitors very attractive in many types of applications. ng-10 16V Capacitor ha-20 Ceramic capacitors are suitable for use with the inter- C-30 nal voltage regulator of this microcontroller. However, ance --5400 10V Capacitor some care is needed in selecting the capacitor to cit-60 ensure that it maintains sufficient capacitance over the Capa--8700 6.3V Capacitor intended operating range of the application. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) Typical low-cost, 10 F ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial toler- When selecting a ceramic capacitor to be used with the ance specifications for these types of capacitors are internal voltage regulator, it is suggested to select a often specified as ±10% to ±20% (X5R and X7R), or high-voltage rating, so that the operating voltage is a -20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt- that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at also vary based on additional factors, such as the 16V for the 2.5V core voltage. Suggested capacitors applied DC bias voltage and the temperature. The total are shown in Table2-1. in-circuit tolerance is, therefore, much wider than the initial tolerance specification. 2.5 ICSP Pins The X5R and X7R capacitors typically exhibit satisfac- The PGC and PGD pins are used for In-Circuit Serial tory temperature stability (ex: ±15% over a wide Programming™ (ICSP™) and debugging purposes. It temperature range, but consult the manufacturer's data is recommended to keep the trace length between the sheets for exact specifications). However, Y5V capaci- ICSP connector and the ICSP pins on the device as tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to specifications of +22%/-82%. Due to the extreme experience an ESD event, a series resistor is recom- temperature tolerance, a 10 F nominal rated Y5V type mended, with the value in the range of a few tens of capacitor may not deliver enough total capacitance to ohms, not to exceed 100Ω. meet minimum internal voltage regulator stability and Pull-up resistors, series diodes and capacitors on the transient response requirements. Therefore, Y5V PGC and PGD pins are not recommended as they will capacitors are not recommended for use with the interfere with the programmer/debugger communica- internal regulator if the application must operate over a tions to the device. If such discrete components are an wide temperature range. application requirement, they should be removed from In addition to temperature tolerance, the effective the circuit during programming and debugging. Alter- capacitance of large value ceramic capacitors can vary natively, refer to the AC/DC characteristics and timing substantially, based on the amount of DC voltage requirements information in the respective device applied to the capacitor. This effect can be very signifi- Flash programming specification for information on cant, but is often overlooked or is not always capacitive loading limits, and pin input voltage high documented. (VIH) and input low (VIL) requirements. A typical DC bias voltage vs. capacitance graph for For device emulation, ensure that the “Communication X7R type and Y5V type capacitors is shown in Channel Select” (i.e., PGCx/PGDx pins), programmed Figure2-4. into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section30.0 “Development Support”. DS30009977G-page 46  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: SUGGESTED PLACEMENT OF THE Many microcontrollers have options for at least two OSCILLATOR CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts: Section3.0 “Oscillator Configurations” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSC1 Oscillator of the board. C1 ` OSC2 Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power T1OSO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board T1OS I Timer1 Oscillator where the crystal is placed. Crystal ` Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With T1 Oscillator: C1 T1 Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins, and other Bottom Layer signals in close proximity to the oscillator, are benign Copper Pour (i.e., free of high frequencies, short rise and fall times, (tied to ground) and other similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.7 Unused I/Os DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low.  2010-2017 Microchip Technology Inc. DS30009977G-page 47

PIC18F66K80 FAMILY 3.0 OSCILLATOR To optimize power consumption when using CONFIGURATIONS EC/HS/XT/LP/RC as the primary oscillator, the fre- quency input range can be configured to yield an opti- mized power bias: 3.1 Oscillator Types • Low-Power Bias – External frequency less than The PIC18F66K80 family of devices can be operated in 160kHz the following oscillator modes: • Medium Power Bias – External frequency • EC External Clock, RA6 Available between 160kHz and 16MHz • ECIO External Clock, Clock Out RA6 (FOSC/4 • High-Power Bias – External frequency greater on RA6) than 16MHz • HS High-Speed Crystal/Resonator All of these modes are selected by the user by • XT Crystal/Resonator programming the FOSC<3:0> Configuration bits • LP Low-Power Crystal (CONFIG1H<3:0>). In addition, PIC18F66K80 family • RC External Resistor/Capacitor, RA6 devices can switch between different clock sources, Available either under software control, or under certain condi- tions, automatically. This allows for additional power • RCIO External Resistor/Capacitor, Clock Out savings by managing device clock speed in real time RA6 (FOSC/4 on RA6) without resetting the application. The clock sources for • INTIO2 Internal Oscillator with I/O on RA6 and the PIC18F66K80 family of devices are shown in RA7 Figure3-1. • INTIO1 Internal Oscillator with FOSC/4 Output on For the HS and EC mode, there are additional power RA6 and I/O on RA7 modes of operation, depending on the frequency of There is also an option for running the 4xPLL on any of operation. the clock sources in the input frequency range of 4 to HS1 is the Medium Power mode with a frequency 16MHz. range of 4MHz to 16MHz. HS2 is the High-Power The PLL is enabled by setting the PLLCFG bit (CON- mode, where the oscillator frequency can go from FIG1H<4>) or the PLLEN bit (OSCTUNE<6>). 16MHz to 25MHz. HS1 and HS2 are achieved by For the EC and HS modes, the PLLEN (software) or setting the CONFIG1H<3:0> bits correctly. (For details, PLLCFG (CONFIG1H<4>) bit can be used to enable see Register28-2 on Page 450.) the PLL. EC mode has these modes of operation: For the INTIOx modes (HF-INTOSC): • EC1 – For low power with a frequency range up to • Only the PLLEN can enable the PLL (PLLCFG is 160kHz ignored). • EC2 – Medium power with a frequency range of • When the oscillator is configured for the internal 160kHz to 16MHz oscillator (FOSC<3:0>= 100x), the PLL can be • EC3 – High power with a frequency range of enabled only when the HF-INTOSC frequency is 16MHz to 64MHz 4, 8 or 16MHz. EC1, EC2 and EC3 are achieved by setting the CON- When the RA6 and RA7 pins are not used for an oscil- FIG1H<3:0> correctly. (For details, see Register28-2 lator function or CLKOUT function, they are available on Page 450.) as general purpose I/Os. Table3-1 shows the HS and EC modes’ frequency range and FOSC<3:0> settings. DS30009977G-page 48  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 3-1: HS, EC, XT, LP AND RC MODES: RANGES AND SETTINGS Mode Frequency Range FOSC<3:0> Setting EC1 (low power) 1101 DC-160kHz (EC1 & EC1IO) 1100 EC2 (medium power) 1011 160kHz-16MHz (EC2 & EC2IO) 1010 EC3 (high power) 0101 16MHz-64MHz (EC3 & EC3IO) 0100 HS1 (medium power) 4MHz-16MHz 0011 HS2 (high power) 16MHz-25MHz 0010 XT 100kHz-4MHz 0001 LP 31.25kHz 0000 RC (External) 0-4MHz 001x INTIO 100x 32kHz-16MHz (and OSCCON, OSCCON2) FIGURE 3-1: PIC18F66K80 FAMILY CLOCK DIAGRAM SOSCO SOSCI OSC2 UX 4x PLL MUX MUX Peripherals M CPU OSC1 PLLEN FOSC<3:0> and PLLCFG IDLEN 16 MHz 16 MHz 111 8 MHz 8 MHz 110 Clock Control SCS<1:0> 4 MHz 4 MHz er 101 H1F63- I1MN kTHHOzz StoC ostscal 5210 MM0 HHkzzHz 50120 MMkHHHzzz 100101 MUX FOSC<3:0> P 010 250 kHz 250 kHz 001 31 kHz 31 kHz 000 X M5F03-01I Nk kTHHOzz StoC stscaler 352105 00k HkkHHzzz MU MUX IRCF<2:0> o P INTSRC MFIOSEL LF-INTOSC 31 kHz 31 kHz  2010-2017 Microchip Technology Inc. DS30009977G-page 49

PIC18F66K80 FAMILY 3.2 Control Registers The OSCTUNE register (Register3-3) controls the tuning and operation of the internal oscillator block. It also The OSCCON register (Register3-1) controls the main implements the PLLEN bit which controls the operation of aspects of the device clock’s operation. It selects the the Phase Locked Loop (PLL) (see Section3.5.3 “PLL oscillator type to be used, which of the power-managed Frequency Multiplier”). modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators. REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-1 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2(2) IRCF1(2) IRCF0(2) OSTS HFIOFS SCS1(4) SCS0(4) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode when a SLEEP instruction is executed 0 = Device enters Sleep mode when a SLEEP instruction is executed bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits(2) 111 = HF-INTOSC output frequency is used (16MHz) 110 = HF-INTOSC/2 output frequency is used (8MHz, default) 101 = HF-INTOSC/4 output frequency is used (4MHz) 100 = HF-INTOSC/8 output frequency is used (2MHz) 011 = HF-INTOSC/16 output frequency is used (1MHz) If INTSRC = 0 and MFIOSEL = 0:(3,5) 010 = HF-INTOSC/32 output frequency is used (500kHz) 001 = HF-INTOSC/64 output frequency is used (250kHz) 000 = LF-INTOSC output frequency is used (31.25kHz)(6) If INTSRC = 1 and MFIOSEL = 0:(3,5) 010 = HF-INTOSC/32 output frequency is used (500kHz) 001 = HF-INTOSC/64 output frequency is used (250kHz) 000 = HF-INTOSC/512 output frequency is used (31.25kHz) If INTSRC = 0 and MFIOSEL = 1:(3,5) 010 = MF-INTOSC output frequency is used (500kHz) 001 = MF-INTOSC/2 output frequency is used (250kHz) 000 = LF-INTOSC output frequency is used (31.25kHz)(6) If INTSRC = 1 and MFIOSEL = 1:(3,5) 010 = MF-INTOSC output frequency is used (500kHz) 001 = MF-INTOSC/2 output frequency is used (250kHz) 000 = MF-INTOSC/16 output frequency is used (31.25kHz) bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running, as defined by FOSC<3:0> 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready – device is running from internal oscillator (HF-INTOSC, MF-INTOSC or LF-INTOSC) Note 1: The Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>). 2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. 3: The source is selected by the INTSRC bit (OSCTUNE<7>). 4: Modifying these bits will cause an immediate clock source switch. 5: INTSRC= OSCTUNE<7> and MFIOSEL= OSCCON2<0>. 6: This is the lowest power option for an internal source. DS30009977G-page 50  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 2 HFIOFS: HF-INTOSC Frequency Stable bit 1 = HF-INTOSC oscillator frequency is stable 0 = HF-INTOSC oscillator frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits(4) 1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC) 01 = SOSC oscillator 00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL; defined by the FOSC<3:0> Configuration bits, CONFIG1H<3:0>) Note 1: The Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>). 2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. 3: The source is selected by the INTSRC bit (OSCTUNE<7>). 4: Modifying these bits will cause an immediate clock source switch. 5: INTSRC= OSCTUNE<7> and MFIOSEL= OSCCON2<0>. 6: This is the lowest power option for an internal source. REGISTER 3-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 R-0 U-0 R/W-1 R/W-0 U-0 R-x R/W-0 — SOSCRUN — SOSCDRV(1) SOSCGO — MFIOFS MFIOSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from a secondary SOSC 0 = System clock comes from an oscillator other than SOSC bit 5 Unimplemented: Read as ‘0’ bit 4 SOSCDRV: Secondary Oscillator Drive Control bit(1) 1 = High-power SOSC circuit is selected 0 = Low/high-power select is done via the SOSCSEL<1:0> Configuration bits bit 3 SOSCGO: Oscillator Start Control bit 1 = Oscillator is running even if no other sources are requesting it. 0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.) bit 2 Unimplemented: Read as ‘0’ bit 1 MFIOFS: MF-INTOSC Frequency Stable bit 1 = MF-INTOSC is stable 0 = MF-INTOSC is not stable bit 0 MFIOSEL: MF-INTOSC Select bit 1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500kHz, 250kHz and 31.25kHz 0 = MF-INTOSC is not used Note 1: When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.  2010-2017 Microchip Technology Inc. DS30009977G-page 51

PIC18F66K80 FAMILY REGISTER 3-3: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock is derived from 16MHz INTOSC source (divide-by-512 enabled, HF-INTOSC) 0 = 31kHz device clock is derived from INTOSC 31kHz oscillator (LF-INTOSC) bit 6 PLLEN: Frequency Multiplier PLL Enable bit 1 = PLL is enabled 0 = PLL is disabled bit 5-0 TUN<5:0>: Fast RC Oscillator (INTOSC) Frequency Tuning bits 011111 = Maximum frequency • • • • 000001 000000 = Center frequency; fast RC oscillator is running at the calibrated frequency 111111 • • • • 100000 = Minimum frequency DS30009977G-page 52  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 3.3 Clock Sources and In addition to being a primary clock source in some Oscillator Switching circumstances, the internal oscillator is available as a power-managed mode clock source. The LF-INTOSC Essentially, PIC18F66K80 family devices have these source is also used as the clock source for several independent clock sources: special features, such as the WDT and Fail-Safe Clock • Primary oscillators Monitor. The internal oscillator block is discussed in • Secondary oscillators more detail in Section3.6 “Internal Oscillator • Internal oscillator Block”. The primary oscillators can be thought of as the main The PIC18F66K80 family includes features that allow device oscillators. These are any external oscillators the device clock source to be switched from the main connected to the OSC1 and OSC2 pins, and include oscillator, chosen by device configuration, to one of the the External Crystal and Resonator modes and the alternate clock sources. When an alternate clock External Clock modes. If selected by the FOSC<3:0> source is enabled, various power-managed operating Configuration bits (CONFIG1H<3:0>), the internal modes are available. oscillator block may be considered a primary oscillator. 3.3.1 OSC1/OSC2 OSCILLATOR The internal oscillator block can be one of the following: The OSC1/OSC2 oscillator block is used to provide the • 31kHz LF-INTOSC source oscillator modes and frequency ranges: • 31kHz to 500kHz MF-INTOSC source • 31kHz to 16MHz HF-INTOSC source Mode Design Operating Frequency The particular mode is defined by the FOSCx LP 31.25-100kHz Configuration bits. The details of these modes are XT 100kHz to 4MHz covered in Section3.5 “External Oscillator Modes”. HS 4MHz to 25MHz The secondary oscillators are external clock EC 0 to 64MHz (external clock) sources that are not connected to the OSC1 or OSC2 pin. These sources may continue to operate, even EXTRC 0 to 4MHz (external RC) after the controller is placed in a power-managed The crystal-based oscillators (XT, HS and LP) have a mode. PIC18F66K80 family devices offer the SOSC built-in start-up time. The operation of the EC and (Timer1/3/5/7) oscillator as a secondary oscillator EXTRC clocks is immediate. source. The SOSC can be enabled from any peripheral that 3.3.2 CLOCK SOURCE SELECTION requests it. The SOSC can be enabled several ways by The System Clock Select bits, SCS<1:0> doing one of the following: (OSCCON<1:0>), select the clock source. The avail- • The SOSC is selected as the source by either of able clock sources are the primary clock defined by the the odd timers, which is done by each respective FOSC<3:0> Configuration bits, the secondary clock SOSCEN bit (TxCON<3>) (SOSC oscillator) and the internal oscillator. The clock source changes after one or more of the bits is written • The SOSC is selected as the CPU clock source to, following a brief clock transition interval. by the SCSx bits (OSCCON<1:0>) • The SOSCGO bit is set (OSCCON2<3>) The OSTS (OSCCON<3>) and SOSCRUN (OSCCON2<6>) bits indicate which clock source is The SOSCGO bit is used to warm up the SOSC so that currently providing the device clock. The OSTS bit it is ready before any peripheral requests it. indicates that the Oscillator Start-up Timer (OST) has The secondary oscillator has three Run modes. The timed out and the primary clock is providing the device SOSCSEL<1:0> bits (CONFIG1L<4:3>) decide the clock in primary clock modes. The SOSCRUN bit indi- SOSC mode of operation: cates when the SOSC oscillator (from Timer1/3/5/7) is • 11 = High-Power SOSC Circuit providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will • 10 = Digital (SCLKI) mode be set at any time. If neither of these bits is set, the • 11 = Low-Power SOSC Circuit INTOSC is providing the clock or the internal oscillator If a secondary oscillator is not desired and digital I/O on has just started and is not yet stable. port pins, RC0 and RC1, is needed, the SOSCSELx The IDLEN bit (OSCCON<7>) determines if the device bits must be set to Digital mode. goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed.  2010-2017 Microchip Technology Inc. DS30009977G-page 53

PIC18F66K80 FAMILY The use of the flag and control bits in the OSCCON 3.4 RC Oscillator register is discussed in more detail in Section4.0 “Power-Managed Modes”. For timing-insensitive applications, the RC and RCIO Oscillator modes offer additional cost savings. The actual Note 1: The Timer1/3/5/7 oscillator must be oscillator frequency is a function of several factors: enabled to select the secondary clock • Supply voltage source. The Timerx oscillator is enabled by • Values of the external resistor (REXT) and capacitor setting the SOSCEN bit in the Timerx Con- (CEXT) trol register (TxCON<3>). If the Timerx • Operating temperature oscillator is not enabled, then any attempt to select a secondary clock source when Given the same device, operating voltage and tempera- executing a SLEEP instruction will be ture, and component values, there will also be unit to unit ignored. frequency variations. These are due to factors such as: 2: It is recommended that the Timerx • Normal manufacturing variation oscillator be operating and stable before • Difference in lead frame capacitance between executing the SLEEP instruction or a very package types (especially for low CEXT values) long delay may occur while the Timerx • Variations within the tolerance of the limits of oscillator starts. REXT and CEXT 3.3.2.1 System Clock Selection and Device In the RC Oscillator mode, the oscillator frequency, Resets divided by 4, is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other Since the SCSx bits are cleared on all forms of Reset, logic. Figure3-2 shows how the R/C combination is this means the primary oscillator defined by the connected. FOSC<3:0> Configuration bits is used as the primary clock source on device Resets. This could either be the FIGURE 3-2: RC OSCILLATOR MODE internal oscillator block by itself, or one of the other primary clock sources (HS, EC, XT, LP, External RC VDD and PLL-enabled modes). REXT In those cases when the internal oscillator block, with- Internal OSC1 out PLL, is the default clock on Reset, the Fast RC Clock Oscillator (INTOSC) will be used as the device clock CEXT source. It will initially start at 8MHz; the postscaler PIC18F66K80 selection that corresponds to the Reset value of the VSS IRCF<2:0> bits (‘110’). OSC2/CLKO FOSC/4 Regardless of which primary oscillator is selected, INTOSC will always be enabled on device power-up. It Recommended values: 3 k  REXT  100 k serves as the clock source until the device has loaded 20 pF CEXT  300 pF its configuration values from memory. It is at this point The RCIO Oscillator mode (Figure3-3) functions like that the FOSCx Configuration bits are read and the the RC mode, except that the OSC2 pin becomes an oscillator selection of the operational mode is made. additional general purpose I/O pin. The I/O pin Note that either the primary clock source or the internal becomes bit 6 of PORTA (RA6). oscillator will have two bit setting options for the possible values of the SCS<1:0> bits, at any given time. FIGURE 3-3: RCIO OSCILLATOR MODE 3.3.3 OSCILLATOR TRANSITIONS VDD PIC18F66K80 family devices contain circuitry to REXT prevent clock “glitches” when switching between clock Internal OSC1 sources. A short pause in the device clock occurs Clock during the clock switch. The length of this pause is the CEXT sum of two cycles of the old clock source and three to PIC18F66K80 four cycles of the new clock source. This formula VSS assumes that the new clock source is stable. RA6 I/O (OSC2) Clock transitions are discussed in greater detail in Recommended values: 3 k  REXT  100 k Section4.1.2 “Entering Power-Managed Modes”. 20 pF CEXT  300 pF DS30009977G-page 54  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 3.5 External Oscillator Modes TABLE 3-3: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR 3.5.1 CRYSTAL OSCILLATOR/CERAMIC Typical Capacitor Values RESONATORS (HS MODES) Crystal Tested: Osc Type In HS or HSPLL Oscillator modes, a crystal or ceramic Freq. resonator is connected to the OSC1 and OSC2 pins to C1 C2 establish oscillation. Figure3-4 shows the pin HS 4 MHz 27 pF 27 pF connections. 8 MHz 22 pF 22 pF The oscillator design requires the use of a crystal rated 20 MHz 15 pF 15 pF for parallel resonant operation. Capacitor values are for design guidance only. Note: Use of a crystal rated for series resonant Different capacitor values may be required to produce operation may give a frequency out of the acceptable oscillator operation. The user should test crystal manufacturer’s specifications. the performance of the oscillator over the expected VDD and temperature range for the application. TABLE 3-2: CAPACITOR SELECTION FOR Refer to the Microchip application notes cited in CERAMIC RESONATORS Table3-2 for oscillator specific information. Also see the notes following this table for additional Typical Capacitor Values Used: information. Mode Freq. OSC1 OSC2 HS 8.0 MHz 27 pF 27 pF Note1: Higher capacitance increases the stability 16.0 MHz 22 pF 22 pF of oscillator but also increases the start-up Capacitor values are for design guidance only. time. Different capacitor values may be required to produce 2: Since each resonator/crystal has its own acceptable oscillator operation. The user should test characteristics, the user should consult the performance of the oscillator over the expected the resonator/crystal manufacturer for VDD and temperature range for the application. Refer appropriate values of external components. to the following application notes for oscillator-specific 3: Rs may be required to avoid overdriving information: crystals with low drive level specification. • AN588, “PIC® Microcontroller Oscillator Design 4: Always verify oscillator performance over Guide” the VDD and temperature range that is • AN826, “Crystal Oscillator Basics and Crystal expected for the application. Selection for rfPIC® and PIC® Devices” • AN849, “Basic PIC® Oscillator Design” FIGURE 3-4: CRYSTAL/CERAMIC • AN943, “Practical PIC® Oscillator Analysis and RESONATOR OPERATION Design” (HS OR HSPLL • AN949, “Making Your Oscillator Work” CONFIGURATION) See the notes following Table3-3 for additional information. C1(1) OSC1 To Internal XTAL RF(3) Logic Sleep OSC2 C2(1) RS(2) PIC18F66K80 Note 1: See Table3-2 and Table3-3 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen.  2010-2017 Microchip Technology Inc. DS30009977G-page 55

PIC18F66K80 FAMILY 3.5.2 EXTERNAL CLOCK INPUT 3.5.3.1 HSPLL and ECPLL Modes (EC MODES) The HSPLL and ECPLL modes provide the ability to The EC and ECPLL Oscillator modes require an selectively run the device at four times the external external clock source to be connected to the OSC1 pin. oscillating source to produce frequencies up to There is no oscillator start-up time required after a 64MHz. Power-on Reset or after an exit from Sleep mode. The PLL is enabled by setting the PLLEN bit In the EC Oscillator mode, the oscillator frequency (OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>). divided by 4 is available on the OSC2 pin. This signal For the HF-INTOSC as primary, the PLL must be may be used for test purposes or to synchronize other enabled with the PLLEN. This provides a software con- logic. Figure3-5 shows the pin connections for the EC trol for the PLL, enabling even if PLLCFG is set to ‘1’, Oscillator mode. so that the PLL is enabled only when the HF-INTOSC frequency is within the 4 MHz to16 MHz input range. FIGURE 3-5: EXTERNAL CLOCK This also enables additional flexibility for controlling the INPUT OPERATION application’s clock speed in software. The PLLEN (EC CONFIGURATION) should be enabled in HF-INTOSC mode only if the input frequency is in the range of 4MHz-16MHz. Clock from OSC1/CLKI FIGURE 3-7: PLL BLOCK DIAGRAM Ext. System PIC18F66K80 PLLCFG (CONFIG1H<4>) FOSC/4 OSC2/CLKO PLL Enable (OSCTUNE<6>) An external clock source may also be connected to the OSC2 OSC1 pin in the HS mode, as shown in Figure3-6. In Phase this configuration, the divide-by-4 output on OSC2 is HS or EC FIN Comparator not available. Current consumption in this configuration OSC1 Mode FOUT will be somewhat higher than EC mode, as the internal oscillator’s feedback circuitry will be enabled (in EC Loop mode, the feedback circuit is disabled). Filter FIGURE 3-6: EXTERNAL CLOCK INPUT OPERATION (HS OSC 4 VCO SYSCLK CONFIGURATION) X U M Clock from OSC1 Ext. System PIC18F66K80 (HS Mode) 3.5.3.2 PLL and HF-INTOSC Open OSC2 The PLL is available to the internal oscillator block when the internal oscillator block is configured as the primary clock source. In this configuration, the PLL is 3.5.3 PLL FREQUENCY MULTIPLIER enabled in software and generates a clock output of up A Phase Lock Loop (PLL) circuit is provided as an to 64MHz. option for users who want to use a lower frequency The operation of INTOSC with the PLL is described in oscillator circuit or to clock the device up to its highest Section3.6.2 “INTPLL Modes”. Care should be taken rated frequency from a crystal oscillator. This may be that the PLL is enabled only if the HF-INTOSC useful for customers who are concerned with EMI due postscaler is configured for 4MHz, 8MHz or 16MHz. to high-frequency crystals or users who require higher clock speeds from an internal oscillator. DS30009977G-page 56  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 3.6 Internal Oscillator Block FIGURE 3-8: INTIO1 OSCILLATOR MODE The PIC18F66K80 family of devices includes an internal oscillator block which generates two different clock RA7 I/O (OSC1) signals. Either clock can be used as the microcontroller’s clock source, which may eliminate the need for an PIC18F66K80 external oscillator circuit on the OSC1 and/or OSC2 pins. FOSC/4 OSC2 The Internal oscillator consists of three blocks, depending on the frequency of operation. They are HF-INTOSC, MF-INTOSC and LF-INTOSC. In HF-INTOSC mode, the internal oscillator can provide FIGURE 3-9: INTIO2 OSCILLATOR MODE a frequency ranging from 31KHz to 16MHz, with the postscaler deciding the selected frequency RA7 I/O (OSC1) (IRCF<2:0>). PIC18F66K80 The INTSRC bit (OSCTUNE<7>) and MFIOSEL bit (OSCCON2<0>) also decide which INTOSC provides RA6 I/O (OSC2) the lower frequency (500kHz to 31KHz). For the HF-INTOSC to provide these frequencies, INTSRC= 1 and MFIOSEL = 0. In HF-INTOSC, the postscaler (IRCF<2:0>) provides 3.6.2 INTPLL MODES the frequency range of 31kHz to 16MHz. If The 4x Phase Lock Loop (PLL) can be used with the HF-INTOSC is used with the PLL, the input frequency HF-INTOSC to produce faster device clock speeds to the PLL should be 4 MHz to 16 MHz than are normally possible with the internal oscillator (IRCF<2:0>=111, 110 or 101). sources. When enabled, the PLL produces a clock For MF-INTOSC mode to provide a frequency range of speed of 16MHz or 64MHz. 500kHz to 31kHz, INTSRC = 1 and MFIOSEL = 1. The postscaler (IRCF<2:0>), in this mode, provides the PLL operation is controlled through software. The frequency range of 31kHz to 500kHz. control bits, PLLEN (OSCTUNE<6>) and PLLCFG (CONFIG1H<4>), are used to enable or disable its The LF-INTOSC can provide only 31kHz if INTSRC = 0. operation. The PLL is available only to HF-INTOSC. The LF-INTOSC provides 31kHz and is enabled if it is The other oscillator is set with HS and EC modes. Addi- selected as the device clock source. The mode is tionally, the PLL will only function when the selected enabled automatically when any of the following are output frequency is either 4 MHz or 16 MHz enabled: (OSCCON<6:4> = 111, 110 or 101). • Power-up Timer (PWRT) Like the INTIO modes, there are two distinct INTPLL • Fail-Safe Clock Monitor (FSCM) modes available: • Watchdog Timer (WDT) • In INTPLL1 mode, the OSC2 pin outputs FOSC/4, • Two-Speed Start-up while OSC1 functions as RA7 for digital input and These features are discussed in greater detail in output. Externally, this is identical in appearance Section28.0 “Special Features of the CPU”. to INTIO1 (see Figure3-8). The clock source frequency (HF-INTOSC, MF-INTOSC • In INTPLL2 mode, OSC1 functions as RA7 and or LF-INTOSC direct) is selected by configuring the OSC2 functions as RA6, both for digital input and IRCFx bits of the OSCCON register, as well the output. Externally, this is identical to INTIO2 (see INTSRC and MFIOSEL bits. The default frequency on Figure3-9). device Resets is 8MHz. 3.6.1 INTIO MODES Using the internal oscillator as the clock source elimi- nates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct oscillator configurations, which are determined by the FOSCx Configuration bits, are available: • In INTIO1 mode, the OSC2 pin (RA6) outputs FOSC/4, while OSC1 functions as RA7 (see Figure3-8) for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure3-9). Both are available as digital input and output ports.  2010-2017 Microchip Technology Inc. DS30009977G-page 57

PIC18F66K80 FAMILY 3.6.3 INTERNAL OSCILLATOR OUTPUT 3.6.4.3 Compensating with the CCP Module FREQUENCY AND TUNING in Capture Mode The internal oscillator block is calibrated at the factory A CCP module can use free-running Timer1 (or Tim- to produce an INTOSC output frequency of 16 MHz. It er3), clocked by the internal oscillator block and an can be adjusted in the user’s application by writing to external event with a known period (i.e., AC power TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE frequency). The time of the first event is captured in the register (Register3-3). CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the When the OSCTUNE register is modified, the INTOSC time of the first event is subtracted from the time of the (HF-INTOSC and MF-INTOSC) frequency will begin second event. Since the period of the external event is shifting to the new frequency. The oscillator will require known, the time difference between events can be some time to stabilize. Code execution continues calculated. during this shift and there is no indication that the shift has occurred. If the measured time is much greater than the calculated time, the internal oscillator block is running The LF-INTOSC oscillator operates independently of too fast. To compensate, decrement the OSCTUNE the HF-INTOSC or the MF-INTOSC source. Any register. If the measured time is much less than the changes in the HF-INTOSC or the MF-INTOSC source, calculated time, the internal oscillator block is running across voltage and temperature, are not necessarily too slow. To compensate, increment the OSCTUNE reflected by changes in LF-INTOSC or vice versa. The register. frequency of LF-INTOSC is not affected by OSCTUNE. 3.6.4 INTOSC FREQUENCY DRIFT 3.7 Reference Clock Output The INTOSC frequency may drift as VDD or tempera- In addition to the FOSC/4 clock output, in certain ture changes and can affect the controller operation in oscillator modes, the device clock in the PIC18F66K80 a variety of ways. It is possible to adjust the INTOSC family can also be configured to provide a reference frequency by modifying the value in the OSCTUNE clock output signal to a port pin. This feature is avail- register. Depending on the device, this may have no able in all oscillator configurations and allows the user effect on the LF-INTOSC clock source frequency. to select a greater range of clock submultiples to drive Tuning INTOSC requires knowing when to make the external devices in the application. adjustment, in which direction it should be made, and in This reference clock output is controlled by the some cases, how large a change is needed. Three REFOCON register (Register3-4). Setting the ROON compensation techniques are shown here. bit (REFOCON<7>) makes the clock signal available on the REFO (RC3) pin. The RODIV<3:0> bits enable 3.6.4.1 Compensating with the EUSARTx the selection of 16 different clock divider options. An adjustment may be required when the EUSARTx The ROSSLP and ROSEL bits (REFOCON<5:4>) con- begins to generate framing errors or receives data with trol the availability of the reference output during Sleep errors while in Asynchronous mode. Framing errors mode. The ROSEL bit determines if the oscillator on indicate that the device clock frequency is too high. To OSC1 and OSC2, or the current system clock source, adjust for this, decrement the value in OSCTUNE to is used for the reference clock output. The ROSSLP bit reduce the clock frequency. On the other hand, errors determines if the reference source is available on RE3 in data may suggest that the clock speed is too low. To when the device is in Sleep mode. compensate, increment OSCTUNE to increase the To use the reference clock output in Sleep mode, both clock frequency. the ROSSLP and ROSEL bits must be set. The device 3.6.4.2 Compensating with the Timers clock must also be configured for an EC or HS mode. If not, the oscillator on OSC1 and OSC2 will be powered This technique compares device clock speed to some down when the device enters Sleep mode. Clearing the reference clock. Two timers may be used; one timer is ROSEL bit allows the reference output frequency to clocked by the peripheral clock, while the other is change as the system clock changes during any clock clocked by a fixed reference source, such as the SOSC switches. oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. DS30009977G-page 58  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL(1) RODIV3 RODIV2 RODIV1 RODIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is available on REFO pin 0 = Reference oscillator output is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 4 ROSEL: Reference Oscillator Source Select bit(1) 1 = Primary oscillator (EC or HS) is used as the base clock 0 = System clock is used as the base clock; base clock reflects any clock switching of the device bit 3-0 RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value Note 1: For ROSEL (REFOCON<4>), the primary oscillator is available only when configured as the default via the FOSCx settings. This is regardless of whether the device is in Sleep mode.  2010-2017 Microchip Technology Inc. DS30009977G-page 59

PIC18F66K80 FAMILY 3.8 Effects of Power-Managed Modes 3.9 Power-up Delays on the Various Clock Sources Power-up delays are controlled by two timers, so that no When PRI_IDLE mode is selected, the designated pri- external Reset circuitry is required for most applications. mary oscillator continues to run without interruption. The delays ensure that the device is kept in Reset until For all other power-managed modes, the oscillator the device power supply is stable under normal circum- using the OSC1 pin is disabled. The OSC1 pin (and stances and the primary clock is operating and stable. OSC2 pin if used by the oscillator) will stop oscillating. For additional information on power-up delays, see Section5.6.1 “Power-up Timer (PWRT)”. In secondary clock modes (SEC_RUN and SEC_I- DLE), the SOSC oscillator is operating and providing The first timer is the Power-up Timer (PWRT), which the device clock. The SOSC oscillator may also run in provides a fixed delay on power-up time of about 64ms all power-managed modes if required to clock SOSC. (Parameter 33, Table31-11); it is always enabled. In RC_RUN and RC_IDLE modes, the internal The second timer is the Oscillator Start-up Timer oscillator provides the device clock source. The 31kHz (OST), intended to keep the chip in Reset until the LF-INTOSC output can be used directly to provide the crystal oscillator is stable (HS, XT or LP modes). The clock and may be enabled to support various special OST does this by counting 1,024 oscillator cycles features, regardless of the power-managed mode (see before allowing the oscillator to clock the device. Section28.2 “Watchdog Timer (WDT)” through There is a delay of interval, TCSD (Parameter 38, Section28.5 “Fail-Safe Clock Monitor” for more Table31-11), following POR, while the controller information on WDT, Fail-Safe Clock Monitor and becomes ready to execute instructions. Two-Speed Start-up). If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTOSC is required to support WDT operation. The SOSC oscillator may be operating to support Timer1 or 3. Other features may be operating that do not require a device clock source (i.e., MSSP slave, INTx pins and others). Peripherals that may add significant current con- sumption are listed in Section31.2 “DC Characteris- tics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended)”. TABLE 3-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output) HS, HSPLL Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level INTOSC, INTPLL1/2 I/O pin, RA6, direction controlled by I/O pin, RA6, direction controlled by TRISA<6> TRISA<7> Note: See Section5.0 “Reset” for time-outs due to Sleep and MCLR Reset. DS30009977G-page 60  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 4.0 POWER-MANAGED MODES The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the The PIC18F66K80 family of devices offers a total of clock source. The individual modes, bit settings, clock seven operating modes for more efficient power man- sources and affected modules are summarized in agement. These modes provide a variety of options for Table4-1. selective power conservation in applications where resources may be limited (such as battery-powered 4.1.1 CLOCK SOURCES devices). The SCS<1:0> bits select one of three clock sources There are three categories of power-managed mode: for power-managed modes. Those sources are: • Run modes • The primary clock as defined by the FOSC<3:0> • Idle modes Configuration bits • Sleep mode • The Secondary Clock (the SOSC oscillator) • The Internal Oscillator block (for LF-INTOSC There is an Ultra Low-Power Wake-up (ULPWU) for modes) waking from Sleep mode. These categories define which portions of the device 4.1.2 ENTERING POWER-MANAGED are clocked, and sometimes, at what speed. The Run MODES and Idle modes may use any of the three available Switching from one power-managed mode to another clock sources (primary, secondary or internal oscillator begins by loading the OSCCON register. The block). The Sleep mode does not use a clock source. SCS<1:0> bits select the clock source and determine The ULPWU mode, on the RA0 pin, enables a slow fall- which Run or Idle mode is used. Changing these bits ing voltage to generate a wake-up, even from Sleep, causes an immediate switch to the new clock source, without excess current consumption. (See Section4.7 assuming that it is running. The switch may also be “Ultra Low-Power Wake-up”.) subject to clock transition delays. These considerations The power-managed modes include several are discussed in Section4.1.3 “Clock Transitions power-saving features offered on previous PIC® and Status Indicators” and subsequent sections. devices. One is the clock switching feature, offered in Entering the power-managed Idle or Sleep modes is other PIC18 devices. This feature allows the controller triggered by the execution of a SLEEP instruction. The to use the SOSC oscillator instead of the primary one. actual mode that results depends on the status of the Another power-saving feature is Sleep mode, offered IDLEN bit. by all PIC devices, where all device clocks are stopped. Depending on the current and impending mode, a change to a power-managed mode does not always 4.1 Selecting Power-Managed Modes require setting all of the previously discussed bits. Many Selecting a power-managed mode requires two transitions can be done by changing the oscillator select decisions: bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured as • Will the CPU be clocked or not desired, it may only be necessary to perform a SLEEP • What will be the clock source instruction to switch to the desired mode. TABLE 4-1: POWER-MANAGED MODES OSCCON Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled Primary – XT, LP, HS, EC, RC and PLL modes. PRI_RUN N/A 00 Clocked Clocked This is the normal, full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator RC_RUN N/A 1x Clocked Clocked Internal oscillator block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – SOSC oscillator RC_IDLE 1 1x Off Clocked Internal oscillator block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC source.  2010-2017 Microchip Technology Inc. DS30009977G-page 61

PIC18F66K80 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS 4.1.4 MULTIPLE SLEEP COMMANDS INDICATORS The power-managed mode that is invoked with the The length of the transition between clock sources is SLEEP instruction is determined by the setting of the the sum of two cycles of the old clock source and three IDLEN bit at the time the instruction is executed. If to four cycles of the new clock source. This formula another SLEEP instruction is executed, the device will assumes that the new clock source is stable. The enter the power-managed mode specified by IDLEN at HF-INTOSC and MF-INTOSC are termed as INTOSC that time. If IDLEN has changed, the device will enter in this chapter. the new power-managed mode specified by the new Three bits indicate the current clock source and its setting. status, as shown in Table4-2. The three bits are: 4.2 Run Modes • OSTS (OSCCON<3>) In the Run modes, clocks to both the core and • HFIOFS (OSCCON<2>) peripherals are active. The difference between these • SOSCRUN (OSCCON2<6>) modes is the clock source. TABLE 4-2: SYSTEM CLOCK INDICATOR 4.2.1 PRI_RUN MODE HFIOFS or The PRI_RUN mode is the normal, full-power execu- Main Clock Source OSTS SOSCRUN MFIOFS tion mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up Primary Oscillator 1 0 0 is enabled. (For details, see Section28.4 “Two-Speed INTOSC (HF-INTOSC 0 1 0 Start-up”.) In this mode, the OSTS bit is set. The or MF-INTOSC) HFIOFS or MFIOFS bit may be set if the internal Secondary Oscillator 0 0 1 oscillator block is the primary clock source. (See MF-INTOSC or Section3.2 “Control Registers”.) HF-INTOSC as Primary 1 1 0 4.2.2 SEC_RUN MODE Clock Source The SEC_RUN mode is the compatible mode to the LF-INTOSC is “clock-switching” feature offered in other PIC18 Running or INTOSC is 0 0 0 devices. In this mode, the CPU and peripherals are Not Yet Stable clocked from the SOSC oscillator. This enables lower When the OSTS bit is set, the primary clock is providing power consumption while retaining a high-accuracy the device clock. When the HFIOFS or MFIOFS bit is clock source. set, the INTOSC output is providing a stable clock SEC_RUN mode is entered by setting the SCS<1:0> source to a divider that actually drives the device clock. bits to ‘01’. The device clock source is switched to the When the SOSCRUN bit is set, the SOSC oscillator is SOSC oscillator (see Figure4-1), the primary oscillator providing the clock. If none of these bits are set, either is shut down, the SOSCRUN bit (OSCCON2<6>) is set the LF-INTOSC clock source is clocking the device or and the OSTS bit is cleared. the INTOSC source is not yet stable. Note: The SOSC oscillator can be enabled by If the internal oscillator block is configured as the setting the SOSCGO bit (OSCCON2<3>). primary clock source by the FOSC<3:0> Configuration If this bit is set, the clock switch to the bits (CONFIG1H<3:0>). Then, the OSTS and HFIOFS SEC_RUN mode can switch immediately or MFIOFS bits can be set when in PRI_RUN or PRI_I- once SCS<1:0> are set to ‘01’. DLE mode. This indicates that the primary clock (INTOSC output) is generating a stable output. Enter- On transitions from SEC_RUN mode to PRI_RUN ing another INTOSC power-managed mode at the mode, the peripherals and CPU continue to be clocked same frequency would clear the OSTS bit. from the SOSC oscillator while the primary clock is Note1: Caution should be used when modifying started. When the primary clock becomes ready, a a single IRCF bit. At a lower VDD, it is clock switch back to the primary clock occurs (see possible to select a higher clock speed Figure4-2). When the clock switch is complete, the than is supportable by that VDD. Improper SOSCRUN bit is cleared, the OSTS bit is set and the device operation may result if the primary clock is providing the clock. The IDLEN and VDD/FOSC specifications are violated. SCSx bits are not affected by the wake-up and the SOSC oscillator continues to run. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode, or one of the Idle modes, depending on the setting of the IDLEN bit. DS30009977G-page 62  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSCI 1 2 3 n-1 n OSC1 Clock Transition(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSC OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> Bits Changed OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. 4.2.3 RC_RUN MODE This mode is entered by setting the SCS1 bit to ‘1’. To maintain software compatibility with future devices, it is In RC_RUN mode, the CPU and peripherals are recommended that the SCS0 bit also be cleared, even clocked from the internal oscillator block using the though the bit is ignored. When the clock source is INTOSC multiplexer. In this mode, the primary clock is switched to the INTOSC multiplexer (see Figure4-3), shut down. When using the LF-INTOSC source, this the primary oscillator is shut down and the OSTS bit is mode provides the best power conservation of all the cleared. The IRCFx bits may be modified at any time to Run modes, while still executing code. It works well for immediately change the clock speed. user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. Note: Caution should be used when modifying a If the primary clock source is the internal oscillator single IRCF bit. At a lower VDD, it is possible to select a higher clock speed block – either LF-INTOSC or INTOSC (MF-INTOSC or HF-INTOSC) – there are no distinguishable differences than is supportable by that VDD. Improper device operation may result if the between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, how- VDD/FOSC specifications are violated. ever, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended.  2010-2017 Microchip Technology Inc. DS30009977G-page 63

PIC18F66K80 FAMILY If the IRCFx bits and the INTSRC bit are all clear, the If the IRCFx bits are changed from all clear (thus, INTOSC output (HF-INTOSC/MF-INTOSC) is not enabling the INTOSC output) or if INTSRC or enabled and the HFIOFS and MFIOFS bits will remain MFIOSEL is set, the HFIOFS or MFIOFS bit is set after clear. There will be no indication of the current clock the INTOSC output becomes stable. For details, see source. The LF-INTOSC source is providing the device Table4-3. clocks. TABLE 4-3: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS IRCF<2:0> INTSRC MFIOSEL Status of MFIOFS or HFIOFS when INTOSC is Stable 000 0 x MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC 000 1 0 MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC 000 1 1 MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC Non-Zero x 0 MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC Non-Zero x 1 MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC Clocks to the device continue while the INTOSC source On transitions from RC_RUN mode to PRI_RUN mode, stabilizes after an interval of TIOBST (Parameter 39, the device continues to be clocked from the INTOSC Table31-11). multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the If the IRCFx bits were previously at a non-zero value, primary clock occurs (see Figure4-4). When the clock or if INTSRC was set before setting SCS1 and the switch is complete, the HFIOFS or MFIOFS bit is INTOSC source was already stable, the HFIOFS or cleared, the OSTS bit is set and the primary clock is MFIOFS bit will remain set. providing the device clock. The IDLEN and SCSx bits are not affected by the switch. The LF-INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor (FSCM) is enabled. DS30009977G-page 64  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 LF-INTOSC 1 2 3 n-1 n OSC1 Clock Transition(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> Bits Changed OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC.  2010-2017 Microchip Technology Inc. DS30009977G-page 65

PIC18F66K80 FAMILY 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode in the PIC18F66K80 The Idle modes allow the controller’s CPU to be family of devices is identical to the legacy Sleep mode selectively shut down while the peripherals continue to offered in all other PIC devices. It is entered by clearing operate. Selecting a particular Idle mode allows users the IDLEN bit (the default state on device Reset) and to further manage power consumption. executing the SLEEP instruction. This shuts down the If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is selected oscillator (Figure4-5). All clock source status executed, the peripherals will be clocked from the clock bits are cleared. source selected using the SCS<1:0> bits. The CPU, Entering Sleep mode from any other mode does not however, will not be clocked. The clock source status bits require a clock switch. This is because no clocks are are not affected. This approach is a quick method to needed once the controller has entered Sleep. If the switch from a given Run mode to its corresponding Idle WDT is selected, the LF-INTOSC source will continue mode. to operate. If the SOSC oscillator is enabled, it will also If the WDT is selected, the LF-INTOSC source will continue to run. continue to operate. If the SOSC oscillator is enabled, When a wake event occurs in Sleep mode (by interrupt, it will also continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS<1:0> bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure4-6). Alternately, the device time-out or a Reset. When a wake event occurs, CPU will be clocked from the internal oscillator block if either execution is delayed by an interval of TCSD the Two-Speed Start-up or the Fail-Safe Clock Monitor is (Parameter38, Table31-11) while it becomes ready to enabled (see Section28.0 “Special Features of the execute code. When the CPU begins executing code, CPU”). In either case, the OSTS bit is set when the it resumes with the same clock source for the current primary clock is providing the device clocks. The IDLEN Idle mode. For example, when waking from RC_IDLE and SCSx bits are not affected by the wake-up. mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCSx bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS Bit Set Note1:TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS30009977G-page 66  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the SOSC clock. For timing-sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation with its more ting the IDLEN bit and executing a SLEEP instruction. If accurate, primary clock source, since the clock source the device is in another Run mode, set the IDLEN bit does not have to “warm-up” or transition from another first, then set the SCS<1:0> bits to ‘01’ and execute oscillator. SLEEP. When the clock source is switched to the SOSC oscillator, the primary oscillator is shut down, the OSTS PRI_IDLE mode is entered from PRI_RUN mode by bit is cleared and the SOSCRUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCSx bits and execute SLEEP. be clocked from the SOSC oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins to be clocked from the primary clock source specified executing code that is being clocked by the SOSC by the FOSC<3:0> Configuration bits. The OSTS bit oscillator. The IDLEN and SCSx bits are not affected by remains set (see Figure4-7). the wake-up and the SOSC oscillator continues to run (see Figure4-8). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD (Parameter 39, Table31-11), is required between the wake event and the start of code execution. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCSx bits are not affected by the wake-up (see Figure4-8). FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event  2010-2017 Microchip Technology Inc. DS30009977G-page 67

PIC18F66K80 FAMILY 4.4.3 RC_IDLE MODE 4.5 Selective Peripheral Module Control In RC_IDLE mode, the CPU is disabled but the periph- erals continue to be clocked from the internal oscillator Idle mode allows users to substantially reduce power block using the INTOSC multiplexer. This mode consumption by stopping the CPU clock. Even so, provides controllable power conservation during Idle peripheral modules still remain clocked, and thus, con- periods. sume power. There may be cases where the application From RC_RUN, this mode is entered by setting the needs what this mode does not provide: the allocation of IDLEN bit and executing a SLEEP instruction. If the power resources to the CPU processing with minimal device is in another Run mode, first set IDLEN, then set power consumption from the peripherals. the SCS1 bit and execute SLEEP. To maintain software PIC18F66K80 family devices address this requirement compatibility with future devices, it is recommended by allowing peripheral modules to be selectively that SCS0 also be cleared, though its value is ignored. disabled, reducing or eliminating their power The INTOSC multiplexer may be used to select a consumption. This can be done with two control bits: higher clock frequency by modifying the IRCFx bits before executing the SLEEP instruction. When the • Peripheral Enable bit, generically named XXXEN – clock source is switched to the INTOSC multiplexer, the Located in the respective module’s main control primary oscillator is shut down and the OSTS bit is register cleared. • Peripheral Module Disable (PMD) bit, generically named, XXXMD – Located in one of the PMDx If the IRCFx bits are set to any non-zero value, or the Control registers (PMD0, PMD1 or PMD2) INTSRC/MFIOSEL bit is set, the INTOSC output is enabled. The HFIOFS/MFIOFS bits become set, after Disabling a module by clearing its XXXEN bit disables the INTOSC output becomes stable, after an interval of the module’s functionality, but leaves its registers TIOBST (Parameter38, Table31-11). For information on available to be read and written to. This reduces power the HFIOFS/MFIOFS bits, see Table4-3. consumption, but not by as much as the second approach. Clocks to the peripherals continue while the INTOSC source stabilizes. The HFIOFS/MFIOFS bits will Most peripheral modules have an enable bit. remain set if the IRCFx bits were previously at a In contrast, setting the PMD bit for a module disables non-zero value or if INTSRC was set before the SLEEP all clock sources to that module, reducing its power instruction was executed and the INTOSC source was consumption to an absolute minimum. In this state, the already stable. If the IRCFx bits and INTSRC are all control and status registers associated with the periph- clear, the INTOSC output will not be enabled, the eral are also disabled, so writes to those registers have HFIOFS/MFIOFS bits will remain clear and there will be no effect and read values are invalid. Many peripheral no indication of the current clock source. modules have a corresponding PMD bit. When a wake event occurs, the peripherals continue to There are three PMD registers in PIC18F66K80 family be clocked from the INTOSC multiplexer. After a delay devices: PMD0, PMD1 and PMD2. These registers of TCSD (Parameter 38, Table31-11) following the wake have bits associated with each module for disabling or event, the CPU begins executing code clocked by the enabling a particular peripheral. INTOSC multiplexer. The IDLEN and SCSx bits are not affected by the wake-up. The INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. DS30009977G-page 68  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 4-1: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — MODMD(1) ECANMD CMP2MD CMP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 MODMD: Modulator Output Module Disable bit(1) 1 = The modulator output module is disabled; all Modulator Output registers are held in Reset and are not writable 0 = The modulator output module is enabled bit 2 ECANMD: Enhanced CAN Module Disable bit 1 = The Enhanced CAN module is disabled; all Enhanced CAN registers are held in Reset and are not writable 0 = The Enhanced CAN module is enabled bit 1 CMP2MD: Comparator 2 Module Disable bit 1 = The Comparator 2 module is disabled; all Comparator 2 registers are held in Reset and are not writable 0 = The Comparator 2 module is enabled bit 0 CMP1MD: Comparator 1 Module Disable bit 1 = The Comparator 1 module is disabled; all Comparator 1 registers are held in Reset and are not writable 0 = The Comparator 1 module is enabled Note 1: This bit is only implemented on devices with 64 pins (PIC18F6XK80, PIC18LF6XK80).  2010-2017 Microchip Technology Inc. DS30009977G-page 69

PIC18F66K80 FAMILY REGISTER 4-2: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPMD(1) CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPMD: Peripheral Module Disable bit(1) 1 = The PSP module is disabled; all PSP registers are held in Reset and are not writable 0 = The PSP module is enabled bit 6 CTMUMD: PMD CTMU Disable bit 1 = The CTMU module is disabled; all CTMU registers are held in Reset and are not writable 0 = The CTMU module is enabled bit 5 ADCMD: A/D Module Disable bit 1 = The A/D module is disabled; all A/D registers are held in Reset and are not writable 0 = The A/D module is enabled bit 4 TMR4MD: TMR4MD Disable bit 1 = The Timer4 module is disabled; all Timer4 registers are held in Reset and are not writable 0 = The Timer4 module is enabled bit 3 TMR3MD: TMR3MD Disable bit 1 = The Timer3 module is disabled; all Timer3 registers are held in Reset and are not writable 0 = The Timer3 module is enabled bit 2 TMR2MD: TMR2MD Disable bit 1 = The Timer2 module is disabled; all Timer2 registers are held in Reset and are not writable 0 = The Timer2 module is enabled bit 1 TMR1MD: TMR1MD Disable bit 1 = The Timer1 module is disabled; all Timer1 registers are held in Reset and are not writable 0 = The Timer1 module is enabled bit 0 TMR0MD: Timer0 Module Disable bit 1 = The Timer0 module is disabled; all Timer0 registers are held in Reset and are not writable 0 = The Timer0 module is enabled Note 1: This bit is unimplemented on 28-pin devices (PIC18F2XK80, PIC18LF2XK80). DS30009977G-page 70  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 4-3: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP5MD: CCP5 Module Disable bit 1 = The CCP5 module is disabled; all CCP5 registers are held in Reset and are not writable 0 = The CCP5 module is enabled bit 6 CCP4MD: CCP4 Module Disable bit 1 = The CCP4 module is disabled; all CCP4 registers are held in Reset and are not writable 0 = The CCP4 module is enabled bit 5 CCP3MD: CCP3 Module Disable bit 1 = The CCP3 module is disabled; all CCP3 registers are held in Reset and are not writable 0 = The CCP3 module is enabled bit 4 CCP2MD: CCP2 Module Disable bit 1 = The CCP2 module is disabled; all CCP2 registers are held in Reset and are not writable 0 = The CCP2 module is enabled bit 3 CCP1MD: ECCP1 Module Disable bit 1 = The ECCP1 module is disabled; all ECCP1 registers are held in Reset and are not writable 0 = The ECCP1 module is enabled bit 2 UART2MD: EUSART2 Module Disable bit 1 = The USART2 module is disabled; all USART2 registers are held in Reset and are not writable 0 = The USART2 module is enabled bit 1 UART1MD: EUSART1 Module Disable bit 1 = The USART1 module is disabled; all USART1 registers are held in Reset and are not writable 0 = The USART1 module is enabled bit 0 SSPMD: MSSP Module Disable bit 1 = The MSSP module is disabled; all SSP registers are held in Reset and are not writable 0 = The MSSP module is enabled  2010-2017 Microchip Technology Inc. DS30009977G-page 71

PIC18F66K80 FAMILY 4.6 Exiting Idle and Sleep Modes 4.6.3 EXIT BY RESET An exit from Sleep mode or any of the Idle modes is Normally, the device is held in Reset by the Oscillator triggered by an interrupt, a Reset or a WDT time-out. Start-up Timer (OST) until the primary clock becomes This section discusses the triggers that cause exits ready. At that time, the OSTS bit is set and the device from power-managed modes. The clocking subsystem begins executing code. If the internal oscillator block is actions are discussed in each of the power-managed the new clock source, the HFIOFS/MFIOFS bits are set modes (see Section4.2 “Run Modes”, Section4.3 instead. “Sleep Mode” and Section4.4 “Idle Modes”). The exit delay time from Reset to the start of code execution depends on both the clock sources before 4.6.1 EXIT BY INTERRUPT and after the wake-up, and the type of oscillator, if the Any of the available interrupt sources can cause the new clock source is the primary clock. Exit delays are device to exit from an Idle mode or Sleep mode to a summarized in Table4-4. Run mode. To enable this functionality, an interrupt Code execution can begin before the primary clock source must be enabled by setting its enable bit in one becomes ready. If either the Two-Speed Start-up (see of the INTCONx or PIEx registers. The exit sequence is Section28.4 “Two-Speed Start-up”) or Fail-Safe initiated when the corresponding interrupt flag bit is set. Clock Monitor (see Section28.5 “Fail-Safe Clock On all exits from Idle or Sleep modes by interrupt, code Monitor”) is enabled, the device may begin execution execution branches to the interrupt vector if the as soon as the Reset source has cleared. Execution is GIE/GIEH bit (INTCON<7>) is set. Otherwise, code clocked by the INTOSC multiplexer driven by the inter- execution continues or resumes without branching nal oscillator block. Execution is clocked by the internal (see Section10.0 “Interrupts”). oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the 4.6.2 EXIT BY WDT TIME-OUT primary clock becomes ready; the primary clock is then shut down. A WDT time-out will cause different actions depending on which power-managed mode the device is in when 4.6.4 EXIT WITHOUT AN OSCILLATOR the time-out occurs. START-UP DELAY If the device is not executing code (all Idle modes and Certain exits from power-managed modes do not Sleep mode), the time-out will result in an exit from the invoke the OST at all. The two cases are: power-managed mode (see Section4.2 “Run Modes” and Section4.3 “Sleep Mode”). If the device • When in PRI_IDLE mode, where the primary is executing code (all Run modes), the time-out will clock source is not stopped result in a WDT Reset (see Section28.2 “Watchdog • When the primary clock source is not any of the Timer (WDT)”). LP, XT, HS or HSPLL modes Executing a SLEEP or CLRWDT instruction clears the In these instances, the primary clock source either WDT timer and postscaler, loses the currently selected does not require an oscillator start-up delay, since it is clock source (if the Fail-Safe Clock Monitor is enabled) already running (PRI_IDLE), or normally, does not and modifies the IRCFx bits in the OSCCON register (if require an oscillator start-up delay (RC, EC and INTIO the internal oscillator block is the device clock source). Oscillator modes). However, a fixed delay of interval, TCSD, following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. DS30009977G-page 72  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 4.7 Ultra Low-Power Wake-up A series resistor, between RA0 and the external capacitor, provides overcurrent protection for the The Ultra Low-Power Wake-up (ULPWU) on pin, RA0, RA0/CVREF/AN0/ULPWU pin and enables software allows a slow falling voltage to generate an interrupt calibration of the time-out (see Figure4-9). without excess current consumption. To use this feature: FIGURE 4-9: ULTRA LOW-POWER WAKE-UP INITIALIZATION 1. Charge the capacitor on RA0 by configuring the RA0 pin to an output and setting it to ‘1’. 2. Stop charging the capacitor by configuring RA0 RA0/CVREF/AN0/ULPWU as an input. 3. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the WDTCON register. 4. Configure Sleep mode. 5. Enter Sleep mode. When the voltage on RA0 drops below VIL, the device wakes up and executes the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode. The time-out is dependent on the discharge time of the RC circuit on RA0. A timer can be used to measure the charge time and When the ULPWU module wakes the device from discharge time of the capacitor. The charge time can Sleep mode, the ULPLVL bit (WDTCON<5>) is set. then be adjusted to provide the desired delay in Sleep. Software can check this bit upon wake-up to determine This technique compensates for the affects of the wake-up source. temperature, voltage and component accuracy. The See Example4-1 for initializing the ULPWU module. peripheral can also be configured as a simple programmable Low-Voltage Detect (LVD) or temperature EXAMPLE 4-1: ULTRA LOW-POWER sensor. WAKE-UP INITIALIZATION Note: For more information, see AN879, “Using the Microchip Ultra Low-Power Wake-up //*************************** Module” (DS00879). //Charge the capacitor on RA0 //*************************** TRISAbits.TRISA0 = 0; PORTAbits.RA0 = 1; for(i = 0; i < 10000; i++) Nop(); //***************************** //Stop Charging the capacitor //on RA0 //***************************** TRISAbits.TRISA0 = 1; //***************************** //Enable the Ultra Low Power //Wakeup module and allow //capacitor discharge //***************************** WDTCONbits.ULPEN = 1; WDTCONbits.ULPSINK = 1; //For Sleep OSCCONbits.IDLEN = 0; //Enter Sleep Mode // Sleep(); //for sleep, execution will //resume here  2010-2017 Microchip Technology Inc. DS30009977G-page 73

PIC18F66K80 FAMILY TABLE 4-4: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Power-Managed Clock Ready Clock Source(5) Exit Delay Mode Status Bits LP, XT, HS HSPLL OSTS EC, RC PRI_IDLE mode TCSD(1) HF-INTOSC(2) HFIOFS MF-INTOSC(2) MFIOFS LF-INTOSC None SEC_IDLE mode SOSC TCSD(1) SOSCRUN HF-INTOSC(2) HFIOFS RC_IDLE mode MF-INTOSC(2) TCSD(1) MFIOFS LF-INTOSC None LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS EC, RC TCSD(1) Sleep mode HF-INTOSC(2) HFIOFS MF-INTOSC(2) TIOBST(4) MFIOFS LF-INTOSC None Note 1: TCSD (Parameter 38, Table31-11) is a required delay when waking from Sleep and all Idle modes, and runs concurrently with any other required delays (see Section4.4 “Idle Modes”). 2: Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz. 3: TOST is the Oscillator Start-up Timer (Parameter 32, Table31-11). TRC is the PLL Lock-out Timer (Parameter F12, Table31-7); it is also designated as TPLL. 4: Execution continues during TIOBST (Parameter 39, Table31-11), the INTOSC stabilization period. 5: The clock source is dependent upon the settings of the SCSx (OSCCON<1:0>), IRCFx (OSCCON<6:4>) and FOSCx (CONFIG1H<3:0>) bits. DS30009977G-page 74  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 5.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure5-1. The PIC18F66K80 family devices differentiate between various kinds of Reset: 5.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during Normal Operation register (Register5-1). The lower five bits of the regis- c) MCLR Reset during Power-Managed modes ter indicate that a specific Reset event has occurred. In d) Watchdog Timer (WDT) Reset (during most cases, these bits can only be cleared by the event execution) and must be set by the application after the event. The e) Configuration Mismatch (CM) Reset state of these flag bits, taken together, can be read to f) Programmable Brown-out Reset (BOR) indicate the type of Reset that just occurred. This is described in more detail in Section5.7 “Reset State g) RESET Instruction of Registers”. h) Stack Full Reset The RCON register also has control bits for setting i) Stack Underflow Reset interrupt priority (IPEN) and software control of the This section discusses Resets generated by MCLR, BOR (SBOREN). Interrupt priority is discussed in POR and BOR, and covers the operation of the various Section10.0 “Interrupts”. BOR is covered in start-up timers. Stack Reset events are covered in Section5.4 “Brown-out Reset (BOR)”. Section6.1.3.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section28.2 “Watchdog Timer (WDT)”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset BOREN<1:0> S OST/PWRT OST 1024 Cycles Chip_Reset 10-Bit Ripple Counter R Q OSC1 32 s PWRT 65.5 ms INTOSC(1) 11-Bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table5-2 for time-out situations.  2010-2017 Microchip Technology Inc. DS30009977G-page 75

PIC18F66K80 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) R/W-1 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enables priority levels on interrupts 0 = Disables priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and reads as ‘0’. bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred. 0 = A Configuration Mismatch Reset has occurred (must be set in software once the Reset occurs) bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out has occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset has occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset has occurred (must be set in software after a Brown-out Reset occurs) Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section5.7 “Reset State of Registers” for additional information. Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS30009977G-page 76  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 5.2 Master Clear Reset (MCLR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. The MCLR pin is not driven low by any internal Resets, D R including the WDT. R1 In PIC18F66K80 family devices, the MCLR input can MCLR be disabled with the MCLRE Configuration bit. When C PIC18FXX80 MCLR is disabled, the pin becomes a digital input. See Section11.6 “PORTE, TRISE and LATE Registers” for more information. Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. 5.3 Power-on Reset (POR) The diode, D, helps discharge the capacitor A Power-on Reset pulse is generated on-chip quickly when VDD powers down. whenever VDD rises above a certain threshold. This 2: R < 40k is recommended to make sure that the voltage drop across R does not violate allows the device to start in the initialized state when the device’s electrical specification. VDD is adequate for operation. 3: R1  1 k will limit any current flowing into To take advantage of the POR circuitry, tie the MCLR MCLR from external capacitor, C, in the event pin through a resistor (1k to 10k) to VDD. This will of MCLR/VPP pin breakdown, due to Electro- eliminate external RC components usually needed to static Discharge (ESD) or Electrical create a Power-on Reset delay. A minimum rise rate for Overstress (EOS). VDD is specified (Parameter D004). For a slow rise time, see Figure5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset.  2010-2017 Microchip Technology Inc. DS30009977G-page 77

PIC18F66K80 FAMILY 5.4 Brown-out Reset (BOR) Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its The PIC18F66K80 family has four BOR Power modes: environment without having to reprogram the device to • High-Power BOR change BOR configuration. It also allows the user to • Medium Power BOR tailor device power consumption in software by elimi- nating the incremental current that the BOR consumes. • Low-Power BOR While the BOR current is typically very small, it may • Zero-Power BOR have some impact in low-power applications. Each power mode is selected by the BORPWR<1:0> Note: Even when BOR is under software con- setting (CONFIG2L<6:5>). For low, medium and trol, the Brown-out Reset voltage level is high-power BOR, the module monitors the VDD depend- still set by the BORV<1:0> Configuration ing on the BORV<1:0> setting (CONFIG1L<3:2>). The bits; it cannot be changed in software. typical current draw (IBOR) for zero, low and medium power BOR is 200 nA, 750 nA and 3 A, respectively. A 5.4.2 DETECTING BOR BOR event re-arms the Power-on Reset. It also causes a Reset, depending on which of the trip levels has been When Brown-out Reset is enabled, the BOR bit always set: 1.8V, 2V, 2.7V or 3V. resets to ‘0’ on any Brown-out Reset or Power-on Reset event. This makes it difficult to determine if a BOR is enabled by BOREN<1:0> (CONFIG2L<2:1>) Brown-out Reset event has occurred just by reading and the SBOREN bit (RCON<6>). The four BOR the state of BOR alone. A more reliable method is to configurations are summarized in Table5-1. simultaneously check the state of both POR and BOR. In Zero-Power BOR (ZPBORMV), the module monitors This assumes that the POR bit is reset to ‘1’ in software the VDD voltage and re-arms the POR at about 2V. immediately after any Power-on Reset event. IF BOR ZPBORMV does not cause a Reset, but re-arms the is ‘0’ while POR is ‘1’, it can be reliably assumed that a POR. Brown-out Reset event has occurred. The BOR accuracy varies with its power level. The lower 5.4.3 DISABLING BOR IN SLEEP MODE the power setting, the less accurate the BOR trip levels are. Therefore, the high-power BOR has the highest When BOREN<1:0> = 10, the BOR remains under accuracy and the low-power BOR has the lowest accu- hardware control and operates as previously racy. The trip levels (BVDD, Parameter D005), current described. Whenever the device enters Sleep mode, consumption (Section31.2 “DC Characteristics: however, the BOR is automatically disabled. When the Power-Down and Supply Current PIC18F66K80 device returns to any other operating mode, BOR is Family (Industrial/Extended)”) and time required automatically re-enabled. below BVDD (TBOR, Parameter 35) can all be found in This mode allows for applications to recover from Section31.0 “Electrical Characteristics”. brown-out situations, while actively executing code, 5.4.1 SOFTWARE ENABLED BOR when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode When BOREN<1:0> = 01, the BOR can be enabled or by eliminating the small incremental BOR current. disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’. TABLE 5-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR is disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR is enabled in software; operation is controlled by SBOREN. 1 0 Unavailable BOR is enabled in hardware, in Run and Idle modes; disabled during Sleep mode. 1 1 Unavailable BOR is enabled in hardware; must be disabled by reprogramming the Configuration bits. DS30009977G-page 78  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 5.5 Configuration Mismatch (CM) 5.6 Device Reset Timers The Configuration Mismatch (CM) Reset is designed to PIC18F66K80 family devices incorporate three sepa- detect, and attempt to recover from, random memory rate on-chip timers that help regulate the Power-on corrupting events. These include Electrostatic Reset process. Their main function is to ensure that the Discharge (ESD) events, which can cause widespread, device clock is stable before code is executed. These single bit changes throughout the device and result in timers are: catastrophic failure. • Power-up Timer (PWRT) In PIC18FXXKXX Flash devices, the device Configura- • Oscillator Start-up Timer (OST) tion registers (located in the configuration memory • PLL Lock Time-out space) are continuously monitored during operation by comparing their values to complimentary Shadow reg- 5.6.1 POWER-UP TIMER (PWRT) isters. If a mismatch is detected between the two sets The Power-up Timer (PWRT) of the PIC18F66K80 of registers, a CM Reset automatically occurs. These family devices is an 11-bit counter which uses the events are captured by the CM bit (RCON<5>) being INTOSC source as the clock input. This yields an set to ‘0’. approximate time interval of 2048x32s=65.6ms. This bit does not change for any other Reset event. A While the PWRT is counting, the device is held in CM Reset behaves similarly to a Master Clear Reset, Reset. RESET instruction, WDT time-out or Stack Event The power-up time delay depends on the INTOSC Resets. As with all hard and power Reset events, the clock and will vary from chip-to-chip due to temperature device Configuration Words are reloaded from the and process variation. See DC Parameter 33 for Flash Configuration Words in program memory as the details. device restarts. The PWRT is enabled by clearing the PWRTEN Configuration bit.  2010-2017 Microchip Technology Inc. DS30009977G-page 79

PIC18F66K80 FAMILY 5.6.2 OSCILLATOR START-UP TIMER 5.6.4 TIME-OUT SEQUENCE (OST) On power-up, the time-out sequence is as follows: The Oscillator Start-up Timer (OST) provides a 1. After the POR pulse has cleared, PWRT 1024oscillator cycle (from OSC1 input) delay after the time-out is invoked (if enabled). PWRT delay is over (Parameter 33). This ensures that 2. Then, the OST is activated. the crystal oscillator or resonator has started and stabilized. The total time-out will vary based on oscillator configu- ration and the status of the PWRT. Figure5-3, The OST time-out is invoked only for XT, LP, HS and Figure5-4, Figure5-5, Figure5-6 and Figure5-7 all HSPLL modes and only on Power-on Reset or on exit depict time-out sequences on power-up, with the from most power-managed modes. Power-up Timer enabled and the device operating in HS Oscillator mode. Figures5-3 through5-6 also apply 5.6.3 PLL LOCK TIME-OUT to devices operating in XT or LP modes. For devices in With the PLL enabled in its PLL mode, the time-out RC mode and with the PWRT disabled, on the other sequence following a Power-on Reset is slightly differ- hand, there will be no time-out at all. ent from other oscillator modes. A separate timer is Since the time-outs occur from the POR pulse, if MCLR used to provide a fixed time-out that is sufficient for the is kept low long enough, all time-outs will expire. Bring- PLL to lock to the main oscillator frequency. This PLL ing MCLR high will begin execution immediately lock time-out (TPLL) is typically 2 ms and follows the (Figure5-5). This is useful for testing purposes or to oscillator start-up time-out. synchronize more than one PIC18FXXXX device operating in parallel. TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS Power-up and Brown-out Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30009977G-page 80  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2010-2017 Microchip Technology Inc. DS30009977G-page 81

PIC18F66K80 FAMILY FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer. DS30009977G-page 82  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 5.7 Reset State of Registers different Reset situations, as indicated in Table5-3. These bits are used in software to determine the nature Most registers are unaffected by a Reset. Their status of the Reset. is unknown on a Power-on Reset and unchanged by all Table5-4 describes the Reset states for all of the other Resets. The other registers are forced to a “Reset Special Function Registers. These are categorized by state” depending on the type of Reset that occurred. Power-on and Brown-out Resets, Master Clear and Most registers are not affected by a WDT wake-up, WDT Resets and WDT wake-ups. since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, CM, POR and BOR, are set or cleared differently in TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter(1) SBOREN CM RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) u 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 1 u 0 u u MCLR Reset during 0000h u(2) u u 1 u u u u u Power-Managed Run modes MCLR Reset during 0000h u(2) u u 1 0 u u u u Power-Managed Idle modes and Sleep mode WDT Time-out during Full Power 0000h u(2) u u 0 u u u u u or Power-Managed Run modes MCLR Reset during Full-Power 0000h u(2) u u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u u 1 u Stack Underflow Reset 0000h u(2) u u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u(2) u u u u u u u 1 actual Reset, STVREN = 0) WDT Time-out during PC + 2 u(2) u u 0 0 u u u u Power-Managed Idle or Sleep modes Interrupt Exit from PC + 2 u(2) u u u 0 u u u u Power-Managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN<1:0>, Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 83

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets TOSU PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu PCL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 000x 0000 000u uuuu uuuu(1) INTCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 -1-1 uuuu -u-u(1) INTCON3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1100 0000 11x0 0x00 uuuu uuuu(1) INDF0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A POSTINC0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A POSTDEC0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A PREINC0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A PLUSW0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A FSR0H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- xxxx ---- uuuu ---- uuuu FSR0L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A POSTINC1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A POSTDEC1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A PREINC1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A PLUSW1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A FSR1H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. DS30009977G-page 84  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets POSTINC2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A POSTDEC2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A PREINC2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A PLUSW2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A FSR2H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- xxxx ---- uuuu ---- uuuu FSR2L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 uuuu uuuu uuuu uuuu TMR0L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0110 q000 0100 00q0 uuuu uuqu OSCCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -0-1 0-x0 -0-0 0-01 -u-u u-uu WDTCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0-x0 -xx0 0-x0 -xx0 u-u0 -uu0 RCON(4) PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0111 11q0 0111 qquu uuuu qquu TMR1H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 u0uu uuuu uuuu uuuu TMR2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu T2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu SSPBUF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu SSPSTAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu SSPCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu SSPCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu ADCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 xxxx 0000 0qqq uuuu uuuu ADCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0-00 0000 0-00 0000 u-uu uuuu ECCP1AS PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 xxxx xxxx CCPR1H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu TXSTA2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0010 0000 0010 uuuu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 85

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets BAUDCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 01x0 0-00 01x0 0-00 uuuu u-uu IPR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 -111 1111 -111 uuuu -uuu PIR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 -000 0000 -000 uuuu -uuu PIE4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 -000 0000 -000 uuuu -uuu CVRCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CMSTAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xx-- ---- xx-- ---- uu-- ---- TMR3H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu T3GCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0x00 0000 0x00 uuuu u-uu SPBRG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu TXREG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu TXSTA1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0010 0000 0010 uuuu uuuu RCSTA1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 000x 0000 000x uuuu uuuu T1GCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0x00 0000 0x00 uuuu u-uu PR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu HLVDCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu BAUDCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 01x0 0-00 01x0 0-00 uuuu u-uu RCSTA2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 000x 0000 000x uuuu uuuu IPR3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --11 111- --11 111- --uu uuu- PIR3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 000- --x0 xxx- --uu uuu- PIE3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 000- 0000 0000 uuuu uuuu IPR2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1--- 1111 1--- 111x u--- uuuu PIR2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0--- 0000 0--- 000x u--- uuuu(1) PIE2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0--- 0000 0--- 0000 u--- uuuu IPR1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -111 1111 -111 1111 -uuu uuuu PIR1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu(1) PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu PIE1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu PSTR1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 00-0 0001 xx-x xxxx — OSCTUNE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu REFOCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0-00 0000 0-00 0000 u-uu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. DS30009977G-page 86  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets CCPTMRS PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000 ---x xxxx ---u uuuu TRISG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---1 1111 ---1 1111 ---u uuuu TRISF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu TRISE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 -111 1111 -111 uuuu -uuu TRISD PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu TRISA(5) PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 111- 1111(5) 111- 1111(5) uuu- uuuu(5) ODCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu SLRCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -111 1111 -111 1111 LATG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---x xxxx ---x xxxx ---u uuuu LATF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx -xxx uuuu -uuu LATE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx -xxx xxxx xxxx uuuu uuuu LATD PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu LATC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu LATB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu LATA(5) PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- xxxx(5) xxx- xxxx(5) uuu- uuuu(5) T4CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -000 0000 -000 0000 -uuu uuuu TMR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu PORTG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---x xxxx ---x xxxx ---u uuuu PORTF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu PORTE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu PORTD PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu PORTC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu PORTB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu PORTA(5) PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- xxxx(5) xxx- xxxx(5) uuu- uuuu(5) EECON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xx-0 x000 uu-0 u000 uu-u uuuu EECON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu SPBRGH1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu SPBRGH2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu SPBRG2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu IPR5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu PIR5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 87

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets PIE5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu EEADRH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- --00 ---- --00 ---- --00 EEADR PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu EEDATA PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu ECANCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 0000 0001 0000 uuuu uuuu COMSTAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CIOCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---0 0000 ---0 uuuu ---u CANCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu RXB0D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CM1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 1111 0001 1111 uuuu uuuu CM2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 1111 0001 1111 uuuu uuuu ANCON0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu ANCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -111 1111 -111 1111 -uuu uuuu WPUB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx 1111 1111 uuuu uuuu IOCB PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---- 0000 ---- uuuu ---- PMD0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. DS30009977G-page 88  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets PMD1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu PMD2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- 0000 ---- 0000 ---- uuuu PADCFG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---0 0000 ---0 uuuu ---u CTMUCONH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0-00 0000 0-00 0000 u-uu uuuu CTMUCONL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CTMUICON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu CCPR2L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu CCP2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu CCPR3H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu CCPR3L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu CCP3CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu CCPR4H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu CCPR4L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu CCP4CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu CCPR5H PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu CCPR5L PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu CCP5CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 --00 0000 --00 0000 --uu uuuu PSPCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---- 0000 ---- uuuu ---- MDCON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0010 0--0 0010 0--0 uuuu u--u MDSRC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0--- xxxx 0--- xxxx u--- uuuu MDCARH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0xx- xxxx 0xx- xxxx uuu- uuuu MDCARL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0xx- xxxx 0xx- xxxx uuu- uuuu CANCON_RO0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu RXB1D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu xxxx xxxx Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 89

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets RXB1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu RXB1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CANCON_RO1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu TXB0D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB0DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu TXB0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu TXB0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu TXB0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx xxx- x-xx uuu- u-uu TXB0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx xxxx xxxx uuuu uuuu TXB0CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0-00 0000 0-00 uuuu u-uu CANCON_RO2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu TXB1D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. DS30009977G-page 90  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets TXB1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0-00 0000 0-00 uuuu u-uu CANCON_RO3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu TXB2D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu TXB2SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu TXB2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0-00 0000 0-00 uuuu u-uu RXM1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXM1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXM1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- 0-xx uuu- u-uu uuu- u-uu RXM1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- 0-xx uuu- u-uu uuu- u-uu RXM0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 91

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets RXF3EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF3SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF2SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu CANCON_RO4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu B5D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu uuuu uuuu B5EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu B5SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B5CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CANCON_RO5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu B4D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. DS30009977G-page 92  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets B4D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu B4EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu B4SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CANCON_RO6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu B3D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu B3EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu B3SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B3CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CANCON_RO7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu B2D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 93

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets B2D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu B2EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu B2SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CANCON_RO8 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu B1D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu B1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu B1SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu CANCON_RO9 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu B0D7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0D6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0D1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu B0EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. DS30009977G-page 94  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets B0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu B0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu TXBIE PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 00-- ---u uu-- ---u uu-- BIE0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu BSEL0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 00-- 0000 00-- uuuu uu-- MSEL3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu MSEL2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu MSEL1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0101 0000 0101 uuuu uuuu MSEL0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0101 0000 0101 0000 uuuu uuuu RXFBCON7 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RXFBCON6 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RXFBCON5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RXFBCON4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RXFBCON3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RXFBCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 0001 0001 0001 uuuu uuuu RXFBCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0001 0001 0001 0001 uuuu uuuu RXFBCON0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu SDFLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000 ---0 0000 ---u uuuu RXF15EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF15EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF15SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF15SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF14EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF14EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF14SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF14SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF13EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF13EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF13SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF13SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF12EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF12EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF12SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 95

PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on MCLR Resets, Wake-up via Reset, WDT Reset, Register Applicable Devices WDT Brown-out RESET Instruction, or Interrupt Reset Stack Resets RXF12SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF11SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF11SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF10EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF10EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF10SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF10SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF9EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF9EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF9SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF9SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF8EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF8EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF8SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF8SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF7EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF7EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF7SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF7SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF6EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF6EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF6SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF6SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXFCON0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RXFCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu BRGCON3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 00-- -000 00-- -000 uu-- -uuu BRGCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu BRGCON1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu TXERRCNT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu RXERRCNT PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific conditions. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. DS30009977G-page 96  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 6.0 MEMORY ORGANIZATION The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is PIC18F66K80 family devices have these types of addressed and accessed through a set of control memory: registers. • Program Memory Additional detailed information on the operation of the • Data RAM Flash program memory is provided in Section7.0 • Data EEPROM “Flash Program Memory”. The data EEPROM is As Harvard architecture devices, the data and program discussed separately in Section8.0 “Data EEPROM memories use separate busses. This enables Memory”. concurrent access of the two memory spaces. FIGURE 6-1: MEMORY MAPS FOR PIC18F66K80 FAMILY DEVICES PC<20:0> 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1    Stack Level 31 PIC18FX5K80 PIC18FX6K80 000000h On-Chip On-Chip Memory Memory 007FFFh 00FFFFh e c a p S y or m e M er s U Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 1FFFFFh Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.  2010-2017 Microchip Technology Inc. DS30009977G-page 97

PIC18F66K80 FAMILY 6.1 Program Memory Organization FIGURE 6-2: HARD VECTOR FOR PIC18F66K80 FAMILY PIC18 microcontrollers implement a 21-bit Program DEVICES Counter (PC) that is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented Reset Vector 0000h memory and the 2-Mbyte address will return all ‘0’s (a High-Priority Interrupt Vector 0008h NOP instruction). The entire PIC18F66K80 family offers a range of Low-Priority Interrupt Vector 0018h on-chip Flash program memory sizes, from 32Kbytes (16,384 single-word instructions) to 64Kbytes (32,768single-word instructions). • PIC18F25K80, PIC18F45K80 and PIC18F65K80 – On-Chip 32Kbytes of Flash memory, storing up to Program Memory 16,384single-word instructions • PIC18F26K80, PIC18F46K80 and PIC18F66K80 – 64Kbytes of Flash memory, storing up to 32,768single-word instructions The program memory maps for individual family members are shown in Figure6-1. 6.1.1 HARD MEMORY VECTORS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the Read ‘0’ Program Counter returns on all device Resets. It is located at 0000h. PIC18 devices also have two interrupt vector addresses for handling high-priority and low-priority interrupts. The high-priority interrupt vector is located at 1FFFFFh 0008h and the low-priority interrupt vector is at 0018h. Legend: (Top of Memory) represents upper boundary The locations of these vectors are shown, in relation to of on-chip program memory space (see the program memory map, in Figure6-2. Figure6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS30009977G-page 98  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 6.1.2 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and contained in three separate 8-bit registers. the stack is readable and writable through the The low byte, known as the PCL register, is both Top-of-Stack (TOS) Special Function Registers. Data readable and writable. The high byte, or PCH register, can also be pushed to, or popped from the stack, using contains the PC<15:8> bits and is not directly readable these registers. or writable. Updates to the PCH register are performed A CALL type instruction causes a push onto the stack. through the PCLATH register. The upper byte is called The Stack Pointer is first incremented and the location PCU. This register contains the PC<20:16> bits; it is also pointed to by the Stack Pointer is written with the not directly readable or writable. Updates to the PCU contents of the PC (already pointing to the instruction register are performed through the PCLATU register. following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred to a pop from the stack. The contents of the location the Program Counter by any operation that writes PCL. pointed to by the STKPTR are transferred to the PC Similarly, the upper two bytes of the Program Counter and then the Stack Pointer is decremented. are transferred to PCLATH and PCLATU by an operation The Stack Pointer is initialized to ‘00000’ after all that reads PCL. This is useful for computed offsets to the Resets. There is no RAM associated with the location PC (see Section6.1.5.1 “Computed GOTO”). corresponding to a Stack Pointer value of ‘00000’; this The PC addresses bytes in the program memory. To is only a Reset value. Status bits indicate if the stack is prevent the PC from becoming misaligned with word full, has overflowed or has underflowed. instructions, the Least Significant bit (LSb) of PCL is fixed to a value of ‘0’. The PC increments by two to 6.1.3.1 Top-of-Stack Access address sequential instructions in the program memory. Only the top of the return address stack is readable and The CALL, RCALL, GOTO and program branch writable. A set of three registers, TOSU:TOSH:TOSL, instructions write to the Program Counter directly. For holds the contents of the stack location pointed to by these instructions, the contents of PCLATH and the STKPTR register (Figure6-3). This allows users to PCLATU are not transferred to the Program Counter. implement a software stack, if necessary. After a CALL, RCALL or interrupt (or ADDULNK and SUBULNK instruc- 6.1.3 RETURN ADDRESS STACK tions, if the extended instruction set is enabled), the The return address stack enables execution of any software can read the pushed value by reading the combination of up to 31 program calls and interrupts. TOSU:TOSH:TOSL registers. These values can be The PC is pushed onto the stack when a CALL or placed on a user-defined software stack. At return time, RCALL instruction is executed or an interrupt is the software can return these values to Acknowledged. The PC value is pulled off the stack on TOSU:TOSH:TOSL and do a return. a RETURN, RETLW or a RETFIE instruction. The value While accessing the stack, users must disable the is also pulled off the stack on ADDULNK and SUBULNK Global Interrupt Enable bits to prevent inadvertent instructions if the extended instruction set is enabled. stack corruption. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack<20:0> Top-of-Stack Registers Stack Pointer 11111 TOSU TOSH TOSL 11110 STKPTR<4:0> 00h 1Ah 34h 11101 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000  2010-2017 Microchip Technology Inc. DS30009977G-page 99

PIC18F66K80 FAMILY 6.1.3.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register6-1) contains the Stack to the PC and set the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and the Pointer remains at zero. The STKUNF bit will remain STKUNF (Stack Underflow) status bits. The value of the set until cleared by software or until a POR occurs. Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and Note: Returning a value of zero to the PC on an decrements after values are popped off of the stack. On underflow has the effect of vectoring the Reset, the Stack Pointer value will be zero. program to the Reset vector, where the stack conditions can be verified and The user may read and write the Stack Pointer value. appropriate actions can be taken. This is This feature can be used by a Real-Time Operating not the same as a Reset, as the contents System (RTOS) for return stack maintenance. of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is 6.1.3.3 PUSH and POP Instructions set. The STKFUL bit is cleared by software or by a POR. Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off What happens when the stack becomes full depends of the stack, without disturbing normal program execu- on the state of the STVREN (Stack Overflow Reset tion, is a desirable feature. The PIC18 instruction set Enable) Configuration bit. (For a description of the includes two instructions, PUSH and POP, that permit device Configuration bits, see Section28.1 “Configu- the TOS to be manipulated under software control. ration Bits”.) If STVREN is set (default), the 31st push TOSU, TOSH and TOSL can be modified to place data will push the (PC + 2) value onto the stack, set the or a return address on the stack. STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push The POP instruction discards the current TOS by and the STKPTR will remain at 31. decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. REGISTER 6-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack has become full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow has occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. DS30009977G-page 100  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 6.1.3.4 Stack Full and Underflow Resets 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit There may be programming situations that require the (CONFIG4L<0>). When STVREN is set, a full or under- creation of data structures, or look-up tables, in flow condition will set the appropriate STKFUL or program memory. For PIC18 devices, look-up tables STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit, but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 6.1.5.1 Computed GOTO 6.1.4 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the Program Counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example6-2. WREG and BSR registers to provide a “fast return” option for interrupts. This stack is only one level deep A look-up table can be formed with an ADDWF PCL and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The current value of the corresponding register when the W register is loaded with an offset into the table before processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the will push values into the Stack registers. The values in called routine is the ADDWF PCL instruction. The next the registers are then loaded back into the working instruction executed will be one of the RETLW nn registers if the RETFIE,FAST instruction is used to instructions that returns the value, ‘nn’, to the calling return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of Stack registers cannot be used reliably to return from bytes that the Program Counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of two (LSb = 0). while servicing a low-priority interrupt, the Stack In this method, only one data byte may be stored in register values stored by the low-priority interrupt will each instruction location and room on the return be overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 6-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label,FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN,FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example6-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 6.1.5.2 Table Reads EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word while programming. The Table Pointer  (TBLPTR) specifies the byte address and the Table  Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program SUB1  memory one byte at a time.  RETURN FAST ;RESTORE VALUES SAVED The table read operation is discussed further in ;IN FAST REGISTER STACK Section7.1 “Table Reads and Table Writes”.  2010-2017 Microchip Technology Inc. DS30009977G-page 101

PIC18F66K80 FAMILY 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles, Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are pipe- The microcontroller clock input, whether from an lined in such a manner that a fetch takes one instruction internal or external source, is internally divided by four cycle, while the decode and execute take another to generate four non-overlapping quadrature clocks instruction cycle. However, due to the pipelining, each (Q1, Q2, Q3 and Q4). Internally, the Program Counter instruction effectively executes in one cycle. If an is incremented on every Q1, with the instruction instruction (such as GOTO) causes the Program fetched from the program memory and latched into the Counter to change, two cycles are required to complete Instruction Register (IR) during Q4. the instruction. (See Example6-3.) The instruction is decoded and executed during the A fetch cycle begins with the Program Counter (PC) following Q1 through Q4. The clocks and instruction incrementing in Q1. execution flow are shown in Figure6-4. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle, Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30009977G-page 102  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as two or four bytes in program word address. The word address is written to PC<20:1> memory. The Least Significant Byte (LSB) of an which accesses the desired byte address in program instruction word is always stored in a program memory memory. Instruction #2 in Figure6-5 shows how the location with an even address (LSB = 0). To maintain instruction, GOTO 0006h, is encoded in the program alignment with instruction boundaries, the PC incre- memory. Program branch instructions, which encode a ments in steps of two and the LSB will always read ‘0’ relative address offset, operate in the same manner. The (see Section6.1.2 “Program Counter”). offset value stored in a branch instruction represents the Figure6-5 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. For more details on the instruction set, see Section29.0 “Instruction Set Summary”. FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is skipped for some reason and the second word is The standard PIC18 instruction set has four, two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all cases, necessary for cases when the two-word instruction is the second word of the instructions always has ‘1111’ as preceded by a conditional instruction that changes the its four Most Significant bits (MSbs). The other 12 bits PC. Example6-4 shows how this works. are literal data, usually a data memory address. The use of ‘1111’ in the 4MSbs of an instruction Note: For information on two-word instructions specifies a special form of NOP. If the instruction is in the extended instruction set, see executed in proper sequence, immediately after the Section6.5 “Program Memory and the first word, the data in the second word is accessed and Extended Instruction Set”. EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code  2010-2017 Microchip Technology Inc. DS30009977G-page 103

PIC18F66K80 FAMILY 6.3 Data Memory Organization 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.6 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 12-bit address, allowing up to 4,096bytes of data eight-bit, low-order address and a four-bit Bank Pointer. memory. The memory space is divided into 16 banks Most instructions in the PIC18 instruction set make use that contain 256bytes each. of the Bank Pointer, known as the Bank Select Register Figure6-6 and Figure6-7 show the data memory (BSR). This SFR holds the four Most Significant bits of organization for the devices. a location’s address. The instruction itself includes the eight Least Significant bits. Only the four lower bits of The data memory contains Special Function Registers the BSR are implemented (BSR<3:0>). The upper four (SFRs) and General Purpose Registers (GPRs). The bits are unused and always read as ‘0’, and cannot be SFRs are used for control and status of the controller written to. The BSR can be loaded directly by using the and peripheral functions, while GPRs are used for data MOVLB instruction. storage and scratchpad operations in the user’s application. Any read of an unimplemented location will The value of the BSR indicates the bank in data read as ‘0’s. memory. The eight bits in the instruction show the loca- tion in the bank and can be thought of as an offset from The instruction set and architecture allow operations the bank’s lower boundary. The relationship between across all banks. The entire data memory may be the BSR’s value and the bank division in data memory accessed by Direct, Indirect or Indexed Addressing is shown in Figure6-7. modes. Addressing modes are discussed later in this section. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that To ensure that commonly used registers (select SFRs the proper bank is selected before performing a data and select GPRs) can be accessed in a single cycle, read or write. For example, writing what should be PIC18 devices implement an Access Bank. This is a program data to an eight-bit address of F9h while the 256-byte memory space that provides fast access to BSR is 0Fh, will end up resetting the Program Counter. select SFRs and the lower portion of GPR Bank 0 with- out using the Bank Select Register. For details on the While any bank can be selected, only those banks that Access RAM, see Section6.3.2 “Access Bank”. are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure6-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. When this instruction executes, it ignores the BSR completely. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS30009977G-page 104  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18FX5K80 AND PIC18FX6K80 DEVICES BSR<3:0> Data Memory Map 00h 000h Access RAM = 0000 05Fh When a = 0: Bank 0 060h GPR The BSR is ignored and the FFh 0FFh Access Bank is used. 00h 100h = 0001 Bank 1 GPR The first 96 bytes are general purpose RAM (from Bank 0). FFh 1FFh 00h 200h The second 160 bytes are = 0010 Special Function Registers Bank 2 GPR (from Bank 15). FFh 2FFh 00h 300h = 0011 Bank 3 GPR When a = 1: FFh 3FFh The BSR specifies the bank 00h 400h used by the instruction. = 0100 Bank 4 GPR FFh 4FFh 00h 500h = 0101 Bank 5 GPR FFh 5FFh 00h 600h = 0110 Bank 6 GPR FFh 6FFh = 0111 00h 700h Access Bank Bank 7 GPR 00h FFh 7FFh Access RAM Low 00h 800h 5Fh = 1000 Access RAM High 60h Bank 8 GPR (SFRs) FFh 8FFh FFh = 1001 00h 900h Bank 9 GPR FFh 9FFh = 1010 00h A00h Bank 10 GPR FFh AFFh = 1011 00h B00h Bank 11 GPR FFh BFFh = 1100 00h C00h Bank 12 GPR FFh CFFh 00h D00h = 1101 Bank 13 GPR FFh DFFh 00h E00h = 1110 Bank 14 GPR(1) = 1111 FFh EFFh Bank 15 00h GPR(1) F00h F5Fh F60h SFR FFh FFFh Note 1: Addresses, E41h through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address, or load the proper BSR value, to access these registers.  2010-2017 Microchip Technology Inc. DS30009977G-page 105

PIC18F66K80 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 7 BSR(1) 0 000h Data Memory 00h 7 From Opcode(2) 0 Bank 0 0 0 0 0 0 0 1 0 11 11 11 11 11 11 11 11 FFh 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK Using this “forced” addressing allows the instruction to operate on a data address in a single cycle without While the use of the BSR, with an embedded 8-bit updating the BSR first. For 8-bit addresses of 60h and address, allows users to address the entire range of data above, this means that users can evaluate and operate memory, it also means that the user must ensure that the on SFRs more efficiently. The Access RAM below 60h correct bank is selected. If not, data may be read from, is a good place for data values that the user might need or written to, the wrong location. This can be disastrous to access rapidly, such as immediate computational if a GPR is the intended target of an operation, but an results or common program variables. SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become Access RAM also allows for faster and more code very inefficient. efficient context saving and switching of variables. To streamline access for the most commonly used data The mapping of the Access Bank is slightly different memory locations, the data memory is configured with when the extended instruction set is enabled (XINST an Access Bank, which allows users to access a Configuration bit = 1). This is discussed in more detail mapped block of memory without specifying a BSR. in Section6.6.3 “Mapping the Access Bank in The Access Bank consists of the first 96 bytes of Indexed Literal Offset Mode”. memory (00h-5Fh) in Bank 0 and the last 160 bytes of 6.3.3 GENERAL PURPOSE memory (60h-FFh) in Bank 15. The lower half is known as the “Access RAM” and is composed of GPRs. The REGISTER FILE upper half is where the device’s SFRs are mapped. PIC18 devices may have banked memory in the GPR These two areas are mapped contiguously in the area. This is data RAM which is available for use by all Access Bank and can be addressed in a linear fashion instructions. GPRs start at the bottom of Bank 0 by an eight-bit address (Figure6-6). (address 000h) and grow upwards towards the bottom of The Access Bank is used by core PIC18 instructions the SFR area. GPRs are not initialized by a Power-on that include the Access RAM bit (the ‘a’ parameter in Reset and are unchanged on all other Resets. the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map. In that case, the current value of the BSR is ignored entirely. DS30009977G-page 106  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, The Special Function Registers (SFRs) are registers Resets and interrupts) and those related to the used by the CPU and peripheral modules for controlling peripheral functions. The Reset and Interrupt registers the desired operation of the device. These registers are are described in their respective chapters, while the implemented as static RAM. SFRs start at the top of ALU’s STATUS register is described later in this section. data memory (FFFh) and extend downward to occupy Registers related to the operation of the peripheral all of Bank 15 (F00h to FFFh) and the top part of features are described in the chapter for that peripheral. Bank14 (EF4h to EFFh). The SFRs are typically distributed among the A list of these registers is given in Table6-1 and peripherals whose functions they control. Unused SFR Table6-2. locations are unimplemented and read as ‘0’s. TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F66K80 FAMILY Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name FFFh TOSU FDFh INDF2(1) FBFh ECCP1AS F9Fh IPR1 F7Fh EECON1 F5Fh CM1CON(5) FFEh TOSH FDEh POSTINC2(1) FBEh ECCP1DEL F9Eh PIR1 F7Eh EECON2 F5Eh CM2CON(5) FFDh TOSL FDDh POSTDEC2(1) FBDh CCPR1H F9Dh PIE1 F7Dh SPBRGH1 F5Dh ANCON0(5) FFCh STKPTR FDCh PREINC2(1) FBCh CCPR1L F9Ch PSTR1CON F7Ch SPBRGH2 F5Ch ANCON1(5) FFBh PCLATU FDBh PLUSW2(1) FBBh CCP1CON F9Bh OSCTUNE F7Bh SPBRG2 F5Bh WPUB(5) FFAh PCLATH FDAh FSR2H FBAh TXSTA2 F9Ah REFOCON F7Ah RCREG2 F5Ah IOCB(5) FF9h PCL FD9h FSR2L FB9h BAUDCON2 F99h CCPTMRS F79h TXREG2 F59h PMD0(5) FF8h TBLPTRU FD8h STATUS FB8h IPR4 F98h TRISG(3) F78h IPR5 F58h PMD1(5) FF7h TBLPTRH FD7h TMR0H FB7h PIR4 F97h TRISF(3) F77h PIR5 F57h PMD2(5) FF6h TBLPTRL FD6h TMR0L FB6h PIE4 F96h TRISE(4) F76h PIE5 F56h PADCFG1(5) FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(4) F75h EEADRH F55hCTMUCONH(5) FF4h PRODH FD4h —(2) FB4h CMSTAT F94h TRISC F74h EEADR F54hCTMUCONL(5) FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h EEDATA F53hCTMUICONH(5) FF2h INTCON FD2h OSCCON2 FB2h TMR3L F92h TRISA F72h ECANCON F52h CCPR2H(5) FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h ODCON F71h COMSTAT F51h CCPR2L(5) FF0h INTCON3 FD0h RCON FB0h T3GCON F90h SLRCON F70h CIOCON F50hCCP2CON(4,5) FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG(3) F6Fh CANCON F4Fh CCPR3H(4,5) FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF(3) F6Eh CANSTAT F4Eh CCPR3L(4,5) FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE(4) F6Dh RXB0D7 F4Dh CCP3CON(5) FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD(4) F6Ch RXB0D6 F4Ch CCPR4H(5) FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RXB0D5 F4Bh CCPR4L(5) FEAh FSR0H FCAh T2CON FAAh T1GCON F8Ah LATB F6Ah RXB0D4 F4Ah CCP4CON(5) FE9h FSR0L FC9h SSPBUF FA9h PR4 F89h LATA F69h RXB0D3 F49h CCPR5H(5) FE8h WREG FC8h SSPADD FA8h HLVDCON F88h T4CON F68h RXB0D2 F48h CCPR5L(5) FE7h INDF1(1) FC8h SSPMSK FA7h BAUDCON1 F87h TMR4 F67h RXB0D1 F47h CCP5CON(5) FE6h POSTINC1(1) FC7h SSPSTAT FA6h RCSTA2 F86h PORTG(3) F66h RXB0D0 F46h PSPCON(4,5) FE5h POSTDEC1(1) FC6h SSPCON1 FA5h IPR3 F85h PORTF(3) F65h RXB0DLC F45h MDCON(3,5) FE4h PREINC1(1) FC5h SSPCON2 FA4h PIR3 F84h PORTE F64h RXB0EIDL F44h MDSRC(3,5) FE3h PLUSW1(1) FC4h ADRESH FA3h PIE3 F83h PORTD(4) F63h RXB0EIDH F43h MDCARH(3,5) FE2h FSR1H FC3h ADRESL FA2h IPR2 F82h PORTC F62h RXB0SIDL F42h MDCARL(3,5) FE1h FSR1L FC2h ADCON0 FA1h PIR2 F81h PORTB F61h RXB0SIDH F41h —(2) FE0h BSR FC1h ADCON1 FA0h PIE2 F80h PORTA F60h RXB0CON F40h —(2) FC0h ADCON2 Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is only available on devices with 64 pins. 4: This register is not available on devices with 28 pins. 5: Addresses, E41h through F5Fh, are also used by the SFRs, but are not part of the Access RAM. To access these registers, users must always load the proper BSR value.  2010-2017 Microchip Technology Inc. DS30009977G-page 107

PIC18F66K80 FAMILY TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F66K80 FAMILY (CONTINUED) Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name F3Fh CANCON_RO0(5) F0Fh CANCON_RO3(5) EDFh CANCON_RO4(5) EAFhCANCON_RO7(5) E7Fh TXBIE(5) E4Fh RXF7EIDL(5) F3EhCANSTAT_RO0(5) F0EhCANSTAT_RO3(5) EDEh CANSTAT_RO4(5) EAEhCANSTAT_RO7(5) E7Eh BIE0(5) E4Eh RXF7EIDH(5) F3Dh RXB1D7(5) F0Dh TXB2D7(5) EDDh B5D7(5) EADh B2D7(5) E7Dh BSEL0(5) E4Dh RXF7SIDL(5) F3Ch RXB1D6(5) F0Ch TXB2D6(5) EDCh B5D6(5) EACh B2D6(5) E7Ch MSEL3(5) E4Ch RXF7SIDH(5) F3Bh RXB1D5(5) F0Bh TXB2D5(5) EDBh B5D5(5) EABh B2D5(5) E7Bh MSEL2(5) E4Bh RXF6EIDL(5) F3Ah RXB1D4(5) F0Ah TXB2D4(5) EDAh B5D4(5) EAAh B2D4(5) E7Ah MSEL1(5) E4Ah RXF6EIDH(5) F39h RXB1D3(5) F09h TXB2D3(5) ED9h B5D3(5) EA9h B2D3(5) E79h MSEL0(5) E49h RXF6SIDL(5) F38h RXB1D2(5) F08h TXB2D2(5) ED8h B5D2(5) EA8h B2D2(5) E78hRXFBCON7(5) E48h RXF6SIDH(5) F37h RXB1D1(5) F07h TXB2D1(5) ED7h B5D1(5) EA7h B2D1(5) E77hRXFBCON6(5) E47h RXFCON1(5) F36h RXB1D0(5) F06h TXB2D0(5) ED6h B5D0(5) EA6h B2D0(5) E76hRXFBCON5(5) E46h RXFCON0(5) F35h RXB1DLC(5) F05h TXB2DLC(5) ED5h B5DLC(5) EA5h B2DLC(5) E75hRXFBCON4(5) E45h BRGCON3(5) F34h RXB1EIDL(5) F04h TXB2EIDL(5) ED4h B5EIDL(5) EA4h B2EIDL(5) E74hRXFBCON3(5) E44h BRGCON2(5) F33h RXB1EIDH(5) F03h TXB2EIDH(5) ED3h B5EIDH(5) EA3h B2EIDH(5) E73hRXFBCON2(5) E43h BRGCON1(5) F32h RXB1SIDL(5) F02h TXB2SIDL(5) ED2h B5SIDL(5) EA2h B2SIDL(5) E72hRXFBCON1(5) E42h TXERRCNT(5) F31h RXB1SIDH(5) F01h TXB2SIDH(5) ED1h B5SIDH(5) EA1h B2SIDH(5) E71hRXFBCON0(5) E41h RXERRCNT(5) F30h RXB1CON(5) F00h TXB2CON(5) ED0h B5CON(5) EA0h B2CON(5) E70h SDFLC(5) F30h RXB1CON(5) EFFh RXM1EIDL(5) ECFh CANCON_RO5(5) E9FhCANCON_RO8(5) E6FhRXF15EIDL(5) F2Fh CANCON_RO1(5) EFEh RXM1EIDH(5) ECEh CANSTAT_RO5(5) E9EhCANSTAT_RO8(5) E6EhRXF15EIDH(5) F2EhCANSTAT_RO1(5) EFDh RXM1SIDL(5) ECDh B4D7(5) E9Dh B1D7(5) E6DhRXF15SIDL(5) F2Dh TXB0D7(5) EFCh RXM1SIDH(5) ECCh B4D6(5) E9Ch B1D6(5) E6ChRXF15SIDH(5) F2Ch TXB0D6(5) EFBh RXM0EIDL(5) ECBh B4D5(5) E9Bh B1D5(5) E6BhRXF14EIDL(5) F2Bh TXB0D5(5) EFAh RXM0EIDH(5) ECAh B4D4(5) E9Ah B1D4(5) E6AhRXF14EIDH(5) F2Ah TXB0D4(5) EF9h RXM0SIDL(5) EC9h B4D3(5) E99h B1D3(5) E69hRXF14SIDL(5) F29h TXB0D3(5) EF8h RXM0SIDH(5) EC8h B4D2(5) E98h B1D2(5) E68hRXF14SIDH(5) F28h TXB0D2(5) EF7h RXF5EIDL(5) EC7h B4D1(5) E97h B1D1(5) E67hRXF13EIDL(5) F27h TXB0D1(5) EF6h RXF5EIDH(5) EC6h B4D0(5) E96h B1D0(5) E66hRXF13EIDH(5) F26h TXB0D0(5) EF5h RXF5SIDL(5) EC5h B4DLC(5) E95h B1DLC(5) E65hRXF13SIDL(5) F25h TXB0DLC(5) EF4h RXF5SIDH(5) EC4h B4EIDL(5) E94h B1EIDL(5) E64hRXF13SIDH(5) F24h TXB0EIDL(5) EF3h RXF4EIDL(5) EC3h B4EIDH(5) E93h B1EIDH(5) E63hRXF12EIDL(5) F23h TXB0EIDH(5) EF2h RXF4EIDH(5) EC2h B4SIDL(5) E92h B1SIDL(5) E62hRXF12EIDH(5) F22h TXB0SIDL(5) EF1h RXF4SIDL(5) EC1h B4SIDH(5) E91h B1SIDH(5) E61hRXF12SIDL(5) F21h TXB0SIDH(5) EF0h RXF4SIDH(5) EC0h B4CON(5) E90h B1CON(5) E60hRXF12SIDH(5) F20h TXB0CON(5) EEFh RXF3EIDL(5) EBFh CANCON_RO6(5) E90h B1CON(5) E5FhRXF11EIDL(5) F1Fh CANCON_RO2(5) EEEh RXF3EIDH(5) EBEh CANSTAT_RO6(5) E8FhCANCON_RO9(5) E5EhRXF11EIDH(5) F1EhCANSTAT_RO2(5) EEDh RXF3SIDL(5) EBDh B3D7(5) E8EhCANSTAT_RO9(5) E5DhRXF11SIDL(5) F1Dh TXB1D7(5) EECh RXF3SIDH(5) EBCh B3D6(5) E8Dh B0D7(5) E5ChRXF11SIDH(5) F1Ch TXB1D6(5) EEBh RXF2EIDL(5) EBBh B3D5(5) E8Ch B0D6(5) E5BhRXF10EIDL(5) F1Bh TXB1D5(5) EEAh RXF2EIDH(5) EBAh B3D4(5) E8Bh B0D5(5) E5AhRXF10EIDH(5) F1Ah TXB1D4(5) EE9h RXF2SIDL(5) EB9h B3D3(5) E8Ah B0D4(5) E59hRXF10SIDL(5) F19h TXB1D3(5) EE8h RXF2SIDH(5) EB8h B3D2(5) E89h B0D3(5) E58hRXF10SIDH(5) F18h TXB1D2(5) EE7h RXF1EIDL(5) EB7h B3D1(5) E88h B0D2(5) E57h RXF9EIDL(5) F17h TXB1D1(5) EE6h RXF1EIDH(5) EB6h B3D0(5) E87h B0D1(5) E56h RXF9EIDH(5) F16h TXB1D0(5) EE5h RXF1SIDL(5) EB5h B3DLC(5) E86h B0D0(5) E55h RXF9SIDL(5) F15h TXB1DLC(5) EE4h RXF1SIDH(5) EB4h B3EIDL(5) E85h B0DLC(5) E54h RXF9SIDH(5) F14h TXB1EIDL(5) EE3h RXF0EIDL(5) EB3h B3EIDH(5) E84h B0EIDL(5) E53h RXF8EIDL(5) F13h TXB1EIDH(5) EE2h RXF0EIDH(5) EB2h B3SIDL(5) E83h B0EIDH(5) E52h RXF8EIDH(5) F12h TXB1SIDL(5) EE1h RXF0SIDL(5) EB1h B3SIDH(5) E82h B0SIDL(5) E51h RXF8SIDL(5) F11h TXB1SIDH(5) EE0h RXF0SIDH(5) EB0h B3CON(5) E81h B0SIDH(5) E50h RXF8SIDH(5) F10h TXB1CON(5) E80h B0CON(5) Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is only available on devices with 64 pins. 4: This register is not available on devices with 28 pins. 5: Addresses, E41h through F5Fh, are also used by the SFRs, but are not part of the Access RAM. To access these registers, users must always load the proper BSR value. DS30009977G-page 108  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page FFFh TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) 84 FFEh TOSH Top-of-Stack High Byte (TOS<15:8>) 84 FFDh TOSL Top-of-Stack Low Byte (TOS<7:0>) 84 FFCh STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 84 FFBh PCLATU — — Bit 21 Holding Register for PC<20:16> 84 FFAh PCLATH Holding Register for PC<15:8> 84 FF9h PCL PC Low Byte (PC<7:0>) 84 FF8h TBLPTRU — — Bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 84 FF7h TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 84 FF6h TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 84 FF5h TABLAT Program Memory Table Latch 84 FF4h PRODH Product Register High Byte 84 FF3h PRODL Product Register Low Byte 84 FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 84 FF1h INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 84 FF0h INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 84 FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) 84 FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) 84 FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) 84 FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) 84 FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – 84 value of FSR0 offset by W FEAh FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte 84 FE9h FSR0L Indirect Data Memory Address Pointer 0 Low Byte 84 FE8h WREG Working Register 84 FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) 84 FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) 84 FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) 84 FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) 84 FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – 84 value of FSR1 offset by W FE2h FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte 84 FE1h FSR1L Indirect Data Memory Address Pointer 1 Low Byte 84 FE0h BSR — — — — Bank Select Register 84 FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) 84 FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) 85 FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) 85 FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) 85 FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – 85 value of FSR2 offset by W FDAh FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte 85 FD9h FSR2L Indirect Data Memory Address Pointer 2 Low Byte 85 FD8h STATUS — — — N OV Z DC C 85 FD7h TMR0H Timer0 Register High Byte 85 FD6h TMR0L Timer0 Register Low Byte 85 FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 85 FD4h Unimplemented — FD3h OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 85 FD2h OSCCON2 — SOSCRUN — SOSCDRV SOSCGO — MFIOFS MFIOSEL 85 FD1h WDTCON REGSLP — ULPLVL SRETEN — ULPEN ULPSINK SWDTEN 85 FD0h RCON IPEN SBOREN CM RI TO PD POR BOR 85  2010-2017 Microchip Technology Inc. DS30009977G-page 109

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page FCFh TMR1H Timer1 Register High Byte 85 FCEh TMR1L Timer1 Register Low Bytes 85 FCDh T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON 85 FCCh TMR2 Timer2 Register 85 FCBh PR2 Timer2 Period Register 85 FCAh T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 85 FC9h SSPBUF MSSP Receive Buffer/Transmit Register 85 FC8h SSPADD MSSP Address Register (I2C™ Slave Mode), MSSP Baud Rate Reload Register (I2C Master Mode) 85 FC8h SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 85 FC7h SSPSTAT SMP CKE D/A P S R/W UA BF 85 FC6h SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 85 FC5h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 85 FC4h ADRESH A/D Result Register High Byte 85 FC3h ADRESL A/D Result Register Low Byte 85 FC2h ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 85 FC1h ADCON1 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 85 FC0h ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 85 FBFh ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 85 FBEh ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 85 FBDh CCPR1H Capture/Compare/PWM Register 1 High Byte 85 FBCh CCPR1L Capture/Compare/PWM Register 1 Low Byte 85 FBBh CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 85 FBAh TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 85 FB9h BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 85 FB8h IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP 85 FB7h PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF 85 FB6h PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE 85 FB5h CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 85 FB4h CMSTAT CMP2OUT CMP1OUT — — — — — — 85 FB3h TMR3H Timer3 Register High Byte 85 FB2h TMR3L Timer3 Register Low Bytes 85 FB1h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON 85 FB0h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 85 T3DONE FAFh SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 85 FAEh RCREG1 EUSART1 Receive Register 85 FADh TXREG1 EUSART1 Transmit Register 85 FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 85 FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 85 FAAh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 85 T1DONE FA9h PR4 Timer4 Period Register 85 FA8h HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 85 FA7h BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 85 FA6h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 85 FA5h IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — 85 FA4h PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — 85 FA3h PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — 85 FA2h IPR2 OSCFIP — — — BCLIP HLVDIP TMR3IP TMR3GIP 85 FA1h PIR2 OSCFIF — — — BCLIF HLVDIF TMR3IF TMR3GIF 85 FA0h PIE2 OSCFIE — — — BCLIE HLVDIE TMR3IE TMR3GIE 85 DS30009977G-page 110  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page F9Fh IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP 86 F9Eh PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF 85 F9Dh PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE 85 F9Ch PSTR1CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 85 F9Bh OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 86 F9Ah REFOCON ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 86 F99h CCPTMRS — — — C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL 86 F98h TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 86 F97h TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 86 F96h TRISE TRISE7 TRISE6 TRISE5 TRISE4 — TRISE2 TRISE1 TRISE0 86 F95h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 86 F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 86 F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 86 F92h TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 86 F91h ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD 86 F90h SLRCON — SLRG SLRF SLRE SLRD SLRC SLRB SLRA 86 F8Fh LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 86 F8Eh LATF LATF7 LATF6 LATF5 LATF4 — LATF2 LATF1 LATF0 86 F8Dh LATE LATE7 LATE6 LATE5 LATE4 — LATE2 LATE1 LATE0 86 F8Ch LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 86 F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 86 F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 86 F89h LATA LATA7 LATA6 LATA5 — LATA3 LATA2 LATA1 LATA0 86 F88h T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 86 F87h TMR4 Timer4 Register 86 F86h PORTG — — — RG4 RG3 RG2 RG1 RG0 86 F85h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 86 F84h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 86 F83h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 86 F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 86 F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 86 F80h PORTA RA7 RA6 RA5 — RA3 RA2 RA1 RA0 86 F7Fh EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 86 F7Eh EECON2 Flash Self-Program Control Register (not a physical register) 86 F7Dh SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 86 F7Ch SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 86 F7Bh SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 86 F7Ah RCREG2 EUSART2 Receive Register 86 F79h TXREG2 EUSART2 Transmit Register 87 F78h IPR5 IRXIP WAKIP ERRIP TX2BIP TXB1IP TXB0IP RXB1IP RXB0IP 87 F77h PIR5 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 87 F76H PIE5 IRXIE WAKIE ERRIE TX2BIE TXB1IE TXB0IE RXB1IE RXB0IE 87 F75h EEADRH Data EE Address Register High Byte 87 F74h EEADR Data EE Address Register Low Byte 87 F73h EEDATA Data EE Data Register 87 F72h ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 87 F71h COMSTAT RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 87 F70h CIOCON TX2SRC TX2EN ENDRHI CANCAP — — — CLKSEL 87 F6Fh CANCON REQOP2 REQOP1 REQOP0 ABAT WIN2/FP3 WIN1/FP2 WIN0/FP1 FP0 87 F6Eh CANSTAT OPMODE2 OPMODE1 OPMODE0 —/ ICODE2/ ICODE1/ ICODE0/ —/ 87 EICOD4 EICODE3 EICODE2 EICODE1 EICODE0  2010-2017 Microchip Technology Inc. DS30009977G-page 111

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page F6Dh RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 87 F6Ch RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 87 F6Bh RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 87 F6Ah RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 87 F69h RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 87 F68h RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 87 F67h RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 87 F66h RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 87 F65h RXB0DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 87 F64h RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 87 F63h RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 87 F62h RXB0SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 87 F61h RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 87 F60h RXB0CON RXFUL RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF FILHIT0 87 F60h RXB0CON RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 87 F5Fh CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 87 F5Eh CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 87 F5Dh ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 87 F5Ch ANCON1 — ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 87 F5Bh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 87 F5Ah IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 87 F59h PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD 87 F58h PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD 89 F57h PMD2 — — — — MODMD ECANMD CMP2MD CMP1MD 89 F56h PADCFG1 RDPU REPU RFPU RGPU — — — CTMUDS 89 F55h CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 89 F54h CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 89 F53h CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 89 F52h CCPR2H Capture/Compare/PWM Register 2 High Byte 89 F51h CCPR2L Capture/Compare/PWM Register 2 Low Byte 89 F50h CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 89 F4Fh CCPR3H Capture/Compare/PWM Register 3 High Byte 89 F4Eh CCPR3L Capture/Compare/PWM Register 3 Low Byte 89 F4Dh CCP3CON — — DC3B1 D32B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 89 F4Ch CCPR4H Capture/Compare/PWM Register 4 High Byte 89 F4Bh CCPR4L Capture/Compare/PWM Register 4 Low Byte 89 F4Ah CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 89 F49H CCPR5H Capture/Compare/PWM Register 5 High Byte 89 F48h CCPR5L Capture/Compare/PWM Register 5 Low Byte 89 F47h CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 89 F46h PSPCON IBF OBF IBOV PSPMODE — — — — 89 F45h MDCON MDEN MDOE MDSLR MDOPOL MDO — — MDBIT 89 F44h MDSRC MDSODIS — — — MDSRC3 MDSRC2 MDSRC1 MDSRC0 89 F43h MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH3 MDCH2 MDCH1 MDCH0 89 F42h MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL3 MDCL2 MDCL1 MDCL0 89 F41h Unimplemented — F40h Unimplemented — F3Fh CANCON_RO0 CANCON_RO0 89 F3Eh CANSTAT_RO0 CANSTAT_RO0 89 F3Dh RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 89 F3Ch RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 89 DS30009977G-page 112  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page F3Bh RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 89 F3Ah RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 89 F39h RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 89 F38h RXB1D2 RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 89 F37h RXB1D1 RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 89 F36h RXB1D0 RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 89 F35h RXB1DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 89 F34h RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 90 F33h RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 90 F32h RXB1SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 90 F31h RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 90 F30h RXB1CON RXFUL RXM1 RXM0 — RXRTRRO RXBODBEN JTOFF FILHIT0 90 F30h RXB1CON RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 90 F2Fh CANCON_RO1 CANCON_RO1 90 F2Eh CANSTAT_RO1 CANSTAT_RO1 90 F2Dh TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 90 F2Ch TXB0D6 TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 90 F2Bh TXB0D5 TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 90 F2Ah TXB0D4 TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 90 F29h TXB0D3 TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 90 F28h TXB0D2 TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 90 F27h TXB0D1 TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 90 F26h TXB0D0 TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 90 F25h TXB0DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 90 F24h TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 90 F23h TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 90 F22h TXB0SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 90 F21h TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 90 F20h TXB0CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 90 F1Fh CANCON_RO2 CANCON_RO2 90 F1Eh CANSTAT_RO2 CANSTAT_RO2 90 F1Dh TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 90 F1Ch TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 90 F1Bh TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 90 F1Ah TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 90 F19h TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 90 F18h TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 90 F17h TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 90 F16h TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 90 F15h TXB1DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 90 F14h TXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 90 F13h TXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 90 F12h TXB1SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 90 F11h TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 90 F10h TXB1CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 90 F0Fh CANCON_RO3 CANCON_RO3 90 F0Eh CANSTAT_RO3 CANSTAT_RO3 90 F0Dh TXB2D7 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 90 F0Ch TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 91 F0Bh TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 91 F0Ah TXB2D4 TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 —  2010-2017 Microchip Technology Inc. DS30009977G-page 113

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page F09h TXB2D3 TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 91 F08h TXB2D2 TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 91 F07h TXB2D1 TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 91 F06h TXB2D0 TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 91 F05h TXB2DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 91 F04h TXB2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 F03h TXB2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 F02h TXB2SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 91 F01h TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 F00h TXB2CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 91 EFFh RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 EFEh RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 EFDh RXM1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 91 EFCh RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 EFBh RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 EFAh RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 EF9h RXM0SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 91 EF8h RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 EF7h RXF5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 EF6h RXF5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 EF5h RXF5SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 91 EF4h RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 EF3h RXF4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 EF2h RXF4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 EF1h RXF4SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 91 EF0h RXF4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 EEFh RXF3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 EEEh RXF3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 EEDh RXF3SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 91 EECh RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 EEBh RXF2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 EEAh RXF2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 EE9h RXF2SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 91 EE8h RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 EE7h RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 EE6h RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 EE5h RXF1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 91 EE4h RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 EE3h RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 EE2h RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 EE1h RXF0SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 91 EE0h RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 EDFh CANCON_RO4 CANCON_RO4 91 EDEh CANSTAT_RO4 CANSTAT_RO4 91 EDDh B5D7 B5D77 B5D76 B5D75 B5D74 B5D73 B5D72 B5D71 B5D70 91 EDCh B5D6 B5D67 B5D66 B5D65 B5D64 B5D63 B5D62 B5D61 B5D60 91 EDBh B5D5 B5D57 B5D56 B5D55 B5D54 B5D53 B5D52 B5D51 B5D50 91 EDAh B5D4 B5D47 B5D46 B5D45 B5D44 B5D43 B5D42 B5D41 B5D40 91 ED9h B5D3 B5D37 B5D36 B5D35 B5D34 B5D33 B5D32 B5D31 B5D30 91 ED8h B5D2 B5D27 B5D26 B5D25 B5D24 B5D23 B5D22 B5D21 B5D20 91 ED7h B5D1 B5D17 B5D16 B5D15 B5D14 B5D13 B5D12 B5D11 B5D10 91 DS30009977G-page 114  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page ED6h B5D0 B5D07 B5D06 B5D05 B5D04 B5D03 B5D02 B5D01 B5D00 91 ED5h B5DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 91 ED4h B5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 91 ED3h B5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 91 ED2h B5SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 91 ED1h B5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 91 ED0h B5CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 91 ECFh CANCON_RO5 CANCON_RO5 91 ECEh CANSTAT_RO5 CANSTAT_RO5 92 ECDh B4D7 B4D77 B4D76 B4D75 B4D74 B4D73 B4D72 B4D71 B4D70 92 ECCh B4D6 B4D67 B4D66 B4D65 B4D64 B4D63 B4D62 B4D61 B4D60 92 ECBh B4D5 B4D57 B4D56 B4D55 B4D54 B4D53 B4D52 B4D51 B4D50 92 ECAh B4D4 B4D47 B4D46 B4D45 B4D44 B4D43 B4D42 B4D41 B4D40 92 EC9h B4D3 B4D37 B4D36 B4D35 B4D34 B4D33 B4D32 B4D31 B4D30 92 EC8h B4D2 B4D27 B4D26 B4D25 B4D24 B4D23 B4D22 B4D21 B4D20 92 EC7h B4D1 B4D17 B4D16 B4D15 B4D14 B4D13 B4D12 B4D11 B4D10 92 EC6h B4D0 B4D07 B4D06 B4D05 B4D04 B4D03 B4D02 B4D01 B4D00 92 EC5h B4DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 92 EC4h B4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 92 EC3h B4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 92 EC2h B4SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 92 EC1h B4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 92 EC0h B4CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 92 EBFh CANCON_RO6 CANCON_RO6 92 EBEh CANSTAT_RO6 CANSTAT_RO6 92 EBDh B3D7 B3D77 B3D76 B3D75 B3D73 B3D73 B3D72 B3D71 B3D70 92 EBCh B3D6 B3D67 B3D66 B3D65 B3D63 B3D63 B3D62 B3D61 B3D60 92 EBBh B3D5 B3D57 B3D56 B3D55 B3D53 B3D53 B3D52 B3D51 B3D50 92 EBAh B3D4 B3D47 B3D46 B3D45 B3D43 B3D43 B3D42 B3D41 B3D40 92 EB9h B3D3 B3D37 B3D36 B3D35 B3D33 B3D33 B3D32 B3D31 B3D30 92 EB8h B3D2 B3D27 B3D26 B3D25 B3D23 B3D23 B3D22 B3D21 B3D20 92 EB7h B3D1 B3D17 B3D16 B3D15 B3D13 B3D13 B3D12 B3D11 B3D10 92 EB6h B3D0 B3D07 B3D06 B3D05 B3D03 B3D03 B3D02 B3D01 B3D00 92 EB5h B3DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 92 EB4h B3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 92 EB3h B3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 92 EB2h B3SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 92 EB1h B3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 92 EB0h B3CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 92 EAFh CANCON_RO7 CANCON_RO7 92 EAEh CANSTAT_RO7 CANSTAT_RO7 92 EADh B2D7 B2D77 B2D76 B2D75 B2D72 B2D73 B2D72 B2D71 B2D70 92 EACh B2D6 B2D67 B2D66 B2D65 B2D62 B2D63 B2D62 B2D61 B2D60 92 EABh B2D5 B2D57 B2D56 B2D55 B2D52 B2D53 B2D52 B2D51 B2D50 93 EAAh B2D4 B2D47 B2D46 B2D45 B2D42 B2D43 B2D42 B2D41 B2D40 93 EA9h B2D3 B2D37 B2D36 B2D35 B2D32 B2D33 B2D32 B2D31 B2D30 93 EA8h B2D2 B2D27 B2D26 B2D25 B2D22 B2D23 B2D22 B2D21 B2D20 93 EA7h B2D1 B2D17 B2D16 B2D15 B2D12 B2D13 B2D12 B2D11 B2D10 93 EA6h B2D0 B2D07 B2D06 B2D05 B2D02 B2D03 B2D02 B2D01 B2D00 93 EA5h B2DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 93 EA4h B2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 93  2010-2017 Microchip Technology Inc. DS30009977G-page 115

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page EA3h B2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 93 EA2h B2SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 93 EA1h B2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 93 EA0h B2CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 93 E9Fh CANCON_RO8 CANCON_RO8 93 E9Eh CANSTAT_RO8 CANSTAT_RO8 93 E9Dh B1D7 B1D77 B1D76 B1D75 B1D71 B1D73 B1D72 B1D71 B1D70 93 E9Ch B1D6 B1D67 B1D66 B1D65 B1D61 B1D63 B1D62 B1D61 B1D60 93 E9Bh B1D5 B1D57 B1D56 B1D55 B1D51 B1D53 B1D52 B1D51 B1D50 93 E9Ah B1D4 B1D47 B1D46 B1D45 B1D41 B1D43 B1D42 B1D41 B1D40 93 E99h B1D3 B1D37 B1D36 B1D35 B1D31 B1D33 B1D32 B1D31 B1D30 93 E98h B1D2 B1D27 B1D26 B1D25 B1D21 B1D23 B1D22 B1D21 B1D20 93 E97h B1D1 B1D17 B1D16 B1D15 B1D11 B1D13 B1D12 B1D11 B1D10 93 E96h B1D0 B1D07 B1D06 B1D05 B1D01 B1D03 B1D02 B1D01 B1D00 93 E95h B1DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 93 E94h B1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 93 E93h B1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 93 E92h B1SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 93 E91h B1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 93 E90h B1CON TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 93 E90h B1CON RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 93 E8Fh CANCON_RO9 CANCON_RO9 93 E8Eh CANSTAT_RO9 CANSTAT_RO9 93 E8Dh B0D7 B0D77 B0D76 B0D75 B0D70 B0D73 B0D72 B0D71 B0D70 93 E8Ch B0D6 B0D67 B0D66 B0D65 B0D60 B0D63 B0D62 B0D61 B0D60 93 E8Bh B0D5 B0D57 B0D56 B0D55 B0D50 B0D53 B0D52 B0D51 B0D50 93 E8Ah B0D4 B0D47 B0D46 B0D45 B0D40 B0D43 B0D42 B0D41 B0D40 93 E89h B0D3 B0D37 B0D36 B0D35 B0D30 B0D33 B0D32 B0D31 B0D30 93 E88h B0D2 B0D27 B0D26 B0D25 B0D20 B0D23 B0D22 B0D21 B0D20 94 E87h B0D1 B0D17 B0D16 B0D15 B0D10 B0D13 B0D12 B0D11 B0D10 94 E86h B0D0 B0D07 B0D06 B0D05 B0D00 B0D03 B0D02 B0D01 B0D00 94 E85h B0DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 94 E84h B0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 94 E83h B0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 94 E82h B0SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 94 E81h B0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 94 E80h B0CON TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 94 E80h B0CON RTXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 94 E7Fh TXBIE — — — CAN TX Buffer Interrupt Enable — — 94 E7Eh BIE0 CAN Buffer Interrupt Enable 94 E7Dh BSEL0 Mode Select Register 0 — — 94 E7Ch MSEL3 CAN Mask Select Register 3 94 E7Bh MSEL2 CAN Mask Select Register 2 94 E7Ah MSEL1 CAN Mask Select Register 1 94 E79h MSEL0 CAN Mask Select Register 0 94 E78h RXFBCON7 CAN Buffer 15/14 Pointer Register 94 E77h RXFBCON6 CAN Buffer 13/12 Pointer Register 94 E76h RXFBCON5 CAN Buffer 11/10 Pointer Register 94 E75h RXFBCON4 CAN Buffer 9/8 Pointer Register 94 E74h RXFBCON3 CAN Buffer 7/6 Pointer Register 94 E73h RXFBCON2 CAN Buffer 5/4 Pointer Register 94 DS30009977G-page 116  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 6-2: PIC18F66K80 FAMILY REGISTER FILE SUMMARY (CONTINUED) Value on Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page E72h RXFBCON1 CAN Buffer 3/2 Pointer Register 94 E71h RXFBCON0 CAN Buffer 1/0 Pointer Register 94 E70h SDFLC — — — CAN Device Net Count Register 94 E6Fh RXF15EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 94 E6Eh RXF15EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 94 E6Dh RXF15SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 94 E6Ch RXF15SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 94 E6Bh RXF14EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 94 E6Ah RXF14EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 94 E69h RXF14SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 94 E68h RXF14SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 94 E67h RXF13EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 94 E66h RXF13EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 95 E65h RXF13SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 95 E64h RXF13SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 95 E63h RXF12EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 95 E62h RXF12EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 95 E61h RXF12SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 95 E60h RXF12SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 95 E5Fh RXF11EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 95 E5Eh RXF11EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 95 E5Dh RXF11SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 95 E5Ch RXF11SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 95 E5Bh RXF10EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 95 E5Ah RXF10EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 95 E59h RXF10SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 95 E58h RXF10SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 95 E57h RXF9EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 95 E56h RXF9EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 95 E55h RXF9SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 95 E54h RXF9SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 95 E53h RXF8EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 95 E52h RXF8EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 95 E51h RXF8SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 95 E50h RXF8SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 95 E4Fh RXF7EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 95 E4Eh RXF7EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 95 E4Dh RXF7SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 95 E4Ch RXF7SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 95 E4Bh RXF6EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 95 E4Ah RXF6EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 95 E49h RXF6SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 95 E48h RXF6SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 95 E47h RXFCON1 CAN Receive Filter Control Register 1 95 E46h RXFCON0 CAN Receive Filter Control Register 0 95 E45h BRGCON3 WAKDIS WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 95 E44h BRGCON2 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 96 E43h BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 96 E42h TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 96 E41h RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 96  2010-2017 Microchip Technology Inc. DS30009977G-page 117

PIC18F66K80 FAMILY 6.3.5 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions be used to alter The STATUS register, shown in Register6-2, contains the STATUS register because these instructions do not the arithmetic status of the ALU. The STATUS register affect the Z, C, DC, OV or N bits in the STATUS can be the operand for any instruction, as with any register. other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, For other instructions not affecting any Status bits, see the write to these five bits is disabled. the instruction set summaries in Table29-2 and Table29-3. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the Note: The C and DC bits operate, in subtraction, STATUS register as destination may be different than as borrow and digit borrow bits, respectively. intended. For example, CLRF STATUS will set the Z bit but leave the other bits unchanged. The STATUS register then reads back as ‘000u u1uu’. REGISTER 6-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the seven-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result occurred bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. 2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. DS30009977G-page 118  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 6.4 Data Addressing Modes of data RAM (see Section6.3.3 “General Purpose Register File”) or a location in the Access Bank (see Note: The execution of some instructions in the Section6.3.2 “Access Bank”). core PIC18 instruction set are changed The Access RAM bit, ‘a’, determines how the address when the PIC18 extended instruction set is is interpreted. When ‘a’ is ‘1’, the contents of the BSR enabled. For more information, see (Section6.3.1 “Bank Select Register”) are used with Section6.6 “Data Memory and the the address to determine the complete 12-bit address Extended Instruction Set”. of the register. When ‘a’ is ‘0’, the address is interpreted While the program memory can be addressed in only as being a register in the Access Bank. Addressing that one way, through the Program Counter, information in uses the Access RAM is sometimes also known as the data memory space can be addressed in several Direct Forced Addressing mode. ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their depending on which operands are used and whether or opcodes. In these cases, the BSR is ignored entirely. not the extended instruction set is enabled. The destination of the operation’s results is determined The addressing modes are: by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are stored back in the source register, overwriting its origi- • Inherent nal contents. When ‘d’ is ‘0’, the results are stored in • Literal the W register. Instructions without the ‘d’ argument • Direct have a destination that is implicit in the instruction, • Indirect either the target register being operated on or the W An additional addressing mode, Indexed Literal Offset, register. is available when the extended instruction set is 6.4.3 INDIRECT ADDRESSING enabled (XINST Configuration bit = 1). For details on this mode’s operation, see Section6.6.1 “Indexed Indirect Addressing allows the user to access a location Addressing with Literal Offset”. in data memory without giving a fixed address in the instruction. This is done by using File Select Registers 6.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written ADDRESSING to. Since the FSRs are themselves located in RAM as Many PIC18 control instructions do not need any Special Function Registers, they can also be directly argument at all. They either perform an operation that manipulated under program control. This makes FSRs globally affects the device or they operate implicitly on very useful in implementing data structures such as one register. This addressing mode is known as Inherent tables and arrays in data memory. Addressing. Examples of this mode include SLEEP, The registers for Indirect Addressing are also RESET and DAW. implemented with Indirect File Operands (INDFs) that Other instructions work in a similar way, but require an permit automatic manipulation of the pointer value with additional explicit argument in the opcode. This method auto-incrementing, auto-decrementing or offsetting is known as the Literal Addressing mode because the with another value. This allows for efficient code using instructions require some literal value as an argument. loops, such as the example of clearing an entire RAM Examples of this include ADDLW and MOVLW, which bank in Example6-5. It also enables users to perform respectively, add or move a literal value to the W Indexed Addressing and other Stack Pointer register. Other examples include CALL and GOTO, operations for program memory in data memory. which include a 20-bit program memory address. EXAMPLE 6-5: HOW TO CLEAR RAM 6.4.2 DIRECT ADDRESSING (BANK 1) USING INDIRECT ADDRESSING Direct Addressing specifies all or part of the source and/or destination address of the operation within the LFSR FSR0, 100h ; opcode itself. The options are specified by the NEXT CLRF POSTINC0 ; Clear INDF arguments accompanying the instruction. ; register then ; inc pointer In the core PIC18 instruction set, bit-oriented and BTFSS FSR0H, 1 ; All done with byte-oriented instructions use some version of Direct ; Bank1? Addressing by default. All of these instructions include BRA NEXT ; NO, clear next some 8-bit literal address as their Least Significant CONTINUE ; YES, continue Byte. This address specifies the instruction’s data source as either a register address in one of the banks  2010-2017 Microchip Technology Inc. DS30009977G-page 119

PIC18F66K80 FAMILY 6.4.3.1 FSR Registers and the mapped in the SFR space, but are not physically imple- INDF Operand mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. At the core of Indirect Addressing are three sets of A read from INDF1, for example, reads the data at the registers: FSR0, FSR1 and FSR2. Each represents a address indicated by FSR1H:FSR1L. pair of 8-bit registers: FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each Instructions that use the INDF registers as operands FSR pair holds a 12-bit value. This represents a value actually use the contents of their corresponding FSR as that can address the entire range of the data memory a pointer to the instruction’s target. The INDF operand in a linear fashion. The FSR register pairs, then, serve is just a convenient way of using the pointer. as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, Indirect Addressing is accomplished with a set of Indi- data RAM banking is not necessary. Thus, the current rect File Operands, INDF0 through INDF2. These can contents of the BSR and the Access RAM bit have no be thought of as “virtual” registers. The operands are effect on determining the target address. FIGURE 6-8: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... x x x x 1 1 1 1 1 1 0 0 1 1 0 0 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains FCCh. This means the contents of Bank 14 location FCCh will be added to that F00h of the W register and stored back in Bank 15 FCCh. FFFh Data Memory DS30009977G-page 120  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 6.4.3.2 FSR Registers and POSTINC, 6.4.3.3 Operations by FSRs on FSRs POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For also has four additional indirect operands. Like INDF, example, using an FSR to point to one of the virtual these are “virtual” registers that cannot be indirectly registers will not result in successful operations. read or written to. Accessing these registers actually As a specific case, assume that the FSR0H:FSR0L accesses the associated FSR register pair, but also registers contain FE7h, the address of INDF1. performs a specific action on its stored value. Attempts to read the value of the INDF1, using INDF0 These operands are: as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a • POSTDEC – Accesses the FSR value, then NOP. automatically decrements it by ‘1’ afterwards • POSTINC – Accesses the FSR value, then On the other hand, using the virtual registers to write to automatically increments it by ‘1’ afterwards an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair, but without any • PREINC – Increments the FSR value by ‘1’, then incrementing or decrementing. Thus, writing to INDF2 uses it in the operation or POSTDEC2 will write the same value to the • PLUSW – Adds the signed value of the W register FSR2H:FSR2L. (range of -127 to 128) to that of the FSR and uses the new value in the operation Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct In this context, accessing an INDF register uses the operations. Users should proceed cautiously when value in the FSR registers without changing them. working on these registers, however, particularly if their Similarly, accessing a PLUSW register gives the FSR code uses Indirect Addressing. value, offset by the value in the W register, with neither value actually changed in the operation. Accessing the Similarly, operations by Indirect Addressing are gener- other virtual registers changes the value of the FSR ally permitted on all other SFRs. Users should exercise registers. the appropriate caution, so that they do not inadvertently change settings that might affect the operation of the Operations on the FSRs with POSTDEC, POSTINC device. and PREINC affect the entire register pair. Rollovers of the FSRnL register, from FFh to 00h, carry over to the 6.5 Program Memory and the FSRnH register. On the other hand, results of these Extended Instruction Set operations do not change the value of any flags in the STATUS register (for example, Z, N and OV bits). The operation of program memory is unaffected by the The PLUSW register can be used to implement a form use of the extended instruction set. of Indexed Addressing in the data memory space. By Enabling the extended instruction set adds five manipulating the value in the W register, users can additional two-word commands to the existing PIC18 reach addresses that are fixed offsets from pointer instruction set: ADDFSR, CALLW, MOVSF, MOVSS and addresses. In some applications, this can be used to SUBFSR. These instructions are executed as described implement some powerful program control structure, in Section6.2.4 “Two-Word Instructions”. such as software stacks, inside of data memory.  2010-2017 Microchip Technology Inc. DS30009977G-page 121

PIC18F66K80 FAMILY 6.6 Data Memory and the Extended Under these conditions, the file address of the Instruction Set instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing) or as Enabling the PIC18 extended instruction set (XINST an 8-bit address in the Access Bank. Instead, the value Configuration bit = 1) significantly changes certain is interpreted as an offset value to an Address Pointer aspects of data memory and its addressing. Using the specified by FSR2. The offset and the contents of FSR2 Access Bank for many of the core PIC18 instructions are added to obtain the target address of the operation. introduces a new addressing mode for the data memory space. This mode also alters the behavior of Indirect 6.6.2 INSTRUCTIONS AFFECTED BY Addressing using FSR2 and its associated operands. INDEXED LITERAL OFFSET MODE What does not change is just as important. The size of Any of the core PIC18 instructions that can use Direct the data memory space is unchanged, as well as its Addressing are potentially affected by the Indexed linear addressing. The SFR map remains the same. Literal Offset Addressing mode. This includes all Core PIC18 instructions can still operate in both Direct byte-oriented and bit-oriented instructions, or almost and Indirect Addressing mode. Inherent and literal one-half of the standard PIC18 instruction set. Instruc- instructions do not change at all. Indirect Addressing tions that only use Inherent or Literal Addressing with FSR0 and FSR1 also remains unchanged. modes are unaffected. Additionally, byte-oriented and bit-oriented instructions 6.6.1 INDEXED ADDRESSING WITH are not affected if they do not use the Access Bank LITERAL OFFSET (Access RAM bit = 1), or include a file address of 60h Enabling the PIC18 extended instruction set changes or above. Instructions meeting these criteria will the behavior of Indirect Addressing using the FSR2 continue to execute as before. A comparison of the dif- register pair and its associated file operands. Under the ferent possible addressing modes when the extended proper conditions, instructions that use the Access instruction set is enabled is shown in Figure6-9. Bank – that is, most bit-oriented and byte-oriented Those who desire to use byte-oriented or bit-oriented instructions – can invoke a form of Indexed Addressing instructions in the Indexed Literal Offset mode should using an offset specified in the instruction. This special note the changes to assembler syntax for this mode. addressing mode is known as Indexed Addressing with This is described in more detail in Section29.2.1 Literal Offset or the Indexed Literal Offset mode. “Extended Instruction Syntax”. When using the extended instruction set, this addressing mode requires the following: • Use of the Access Bank (‘a’ = 0) • A file address argument that is less than or equal to 5Fh DS30009977G-page 122  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When a = 0 and f  60h: The instruction executes in 060h Direct Forced mode. ‘f’ is Bank 0 interpreted as a location in the 100h Access RAM between 060h 00h and FFFh. This is the same as Bank 1 60h locations, F60h to FFFh, through Bank 14 Valid Range (Bank15) of data memory. for ‘f’ Locations below 060h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F40h SFRs FFFh Data Memory When a = 0 and f5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 060h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F40h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 060h Direct mode (also known as Direct Long mode). ‘f’ is 100h interpreted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F40h SFRs FFFh Data Memory  2010-2017 Microchip Technology Inc. DS30009977G-page 123

PIC18F66K80 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN Remapping the Access Bank applies only to operations INDEXED LITERAL OFFSET MODE using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit = 1) will continue to use The use of Indexed Literal Offset Addressing mode Direct Addressing as before. Any Indirect or Indexed effectively changes how the lower part of Access RAM Addressing operation that explicitly uses any of the (00h to 5Fh) is mapped. Rather than containing just the indirect file operands (including FSR2) will continue to contents of the bottom part of Bank 0, this mode maps operate as standard Indirect Addressing. Any instruc- the contents from Bank 0 and a user-defined “window” tion that uses the Access Bank, but includes a register that can be located anywhere in the data memory address of greater than 05Fh, will use Direct space. Addressing and the normal Access Bank map. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the 6.6.4 BSR IN INDEXED LITERAL upper boundary is defined by FSR2 plus 95 (5Fh). OFFSET MODE Addresses in the Access RAM above 5Fh are mapped Although the Access Bank is remapped when the as previously described. (See Section6.3.2 “Access extended instruction set is enabled, the operation of the Bank”.) An example of Access Bank remapping in this BSR remains unchanged. Direct Addressing, using the addressing mode is shown in Figure6-10. BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Not Accessible FSR2H:FSR2L = 120h 05Fh Locations in the region Bank 0 from the FSR2 Pointer 100h (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Access RAM (000h-05Fh). 200h Bank 1 “Window” 5Fh Special Function Registers 60h at F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh are not available in FFh this mode. They can still Access Bank be addressed by using the F00h BSR. Bank 15 F60h SFRs FFFh Data Memory DS30009977G-page 124  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time. Program memory is The program memory space is 16 bits wide, while the erased in blocks of 64 bytes at a time. A bulk erase data RAM space is 8 bits wide. Table reads and table operation may not be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and place it into the data RAM space. or erase, therefore, code cannot execute. An internal Figure7-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory A value written to program memory does not need to be space into holding registers in program memory. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section7.5 “Writing NOP. to Flash Program Memory”. Figure7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory.  2010-2017 Microchip Technology Inc. DS30009977G-page 125

PIC18F66K80 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section7.5 “Writing to Flash Program Memory”. 7.2 Control Registers The FREE bit, when set, allows a program memory erase operation. When FREE is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, allows a write operation. On • EECON2 register power-up, the WREN bit is clear. The WRERR bit is set • TABLAT register in hardware when the WR bit is set and cleared when • TBLPTR registers the internal programming timer expires and the write operation is complete. 7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is The EECON1 register (Register7-1) is the control read as ‘1’. This can indicate that a write register for memory accesses. The EECON2 register, operation was prematurely terminated by not a physical register, is used exclusively in the a Reset, or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The WR control bit initiates write operations. The bit The EEPGD control bit determines if the access is a cannot be cleared, only set, in software. It is cleared in program or data EEPROM memory access. When hardware at the completion of the write operation. clear, any subsequent operations operate on the data EEPROM memory. When set, any subsequent Note: The EEIF interrupt flag bit (PIR4<6>) is operations operate on the program memory. set when the write is complete. It must be cleared in software. The CFGS control bit determines if the access is to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations operate on Configuration registers regardless of EEPGD (see Section28.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. DS30009977G-page 126  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Accesses Flash program memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration registers 0 = Accesses Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erases the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Performs write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or, a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2010-2017 Microchip Technology Inc. DS30009977G-page 127

PIC18F66K80 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an eight-bit register TBLPTR is used in reads, writes and erases of the mapped into the SFR space. The Table Latch register Flash program memory. is used to hold 8-bit data during data transfers between When a TBLRD is executed, all 22bits of the TBLPTR program memory and data RAM. determine which byte is read from program memory into TABLAT. 7.2.3 TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of The Table Pointer (TBLPTR) register addresses a byte the 64 program memory holding registers is written to. within the program memory. The TBLPTR is comprised When the timed write to program memory begins (via of three SFR registers: Table Pointer Upper Byte, Table the WR bit), the 16 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:6>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 64 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section7.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2Mbytes of When an erase of program memory is executed, the program memory space. The 22nd bit allows access to 16MSbs of the Table Pointer register (TBLPTR<21:6>) the Device ID, the User ID and the Configuration bits. point to the 64-byte block that will be erased. The Least The Table Pointer register, TBLPTR, is used by the Significant bits (TBLPTR<5:0>) are ignored. TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways, based on the Figure7-3 describes the relevant boundaries of table operation. These operations are shown in TBLPTR based on Flash program memory operations. Table7-1 and only affect the low-order 21bits. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE/WRITE TABLE WRITE TBLPTR<21:6> TBLPTR<5:0> TABLE READ – TBLPTR<21:0> DS30009977G-page 128  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 7.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVF WORD_ODD  2010-2017 Microchip Technology Inc. DS30009977G-page 129

PIC18F66K80 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The erase blocks are 32 words or 64 bytes. The sequence of events for erasing a block of internal Word erase in the Flash array is not supported. program memory location is: When initiating an erase sequence from the micro- 1. Load the Table Pointer register with the address controller itself, a block of 64 bytes of program memory of row to be erased. is erased. The Most Significant 16 bits of the 2. Set the EECON1 register for the erase operation: TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored. • Set the EEPGD bit to point to program memory • Clear the CFGS bit to access program memory The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash • Set the WREN bit to enable writes program memory. The WREN bit must be set to enable • Set the FREE bit to enable the erase write operations. The FREE bit is set to select an erase 3. Disable the interrupts. operation. 4. Write 55h to EECON2. For protection, the write initiate sequence for EECON2 5. Write 0AAh to EECON2. must be used. 6. Set the WR bit. A long write is necessary for erasing the internal Flash. This begins the row erase cycle. Instruction execution is halted while in a long write The CPU will stall for the duration of the erase cycle. The long write will be terminated by the internal for TIW. (See Parameter D133A.) programming timer. 7. Re-enable interrupts. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS30009977G-page 130  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 7.5 Writing to Flash Program Memory The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip The programming blocks are 32 words or 64 bytes. charge pump, rated to operate over the voltage range Word or byte programming is not supported. of the device. Table writes are used internally to load the holding regis- Note: The default value of the holding registers on ters needed to program the Flash memory. There are device Resets and after write operations is 64holding registers for programming by the table writes. FFh. A write of FFh to a holding register does not modify that byte. This means that Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64times for individual bytes of program memory may each programming operation. All of the table write oper- be modified, provided that the change does ations will essentially be short writes because only the not attempt to change any bit from a ‘0’ to a holding registers are written. At the end of updating the ‘1’. When modifying individual bytes, it is not necessary to load all 64 holding 64 or 128 holding registers, the EECON1 register must registers before executing a write be written to in order to start the programming operation operation. with a long write. The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle. The long write is terminated by the internal programming timer. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F Holding Register Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE 9. Write 55h to EECON2. SEQUENCE 10. Write 0AAh to EECON2. The sequence of events for programming an internal 11. Set the WR bit. This will begin the write cycle. program memory location should be: The CPU will stall for the duration of the write for TIW (see Parameter D133A). 1. Read the 64bytes into RAM. 12. Re-enable the interrupts. 2. Update the data values in RAM as necessary. 13. Verify the memory (table read). 3. Load the Table Pointer register with the address being erased. An example of the required code is shown in Example7-3 on the following page. 4. Execute the row erase procedure. 5. Load the Table Pointer register with the address Note: Before setting the WR bit, the Table of the first byte being written. Pointer address needs to be within the 6. Write the 64bytes into the holding registers with intended address range of the 64bytes in auto-increment. the holding register. 7. Set the EECON1 register for the write operation: • Set the EEPGD bit to point to program memory • Clear the CFGS bit to access program memory • Set the WREN to enable byte writes 8. Disable the interrupts.  2010-2017 Microchip Technology Inc. DS30009977G-page 131

PIC18F66K80 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW SIZE_OF_BLOCK ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L WRITE_BUFFER_BACK MOVLW SIZE_OF_BLOCK ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS DS30009977G-page 132  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory 7.5.2 WRITE VERIFY 7.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section28.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more detail. 7.5.3 UNEXPECTED TERMINATION OF 7.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section28.6 “Program Verification and Code location just programmed should be verified and repro- Protection” for details on code protection of Flash grammed if needed. If the write operation is interrupted program memory. by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBLPTRU — — bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS — FREE WRERR WREN WR RD IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.  2010-2017 Microchip Technology Inc. DS30009977G-page 133

PIC18F66K80 FAMILY 8.0 DATA EEPROM MEMORY 8.2 EECON1 and EECON2 Registers The data EEPROM is a nonvolatile memory array, Access to the data EEPROM is controlled by two separate from the data RAM and program memory, that registers: EECON1 and EECON2. These are the same is used for long-term storage of program data. It is not registers which control access to the program memory directly mapped in either the register file or program and are used in a similar manner for the data memory space, but is indirectly addressed through the EEPROM. Special Function Registers (SFRs). The EEPROM is The EECON1 register (Register8-1) is the control readable and writable during normal operation over the register for data and program memory access. Control entire VDD range. bit, EEPGD, determines if the access will be to program Five SFRs are used to read and write to the data memory or data EEPROM memory. When clear, EEPROM, as well as the program memory. They are: operations will access the data EEPROM memory. When set, program memory is accessed. • EECON1 • EECON2 Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data • EEDATA EEPROM memory. When set, subsequent operations • EEADR access Configuration registers. When CFGS is clear, • EEADRH the EEPGD bit selects either program Flash or data The data EEPROM allows byte read and write. When EEPROM memory. interfacing to the data memory block, EEDATA holds The WREN bit, when set, will allow a write operation. the 8-bit data for read/write and the EEADRH:EEADR On power-up, the WREN bit is clear. The WRERR bit is register pair holds the address of the EEPROM location set in hardware when the WREN bit is set and cleared, being accessed. when the internal programming timer expires and the The EEPROM data memory is rated for high erase/write write operation is complete. cycle endurance. A byte write automatically erases the Note: During normal operation, the WRERR is location and writes the new data (erase-before-write). read as ‘1’. This can indicate that a write The write time is controlled by an on-chip timer; it will operation was prematurely terminated by vary with voltage and temperature, as well as from chip- a Reset, or a write operation was to-chip. Please refer to Parameter D122 (Table31-1 in attempted improperly. Section31.0 “Electrical Characteristics”) for exact limits. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in 8.1 EEADR and EEADRH Registers hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR4<6>) is The EEADRH:EEADR register pair is used to address set when the write is complete. It must be the data EEPROM for read and write operations. cleared in software. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can Control bits, RD and WR, start read and erase/write address a memory range of 1024 bytes (00h to 3FFh). operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section7.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. DS30009977G-page 134  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Accesses Flash program memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration registers 0 = Accesses Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erases the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Performs write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2010-2017 Microchip Technology Inc. DS30009977G-page 135

PIC18F66K80 FAMILY 8.3 Reading the Data EEPROM After a write sequence has been initiated, EECON1, Memory EEADRH:EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the To read a data memory location, the user must write the WREN bit is set. The WREN bit must be set on a address to the EEADRH:EEADR register pair, clear the previous instruction. Both WR and WREN cannot be EEPGD control bit (EECON1<7>) and then set control set with the same instruction. bit, RD (EECON1<0>). The data is available after one At the completion of the write cycle, the WR bit is instruction cycle, in the EEDATA register. It can be read cleared in hardware and the EEPROM Interrupt Flag bit after one NOP instruction. EEDATA will hold this value (EEIF) is set. The user may either enable this interrupt until another read operation or until it is written to by the or poll this bit; EEIF must be cleared by software. user (during a write operation). The basic process is shown in Example8-1. 8.5 Write Verify 8.4 Writing to the Data EEPROM Depending on the application, good programming practice may dictate that the value written to the Memory memory should be verified against the original value. To write an EEPROM data location, the address must This should be used in applications where excessive first be written to the EEADRH:EEADR register pair writes can stress bits near the specification limit. and the data written to the EEDATA register. The Note: Self-write execution to Flash and sequence in Example8-2 must be followed to initiate EEPROM memory cannot be done while the write cycle. running in LP Oscillator (low-power) The write will not begin if this sequence is not exactly mode. Executing a self-write will put the followed (write 55h to EECON2, write 0AAh to device into High-Power mode. EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this codesegment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared byhardware. DS30009977G-page 136  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY EXAMPLE 8-1: DATA EEPROM READ MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to read MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read NOP MOVF EEDATA, W ; W = EEDATA EXAMPLE 8-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to write MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete GOTO $-2 BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set)  2010-2017 Microchip Technology Inc. DS30009977G-page 137

PIC18F66K80 FAMILY 8.6 Operation During Code-Protect 8.8 Using the Data EEPROM Data EEPROM memory has its own code-protect bits in The data EEPROM is a high-endurance, Configuration Words. External read and write byte-addressable array that has been optimized for the operations are disabled if code protection is enabled. storage of frequently changing information (e.g., pro- gram variables or other data that are updated often). The microcontroller itself can both read and write to the Frequently changing values will typically be updated internal data EEPROM regardless of the state of the more often than Parameter D124. If this is not the case, code-protect Configuration bit. Refer to Section28.0 an array refresh must be performed. For this reason, “Special Features of the CPU” for additional variables that change infrequently (such as constants, information. IDs, calibration, etc.) should be stored in Flash program memory. 8.7 Protection Against Spurious Write A simple data EEPROM refresh routine is shown in There are conditions when the device may not want to Example8-3. write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have Note: If data EEPROM is only used to store been implemented. On power-up, the WREN bit is constants and/or data that changes often, cleared. In addition, writes to the EEPROM are blocked an array refresh is likely not required. See during the Power-up Timer period (TPWRT, Parameter D124. Parameter33). The write initiate sequence, and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 CLRF EEADRH ; BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes LOOP ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again INCFSZ EEADRH, F ; Increment the high address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS30009977G-page 138  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF EEADRH EEPROM Address Register High Byte EEADR EEPROM Address Register Low Byte EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS — FREE WRERR WREN WR RD IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2010-2017 Microchip Technology Inc. DS30009977G-page 139

PIC18F66K80 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 9.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W advantages of higher computational throughput and MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows PIC18 devices to be used in many applications SUBWF PRODH, F ; PRODH = PRODH previously reserved for digital-signal processors. A ; - ARG1 comparison of various hardware and software multiply MOVF ARG2, W operations, along with the savings in memory and BTFSC ARG1, SB ; Test Sign Bit execution time, is shown in Table9-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 9.2 Operation Example9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the argu- ments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 64 MHz @ 48 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 4.3 s 5.7 s 27.6 s 69 s 8 x 8 unsigned Hardware multiply 1 1 62.5 ns 83.3 ns 400 ns 1 s Without hardware multiply 33 91 5.6 s 7.5 s 36.4 s 91 s 8 x 8 signed Hardware multiply 6 6 375 ns 500 ns 2.4 s 6 s 16 x 16 Without hardware multiply 21 242 15.1 s 20.1 s 96.8 s 242 s unsigned Hardware multiply 28 28 1.7 s 2.3 s 11.2 s 28 s Without hardware multiply 52 254 15.8 s 21.2 s 101.6 s 254 s 16 x 16 signed Hardware multiply 35 40 2.5 s 3.3 s 16.0 s 40 s DS30009977G-page 140  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY Example9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED unsigned multiplication. Equation9-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0= ARG1H:ARG1L  ARG2H:ARG2L = (ARG1H  ARG2H  216) + EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H  ARG2L  28) + MULTIPLICATION (ARG1L  ARG2H  28) + ALGORITHM (ARG1L  ARG2L) + (-1  ARG2H<7>  ARG1H:ARG1L  216) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (-1  ARG1H<7>  ARG2H:ARG2L  216) = (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + EXAMPLE 9-4: 16 x 16 SIGNED MULTIPLY (ARG1L  ARG2L) ROUTINE MOVF ARG1L, W EXAMPLE 9-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL MOVF PRODL, W ; ; ADDWF RES1, F ; Add cross MOVF ARG1L, W MOVF PRODH, W ; products MULWF ARG2H ; ARG1L * ARG2H-> ADDWFC RES2, F ; ; PRODH:PRODL CLRF WREG ; MOVF PRODL, W ; ADDWFC RES3, F ; ADDWF RES1, F ; Add cross ; MOVF PRODH, W ; products MOVF ARG1H, W ; ADDWFC RES2, F ; MULWF ARG2L ; ARG1H * ARG2L -> CLRF WREG ; ; PRODH:PRODL ADDWFC RES3, F ; MOVF PRODL, W ; ; ADDWF RES1, F ; Add cross MOVF ARG1H, W ; MOVF PRODH, W ; products MULWF ARG2L ; ARG1H * ARG2L-> ADDWFC RES2, F ; ; PRODH:PRODL CLRF WREG ; MOVF PRODL, W ; ADDWFC RES3, F ; ADDWF RES1, F ; Add cross ; MOVF PRODH, W ; products BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? ADDWFC RES2, F ; BRA SIGN_ARG1 ; no, check ARG1 CLRF WREG ; MOVF ARG1L, W ; SUBWF RES2 ; ADDWFC RES3, F ; MOVF ARG1H, W ; SUBWFB RES3 ; Example9-4 shows the sequence to do a 16 x 16 SIGN_ARG1 signed multiply. Equation9-2 shows the algorithm BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? used. The 32-bit result is stored in four registers BRA CONT_CODE ; no, done (RES3:RES0). To account for the sign bits of the MOVF ARG2L, W ; arguments, the MSb for each argument pair is tested SUBWF RES2 ; MOVF ARG2H, W ; and the appropriate subtractions are done. SUBWFB RES3 ; CONT_CODE :  2010-2017 Microchip Technology Inc. DS30009977G-page 141

PIC18F66K80 FAMILY 10.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible Members of the PIC18F66K80 family of devices have with PIC® mid-range devices. In Compatibility mode, the multiple interrupt sources and an interrupt priority interrupt priority bits for each source have no effect. INT- feature that allows most interrupt sources to be CON<6> is the PEIE bit that enables/disables all periph- assigned a high-priority level or a low-priority level. The eral interrupt sources. INTCON<7> is the GIE bit that high-priority interrupt vector is at 0008h and the enables/disables all interrupt sources. All interrupts low-priority interrupt vector is at 0018h. High-priority branch to address 0008h in Compatibility mode. interrupt events will interrupt any low-priority interrupts When an interrupt is responded to, the Global Interrupt that may be in progress. Enable bit is cleared to disable further interrupts. If the The registers for controlling interrupt operation are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a • INTCON low-priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3, PIR4 and PIR5 PC is loaded with the interrupt vector address (0008h • PIE1, PIE2, PIE3, PIE4 and PIE5 or 0018h). Once in the Interrupt Service Routine (ISR), • IPR1, IPR2, IPR3, IPR4 and IPR5 the source(s) of the interrupt can be determined by poll- It is recommended that the Microchip header files ing the interrupt flag bits. The interrupt flag bits must be supplied with MPLAB® IDE be used for the symbolic cleared in software before re-enabling interrupts to bit names in these registers. This allows the avoid recursive interrupts. assembler/compiler to automatically take care of the The “return from interrupt” instruction, RETFIE, exits placement of these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL In general, interrupt sources have three bits to control if priority levels are used) that re-enables interrupts. their operation. They are: For external interrupt events, such as the INTx pins or • Flag bit – Indicating that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit – Enabling program execution to Individual interrupt flag bits are set regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit – Specifying high priority or low priority Note: Do not use the MOVFF instruction to modify any of the Interrupt Control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is cause erratic microcontroller behavior. enabled, there are two bits that enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate Global Interrupt Enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. DS30009977G-page 142  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 10-1: PIC18F66K80 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> TMR0IF Wake-up if in IPR1<7:0> TMR0IE Idle or Sleep modes TMR0IP RBIF PIR2<7,5:0> RBIE PIE2<7,5:0> RBIP IPR2<7,5:0> INT0IF INT0IE PIR3<7,5> INT1IF PIE3<7,5> INT1IE Interrupt to CPU IPR3<7,5> INT1IP Vector to Location INT2IF PIR4<7:0> INT2IE 0008h PIE4<7:0> INT2IP IPR4<7:0> INT3IF INT3IE INT3IP GIE/GIEH PIR5<7:0> PIE5<7:0> IPR5<7:0> IPEN IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7, 5:0> PIE2<7, 5:0> IPR2<7, 5:0> Interrupt to CPU PIR3<7, 5:0> TTMMRR00IIEF IPEN V00e1c8tohr to Location PIE3<7, 5:0> TMR0IP IPR3<7, 5:0> RBIF PIR4<7:0> RBIE PIE4<7:0> RBIP GIE/GIEH IPR4<7:0> PEIE/GIEL INT1IF INT1IE PIR5<7:0> INT1IP PIE5<7:0> INT2IF IPR5<7:0> INT2IE INT2IP INT3IF INT3IE INT3IP  2010-2017 Microchip Technology Inc. DS30009977G-page 143

PIC18F66K80 FAMILY 10.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the Global registers that contain various enable, priority and flag Interrupt Enable bit. User software should bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE(2) TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit(2) 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register has not overflowed bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. To end the mismatch condition and allow the bit to be cleared, read PORTB and wait one additional instruction cycle. 2: Each pin on PORTB for interrupt-on-change is individually enabled and disabled in the IOCB register. By default, all pins are disabled. DS30009977G-page 144  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port TRIS values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010-2017 Microchip Technology Inc. DS30009977G-page 145

PIC18F66K80 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS30009977G-page 146  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 10.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs regardless of The PIR registers contain the individual flag bits for the the state of its corresponding enable bit or peripheral interrupts. Due to the number of peripheral the Global Interrupt Enable bit, GIE interrupt sources, there are six Peripheral Interrupt (INTCON<7>). Request (Flag) registers (PIR1 through PIR5). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or write operation has taken place (must be cleared in software) 0 = No read or write operation has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSARTx Receive Interrupt Flag bit 1 = The EUSARTx receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSARTx receive buffer is empty bit 4 TX1IF: EUSARTx Transmit Interrupt Flag bit 1 = The EUSARTx transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSARTx transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software) 0 = No timer gate interrupt occurred bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow  2010-2017 Microchip Technology Inc. DS30009977G-page 147

PIC18F66K80 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF — — — BCLIF HLVDIF TMR3IF TMR3GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (bit must be cleared in software) 0 = Device clock is operating bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (bit must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (bit must be cleared in software) 0 = The device voltage is above the regulator’s low-voltage trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (bit must be cleared in software) 0 = TMR3 register did not overflow bit 0 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (bit must be cleared in software) 0 = No timer gate interrupt occurred DS30009977G-page 148  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 U-0 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: EUSARTx Receive Interrupt Flag bit 1 = The EUSARTx receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSARTx receive buffer is empty bit 4 TX2IF: EUSARTx Transmit Interrupt Flag bit 1 = The EUSARTx transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSARTx transmit buffer is full bit 3 CTMUIF: CTMU Interrupt Flag bit 1 = CTMU interrupt occurred (must be cleared in software) 0 = No CTMU interrupt occurred bit 2 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 0 Unimplemented: Read as ‘0’  2010-2017 Microchip Technology Inc. DS30009977G-page 149

PIC18F66K80 FAMILY REGISTER 10-7: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR4IF: TMR4 Overflow Interrupt Flag bit 1 = TMR4 register overflowed (must be cleared in software) 0 = TMR4 register did not overflow bit 6 EEIF: Data EEDATA/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 5 CMP2IF: CMP2 Interrupt Flag bit 1 = CMP2 interrupt occurred (must be cleared in software) 0 = CMP2 interrupt did not occur bit 4 CMP1IF: CMP1 Interrupt Flag bit 1 = CMP1 interrupt occurred (must be cleared in software) 0 = CMP1 interrupt did not occur bit 3 Unimplemented: Read as ‘0’ bit 2 CCP5IF: CCP5 Interrupt Flag bit Capture Mode 1 = A TMR register capture occurred (bit must be cleared in software) 0 = No TMR register capture occurred Compare Mode 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode Not used in PWM mode. bit 1 CCP4IF: CCP4 Interrupt Flag bit Capture Mode 1 = A TMR register capture occurred (bit must be cleared in software) 0 = No TMR register capture occurred Compare Mode 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode Not used in PWM mode. bit 0 CCP3IF: CCP3 Interrupt Flag bit Capture Mode 1 = A TMR register capture occurred (bit must be cleared in software) 0 = No TMR register capture occurred Compare Mode 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode Not used in PWM mode. DS30009977G-page 150  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 10-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF/ FIFOFIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIF: Invalid Message Received Interrupt Flag bits 1 = An invalid message occurred on the CAN bus 0 = No invalid message occurred on the CAN bus bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit 1 = Activity on the CAN bus has occurred 0 = No activity on the CAN bus bit 5 ERRIF: Error Interrupt Flag bit (Multiple sources in COMSTAT register) 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors have occurred bit 4 TXB2IF: Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message bit 3 TXB1IF: Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 RXB1IF: Receive Buffer 1 Interrupt Flag bit Mode 0: 1 = CAN Receive Buffer 1 has received a new message 0 = CAN Receive Buffer 1 has not received a new message Modes 1 and 2: 1 = A CAN Receive Buffer/FIFO has received a new message 0 = A CAN Receive Buffer/FIFO has not received a new message bit 0 Bit operation is dependent on the selected mode: Mode 0: RXB0IF: Receive Buffer 0 Interrupt Flag bit 1 = CAN Receive Buffer 0 has received a new message 0 = CAN Receive Buffer 0 has not received a new message Mode 1: Unimplemented: Read as ‘0’ Mode 2: FIFOFIF: FIFO Full Interrupt Flag bit 1 = FIFO has reached full status as defined by the FIFO_HF bit 0 = FIFO has not reached full status as defined by the FIFO_HF bit  2010-2017 Microchip Technology Inc. DS30009977G-page 151

PIC18F66K80 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Enable registers (PIE1 through PIE6). When IPEN (RCON<7>) = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-9: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSARTx Receive Interrupt Enable bit 1 = Enables the EUSARTx receive interrupt 0 = Disables the EUSARTx receive interrupt bit 4 TX1IE: EUSARTx Transmit Interrupt Enable bit 1 = Enables the EUSARTx transmit interrupt 0 = Disables the EUSARTx transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enables the gate 0 = Disabled the gate bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30009977G-page 152  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 10-10: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE — — — BCLIE HLVDIE TMR3IE TMR3GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled  2010-2017 Microchip Technology Inc. DS30009977G-page 153

PIC18F66K80 FAMILY REGISTER 10-11: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 U-0 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: EUSARTx Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSARTx Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 CTMUIE: CTMU Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ DS30009977G-page 154  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 10-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR4IE: TMR4 Overflow Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 EEIE: Data EEDATA/Flash Write Operation Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 CMP2IE: CMP2 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 CMP1IE: CMP1 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 Unimplemented: Read as ‘0’ bit 2 CCP5IE: CCP5 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 CCP4IE: CCP4 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 CCP3IE: CCP3 Interrupt Flag bits 1 = Interrupt is enabled 0 = Interrupt is disabled  2010-2017 Microchip Technology Inc. DS30009977G-page 155

PIC18F66K80 FAMILY REGISTER 10-13: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE/ FIFOFIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIE: Invalid Message Received Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 WAKIE: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 ERRIE: Error Interrupt Flag bit (multiple sources in the COMSTAT register) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 TXB2IE: Transmit Buffer 2 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 TXB1IE: Transmit Buffer 1 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 TXB0IE: Transmit Buffer 0 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 RXB1IE: Receive Buffer 1 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 Bit operation is dependent on the selected mode: Mode 0: RXB0IE: Receive Buffer 0 Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled Mode 1: Unimplemented: Read as ‘0’ Mode 2: FIFOFIE: FIFO Full Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled DS30009977G-page 156  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Priority registers (IPR1 through IPR6). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit (RCON<7>) be set. REGISTER 10-14: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSARTx Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSARTx Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TMR1GIP: Timer1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority  2010-2017 Microchip Technology Inc. DS30009977G-page 157

PIC18F66K80 FAMILY REGISTER 10-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP — — — BCLIP HLVDIP TMR3IP TMR3GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority DS30009977G-page 158  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 10-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: EUSARTx Receive Priority Flag bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSARTx Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’  2010-2017 Microchip Technology Inc. DS30009977G-page 159

PIC18F66K80 FAMILY REGISTER 10-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR4IP: TMR4 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 EEIP: EE Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 CMP2IP: CMP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 CMP1IP: CMP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as ‘0’ bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit CCP3IP: CCP3 Interrupt Priority bits 1 = High priority 0 = Low priority DS30009977G-page 160  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 10-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP/ FIFOFIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIP: Invalid Message Received Interrupt Priority bits 1 = High priority 0 = Low priority bit 6 WAKIP: Bus Wake-up Activity Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN Bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXB2IP: Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TXB0IP: Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 RXB1IP: Receive Buffer 1 Interrupt Priority bit Mode 0: 1 = High priority for Receive Buffer 1 0 = Low priority for Receive Buffer 1 Modes 1 and 2: 1 = High priority for received messages 0 = Low priority for received messages bit 0 RXB0IP/FIFOFIP: Receive Buffer 0 Interrupt Priority bit Mode 0: 1 = High priority for Receive Buffer 0 0 = Low priority for Receive Buffer 0 Mode 1: Unimplemented: Read as ‘0’ Mode 2: FIFOFIE: FIFO Full Interrupt Flag bit 1 = High priority 0 = Low priority  2010-2017 Microchip Technology Inc. DS30009977G-page 161

PIC18F66K80 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-19: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enables priority levels on interrupts 0 = Disables priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: Software BOR Enable bit For details of bit operation, see Register5-1. bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be subsequently set in software) bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register5-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register5-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register5-1. DS30009977G-page 162  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, In 8-bit mode (the default), an overflow in the TMR0 RB2/INT2 and RB3/INT3 pins are edge-triggered. If the register (FFh00h) will set flag bit, TMR0IF. In 16-bit corresponding INTEDGx bit in the INTCON2 register is mode, an overflow in the TMR0H:TMR0L register pair set (= 1), the interrupt is triggered by a rising edge. If (FFFFh0000h) will set TMR0IF. that bit is clear, the trigger is on the falling edge. The interrupt can be enabled/disabled by setting/clearing When a valid edge appears on the RBx/INTx pin, the enable bit, TMR0IE (INTCON<5>). Interrupt priority for corresponding flag bit, INTxIF, is set. This interrupt can Timer0 is determined by the value contained in the inter- be disabled by clearing the corresponding enable bit, rupt priority bit, TMR0IP (INTCON2<2>). For further INTxIE. Before re-enabling the interrupt, the flag bit details on the Timer0 module, see Section13.0 “Timer0 (INTxIF) must be cleared in software in the Interrupt Module”. Service Routine. 10.8 PORTB Interrupt-on-Change All external interrupts (INT0, INT1, INT2 and INT3) can wake up the processor from the power-managed An input change on PORTB<7:4> sets flag bit, RBIF modes, if bit, INTxIE, was set prior to going into the (INTCON<0>). The interrupt can be enabled/disabled power-managed modes. If the Global Interrupt Enable by setting/clearing enable bit, RBIE (INTCON<3>), and bit (GIE) is set, the processor will branch to the interrupt each individual pin can be enabled/disabled by its vector following wake-up. corresponding bit in the IOCB register. The interrupt priority for INT1, INT2 and INT3 is Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the Interrupt determined by the value contained in the interrupt Priority bits, INT1IP (INTCON3<6>), INT2IP priority bit, RBIP (INTCON2<0>). (INTCON3<7>) and INT3IP (INTCON2<1>). There is no priority bit associated with INT0; it is always a high-priority interrupt source. REGISTER 10-20: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IOCB7(1) IOCB6(1) IOCB5(1) IOCB4(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB Control bits(1) 1 = Interrupt-on-change is enabled 0 = Interrupt-on-change is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: Interrupt-on-change also requires that the RBIE bit of the INTCON register be set.  2010-2017 Microchip Technology Inc. DS30009977G-page 163

PIC18F66K80 FAMILY 10.9 Context Saving During Interrupts If a fast return from interrupt is not used (see Section6.3 “Data Memory Organization”), the user During interrupts, the return PC address is saved on may need to save the WREG, STATUS and BSR regis- the stack. Additionally, the WREG, STATUS and BSR ters on entry to the Interrupt Service Routine (ISR). registers are saved on the Fast Return Stack. Depending on the user’s application, other registers also may need to be saved. Example10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF PIR1 PSPIP ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIR2 OSCFIF — — — BCLIF HLVDIF TMR3IF TMR3GIF PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIR5 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE PIE2 OSCFIE — — — BCLIE HLVDIE TMR3IE TMR3GIE PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — PIE4 TMR4IE EEIE CCP2IE CMP1IE — CCP5IE CCP4IE CCP3IE PIE5 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP IPR2 OSCFIP — — — BCLIP HLVDIP TMR3IP TMR3GIP IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP IPR5 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP RCON IPEN SBOREN CM RI TO PD POR BOR Legend: Shaded cells are not used by the interrupts. DS30009977G-page 164  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 11.0 I/O PORTS 11.1 I/O Port Pin Capabilities Depending on the device selected and features When developing an application, the capabilities of the enabled, there are up to seven ports available. Some port pins must be considered. Outputs on some pins pins of the I/O ports are multiplexed with an alternate have higher output drive strength than others. Similarly, function from the peripheral features on the device. In some pins can tolerate higher than VDD input levels. general, when a peripheral is enabled, that pin may not All of the digital ports are 5.5V input tolerant. The be used as a general purpose I/O pin. analog ports have the same tolerance, having clamping Each port has three memory mapped registers for its diodes implemented internally. operation: 11.1.1 PIN OUTPUT DRIVE • TRIS register (Data Direction register) When used as digital I/O, the output pin drive strengths • PORT register (reads the levels on the pins of the vary, according to the pins’ grouping to meet the needs device) for a variety of applications. In general, there are two • LAT register (Output Latch register) classes of output pins, in terms of drive capability: Reading the PORT register reads the current status of • Outputs that are designed to drive higher current the pins, whereas writing to the PORT register, writes loads, such as LEDs: to the Output Latch (LAT) register. - PORTA – PORTB Setting a TRIS bit (= 1) makes the corresponding port - PORTC pin an input (putting the corresponding output driver in • Outputs with lower drive levels, but capable of a High-Impedance mode). Clearing a TRIS bit (= 0) driving normal digital circuit loads with a high input makes the corresponding port pin an output (i.e., put the contents of the corresponding LAT bit on the impedance. Able to drive LEDs, but only those selected pin). with smaller current requirements: - PORTD(1) – PORTE(1) The Output Latch (LAT register) is useful for read-modify-write operations on the value that the I/O - PORTF(2) – PORTG(2) pins are driving. Read-modify-write operations on the Note1: These ports are not available on 28-pin LAT register read and write the latched output value for devices. the PORT register. 2: These ports are not available on 28-pin A simplified model of a generic I/O port, without the or 40/44-pin devices interfaces to other peripherals, is shown in Figure11-1. For more details, see “Absolute Maximum Ratings” in FIGURE 11-1: GENERIC I/O PORT Section31.0 “Electrical Characteristics”. OPERATION 11.1.2 PULL-UP CONFIGURATION Five of the I/O ports (PORTB, PORTD, PORTE, RD LAT PORTF and PORTG) implement configurable weak Data pull-ups on all pins. These are internal pull-ups that Bus D Q allow floating digital input signals to be pulled to a WR LAT I/O Pin(1) consistent level without the use of external resistors. or PORT CKx The pull-ups are enabled with a single bit for each of the Data Latch ports: RBPU (INTCON2<7>) for PORTB, and RDPU, REPU, RFPU and RGPU (PADCFG1<7:4>) for the D Q other ports. WR TRIS Additionally, the PORTB pull-up resistors can be CKx enabled individually using the WPUB register. Each bit TRIS Latch Input in the register corresponds to a bit on PORTB. Buffer RD TRIS Q D ENEN RD PORT Note1: I/O pins have diode protection to VDD and VSS.  2010-2017 Microchip Technology Inc. DS30009977G-page 165

PIC18F66K80 FAMILY REGISTER 11-1: PADCFG1: PAD CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 RDPU(1) REPU(1) RFPU(2) RGPU(2) — — — CTMUDS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDPU: PORTD Pull-up Enable bit(1) 1 = PORTD pull-up resistors are enabled by individual port latch values 0 = All PORTD pull-up resistors are disabled bit 6 REPU: PORTE Pull-up Enable bit(1) 1 = PORTE pull-up resistors are enabled by individual port latch values 0 = All PORTE pull-up resistors are disabled bit 5 RFPU: PORTF Pull-up Enable bit(2) 1 = PORTF pull-up resistors are enabled by individual port latch values 0 = All PORTF pull-up resistors are disabled bit 4 RGPU: PORTG Pull-up Enable bit(2) 1 = PORTG pull-up resistors are enabled by individual port latch values 0 = All PORTG pull-up resistors are disabled bit 3-1 Unimplemented: Read as ‘0’ bit 0 CTMUDS: CTMU Comparator Data Select bit 1 = External comparator (with output on pin CTDIN) is used for CTMU compares 0 = Internal comparator (CMP2) is used for CTMU compares Note 1: These bits are unimplemented on 28-pin devices. 2: These bits are unimplemented on 40-pin devices. REGISTER 11-2: WPUB: WEAK PULL-UP PORTB ENABLE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 WPUB<7:0>: Weak Pull-Up Enable Register bits 1 = Pull-up is enabled on corresponding PORTB pin when RBPU = 0 and the pin is an input 0 = Pull-up is disabled on corresponding PORTB pin DS30009977G-page 166  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 11.1.3 OPEN-DRAIN OUTPUTS FIGURE 11-2: USING THE OPEN-DRAIN OUTPUT (USARTx SHOWN The output pins for several peripherals are also AS EXAMPLE) equipped with a configurable, open-drain output option. This allows the peripherals to communicate with 5.5V +5.5V external pull-up voltage. PIC18F66K80 The open-drain option is implemented on port pins specifically associated with the data and clock outputs of the USARTs, the MSSP module (in SPI mode) and 5V the CCP modules. This option is selectively enabled by VDD TXX 5.5V setting the open-drain control bits in the ODCON (at logic ‘1’) register. When the open-drain option is required, the output pin must also be tied through an external pull-up resistor provided by the user. REGISTER 11-3: ODCON: PERIPHERAL OPEN-DRAIN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSPOD: SPI Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 CCP5OD: CCP5 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 5 CCP4OD: CCP4 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 4 CCP3OD: CCP3 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 3 CCP2OD: CCP2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 2 CCP1OD: CCP1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 1 U2OD: UART2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 0 U1OD: UART1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled  2010-2017 Microchip Technology Inc. DS30009977G-page 167

PIC18F66K80 FAMILY 11.1.4 ANALOG AND DIGITAL PORTS 11.1.5 PORT SLEW RATE Many of the ports multiplex analog and digital function- The output slew rate of each port is programmable to ality, providing a lot of flexibility for hardware designers. select either the standard transition rate, or a reduced PIC18F66K80 family devices can make any analog pin transition rate of ten percent of the standard transition analog or digital, depending on an application’s needs. time, to minimize EMI. The reduced transition time is The ports’ analog/digital functionality is controlled by the default slew rate for all ports. the registers: ANCON0 and ANCON1. Setting these registers makes the corresponding pins analog and clearing the registers makes the ports digi- tal. For details on these registers, see Section23.0 “12-Bit Analog-to-Digital Converter (A/D) Module” REGISTER 11-4: SLRCON: SLEW RATE CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SLRG(1) SLRF(1) SLRE(2) SLRD(2) SLRC(2) SLRB SLRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SLRG: PORTG Slew Rate Control bit(1) 1 = All output pins on PORTG slew at 0.1 the standard rate 0 = All output pins on PORTG slew at standard rate bit 5 SLRF: PORTF Slew Rate Control bit(1) 1 = All output pins on PORTF slew at 0.1 the standard rate 0 = RAll output pins on PORTF slew at standard rate bit 4 SLRE: PORTE Slew Rate Control bit(2) 1 = All output pins on PORTE slew at 0.1 the standard rate 0 = All output pins on PORTE slew at standard rate bit 3 SLRD: PORTD Slew Rate Control bit(2) 1 = All output pins on PORTD slew at 0.1 the standard rate 0 = All output pins on PORTD slew at standard rate bit 2 SLRC: PORTC Slew Rate Control bit(2) 1 = All output pins on PORTC slew at 0.1 the standard rate 0 = All output pins on PORTC slew at standard rate bit 1 SLRB: PORTB Slew Rate Control bit 1 = All output pins on PORTB slew at 0.1 the standard rate 0 = All output pins on PORTB slew at standard rate bit 0 SLRA: PORTA Slew Rate Control bit 1 = All output pins on PORTA slew at 0.1 the standard rate 0 = All output pins on PORTA slew at standard rate Note 1: These bits are unimplemented and read back as ‘0’ on 28-pin and 40/44-pin devices. 2: These bits are unimplemented and read back as ‘0’ on 28-pin devices. DS30009977G-page 168  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 11.2 PORTA, TRISA and OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally LATA Registers serve as the external circuit connections for the exter- nal (primary) oscillator circuit (HS Oscillator modes) or PORTA is a seven-bit wide, bidirectional port. The cor- the external clock input and output (EC Oscillator responding Data Direction and Output Latch registers modes). In these cases, RA6 and RA7 are not available are TRISA and LATA. as digital I/O and their corresponding TRIS and LAT RA5 and RA<3:0> are multiplexed with analog inputs bits are read as ‘0’. When the device is configured to for the A/D Converter. use HF-INTOSC, MF-INTOSC or LF-INTOSC as the default oscillator mode, RA6 and RA7 are automatically The operation of the analog inputs as A/D Converter configured as digital I/O; the oscillator and clock inputs is selected by clearing or setting the ANSELx in/clock out functions are disabled. control bits in the ANCON1 register. The corresponding RA5 has additional functionality for Timer1 and Timer3. TRISA bits control the direction of these pins, even when they are being used as analog inputs. The user It can be configured as the Timer1 clock input or the Timer3 external clock gate input. must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 11-1: INITIALIZING PORTA Note: RA5 and RA<3:0> are configured as CLRF PORTA ; Initialize PORTA by analog inputs on any Reset and are read ; clearing output latches as ‘0’. CLRF LATA ; Alternate method to ; clear output data latches MOVLW 00h ; Configure A/D MOVWF ANCON1 ; for digital inputs MOVLW 0BFh ; Value used to initialize ; data direction MOVWF TRISA ; Set RA<7, 5:0> as inputs, ; RA<6> as output  2010-2017 Microchip Technology Inc. DS30009977G-page 169

PIC18F66K80 FAMILY TABLE 11-1: PORTA FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RA0/CVREF/AN0/ RA0 0 O DIG LATA<0> data output; not affected by analog input. ULPWU 1 I ST PORTA<0> data input; disabled when analog input is enabled. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. ULPWU 1 O DIG Ultra Low-Power Wake-up input. RA1/AN1/C1INC RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I ST PORTA<1> data input; disabled when analog input is enabled. AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not affect digital output. C1INC(1) x I ANA Comparator 1 Input C. RA2/VREF-/AN2/ RA2 0 O DIG LATA<2> data output; not affected by analog input. C2INC 1 I ST PORTA<2> data input; disabled when analog functions are enabled. VREF- 1 I ANA A/D and comparator low reference voltage input. AN2 1 I ANA A/D Input Channel 2. Default input configuration on POR. C2INC(1) x I ANA Comparator 2 Input C. RA3/VREF+/AN3 RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I ST PORTA<3> data input; disabled when analog input is enabled. VREF+ 1 I ANA A/D Input Channel 3. Default input configuration on POR. AN3 1 I ANA A/D and comparator high reference voltage input. RA5/AN4/C2INB/ RA5 0 O DIG LATA<5> data output; not affected by analog input. HLVDIN/T1CKI/ 1 I ST PORTA<5> data input; disabled when analog input is enabled. SS/CTMUI AN4 1 I ANA A/D Input Channel 4. Default configuration on POR. C2INB(2) 1 I ANA Comparator 2 Input B. HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input. T1CKI x I ST Timer1 clock input. SS 1 I ST Slave select input for MSSP module. CTMUI(2) x O — CTMU pulse generator charger for the C2INB comparator input. RA6/OSC2/ RA6 0 O DIG LATA<6> data output; disabled when FOSC2 Configuration bit is set. CLKOUT 1 I ST PORTA<6> data input; disabled when FOSC2 Configuration bit is set. OSC2 x O ANA Main oscillator feedback output connection (HS, XT and LP modes). CLKOUT x O DIG System cycle clock output (FOSC/4) (EC and INTOSC modes). RA7/OSC1/CLKIN RA7 0 O DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set. 1 I ST PORTA<7> data input; disabled when FOSC2 Configuration bit is set. OSC1 x I ANA Main oscillator input connection (HS, XT, and LP modes). CLKIN x I ANA Main external clock source input (EC modes). Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This pin assignment is unavailable for 28-pin devices (PIC18F2XK80). 2: This pin assignment is only available for 28-pin devices (PIC18F2XK80). TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTA RA7(1) RA6(1) RA5 — RA3 RA2 RA1 RA0 LATA LATA7(1) LATA6(1) LATA5 — LATA3 LATA2 LATA1 LATA0 TRISA TRISA7(1) TRISA6(1) TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. DS30009977G-page 170  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 11.3 PORTB, TRISB and Four of the PORTB pins (RB<7:4>) have an LATB Registers interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur. Any RB<7:4> PORTB is an eight-bit wide, bidirectional port. The pins that are configured as outputs are excluded from corresponding Data Direction and Output Latch registers the interrupt-on-change comparison. are TRISB and LATB. All pins on PORTB are digital only. Comparisons with the input pins (of RB<7:4>) are made with the old value latched on the last read of EXAMPLE 11-2: INITIALIZING PORTB PORTB. The “mismatch” outputs of RB<7:4> are ORed CLRF PORTB ; Initialize PORTB by together to generate the RB Port Change Interrupt with ; clearing output Flag bit, RBIF (INTCON<0>). ; data latches This interrupt can wake the device from CLRF LATB ; Alternate method power-managed modes. To clear the interrupt in the ; to clear output Interrupt Service Routine: ; data latches MOVLW 0CFh ; Value used to 1. Perform any read or write of PORTB (except ; initialize data with the MOVFF (ANY), PORTB instruction). ; direction 2. Wait one instruction cycle (such as executing a MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs NOP instruction). ; RB<7:6> as inputs This ends the mismatch condition. 3. Clear flag bit, RBIF. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is A mismatch condition will continue to set flag bit, RBIF. performed by clearing bit, RBPU (INTCON2<7>). The Reading PORTB will end the mismatch condition and weak pull-up is automatically turned off when the port allow flag bit, RBIF, to be cleared after a one TCY delay. pin is configured as an output. The pull-ups are The interrupt-on-change feature is recommended for disabled on a Power-on Reset. wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. The RB<3:2> pins are multiplexed as CTMU edge inputs. RB5 has an additional function for Timer3 and Timer1. It can be configured for Timer3 clock input or Timer1 external clock gate input.  2010-2017 Microchip Technology Inc. DS30009977G-page 171

PIC18F66K80 FAMILY TABLE 11-3: PORTB FUNCTIONS TRIS Pin Name Function I/O I/O Type Description Setting RB0/AN10/C1INA RB0 0 O DIG LATB<0> data output. FLT0/INT0 1 I ST PORTB<0> data input; weak pull-up when RBPU bit is cleared. AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input configuration on POR. C1INA(1) 1 I ANA Comparator 1 Input A. FLT0 x I ST Enhanced PWM Fault input for ECCPx. INT0 1 I ST External Interrupt 0 input. RB1/AN8/C1INB/ RB1 0 O DIG LATB<1> data output. P1B/CTDIN/INT1 1 I ST PORTB<1> data input; weak pull-up when RBPU bit is cleared. AN8 1 I ANA A/D Input Channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. C1INB(1) 1 I ANA Comparator 1 Input B. P1B(1) 0 O DIG ECCP1 PWM Output B. May be configured for tri-state during Enhanced PWM shutdown events. CTDIN 1 I ST CTMU pulse delay input. INT1 1 I ST External Interrupt 1 input. RB2/CANTX/C1OUT/ RB2 0 O DIG LATB<2> data output. P1C/CTED1/INT2 1 I ST PORTB<2> data input; weak pull-up when RBPU bit is cleared. CANTX(2) 0 O DIG CAN bus TX. C1OUT(1) 0 O DIG Comparator 1 output; takes priority over port data. P1C(1) 0 O DIG ECCP1 PWM Output C. May be configured for tri-state during Enhanced PWM. CTED1 x I ST CTMU Edge 1 input. INT2 1 I ST External Interrupt 2. RB3/CANRX/ RB3 0 O DIG LATB<3> data output. C2OUT/P1D/ 1 I ST PORTB<3> data input; weak pull-up when RBPU bit is cleared. CTED2/INT3 CANRX(2) 1 I ST CAN bus RX. C2OUT(1) x I ST CTMU Edge 2 input. P1D(1) 0 O DIG ECCP1 PWM Output D. May be configured for tri-state during Enhanced PWM. CTED2 x I ST CTMU Edge 2 input. INT3 1 I ST External Interrupt 3 input. Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This pin assignment is only available for 28-pin devices (PIC18F2XK80). 2: This is the default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set. 3: This is the default pin assignment for T0CKI when the T0CKMX Configuration bit is set. 4: This is the default pin assignment for T3CKI for 28, 40 and 44-pin devices. This is the alternate pin assignment for T3CKI for 64-pin devices when T3CKMX is cleared. DS30009977G-page 172  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 11-3: PORTB FUNCTIONS (CONTINUED) TRIS Pin Name Function I/O I/O Type Description Setting RB4/AN9/C2INA/ RB4 0 O DIG LATB<4> data output. ECCP1/P1A/CTPLS/ 1 I ST PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 AN9 1 I ANA A/D Input Channel 9 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. C2INA(1) 2 I ANA Comparator 2 Input A. ECCP1(1) 0 O DIG ECCP1 compare output and ECCP1 PWM output. Takes priority over port data. 1 I ST ECCP1 capture input. P1A(1) 0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. CTPLS x O DIG CTMU pulse generator output. KBI0 1 I ST Interrupt-on-pin change. RB5/T0CKI/T3CKI/ RB5 0 O DIG LATB<5> data output. CCP5/KBI1 1 I ST PORTB<5> data input; weak pull-up when RBPU bit is cleared. T0CKI(3) x I ST Timer0 clock input. T3CKI(4) x I ST Timer3 clock input. CCP5 0 O DIG CCP5 compare/PWM output. Takes priority over port data. 1 I ST CCP5 capture input. KBI1 1 I ST Interrupt-on-pin change. RB6/PGC/TX2/CK2/ RB6 0 O DIG LATB<6> data output. KBI2 1 I ST PORTB<6> data input; weak pull-up when RBPU bit is cleared. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation. TX2(1) 0 O DIG Asynchronous serial data output (EUSARTx module); takes priority over port data. CK2(1) 0 O DIG Synchronous serial clock output (EUSARTx module); user must configure as an input. 1 I ST Synchronous serial clock input (EUSARTx module); user must configure as an input. KBI2 1 I ST Interrupt-on-pin change. RB7/PGD/T3G/RX2/ RB7 0 O DIG LATB<7> data output. DT2/KBI3 1 I ST PORTB<7> data input; weak pull-up when RBPU bit is cleared. PGD x O DIG Serial execution data output for ICSP and ICD operation. x I ST Serial execution data input for ICSP and ICD operation. T3G x I ST Timer3 external clock gate input. RX2(1) 1 I ST Asynchronous serial receive data input (EUSARTx module). DT2(1) 1 O DIG Synchronous serial data output (AUSART module); takes priority over port data. 1 I ST Synchronous serial data input (AUSART module); user must configure as an input. KBI3 1 I ST Interrupt-on-pin change. Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This pin assignment is only available for 28-pin devices (PIC18F2XK80). 2: This is the default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set. 3: This is the default pin assignment for T0CKI when the T0CKMX Configuration bit is set. 4: This is the default pin assignment for T3CKI for 28, 40 and 44-pin devices. This is the alternate pin assignment for T3CKI for 64-pin devices when T3CKMX is cleared.  2010-2017 Microchip Technology Inc. DS30009977G-page 173

PIC18F66K80 FAMILY TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD ANCON1 — ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 Legend: Shaded cells are not used by PORTB. DS30009977G-page 174  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 11.4 PORTC, TRISC and When enabling peripheral functions, use care in defin- LATC Registers ing TRIS bits for each PORTC pin. Some peripherals can override the TRIS bit to make a pin an output or PORTC is an eight-bit wide, bidirectional port. The input. Consult the corresponding peripheral section for corresponding Data Direction and Output Latch registers the correct TRIS bit settings. are TRISC and LATC. Only PORTC pins, RC2 through Note: These pins are configured as digital inputs RC7, are digital only pins. on any device Reset. PORTC is multiplexed with CCP, MSSP and EUSARTx peripheral functions (Table11-5). The pins have The contents of the TRISC register are affected by Schmitt Trigger input buffers. The pins for CCP, SPI peripheral overrides. Reading TRISC always returns and EUSARTx are also configurable for open-drain the current contents, even though a peripheral device output whenever these functions are active. may be overriding one or more of the pins. Open-drain configuration is selected by setting the SSPOD, CCPxOD and U1OD control bits in the EXAMPLE 11-3: INITIALIZING PORTC ODCON register. CLRF PORTC ; Initialize PORTC by RC1 is configurable for open-drain output when CCP2 ; clearing output is active on this pin. Open-drain configuration is ; data latches selected by setting the CCP2OD control bit CLRF LATC ; Alternate method (ODCON<3>). ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs  2010-2017 Microchip Technology Inc. DS30009977G-page 175

PIC18F66K80 FAMILY TABLE 11-5: PORTC FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RC0/SOSCO/ RC0 0 O DIG LATC<0> data output. SCLKI 1 I ST PORTC<0> data input. SOSCO 1 I ST SOSC oscillator output. SCLKI 1 I ST Digital clock input; enabled when SOSC oscillator is disabled. RC1/SOSCI RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. SOSCI x I ANA SOSC oscillator input. RC2/T1G/ RC2 0 O DIG LATC<2> data output. CCP2 1 I ST PORTC<2> data input. T1G x I ST Timer1 external clock gate input. CCP2 0 O DIG CCP2 compare/PWM output; takes priority over port data. 1 I ST CCP2 capture input. RC3/REFO/ RC3 0 O DIG LATC<3> data output. SCL/SCK 1 I ST PORTC<3> data input. REFO x O DIG Reference output clock. SCL 0 O DIG I2C™ clock output (MSSP module); takes priority over port data. 1 I I2C I2C clock input (MSSP module); input type depends on module setting. SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data. 1 I ST SPI clock input (MSSP module). RC4/SDA/SDI RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. SDA 1 O DIG I2C data output (MSSP module); takes priority over port data. 1 I I2C I2C data input (MSSP module); input type depends on module setting. SDI 1 I ST SPI data input (MSSP module). RC5/SDO RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO 0 O DIG SPI data output (MSSP module). RC6/CANTX/ RC6 0 O DIG LATC<6> data output. TX1/CK1/ 1 I ST PORTC<6> data input. CCP3 CANTX(2) 0 O DIG CAN bus TX. TX1(1) 0 O DIG Asynchronous serial data output (EUSARTx module); takes priority over port data. CK1(1) 0 O DIG Synchronous serial clock output (EUSARTx module); user must configure as an input. 1 I ST Synchronous serial clock input (EUSARTx module); user must configure as an input. CCP3 0 O DIG CCP3 compare/PWM output. Takes priority over port data. 1 I ST CCP3 capture input. Legend: O = Output; I = Input; I2C = I2C/SMBus; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: The pin assignment for 28, 40 and 44-pin devices (PIC18F2XK80 and PIC18F4XK80). 2: The alternate pin assignment for CANRX and CANTX on 28, 40 and 44-pin devices (PIC18F4XK80) when the CANMX Configuration bit is set. DS30009977G-page 176  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 11-5: PORTC FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RC7/CANRX/ RC7 0 O DIG LATC<7> data output. RX1/DT1/ 1 I ST PORTC<7> data input. CCP4 CANRX(2) 1 I ST CAN bus RX. RX1(1) 1 I ST Asynchronous serial receive data input (EUSARTx module). DT1(1) 1 O DIG Synchronous serial data output (EUSARTx module); takes priority over port data. 1 I ST Synchronous serial data input (EUSARTx module); user must configure as an input. CCP4 0 O DIG CCP4 compare/PWM output; takes priority over port data. 1 I ST CCP4 capture input. Legend: O = Output; I = Input; I2C = I2C/SMBus; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: The pin assignment for 28, 40 and 44-pin devices (PIC18F2XK80 and PIC18F4XK80). 2: The alternate pin assignment for CANRX and CANTX on 28, 40 and 44-pin devices (PIC18F4XK80) when the CANMX Configuration bit is set. TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 LATC LATC7 LATBC6 LATC5 LATCB4 LATC3 LATC2 LATC1 LATC0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD Legend: Shaded cells are not used by PORTC.  2010-2017 Microchip Technology Inc. DS30009977G-page 177

PIC18F66K80 FAMILY 11.5 PORTD, TRISD and PORTD can also be configured as an 8-bit wide micro- LATD Registers processor port (Parallel Slave Port) by setting control bit, PSPMODE (PSPCON<4>). In this mode, the input PORTD is an 8-bit wide, bidirectional port. The buffers are ST. For additional information, see corresponding Data Direction and Output Latch registers Section11.9 “Parallel Slave Port”. are TRISD and LATD. RD3 has a CTMU functionality. Note: PORTD is unavailable on 28-pin devices. EXAMPLE 11-4: INITIALIZING PORTD All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually CLRF PORTD ; Initialize PORTD by configurable as an input or output. ; clearing output ; data latches Note: These pins are configured as digital inputs CLRF LATD ; Alternate method on any device Reset. ; to clear output ; data latches Each of the PORTD pins has a weak internal pull-up. A MOVLW 0CFh ; Value used to single control bit can turn off all the pull-ups. This is ; initialize data performed by setting bit, RDPU (PADCFG1<7>). The ; direction weak pull-up is automatically turned off when the port MOVWF TRISD ; Set RD<3:0> as inputs pin is configured as an output. The pull-ups are ; RD<5:4> as outputs disabled on all device Resets. ; RD<7:6> as inputs DS30009977G-page 178  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 11-7: PORTD FUNCTIONS TRIS Pin Name Function I/O I/O Type Description Setting RD0/C1INA/ RD0 0 O DIG LATD<0> data output. PSP0 1 I ST PORTD<0> data input. C1INA 1 I ANA Comparator 1 Input A. PSP0 x I/O ST Parallel Slave Port data. RD1/C1INB/ RD1(1) 0 O DIG LATD<1> data output. PSP1 1 I ST PORTD<1> data input. C1INB(1) 1 I ANA Comparator 1 Input B. PSP1(1) x I/O ST Parallel Slave Port data. RD2/C2INA/ RD2 0 O DIG LATD<2> data output. PSP2 1 I ST PORTD<2> data input. C2INA 1 I ANA Comparator 2 Input A. PSP2 x I/O ST Parallel Slave Port data. RD3/C2INB/ RD3 0 O DIG LATD<3> data output. CTMUI/PSP3 1 I ST PORTD<3> data input. C2INB 1 I ANA Comparator 2 Input B. CTMUI x I — CTMU pulse generator charger for the C2INB comparator input. PSP3 x I/O ST Parallel Slave Port data. RD4/ECCP1/ RD4 0 O DIG LATD<4> data output. P1A/PSP4 1 I ST PORTD<4> data input. ECCP1 0 O DIG ECCP1 compare output and ECCP1 PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events; takes priority over port data. PSP4 x I/O ST Parallel Slave Port data. RD5/P1B/PSP5 RD5 0 O DIG LATD<5> data output. 1 I ST PORTD<5> data input. P1B 0 O DIG ECCP1 Enhanced PWM output, Channel B. May be configured for tri-state during Enhanced PWM shutdown events; takes priority over port data. PSP5 x I/O ST Parallel Slave Port data. RD6/TX2/CK2 RD6 0 O DIG LATD<6> data output. P1C/PSP6 1 I ST PORTD<6> data input. TX2(1) 0 O DIG Asynchronous serial data output (EUSARTx module); takes priority over port data. CK2(1) 0 O DIG Synchronous serial clock output (EUSARTx module); user must configure as an input. 1 I ST Synchronous serial clock input (EUSARTx module); user must configure as an input. P1C 0 O DIG ECCP1 Enhanced PWM output, Channel C. May be configured for tri-state during Enhanced PWM. PSP6 x I/O ST Parallel Slave Port data. Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This is the pin assignment for 40 and 44-pin devices (PIC18F4XK80).  2010-2017 Microchip Technology Inc. DS30009977G-page 179

PIC18F66K80 FAMILY TABLE 11-7: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function I/O I/O Type Description Setting RD7/RX2/DT2/ RD7 0 O DIG LATD<7> data output. P1D/PSP7 1 I ST PORTD<7> data input. RX2(1) 1 I ST Asynchronous serial receive data input (EUSARTx module). DT2(1) 1 O DIG Synchronous serial data output (EUSARTx module); takes priority over port data. 1 I ST Synchronous serial data input (EUSARTx module); user must configure as an input. P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D. May be configured for tri-state during Enhanced PWM. PSP7 x I/O ST Parallel Slave Port data. Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This is the pin assignment for 40 and 44-pin devices (PIC18F4XK80). TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 PADCFG1 RDPU(1) REPU(1) RFPU(2) RGPU(2) — — — CTMUDS ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD ANCON1 — ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 Legend: Shaded cells are not used by PORTD. Note 1: These bits are unimplemented on 28-pin devices, read as ‘0’. 2: These bits are unimplemented on 28/40/44-pin devices, read as ‘0’. DS30009977G-page 180  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 11.6 PORTE, TRISE and weak pull-up is automatically turned off when the port LATE Registers pin is configured as an output. The pull-ups are disabled on any device Reset. PORTE is a seven-bit-wide, bidirectional port. The PORTE is also multiplexed with the Parallel Slave Port corresponding Data Direction and Output Latch registers address lines. RE1 and RE0 are multiplexed with the are TRISE and LATE. Parallel Slave Port (PSP) control signals, WR and RD. Note: PORTE is unavailable on 28-pin devices. EXAMPLE 11-5: INITIALIZING PORTE All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually CLRF PORTE ; Initialize PORTE by ; clearing output configurable as an input or output. ; data latches Note: These pins are configured as digital inputs CLRF LATE ; Alternate method ; to clear output on any device Reset. ; data latches Each of the PORTE pins has a weak internal pull-up. A MOVLW 03h ; Value used to ; initialize data single control bit can turn off all the pull-ups. This is ; direction performed by clearing bit, REPU (PADCFG1<6>). The MOVWF TRISE ; Set RE<1:0> as inputs ; RE<7:2> as outputs TABLE 11-9: PORTE FUNCTIONS TRIS Pin Name Function I/O I/O Type Description Setting RE0/AN5/RD RE0 0 O DIG LATE<0> data output. 1 I ST PORTE<0> data input. AN5 1 I ANA A/D Input Channel 5. Default input configuration on POR; does not affect digital output. RD x O DIG Parallel Slave Port read strobe pin. x I ST Parallel Slave Port read pin. RE1/AN6/ RE1 0 O DIG LATE<1> data output. C1OUT/WR 1 I ST PORTE<1> data input. AN6 1 I ANA A/D Input Channel 5. Default input configuration on POR; does not affect digital output. C1OUT 0 O DIG Comparator 1 output; takes priority over port data. WR x O DIG Parallel Slave Port write strobe pin. x I ST Parallel Slave Port write pin. RE2/AN7/ RE2 0 O DIG LATE<2> data output. C2OUT/CS 1 I ST PORTE<2> data input. AN7 1 I ANA A/D Input Channel 7. Default input configuration on POR; does not affect digital output. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. CS x I ST Parallel Slave Port chip select. RE3 RE3 1 I ST PORT<3> data input. RE4/CANRX RE4(1) 0 O DIG LATE<4> data output. 1 I ST PORTE<4> data input. CANRX(1,2) 1 I ST CAN bus RX. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: These bits are unavailable for 40 and 44-pin devices (PIC18F4XK0). 2: This is the alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration bit is cleared.  2010-2017 Microchip Technology Inc. DS30009977G-page 181

PIC18F66K80 FAMILY TABLE 11-9: PORTE FUNCTIONS (CONTINUED) TRIS Pin Name Function I/O I/O Type Description Setting RE5/CANTX RE5(1) 0 O DIG LATE<5> data output. 1 I ST PORTE<5> data input. CANTX(1,2) 0 O DIG CAN bus TX. RE6/RX2/DT2 RE6(1) 0 O DIG LATE<6> data output. 1 I ST PORTE<6> data input. RX2(1) 1 I ST Asynchronous serial receive data input (EUSARTx module). DT2(1) 1 O DIG Synchronous serial data output (EUSARTx module); takes priority over port data. 1 I ST Synchronous serial data input (EUSARTx module); user must configure as an input. RE7/TX2/CK2 RE7(1) 0 O DIG LATE<7> data output. 1 I ST PORTE<7> data input. TX2(1) 0 O DIG Asynchronous serial data output (EUSARTx module); takes priority over port data. CK2(1) 0 O DIG Synchronous serial clock output (EUSARTx module); user must configure as an input. 1 I ST Synchronous serial clock input (EUSARTx module); user must config- ure as an input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: These bits are unavailable for 40 and 44-pin devices (PIC18F4XK0). 2: This is the alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration bit is cleared. TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTE RE7(1) RE6(1) RE5(1) RE4(1) RE3 RE2 RE1 RE0 LATE LATE7 LATE6 LATE5 LATE4 — LATE2 LATE1 LATE0 TRISE TRISE7 TRISE6 TRISE5 TRISE4 — TRISE2 TRISE1 TRISE0 PADCFG1 RDPU REPU RFPU(1) RGPU(1) — — — CTMUDS ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 Legend: Shaded cells are not used by PORTE. Note 1: These bits are unimplemented on 44-pin devices, read as ‘0’. DS30009977G-page 182  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 11.7 PORTF, LATF and TRISF Registers Note: On device Resets, pins, RF<7:1>, are configured as analog inputs and are read PORTF is an 8-bit wide, bidirectional port. The as ‘0’. corresponding Data Direction and Output Latch regis- ters are TRISF and LATF. All pins on PORTF are EXAMPLE 11-6: INITIALIZING PORTF implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. CLRF PORTF ; Initialize PORTF by ; clearing output Note: PORTF is only available on 64-pin devices. ; data latches CLRF LATF ; Alternate method Each of the PORTF pins has a weak internal pull-up. A ; to clear output single control bit can turn off all the pull-ups. This is ; data latches done by clearing bit, RFPU (PADCFG1<5>). The weak MOVLW 0CEh ; Value used to pull-up is automatically turned off when the port pin is ; initialize data configured as an output. The pull-ups are disabled on ; direction any device Reset. MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs TABLE 11-11: PORTF FUNCTIONS TRIS Pin Name Function I/O I/O Type Description Setting RF0/MDMIN RF0 0 O DIG LATF<0> data output. 1 I ST PORTF<0> data input. MDMIN 1 I ST Modulator source input. RF1 RF1 0 O DIG LATF<1> data output. 1 I ST PORTF<1> data input. RF2/MDCIN1 RF2 0 O DIG LATF<2> data output. 1 I ST PORTF<2> data input. MDCIN1 1 I ST Modulator Carrier Input 1. RF3 RF3 0 O DIG LATF<3> data output. 1 I ST PORTF<3> data input. RF4/MDCIN2 RF4 0 O DIG LATF<4> data output. 1 I ST PORTF<4> data input. MDCIN2 1 I ST Modulator Carrier Input 2. RF5 RF5 0 O DIG LATF<5> data output. 1 I ST PORTF<5> data input. RF6/MDOUT RF6 0 O DIG LATF<6> data output. 1 I ST PORTF<6> data input. MDOUT 0 O DIG Modulator output. RF7 RF7 0 O DIG LATF<7> data output. 1 I ST PORTF<7> data input. Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 PADCFG1 RDPU REPU RFPU(1) RGPU(1) — — — CTMUDS Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. Note 1: These bits are unimplemented on 28-pin devices, read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 183

PIC18F66K80 FAMILY 11.8 PORTG, TRISG and put, while other peripherals override the TRIS bit to LATG Registers make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS PORTG is a 5-bit wide, bidirectional port. The bit settings. The pin override value is not loaded into corresponding Data Direction and Output Latch registers the TRIS register. This allows read-modify-write of the are TRISG and LATG. TRIS register without concern due to peripheral overrides. Note: PORTG is only available on 64-pin devices. EXAMPLE 11-7: INITIALIZING PORTG PORTG is multiplexed with EUSARTx and CCP, ECCP, Analog, Comparator and Timer input functions CLRF PORTG ; Initialize PORTG by ; clearing output (Table11-13). When operating as I/O, all PORTG pins ; data latches have Schmitt Trigger input buffers. The open-drain CLRF LATG ; Alternate method functionality for the EUARTx can be configured using ; to clear output ODCON. ; data latches Each of the PORTG pins has a weak internal pull-up. A MOVLW 04h ; Value used to single control bit can turn off all the pull-ups. This is per- ; initialize data ; direction formed by clearing bit, RGPU (PADCFG1<4>). The MOVWF TRISG ; Set RG1:RG0 as weak pull-up is automatically turned off when the port ; outputs pin is configured as an output. The pull-ups are ; RG2 as input disabled on any device Reset. ; RG4:RG3 as inputs When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an out- TABLE 11-13: PORTG FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RG0/RX1/DT1 RG0 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. RX1 1 I ST Asynchronous serial receive data input (EUSARTx module). DT1 0 O DIG Synchronous serial data output (EUSARTx module); takes priority over port data. 1 I ST Synchronous serial data input (EUSARTx module); user must configure as an input. RG1/CANTX RG1 0 O DIG LATG<1> data output. 1 I ST PORTG<1> data input. CANTX 0 O DIG CAN bus TX. RG2/T3CKI RG2 0 O DIG LATG<2> data output. 1 I ST PORTG<2> data input. T3CKI(2) x I ST Timer3 clock input. RG3/TX1/CK1 RG3 0 O DIG LATG<3> data output. 1 I ST PORTG<3> data input. TX1 0 O DIG Asynchronous serial data output (EUSARTx module); takes priority over port data. CK1 0 O DIG Synchronous serial clock output (EUSARTx module); user must configure as an input. 1 I ST Synchronous serial clock input (EUSARTx module); user must configure as an input. RG4/T0CKI RG4 0 O DIG LATG<4> data output. 1 I ST PORTG<4> data input. T0CKI(1) x I ST Timer0 clock input. Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: This is the alternate pin assignment for T0CKI on 64-pin devices when the T0CKMX Configuration bit is cleared. 2: This is the default pin assignment for T3CKI on 64-pin devices when the T3CKMX Configuration bit is set. DS30009977G-page 184  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTG — — — RG4 RG3 RG2 RG1 RG0 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 PADCFG1 RDPU REPU RFPU(1) RGPU(1) — — — CTMUDS Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: These bits are unimplemented on 28-pin devices; read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 185

PIC18F66K80 FAMILY 11.9 Parallel Slave Port FIGURE 11-3: PORTD AND PORTE BLOCK DIAGRAM PORTD can function as an 8-bit-wide Parallel Slave (PARALLEL SLAVE PORT) Port (PSP), or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. The port is asyn- chronously readable and writable by the external world Data Bus through the RD control input pin (RE0/AN5/RD) and D Q WR control input pin (RE1/AN6/C1OUT/WR). RDx WR LATD Pin CK Note: The Parallel Slave Port is available only on or PORTD 40/44-pin and 64-pin devices. Data Latch ST The PSP can directly interface to an 8-bit micro- Q D processor data bus. The external microprocessor can read or write the PORTD latch as an eight-bit latch. RD PORTD ENEN TRIS Latch Setting bit, PSPMODE, enables port pin, RE0/AN5/RD, to be the RD input, RE1/AN6/C1OUT/WR to be the WR input and RD LATD RE2/AN7/C2OUT/CS to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (= 111). One bit of PORTD A write to the PSP occurs when both the CS and WR Set Interrupt Flag lines are first detected low and ends when either are PSPIF (PIR1<7>) detected high. The PSPIF and IBF flag bits (PIR1<7> and PSPCON<7>, respectively) are set when the write ends. A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit (PSPCON<6>) is set. If the user Read ST RD writes new data to PORTD to set OBF, the data is immediately read out, but the OBF bit is not set. Chip Select ST CS When either the CS or RD line is detected high, the PORTD pins return to the input state and the PSPIF bit Write is set. User applications should wait for PSPIF to be set ST WR before servicing the PSP. When this happens, the IBF Note: The I/O pin has protection diodes to VDD and VSS. and OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure11-4 and Figure11-5, respectively. DS30009977G-page 186  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 11-5: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word had not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-4: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF  2010-2017 Microchip Technology Inc. DS30009977G-page 187

PIC18F66K80 FAMILY FIGURE 11-5: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-15: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 LATE LATE7 LATE6 LATE5 LATE4 — LATE2 LATE1 LATE0 TRISE TRISE7 TRISE6 TRISE5 TRISE4 — TRISE2 TRISE1 TRISE0 PSPCON IBF OBF IBOV PSPMODE — — — — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. DS30009977G-page 188  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 12.0 DATA SIGNAL MODULATOR Using this method, the DSM can generate the following types of key modulation schemes: Note: The Data Signal Modulator is only available • Frequency-Shift Keying (FSK) on 64-pin devices (PIC18F6XK80). • Phase-Shift Keying (PSK) The Data Signal Modulator (DSM) is a peripheral which • On-Off Keying (OOK) allows the user to mix a data stream, also known as a Additionally, the following features are provided within modulator signal, with a carrier signal to produce a the DSM module: modulated output. • Carrier Synchronization Both the carrier and the modulator signals are supplied • Carrier Source Polarity Select to the DSM module, either internally from the output of a peripheral, or externally through an input pin. • Carrier Source Pin Disable • Programmable Modulator Data The modulated output signal is generated by perform- ing a logical “AND” operation of both the carrier and • Modulator Source Pin Disable modulator signals and then it is provided to the MDOUT • Modulated Output Polarity Select pin. • Slew Rate Control The carrier signal is comprised of two distinct and sepa- Figure12-1 shows a simplified block diagram of the rate signals: a carrier high (CARH) signal and a carrier Data Signal Modulator peripheral. low (CARL) signal. During the time in which the modula- tor (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal.  2010-2017 Microchip Technology Inc. DS30009977G-page 189

PIC18F66K80 FAMILY FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCH<3:0> MDEN VSS 0000 MDCIN1 0001 EN MDCIN2 0010 Data Signal REFO Clock 0011 Modulator ECCP1 0100 CCP2 0101 CARH CCP3 0110 CCP4 0111 CCP5 1000 MDCHPOL Reserved 1001 * * No Channel Selected 1111 D SYNC MDMS<3:0> Q 1 MDBIT 0000 MDMIN 0001 MSSP (SDO) 0010 0 EUSART1 (TX) 0011 EUSART2 (TX) 0100 MDCHSYNC ECCP1 0101 CCP2 0110 MOD CCP3 0111 CCP4 1000 MDOUT CCP5 1001 MDOE 1010 MDOPOL Reserved No Channel * * Selected 1111 D MDCL<3:0> SYNC Q 1 VSS 0000 MDCIN1 0001 MDCIN2 0010 REFO Clock 0011 0 ECCP1 0100 CCP2 0101 CARL MDCLSYNC CCP3 0110 CCP4 0111 CCP5 1000 1001 MDCLPOL Reserved * * No Channel Selected 1111 DS30009977G-page 190  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 12.1 DSM Operation 12.3 Carrier Signal Sources The DSM module can be enabled by setting the MDEN The carrier high signal and carrier low signal can be bit in the MDCON register. Clearing the MDEN bit in the supplied from the following sources: MDCON register, disables the DSM module by auto- • CCP1 Signal matically switching the carrier high and carrier low • CCP2 Signal signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON • CCP3 Signal register. This not only assures that the DSM module is • CCP4 Signal inactive, but that it is also consuming the least amount • Reference Clock Module Signal of current. • External Signal on MDCIN1 Pin (RF2/MDCIN1) The values used to select the carrier high, carrier low • External Signal on MDCIN2 Pin (RF4/MDCIN2) and modulator sources held by the Modulation Source, • VSS Modulation High Carrier and Modulation Low Carrier The carrier high signal is selected by configuring the Control registers are not affected when the MDEN bit is MDCH<3:0> bits in the MDCARH register. The carrier cleared, and the DSM module is disabled. The values low signal is selected by configuring the MDCL<3:0> inside these registers remain unchanged while the bits in the MDCARL register. DSM is inactive. The sources for the carrier high, carrier low and modulator signals will once again be 12.4 Carrier Synchronization selected when the MDEN bit is set and the DSM module is again enabled and active. During the time when the DSM switches between car- The modulated output signal can be disabled without rier high and carrier low signal sources, the carrier data shutting down the DSM module. The DSM module will in the modulated output signal can become truncated. remain active and continue to mix signals, but the out- To prevent this, the carrier signal can be synchronized put value will not be sent to the MDOUT pin. During the to the modulator signal. When synchronization is time that the output is disabled, the MDOUT pin will enabled, the carrier pulse that is being mixed at the remain low. The modulated output can be disabled by time of the transition is allowed to transition low before clearing the MDOE bit in the MDCON register. the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier 12.2 Modulator Signal Sources high and carrier low signal sources. Synchronization for the carrier high signal can be enabled by setting the The modulator signal can be supplied from the following MDCHSYNC bit in the MDCARH register. Synchroniza- sources: tion for the carrier low signal can be enabled by setting • ECCP1 Signal the MDCLSYNC bit in the MDCARL register. • CCP2 Signal Figure12-1 through Figure12-5 show timing diagrams • CCP3 Signal of using various synchronization methods. • CCP4 Signal • CCP5 Signal • MSSP SDO Signal (SPI mode only) • EUSART1 TX1 Signal • EUSART2 TX2 Signal • External Signal on MDMIN Pin (RF0/MDMIN) • MDBIT bit in the MDCON Register The modulator signal is selected by configuring the MDSRC<3:0> bits in the MDSRC register.  2010-2017 Microchip Technology Inc. DS30009977G-page 191

PIC18F66K80 FAMILY FIGURE 12-2: ON/OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 12-1: NO SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier CARH CARL CARH CARL State FIGURE 12-3: CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier CARH both CARL CARH both CARL State DS30009977G-page 192  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 12-4: CARRIER LOW SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier CARH CARL CARH CARL State FIGURE 12-5: FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling Edges Used to Sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH CARL CARH CARL State  2010-2017 Microchip Technology Inc. DS30009977G-page 193

PIC18F66K80 FAMILY 12.5 Carrier Source Polarity Select 12.8 Modulator Source Pin Disable The signal provided from any selected input source for The modulator source default connection to a pin can the carrier high and carrier low signals can be inverted. be disabled by setting the MDSODIS bit in the MDSRC Inverting the signal for the carrier high source is register. enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is 12.9 Modulated Output Polarity enabled by setting the MDCLPOL bit of the MDCARL The modulated output signal provided on the MDOUT register. pin can also be inverted. Inverting the modulated out- 12.6 Carrier Source Pin Disable put signal is enabled by setting the MDOPOL bit of the MDCON register. Some peripherals assert control over their correspond- ing output pin when they are enabled. For example, 12.10 Slew Rate Control when the CCP1 module is enabled, the output of CCP1 When modulated data streams of 20 MHz or greater is connected to the CCP1 pin. are required, the slew rate limitation on the output port This default connection to a pin can be disabled by pin can be disabled. The slew rate limitation can be setting the MDCHODIS bit in the MDCARH register for removed by clearing the MDSLR bit in the MDCON the carrier high source and the MDCLODIS bit in the register. MDCARL register for the carrier low source. 12.11 Operation In Sleep Mode 12.7 Programmable Modulator Data The DSM module is not affected by Sleep mode. The The MDBIT of the MDCON register can be selected as DSM can still operate during Sleep if the Carrier and the source for the modulator signal. This gives the user Modulator input sources are also still operable during the ability to program the value used for modulation. Sleep. 12.12 Effects of a Reset Upon any device Reset, the Data Signal Modulator module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. DS30009977G-page 194  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 12-1: MDCON: MODULATION CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 MDEN MDOE MDSLR MDOPOL MDO — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output is enabled 0 = Modulator pin output is disabled bit 5 MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting is enabled 0 = MDOUT pin slew rate limiting is disabled bit 4 MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted bit 3 MDO: Modulator Output bit Displays the current output value of the modulator module.(2) bit 2-1 Unimplemented: Read as ‘0’ bit 0 MDBIT: Modulator Source Input bit Allows software to manually set modulation source input to module.(1) Note 1: The MDBIT must be selected as the modulation source in the MDSRC register for this operation. 2: The modulated output frequency can be greater and asynchronous from the clock that updates this register bit. The bit value may not be valid for higher speed modulator or carrier signals.  2010-2017 Microchip Technology Inc. DS30009977G-page 195

PIC18F66K80 FAMILY REGISTER 12-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x MDSODIS — — — MDSRC3 MDSRC2 MDSRC1 MDSRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 MDSRC<3:0> Modulation Source Selection bits 1111-1010 = Reserved; no channel connected 1001 = CCP5 output (PWM Output mode only) 1000 = CCP4 output (PWM Output mode only) 0111 = CCP3 output (PWM Output mode only) 0110 = CCP2 output (PWM Output mode only) 0101 = ECCP1 output (PWM Output mode only) 0100 = EUSART2 TX output 0011 = EUSART1 TX output 0010 = MSSP SDO output 0001 = MDMIN port pin 0000 = MDBIT bit of the MDCON register is the modulation source DS30009977G-page 196  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 12-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x MDCHODIS MDCHPOL MDCHSYNC — MDCH3(1) MDCH2(1) MDCH1(1) MDCH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled bit 6 MDCHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted bit 5 MDCHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator output is not synchronized to the high time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCH<3:0> Modulator Data High Carrier Selection bits(1) 1111-1001 = Reserved 1000 = CCP5 output (PWM Output mode only) 0111 = CCP4 output (PWM Output mode only) 0110 = CCP3 output (PWM Output mode only) 0101 = CCP2 output (PWM Output mode only) 0100 = ECCP1 output (PWM Output mode only) 0011 = Reference clock module signal 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.  2010-2017 Microchip Technology Inc. DS30009977G-page 197

PIC18F66K80 FAMILY REGISTER 12-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x MDCLODIS MDCLPOL MDCLSYNC — MDCL3(1) MDCL2(1) MDCL1(1) MDCL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is enabled bit 6 MDCLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted bit 5 MDCLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator output is not synchronized to the low time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCL<3:0> Modulator Data High Carrier Selection bits(1) 1111-1001 = Reserved 1000 = CCP5 output (PWM Output mode only) 0111 = CCP4 output (PWM Output mode only) 0110 = CCP3 output (PWM Output mode only) 0101 = CCP2 output (PWM Output mode only) 0100 = ECCP1 output (PWM Output mode only) 0011 = Reference clock module signal 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH3 MDCH2 MDCH1 MDCH0 MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL3 MDCL2 MDCL1 MDCL0 MDCON MDEN MDOE MDSLR MDOPOL MDO — — MDBIT MDSRC MDSODIS — — — MDSRC3 MDSRC2 MDSRC1 MDSRC0 PMD2 — — — — MODMD ECANMD CMP2MD CMP1MD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode. DS30009977G-page 198  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 13.0 TIMER0 MODULE The T0CON register (Register13-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or Figure13-1 provides a simplified block diagram of the counter in both 8-bit or 16-bit modes Timer0 module in 8-bit mode. Figure13-2 provides a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 13-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transitions on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increments on high-to-low transition on T0CKI pin 0 = Increments on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = Timer0 prescaler is not assigned; Timer0 clock input bypasses prescaler 0 = Timer0 prescaler is assigned; Timer0 clock input comes from prescaler output bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value  2010-2017 Microchip Technology Inc. DS30009977G-page 199

PIC18F66K80 FAMILY 13.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter. The timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 13.2 Timer0 Reads and Writes in 16-Bit every clock by default unless a different prescaler value Mode is selected (see Section13.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode. It is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0, which is not directly readable nor TMR0 register. writable. (See Figure13-2.) TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising edge or falling edge of the T0CKI pin. The and low byte were valid, due to a rollover between incrementing edge is determined by the Timer0 Source successive reads of the high and low byte. Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external Similarly, a write to the high byte of Timer0 must also clock input are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 13-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI Pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) T0CS 3 8 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 13-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with TMR0 Set 1 Internal TMR0L High Byte TMR0IF T0CKI Pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS30009977G-page 200  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 13.3 Prescaler 13.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. The prescaler assignment is fully under software Its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>), which determine the prescaler execution. assignment and prescale ratio. 13.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Tim- er0 module. When it is assigned, prescale values from The TMR0 interrupt is generated when the TMR0 1:2 through 1:256, in power-of-two increments, are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (for example, CLRF TMR0, clearing the TMR0IE bit (INTCON<5>). Before MOVWF TMR0, BSF TMR0) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine Note: Writing to TMR0 when the prescaler is (ISR). assigned to Timer0 will clear the prescaler count but will not change the prescaler Since Timer0 is shutdown in Sleep mode, the TMR0 assignment. interrupt cannot awaken the processor from Sleep. TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0L Timer0 Register Low Byte TMR0H Timer0 Register High Byte INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.  2010-2017 Microchip Technology Inc. DS30009977G-page 201

PIC18F66K80 FAMILY 14.0 TIMER1 MODULE The module derives its clocking source from either the secondary oscillator or from an external digital source. The Timer1 timer/counter module incorporates these If using the secondary oscillator, there are the addi- features: tional options for low-power, high-power and external • Software selectable operation as a 16-bit timer or digital clock source. counter Timer1 is controlled through the T1CON Control • Readable and writable 8-bit registers (TMR1H register (Register14-1). It also contains the Timer1 and TMR1L) Oscillator Enable bit (SOSCEN). Timer1 can be • Selectable clock source (internal or external) with enabled or disabled by setting or clearing control bit, device clock or SOSC oscillator internal options TMR1ON (T1CON<0>). • Interrupt-on-overflow The FOSC clock source should not be used with the • Reset on ECCP Special Event Trigger ECCP capture/compare features. If the timer will be used with the capture or compare features, always • Timer with gated control select one of the other timer clocking options. Figure14-1 displays a simplified block diagram of the Timer1 module. REGISTER 14-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 10 = Timer1 clock source is either from pin or oscillator, depending on the SOSCEN bit: SOSCEN = 0: External clock is from the T1CKI pin (on the rising edge). SOSCEN = 1: Depending on the SOSCSELx Configuration bit, the clock source is either a crystal oscillator on SOSCI/SOSCO or an internal digital clock from the SCLKI pin. 01 = Timer1 clock source is the system clock (FOSC)(1) 00 = Timer1 clock source is the instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 SOSCEN: SOSC Oscillator Enable bit 1 = SOSC is enabled and available for Timer1 0 = SOSC is disabled for Timer1 The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit TMR1CS<1:0> = 10: 1 = Do not synchronize external clock input 0 = Synchronizes external clock input TMR1CS<1:0> = 0x: This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1x. Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. DS30009977G-page 202  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 14-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED) bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.  2010-2017 Microchip Technology Inc. DS30009977G-page 203

PIC18F66K80 FAMILY 14.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register14-2, is used to control the Tim- er1 gate. REGISTER 14-2: T1GCON: TIMER1 GATE CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/T1DONE T1GVAL T1GSS1 T1GSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single Pulse Mode bit 1 = Timer1 Gate Single Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single Pulse mode is disabled bit 3 T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit 1 = Timer1 gate single pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by Timer1 Gate Enable (TMR1GE) bit. bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 output 10 = Comparator 1 output 01 = TMR2 to match PR2 output 00 = Timer1 gate pin Note 1: Programming the T1GCON prior to T1CON is recommended. DS30009977G-page 204  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 14.2 Timer1 Operation 14.3.2 EXTERNAL CLOCK SOURCE The Timer1 module is an 8 or 16-bit incrementing When the external clock source is selected, the Timer1 counter that is accessed through the TMR1H:TMR1L module may work as a timer or a counter. register pair. When enabled to count, Timer1 is incremented on the When used with an internal clock source, the module is rising edge of the external clock input, T1CKI. Either of a timer and increments on every instruction cycle. these external clock sources can be synchronized to the When used with an external clock source, the module microcontroller system clock or they can run can be used as either a timer or counter. It increments asynchronously. on every selected edge of the external source. When used as a timer with a clock oscillator, an Timer1 is enabled by configuring the TMR1ON and external, 32.768 kHz crystal can be used in conjunction TMR1GE bits in the T1CON and T1GCON registers, with the dedicated internal oscillator circuit. respectively. Note: In Counter mode, a falling edge must be When SOSC is selected as Crystal mode (by the registered by the counter prior to the first SOSCSELx bits), the RC1/SOSCI and incrementing rising edge after any one or RC0/SOSCO/SCLKI pins become inputs. This means more of the following conditions: the values of TRISC<1:0> are ignored and the pins are • Timer1 is enabled after POR Reset read as ‘0’. • Write to TMR1H or TMR1L • Timer1 is disabled 14.3 Clock Source Selection • Timer1 is disabled (TMR1ON = 0) When T1CKI is high, Timer1 is enabled The TMR1CS<1:0> and SOSCEN bits of the T1CON (TMR1ON = 1) when T1CKI is low. register are used to select the clock source for Timer1. Table14-1 displays the clock source selections. 14.3.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. TABLE 14-1: TIMER1 CLOCK SOURCE SELECTION TMR1CS1 TMR1CS0 SOSCEN Clock Source 0 1 x Clock Source (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 0 0 External Clock on T1CKI Pin 1 0 1 Oscillator Circuit on SOSCI/SOSCO Pins  2010-2017 Microchip Technology Inc. DS30009977G-page 205

PIC18F66K80 FAMILY FIGURE 14-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 T1GSPM From TMR2 01 T1G_IN 0 Match PR2 0 T1GVAL D Q Data Bus From CompaOrautotpru 1t 10 SAicnqg.l eC oPnutlrsoel 1 Q1 EN RT1DGCON D Q 1 From Comparator 2 Output 11 CK Q T1GGO/T1DONE Interrupt Set TMR1ON R det TMR1GIF T1GPOL T1GTM TMR1GE Set Flag bit, TMR1ON TMR1IF, on Overflow TMR1(2) EN Synchronized TMR1H TMR1L T1CLK 0 Clock Input Q D 1 TMR1CS<1:0> T1SYNC SOSCO/SCLKI OUT(4) SOSC 10 Prescaler Synchronize(3) 1 1, 2, 4, 8 det SOSCI EN FOSC 2 0 Internal 01 Clock T1CKPS<1:0> T1CON.SOSCEN T3CON.SSOOSSCCGEON IFnOteSrCn/a4l 00 IFnOteSrCn/a2l Sleep Input SCS<1:0> = 01 Clock Clock (1) T1CKI Note 1: ST Buffer is high-speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits. DS30009977G-page 206  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 14.4 Timer1 16-Bit Read/Write Mode FIGURE 14-2: EXTERNAL COMPONENTS FOR THE SOSC Timer1 can be configured for 16-bit reads and writes. OSCILLATOR When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for C1 PIC18F66K80 the high byte of Timer1. A read from TMR1L loads the 12 pF contents of the high byte of Timer1 into the Timer1 High SOSCI Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without XTAL having to determine whether a read of the high byte, 32.768 kHz followed by a read of the low byte, has become invalid due to a rollover between reads. SOSCO C2 A write to the high byte of Timer1 must also take place 12 pF through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a Note: See the Notes with Table14-2 for additional information about capacitor selection. write occurs to TMR1L. This allows a user to write all 16 bits at once to both the high and low bytes of Timer1. TABLE 14-2: CAPACITOR SELECTION FOR The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take THE TIMER place through the Timer1 High Byte Buffer register. OSCILLATOR(2,3,4,5) Writes to TMR1H do not clear the Timer1 prescaler. Oscillator The prescaler is only cleared on writes to TMR1L. Freq. C1 C2 Type LP 32kHz 12pF(1) 12pF(1) 14.5 SOSC Oscillator An on-chip crystal oscillator circuit is incorporated Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. between pins, SOSCI (input) and SOSCO (amplifier output). It can be enabled one of these ways: 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up • Setting the SOSCEN bit in either the T1CON or time. T3CON register (TxCON<3>) 3: Since each resonator/crystal has its own • Setting the SOSCGO bit in the OSCCON2 register characteristics, the user should consult the (OSCCON2<3>) resonator/crystal manufacturer for appropriate • Setting the SCSx bits to secondary clock source in values of external components. the OSCCON register (OSCCON<1:0> = 01) 4: Capacitor values are for design guidance only. Values listed would be typical of a CL = 10 pF The SOSCGO bit is used to warm up the SOSC so that rated crystal, when SOSCSEL<1:0> = 11. it is ready before any peripheral requests it. 5: Incorrect capacitance value may result in a fre- The oscillator is a low-power circuit rated for 32 kHz quency not meeting the crystal manufacturer’s crystals. It will continue to run during all tolerance specification. power-managed modes. The circuit for a typical The SOSC crystal oscillator drive level is determined low-power oscillator is depicted in Figure14-2. based on the SOSCSELx (CONFIG1L<4:3>) Configu- Table14-2 provides the capacitor selection for the ration bits. The Higher Drive Level mode, SOSC oscillator. SOSCSEL<1:0> = 11, is intended to drive a wide The user must provide a software time delay to ensure variety of 32.768 kHz crystals with a variety of Load proper start-up of the SOSC oscillator. Capacitance (CL) ratings. The Lower Drive Level mode is highly optimized for extremely low-power consumption. It is not intended to drive all types of 32.768 kHz crystals. In the Low Drive Level mode, the crystal oscillator circuit may not work correctly if excessively large discrete capacitors are placed on the SOSCO and SOSCI pins. This mode is designed to work only with discrete capacitances of approximately 3pF-10pF on each pin. Crystal manufacturers usually specify a CL (Load Capacitance) rating for their crystals. This value is related to, but not necessarily the same as, the values that should be used for C1 and C2 in Figure14-2.  2010-2017 Microchip Technology Inc. DS30009977G-page 207

PIC18F66K80 FAMILY For more details on selecting the optimum C1 and C2 FIGURE 14-3: OSCILLATOR CIRCUIT for a given crystal, see the crystal manufacture’s appli- WITH GROUNDED cations information. The optimum value depends in GUARD RING part on the amount of parasitic capacitance in the circuit, which is often unknown. For that reason, it is VDD highly recommended that thorough testing and valida- tion of the oscillator be performed after values have VSS been selected. OSC1 14.5.1 USING SOSC AS A OSC2 CLOCKSOURCE The SOSC oscillator is also available as a clock source in power-managed modes. By setting the clock select RC0 bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device switches to SEC_RUN mode and both the CPU and RC1 peripherals are clocked from the SOSC oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE RC2 mode. Additional details are available in Section4.0 Note: Not drawn to scale. “Power-Managed Modes”. Whenever the SOSC oscillator is providing the clock In the Low Drive Level mode, SOSCSEL<1:0> = 01, it is source, the SOSC System Clock Status flag, critical that RC2 I/O pin signals be kept away from the SOSCRUN (OSCCON2<6>), is set. This can be used oscillator circuit. Configuring RC2 as a digital output, and to determine the controller’s current clocking mode. It toggling it, can potentially disturb the oscillator circuit, can also indicate the clock source currently being used even with a relatively good PCB layout. If possible, either by the Fail-Safe Clock Monitor. leave RC2 unused or use it as an input pin with a slew If the Clock Monitor is enabled and the SOSC oscillator rate limited signal source. If RC2 must be used as a fails while providing the clock, polling the SOCSRUN digital output, it may be necessary to use the Higher bit will indicate whether the clock is being provided by Drive Level Oscillator mode (SOSCSEL<1:0> =11) with the SOSC oscillator or another source. many PCB layouts. Even in the Higher Drive Level mode, careful layout 14.5.2 SOSC OSCILLATOR LAYOUT procedures should still be followed when designing the CONSIDERATIONS oscillator circuit. The SOSC oscillator circuit draws very little power In addition to dV/dt induced noise considerations, it is during operation. Due to the low-power nature of the important to ensure that the circuit board is clean. Even oscillator, it may also be sensitive to rapidly changing a very small amount of conductive, soldering flux signals in close proximity. This is especially true when residue can cause PCB leakage currents that can the oscillator is configured for extremely Low-Power overwhelm the oscillator circuit. mode, SOSCSEL<1:0> (CONFIG1L<4:3>) = 01. The oscillator circuit, displayed in Figure14-2, should 14.6 Timer1 Interrupt be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator The TMR1 register pair (TMR1H:TMR1L) increments circuit boundaries other than VSS or VDD. from 0000h to FFFFh and rolls over to 0000h. The Tim- er1 interrupt, if enabled, is generated on overflow which If a high-speed circuit must be located near the oscillator, is latched in interrupt flag bit, TMR1IF (PIR1<0>). This it may help to have a grounded guard ring around the interrupt can be enabled or disabled by setting or clear- oscillator circuit. The guard, as displayed in Figure14-3, ing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). could be used on a single-sided PCB or in addition to a ground plane. (Examples of a high-speed circuit include the ECCP1 pin, in Output Compare or PWM mode, or the primary oscillator, using the OSC2 pin.) DS30009977G-page 208  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 14.7 Resetting Timer1 Using the ECCP 14.8 Timer1 Gate Special Event Trigger Timer1 can be configured to count freely or the count can If ECCP modules are configured to use Timer1 and to be enabled and disabled using the Timer1 gate circuitry. generate a Special Event Trigger in Compare mode This is also referred to as Timer1 gate count enable. (CCP1M<3:0>=1011), this signal will reset Timer1. The Timer1 gate can also be driven by multiple selectable trigger from ECCP will also start an A/D conversion if the sources. A/D module is enabled. (For more information, see Section20.3.4 “Special Event Trigger”.) 14.8.1 TIMER1 GATE COUNT ENABLE To take advantage of this feature, the module must be The Timer1 Gate Enable mode is enabled by setting configured as either a timer or a synchronous counter. the TMR1GE bit of the T1GCON register. The polarity When used this way, the CCPR1H:CCPR1L register of the Timer1 Gate Enable mode is configured using pair effectively becomes a Period register for Timer1. the T1GPOL bit (T1GCON<6>). If Timer1 is running in Asynchronous Counter mode, When Timer1 Gate Enable mode is enabled, Timer1 this Reset operation may not work. will increment on the rising edge of the Timer1 clock In the event that a write to Timer1 coincides with a source. When Timer1 Gate Enable mode is disabled, Special Event Trigger, the write operation will take no incrementing will occur and Timer1 will hold the precedence. current count. See Figure14-4 for timing details. TABLE 14-3: TIMER1 GATE ENABLE Note: The Special Event Trigger from the ECCP SELECTIONS module will only clear the TMR1 register’s content, but not set the TMR1IF interrupt T1GPOL Timer1 flag bit (PIR1<0>). T1CLK(†) T1G Pin (T1GCON<6>) Operation  0 0 Counts  0 1 Holds Count  1 0 Holds Count  1 1 Counts † The clock on which TMR1 is running. For more information, see Figure14-1. Note: The CCP and ECCP modules use Timers, 1 through 4, for some modes. The assign- ment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRS register. For more details, see Register20-2 and Register19-2.  2010-2017 Microchip Technology Inc. DS30009977G-page 209

PIC18F66K80 FAMILY FIGURE 14-4: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 14.8.2 TIMER1 GATE SOURCE Depending on T1GPOL, Timer1 increments differently SELECTION when TMR2 matches PR2. When T1GPOL = 1, Timer1 increments for a single instruction cycle following a The Timer1 gate source can be selected from one of TMR2 match with PR2. When T1GPOL = 0, Timer1 four sources. Source selection is controlled by the increments continuously except for the cycle following T1GSSx (T1GCON<1:0>) bits (see Table14-4). the match when the gate signal goes from low-to-high. TABLE 14-4: TIMER1 GATE SOURCES 14.8.2.3 Comparator 1 Output Gate Operation T1GSS<1:0> Timer1 Gate Source The output of Comparator 1 can be internally supplied 00 Timer1 Gate Pin to the Timer1 gate circuitry. After setting up 01 TMR2 to Match PR2 Comparator1 with the CM1CON register, Timer1 will (TMR2 increments to match PR2) increment depending on the transitions of the 10 Comparator 1 Output CMP1OUT (CMSTAT<6>) bit. (comparator logic high output) 14.8.2.4 Comparator 2 Output Gate 11 Comparator 2 Output Operation (comparator logic high output) The polarity for each available source is also selectable, The output of Comparator 2 can be internally supplied controlled by the T1GPOL bit (T1GCON<6>). to the Timer1 gate circuitry. After setting up Comparator2 with the CM2CON register, Timer1 will 14.8.2.1 T1G Pin Gate Operation increment depending on the transitions of the CMP2OUT (CMSTAT<7>) bit. The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 14.8.2.2 Timer2 Match Gate Operation The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be gener- ated and internally supplied to the Timer1 gate circuitry. The pulse will remain high for one instruction cycle and will return back to a low state until the next match. DS30009977G-page 210  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 14.8.3 TIMER1 GATE TOGGLE MODE The T1GVAL bit (T1GCON<2>) indicates when the Toggled mode is active and the timer is counting. When Timer1 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer1 The Timer1 Gate Toggle mode is enabled by setting the gate signal, as opposed to the duration of a single level T1GTM bit (T1GCON<5>). When T1GTM is cleared, pulse. the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. (For timing details, see Figure14-5.) FIGURE 14-5: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8  2010-2017 Microchip Technology Inc. DS30009977G-page 211

PIC18F66K80 FAMILY 14.8.4 TIMER1 GATE SINGLE PULSE Clearing the T1GSPM bit of the T1GCON register will MODE also clear the T1GGO/T1DONE bit. (For timing details, see Figure14-6.) When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Simultaneously enabling the Toggle and Single Pulse Gate Single Pulse mode is enabled by setting the modes will permit both sections to work together. This T1GSPM bit (T1GCON<4>) and the T1GGO/T1DONE allows the cycle times on the Timer1 gate source to be bit (T1GCON<3>). The Timer1 will be fully enabled on measured. (For timing details, see Figure14-7.) the next incrementing edge. 14.8.5 TIMER1 GATE VALUE STATUS On the next trailing edge of the pulse, the T1GGO/T1DONE bit will automatically be cleared. No When the Timer1 gate value status is utilized, it is other gate events will be allowed to increment Timer1 possible to read the most current level of the gate until the T1GGO/T1DONE bit is once again set in control value. The value is stored in the T1GVAL bit software. (T1GCON<2>). This bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). FIGURE 14-6: TIMER1 GATE SINGLE PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by Hardware on T1GGO/ Set by Software Falling Edge of T1GVAL T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 DS30009977G-page 212  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 14-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by Hardware on T1GGO/ Set by Software Falling Edge of T1GVAL T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 TABLE 14-5: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP TMR1L Timer1 Register Low Byte TMR1H Timer1 Register High Byte T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 T1DONE OSCCON2 — SOSCRUN — SOSCDRV SOSCGO — MFIOFS MFIOSEL PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD Legend: Shaded cells are not used by the Timer1 module.  2010-2017 Microchip Technology Inc. DS30009977G-page 213

PIC18F66K80 FAMILY 15.0 TIMER2 MODULE The value of TMR2 is compared to that of the Period reg- ister, PR2, on each clock cycle. When the two values The Timer2 module incorporates the following features: match, the comparator generates a match signal as the • Eight-bit Timer and Period registers (TMR2 and timer output. This signal also resets the value of TMR2 PR2, respectively) to 00h on the next cycle and drives the output counter/postscaler. (See Section15.2 “Timer2 Inter- • Both registers are readable and writable rupt”.) • Software programmable prescaler (1:1, 1:4 and 1:16) The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any • Software programmable postscaler device Reset, while the PR2 register initializes at FFh. (1:1 through 1:16) Both the prescaler and postscaler counters are cleared • Interrupt on TMR2 to PR2 match on the following events: • Optional use as the shift clock for the • A write to the TMR2 register MSSP module • A write to the T2CON register The module is controlled through the T2CON register • Any device Reset – Power-on Reset (POR), (Register15-1) that enables or disables the timer, and MCLR Reset, Watchdog Timer Reset (WDTR) or configures the prescaler and postscaler. Timer2 can be Brown-out Reset (BOR) shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. TMR2 is not cleared when T2CON is written. A simplified block diagram of the module is shown in Note: The CCP and ECCP modules use Timers, Figure15-1. 1 through 4, for some modes. The assign- ment of a particular timer to a CCP/ECCP 15.1 Timer2 Operation module is determined by the Timer to CCP enable bits in the CCPTMRS register. For In normal operation, TMR2 is incremented from 00h on more details, see Register20-2 and each clock (FOSC/4). A four-bit counter/prescaler on the Register19-2. clock input gives the prescale options of direct input, divide-by-4 or divide-by-16. These are selected by the prescaler control bits, T2CKPS<1:0> (T2CON<1:0>). REGISTER 15-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off DS30009977G-page 214  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 15-1: T2CON: TIMER2 CONTROL REGISTER (CONTINUED) bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  2010-2017 Microchip Technology Inc. DS30009977G-page 215

PIC18F66K80 FAMILY 15.2 Timer2 Interrupt 15.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) provides the ECCP modules, where it is used as a time base for the input for the four-bit output counter/postscaler. This operations in PWM mode. counter generates the TMR2 match interrupt flag, which Timer2 can optionally be used as the shift clock source is latched in TMR2IF (PIR1<1>). The interrupt is enabled for the MSSP module operating in SPI mode. by setting the TMR2 Match Interrupt Enable bit, TMR2IE Additional information is provided in Section21.0 (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscaler options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 15-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP TMR2 Timer2 Register T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 PR2 Timer2 Period Register PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. DS30009977G-page 216  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 16.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure16-1. The Timer3 timer/counter modules incorporate these The Timer3 module is controlled through the T3CON features: register (Register16-1). It also selects the clock source • Software selectable operation as a 16-bit timer or options for the ECCP modules. (For more information, counter see Section20.1.1 “ECCP Module and Timer • Readable and writable eight-bit registers (TMR3H Resources”.) and TMR3L) The FOSC clock source should not be used with the • Selectable clock source (internal or external) with ECCP capture/compare features. If the timer will be device clock or SOSC oscillator internal options used with the capture or compare features, always • Interrupt-on-overflow select one of the other timer clocking options. • Module Reset on ECCP Special Event Trigger REGISTER 16-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMR3CS<1:0>: Timer3 Clock Source Select bits 10 = Timer3 clock source is either from pin or oscillator, depending on the SOSCEN bit: SOSCEN = 0: External clock is from T3CKI pin (on the rising edge). SOSCEN = 1: Depending on the SOSCSELx Configuration bit, the clock source is either a crystal oscillator on SOSCI/SOSCO or an internal digital clock from the SCLKI pin. 01 = Timerx clock source is system clock (FOSC)(1) 00 = Timerx clock source is instruction clock (FOSC/4) bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 SOSCEN: SOSC Oscillator Enable bit 1 = SOSC is enabled and available for Timer3 0 = SOSC is disabled and available for Timer3 bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS<1:0> = 10: 1 = Does not synchronize external clock input 0 = Synchronizes external clock input When TMR3CS<1:0> = 0x: This bit is ignored; Timer3 uses the internal clock. bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two eight-bit operations bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.  2010-2017 Microchip Technology Inc. DS30009977G-page 217

PIC18F66K80 FAMILY 16.1 Timer3 Gate Control Register The Timer3 Gate Control register (T3GCON), provided in Register 14-2, is used to control the Timer3 gate. REGISTER 16-2: T3GCON: TIMER3 GATE CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR3GE T3GPOL T3GTM T3GSPM T3GGO/T3DONE T3GVAL T3GSS1 T3GSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR3GE: Timer3 Gate Enable bit If TMR3ON = 0: This bit is ignored. If TMR3ON = 1: 1 = Timer3 counting is controlled by the Timer3 gate function 0 = Timer3 counts regardless of Timer3 gate function bit 6 T3GPOL: Timer3 Gate Polarity bit 1 = Timer3 gate is active-high (Timer3 counts when gate is high) 0 = Timer3 gate is active-low (Timer3 counts when gate is low) bit 5 T3GTM: Timer3 Gate Toggle Mode bit 1 = Timer3 Gate Toggle mode is enabled. 0 = Timer3 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer3 gate flip-flop toggles on every rising edge. bit 4 T3GSPM: Timerx Gate Single Pulse Mode bit 1 = Timer3 Gate Single Pulse mode is enabled and is controlling Timer3 gate 0 = Timer3 Gate Single Pulse mode is disabled bit 3 T3GGO/T3DONE: Timer3 Gate Single Pulse Acquisition Status bit 1 = Timer3 Gate Single Pulse mode acquisition is ready, waiting for an edge 0 = Timer3 Gate Single Pulse mode acquisition has completed or has not been started This bit is automatically cleared when T3GSPM is cleared. bit 2 T3GVAL: Timer3 Gate Current State bit Indicates the current state of the Timerx gate that could be provided to TMR3H:TMR3L. Unaffected by Timerx Gate Enable (TMR3GE) bit. bit 1-0 T3GSS<1:0>: Timer3 Gate Source Select bits 11 = Comparator 2 output 10 = Comparator 1 output 01 = TMR4 to match PR4 output 00 = Timer3 gate pin Watchdog Timer oscillator is turned on if TMR3GE = 1, regardless of the state of TMR3ON. Note 1: Programming the T3GCON prior to T3CON is recommended. DS30009977G-page 218  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 16-3: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 R-0 U-0 RW-1 R/W-0 U-0 R-x R/W-0 — SOSCRUN — SOSCDRV(1) SOSCGO — MFIOFS MFIOSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from a secondary SOSC 0 = System clock comes from an oscillator other than SOSC bit 5 Unimplemented: Read as ‘0’ bit 4 SOSCDRV: Secondary Oscillator Drive Control bit(1) 1 = High-power SOSC circuit selected 0 = Low/high-power select is done via the SOSCSEL<1:0> Configuration bits bit 3 SOSCGO: Oscillator Start Control bit 1 = Oscillator is running even if no other sources are requesting it 0 = Oscillator is shut off if no other sources are requesting it (When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.) bit 2 Unimplemented: Read as ‘0’ bit 1 MFIOFS: MF-INTOSC Frequency Stable bit 1 = MF-INTOSC is stable 0 = MF-INTOSC is not stable bit 0 MFIOSEL: MF-INTOSC Select bit 1 = MF-INTOSC is used in place of HF-INTOSC frequencies of 500kHz, 250kHz and 31.25kHz 0 = MF-INTOSC is not used Note 1: When SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect.  2010-2017 Microchip Technology Inc. DS30009977G-page 219

PIC18F66K80 FAMILY 16.2 Timer3 Operation The operating mode is determined by the clock select bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits Timer3 can operate in these modes: are cleared (= 00), Timer3 increments on every internal • Timer instruction cycle (FOSC/4). When TMR3CSx = 01, the • Synchronous Counter Timer3 clock source is the system clock (FOSC), and when it is ‘10’, Timer3 works as a counter from the • Asynchronous Counter external clock from the T3CKI pin (on the rising edge • Timer with Gated Control after the first falling edge) or the SOSC oscillator. FIGURE 16-1: TIMER3 BLOCK DIAGRAM T3GSS<1:0> T3G 00 T3GSPM From TMR4 01 T3G_IN 0 Match PR4 0 T3GVAL D Q Data Bus FOruotmpu Ctomparator 1 10 D Q 1 SAicnqg.l eC oPnutlrsoel 1 Q1 EN RT3DGCON From Comparator 2 Output 11 CK Q T3GGO/T3DONE Interrupt Set TMR3ON R det TMR3GIF T3GPOL T3GTM TMR3GE Set Flag bit, TMR3ON TMR3IF, on Overflow TMR3(2) EN Synchronized TMR3H TMR3L T3CLK 0 Clock Input Q D 1 TMR3CS<1:0> T3SYNC SOSCO/SCLKI OUT(4) SOSC Prescaler Synchronize(3) 1 1, 2, 4, 8 det SOSCI EN 10 2 0 FOSC T3CKPS<1:0> T1CON.SOSCEN Internal 01 T3CON.SSOOSSCCGEON Clock IFnOteSrCn/a2l Sleep Input SCS<1:0> = 01 FOSC/4 Clock Internal 00 (1) Clock T3CKI Note 1: ST Buffer is high-speed type when using T3CKI. 2: Timer3 registers increment on rising edge. 3: Synchronization does not operate while in Sleep. 4: The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits. DS30009977G-page 220  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 16.3 Timer3 16-Bit Read/Write Mode 16.4 Using the SOSC Oscillator as the Timer3 Clock Source Timer3 can be configured for 16-bit reads and writes (see Figure16.3). When the RD16 control bit The SOSC internal oscillator may be used as the clock (T3CON<1>) is set, the address for TMR3H is mapped source for Timer3. It can be enabled in one of these to a buffer register for the high byte of Timer3. A read ways: from TMR3L will load the contents of the high byte of • Setting the SOSCEN bit in either the T1CON or Timer3 into the Timer3 High Byte Buffer register. This T3CON register (TxCON<3>) provides users with the ability to accurately read all • Setting the SOSCGO bit in the OSCCON2 register 16bits of Timer3 without having to determine whether a read of the high byte, followed by a read of the low byte, (OSCCON2<3>) has become invalid due to a rollover between reads. • Setting the SCSx bits to secondary clock source in the OSCCON register (OSCCON<1:0> = 01) A write to the high byte of Timer3 must also take place through the TMR3H Buffer register. The Timer3 high The SOSCGO bit is used to warm up the SOSC so that byte is updated with the contents of TMR3H when a it is ready before any peripheral requests it. write occurs to TMR3L. This allows users to write all To use it as the Timer3 clock source, the TMR3CSx bits 16bits to both the high and low bytes of Timer3 at once. must also be set. As previously noted, this also config- The high byte of Timer3 is not directly readable or ures Timer3 to increment on every rising edge of the writable in this mode. All reads and writes must take oscillator source. place through the Timer3 High Byte Buffer register. The SOSC oscillator is described in Section14.5 Writes to TMR3H do not clear the Timer3 prescaler. “SOSC Oscillator”. The prescaler is only cleared on writes to TMR3L.  2010-2017 Microchip Technology Inc. DS30009977G-page 221

PIC18F66K80 FAMILY 16.5 Timer3 Gates TABLE 16-1: TIMER3 GATE ENABLE SELECTIONS Timer3 can be configured to count freely or the count can be enabled and disabled using the Timer3 gate T3CLK(†) T3GPOL T3G Pin Timer3 circuitry. This is also referred to as the Timer3 gate (T3GCON<6>) Operation count enable.  0 0 Counts The Timer3 gate can also be driven by multiple  0 1 Holds Count selectable sources.  1 0 Holds Count 16.5.1 TIMER3 GATE COUNT ENABLE  1 1 Counts The Timer3 Gate Enable mode is enabled by setting † The clock on which TMR3 is running. For more the TMR3GE bit (TxGCON<7>). The polarity of the information, see T3CLK in Figure16-1. Timer3 Gate Enable mode is configured using the T3GPOL bit (T3GCON<6>). When Timer3 Gate Enable mode is enabled, Timer3 will increment on the rising edge of the Timer3 clock source. When Timer3 Gate Enable mode is disabled, no incre- menting will occur and Timer3 will hold the current count. See Figure16-2 for timing details. FIGURE 16-2: TIMER3 GATE COUNT ENABLE MODE TMR3GE T3GPOL T3G_IN T3CKI T3GVAL Timer3 N N + 1 N + 2 N + 3 N + 4 DS30009977G-page 222  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 16.5.2 TIMER3 GATE SOURCE TMR4 match with PR4. When T3GPOL = 0, Timer3 SELECTION increments continuously, except for the cycle following the match, when the gate signal goes from low-to-high. The Timer3 gate source can be selected from one of four different sources. Source selection is controlled by 16.5.2.3 Comparator 1 Output Gate the T3GSS<1:0> bits (T3GCON<1:0>). The polarity for Operation each available source is also selectable and is controlled by the T3GPOL bit (T3GCON<6>). The output of Comparator 1 can be internally supplied to the Timer3 gate circuitry. After setting up TABLE 16-2: TIMER3 GATE SOURCES Comparator1 with the CM1CON register, Timer3 will increment depending on the transitions of the T3GSS<1:0> Timer3 Gate Source CMP1OUT (CMSTAT<6>) bit. 00 Timerx Gate Pin 16.5.2.4 Comparator 2 Output Gate 01 TMR4 to Match PR4 Operation (TMR4 increments to match PR4) The output of Comparator 2 can be internally supplied 10 Comparator 1 Output to the Timer3 gate circuitry. After setting up (comparator logic high output) Comparator2 with the CM2CON register, Timer3 will 11 Comparator 2 Output increment depending on the transitions of the (comparator logic high output) CMP2OUT (CMSTAT<7>) bit. 16.5.2.1 T3G Pin Gate Operation 16.5.3 TIMER3 GATE TOGGLE MODE The T3G pin is one source for Timer3 gate control. It can When Timer3 Gate Toggle mode is enabled, it is be used to supply an external source to the Timerx gate possible to measure the full cycle length of a Timer3 circuitry. gate signal, as opposed to the duration of a single level pulse. 16.5.2.2 Timer4 Match Gate Operation The Timer3 gate source is routed through a flip-flop that The TMR4 register will increment until it matches the changes state on every incrementing edge of the value in the PR4 register. On the very next increment signal. (For timing details, see Figure16-3.) cycle, TMR4 will be reset to 00h. When this Reset The T3GVAL bit will indicate when the Toggled mode is occurs, a low-to-high pulse will automatically be gener- active and the timer is counting. ated and internally supplied to the Timerx gate circuitry. The pulse will remain high for one instruction cycle and Timer3 Gate Toggle mode is enabled by setting the will return back to a low state until the next match. T3GTM bit (T3GCON<5>). When the T3GTM bit is cleared, the flip-flop is cleared and held clear. This is Depending on T3GPOL, Timerx increments differently necessary in order to control which edge is measured. when TMR4 matches PR4. When T3GPOL=1, Timer3 increments for a single instruction cycle following a FIGURE 16-3: TIMER3 GATE TOGGLE MODE TMR3GE T3GPOL T3GTM T3G_IN T3CKI T3GVAL Timer3 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8  2010-2017 Microchip Technology Inc. DS30009977G-page 223

PIC18F66K80 FAMILY 16.5.4 TIMER3 GATE SINGLE PULSE other gate events will be allowed to increment Timer3 MODE until the T3GGO/T3DONE bit is once again set in software. When Timer3 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer3 Clearing the T3GSPM bit will also clear the Gate Single Pulse mode is first enabled by setting the T3GGO/T3DONE bit. (For timing details, see T3GSPM bit (T3GCON<4>). Next, the Figure16-4.) T3GGO/T3DONE bit (T3GCON<3>) must be set. Simultaneously enabling the Toggle mode and the The Timer3 will be fully enabled on the next increment- Single Pulse mode will permit both sections to work ing edge. On the next trailing edge of the pulse, the together. This allows the cycle times on the Timer3 gate T3GGO/T3DONE bit will automatically be cleared. No source to be measured. (For timing details, see Figure16-5.) FIGURE 16-4: TIMER3 GATE SINGLE PULSE MODE TMR3GE T3GPOL T3GSPM Cleared by Hardware on T3GGO/ Set by Software Falling Edge of T3GVAL T3DONE Counting Enabled on Rising Edge of T3G T3G_IN T3CKI T3GVAL Timer3 N N + 1 N + 2 Cleared by TMR3GIF Cleared by Software Set by Hardware on Software Falling Edge of T3GVAL DS30009977G-page 224  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 16-5: TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR3GE T3GPOL T3GSPM T3GTM Cleared by Hardware on T3GGO/ Set by Software Falling Edge of T3GVAL T3DONE Counting Enabled on Rising Edge of T3G T3G_IN T3CKI T3GVAL Timer3 N N + 1 N + 2 N + 3 N + 4 Set by Hardware on Cleared by TMR3GIF Cleared by Software Falling Edge of T3GVAL Software 16.5.5 TIMER3 GATE VALUE STATUS 16.5.6 TIMER3 GATE EVENT INTERRUPT When Timer3 gate value status is utilized, it is possible When the Timer3 gate event interrupt is enabled, it is to read the most current level of the gate control value. possible to generate an interrupt upon the completion The value is stored in the T3GVAL bit (T3GCON<2>). of a gate event. When the falling edge of T3GVAL The T3GVAL bit is valid even when the Timer3 gate is occurs, the TMR3GIF flag bit in the PIR2 register will be not enabled (TMR3GE bit is cleared). set. If the TMR3GIE bit in the PIE2 register is set, then an interrupt will be recognized. The TMR3GIF flag bit operates even when the Timer3 gate is not enabled (TMR3GE bit is cleared).  2010-2017 Microchip Technology Inc. DS30009977G-page 225

PIC18F66K80 FAMILY 16.6 Timer3 Interrupt The module must be configured as either a timer or synchronous counter to take advantage of this feature. The TMR3 register pair (TMR3H:TMR3L) increments When used this way, the CCPR3H:CCPR3L register from 0000h to FFFFh and overflows to 0000h. The pair effectively becomes a Period register for Timer3. Timer3 interrupt, if enabled, is generated on overflow If Timer3 is running in Asynchronous Counter mode, and is latched in the interrupt flag bit, TMR3IF. the Reset operation may not work. Table16-3 gives each module’s flag bit. In the event that a write to Timer3 coincides with a This interrupt can be enabled or disabled by setting or Special Event Trigger from an ECCP module, the write clearing the TMR3IE bit. Table16-3 displays each will take precedence. module’s enable bit. Note: The Special Event Triggers from the ECCPx module will only clear the TMR3 16.7 Resetting Timer3 Using the ECCP register’s content, but not set the TMR3IF Special Event Trigger interrupt flag bit (PIR2<1>). If the ECCP modules are configured to use Timer3 and to generate a Special Event Trigger in Compare mode Note: The CCP and ECCP modules use Timers, (CCP3M<3:0>=1011), this signal will reset Timer3. 1 through 4, for some modes. The assign- The trigger from ECCP will also start an A/D conversion ment of a particular timer to a CCP/ECCP if the A/D module is enabled (For more information, see module is determined by the Timer to CCP Section20.3.4 “Special Event Trigger”.) enable bits in the CCPTMRS register. For more details, see Register20-2 and Register19-2. TABLE 16-3: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR5 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF PIE5 IRXIE WAKIE ERRIE TX2BIE TXB1IE TXB0IE RXB1IE RXB0IE PIR2 OSCFIF — — — BCLIF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — — — BCLIE HLVDIE TMR3IE TMR3GIE TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 T3DONE T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON OSCCON2 — SOSCRUN — SOSCDRV SOSCGO — MFIOFS MFIOSEL PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. DS30009977G-page 226  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 17.0 TIMER4 MODULES TMR4 goes through a four-bit postscaler (that gives a 1:1 to 1:16 inclusive scaling) to generate a TMR4 The Timer4 timer modules have the following features: interrupt, latched in the flag bit, TMR4IF. Table17-1 • Eight-bit Timer register (TMR4) gives each module’s flag bit. • Eight-bit Period register (PR4) The interrupt can be enabled or disabled by setting or • Readable and writable (all registers) clearing the Timer4 Interrupt Enable bit (TMR4IE), shown in Table17-1. • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) The prescaler and postscaler counters are cleared when any of the following occurs: • Interrupt on TMR4 match of PR4 • A write to the TMR4 register The Timer4 modules have a control register shown in Register17-1. Timer4 can be shut off by clearing • A write to the T4CON register control bit, TMR4ON (T4CON<2>), to minimize power • Any device Reset – Power-on Reset (POR), consumption. The prescaler and postscaler selection of MCLR Reset, Watchdog Timer Reset (WDTR) or Timer4 also are controlled by this register. Figure17-1 Brown-out Reset (BOR) is a simplified block diagram of the Timer4 modules. A TMR4 is not cleared when a T4CON is written. 17.1 Timer4 Operation Note: The CCP and ECCP modules use Timers, 1 through 4, for some modes. The assign- Timer4 can be used as the PWM time base for the ment of a particular timer to a CCP/ECCP PWM mode of the ECCP modules. The TMR4 registers module is determined by the Timer to CCP are readable and writable, and are cleared on any enable bits in the CCPTMRS register. For device Reset. The input clock (FOSC/4) has a prescale more details, see Register20-2 and option of 1:1, 1:4 or 1:16, selected by control bits, Register19-2. T4CKPS<1:0> (T4CON<1:0>). The match output of REGISTER 17-1: T4CON: TIMER4 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  2010-2017 Microchip Technology Inc. DS30009977G-page 227

PIC18F66K80 FAMILY 17.2 Timer4 Interrupt 17.3 Output of TMR4 The Timer4 module has an eight-bit Period register, The outputs of TMR4 (before the postscaler) are used PR4, that is both readable and writable. Timer4 incre- only as a PWM time base for the ECCP modules. They ment from 00h until it matches PR4 and then resets to are not used as baud rate clocks for the MSSP module 00h on the next increment cycle. The PR4 register is as is the Timer2 output. initialized to FFh upon Reset. FIGURE 17-1: TIMER4 BLOCK DIAGRAM 4 1:1 to 1:16 T4OUTPS<3:0> Set TMR4IF Postscaler 2 T4CKPS<1:0> TMR4 Output (to PWM) TMRx/PRx Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR4 Comparator PR4 Prescaler 8 8 8 Internal Data Bus TABLE 17-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE TMR4 Timer4 Register T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 PR4 Timer4 Period Register PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module. DS30009977G-page 228  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 18.0 CHARGE TIME • Control of edge sequence MEASUREMENT UNIT (CTMU) • Control of response to edges • Time measurement resolution of 1nanosecond The Charge Time Measurement Unit (CTMU) is a • High-precision time measurement flexible analog module that provides accurate differen- • Time delay of external or internal signal tial time measurement between pulse sources, as well asynchronous to system clock as asynchronous pulse generation. By working with other on-chip analog modules, the CTMU can precisely • Accurate current source suitable for capacitive measure time, capacitance and relative changes in measurement capacitance or generate output pulses with a specific The CTMU works in conjunction with the A/D Converter time delay. The CTMU is ideal for interfacing with to provide up to 11 channels for time or charge capacitive-based sensors. measurement, depending on the specific device and The module includes these key features: the number of A/D channels available. When config- ured for time delay, the CTMU is connected to one of • Up to 11 channels available for capacitive or time the analog comparators. The level-sensitive input edge measurement input sources can be selected from four sources: two • Low-cost temperature measurement using on-chip external inputs or the ECCP1/CCP2 Special Event diode channel Triggers. • On-chip precision current source The CTMU special event can trigger the Analog-to-Digital • Four-edge input trigger sources Converter module. • Polarity control for each edge source Figure18-1 provides a block diagram of the CTMU. FIGURE 18-1: CTMU BLOCK DIAGRAM CTMUCONH:CTMUCONL CTMUICON EDGEN EDGSEQEN EDG1SEL<1:0> ITRIM<5:0> TGEN EDG1POL IRNG<1:0> IDISSEN EDG2SEL<1:0> EDG1STAT CTTRIG Current Source EDG2POL EDG2STAT CTED1 Edge CTMU Control Control A/D Trigger CTED2 Logic Current Logic Control CCP2 Pulse CTPLS ECCP1 Generator A/D Converter Comparator 2 Input Comparator 2 Output  2010-2017 Microchip Technology Inc. DS30009977G-page 229

PIC18F66K80 FAMILY 18.1 CTMU Registers The CTMUCONH and CTMUCONL registers (Register18-1 and Register18-2) contain control bits The control registers for the CTMU are: for configuring the CTMU module edge source selec- • CTMUCONH tion, edge source polarity selection, edge sequencing, • CTMUCONL A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register18-3) has • CTMUICON bits for selecting the current source range and current source trim. REGISTER 18-1: CTMUCONH: CTMU CONTROL HIGH REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 4 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 3 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 2 ESGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 1 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 0 CTTRIG: CTMU Special Event Trigger bit 1 = CTMU Special Event Trigger is enabled 0 = CTMU Special Event Trigger is disabled DS30009977G-page 230  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 18-2: CTMUCONL: CTMU CONTROL LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = CCP2 Special Event Trigger bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = ECCP1 Special Event Trigger 00 = CCP2 Special Event Trigger bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred  2010-2017 Microchip Technology Inc. DS30009977G-page 231

PIC18F66K80 FAMILY REGISTER 18-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change (+62% typ.) from nominal current 011110 . . . 000001 = Minimum positive change (+2% typ.) from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change (-2% typ.) from nominal current . . . 100010 100001 = Maximum negative change (-62% typ.) from nominal current bit 1-0 IRNG<1:0>: Current Source Range Select bits 11 = 100 x Base Current 10 = 10 x Base Current 01 = Base Current level (0.55A nominal) 00 = Current source is disabled DS30009977G-page 232  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 18.2 CTMU Operation Current trim is provided by the ITRIM<5:0> bits (CTMUICON<7:2>). These six bits allow trimming of The CTMU works by using a fixed current source to the current source in steps of approximately 2% per charge a circuit. The type of circuit depends on the type step. Half of the range adjusts the current source posi- of measurement being made. tively and the other half reduces the current source. A In the case of charge measurement, the current is fixed value of ‘000000’ is the neutral position (no change). A and the amount of time the current is applied to the cir- value of ‘100001’ is the maximum negative adjustment cuit is fixed. The amount of voltage read by the A/D (approximately -62%) and ‘011111’ is the maximum becomes a measurement of the circuit’s capacitance. positive adjustment (approximately +62%). In the case of time measurement, the current, as well 18.2.3 EDGE SELECTION AND CONTROL as the capacitance of the circuit, is fixed. In this case, the voltage read by the A/D is representative of the CTMU measurements are controlled by edge events amount of time elapsed from the time the current occurring on the module’s two input channels. Each source starts and stops charging the circuit. channel, referred to as Edge 1 and Edge 2, can be con- If the CTMU is being used as a time delay, both capaci- figured to receive input pulses from one of the edge tance and current source are fixed, as well as the voltage input pins (CTED1 and CTED2) or CCPx Special Event supplied to the comparator circuit. The delay of a signal Triggers (ECCP1 and CCP2). The input channels are is determined by the amount of time it takes the voltage level-sensitive, responding to the instantaneous level to charge to the comparator threshold voltage. on the channel rather than a transition between levels. The inputs are selected using the EDG1SEL and 18.2.1 THEORY OF OPERATION EDG2SEL bit pairs (CTMUCONL<3:2>, 6:5>). The operation of the CTMU is based on the equation In addition to source, each channel can be configured for for charge: event polarity using the EDGE2POL and EDGE1POL dV bits (CTMUCONL<7,4>). The input channels can also I = C • dT be filtered for an edge event sequence (Edge 1 occur- ring before Edge 2) by setting the EDGSEQEN bit More simply, the amount of charge measured in (CTMUCONH<2>). coulombs in a circuit is defined as current in amperes 18.2.4 EDGE STATUS (I) multiplied by the amount of time in seconds that the current flows (t). Charge is also defined as the capaci- The CTMUCONL register also contains two status bits, tance in farads (C) multiplied by the voltage of the EDG2STAT and EDG1STAT (CTMUCONL<1:0>). circuit (V). It follows that: Their primary function is to show if an edge response has occurred on the corresponding channel. The I • t = C • V CTMU automatically sets a particular bit when an edge response is detected on its channel. The level-sensitive The CTMU module provides a constant, known current nature of the input channels also means that the status source. The A/D Converter is used to measure (V) in bits become set immediately if the channel’s configura- the equation, leaving two unknowns: capacitance (C) tion is changed and matches the channel’s current and time (t). The above equation can be used to calcu- state. late capacitance or time, by either the relationship using the known fixed capacitance of the circuit: The module uses the edge status bits to control the cur- rent source output to external analog modules (such as t = (C • V)/I the A/D Converter). Current is only supplied to external modules when only one (not both) of the status bits is or by: set. Current is shut off when both bits are either set or C = (I • t)/V cleared. This allows the CTMU to measure current only during the interval between edges. After both status using a fixed time that the current source is applied to bits are set, it is necessary to clear them before another the circuit. measurement is taken. Both bits should be cleared simultaneously, if possible, to avoid re-enabling the 18.2.2 CURRENT SOURCE CTMU current source. At the heart of the CTMU is a precision current source, In addition to being set by the CTMU hardware, the designed to provide a constant reference for measure- edge status bits can also be set by software. This per- ments. The level of current is user-selectable across mits a user application to manually enable or disable three ranges, or a total of two orders of magnitude, with the current source. Setting either (but not both) of the the ability to trim the output in ±2% increments bits enables the current source. Setting or clearing both (nominal). The current range is selected by the bits at once disables the source. IRNG<1:0> bits (CTMUICON<1:0>), with a value of ‘01’ representing the lowest range.  2010-2017 Microchip Technology Inc. DS30009977G-page 233

PIC18F66K80 FAMILY 18.2.5 INTERRUPTS Depending on the type of measurement or pulse generation being performed, one or more additional The CTMU sets its interrupt flag (PIR3<3>) whenever modules may also need to be initialized and configured the current source is enabled, then disabled. An inter- with the CTMU module: rupt is generated only if the corresponding interrupt enable bit (PIE3<3>) is also set. If edge sequencing is • Edge Source Generation: In addition to the not enabled (i.e., Edge 1 must occur before Edge 2), it external edge input pins, ECCP1/CCP2 Special is necessary to monitor the edge status bits and Event Triggers can be used as edge sources for determine which edge occurred last and caused the the CTMU. interrupt. • Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the 18.3 CTMU Module Initialization voltage across a capacitor that is connected to one of the analog input channels. The following sequence is a general guideline used to • Pulse Generation: When generating system clock initialize the CTMU module: independent, output pulses, the CTMU module 1. Select the current source range using the uses Comparator 2 and the associated IRNGx bits (CTMUICON<1:0>). comparator voltage reference. 2. Adjust the current source trim using the ITRIMx bits (CTMUICON<7:2>). 18.4 Calibrating the CTMU Module 3. Configure the edge input sources for Edge 1 and The CTMU requires calibration for precise measure- Edge 2 by setting the EDG1SEL and EDG2SEL ments of capacitance and time, as well as for accurate bits (CTMUCONL<3:2> and <6:5>, respectively). time delay. If the application only requires measurement 4. Configure the input polarities for the edge inputs of a relative change in capacitance or time, calibration is using the EDG1POL and EDG2POL bits usually not necessary. An example of a less precise (CTMUCONL<4,7>). application is a capacitive touch switch, in which the The default configuration is for negative edge touch circuit has a baseline capacitance and the added polarity (high-to-low transitions). capacitance of the human body changes the overall capacitance of a circuit. 5. Enable edge sequencing using the EDGSEQEN bit (CTMUCONH<2>). If actual capacitance or time measurement is required, two hardware calibrations must take place: By default, edge sequencing is disabled. • The current source needs calibration to set it to a 6. Select the operating mode (Measurement or Time precise current. Delay) with the TGEN bit (CTMUCONH<4>). • The circuit being measured needs calibration to The default mode is Time/Capacitance measure or nullify any capacitance other than that Measurement. to be measured. 7. Configure the module to automatically trigger an A/D conversion when the second edge 18.4.1 CURRENT SOURCE CALIBRATION event has occurred using the CTTRIG bit The current source on board the CTMU module has a (CTMUCONH<0>). range of ±62% nominal for each of three current The conversion trigger is disabled by default. ranges. For precise measurements, it is possible to measure and adjust this current source by placing a 8. Discharge the connected circuit by setting the IDISSEN bit (CTMUCONH<1>). high-precision resistor, RCAL, onto an unused analog channel. An example circuit is shown in Figure18-2. 9. After waiting a sufficient time for the circuit to discharge, clear the IDISSEN bit. To measure the current source: 10. Disable the module by clearing the CTMUEN bit 1. Initialize the A/D Converter. (CTMUCONH<7>). 2. Initialize the CTMU. 11. Clear the Edge Status bits, EDG2STAT and 3. Enable the current source by setting EDG1STAT EDG1STAT (CTMUCONL<1:0>). (CTMUCONL<0>). Both bits should be cleared simultaneously, if 4. Issue time delay for voltage across RCAL to possible, to avoid re-enabling the CTMU current stabilize and A/D sample/hold capacitor to charge. source. 5. Perform the A/D conversion. 12. Enable both edge inputs by setting the EDGEN 6. Calculate the current source current using bit (CTMUCONH<3>). I=V/RCAL, where RCAL is a high-precision 13. Enable the module by setting the CTMUEN bit. resistance and V is measured by performing an A/D conversion. DS30009977G-page 234  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY The CTMU current source may be trimmed with the A value of 70% of full-scale voltage is chosen to make trim bits in CTMUICON, using an iterative process to sure that the A/D Converter is in a range that is well get the exact current desired. Alternatively, the nominal above the noise floor. If an exact current is chosen to value without adjustment may be used. That value may incorporate the trimming bits from CTMUICON, the be stored by software, for use in all subsequent resistor value of RCAL may need to be adjusted accord- capacitive or time measurements. ingly. RCAL also may be adjusted to allow for available To calculate the optimal value for RCAL, the nominal resistor values. RCAL should be of the highest precision available, in light of the precision needed for the circuit current must be chosen. that the CTMU will be measuring. A recommended For example, if the A/D Converter reference voltage is minimum would be 0.1% tolerance. 3.3V, use 70% of full scale (or 2.31V) as the desired The following examples show a typical method for approximate voltage to be read by the A/D Converter. If performing a CTMU current calibration. the range of the CTMU current source is selected to be 0.55 A, the resistor value needed is calculated as • Example18-1 demonstrates how to initialize the RCAL=2.31V/0.55A, for a value of 4.2MΩ. Similarly, A/D Converter and the CTMU. if the current source is chosen to be 5.5A, RCAL would This routine is typical for applications using both be 420,000Ω, and 42,000Ω if the current source is set modules. to 55A. • Example18-2 demonstrates one method for the actual calibration routine. FIGURE 18-2: CTMU CURRENT SOURCE CALIBRATION CIRCUIT This method manually triggers the A/D Converter to demonstrate the entire step-wise process. It is also PIC18F66K80 possible to automatically trigger the conversion by setting the CTMU’s CTTRIG bit (CTMUCONH<0>). CTMU Current Source A/D Trigger A/D Converter ANx A/D RCAL MUX  2010-2017 Microchip Technology Inc. DS30009977G-page 235

PIC18F66K80 FAMILY EXAMPLE 18-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.h" /**************************************************************************/ /*Setup CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCON - CTMU Control register CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0x90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, // Set Edge status bits to zero //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Setup AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configured AN2 as an analog channel // ANCON1 ANCON1 = 0x04; // ADCON1 ADCON2bits.ADFM=1; // Result format 1= Right justified ADCON2bits.ACQT=1; // Acquisition time 7 = 20TAD 2 = 4TAD 1=2TAD ADCON2bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32 // ADCON1 ADCON1bits.VCFG0 =0; // Vref+ = AVdd ADCON1bits.VCFG1 =0; // Vref+ = AVdd ADCON1bits.VNCFG = 0; // Vref- = AVss ADCON1bits.CHS=2; // Select ADC channel ADCON0bits.ADON=1; // Turn on ADC } DS30009977G-page 236  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY EXAMPLE 18-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; double VTot = 0; float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA }  2010-2017 Microchip Technology Inc. DS30009977G-page 237

PIC18F66K80 FAMILY 18.4.2 CAPACITANCE CALIBRATION This measured value is then stored and used for calculations of time measurement or subtracted for There is a small amount of capacitance from the inter- capacitance measurement. For calibration, it is nal A/D Converter sample capacitor as well as stray expected that the capacitance of CSTRAY+CAD is capacitance from the circuit board traces and pads that approximately known; CAD is approximately 4pF. affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by An iterative process may be required to adjust the time, making sure the desired capacitance to be measured t, that the circuit is charged to obtain a reasonable volt- has been removed. age reading from the A/D Converter. The value of t may be determined by setting COFFSET to a theoretical value After removing the capacitance to be measured: and solving for t. For example, if CSTRAY is theoretically 1. Initialize the A/D Converter and the CTMU. calculated to be 11pF, and V is expected to be 70% of 2. Set EDG1STAT (=1). VDD or 2.31V, t would be: 3. Wait for a fixed delay of time, t. (4 pF + 11 pF) • 2.31V/0.55 A 4. Clear EDG1STAT. 5. Perform an A/D conversion. or 63s. 6. Calculate the stray and A/D sample capacitances: See Example18-3 for a typical routine for CTMU COFFSET = CSTRAY + CAD = (I • t)/V capacitance calibration. Where: • I is known from the current source measurement step • t is a fixed delay • V is measured by performing an A/D conversion DS30009977G-page 238  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY EXAMPLE 18-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 25 //@ 8MHz INTFRC = 62.5 us. #define ETIME COUNT*2.5 //time in uS #define DELAY for(i=0;i<COUNT;i++) #define ADSCALE 1023 //for unsigned conversion 10 sig bits #define ADREF 3.3 //Vdd connected to A/D Vr+ #define RCAL .027 //R value is 4200000 (4.2M) //scaled so that result is in //1/100th of uA int main(void) { int i; int j = 0; //index for loop unsigned int Vread = 0; float CTMUISrc, CTMUCap, Vavg, VTot, Vcal; //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU for(j=0;j<10;j++) { CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag VTot += Vread; //Add the reading to the total } Vavg = (float)(VTot/10.000); //Average of 10 readings Vcal = (float)(Vavg/ADSCALE*ADREF); CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA CTMUCap = (CTMUISrc*ETIME/Vcal)/100; }  2010-2017 Microchip Technology Inc. DS30009977G-page 239

PIC18F66K80 FAMILY 18.5 Measuring Capacitance with the 18.5.2 CAPACITIVE TOUCH SENSE USING CTMU RELATIVE CHARGE MEASUREMENT There are two ways to measure capacitance with the Not all applications require precise capacitance CTMU. The absolute method measures the actual measurements. When detecting a valid press of a capacitance value. The relative method only measures for any change in the capacitance. capacitance-based switch, only a relative change of capacitance needs to be detected. 18.5.1 ABSOLUTE CAPACITANCE In such an application, when the switch is open (or not MEASUREMENT touched), the total capacitance is the capacitance of the For absolute capacitance measurements, both the combination of the board traces, the A/D Converter and current and capacitance calibration steps found in other elements. A larger voltage will be measured by the Section 18.4 “Calibrating the CTMU Module” should A/D Converter. When the switch is closed (or touched), be followed. the total capacitance is larger due to the addition of the capacitance of the human body to the above listed To perform these measurements: capacitances and a smaller voltage will be measured by 1. Initialize the A/D Converter. the A/D Converter. 2. Initialize the CTMU. To detect capacitance changes simply: 3. Set EDG1STAT. 1. Initialize the A/D Converter and the CTMU. 4. Wait for a fixed delay, T. 2. Set EDG1STAT. 5. Clear EDG1STAT. 3. Wait for a fixed delay. 6. Perform an A/D conversion. 4. Clear EDG1STAT. 7. Calculate the total capacitance, CTOTAL = (I * T)/V, 5. Perform an A/D conversion. where: The voltage measured by performing the A/D conver- • I is known from the current source sion is an indication of the relative capacitance. In this measurement step (Section 18.4.1 “Current case, no calibration of the current source or circuit Source Calibration”) capacitance measurement is needed. (For a sample • T is a fixed delay software routine for a capacitive touch switch, see • V is measured by performing an A/D conversion Example18-4.) 8. Subtract the stray and A/D capacitance (COFFSET from Section 18.4.2 “Capacitance Calibration”) from CTOTAL to determine the measured capacitance. DS30009977G-page 240  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY EXAMPLE 18-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define COUNT 500 //@ 8MHz = 125uS. #define DELAY for(i=0;i<COUNT;i++) #define OPENSW 1000 //Un-pressed switch value #define TRIP 300 //Difference between pressed //and un-pressed switch #define HYST 65 //amount to change //from pressed to un-pressed #define PRESSED 1 #define UNPRESSED 0 int main(void) { unsigned int Vread; //storage for reading unsigned int switchState; int i; //assume CTMU and A/D have been setup correctly //see Example 25-1 for CTMU & A/D setup setup(); CTMUCONHbits.CTMUEN = 1; //Enable the CTMU CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit DELAY; //wait 125us CTMUCONHbits.IDISSEN = 0; //end drain of circuit CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit //using CTMU current source DELAY; //wait for 125us CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit PIR1bits.ADIF = 0; //make sure A/D Int not set ADCON0bits.GO=1; //and begin A/D conv. while(!PIR1bits.ADIF); //Wait for A/D convert complete Vread = ADRES; //Get the value from the A/D if(Vread < OPENSW - TRIP) { switchState = PRESSED; } else if(Vread > OPENSW - TRIP + HYST) { switchState = UNPRESSED; } }  2010-2017 Microchip Technology Inc. DS30009977G-page 241

PIC18F66K80 FAMILY 18.6 Measuring Time with the CTMU It is assumed that the time measured is small enough Module that the capacitance, CAD + CEXT, provides a valid voltage to the A/D Converter. For the smallest time Time can be precisely measured after the ratio (C/I) is measurement, always set the A/D Channel Select bits measured from the current and capacitance calibration CHS<4:0> (ADCON0<6:2>) to an unused A/D channel, step. To do that: the corresponding pin for which is not connected to any 1. Initialize the A/D Converter and the CTMU. circuit board trace. This minimizes added stray capaci- tance, keeping the total circuit capacitance close to that 2. Set EDG1STAT. of the A/D Converter itself (25pF). 3. Set EDG2STAT. To measure longer time intervals, an external capacitor 4. Perform an A/D conversion. may be connected to an A/D channel and that channel 5. Calculate the time between edges as T = (C/I) * V, selected whenever making a time measurement. where: • I is calculated in the current calibration step (Section 18.4.1 “Current Source Calibration”) • C is calculated in the capacitance calibra- tion step (Section 18.4.2 “Capacitance Calibration”) • V is measured by performing the A/D conversion FIGURE 18-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC18F66K80 CTMU CTED1 EDG1 Current Source CTED2 EDG2 A/D Voltage A/D Converter ANX CAD CEXT DS30009977G-page 242  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 18.7 Measuring Temperature To perform a measurement, the multiplexer is config- with the CTMU ured to select the pin connected to the diode. The CTMU current source is then turned on and an A/D The constant current source provided by the CTMU conversion is performed on the channel. As shown in module can be used for low-cost temperature the equivalent circuit diagram, the diode is driven by measurement by exploiting a basic property of com- the CTMU at I . The resulting V across the diode is F F mon and inexpensive diodes. An on-chip temperature measured by the A/D. A code snippet is shown in sense diode is provided on A/D Channel 29 to further Example18-5. simplify design and cost. FIGURE 18-4: CTMU TEMPERATURE 18.7.1 BASIC PRINCIPAL MEASUREMENT CIRCUIT We can show that the forward voltage (V ) of a P-N F Simplified Block Diagram junction, such as a diode, is an extension of the equation for the junction’s thermal voltage: PIC® Microcontroller CTMU V = kT 1n ( 1 – IF) Current Source F q I S where k is the Boltzmann constant (1.38x10-23 J K-1), T is the absolute junction temperature in kelvin, q is the electron charge (1.6x10-19 C), IF is the forward current A/D Converter applied to the diode and IS is the diode’s characteristic MUX saturation current, which varies between devices. A/D Since k and q are physical constants, and I is a constant S for the device, this only leaves T and I as independent F variables. If IF is held constant, it follows from the equa- VF tion that V will vary as a function of T. As the natural log F term of the equation will always be negative, the tem- perature will be negatively proportional to V. In other F words, as temperature increases, V decreases. F By using the CTMU’s current source to provide a Equivalent Circuit constant I , it becomes possible to calculate the F temperature by measuring the V across the diode. F CTMU 18.7.2 IMPLEMENTATION To implement this theory, all that is needed is to con- IF A/D nect a regular junction diode to one of the microcontrol- VF ler’s A/D pins (Figure18-2). The A/D channel multiplexer is shared by the CTMU and the A/D. EXAMPLE 18-5: ROUTINE FOR TEMPERATURE MEASUREMENT USING INTERNAL DIODE // Initialize CTMU CTMUICON = 0x03; CTMUCONHbits.CTMUEN = 1; CTMUCONLbits.EDG1STAT = 1; // Initialize ADC ADCON0 = 0x75; // Enable ADC and connect to Internal diode ADCON1 = 0x00; ADCON2 = 0xBE; //Right Justified ADCON0bits.GO = 1; // Start conversion while(ADCON0bits.G0); Temp = ADRES; // Read ADC results (inversely proportional to temperature) Note: The temperature diode is not calibrated or standardized; the user must calibrate the diode to their application.  2010-2017 Microchip Technology Inc. DS30009977G-page 243

PIC18F66K80 FAMILY 18.8 Creating a Delay with the CTMU An example use of the external capacitor feature is Module interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the A unique feature on board the CTMU module is its ability pulse-width output on CTPLS will vary. An example use to generate system clock independent output pulses of the CTDIN feature is interfacing with a digital sensor. based on either an external voltage or an external The CTPLS output pin can be connected to an input capacitor value. When using an external voltage, this is capture pin and the varying pulse width measured to accomplished using the CTDIN input pin as a trigger for determine the sensor’s output in the application. the pulse delay. When using an external capacitor To use this feature: value, this is accomplished using the internal compara- tor voltage reference module and Comparator 2 input 1. If CTMUDS is cleared, initialize Comparator 2. pin.The pulse is output onto the CTPLS pin. To enable 2. If CTMUDS is cleared, initialize the comparator this mode, set the TGEN bit. voltage reference. See Figure18-5 for an example circuit. When 3. Initialize the CTMU and enable time delay CTMUDS (PADCFG1<0>) is cleared, the pulse delay is generation by setting the TGEN bit. determined by the output of Comparator 2, and when it 4. Set EDG1STAT. is set, the pulse delay is determined by the input of When CTMUDS is cleared, as soon as CDELAY CTDIN. CDELAY is chosen by the user to determine the charges to the value of the voltage reference trip point, output pulse width on CTPLS. The pulse width is calcu- an output pulse is generated on CTPLS. When lated by T = (CDELAY/I)*V, where I is known from the CTMUDS is set, as soon as CTDIN is set, an output current source measurement step (Section18.4.1 pulse is generated on CTPLS. “Current Source Calibration”) and V is the internal reference voltage (CVREF). FIGURE 18-5: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC18F66K80 CTMU CTED1 EDG1 CTPLS Current Source Comparator CTMUDS CTMUI CTDIN C2 CDELAY CVREF C1 External Reference External Comparator DS30009977G-page 244  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 18.9 Measuring Temperature with the source the current to the diode. The A/D reading will CTMU Module reflect the temperature. With the increase, the A/D readings will go low. This can be used for low-cost The CTMU, along with an internal diode, can be used temperature measurement applications. to measure the temperature. The A/D can be con- nected to the internal diode and the CTMU module can EXAMPLE 18-6: ROUTINE FOR TEMPERATURE MEASUREMENT USING INTERNAL DIODE // Initialize CTMU CTMUICON = 0x03; CTMUCONHbits.CTMUEN = 1; CTMUCONLbits.EDG1STAT = 1; // Initialize ADC ADCON0 = 0xE5; // Enable ADC and connect to Internal diode ADCON1 = 0x00; ADCON2 = 0xBE; //Right Justified ADCON0bits.GO = 1; // Start conversion while(ADCON0bits.G0); Temp = ADRES; // Read ADC results (inversely proportional to temperature) Note: The temperature diode is not calibrated or standardized; the user must calibrate the diode to their application.  2010-2017 Microchip Technology Inc. DS30009977G-page 245

PIC18F66K80 FAMILY 18.10 Operation During Sleep/Idle Modes case, if the module is performing an operation when Idle mode is invoked, the results will be similar to those 18.10.1 SLEEP MODE with Sleep mode. When the device enters any Sleep mode, the CTMU 18.11 Effects of a Reset on CTMU module current source is always disabled. If the CTMU is performing an operation that depends on the current Upon Reset, all registers of the CTMU are cleared. This source when Sleep mode is invoked, the operation may disables the CTMU module, turns off its current source not terminate correctly. Capacitance and time and returns all configuration options to their default set- measurements may return erroneous values. tings. The module needs to be re-initialized following any Reset. 18.10.2 IDLE MODE If the CTMU is in the process of taking a measurement The behavior of the CTMU in Idle mode is determined at the time of Reset, the measurement will be lost. A by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL partial charge may exist on the circuit that was being is cleared, the module will continue to operate in Idle measured, which should be properly discharged before mode. If CTMUSIDL is set, the module’s current source the CTMU makes subsequent attempts to make a is disabled when the device enters Idle mode. In this measurement. The circuit is discharged by setting and clearing the IDISSEN bit (CTMUCONH<1>) while the A/D Converter is connected to the appropriate channel. TABLE 18-1: REGISTERS ASSOCIATED WITH CTMU MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — PADCFG1 RDPU REPU RFPU RGPU — — — CTMUDS Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. DS30009977G-page 246  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 19.0 CAPTURE/COMPARE/PWM Each CCP module contains a 16-bit register that can (CCP) MODULES operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. PIC18F66K80 family devices have four CCP For the sake of clarity, all CCP module operation in the (Capture/Compare/PWM) modules, designated CCP2 following sections is described with respect to CCP2, through CCP5. All the modules implement standard but is equally applicable to CCP3 through CCP5. Capture, Compare and Pulse-Width Modulation (PWM) modes. Note: Throughout this section, generic references are used for register and bit names that are the same, except for an ‘x’ variable that indicates the item’s association with the specific CCP module. For example, the control register is named CCPxCON and refers to CCP2CON through CCP5CON. REGISTER 19-1: CCPxCON: CCPx CONTROL REGISTER (CCP2-CCP5 MODULES) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3(1) CCPxM2(1) CCPxM1(1) CCPxM0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits(1) 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode: every falling edge or CAN message received (time-stamp)(2) 0101 = Capture mode: every rising edge or CAN message received (time-stamp)(2) 0110 = Capture mode: every 4th rising edge or on every fourth CAN message received (time-stamp)(2 0111 = Capture mode: every 16th rising edge or on every 16th CAN message received (time-stamp)(2) 1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set) 11xx = PWM mode Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on CCPx match. 2: Available only on CCP2. Selected by the CANCAP (CIOCON<4>) bit. Overrides the CCP2 input pin source.  2010-2017 Microchip Technology Inc. DS30009977G-page 247

PIC18F66K80 FAMILY REGISTER 19-2: CCPTMRS: CCP TIMER SELECT REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 C5TSEL: CCP5 Timer Selection bit 0 = CCP5 is based off of TMR1/TMR2 1 = CCP5 is based off of TMR3/TMR4 bit 3 C4TSEL: CCP4 Timer Selection bit 0 = CCP4 is based off of TMR1/TMR2 1 = CCP4 is based off of TMR3/TMR4 bit 2 C3TSEL: CCP3 Timer Selection bit 0 = CCP3 is based off of TMR1/TMR2 1 = CCP3 is based off of TMR3/TMR4 bit 1 C2TSEL: CCP2 Timer Selection bit 0 = CCP2 is based off of TMR1/TMR2 1 = CCP2 is based off of TMR3/TMR4 bit 0 C1TSEL: CCP1 Timer Selection bit 0 = ECCP1 is based off of TMR1/TMR2 1 = ECCP1 is based off of TMR3/TMR4 DS30009977G-page 248  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 19-3: CCPRxL: CCPx PERIOD LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CCPRxL7 CCPRxL6 CCPRxL5 CCPRxL4 CCPRxL3 CCPRxL2 CCPRxL1 CCPRxL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CCPRxL<7:0>: CCPx Period Register Low Byte bits Capture Mode: Capture register low byte Compare Mode: Compare register low byte PWM Mode: Duty Cycle Buffer register REGISTER 19-4: CCPRxH: CCPx PERIOD HIGH BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CCPRxH7 CCPRxH6 CCPRxH5 CCPRxH4 CCPRxH3 CCPRxH2 CCPRxH1 CCPRxH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 CCPRxH<7:0>: CCPx Period Register High Byte bits Capture Mode: Capture register high byte Compare Mode: Compare register high byte PWM Mode: Duty Cycle Buffer register  2010-2017 Microchip Technology Inc. DS30009977G-page 249

PIC18F66K80 FAMILY 19.1 CCP Module Configuration TABLE 19-1: CCP MODE – TIMER RESOURCE Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a CCP Mode Timer Resource data register (CCPRx). The data register, in turn, is Capture comprised of two 8-bit registers: CCPRxL (low byte) Timer1 or Timer3 Compare and CCPRxH (high byte). All registers are both readable and writable. PWM Timer2 or Timer4 19.1.1 CCP MODULES AND TIMER The assignment of a particular timer to a module is RESOURCES determined by the Timer to CCP enable bits in the CCPTMRS register (see Register19-2). All of the The CCP modules utilize Timers, 1 through 4, varying modules may be active at once and may share the with the selected mode. Various timers are available to same timer resource if they are configured to operate the CCP modules in Capture, Compare or PWM in the same mode (Capture/Compare or PWM) at the modes, as shown in Table19-1. same time. The CCPTMRS register selects the timers for CCP modules, 2, 3, 4 and 5. The possible configurations are shown in Table19-2. TABLE 19-2: TIMER ASSIGNMENTS FOR CCP MODULES 2, 3, 4 AND 5 CCPTMRS Register CCP2 CCP3 CCP4 CCP5 Capture/ Capture/ Capture/ Capture/ PWM PWM PWM PWM C2TSEL Compare C3TSEL Compare C4TSEL Compare C5TSEL Compare Mode Mode Mode Mode Mode Mode Mode Mode 0 TMR1 TMR2 0 TMR1 TMR2 0 TMR1 TMR2 0 0 TMR1 TMR2 1 TMR3 TMR4 1 TMR3 TMR4 1 TMR3 TMR4 0 1 TMR3 TMR4 19.1.2 OPEN-DRAIN OUTPUT OPTION The open-drain output option is controlled by the CCPxOD bits (ODCON<6:2>). Setting the appropriate When operating in Output mode (the Compare or PWM bit configures the pin for the corresponding module for modes), the drivers for the CCPx pins can be optionally open-drain operation. configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. DS30009977G-page 250  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 19.2 Capture Mode 19.2.1 CCP PIN CONFIGURATION In Capture mode, the CCPRxH:CCPRxL register pair In Capture mode, the appropriate CCPx pin should be captures the 16-bit value of the Timer register selected configured as an input by setting the corresponding in the CCPTMRS when an event occurs on the CCPx TRIS direction bit. pin. An event is defined as one of the following: 19.2.2 TIMER1/3 MODE SELECTION • Every falling edge For the available timers (1/3) to be used for the capture • Every rising edge feature, the used timers must be running in Timer mode • Every 4th rising edge or Synchronized Counter mode. In Asynchronous • Every 16th rising edge Counter mode, the capture operation may not work. Note: For CCP2 only, the Capture mode can use The timer to be used with each CCP module is selected the CCP2 input pin as the capture trigger in the CCPTMRS register. (See Section19.1.1 “CCP for CCP2 or the input can function as a Modules and Timer Resources”.) time-stamp through the CAN module. The Details of the timer assignments for the CCP modules CAN module provides the necessary are given in Table19-2. control and trigger signals. The event is selected by the mode select bits, CCPxM<3:0> (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF (PIR4<x>), is set; it must be cleared in software. If another capture occurs before the value in CCPRx is read, the old captured value is overwritten by the new captured value. Figure19-1 shows the Capture mode block diagram. FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP3IF C3TSEL TMR3 Enable CCP3 Pin Prescaler and CCPR3H CCPR3L  1, 4, 16 Edge Detect TMR1 C3TSEL Enable 4 TMR1H TMR1L CCP3CON<3:0> Set CCP4IF 4 Q1:Q4 4 CCP4CON<3:0> TMR3H TMR3L C4TSEL TMR3 Enable CCP4 Pin Prescaler and CCPR4H CCPR4L  1, 4, 16 Edge Detect TMR1 Enable C4TSEL TMR1H TMR1L Note: This block diagram uses CCP3 and CCP4, and their appropriate timers as an example. For details on all of the CCP modules and their timer assignments, see Table19-2.  2010-2017 Microchip Technology Inc. DS30009977G-page 251

PIC18F66K80 FAMILY 19.2.3 SOFTWARE INTERRUPT 19.2.5 CAN MESSAGE TIME-STAMP (CCP2 ONLY) When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the For CCP2, only the CAN capture event occurs when a CCPxIE bit (PIE4<x>) clear to avoid false interrupts message is received in any of the receive buffers. and should clear the flag bit, CCPxIF, following any When configured, the CAN module provides the trigger such change in operating mode. to the CCP2 module to cause a capture event. This feature is provided to “time-stamp” the received CAN 19.2.4 CCP PRESCALER messages. There are four prescaler settings in Capture mode. This feature is enabled by setting the CANCAP bit of They are specified as part of the operating mode the CAN I/O Control register (CIOCON<4>). The mes- selected by the mode select bits (CCPxM<3:0>). sage receive signal from the CAN module then takes Whenever the CCP module is turned off, or the CCP the place of the events on RC2/CCP2. module is not in Capture mode, the prescaler counter If this feature is selected, then four different capture is cleared. This means that any Reset will clear the options for CCP2M<3:0> are available: prescaler counter. • 0100 – Every time a CAN message is received Switching from one capture prescaler to another may generate an interrupt. Doing that also will not clear the • 0101 – Every time a CAN message is received prescaler counter – meaning the first capture may be • 0110 – Every 4th time a CAN message is from a non-zero prescaler. received Example19-1 shows the recommended method for • 0111 – Capture mode, every 16th time a CAN message is received switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. EXAMPLE 19-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF CCPxCON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON MOVWF CCPxCON ; Load CCPxCON with ; this value DS30009977G-page 252  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 19.3 Compare Mode 19.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPRx register value is When the Generate Software Interrupt mode is chosen constantly compared against the Timer register pair (CCPxM<3:0> = 1010), the CCPx pin is not affected. value selected in the CCPTMR register. When a match Only a CCP interrupt is generated, if enabled, and the occurs, the CCPx pin can be: CCPxIE bit is set. • Driven high 19.3.4 SPECIAL EVENT TRIGGER • Driven low All CCP modules are equipped with a Special Event • Toggled (high-to-low or low-to-high) Trigger. This is an internal hardware signal generated • Unchanged (that is, reflecting the state of the I/O in Compare mode to trigger actions by other modules. latch) The Special Event Trigger is enabled by selecting The action on the pin is based on the value of the mode the Compare Special Event Trigger mode bits select bits (CCPxM<3:0>). At the same time, the (CCPxM<3:0> = 1011). interrupt flag bit, CCPxIF, is set. For either CCPx module, the Special Event Trigger resets the Timer register pair for whichever timer Figure19-2 gives the Compare mode block diagram resource is currently assigned as the module’s time 19.3.1 CCP PIN CONFIGURATION base. This allows the CCPRx registers to serve as a programmable Period register for either timer. The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. 19.3.5 COMPARE MODE INTERRUPT Note: Clearing the CCPxCON register will force TIMING the corresponding CCPx compare output For all Compare modes, an interrupt may be triggered latch (depending on device configuration) when the selected Timer register pair matches the to the default low level. This is not the value in the CCPRx register pair. This interrupt will be PORTx data latch. triggered upon the timer transitioning from the value of the CCPRx register pair to the next value. 19.3.2 TIMER1/3 MODE SELECTION If the CCPx module is using the compare feature in conjunction with any of the Timer1/3 timers, the timers must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the compare operation may not work. Note: Details of the timer assignments for the CCPx modules are given in Table19-2.  2010-2017 Microchip Technology Inc. DS30009977G-page 253

PIC18F66K80 FAMILY FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set CCP5IF (Timer1/3 Reset) CCPR5H CCPR5L CCP5 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP5CON<3:0> TMR1H TMR1L 0 TMR3H TMR3L 1 C5TSEL TMR1H TMR1L 0 1 TMR3H TMR3L Special Event Trigger (Timer1/Timer3 Reset) C4TSEL Set CCP4IF CCP4 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR4H CCPR4L CCP4CON<3:0> Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of the CCP modules and their timer assignments, see Table19-2. DS30009977G-page 254  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 19-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF RCON IPEN SBOREN CM RI TO PD POR BOR PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TMR1L Timer1 Register Low Byte TMR1H Timer1 Register High Byte TMR3L Timer3 Register Low Byte TMR3H Timer3 Register High Byte T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON CCPR2L Capture/Compare/PWM Register 2 Low Byte CCPR2H Capture/Compare/PWM Register 2 High Byte CCPR3L Capture/Compare/PWM Register 3 Low Byte CCPR3H Capture/Compare/PWM Register 3 High Byte CCPR4L Capture/Compare/PWM Register 4 Low Byte CCPR4H Capture/Compare/PWM Register 4 High Byte CCPR5L Capture/Compare/PWM Register 5 Low Byte CCPR5H Capture/Compare/PWM Register 5 High Byte CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 CCPTMRS — — — C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3.  2010-2017 Microchip Technology Inc. DS30009977G-page 255

PIC18F66K80 FAMILY 19.4 PWM Mode A PWM output (Figure19-4) has a time base (period) and a time that the output stays high (duty cycle). The In Pulse-Width Modulation (PWM) mode, the CCPx pin frequency of the PWM is the inverse of the period produces up to a 10-bit resolution PWM output. Since (1/period). the CCPx pin is multiplexed with a PORTC or PORTB data latch, the appropriate TRIS bit must be cleared to FIGURE 19-4: PWM OUTPUT make the CCPx pin an output. Period Note: Clearing the CCPxCON register will force the corresponding CCPx output latch (depending on device configuration) to the default low level. This is not the PORTx Duty Cycle I/O data latch. TMR2 = PR2 Figure19-3 shows a simplified block diagram of the TMR2 = Duty Cycle CCPx module in PWM mode. For a step-by-step procedure on how to set up the CCP TMR2 = PR2 module for PWM operation, see Section19.4.3 “Setup for PWM Operation”. 19.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 FIGURE 19-3: SIMPLIFIED PWM BLOCK register. The PWM period can be calculated using the DIAGRAM following formula: CCP4CON<5:4> Duty Cycle Registers EQUATION 19-1: CCPR4L PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. CCPR4H (Slave) When TMR2 is equal to PR2, the following three events occur on the next increment cycle: Comparator R Q • TMR2 is cleared RC2/CCP1 • The CCP4 pin is set TMR2 (Note 1) S (An exception: If PWM duty cycle=0%, the CCP4 pin will not be set) Comparator TRISC<2> • The PWM duty cycle is latched from CCPR4L into Clear Timer, CCP1 Pin and CCPR4H Latch D.C. PR2 Note: The Timer2 postscalers (see Section15.0 “Timer2 Module”) are not Note1: The 8-bit TMR2 value is concatenated with the 2-bit used in the determination of the PWM internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. frequency. The postscaler could be used 2: CCP4 and its appropriate timers are used as an to have a servo update rate at a different example. For details on all of the CCP modules and frequency than the PWM output. their timer assignments, see Table19-2. DS30009977G-page 256  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 19.4.2 PWM DUTY CYCLE The CCPR4H register and a two-bit internal latch are used to double-buffer the PWM duty cycle. This The PWM duty cycle is specified, to use CCP4 as an double-buffering is essential for glitchless PWM example, by writing to the CCPR4L register and to the operation. CCP4CON<5:4> bits. Up to 10-bit resolution is avail- able. The CCPR4L contains the eight MSbs and the When the CCPR4H and two-bit latch match TMR2, CCP4CON<5:4> contains the two LSbs. This 10-bit concatenated with an internal two-bit Q clock or two value is represented by CCPR4L:CCP4CON<5:4>. bits of the TMR2 prescaler, the CCP4 pin is cleared. The following equation is used to calculate the PWM The maximum PWM resolution (bits) for a given PWM duty cycle in time: frequency is given by the equation: EQUATION 19-2: EQUATION 19-3: PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) • TOSC • (TMR2 Prescale Value) logF--F--P-O--W--S---CM--- PWM Resolution (max) = -----------------------------bits log2 CCPR4L and CCP4CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR4H until after a match between PR2 and TMR2 Note: If the PWM duty cycle value is longer than occurs (that is, the period is complete). In PWM mode, the PWM period, the CCP4 pin will not be CCPR4H is a read-only register. cleared. TABLE 19-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 19.4.3 SETUP FOR PWM OPERATION 3. Make the CCP4 pin an output by clearing the appropriate TRIS bit. To configure the CCP module for PWM operation, using CCP4 as an example: 4. Set the TMR2 prescale value, then enable Tim- er2 by writing to T2CON. 1. Set the PWM period by writing to the PR2 5. Configure the CCP4 module for PWM operation. register. 2. Set the PWM duty cycle by writing to the CCPR4L register and CCP4CON<5:4> bits.  2010-2017 Microchip Technology Inc. DS30009977G-page 257

PIC18F66K80 FAMILY TABLE 19-5: REGISTERS ASSOCIATED WITH PWM AND TIMERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF RCON IPEN SBOREN CM RI TO PD POR BOR PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TMR2 Timer2 Register TMR4 Timer4 Register PR2 Timer2 Period Register PR4 Timer4 Period Register T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 CCPR2L Capture/Compare/PWM Register 2 Low Byte CCPR2H Capture/Compare/PWM Register 2 High Byte CCPR3L Capture/Compare/PWM Register 3 Low Byte CCPR3H Capture/Compare/PWM Register 3 High Byte CCPR4L Capture/Compare/PWM Register 4 Low Byte CCPR4H Capture/Compare/PWM Register 4 High Byte CCPR5L Capture/Compare/PWM Register 5 Low Byte CCPR5H Capture/Compare/PWM Register 5 High Byte CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 CCPTMRS — — — C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2/4. DS30009977G-page 258  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 20.0 ENHANCED • Provision for two or four output channels CAPTURE/COMPARE/PWM • Output Steering modes (ECCP) MODULE • Programmable polarity • Programmable dead-band control PIC18F66K80 family devices have one Enhanced • Automatic shutdown and restart Capture/Compare/PWM (ECCP) module: ECCP1. These modules contain a 16-bit register, which can The enhanced features are discussed in detail in operate as a 16-bit Capture register, a 16-bit Compare Section20.4 “PWM (Enhanced Mode)”. register or a PWM Master/Slave Duty Cycle register. The ECCP1 module uses the control register, These ECCP modules are upward compatible with CCP CCP1CON. The control registers, CCP2CON through ECCP1 is implemented as standard CCP modules with CCP5CON, are for the modules, CCP2 through CCP5. enhanced PWM capabilities. These include:  2010-2017 Microchip Technology Inc. DS30009977G-page 259

PIC18F66K80 FAMILY REGISTER 20-1: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM1 CONTROL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as capture/compare input/output; P1B, P1C and P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output: P1A, P1B, P1C and P1D are controlled by steering (see Section20.4.7 “Pulse Steering Mode”) 01 = Full-bridge output forward: P1D is modulated; P1A is active; P1B, P1C is inactive 10 = Half-bridge output: P1A, P1B are modulated with dead-band control; P1C and P1D are assigned as port pins 11 = Full-bridge output reverse: P1B is modulated; P1C is active; P1A and P1D are inactive bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP1 module) 0001 = Reserved 0010 = Compare mode: Toggle output on match 0011 = Capture mode 0100 = Capture mode: Every falling edge 0101 = Capture mode: Every rising edge 0110 = Capture mode: Every fourth rising edge 0111 = Capture mode: Every 16th rising edge 1000 = Compare mode: Initialize ECCP1 pin low, set output on compare match (set CCP1IF) 1001 = Compare mode: Initialize ECCP1 pin high, clear output on compare match (set CCP1IF) 1010 = Compare mode: Generate software interrupt only, ECCP1 pin reverts to I/O state 1011 = Compare mode: Trigger special event (ECCP1 resets TMR1 or TMR3, starts A/D conversion, sets CCP1IF bit) 1100 = PWM mode: P1A and P1C are active-high; P1B and P1D are active-high 1101 = PWM mode: P1A and P1C are active-high; P1B and P1D are active-low 1110 = PWM mode: P1A and P1C are active-low; P1B and P1D are active-high 1111 = PWM mode: P1A and P1C are active-low; P1B and P1D are active-low DS30009977G-page 260  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 20-2: CCPTMRS: CCP TIMER SELECT REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 C5TSEL: CCP5 Timer Selection bit 0 = CCP5 is based off of TMR1/TMR2 1 = CCP5 is based off of TMR3/TMR4 bit 3 C4TSEL: CCP4 Timer Selection bit 0 = CCP4 is based off of TMR1/TMR2 1 = CCP4 is based off of TMR3/TMR4 bit 2 C3TSEL: CCP3 Timer Selection bit 0 = CCP3 is based off of TMR1/TMR2 1 = CCP3 is based off of TMR3/TMR4 bit 1 C2TSEL: CCP2 Timer Selection bit 0 = CCP2 is based off of TMR1/TMR2 1 = CCP2 is based off of TMR3/TMR4 bit 0 C1TSEL: CCP1 Timer Selection bit 0 = ECCP1 is based off of TMR1/TMR2 1 = ECCP1 is based off of TMR3/TMR4  2010-2017 Microchip Technology Inc. DS30009977G-page 261

PIC18F66K80 FAMILY In addition to the expanded range of modes available The assignment of a particular timer to a module is through the CCP1CON and ECCP1AS registers, the determined by the Timer to ECCP enable bits in the ECCP module has two additional registers associated CCPTMRS register (Register20-2). The interactions with Enhanced PWM operation and auto-shutdown between the two modules are depicted in Figure20-1. features. They are: Capture operations are designed to be used when the timer is configured for Synchronous Counter mode. • ECCP1DEL – Enhanced PWM Control Capture operations may not work as expected if the • PSTR1CON – Pulse Steering Control associated timer is configured for Asynchronous Counter mode. 20.1 ECCP Outputs and Configuration 20.2 Capture Mode The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. In Capture mode, the CCPR1H:CCPR1L register pair The CCP1CON register is modified to allow control captures the 16-bit value of the TMR1 or TMR3 over four PWM outputs: ECCP1/P1A, P1B, P1C and registers when an event occurs on the corresponding P1D. Applications can use one, two or four of these ECCP1 pin. An event is defined as one of the following: outputs. • Every falling edge The outputs that are active depend on the ECCP • Every rising edge operating mode selected. The pin assignments are summarized in Table20-2. • Every fourth rising edge • Every 16th rising edge To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1M<1:0> The event is selected by the mode select bits, and CCP1M<3:0> bits. The appropriate TRIS direction CCP1M<3:0> (CCP1CON<3:0>). When a capture is bits for the port pins must also be set as outputs. made, the interrupt request flag bit, CCP1IF, is set (PIR3<1>). The flag must be cleared by software. If 20.1.1 ECCP MODULE AND TIMER another capture occurs before the value in the RESOURCES CCPR1H/L register is read, the old captured value is overwritten by the new captured value. The ECCP modules use Timers, 1, 2, 3 and 4, depend- ing on the mode selected. These timers are available to 20.2.1 ECCP PIN CONFIGURATION CCP modules in Capture, Compare or PWM modes, as shown in Table20-1. In Capture mode, the appropriate ECCP1 pin should be configured as an input by setting the corresponding TABLE 20-1: ECCP MODE – TIMER TRIS direction bit. RESOURCE Note: If the ECCP1 pin is configured as an out- ECCP Mode Timer Resource put, a write to the port can cause a capture condition. Capture Timer1 or Timer3 Compare Timer1 or Timer3 PWM Timer2 or Timer4 DS30009977G-page 262  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 20.2.2 TIMER1/2/3/4 MODE SELECTION 20.2.4 ECCP PRESCALER The timers that are to be used with the capture feature There are four prescaler settings in Capture mode; they (Timer1 2, 3 or 4) must be running in Timer mode or are specified as part of the operating mode selected by Synchronized Counter mode. In Asynchronous the mode select bits (CCP1M<3:0>). Whenever the Counter mode, the capture operation may not work. ECCP module is turned off, or Capture mode is dis- The timer to be used with each ECCP module is abled, the prescaler counter is cleared. This means selected in the CCPTMRS register (Register20-2). that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may 20.2.3 SOFTWARE INTERRUPT generate an interrupt. Also, the prescaler counter will When the Capture mode is changed, a false capture not be cleared; therefore, the first capture may be from interrupt may be generated. The user should keep the a non-zero prescaler. Example20-1 provides the CCP1IE interrupt enable bit clear to avoid false inter- recommended method for switching between capture rupts. The interrupt flag bit, CCP1IF, should also be prescalers. This example also clears the prescaler cleared following any such change in operating mode. counter and will not generate the “false” interrupt. EXAMPLE 20-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF CCP1CON ; Turn ECCP module off MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and ECCP ON MOVWF CCP1CON ; Load ECCP1CON with ; this value FIGURE 20-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF C1TSEL0 C1TSEL1 TMR3 ECCP1 Pin C1TSEL2 Enable Prescaler and CCPR1H CCPR1L  1, 4, 16 Edge Detect C1TSEL0 TMR1 C1TSEL1 Enable C1TSEL2 4 TMR1H TMR1L CCP1CON<3:0> 4 Q1:Q4  2010-2017 Microchip Technology Inc. DS30009977G-page 263

PIC18F66K80 FAMILY 20.3 Compare Mode 20.3.2 TIMER1/2/3/4 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is Timer1, 2, 3 or 4 must be running in Timer mode or constantly compared against the Timer register pair Synchronized Counter mode if the ECCP module is value selected in the CCPTMR1 register. When a using the compare feature. In Asynchronous Counter match occurs, the ECCP1 pin can be: mode, the compare operation will not work reliably. • Driven high 20.3.3 SOFTWARE INTERRUPT MODE • Driven low When the Generate Software Interrupt mode is chosen • Toggled (high-to-low or low-to-high) (CCP1M<3:0> = 1010), the ECCP1 pin is not affected; • Unchanged (that is, reflecting the state of the I/O only the CCP1IF interrupt flag is affected. latch) 20.3.4 SPECIAL EVENT TRIGGER The action on the pin is based on the value of the mode select bits (CCP1M<3:0>). At the same time, the The ECCP module is equipped with a Special Event interrupt flag bit, CCP1IF, is set. Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. 20.3.1 ECCP PIN CONFIGURATION The Special Event Trigger is enabled by selecting Users must configure the ECCP1 pin as an output by the Compare Special Event Trigger mode clearing the appropriate TRIS bit. (CCP1M<3:0> = 1011). The Special Event Trigger resets the Timer register pair Note: Clearing the CCP1CON register will force for whichever timer resource is currently assigned as the the ECCP1 compare output latch module’s time base. This allows the CCPR1 registers to (depending on device configuration) to the serve as a programmable Period register for either timer. default low level. This is not the port I/O data latch. The Special Event Trigger can also start an A/D conver- sion. In order to do this, the A/D Converter must already be enabled. FIGURE 20-2: COMPARE MODE OPERATION BLOCK DIAGRAM TMR1H TMR1L 0 1 TMR3H TMR3L Special Event Trigger C1TSEL0 (Timer1/Timer3 Reset, A/D Trigger) C1TSEL1 C1TSEL2 Set CCP1IF ECCP1 Pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR1H CCPR1L CCP1CON<3:0> DS30009977G-page 264  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 20.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated: P1A, P1B, P1C and P1D. The polarity of the The Enhanced PWM mode can generate a PWM signal PWM pins is configurable and is selected by setting the on up to four different output pins with up to 10 bits of CCP1M bits in the CCP1CON register appropriately. resolution. It can do this through four different PWM Table20-1 provides the pin assignments for each Output modes: Enhanced PWM mode. • Single PWM Figure20-3 provides an example of a simplified block • Half-Bridge PWM diagram of the Enhanced PWM module. • Full-Bridge PWM, Forward mode Note: To prevent the generation of an • Full-Bridge PWM, Reverse mode incomplete waveform when the PWM is To select an Enhanced PWM mode, the P1M bits of the first enabled, the ECCP module waits until CCP1CON register must be set appropriately. the start of a new PWM period before generating a PWM signal. FIGURE 20-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> P1M<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L ECCP1/P1A ECCP1/Output Pin TRIS CCPR1H (Slave) P1B Output Pin Output TRIS Comparator R Q Controller P1C Output Pin TMR2 (1) S TRIS P1D Output Pin Comparator Clear Timer2, TRIS Toggle PWM Pin and Latch Duty Cycle PR2 ECCP1DEL Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. Note1: The TRIS register value for each PWM output must be configured appropriately. 2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.  2010-2017 Microchip Technology Inc. DS30009977G-page 265

PIC18F66K80 FAMILY TABLE 20-2: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M<1:0> P1A P1B P1C P1D Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Outputs are enabled by pulse steering in Single mode (see Register20-5). FIGURE 20-4: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse Width PR2 + 1 P1M<1:0> Signal 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section20.4.6 “Programmable Dead-Band Delay Mode”). DS30009977G-page 266  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 20-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PR2 + 1 P1M<1:0> Signal 0 Pulse Width Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section20.4.6 “Programmable Dead-Band Delay Mode”).  2010-2017 Microchip Technology Inc. DS30009977G-page 267

PIC18F66K80 FAMILY 20.4.1 HALF-BRIDGE MODE Since the P1A and P1B outputs are multiplexed with the port data latches, the associated TRIS bits must be In Half-Bridge mode, two pins are used as outputs to cleared to configure P1A and P1B as outputs. drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output FIGURE 20-6: EXAMPLE OF signal is output on the P1B pin (see Figure20-6). This HALF-BRIDGE PWM mode can be used for half-bridge applications, as shown in Figure20-7, or for full-bridge applications, OUTPUT where four power switches are being modulated with Period Period two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in P1A(2) half-bridge power devices. The value of the P1DC<6:0> td bits of the ECCP1DEL register sets the number of td instruction cycles before the output is driven active. If the P1B(2) value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. For more (1) (1) (1) details on the dead-band delay operations, see Section20.4.6 “Programmable Dead-Band Delay td = Dead-Band Delay Mode”. Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FIGURE 20-7: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A - Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver P1A Load FET FET Driver Driver P1B DS30009977G-page 268  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 20.4.2 FULL-BRIDGE MODE In the Reverse mode, the P1C pin is driven to its active state and the P1B pin is modulated, while the P1A and In Full-Bridge mode, all four pins are used as outputs. P1D pins are driven to their inactive state, as provided An example of a full-bridge application is provided in Figure20-9. Figure20-8. The P1A, P1B, P1C and P1D outputs are multiplexed In the Forward mode, the P1A pin is driven to its active with the port data latches. The associated TRIS bits state and the P1D pin is modulated, while the P1B and must be cleared to configure the P1A, P1B, P1C and P1C pins are driven to their inactive state, as provided in P1D pins as outputs. Figure20-9. FIGURE 20-8: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D  2010-2017 Microchip Technology Inc. DS30009977G-page 269

PIC18F66K80 FAMILY FIGURE 20-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: The output signal is shown as active-high. DS30009977G-page 270  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 20.4.2.1 Direction Change in Full-Bridge • The direction of the PWM output changes when Mode the duty cycle of the output is at or near 100%. • The turn-off time of the power switch, including In the Full-Bridge mode, the P1M1 bit in the CCP1CON the power device and driver circuit, is greater than register allows users to control the forward/reverse the turn-on time. direction. When the application firmware changes this direction control bit, the module will change to the new Figure20-11 shows an example of the PWM direction direction on the next PWM cycle. changing from forward to reverse, at a near 100% duty cycle. In this example, at time, t1, the P1A and P1D A direction change is initiated in software by changing outputs become inactive, while the P1C output the P1M1 bit of the CCP1CON register. The following becomes active. Since the turn-off time of the power sequence occurs prior to the end of the current PWM devices is longer than the turn-on time, a shoot-through period: current will flow through power devices, QC and QD • The modulated outputs (P1B and P1D) are placed (see Figure20-8), for the duration of ‘t’. The same in their inactive state. phenomenon will occur to power devices, QA and QB, • The associated unmodulated outputs (P1A and for PWM direction change from reverse to forward. P1C) are switched to drive in the opposite If changing PWM direction at high duty cycle is required direction. for an application, two possible solutions for eliminating • PWM modulation resumes at the beginning of the the shoot-through current are: next period. • Reduce PWM duty cycle for one PWM period For an illustration of this sequence, see Figure20-10. before changing directions. The Full-Bridge mode does not provide a dead-band • Use switch drivers that can drive the switches off delay. As one output is modulated at a time, a faster than they can drive them on. dead-band delay is generally not required. There is a Other options to prevent shoot-through current may situation where a dead-band delay is required. This exist. situation occurs when both of the following conditions are true: FIGURE 20-10: EXAMPLE OF PWM DIRECTION CHANGE Signal Period(1) Period P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: The direction bit, P1M1 of the CCP1CON register, is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is: (1/FOSC) • TMR2 Prescale Value.  2010-2017 Microchip Technology Inc. DS30009977G-page 271

PIC18F66K80 FAMILY FIGURE 20-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential T = TOFF – TON Shoot-Through Current Note 1: All signals are shown as active-high. 2: TON is the turn-on delay of power switch, QC, and its driver. 3: TOFF is the turn-off delay of power switch, QD, and its driver. 20.4.3 START-UP CONSIDERATIONS damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and When any PWM mode is used, the application complete a full PWM cycle before enabling the PWM hardware must use the proper external pull-up and/or pin output drivers. The completion of a full PWM cycle pull-down resistors on the PWM output pins. is indicated by the TMR2IF or TMR4IF bit of the PIR1 Note: When the microcontroller is released from or PIR4 register being set as the second PWM period Reset, all of the I/O pins are in the begins. high-impedance state. The external circuits must keep the power switch 20.4.4 ENHANCED PWM devices in the OFF state until the micro- AUTO-SHUTDOWN MODE controller drives the I/O pins with the The PWM mode supports an Auto-Shutdown mode that proper signal levels or activates the PWM will disable the PWM outputs when an external output(s). shutdown event occurs. Auto-Shutdown mode places The CCP1M<1:0> bits of the CCP1CON register allow the PWM output pins into a predetermined state. This the user to choose whether the PWM output signals are mode is used to help prevent the PWM from damaging active-high or active-low for each pair of PWM output the application. pins (P1A/P1C and P1B/P1D). The PWM output The auto-shutdown sources are selected using the polarities must be selected before the PWM pin output ECCP1AS<2:0> bits (ECCP1AS<6:4>). A shutdown drivers are enabled. Changing the polarity configura- event may be generated by: tion while the PWM pin output drivers are enabled is • A logic ‘0’ on the pin that is assigned the FLT0 not recommended since it may result in damage to the input function application circuits. • Comparator C1 The P1A, P1B, P1C and P1D output latches may not be • Comparator C2 in the proper states when the PWM module is • Setting the ECCP1ASE bit in firmware initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause DS30009977G-page 272  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY A shutdown condition is indicated by the ECCP1ASE Each pin pair may be placed into one of three states: (Auto-Shutdown Event Status) bit (ECCP1AS<7>). If • Drive logic ‘1’ the bit is a ‘0’, the PWM pins are operating normally. If • Drive logic ‘0’ the bit is a ‘1’, the PWM outputs are in the shutdown • Tri-state (high-impedance) state. When a shutdown event occurs, two things happen: • The ECCP1ASE bit is set to ‘1’. The ECCP1ASE will remain set until cleared in firmware or an auto-restart occurs. (See Section20.4.5 “Auto-Restart Mode”.) • The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs (P1A/P1C) and (P1B/P1D). The state of each pin pair is determined by the PSS1ACx and PSS1BDx bits (ECCP1AS<3:2> and <1:0>, respectively). REGISTER 20-3: ECCP1AS: ECCP1 AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCP1ASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in a shutdown state 0 =ECCP outputs are operating bit 6-4 ECCP1AS<2:0>: ECCP Auto-Shutdown Source Select bits 000 =Auto-shutdown is disabled 001 =Comparator C1OUT output is high 010 =Comparator C2OUT output is high 011 =Either Comparator C1OUT or C2OUT is high 100 =VIL on FLT0 pin 101 =VIL on FLT0 pin or Comparator C1OUT output is high 110 =VIL on FLT0 pin or Comparator C2OUT output is high 111 =VIL on FLT0 pin or Comparator C1OUT or Comparator C2OUT is high bit 3-2 PSS1AC<1:0>: P1A and P1C Pins Shutdown State Control bits 00 =Drive pins, P1A and P1C, to ‘0’ 01 =Drive pins, P1A and P1C, to ‘1’ 1x = Pins, P1A and P1C, tri-state bit 1-0 PSS1BD<1:0>: P1B and P1D Pins Shutdown State Control bits 00 = Drive pins, P1B and P1D, to ‘0’ 01 = Drive pins, P1B and P1D, to ‘1’ 1x = Pins, P1B and P1D, tri-state Note1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCP1ASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period.  2010-2017 Microchip Technology Inc. DS30009977G-page 273

PIC18F66K80 FAMILY FIGURE 20-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (P1RSEN = 0) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM ECCP1ASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes 20.4.5 AUTO-RESTART MODE The module will wait until the next PWM period begins, however, before re-enabling the output pin. This behav- The Enhanced PWM can be configured to automatically ior allows the auto-shutdown with auto-restart features restart the PWM signal once the auto-shutdown condi- to be used in applications based on current mode of tion has been removed. Auto-restart is enabled by PWM control. setting the P1RSEN bit (ECCP1DEL<7>). If auto-restart is enabled, the ECCP1ASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCP1ASE bit will be cleared via hardware and normal operation will resume. FIGURE 20-13: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (P1RSEN = 1) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes DS30009977G-page 274  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 20.4.6 PROGRAMMABLE DEAD-BAND FIGURE 20-14: EXAMPLE OF DELAY MODE HALF-BRIDGE PWM OUTPUT In half-bridge applications, where all power switches are modulated at the PWM frequency, the power Period Period switches normally require more time to turn off than to Pulse Width turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other P1A(2) turned off), both switches may be on for a short period td until one switch completely turns off. During this brief td interval, a very high current (shoot-through current) will P1B(2) flow through both power switches, shorting the bridge supply. To avoid this potentially destructive (1) (1) (1) shoot-through current from flowing during switching, turning on either of the power switches is normally td = Dead-Band Delay delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable Note 1: At this time, the TMR2 register is equal to the dead-band delay is available to avoid shoot-through PR2 register. current from destroying the bridge power switches. The 2: Output signals are shown as active-high. delay occurs at the signal transition from the non-active state to the active state. For an illustration, see Figure20-14. The lower seven bits of the associated ECCP1DEL register (Register20-4) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 20-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A V - Load FET Driver + P1B V - V-  2010-2017 Microchip Technology Inc. DS30009977G-page 275

PIC18F66K80 FAMILY REGISTER 20-4: ECCP1DEL: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCP1ASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCP1ASE must be cleared by software to restart the PWM bit 6-0 P1DC<6:0>: PWM Delay Count bits P1DCn = Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it does transition active. 20.4.7 PULSE STEERING MODE While the PWM Steering mode is active, the CCP1M<1:0> bits (CCP1CON<1:0>) select the PWM In Single Output mode, pulse steering allows any of the output polarity for the P1<D:A> pins. PWM pins to be the modulated signal. Additionally, the same PWM signal can simultaneously be available on The PWM auto-shutdown operation also applies to the multiple pins. PWM Steering mode, as described in Section20.4.4 “Enhanced PWM Auto-shutdown mode”. An Once the Single Output mode is selected auto-shutdown event will only affect pins that have (CCP1M<3:2> = 11 and P1M<1:0> = 00 of the PWM outputs enabled. CCP1CON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR<D:A> bits (PSTR1CON<3:0>), as provided in Table20-2. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. DS30009977G-page 276  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 20-5: PSTR1CON: PULSE STEERING CONTROL(1) R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 00 = See STR<D:A>. 01 = PA and PB are selected as the complementary output pair 10 = PA and PC are selected as the complementary output pair 11 = PA and PD are selected as the complementary output pair bit 5 Unimplemented: Read as ‘0’ bit 4 STRSYNC: Steering Sync bit 1 = Output steering update occurs on the next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRD: Steering Enable bit D 1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1D pin is assigned to port pin bit 2 STRC: Steering Enable bit C 1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1C pin is assigned to port pin bit 1 STRB: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1B pin is assigned to port pin bit 0 STRA: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits, CCP1M<3:2>=11 and P1M<1:0>=00.  2010-2017 Microchip Technology Inc. DS30009977G-page 277

PIC18F66K80 FAMILY FIGURE 20-16: SIMPLIFIED STEERING 20.4.7.1 Steering Synchronization BLOCK DIAGRAM(1,2) The STRSYNC bit of the PSTR1CON register gives the STRA user two choices for when the steering event will happen. When the STRSYNC bit is ‘0’, the steering P1A Signal Output Pin event will happen at the end of the instruction that CCP1M1 1 writes to the PSTR1CON register. In this case, the out- Port Data put signal at the P1<D:A> pins may be an incomplete 0 TRIS PWM waveform. This operation is useful when the user STRB firmware needs to immediately remove a PWM signal from the pin. Output Pin CCP1M0 1 When the STRSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM Port Data 0 period. In this case, steering on/off the PWM output will TRIS STRC always produce a complete PWM waveform. Figures 20-17 and20-18 illustrate the timing diagrams Output Pin CCP1M1 1 of the PWM steering depending on the STRSYNC setting. Port Data 0 TRIS STRD Output Pin CCP1M0 1 Port Data 0 TRIS Note 1: Port outputs are configured as displayed when the CCP1CON register bits, P1M<1:0>=00 and CCP1M<3:2>=11. 2: Single PWM output requires setting at least one of the STR<D:A> bits. FIGURE 20-17: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STR<D:A> P1<D:A> Port Data Port Data P1n = PWM FIGURE 20-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STR<D:A> P1<D:A> Port Data Port Data P1n = PWM DS30009977G-page 278  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 20.4.8 OPERATION IN POWER-MANAGED 20.4.8.1 Operation with Fail-Safe MODES ClockMonitor (FSCM) In Sleep mode, all clock sources are disabled. Timer2/4 If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock will not increment and the state of the module will not failure will force the device into the power-managed change. If the ECCP1 pin is driving a value, it will con- RC_RUN mode and the OSCFIF bit of the PIR2 register tinue to drive that value. When the device wakes up, it will be set. The ECCP1 will then be clocked from the will continue from this state. If Two-Speed Start-ups are internal oscillator clock source, which may have a enabled, the initial start-up frequency from HF-INTOSC different clock frequency than the primary clock. and the postscaler may not be stable immediately. 20.4.9 EFFECTS OF A RESET In PRI_IDLE mode, the primary clock will continue to clock the ECCP1 module without change. Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP registers to their Reset states. This forces the ECCP module to reset to a state compatible with previous, non-enhanced CCP modules used on other PIC18 and PIC16 devices.  2010-2017 Microchip Technology Inc. DS30009977G-page 279

PIC18F66K80 FAMILY TABLE 20-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1/2/3/4 File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF RCON IPEN SBOREN CM RI TO PD POR BOR PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISE(1) TRISE7 TRISE6 TRISE5 TRISE4 — TRISE2 TRISE1 TRISE0 TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte TMR2 Timer2 Register TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte TMR4 Timer4 Register PR2 Timer2 Period Register PR4 Timer4 Period Register T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 CCPR1H Capture/Compare/PWM Register 1 High Byte CCPR1L Capture/Compare/PWM Register 1 Low Byte CCPR2H Capture/Compare/PWM Register 2 High Byte CCPR2L Capture/Compare/PWM Register 2 Low Byte CCPR3H Capture/Compare/PWM Register 3 High Byte CCPR3L Capture/Compare/PWM Register 3 Low Byte CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 CCPTMRS — — — C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD Note 1: Unimplemented on devices with a program memory of 32Kbytes (PIC18F25K80 and PIC18F46K80). DS30009977G-page 280  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.0 MASTER SYNCHRONOUS FIGURE 21-1: MSSP BLOCK DIAGRAM SERIAL PORT (MSSP) (SPIMODE) MODULE Internal Data Bus 21.1 Master SSP (MSSP) Module Read Write Overview SSPBUF reg The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral SDI devices may be devices such as serial EEPROMs, shift SSPSR reg registers, display drivers and A/D Converters. The SDO bit 0 Shift MSSP module can operate in either of two modes: Clock • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) - Full Master mode SS SS Control - Slave mode (with general address call) Enable The I2C interface supports the following modes in Edge hardware: Select • Master mode • Multi-Master mode 2 Clock Select • Slave mode with 5-bit and 7-bit address masking (with address masking for both 10-bit and 7-bit SSPM<3:0> addressing) SMP:CKE 4 (T M R 2 O u tp u t) SCK 2 2 21.2 Control Registers Edge Select Prescaler TOSC The MSSP module has three associated control regis- 4, 16, 64 ters. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The Data to TXx/RXx in SSPSR use of these registers and their individual configuration TRIS bit bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of Additional details are provided under the individual multiplexed functions. sections. 21.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) – RC5/SDO • Serial Data In (SDI) – RC4/SDA/SDI • Serial Clock (SCK) – RC3/REF0/SCL/SCK Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) – RA5/AN4/C2INB/ HLVDIN/T1CKI/SS/CTMU1 Figure21-1 shows the block diagram of the MSSP module when operating in SPI mode.  2010-2017 Microchip Technology Inc. DS30009977G-page 281

PIC18F66K80 FAMILY 21.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together, • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer Register and the SSPIF interrupt is set. (SSPBUF) During transmission, the SSPBUF is not • MSSP Shift Register (SSPSR) – Not directly double-buffered. A write to SSPBUF will write to both accessible SSPBUF and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 21-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C™ mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled; SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive is complete, SSPBUF is full 0 = Receive is not complete, SSPBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>). DS30009977G-page 282  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 21-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over- flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables the serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables the serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 1010 = SPI Master mode: clock = FOSC/8 0101 = SPI Slave mode: clock = SCK pin; SS pin control disabled; SS can be used as I/O pin 0100 = SPI Slave mode: clock = SCK pin; SS pin control enabled 0011 = SPI Master mode: clock = TMR2 output/2 0010 = SPI Master mode: clock = FOSC/64 0001 = SPI Master mode: clock = FOSC/16 0000 = SPI Master mode: clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as inputs or outputs. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.  2010-2017 Microchip Technology Inc. DS30009977G-page 283

PIC18F66K80 FAMILY 21.3.2 OPERATION When the application software is expecting to receive valid data, the SSPBUF should be read before the next When initializing the SPI, several options need to be byte of data to transfer is written to the SSPBUF. The specified. This is done by programming the appropriate Buffer Full bit, BF (SSPSTAT<0>), indicates when control bits (SSPCON1<5:0> and SSPSTAT<7:6>). SSPBUF has been loaded with the received data These control bits allow the following to be specified: (transmission is complete). When the SSPBUF is read, • Master mode (SCK is the clock output) the BF bit is cleared. This data may be irrelevant if the • Slave mode (SCK is the clock input) SPI is only a transmitter. Generally, the MSSP interrupt • Clock Polarity (Idle state of SCK) is used to determine when the transmission/reception has completed. If the interrupt method is not going to • Data Input Sample Phase (middle or end of data be used, then software polling can be done to ensure output time) that a write collision does not occur. Example21-1 • Clock Edge (output data on rising/falling edge of shows the loading of the SSPBUF (SSPSR) for data SCK) transmission. • Clock Rate (Master mode only) The SSPSR is not directly readable or writable and can • Slave Select mode (Slave mode only) only be accessed by addressing the SSPBUF register. The MSSP module consists of a Transmit/Receive Shift Additionally, the SSPSTAT register indicates the register (SSPSR) and a Buffer register (SSPBUF). The various status conditions. SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the 21.3.3 OPEN-DRAIN OUTPUT OPTION SSPSR until the received data is ready. Once the 8 bits The drivers for the SDO output and SCK clock pins can of data have been received, that byte is moved to the be optionally configured as open-drain outputs. This SSPBUF register. Then, the Buffer Full detect bit, BF feature allows the voltage level on the pin to be pulled (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are to a higher level through an external pull-up resistor, set. This double-buffering of the received data and allows the output to communicate with external cir- (SSPBUF) allows the next byte to start reception before cuits without the need for additional level shifters. For reading the data that was just received. Any write to the more information, see Section11.1.3 “Open-Drain SSPBUF register during transmission/reception of data Outputs”. will be ignored and the Write Collision Detect bit, The open-drain output option is controlled by the WCOL (SSPCON1<7>), will be set. User software SSPOD bit (ODCON<7>). Setting the SSPOD bit must clear the WCOL bit so that it can be determined if configures the SDO and SCK pins for open-drain the following write(s) to the SSPBUF register operation. completed successfully. EXAMPLE 21-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS30009977G-page 284  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.3.4 ENABLING SPI I/O 21.3.5 TYPICAL CONNECTION To enable the serial port, MSSP Enable bit, SSPEN Figure21-2 shows a typical connection between two (SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, reinitialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their pro- configures the SDI, SDO, SCK and SS pins as serial grammed clock edge and latched on the opposite edge port pins. For the pins to behave as the serial port func- of the clock. Both processors should be programmed to tion, some must have their data direction bits (in the the same Clock Polarity (CKP), then both controllers TRIS register) appropriately programmed as follows: would send and receive data at the same time. Whether the data is meaningful (or dummy data) • SDI is automatically controlled by the SPI module depends on the application software. This leads to • SDO must have the TRISC<5> bit cleared three scenarios for data transmission: • SCK (Master mode) must have the TRISC<3> bit • Master sends data–Slave sends dummy data cleared • Master sends data–Slave sends data • SCK (Slave mode) must have the TRISC<3> bit set • Master sends dummy data–Slave sends data • SS must have the TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. FIGURE 21-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2  2010-2017 Microchip Technology Inc. DS30009977G-page 285

PIC18F66K80 FAMILY 21.3.6 MASTER MODE shown in Figure21-3, Figure21-5 and Figure21-6, where the MSB is transmitted first. In Master mode, the The master can initiate the data transfer at any time SPI clock rate (bit rate) is user-programmable to be one because it controls the SCK. The master determines of the following: when the slave (Processor 1, Figure21-2) is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY) soon as the SSPBUF register is written to. If the SPI is • FOSC/64 (or 16 • TCY) only going to receive, the SDO output could be dis- • Timer2 output/2 abled (programmed as an input). The SSPSR register This allows a maximum data rate (at 64MHz) of will continue to shift in the signal present on the SDI pin 16Mbps. at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as Figure21-3 shows the waveforms for Master mode. if a normal received byte (interrupts and status bits When the CKE bit is set, the SDO data is valid before appropriately set). This could be useful in receiver there is a clock edge on SCK. The change of the input applications as a “Line Activity Monitor” mode. sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received The clock polarity is selected by appropriately data is shown. programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as FIGURE 21-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Four Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2 SSPBUF DS30009977G-page 286  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.3.7 SLAVE MODE transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable In Slave mode, the data is transmitted and received as depending on the application. the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode, with SS pin While in Slave mode, the external clock is supplied by control enabled (SSPCON1<3:0>=0100), the external clock source on the SCK pin. This external the SPI module will reset if the SS pin is set clock must meet the minimum high and low times as to VDD. specified in the electrical specifications. 2: If the SPI is used in Slave mode, with CKE While in Sleep mode, the slave can transmit/receive set, then the SS pin control must be data. When a byte is received, the device can be enabled. configured to wake-up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to 21.3.8 SLAVE SELECT a high level or clearing the SSPEN bit. SYNCHRONIZATION To emulate two-wire communication, the SDO pin can The SS pin allows a Synchronous Slave mode. The be connected to the SDI pin. When the SPI needs to SPI must be in Slave mode with the SS pin control operate as a receiver, the SDO pin can be configured enabled (SSPCON1<3:0> = 04h). When the SS pin is as an input. This disables transmissions from the SDO. low, transmission and reception are enabled and the The SDI can always be left as an input (SDI function) SDO pin is driven. When the SS pin goes high, the since it cannot create a bus conflict. SDO pin is no longer driven, even if in the middle of a FIGURE 21-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF  2010-2017 Microchip Technology Inc. DS30009977G-page 287

PIC18F66K80 FAMILY FIGURE 21-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF FIGURE 21-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF DS30009977G-page 288  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.3.9 OPERATION IN POWER-MANAGED 21.3.10 EFFECTS OF A RESET MODES A Reset disables the MSSP module and terminates the In SPI Master mode, module clocks may be operating current transfer. at a different speed than when in full-power mode; in 21.3.11 BUS MODE COMPATIBILITY the case of the Sleep mode, all clocks are halted. Table21-1 shows the compatibility between the In Idle modes, a clock is provided to the peripherals. standard SPI modes, and the states of the CKP and That clock can be from the primary clock source, the CKE control bits. secondary clock (SOSC oscillator) or the INTOSC source. See Section3.3 “Clock Sources and TABLE 21-1: SPI BUS MODES Oscillator Switching” for additional information. In most cases, the speed that the master clocks SPI Standard SPI Mode Control Bits State data is not important; however, this should be Terminology CKP CKE evaluated for each system. If MSSP interrupt is enabled, it can wake the controller 0, 0 0 1 from Sleep mode, or one of the Idle modes, when the 0, 1 0 0 master completes sending data. If an exit from Sleep or 1, 0 1 1 Idle mode is not desired, MSSP interrupts should be 1, 1 1 0 disabled. There is also an SMP bit which controls when the data If the Sleep mode is selected, all module clocks are is sampled. halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set, and if enabled, will wake the device. TABLE 21-2: REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 SSPBUF MSSP Receive Buffer/Transmit Register SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSPSTAT SMP CKE D/A P S R/W UA BF ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD Legend: Shaded cells are not used by the MSSP module in SPI mode.  2010-2017 Microchip Technology Inc. DS30009977G-page 289

PIC18F66K80 FAMILY 21.4 I2C Mode 21.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has seven registers for I2C master and slave functions (including general call operation. These are: support), and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPSR) – Not directly • Serial Clock (SCL) – RC3/REFO/SCL/SCK accessible • Serial Data (SDA) – RC4/SDA/SDI • MSSP Address Register (SSPADD) The user must configure these pins as inputs by setting • I2C Slave Address Mask Register (SSPMSK) the associated TRIS bits. SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSP- FIGURE 21-7: MSSP BLOCK DIAGRAM CON1 and SSPCON2 registers are readable and writ- (I2C™ MODE) able. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. Internal SSPSR is the shift register used for shifting data in or Data Bus out. SSPBUF is the buffer register to which data bytes Read Write are written to or read from. SSPADD contains the slave device address when the SSPBUF reg SCL MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, all eight bits of Shift SSPADD act as the Baud Rate Generator reload value. Clock SSPSR reg SSPMSK holds the slave address mask value when SDA MSb LSb the module is configured for 7-Bit Address Masking mode. While it is a separate register, it shares the same SFR address as SSPADD; it is only accessible when Match Detect Addr Match the SSPM<3:0> bits are specifically set to permit Address Mask access. Additional details are provided in Section21.4.3.4 “7-Bit Address Masking Mode”. In receive operations, SSPSR and SSPBUF together, SSPADD reg create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. Start and Set, Reset Stop bit Detect S, P bits During transmission, the SSPBUF is not (SSPSTAT reg) double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. DS30009977G-page 290  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 21-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enables SMBus specific inputs 0 = Disables SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.  2010-2017 Microchip Technology Inc. DS30009977G-page 291

PIC18F66K80 FAMILY REGISTER 21-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1001 = Load SSPMSK register at SSPADD SFR address(3,4) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note 1: When enabled, the SDA and SCL pins must be configured as inputs. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. 3: When SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address actually access the SSPMSK register. 4: This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is ‘1’). DS30009977G-page 292  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 21-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit Unused in Master mode. bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledged 0 = Acknowledged bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiates Acknowledge sequence on SDA and SCL pins and transmits ACKDT data bit; automatically cleared by hardware 0 = Acknowledge sequence is Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C™ 0 = Receive is Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiates Stop condition on SDA and SCL pins; automatically cleared by hardware 0 = Stop condition is Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiates Repeated Start condition on SDA and SCL pins; automatically cleared by hardware 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable bit(2) 1 = Initiates Start condition on SDA and SCL pins; automatically cleared by hardware 0 = Start condition Idle Note 1: The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written to (or writes to the SSPBUF are disabled).  2010-2017 Microchip Technology Inc. DS30009977G-page 293

PIC18F66K80 FAMILY REGISTER 21-6: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit 1 = Enables interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address is disabled bit 6 ACKSTAT: Acknowledge Status bit Unused in Slave mode. bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledged 0 = Acknowledged bit 4 ACKEN: Acknowledge Sequence Enable bit(1) 1 = Initiates Acknowledge sequence on SDA and SCL pins and transmits ACKDT data bit; automatically cleared by hardware 0 = Acknowledge sequence is Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(1) 1 = Enables Receive mode for I2C™ 0 = Receive is Idle bit 2 PEN: Stop Condition Enable bit(1) 1 = Initiates Stop condition on SDA and SCL pins; automatically cleared by hardware 0 = Stop condition is Idle bit 1 RSEN: Repeated Start Condition Enable bit(1) 1 = Initiates Repeated Start condition on SDA and SCL pins; automatically cleared by hardware 0 = Repeated Start condition is Idle bit 0 SEN: Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). REGISTER 21-7: SSPMSK: I2C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 MSK<7:0>: Slave Address Mask Select bit(2) 1 = Masking of corresponding bit of SSPADD is enabled 0 = Masking of corresponding bit of SSPADD is disabled Note 1: This register shares the same SFR address as SSPADD and is only addressable in select MSSP operating modes. See Section21.4.3.4 “7-Bit Address Masking Mode” for more details. 2: MSK0 is not used as a mask bit in 7-bit addressing. DS30009977G-page 294  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.2 OPERATION 21.4.3.1 Addressing The MSSP module functions are enabled by setting the Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON1<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C the 8 bits are shifted into the SSPSR register. All incom- ing bits are sampled with the rising edge of the clock operation. Four mode selection bits (SSPCON1<3:0>) allow one of the following I2C modes to be selected: (SCL) line. The value of register, SSPSR<7:1>, is com- pared to the value of the SSPADD register. The • I2C Master mode, clock address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. The MSSP Interrupt Flag bit, SSPIF, is set (and Idle interrupt is generated, if enabled) on the falling Selection of any I2C mode with the SSPEN bit set edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, In 10-Bit Addressing mode, two address bytes need to provided these pins are programmed as inputs by be received by the slave. The five Most Significant bits setting the appropriate TRISC bit. To ensure proper (MSbs) of the first address byte specify if this is a 10-bit operation of the module, pull-up resistors must be address. The R/W (SSPSTAT<2>) bit must specify a provided externally to the SCL and SDA pins. write so the slave device will receive the second address byte. For a 10-bit address, the first byte would 21.4.3 SLAVE MODE equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the In Slave mode, the SCL and SDA pins must be two MSbs of the address. The sequence of events for configured as inputs (TRISC<4:3> set). The MSSP 10-bit addressing is as follows, with Steps 7 through 9 module will override the input state with the output data for the slave-transmitter: when required (slave-transmitter). 1. Receive first (high) byte of address (bits, SSPIF, The I2C Slave mode hardware will always generate an BF and UA, are set on address match). interrupt on an address match. Address masking will 2. Update the SSPADD register with second (low) allow the hardware to generate an interrupt for more byte of address (clears bit, UA, and releases the than one address (up to 31 in 7-bit addressing and up SCL line). to 63 in 10-bit addressing). Through the mode select 3. Read the SSPBUF register (clears bit, BF) and bits, the user can also choose to interrupt on Start and clear flag bit, SSPIF. Stop bits. 4. Receive second (low) byte of address (bits, When an address is matched, or the data transfer after SSPIF, BF and UA, are set). an address match is received, the hardware auto- 5. Update the SSPADD register with the first (high) matically will generate the Acknowledge (ACK) pulse byte of address. If match releases SCL line, this and load the SSPBUF register with the received value will clear bit, UA. currently in the SSPSR register. 6. Read the SSPBUF register (clears bit, BF) and Any combination of the following conditions will cause clear flag bit SSPIF. the MSSP module not to give this ACK pulse: 7. Receive Repeated Start condition. • The Buffer Full bit, BF (SSPSTAT<0>), was set 8. Receive first (high) byte of address (bits, SSPIF before the transfer was received. and BF, are set). • The overflow bit, SSPOV (SSPCON1<6>), was 9. Read the SSPBUF register (clears bit, BF) and set before the transfer was received. clear flag bit, SSPIF. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit, SSPIF, is set. The BF bit is cleared by reading the SSPBUF register, while bit, SSPOV, is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing Parameter 100 and Parameter 101.  2010-2017 Microchip Technology Inc. DS30009977G-page 295

PIC18F66K80 FAMILY 21.4.3.2 Address Masking Modes of the incoming address. This allows the module to Acknowledge up to 31 addresses when using 7-bit Masking an address bit causes that bit to become a addressing, or 63 addresses with 10-bit addressing “don’t care”. When one address bit is masked, two (see Example21-2). This Masking mode is selected addresses will be Acknowledged and cause an when the MSSPMSK Configuration bit is programmed interrupt. It is possible to mask more than one address (‘0’). bit at a time, which greatly expands the number of addresses Acknowledged. The address mask in this mode is stored in the SSP- The I2C slave behaves the same way, whether address CON2 register, which stops functioning as a control register in I2C Slave mode (Register21-6). In 7-Bit masking is used or not. However, when address masking is used, the I2C slave can Acknowledge Addressing mode, address mask bits, ADMSK<5:1> (SSPCON2<5:1>), mask the corresponding address multiple addresses and cause interrupts. When this bits in the SSPADD register. For any ADMSKx bits that occurs, it is necessary to determine which address are set (ADMSK<n>=1), the corresponding address caused the interrupt by checking the SSPBUF. bit is ignored (SSPADD<n>=x). For the module to The PIC18F66K80 family of devices is capable of using issue an address Acknowledge, it is sufficient to match two different Address Masking modes in I2C slave only on addresses that do not have an active address operation: 5-Bit Address Masking and 7-Bit Address mask. Masking. The Masking mode is selected at device In 10-Bit Addressing mode, bits, ADMSK<5:2>, mask configuration using the MSSPMSK Configuration bit. the corresponding address bits in the SSPADD The default device configuration is 7-Bit Address register. In addition, ADMSK1 simultaneously masks Masking. the two LSbs of the address (SSPADD<1:0>). For any Both Masking modes, in turn, support address masking ADMSKx bits that are active (ADMSK<n>=1), the cor- of 7-bit and 10-bit addresses. The combination of responding address bit is ignored (SPxADD<n>=x). Masking modes and addresses provide different Also note that although in 10-Bit Addressing mode, the ranges of Acknowledgable addresses for each upper address bits reuse part of the SSPADD register combination. bits. The address mask bits do not interact with those While both Masking modes function in roughly the bits; they only affect the lower address bits. same manner, the way they use address masks are Note1: ADMSK1 masks the two Least Significant different. bits of the address. 21.4.3.3 5-Bit Address Masking Mode 2: The two Most Significant bits of the address are not affected by address As the name implies, 5-Bit Address Masking mode uses masking. an address mask of up to 5 bits to create a range of addresses to be Acknowledged, using bits, 5 through 1, EXAMPLE 21-2: ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE 7-Bit Addressing: SSPADD<7:1>= A0h (1010000) (SSPADD<0> is assumed to be ‘0’) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPADD<7:0> = A0h (10100000) (The two MSb of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh DS30009977G-page 296  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.3.4 7-Bit Address Masking Mode Setting or clearing mask bits in SSPMSK behaves in the opposite manner of the ADMSKx bits in 5-Bit Unlike 5-bit masking, 7-Bit Address Masking mode Address Masking mode. That is, clearing a bit in uses a mask of up to 8 bits (in 10-bit addressing) to SSPMSK causes the corresponding address bit to be define a range of addresses that can be Acknowl- masked; setting the bit requires a match in that edged, using the lowest bits of the incoming address. position. SSPMSK resets to all ‘1’s upon any Reset This allows the module to Acknowledge up to condition and, therefore, has no effect on the standard 127different addresses with 7-bit addressing, or MSSP operation until written with a mask value. 255with 10-bit addressing (see Example21-3). This mode is the default configuration of the module, which With 7-bit addressing, SSPMSK<7:1> bits mask the is selected when MSSPMSK is unprogrammed (‘1’). corresponding address bits in the SSPADD register. For any SSPMSK bits that are active (SSPMSK<n>=0), The address mask for 7-Bit Address Masking mode is the corresponding SSPADD address bit is ignored stored in the SSPMSK register, instead of the SSP- (SSPADD<n>=x). For the module to issue an address CON2 register. SSPMSK is a separate hardware regis- Acknowledge, it is sufficient to match only on ter within the module, but it is not directly addressable. addresses that do not have an active address mask. Instead, it shares an address in the SFR space with the SSPADD register. To access the SSPMSK register, it is With 10-bit addressing, SSPMSK<7:0> bits mask the necessary to select MSSP mode, ‘1001’ (SSP- corresponding address bits in the SSPADD register. CON1<3:0> = 1001) and then read or write to the loca- For any SSPMSK bits that are active (= 0), the tion of SSPADD. corresponding SSPADD address bit is ignored (SSPADD<n>=x). To use 7-Bit Address Masking mode, it is necessary to initialize SSPMSK with a value before selecting the I2C Note: The two Most Significant bits of the Slave Addressing mode. Thus, the required sequence address are not affected by address of events is: masking. 1. Select SSPMSK Access mode (SSP- CON2<3:0> = 1001). 2. Write the mask value to the appropriate SSPADD register address (FC8h). 3. Set the appropriate I2C Slave mode (SSP- CON2<3:0> = 0111 for 10-bit addressing, 0110 for 7-bit addressing). EXAMPLE 21-3: ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE 7-Bit Addressing: SSPADD<7:1> = 1010 000 SSPMSK<7:1> = 1111 001 Addresses Acknowledged = ACh, A8h, A4h, A0h 10-Bit Addressing: SSPADD<7:0> = 1010 0000 (The two MSb are ignored in this example since they are not affected) SSPMSK<5:1> = 1111 0011 Addresses Acknowledged = ACh, A8h, A4h, A0h  2010-2017 Microchip Technology Inc. DS30009977G-page 297

PIC18F66K80 FAMILY 21.4.3.5 Reception 21.4.3.6 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin SCL is held low regard- less of SEN (see Section21.4.4 “Clock Stretching” When the address byte overflow condition exists, then for more details). By stretching the clock, the master the no Acknowledge (ACK) pulse is given. An overflow will be unable to assert another clock pulse until the condition is defined as either bit, BF (SSPSTAT<0>), is slave is done preparing the transmit data. The transmit set or bit, SSPOV (SSPCON1<6>), is set. data must be loaded into the SSPBUF register, which An MSSP interrupt is generated for each data transfer also loads the SSPSR register. Then, the SCL pin byte. The interrupt flag bit, SSPIF, must be cleared in should be enabled by setting bit, CKP (SSPCON1<4>). software. The SSPSTAT register is used to determine The eight data bits are shifted out on the falling edge of the status of the byte. the SCL input. This ensures that the SDA signal is valid If SEN is enabled (SSPCON2<0> = 1), SCL will be held during the SCL high time (Figure21-10). low (clock stretch) following each data transfer. The The ACK pulse from the master-receiver is latched on clock must be released by setting bit, CKP the rising edge of the ninth SCL input pulse. If the SDA (SSPCON1<4>). See Section21.4.4 “Clock line is high (not ACK), then the data transfer is com- Stretching” for more details. plete. In this case, when the ACK is latched by the slave, the slave logic is reset and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, the SCL pin must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. DS30009977G-page 298  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 2 FIGURE 21-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 ec R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D5D4 34 ared in softwarPBUF is read D6 2 CleSS 7 D 1 K 9 = 0 AC W 8 R/ A1 7 2 )0 A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 eset to ‘’ wh0 SDAA7A6 SCL12S SSPIF (PIR1<3> or PIR3<7>) BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) CKP (SSPCON<4>) (CKP does not r  2010-2017 Microchip Technology Inc. DS30009977G-page 299

PIC18F66K80 FAMILY 2 FIGURE 21-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 pt. u D1 7 nterr n i D2 6 e a s u Data D3 5 e d ca Receiving D5D4 34 ared in softwarPBUF is read owledged an D6 2 CleSS Ackn e D7 1 ’).0 X will b K 9 a ‘ X. R/W = 0 AC 8 a ‘’ or 1 5.X.A3. X 7 her be 7.A6.A Receiving Address SDAA7A6A5XA3X SCL123456S SSPIF (PIR1<3> or PIR3<7>) BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) CKP (SSPCON<4>) (CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can eitx 2:In this example, an address equal to A DS30009977G-page 300  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 2 FIGURE 21-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o Data D1 7 Fr Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S S D0 8 m o Fr D1 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft eading CKP is set in software D7 1 SCL held lowwhile CPUresponds to SSPIF Clear by r K C A 9 1 = W 8 R/ 1 A 7 ess A2 6 Addr A3 5 g n eivi A4 4 ec R A5 3 >) A6A7 12 Data in sampled > or PIR3<7 0>) <4>) 3 < N DA CL S SPIF (PIR1< F (SSPSTAT KP (SSPCO S S S B C  2010-2017 Microchip Technology Inc. DS30009977G-page 301

PIC18F66K80 FAMILY FIGURE 21-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n eceive Dat D5D4 34 Cleared i R D6 2 7 D 1 K AC 9 0 D 8 Clock is held low untilClock is held low untilupdate of SSPADD has update of SSPADD has taken placetaken place Receive First Byte of AddressReceive Second Byte of AddressReceive Data ByteR/W = 0 ACKACKDA11110A9A8A7A6A5XA3A2XXD7D6D5D4D3D1D2 CL1234567891234567891234576S SPIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in softwareCleared in software F (SSPSTAT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag SPOV (SSPCON1<6>) A (SSPSTAT<1>) UA is set indicating thatCleared by hardware whenCleared by hardwarethe SSPADD needs to beSSPADD is updated with highwhen SSPADD is updatedupdatedbyte of addresswith low byte of address UA is set indicating thatSSPADD needs to beupdatedKP (SSPCON<4>) (CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can either be a ‘’ or a ‘’).x10 2:In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt. 3:Note that the Most Significant bits of the address are not affected by the bit masking. S S S B S U C DS30009977G-page 302  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 21-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n eceive Dat D5D4 34 Cleared i R D6 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKDA11110A9A8A7A6A5A4A3A2A1 CL1234567891234567S SPIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPSTAT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag SPOV (SSPCON1<6>) A (SSPSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdatedKP (SSPCON<4>) (CKP does not reset to ‘’ when SEN = )00 S S S B S U C  2010-2017 Microchip Technology Inc. DS30009977G-page 303

PIC18F66K80 FAMILY 2 FIGURE 21-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W = 1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/Receive First Byte of Address DA11110A9A8 CL12345678S SPIF (PIR1<3> or PIR3<7>) F (SSPSTAT<0>) SSPBUF is written withcontents of SSPSR A (SSPSTAT<1>) UA is set indicating thatthe SSPADD needs to beupdated KP (SSPCON1<4>) S S S B U C DS30009977G-page 304  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.4 CLOCK STRETCHING 21.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The 7-Bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause of the ninth clock if the BF bit is clear. This occurs the SCL pin to be held low at the end of each data regardless of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 21.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-Bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure21-10). ninth clock at the end of the ACK sequence, if the BF Note1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge automatically cleared, forcing the SCL output to be of the ninth clock, the CKP bit will not be held low. The CKP bit being cleared to ‘0’ will assert cleared and clock stretching will not the SCL line low. The CKP bit must be set in the user’s occur. ISR before reception is allowed to continue. By holding 2: The CKP bit can be set in software the SCL line low, the user has time to service the ISR regardless of the state of the BF bit. and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see 21.4.4.4 Clock Stretching for 10-Bit Slave Figure21-15). Transmit Mode Note1: If the user reads the contents of the In 10-Bit Slave Transmit mode, clock stretching is SSPBUF before the falling edge of the controlled during the first two address sequences by ninth clock, thus clearing the BF bit, the the state of the UA bit, just as it is in 10-Bit Slave CKP bit will not be cleared and clock Receive mode. The first two addresses are followed stretching will not occur. by a third address sequence, which contains the high-order bits of the 10-bit address and the R/W bit 2: The CKP bit can be set in software, set to ‘1’. After the third address sequence is regardless of the state of the BF bit. The performed, the UA bit is not set, the module is now user should be careful to clear the BF bit configured in Transmit mode and clock stretching is in the ISR before the next receive controlled by the BF flag as in 7-Bit Slave Transmit sequence in order to prevent an overflow mode (see Figure21-13). condition. 21.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs, and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence.  2010-2017 Microchip Technology Inc. DS30009977G-page 305

PIC18F66K80 FAMILY 21.4.4.5 Clock Synchronization and already asserted the SCL line. The SCL output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This When the CKP bit is cleared, the SCL output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCL (see SCL output low until the SCL output is already Figure21-14). sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 21-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX – 1 SCL Master device CKP asserts clock Master device deasserts clock WR SSPCON1 DS30009977G-page 306  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 2 FIGURE 21-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 ss e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 <7>) R3 >) A7 1 > or PI 0>) ON1<6 <4>) DA CLS SPIF (PIR1<3 F (SSPSTAT< SPOV (SSPC KP (SSPCON S S S B S C  2010-2017 Microchip Technology Inc. DS30009977G-page 307

PIC18F66K80 FAMILY FIGURE 21-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lobecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s D 8 1 D 7 e yte D2 6 war Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data B ACKD7D6D5D4D3D1D0D2D7D6D5D4D3 12345789612345 Cleared in softwareCleared in soft Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPADD register before thefalling edge of the ninth clock will have noeffect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of AddressW = 0 A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/ DA11110A9A8 CL12345678S SPIF (PIR1<3> or PIR3<7>) Cleared in software F (SSPSTAT<0>) SSPBUF is written withcontents of SSPSR SPOV (SSPCON1<6>) A (SSPSTAT<1>) UA is set indicating thatthe SSPADD needs to beupdated KP (SSPCON<4>) S S S B S U C DS30009977G-page 308  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), The addressing procedure for the I2C bus is such that the SSPIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device-specific or a general call address. Acknowledge. In 10-Bit Addressing mode, the SSPADD is required to The general call address is one of eight addresses be updated for the second half of the address to match reserved for specific purposes by the I2C protocol. It and the UA bit is set (SSPSTAT<1>). If the general call consists of all ‘0’s with R/W = 0. address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the The general call address is recognized when the second half of the address is not necessary, the UA bit General Call Enable bit, GCEN, is enabled (SSP- will not be set and the slave will begin receiving data CON2<7> set). Following a Start bit detect, eight bits after the Acknowledge (Figure21-17). are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 21-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is Compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK General Call Address SDA ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’  2010-2017 Microchip Technology Inc. DS30009977G-page 309

PIC18F66K80 FAMILY 21.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPMx bits in SSPCON1 and by setting of events. For instance, the user is not the SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware if the TRIS bits immediately write the SSPBUF register to are set. initiate transmission before the Start condition is complete. In this case, the Master mode of operation is supported by interrupt SSPBUF will not be written to and the generation on the detection of the Start and Stop WCOL bit will be set, indicating that a write conditions. The Stop (P) and Start (S) bits are cleared to the SSPBUF did not occur. from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is The following events will cause the MSSP Interrupt set, or the bus is Idle, with both the S and P bits clear. Flag bit, SSPIF, to be set (and MSSP interrupt, if In Firmware Controlled Master mode, user code enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmitted 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 21-18: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e SSPSR Detce) MSb LSb L ur e Oo abl WCk s SCL Receive En StAarcGtk beninot,ew Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset S, P (SSPSTAT), WCOL (SSPCON1); Clock Arbitration Set SSPIF, BCLIF; Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) End of XMIT/RCV DS30009977G-page 310  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.6.1 I2C™ Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the SSP- transmitted, 8 bits at a time. After each byte is transmit- CON2 register (SSPCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all 8 bits are logic ‘1’. Thus, the first byte transmitted is a 7-bit slave transmitted. address, followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDA, while SCL outputs the slave device and writes its value into the SSP- serial clock. Serial data is received, 8 bits at a time. CON2 register (SSPCON2<6>). After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator, used for the SPI mode 11. The user generates a Stop condition by setting operation, is used to set the SCL clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPCON2<2>). Section21.4.7 “Baud Rate” for more details. 12. Interrupt is generated once the Stop condition is complete.  2010-2017 Microchip Technology Inc. DS30009977G-page 311

PIC18F66K80 FAMILY 21.4.7 BAUD RATE Once the given operation is complete (i.e., transmis- In I2C Master mode, the Baud Rate Generator (BRG) sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin reload value is placed in the 8 bits of the SSPADD reg- will remain in its last state. ister (Figure21-19). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin Table21-3 demonstrates clock rates based on counting. The BRG counts down to 0 and stops until instruction cycles and the BRG value loaded into another reload has taken place. The BRG count is SSPADD. The SSPADD BRG value of 00h is not decremented twice per instruction cycle (TCY) on the supported. Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 21-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<6:0> SSPM<3:0> Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 21-3: I2C™ CLOCK RATE w/BRG FSCL FOSC FCY FCY * 2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz(1) 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz(1) 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz(1) 4 MHz 1 MHz 2 MHz 09h 100 kHz 16 MHz(2) 4 MHz 8 MHz 03h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. 2: A minimum 16-MHz FOSC is required for 1 MHz I2C. DS30009977G-page 312  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure21-20). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 21-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload  2010-2017 Microchip Technology Inc. DS30009977G-page 313

PIC18F66K80 FAMILY 21.4.8 I2C™ MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDA and SCL pins are already To initiate a Start condition, the user sets the Start sampled low or if during the Start condi- Enable bit, SEN (SSPCON2<0>). If the SDA and SCL tion, the SCL line is sampled low before pins are sampled high, the Baud Rate Generator is the SDA line is driven low, a bus collision reloaded with the contents of SSPADD<6:0> and starts occurs, the Bus Collision Interrupt Flag, its count. If SCL and SDA are both sampled high when BCLIF, is set, the Start condition is aborted the Baud Rate Generator times out (TBRG), the SDA and the I2C module is reset into its Idle pin is driven low. The action of the SDA being driven state. low while SCL is high is the Start condition and causes 21.4.8.1 WCOL Status Flag the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of If the user writes the SSPBUF when a Start sequence SSPADD<6:0> and resumes its count. When the Baud is in progress, the WCOL bit is set and the contents of Rate Generator times out (TBRG), the SEN bit (SSP- the buffer are unchanged (the write doesn’t occur). CON2<0>) will be automatically cleared by hardware. Note: Because queueing of events is not The Baud Rate Generator is suspended, leaving the allowed, writing to the lower 5 bits of SSP- SDA line held low and the Start condition is complete. CON2 is disabled until the Start condition is complete. FIGURE 21-21: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S DS30009977G-page 314  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.9 I2C™ MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDA is sampled low when SCL goes the SCL pin is asserted low. When the SCL pin is from low-to-high. sampled low, the Baud Rate Generator is loaded with • SCL goes low before SDA is the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one Baud asserted low. This may indicate that Rate Generator count (TBRG). When the Baud Rate another master is attempting to Generator times out, and if SDA is sampled high, the transmit a data ‘1’. SCL pin will be deasserted (brought high). When SCL Immediately following the SSPIF bit getting set, the user is sampled high, the Baud Rate Generator is reloaded may write the SSPBUF with the 7-bit address in 7-bit with the contents of SSPADD<6:0> and begins mode or the default first address in 10-bit mode. After the counting. SDA and SCL must be sampled high for one first eight bits are transmitted and an ACK is received, TBRG. This action is then followed by assertion of the the user may then transmit an additional eight bits of SDA pin (SDA = 0) for one TBRG while SCL is high. address (10-bit mode) or eight bits of data (7-bit mode). Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will 21.4.9.1 WCOL Status Flag not be reloaded, leaving the SDA pin held low. As soon If the user writes the SSPBUF when a Repeated Start as a Start condition is detected on the SDA and SCL sequence is in progress, the WCOL is set and the pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit contents of the buffer are unchanged (the write doesn’t will not be set until the Baud Rate Generator has timed occur). out. Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSP- CON2 is disabled until the Repeated Start condition is complete. FIGURE 21-22: REPEATED START CONDITION WAVEFORM S bit set by hardware SDA = 1, At completion of Start bit, Write to SSPCON2 occurs here: SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG SDA 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPBUF occurs here end of XMIT TBRG SCL TBRG Sr = Repeated Start  2010-2017 Microchip Technology Inc. DS30009977G-page 315

PIC18F66K80 FAMILY 21.4.10 I2C™ MASTER MODE The user should verify that the WCOL bit is clear after TRANSMISSION each write to SSPBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in software. Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by 21.4.10.3 ACKSTAT Status Flag simply writing a value to the SSPBUF register. This In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is action will set the Buffer Full flag bit, BF, and allow the cleared when the slave has sent an Acknowledge Baud Rate Generator to begin counting and start the (ACK=0) and is set when the slave does not Acknowl- next transmission. Each bit of address/data will be edge (ACK = 1). A slave sends an Acknowledge when shifted out onto the SDA pin after the falling edge of it has recognized its address (including a general call), SCL is asserted (see data hold time specification or when the slave has properly received its data. Parameter106). SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid 21.4.11 I2C™ MASTER MODE RECEPTION before SCL is released high (see data setup time spec- ification Parameter 107). When the SCL pin is released Master mode reception is enabled by programming the high, it is held that way for TBRG. The data on the SDA Receive Enable bit, RCEN (SSPCON2<3>). pin must remain stable for that duration and some hold Note: The MSSP module must be in an inactive time after the next falling edge of SCL. After the eighth state before the RCEN bit is set or the bit is shifted out (the falling edge of the eighth clock), RCEN bit will be disregarded. the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to The Baud Rate Generator begins counting, and on respond with an ACK bit during the ninth bit time if an each rollover, the state of the SCL pin changes address match occurred, or if data was received prop- (high-to-low/low-to-high) and data is shifted into the erly. The status of ACK is written into the ACKDT bit on SSPSR. After the falling edge of the eighth clock, the the falling edge of the ninth clock. If the master receives receive enable flag is automatically cleared, the con- an Acknowledge, the Acknowledge Status bit, tents of the SSPSR are loaded into the SSPBUF, the ACKSTAT, is cleared; if not, the bit is set. After the ninth BF flag bit is set, the SSPIF flag bit is set and the Baud clock, the SSPIF bit is set and the master clock (Baud Rate Generator is suspended from counting, holding Rate Generator) is suspended until the next data byte SCL low. The MSSP is now in Idle state awaiting the is loaded into the SSPBUF, leaving SCL low and SDA next command. When the buffer is read by the CPU, unchanged (Figure21-23). the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception After the write to the SSPBUF, each bit of the address by setting the Acknowledge Sequence Enable bit, will be shifted out on the falling edge of SCL until all ACKEN (SSPCON2<4>). seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will 21.4.11.1 BF Status Flag deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth In receive operation, the BF bit is set when an address clock, the master will sample the SDA pin to see if the or data byte is loaded into SSPBUF from SSPSR. It is address was recognized by a slave. The status of the cleared when the SSPBUF register is read. ACK bit is loaded into the ACKSTAT status bit (SSP- 21.4.11.2 SSPOV Status Flag CON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF flag is set, the In receive operation, the SSPOV bit is set when 8 bits BF flag is cleared and the Baud Rate Generator is are received into the SSPSR and the BF flag bit is turned off until another write to the SSPBUF takes already set from a previous reception. place, holding SCL low and allowing SDA to float. 21.4.11.3 WCOL Status Flag 21.4.10.1 BF Status Flag If the user writes the SSPBUF when a receive is In Transmit mode, the BF bit (SSPSTAT<0>) is set already in progress (i.e., SSPSR is still shifting in a data when the CPU writes to SSPBUF and is cleared when byte), the WCOL bit is set and the contents of the buffer all 8 bits are shifted out. are unchanged (the write doesn’t occur). 21.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur) after 2TCY after the SSPBUF write. If SSPBUF is rewritten within 2 TCY, the WCOL bit is set and SSPBUF is updated. This may result in a corrupted transfer. DS30009977G-page 316  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 21-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl >) A 2<6 D0 8 e N n slave, clear ACKSTAT bit (SSPCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared in software service routifrom MSSP interrupt SSPBUF is written in software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re R/W = 0 A1A ss and R/W, 789 d by hardware ave A2 ddre 6 eare PCON2<0> (SEN = ),1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared in software SSPBUF written After Start condition, SEN cl Sn So Write Start c S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W  2010-2017 Microchip Technology Inc. DS30009977G-page 317

PIC18F66K80 FAMILY FIGURE 21-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) et ACKEN, start Acknowledge sequence,DA = ACKDT = 1 PEN bit = 1N clearedwritten herematically D0ACK Bus masterACK is not sentterminatestransfer98PSet SSPIF at endof receiveSet SSPIF interruptat end of Acknowledgesequence Set P bit (SSPSTAT<4>)Cleared insoftwareand SSPIF SSPOV is set becauseSSPBUF is still full SS RCEauto D1 7 CLK Write to SSPCON2<4>to start Acknowledge sequence,SDA = ACKDT (SSPCON2<5>) = 0 ACK from master,ster configured as a receiverSDA = ACKDT = 0programming SSPCON2<3> (RCEN = )1 RCEN = , start1RCEN clearednext receiveautomatically Receiving Data from SlaveReceiving Data from SlaveACKD2D5D2D5D3D4D6D7D3D4D6D7D1D0 678956512343124 Data shifted in on falling edge of Set SSPIF interruptSet SSPIF interruptat end of receiveat end of Acknowledgesequence Cleared in softwareCleared in softwareCleared in software Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF Maby ACK from Slave R/W = 1A1ACK 798 PCON2<0> (SEN = ),1condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2 361245 Cleared in software Write to SSbegin Start SDA SCLS SSPIF SDA = , SCL = ,01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN DS30009977G-page 318  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.12 ACKNOWLEDGE SEQUENCE 21.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN (SSP- bit, PEN (SSPCON2<2>). At the end of a CON2<4>). When this bit is set, the SCL pin is pulled low receive/transmit, the SCL line is held low after the and the contents of the Acknowledge data bit are pre- falling edge of the ninth clock. When the PEN bit is set, sented on the SDA pin. If the user wishes to generate an the master will assert the SDA line low. When the SDA Acknowledge, then the ACKDT bit should be cleared. If line is sampled low, the Baud Rate Generator is not, the user should set the ACKDT bit before starting an reloaded and counts down to 0. When the Baud Rate Acknowledge sequence. The Baud Rate Generator then Generator times out, the SCL pin will be brought high counts for one rollover period (TBRG) and the SCL pin is and one TBRG (Baud Rate Generator rollover count) deasserted (pulled high). When the SCL pin is sampled later, the SDA pin will be deasserted. When the SDA high (clock arbitration), the Baud Rate Generator counts pin is sampled high while SCL is high, the P bit for TBRG; the SCL pin is then pulled low. Following this, (SSPSTAT<4>) is set. A TBRG later, the PEN bit is the ACKEN bit is automatically cleared, the Baud Rate cleared and the SSPIF bit is set (Figure21-26). Generator is turned off and the MSSP module then goes 21.4.13.1 WCOL Status Flag into an inactive state (Figure21-25). If the user writes the SSPBUF when a Stop sequence 21.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 21-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2, ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in SSPIF set at Cleared in software the end of receive software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 21-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period.  2010-2017 Microchip Technology Inc. DS30009977G-page 319

PIC18F66K80 FAMILY 21.4.14 SLEEP OPERATION 21.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 21.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high, and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin=0, 21.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF, and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure21-27). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus bus is busy, enabling the MSSP interrupt will generate is free, the user can resume communication by asserting the interrupt when the Stop condition occurs. a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the con- expected output level. This check is performed in dition is aborted, the SDA and SCL lines are deasserted hardware with the result placed in the BCLIF bit. and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision The states where arbitration can be lost are: Interrupt Service Routine, and if the I2C bus is free, the • Address Transfer user can resume communication by asserting a Start • Data Transfer condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 21-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data doesn’t match what is driven while SCL = 0 by another source by the master; bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS30009977G-page 320  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure21-30). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL is sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure21-28). counts down to 0. If the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure21-29). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a fac- pins are monitored. tor during a Start condition is that no two bus masters can assert a Start condition If the SDA pin is already low, or the SCL pin is already at the exact same time. Therefore, one low, then all of the following occur: master will always assert SDA before the • the Start condition is aborted, other. This condition does not cause a bus • the BCLIF flag is set and collision because the two masters must be • the MSSP module is reset to its inactive state allowed to arbitrate the first address (Figure21-28) following the Start condition. If the address The Start condition begins with the SDA and SCL pins is the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 21-28: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 MSSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software  2010-2017 Microchip Technology Inc. DS30009977G-page 321

PIC18F66K80 FAMILY FIGURE 21-29: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 21-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software DS30009977G-page 322  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 21.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure21-31). If SDA is sampled high, the BRG is During a Repeated Start condition, a bus collision reloaded and begins counting. If SDA goes from occurs if: high-to-low before the BRG times out, no bus collision a) A low level is sampled on SDA when SCL goes occurs because no two masters can assert SDA at from a low level to a high level. exactly the same time. b) SCL goes low before SDA is asserted low, If SCL goes from high-to-low before the BRG times out indicating that another master is attempting to and SDA has not already been asserted, a bus collision transmit a data ‘1’. occurs. In this case, another master is attempting to When the user deasserts SDA and the pin is allowed to transmit a data ‘1’ during the Repeated Start condition float high, the BRG is loaded with SSPADD<6:0> and (see Figure21-32). counts down to 0. The SCL pin is then deasserted and If, at the end of the BRG time-out, both SCL and SDA when sampled high, the SDA pin is sampled. are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 21-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 21-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF  2010-2017 Microchip Technology Inc. DS30009977G-page 323

PIC18F66K80 FAMILY 21.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure21-33). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure21-34). FIGURE 21-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 21-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’ DS30009977G-page 324  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 21-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR2 OSCFIF — — — BCLIF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — — — BCLIE HLVDIE TMR3IE TMR3GIE IPR2 OSCFIP — — — BCLIP HLVDIP TMR3IP TMR3GIP TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 SSPBUF MSSP Receive Buffer/Transmit Register SSPADD MSSP Address Register (I2C™ Slave mode), MSSP Baud Rate Reload Register (I2C Master mode) SSPMSK(1) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN SSPSTAT SMP CKE D/A P S R/W UA BF PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. Note 1: SSPMSK shares the same address in SFR space as SSPADD, but is only accessible in certain I2C™ Slave operating modes in 7-Bit Masking mode. See Section21.4.3.4 “7-Bit Address Masking Mode” for more details. 2: Alternate bit definitions for use in I2C Slave mode operations only.  2010-2017 Microchip Technology Inc. DS30009977G-page 325

PIC18F66K80 FAMILY 22.0 ENHANCED UNIVERSAL All members of the PIC18F66K80 family are equipped SYNCHRONOUS with two independent EUSART modules, referred to as EUSART1 and EUSART2. They can be configured in ASYNCHRONOUS RECEIVER the following modes: TRANSMITTER (EUSART) • Asynchronous (full duplex) with: The Enhanced Universal Synchronous Asynchronous - Auto-wake-up on character reception Receiver Transmitter (EUSART) module is one of two - Auto-baud calibration serial I/O modules. (Generically, the EUSART is also - 12-bit Break character transmission known as a Serial Communications Interface or SCI.) • Synchronous – Master (half duplex) with The EUSART can be configured as a full-duplex, selectable clock polarity asynchronous system that can communicate with • Synchronous – Slave (half duplex) with selectable peripheral devices, such as CRT terminals and clock polarity personal computers. It can also be configured as a The pins of EUSART1 and EUSART2 are multiplexed half-duplex synchronous system that can communicate with the functions with the following ports, depending with peripheral devices, such as A/D or D/A integrated on the device pin count. See Table22-1. circuits, serial EEPROMs, etc. The Enhanced USARTx modules implement additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break recep- tion and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN/J2602 bus) systems. TABLE 22-1: CONFIGURING EUSARTx PINS(1) EUSART1 EUSART2 Pin Count Port Pins Port Pins RC6/TX1/CK1 and RB6/PGC/TX2/CK2/KBI2 and 28-pin PORTC PORTB RC7/RX1/DT1 RB7/PGD/T3G/RX2/DT2/KBI3 RC6/TX1/CK1 and RD6/TX2/CK2/P1C/PSP6 and 40/44-pin PORTC PORTD RC7/RX1/DT1 RD7/RX2/DT2/P1D/PSP7 RG3/TX1/CK1 and 64-pin PORTG PORTE RE7/TX2/CK2 and RE6/RX2/DT2 RG0/RX1/DT1 Note 1: The EUSARTx control will automatically reconfigure the pin from input to output as needed. In order to configure the pins as an EUSARTx: • For EUSART2: • For EUSART1: - SPEN (RCSTA2<7>) must be set (= 1) - SPEN (RCSTA1<7>) must be set (= 1) - TRISx<x> must be set (= 1) - TRISx<x> must be set (= 1) - For Asynchronous and Synchronous Master modes, TRISx<x> must be cleared (= 0) - For Asynchronous and Synchronous Master modes, TRISx<x> must be cleared (= 0) - For Synchronous Slave mode, TRISx<x> must be set (= 1) - For Synchronous Slave mode, TRISx<x> must be set (= 1) DS30009977G-page 326  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 22.1 EUSARTx Control Registers Note: Throughout this section, references to The operation of each Enhanced USARTx module is register and bit names that may be asso- controlled through three registers: ciated with a specific EUSART module are referred to generically by the use of ‘x’ in • Transmit Status and Control (TXSTAx) place of the specific module number. • Receive Status and Control (RCSTAx) Thus, “RCSTAx” might refer to the • Baud Rate Control (BAUDCONx) Receive Status register for either These are detailed on the following pages in EUSART1 or EUSART2. Register22-1, Register22-2 and Register22-3, respectively. REGISTER 22-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit is enabled 0 = Transmit is disabled bit 4 SYNC: EUSARTx Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Sends Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission is completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2010-2017 Microchip Technology Inc. DS30009977G-page 327

PIC18F66K80 FAMILY REGISTER 22-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port is disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection; enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection; all bytes are received and the ninth bit can be used as a parity bit Asynchronous mode 9-Bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be cleared by reading the RCREGx register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS30009977G-page 328  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 22-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-x R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 RXDTP: Received Data Polarity Select bit (Asynchronous mode only) Asynchronous mode: 1 = Receive data (RXx) is inverted 0 = Receive data (RXx) is not inverted bit 4 TXCKP: Clock and Data Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is a low level 0 = Idle state for transmit (TXx) is a high level Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value is ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSARTx will continue to sample the RXx pin: interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin is not monitored or rising edge is detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enables baud rate measurement on the next character: requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed Synchronous mode: Unused in this mode.  2010-2017 Microchip Technology Inc. DS30009977G-page 329

PIC18F66K80 FAMILY 22.2 Baud Rate Generator (BRG) the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate The BRG is a dedicated, 8-bit or 16-bit generator that for a fast oscillator frequency. supports both the Asynchronous and Synchronous Writing a new value to the SPBRGHx:SPBRGx regis- modes of the EUSARTx. By default, the BRG operates ters causes the BRG timer to be reset (or cleared). This in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) ensures the BRG does not wait for a timer overflow selects 16-bit mode. before outputting the new baud rate. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits, 22.2.1 OPERATION IN POWER-MANAGED BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>), MODES also control the baud rate. In Synchronous mode, BRGH The device clock is used to generate the desired baud is ignored. Table22-2 shows the formula for computation rate. When one of the power-managed modes is of the baud rate for different EUSARTx modes which only entered, the new clock source may be operating at a apply in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRGHx:SPBRGx register pair. integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table22-2. From this, 22.2.2 SAMPLING the error in baud rate can be determined. An example The data on the RXx pin (either RC7/CANRX/RX1/DT1 calculation is shown in Example22-1. Typical baud rates or RB7/PGD/T3G/RX2/DT2/KBI3) is sampled three and error values for the various Asynchronous modes times by a majority detect circuit to determine if a high are shown in Table22-3. It may be advantageous to use or a low level is present at the RXx pin. TABLE 22-2: BAUD RATE FORMULAS Configuration Bits BRG/EUSARTx Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair DS30009977G-page 330  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY EXAMPLE 22-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 22-3: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register Low Byte PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.  2010-2017 Microchip Technology Inc. DS30009977G-page 331

PIC18F66K80 FAMILY TABLE 22-4: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 64.000 MHz FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — 1.221 1.73 255 1.202 0.16 129 2.4 — — — 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 9.6 9.615 0.16 103 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 19.2 19.231 0.16 51 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 57.6 58.824 2.13 16 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 115.2 111.111 -3.55 8 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.201 -0.16 103 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.403 -0.16 51 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 9.615 -0.16 12 8.929 -6.99 6 — — — — — — 19.2 — — — 20.833 8.51 2 — — — — — — 57.6 — — — 62.500 8.51 0 — — — — — — 115.2 — — — 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 64.000 MHz FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — — — — 2.441 1.73 255 9.6 — — — 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 19.2 19.417 1.13 207 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 57.6 59.701 3.65 68 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 115.2 121.212 5.22 34 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — 0.300 -0.16 207 1.2 — — — 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.403 -0.16 207 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 -0.16 51 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.230 -0.16 25 19.231 0.16 12 — — — — — — 57.6 55.555 3.55 8 62.500 8.51 3 — — — — — — 115.2 — — — 125.000 8.51 1 — — — — — — DS30009977G-page 332  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 22-4: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 64.000 MHz FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 13332 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 1.2 1.200 0.00 3332 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 2.4 2.400 0.00 1666 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 9.6 9.592 -0.08 416 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 19.2 19.417 1.13 207 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 57.6 59.701 3.65 68 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 115.2 121.212 5.22 34 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 -0.04 1665 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.201 -0.16 415 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.403 -0.16 207 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 -0.16 51 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.230 -0.16 25 19.231 0.16 12 — — — — — — 57.6 55.555 3.55 8 62.500 8.51 3 — — — — — — 115.2 — — — 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 64.000 MHz FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 53332 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 1.2 1.200 0.00 13332 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 2.4 2.400 0.00 6666 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 9.6 9.598 -0.02 1666 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 19.2 19.208 0.04 832 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 57.6 57.348 -0.44 278 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 115.2 115.108 -0.08 138 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 -0.01 6665 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 -0.04 1665 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.400 -0.04 832 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 -0.16 207 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.230 -0.16 103 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 57.142 0.79 34 58.824 2.12 16 55.555 3.55 8 — — — 115.2 117.647 -2.12 16 111.111 -3.55 8 — — — — — —  2010-2017 Microchip Technology Inc. DS30009977G-page 333

PIC18F66K80 FAMILY 22.2.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USARTx modules support the auto- Auto-Baud Rate Detection will occur on matic detection and calibration of baud rate. This the byte following the Break character. feature is active only in Asynchronous mode and while 2: It is up to the user to determine that the the WUE bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure22-1) begins whenever a Start bit is received Some combinations of oscillator fre- and the ABDEN bit is set. The calculation is quency and EUSARTx baud rates are not self-averaging. possible due to bit error rates. Overall system timing and communication baud In the Auto-Baud Rate Detect (ABD) mode, the clock to rates must be taken into consideration the BRG is reversed. Rather than the BRG clocking the when using the Auto-Baud Rate Detection incoming RXx signal, the RXx signal is timing the BRG. feature. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming 3: To maximize baud rate range, if that serial byte stream. feature is used it is recommended that the BRG16 bit (BAUDCONx<3>) be set. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value, 55h (ASCII TABLE 22-5: BRG COUNTER “U”, which is also the LIN/J2602 bus Sync character), in CLOCK RATES order to calculate the proper bit rate. The measurement BRG16 BRGH BRG Counter Clock is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incom- 0 0 FOSC/512 ing signal. After a Start bit, the SPBRGx begins counting 0 1 FOSC/128 up, using the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth 1 0 FOSC/128 rising edge, an accumulated value totalling the proper 1 1 FOSC/32 BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond 22.2.3.1 ABD and EUSARTx Transmission to the Stop bit), the ABDEN bit is automatically cleared. Since the BRG clock is reversed during ABD acquisi- If a rollover of the BRG occurs (an overflow from FFFFh tion, the EUSARTx transmitter cannot be used during to 0000h), the event is trapped by the ABDOVF status ABD. This means that whenever the ABDEN bit is set, bit (BAUDCONx<7>). It is set in hardware by BRG roll- TXREGx cannot be written to. Users should also overs and can be set or cleared by the user in software. ensure that ABDEN does not become set during a ABD mode remains active after rollover events and the transmit sequence. Failing to do this may result in ABDEN bit remains set (Figure22-2). unpredictable EUSARTx operation. While calibrating the baud rate period, the BRG regis- ters are clocked at 1/8th the preconfigured clock rate. The BRG clock will be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG1 and SPBRGH1 as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table22-5 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSARTx state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. DS30009977G-page 334  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 22-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RXx pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSARTx module to be configured in Asynchronous mode and WUE=0. FIGURE 22-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h  2010-2017 Microchip Technology Inc. DS30009977G-page 335

PIC18F66K80 FAMILY 22.3 EUSARTx Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is The Asynchronous mode of operation is selected by empty and the TXxIF flag bit is set. This interrupt can be clearing the SYNC bit (TXSTAx<4>). In this mode, the enabled or disabled by setting or clearing the interrupt EUSARTx uses standard Non-Return-to-Zero (NRZ) enable bit, TXxIE. TXxIF will be set regardless of the format (one Start bit, eight or nine data bits and one Stop state of TXxIE; it cannot be cleared in software. TXxIF is bit). The most common data format is 8 bits. An on-chip, also not cleared immediately upon loading TXREGx, but dedicated 8-bit/16-bit Baud Rate Generator can be used becomes valid in the second instruction cycle following to derive standard baud rate frequencies from the the load instruction. Polling TXxIF immediately following oscillator. a load of TXREGx will return invalid results. The EUSARTx transmits and receives the LSb first. The While TXxIF indicates the status of the TXREGx regis- EUSARTx’s transmitter and receiver are functionally independent but use the same data format and baud ter; another bit, TRMT (TXSTAx<1>), shows the status rate. The Baud Rate Generator produces a clock, either of the TSR register. TRMT is a read-only bit which is set x16 or x64 of the bit shift rate, depending on the BRGH when the TSR register is empty. No interrupt logic is and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). tied to this bit so the user has to poll this bit in order to Parity is not supported by the hardware but can be determine if the TSR register is empty. implemented in software and stored as the 9th data bit. Note1: The TSR register is not mapped in data When operating in Asynchronous mode, the EUSARTx memory, so it is not available to the user. module consists of the following important elements: 2: Flag bit, TXxIF, is set when enable bit, • Baud Rate Generator TXEN, is set. • Sampling Circuit To set up an Asynchronous Transmission: • Asynchronous Transmitter • Asynchronous Receiver 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the • Auto-Wake-up on Sync Break Character BRGH and BRG16 bits, as required, to achieve • 12-Bit Break Character Transmit the desired baud rate. • Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 22.3.1 EUSARTx ASYNCHRONOUS 3. If interrupts are desired, set enable bit, TXxIE. TRANSMITTER 4. If 9-bit transmission is desired, set transmit bit, The EUSARTx transmitter block diagram is shown in TX9. Can be used as address/data bit. Figure22-3. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit, TXEN, (Serial) Shift Register (TSR). The Shift register obtains which will also set bit, TXxIF. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREGx. The TXREGx register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the Stop 7. Load data to the TXREGx register (starts bit has been transmitted from the previous load. As transmission). soon as the Stop bit is transmitted, the TSR is loaded 8. If using interrupts, ensure that the GIE and PEIE with new data from the TXREGx register (if available). bits (INTCON<7:6>) are set. FIGURE 22-3: EUSARTx TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register TXx pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator TX9D DS30009977G-page 336  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 22-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 22-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXxIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions.  2010-2017 Microchip Technology Inc. DS30009977G-page 337

PIC18F66K80 FAMILY TABLE 22-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register Low Byte RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG2 EUSART2 Transmit Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register Low Byte PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. DS30009977G-page 338  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 22.3.2 EUSARTx ASYNCHRONOUS 22.3.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure22-6. This mode would typically be used in RS-485 systems. The data is received on the RXx pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGHx:SPBRGx registers for whereas the main receive serial shifter operates at the the appropriate baud rate. Set or clear the bit rate or at FOSC. This mode would typically be used BRGH and BRG16 bits, as required, to achieve in RS-232 systems. the desired baud rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRGHx:SPBRGx registers for the SYNC bit and setting the SPEN bit. the appropriate baud rate. Set or clear the 3. If interrupts are required, set the RCEN bit and BRGH and BRG16 bits, as required, to achieve select the desired priority level with the RCxIP bit. the desired baud rate. 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit, SYNC, and setting bit, SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit, RCxIE. 7. The RCxIF bit will be set when reception is 4. If 9-bit reception is desired, set bit, RX9. complete. The interrupt will be Acknowledged if 5. Enable the reception by setting bit, CREN. the RCxIE and GIE bits are set. 6. Flag bit, RCxIF, will be set when reception is 8. Read the RCSTAx register to determine if any complete and an interrupt will be generated if error occurred during reception, as well as read enable bit, RCxIE, was set. bit 9 of data (if applicable). 7. Read the RCSTAx register to get the 9th bit (if 9. Read RCREGx to determine if the device is enabled) and determine if any error occurred being addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREGx register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. FIGURE 22-6: EUSARTx RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx  o6r4 MSb RSR Register LSb  16 or Stop (8) 7  1 0 Start Baud Rate Generator  4 RX9 Pin Buffer Data and Control Recovery RXx RX9D RCREGx Register FIFO SPEN 8 Interrupt RCxIF Data Bus RCxIE  2010-2017 Microchip Technology Inc. DS30009977G-page 339

PIC18F66K80 FAMILY FIGURE 22-7: ASYNCHRONOUS RECEPTION RXx (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREGx RCREGx Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. TABLE 22-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG1 EUSART1 Receive Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG2 EUSART2 Receive Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register Low Byte PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. DS30009977G-page 340  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 22.3.4 AUTO-WAKE-UP ON SYNC BREAK 22.3.4.1 Special Considerations Using CHARACTER Auto-Wake-up During Sleep mode, all clocks to the EUSARTx are Since auto-wake-up functions by sensing rising edge suspended. Because of this, the Baud Rate Generator transitions on RXx/DTx, information with any state is inactive and a proper byte reception cannot be per- changes before the Stop bit may signal a false formed. The auto-wake-up feature allows the controller End-of-Character (EOC) and cause data or framing to wake-up due to activity on the RXx/DTx line while the errors. To work properly, therefore, the initial character EUSARTx is operating in Asynchronous mode. in the transmission must be all ‘0’s. This can be 00h (8bytes) for standard RS-232 devices or 000h (12 bits) The auto-wake-up feature is enabled by setting the for LIN/J2602 bus. WUE bit (BAUDCONx<1>). Once set, the typical receive sequence on RXx/DTx is disabled and the Oscillator start-up time must also be considered, EUSARTx remains in an Idle state, monitoring for a especially in applications using oscillators with longer wake-up event independent of the CPU mode. A start-up intervals (i.e., HS or HSPLL mode). The Sync wake-up event consists of a high-to-low transition on Break (or Wake-up Signal) character must be of the RXx/DTx line. (This coincides with the start of a sufficient length and be followed by a sufficient interval Sync Break or a Wake-up Signal character for the to allow enough time for the selected oscillator to start LIN/J2602 protocol.) and provide proper initialization of the EUSARTx. Following a wake-up event, the module generates an RCxIF interrupt. The interrupt is generated synchro- nously to the Q clocks in normal operating modes (Figure22-8) and asynchronously if the device is in Sleep mode (Figure22-9). The interrupt condition is cleared by reading the RCREGx register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RXx line following the wake-up event. At this point, the EUSARTx module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over.  2010-2017 Microchip Technology Inc. DS30009977G-page 341

PIC18F66K80 FAMILY 22.3.4.2 Special Considerations Using The fact that the WUE bit has been cleared (or is still the WUE Bit set) and the RCxIF flag is set should not be used as an indicator of the integrity of the data in RCREGx. Users The timing of WUE and RCxIF events may cause some should consider implementing a parallel method in confusion when it comes to determining the validity of firmware to verify received data integrity. received data. As noted, setting the WUE bit places the EUSARTx in an Idle mode. The wake-up event causes To assure that no actual data is lost, check the RCIDL a receive interrupt by setting the RCxIF bit. The WUE bit bit to verify that a receive operation is not in process. If is cleared after this when a rising edge is seen on a receive operation is not occurring, the WUE bit may RXx/DTx. The interrupt condition is then cleared by then be set just prior to entering the Sleep mode. reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. FIGURE 22-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note1:The EUSARTx remains in Idle while the WUE bit is set. FIGURE 22-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RXx/DTx Line Note 1 RCxIF Cleared due to user read of RCREGx SLEEP Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSARTx remains in Idle while the WUE bit is set. DS30009977G-page 342  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 22.3.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSARTx for the desired mode. The EUSARTx module has the capability of sending 2. Set the TXEN and SENDB bits to set up the the special Break character sequences that are Break character. required by the LIN/J2602 bus standard. The Break 3. Load the TXREGx with a dummy character to character transmit consists of a Start bit, followed by initiate transmission (the value is ignored). twelve ‘0’ bits and a Stop bit. The Frame Break charac- 4. Write ‘55h’ to TXREGx to load the Sync ter is sent whenever the SENDB and TXEN bits character into the transmit FIFO buffer. (TXSTAx<3> and TXSTAx<5>, respectively) are set 5. After the Break has been sent, the SENDB bit is while the Transmit Shift Register is loaded with data. reset by hardware. The Sync character now Note that the value of data written to TXREGx will be transmits in the preconfigured mode. ignored and all ‘0’s will be transmitted. When the TXREGx becomes empty, as indicated by The SENDB bit is automatically reset by hardware after the TXxIF, the next data byte can be written to the corresponding Stop bit is sent. This allows the user TXREGx. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 22.3.6 RECEIVING A BREAK CHARACTER character in the LIN/J2602 specification). The Enhanced USARTx modules can receive a Break Note that the data value written to the TXREGx for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling active or Idle, just as it does during normal transmis- location (13 bits for Break versus Start bit and 8 data sion. See Figure22-10 for the timing of the Break bits for typical data). character sequence. The second method uses the auto-wake-up feature 22.3.5.1 Break and Sync Transmit Sequence described in Section22.3.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSARTx will sample the next two transitions on header made up of a Break, followed by an Auto-Baud RXx/DTx, cause an RCxIF interrupt and receive the Sync byte. This sequence is typical of a LIN/J2602 bus next data byte followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. FIGURE 22-10: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB bit (Transmit Shift Reg. Empty Flag)  2010-2017 Microchip Technology Inc. DS30009977G-page 343

PIC18F66K80 FAMILY 22.4 EUSARTx Synchronous Once the TXREGx register transfers the data to the Master Mode TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTAx<7>). In this mode, the data is enable bit, TXxIE. TXxIF is set regardless of the state transmitted in a half-duplex manner (i.e., transmission of enable bit, TXxIE; it cannot be cleared in software. It and reception do not occur at the same time). When will reset only when new data is loaded into the transmitting data, the reception is inhibited and vice TXREGx register. versa. Synchronous mode is entered by setting bit, While flag bit, TXxIF, indicates the status of the TXREGx SYNC (TXSTAx<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTAx<1>), shows the (RCSTAx<7>), is set in order to configure the TXx and status of the TSR register. TRMT is a read-only bit which RXx pins to CKx (clock) and DTx (data) lines, is set when the TSR is empty. No interrupt logic is tied to respectively. this bit, so the user must poll this bit in order to determine The Master mode indicates that the processor trans- if the TSR register is empty. The TSR is not mapped in mits the master clock on the CKx line. Clock polarity is data memory so it is not available to the user. selected with the TXCKP bit (BAUDCONx<4>). Setting To set up a Synchronous Master Transmission: TXCKP sets the Idle state on CKx as high, while clear- ing the bit sets the Idle state as low. This option is 1. Initialize the SPBRGHx:SPBRGx registers for the provided to support Microwire devices with this module. appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. 22.4.1 EUSARTx SYNCHRONOUS 2. Enable the synchronous master serial port by MASTER TRANSMISSION setting bits, SYNC, SPEN and CSRC. The EUSARTx transmitter block diagram is shown in 3. If interrupts are desired, set enable bit, TXxIE. Figure22-3. The heart of the transmitter is the Transmit 4. If 9-bit transmission is desired, set bit, TX9. (Serial) Shift Register (TSR). The shift register obtains 5. Enable the transmission by setting bit, TXEN. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREGx. The TXREGx register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the last 7. Start transmission by loading data to the bit has been transmitted from the previous load. As TXREGx register. soon as the last bit is transmitted, the TSR is loaded with new data from the TXREGx (if available). 8. If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. FIGURE 22-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/CANRX/RX1/ DT1/CCP4Pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/CANTX/TX1/CK1/ CCP3/Pin (TXCKP = 0) RC6/CANTX/TX1/CK1/ CCP3/Pin (TXCKP = 1) Write to TxREG1 Reg Write Word 1 Write Word 2 Tx1IF bit (Interrupt Flag) TRMT bit TxEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRGx = 0; continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3). DS30009977G-page 344  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 22-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/CANRX/RX1/DT1/ bit 0 bit 1 bit 2 bit 6 bit 7 CCP4 Pin RC6/CANTX/TX1/CK1/ CCP3 Pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3). TABLE 22-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register Low Byte RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG2 EUSART2 Transmit Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register Low Byte PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.  2010-2017 Microchip Technology Inc. DS30009977G-page 345

PIC18F66K80 FAMILY 22.4.2 EUSARTx SYNCHRONOUS 3. Ensure bits, CREN and SREN, are clear. MASTER RECEPTION 4. If interrupts are desired, set enable bit, RCxIE. Once Synchronous mode is selected, reception is 5. If 9-bit reception is desired, set bit, RX9. enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit, SREN. SREN (RCSTAx<5>) or the Continuous Receive For continuous reception, set bit, CREN. Enable bit, CREN (RCSTAx<4>). Data is sampled on 7. Interrupt flag bit, RCxIF, will be set when recep- the RXx pin on the falling edge of the clock. tion is complete and an interrupt will be generated If enable bit, SREN, is set, only a single word is if the enable bit, RCxIE, was set. received. If enable bit, CREN, is set, the reception is 8. Read the RCSTAx register to get the 9th bit (if continuous until CREN is cleared. If both bits are set, enabled) and determine if any error occurred then CREN takes precedence. during reception. To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the RCREGx register. 1. Initialize the SPBRGHx:SPBRGx registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRG16 bit, CREN. bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE bits 2. Enable the synchronous master serial port by (INTCON<7:6>) are set. setting bits, SYNC, SPEN and CSRC. FIGURE 22-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/CANRX/ RX1/DT1/CCP4 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/CANTX/TX1/ CK1/CCP3 (TXCKP = 0) RC6/CANTX/TX1/ CK1/CCP3 (TXCKP = 0) Write to bit, SREN SREN bit CREN bit ‘0’ ‘0’ RC1IF bit (Interrupt) Read RCREG1 Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0. This example is equally applicable to EUSART2 (RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3). DS30009977G-page 346  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 22-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG1 EUSART1 Receive Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register Low Byte RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG2 EUSART2 Receive Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register Low Byte PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.  2010-2017 Microchip Technology Inc. DS30009977G-page 347

PIC18F66K80 FAMILY 22.5 EUSARTx Synchronous e) If enable bit, TXxIE, is set, the interrupt will wake Slave Mode the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt Synchronous Slave mode is entered by clearing bit, vector. CSRC (TXSTAx<7>). This mode differs from the To set up a Synchronous Slave Transmission: Synchronous Master mode in that the shift clock is sup- plied externally at the CKx pin (instead of being supplied 1. Enable the synchronous slave serial port by internally in Master mode). This allows the device to setting bits, SYNC and SPEN, and clearing bit, transfer or receive data while in any low-power mode. CSRC. 2. Clear bits, CREN and SREN. 22.5.1 EUSARTx SYNCHRONOUS 3. If interrupts are desired, set enable bit, TXxIE. SLAVE TRANSMISSION 4. If 9-bit transmission is desired, set bit, TX9. The operation of the Synchronous Master and Slave 5. Enable the transmission by setting enable bit, modes is identical, except in the case of Sleep mode. TXEN. If two words are written to the TXREGx and then the 6. If 9-bit transmission is selected, the ninth bit SLEEP instruction is executed, the following will occur: should be loaded in bit, TX9D. a) The first word will immediately transfer to the 7. Start transmission by loading data to the TSR register and transmit. TXREGx register. b) The second word will remain in the TXREGx 8. If using interrupts, ensure that the GIE and PEIE register. bits (INTCON<7:6>) are set. c) Flag bit, TXxIF, will not be set. d) When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register Low Byte RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D TXREG2 EUSART2 Transmit Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register Low Byte PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. DS30009977G-page 348  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 22.5.2 EUSARTx SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCxIE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCxIF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit, RCxIE, was set. RCREGx register. If the RCxIE enable bit is set, the 6. Read the RCSTAx register to get the 9th bit (if interrupt generated will wake the chip from the enabled) and determine if any error occurred low-power mode. If the global interrupt is enabled, the during reception. program will branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREGx register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits (INTCON<7:6>) are set. TABLE 22-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG1 EUSART1 Receive Register TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH1 EUSART1 Baud Rate Generator Register High Byte SPBRG1 EUSART1 Baud Rate Generator Register Low Byte RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D RCREG2 EUSART2 Receive Register TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN SPBRGH2 EUSART2 Baud Rate Generator Register High Byte SPBRG2 EUSART2 Baud Rate Generator Register Low Byte PMD0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD ODCON SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.  2010-2017 Microchip Technology Inc. DS30009977G-page 349

PIC18F66K80 FAMILY 23.0 12-BIT ANALOG-TO-DIGITAL 23.1 Differential A/D Converter CONVERTER (A/D) MODULE The converter in PIC18F66K80 family devices is implemented as a differential A/D where the differential The Analog-to-Digital (A/D) Converter module in the voltage between two channels is measured and PIC18F66K80 family of devices. It is a 13-bit differential converted to digital values (see Figure23-1). A/D with 12-bit single-ended compatibility. It has inputs eight inputs for the 28-pin devices, 11inputs for the The converter also can be configured to measure a 40/44-pin and 64-pin devices. This module allows con- voltage from a single input by clearing the CHSNx bits version of an analog input signal to a corresponding (ADCON1<2:0>). With this configuration, the negative 12-bit digital number. channel input is connected internally to AVSS (see Figure23-2). The module has these registers: • A/D Control Register 0 (ADCON0) FIGURE 23-1: DIFFERENTIAL CHANNEL • A/D Control Register 1 (ADCON1) MEASUREMENT • A/D Control Register 2 (ADCON2) • A/D Port Configuration Register 1 (ANCON0) Positive Input • A/D Port Configuration Register 2 (ANCON1) CHS<4:0> A/D • ADRESH (the upper, A/D Results register) Negative Input CHSN<2:0> • ADRESL (the lower, A/D Results register) The ADCON0 register, shown in Register23-1, con- trols the operation of the A/D module. The ADCON1 Differential conversion feeds the two input channels to register, shown in Register23-2, configures the voltage a unity gain differential amplifier. The positive channel reference and special trigger selection. The ADCON2 input is selected using the CHSx bits (ADCON0<6:2>) register, shown in Register23-3, configures the A/D and the negative channel input is selected using the clock source and programmed acquisition time and CHSNx bits (ADCON1<2:0>). justification. The output from the amplifier is fed to the A/D Con- verter, as shown in Figure23-1. The 12-bit result is available on the ADRESH and ADRESL registers. An additional bit indicates if the 12-bit result is a positive or negative value. FIGURE 23-2: SINGLE CHANNEL MEASUREMENT Positive Input CHS<4:0> A/D CHSN<2:0> = 000 In the Single Channel Measurement mode, the negative input is connected to AVSS by clearing the CHSNx bits (ADCON1<2:0>). DS30009977G-page 350  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 23.2 A/D Registers 23.2.1 A/D CONTROL REGISTERS REGISTER 23-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = Channel 00 (AN0) 10000 =(Reserved)(2) 00001 = Channel 01 (AN1) 10001 =(Reserved)(2) 00010 = Channel 02 (AN2) 10010 =(Reserved)(2) 00011 = Channel 03 (AN3) 10011 =(Reserved)(2) 00100 = Channel 04 (AN4) 10100 =(Reserved)(2) 00101 = Channel 05 (AN5)(1,2) 10101 =(Reserved)(2) 00110 = Channel 06 (AN6)(1,2) 10110 =(Reserved)(2) 00111 = Channel 07 (AN7)(1,2) 10111 =(Reserved)(2) 01000 = Channel 08 (AN8) 11000 =(Reserved)(2) 01001 = Channel 09 (AN9) 11001 =(Reserved)(2) 01010 = Channel 10 (AN10) 11010 =(Reserved)(2) 01011 = (Reserved)(2) 11011 =(Reserved)(2) 01100 = (Reserved)(2)) 11100 =(MUX disconnect)(3) 01101 = (Reserved)(2)) 11101 =Channel 29 (temperature diode) 01110 = (Reserved)(2)) 11110 =Channel 30 (VDDCORE) 01111 = (Reserved)(2) 11111 =Channel 31 (1.024V band gap)(4) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D cycle is in progress. Setting this bit starts an A/D conversion cycle. The bit is cleared automatically by hardware when the A/D conversion is completed. 0 = A/D conversion has completed or is not in progress bit 0 ADON: A/D On bit 1 = A/D Converter is operating 0 = A/D conversion module is shut off and consuming no operating current Note 1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return random values. 3: Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of the A/D input, for finer resolution CTMU time measurements. 4: Allow greater than 15 s acquisition time when measuring the Fixed Voltage Reference.  2010-2017 Microchip Technology Inc. DS30009977G-page 351

PIC18F66K80 FAMILY REGISTER 23-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x R/W-x R/W-x R/W-x TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TRIGSEL<1:0>: Special Trigger Select bits 11 = Selects the special trigger from the CCP2 10 = Selects the special trigger from the Timer1 01 = Selects the special trigger from the CTMU 00 = Selects the special trigger from the ECCP1 bit 5-4 VCFG<1:0>: A/D VREF+ Configuration bits(1) 11 = Internal VREF+ (4.1V) 10 = Internal VREF+ (2.0V) 01 = External VREF+ 00 = AVDD bit 3 VNCFG: A/D VREF- Configuration bit 1 = External VREF 0 = AVSS bit 2-0 CHSN<2:0>: Analog Negative Channel Select bits 111 = Reserved 110 = Channel 06 (AN5) 101 = Channel 05 (AN4) 100 = Channel 04 (AN3) 011 = Channel 03 (AN2) 010 = Channel 02 (AN1) 001 = Channel 01 (AN0) 000 = Channel 00 (AVSS) Note 1: When CHS<4:0> = 11111 a VCFG<1:0> value of '10' or '11' is not allowed. DS30009977G-page 352  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 23-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion.  2010-2017 Microchip Technology Inc. DS30009977G-page 353

PIC18F66K80 FAMILY 23.2.2 A/D RESULT REGISTERS be performed on the result. The results are represented as a two's compliment binary value. This The ADRESH:ADRESL register pair is where the 12-bit means that when sign bits and magnitude bits are A/D result and extended sign bits (ADSGNx) are considered together in right justification, the ADRESH loaded at the completion of a conversion. This register and ADRESL registers can be read as a single signed pair is 16 bits wide. The A/D module gives the flexibility integer value. of left or right justifying the 12-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) con- When the A/D Converter is disabled, these 8-bit trols this justification. registers can be used as two general purpose registers. Figure23-3 shows the operation of the A/D result justification and the location of the sign bit (ADSGNx). The extended sign bits allow for easier 16-bit math to FIGURE 23-3: A/D RESULT JUSTIFICATION 12-Bit Result Left Justified Right Justified ADFM = 0 ADFM = 1 ADRESH ADRESL ADRESH ADRESL Result bits ADSGN bit Two’s Complement Example Results Number Line Left Justified Right Justified Hex Decimal Hex Decimal 0xFFF0 4095 0x0FFF 4095 0xFFE0 4094 0x0FFE 4094 … … … … 0x0020 2 0x0002 2 0x0010 1 0x0001 1 0x0000 0 0x0000 0 0xFFFF -1 0xFFFF -1 0xFFEF -2 0xFFFE -2 … … … … 0x001F -4095 0xF001 -4095 0x000F -4096 0xF000 -4096 DS30009977G-page 354  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 23-4: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES11 ADRES10 ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<11:4>: A/D Result High Byte bits REGISTER 23-5: ADRESL: A/D RESULT LOW BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0) R/W-x R/W-x R/W-x R/W-x U-x U-x U-x U-x ADRES3 ADRES2 ADRES1 ADRES0 ADSGN3 ADSGN2 ADSGN1 ADSGN0 bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 ADRES<3:0>: A/D Result Low Byte bits bit 3-0 ADSGN<3:0>: A/D Result Sign bits 1 = A/D result is negative 0 = A/D result is positive REGISTER 23-6: ADRESH: A/D RESULT HIGH BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1) U-x U-x U-x U-x R/W-x R/W-x R/W-x R/W-x ADSGN7 ADSGN6 ADSGN5 ADSGN4 ADRES11 ADRES10 ADRES9 ADRES8 bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 ADSGN<7:4>: A/D Result Sign bits 1 = A/D result is negative 0 = A/D result is positive bit 3-0 ADRES<11:8>: A/D Result High Byte bits  2010-2017 Microchip Technology Inc. DS30009977G-page 355

PIC18F66K80 FAMILY REGISTER 23-7: ADRESL: A/D RESULT LOW BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: A/D Result Low Byte bits The ANCONx registers are used to configure the module, with all digital peripherals disabled and digital operation of the I/O pin associated with each analog inputs read as ‘0’. channel. Clearing an ANSELx bit configures the As a rule, I/O pins that are multiplexed with analog corresponding pin (ANx) to operate as a digital only I/O. inputs default to analog operation on any device Reset. Setting a bit configures the pin to operate as an analog input for either the A/D Converter or the comparator REGISTER 23-8: ANCON0: A/D PORT CONFIGURATION REGISTER 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSEL7(1) ANSEL6(1) ANSEL5(1) ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANSEL<7:0>: Analog Port Configuration bits (AN7 and AN0)(1) 1 = Pin configured as an analog channel: digital input disabled and any inputs read as ‘0’ 0 = Pin configured as a digital port Note 1: AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect. DS30009977G-page 356  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 23-9: ANCON1: A/D PORT CONFIGURATION REGISTER 1 U-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — ANSEL14(1) ANSEL13(1) ANSEL12(1) ANSEL11(1) ANSEL10 ANSEL9 ANSEL8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ANSEL14: RD3/C2INB Pin Analog Enable bit(1) 1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’ 0 = Pin is configured as a digital port bit 5 ANSEL13: RD2/C2INA Pin Analog Enable bit(1) 1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’ 0 = Pin is configured as a digital port bit 4 ANSEL12: RD1/C1INB Pin Analog Enable bit(1) 1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’ 0 = Pin is configured as a digital port bit 3 ANSEL11: RD0/C1INA Pin Analog Enable bit(1) 1 = Pin is configured as an analog channel: digital input disabled and any inputs read as ‘0’ 0 = Pin is configured as a digital port bit 2-0 ANSEL11<10:8>: Analog Port Configuration bits (AN10 through AN8) 1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’ 0 = Pin configured as a digital port Note 1: AN14 through AN11 and AN7 to AN5 are implemented only on 40/44-pin and 64-pin devices. For 28-pin devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect. The analog reference voltage is software selectable to Each port pin associated with the A/D Converter can be either the device’s positive and negative supply voltage configured as an analog input or a digital I/O. The (AVDD and AVSS) or the voltage level on the ADRESH and ADRESL registers contain the result of RA3/VREF+/AN3 and RA2/VREF-/AN2 pins. VREF+ has the A/D conversion. When the A/D conversion is com- two additional internal voltage reference selections: plete, the result is loaded into the ADRESH:ADRESL 2.0V and 4.1V. register pair, the GO/DONE bit (ADCON0<1>) is cleared and the A/D Interrupt Flag bit, ADIF (PIR1<6>), is set. The A/D Converter can uniquely operate while the device is in Sleep mode. To operate in Sleep, the A/D A device Reset forces all registers to their Reset state. conversion clock must be derived from the A/D’s This forces the A/D module to be turned off and any internal RC oscillator. conversion in progress is aborted. The value in the ADRESH:ADRESL register pair is not modified for a The output of the sample and hold is the input into the Power-on Reset. These registers will contain unknown converter, which generates the result via successive data after a Power-on Reset. approximation. The block diagram of the A/D module is shown in Figure23-4.  2010-2017 Microchip Technology Inc. DS30009977G-page 357

PIC18F66K80 FAMILY FIGURE 23-4: A/D BLOCK DIAGRAM CHS<4:0> 11111 1.024V Band Gap 11110 VDDCORE 11101 Reserved Temperature Diode 11100 (MUX Disconnected)(3) 11011 (Unimplemented) 11010 (Unimplemented) 11001 (Unimplemented) 11000 (Unimplemented) 01110 AN14(1) 12-Bit 01101 A/D AN13(1) Converter 00100 AN4 00011 AN3 00010 AN2 00001 AN1 00000 AN0 Positive Input Voltage CHSN<2:0> 111 Negative Input Voltage AN6 110 AN5 Reference VCFG<1:0> Voltage Internal VREF+ 11 (4.1V) 001 AN0 10 Internal VREF+ VREF+ (2.0V) 000 AVSS(4) 01 AN3 VREF- VDD(4) 00 VNCFG AN2 VSS(2,4) Note 1: Channels, AN14 through AN11, and AN7 through AN5, are implemented only on 40/44-pin and 64-pin devices. For 28-pin devices, the corresponding ANSELx bits are still implemented for those channels, but have no effect. 2: I/O pins have diode protection to VDD and VSS. 3: Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of A/D inputs for finer resolution CTMU time measurements. 4: I/O pins have diode protection to VDD and VSS. DS30009977G-page 358  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY After the A/D module has been configured as desired, 2. Configure the A/D interrupt (if desired): the selected channel must be acquired before the • Clear the ADIF bit (PIR1<6>) conversion can start. The analog input channels must • Set the ADIE bit (PIE1<6>) have their corresponding TRIS bits selected as an • Set the GIE bit (INTCON<7>) input. To determine acquisition time, see Section23.3 3. Wait the required acquisition time (if required). “A/D Acquisition Requirements”. After this acquisi- tion time has elapsed, the A/D conversion can be 4. Start the conversion: started. An acquisition time can be programmed to • Set the GO/DONE bit (ADCON0<1>) occur between setting the GO/DONE bit and the actual 5. Wait for A/D conversion to complete, by either: start of the conversion. • Polling for the GO/DONE bit to be cleared To do an A/D conversion, follow these steps: OR 1. Configure the A/D module: • Waiting for the A/D interrupt • Configure the required A/D pins as analog pins 6. Read A/D Result registers (ADRESH:ADRESL) (ANCON0 and ANCON1) and, if required, clear bit, ADIF. • Set the voltage reference (ADCON1) 7. For the next conversion, begin with Step 1 or 2, • Select the A/D positive and negative input as required. channels (ADCON0 and ADCON1) The A/D conversion time per bit is defined as TAD. • Select the A/D acquisition time (ADCON2) Before the next acquisition starts, a minimum wait • Select the A/D conversion clock (ADCON2) of 2 TAD is required. • Turn on the A/D module (ADCON0) FIGURE 23-5: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to VDD various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance 1 2 3 4 Sampling Switch (k)  2010-2017 Microchip Technology Inc. DS30009977G-page 359

PIC18F66K80 FAMILY 23.3 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation23-1 can be used. This equation assumes For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1,024 steps for the A/D). The the Charge Holding (CHOLD) capacitor must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure23-5. The Equation23-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). CHOLD = 25 pF The source impedance affects the offset voltage at the Rs = 2.5 k analog input (due to pin leakage current). The maxi- Conversion Error  1/2 LSb mum recommended impedance for analog sources is 2.5k. After the analog input channel is selected or VDD = 3VRss = 2 k changed, the channel must be sampled for at least the Temperature = 85C (system max.) minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 23-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 23-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 23-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 s TCOFF = (Temp – 25C)(0.02 s/C) (85C – 25C)(0.02 s/C) 1.2 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s TACQ = 0.2 s + 1.05 s + 1.2 s 2.45 s DS30009977G-page 360  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 23.4 Selecting and Configuring TABLE 23-1: TAD vs. DEVICE OPERATING Automatic Acquisition Time FREQUENCIES The ADCON2 register allows the user to select an AD Clock Source (TAD) Maximum acquisition time that occurs each time the GO/DONE Device bit is set. Operation ADCS<2:0> Frequency When the GO/DONE bit is set, sampling is stopped and 2 TOSC 000 2.50 MHz a conversion begins. The user is responsible for ensur- 4 TOSC 100 5.00 MHz ing the required acquisition time has passed between 8 TOSC 001 10.00 MHz selecting the desired input channel and setting the GO/DONE bit. 16 TOSC 101 20.00 MHz This occurs when the ACQT<2:0> bits 32 TOSC 010 40.00 MHz (ADCON2<5:3>) remain in their Reset state (‘000’), 64 TOSC 110 64.00 MHz which is compatible with devices that do not offer RC(2) x11 1.00 MHz(1) programmable acquisition times. Note 1: The RC source has a typical TAD time of If desired, the ACQTx bits can be set to select a pro- 4s. grammable acquisition time for the A/D module. When 2: For device frequencies above 1MHz, the the GO/DONE bit is set, the A/D module continues to device must be in Sleep mode for the sample the input for the selected acquisition time, then entire conversion or the A/D accuracy may automatically begins a conversion. Since the acquisi- be out of specification. tion time is programmed, there may be no need to wait for an acquisition time between selecting a channel and 23.6 Configuring Analog Port Pins setting the GO/DONE bit. The ANCON0, ANCON1, TRISA, TRISB, TRISC and In either case, when the conversion is completed, the TRISC registers control the operation of the A/D port GO/DONE bit is cleared, the ADIF flag is set and the pins. The port pins needed as analog inputs must have A/D begins sampling the currently selected channel their corresponding TRISx bits set (input). If the TRISx again. If an acquisition time is programmed, there is bit is cleared (output), the digital output level (VOH or nothing to indicate if the acquisition time has ended or VOL) will be converted. if the conversion has begun. The A/D operation is independent of the state of the 23.5 Selecting the A/D Conversion CHS<3:0> bits and the TRISx bits. Clock Note: When reading the PORT register, all pins The A/D conversion time per bit is defined as TAD. The configured as analog input channels will A/D conversion requires 14 TAD per 12-bit conversion. read as cleared (a low level). Pins The source of the A/D conversion clock is software configured as digital inputs will convert an selectable. analog input. Analog levels on a digitally configured input will be accurately The possible options for TAD are: converted. • 2 TOSC Analog levels on any pin defined as a • 4 TOSC digital input may cause the digital input • 8 TOSC buffer to consume current out of the • 16 TOSC device’s specification limits. • 32 TOSC • 64 TOSC • Using the internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD. (For more information, see Parameter130 in Table31-26.) Table23-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.  2010-2017 Microchip Technology Inc. DS30009977G-page 361

PIC18F66K80 FAMILY 23.7 A/D Conversions ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last Figure23-6 shows the operation of the A/D Converter value written to the ADRESH:ADRESL registers). after the GO/DONE bit has been set and the After the A/D conversion is completed or aborted, a ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep 2TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected mode before the conversion begins. channel is automatically started. Figure23-7 shows the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT<2:0> Note: The GO/DONE bit should NOT be set in bits set to ‘010’ and a 4TAD acquisition time selected. the same instruction that turns on the A/D. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the FIGURE 23-6: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11TAD12TAD13 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 23-7: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS30009977G-page 362  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 23.8 Use of the Special Event Triggers 23.9 Operation in Power-Managed Modes A/D conversion can be started by the Special Event Trigger of any of these modules: The selection of the automatic acquisition time and A/D • CCP2 – Requires CCP2M<3:0> bits conversion clock is determined, in part, by the clock (CCP2CON<3:0>) set at ‘1011’(†) source and frequency while in a power-managed mode. • ECCP1 • CTMU – Requires the setting of the CTTRIG bit If the A/D is expected to operate while the device is in (CTMUCONH<0>) a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in • Timer1 accordance with the power-managed mode clock that To start an A/D conversion: will be used. • The A/D module must be enabled (ADON = 1) After the power-managed mode is entered (either of the • The appropriate analog input channel selected power-managed Run modes), an A/D acquisition or • The minimum acquisition period set one of these conversion may be started. Once an acquisition or con- ways: version is started, the device should continue to be - Timing provided by the user clocked by the same power-managed mode clock source until the conversion has been completed. If desired, the - Selection made of an appropriate TACQ time device may be placed into the corresponding With these conditions met, the trigger sets the power-managed Idle mode during the conversion. GO/DONE bit and the A/D acquisition starts. If the power-managed mode clock frequency is less If the A/D module is not enabled (ADON = 0), the than 1MHz, the A/D RC clock source should be module ignores the Special Event Trigger. selected. Note: With an ECCP1 or CCP2 trigger, Timer1 Operation in Sleep mode requires that the A/D RC or Timer3 is cleared. The timers reset to clock be selected. If bits, ACQT<2:0>, are set to ‘000’ automatically repeat the A/D acquisition and a conversion is started, the conversion will be period with minimal software overhead delayed one instruction cycle to allow execution of the (moving ADRESH:ADRESL to the desired SLEEP instruction and entry into Sleep mode. The location). If the A/D module is not enabled, IDLEN and SCS<1:0> bits in the OSCCON register the Special Event Trigger is ignored by the must have already been cleared prior to starting the module, but the timer’s counter resets. conversion.  2010-2017 Microchip Technology Inc. DS30009977G-page 363

PIC18F66K80 FAMILY TABLE 23-2: REGISTERS ASSOCIATED WITH THE A/D MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON ADCON1 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 ANCON1 — ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 PORTA RA7(1) RA6(1) RA5 — RA3 RA2 RA1 RA0 TRISA TRISA7(1) TRISA6(1) TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 PORTE RE7 RE6 RE5 RE4 RE3 — RE1 RE0 TRISE TRISE7 TRISE6 TRISE5 TRISE4 — TRISE2 TRISE1 TRISE0 PMD1 PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These bits are available only in certain oscillator modes when the FOSC2 Configuration bit = 0. If that Configuration bit is cleared, this signal is not implemented. DS30009977G-page 364  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 24.0 COMPARATOR MODULE 24.1 Registers The analog comparator module contains two compara- The CMxCON registers (CM1CON and CM2CON) tors that can be independently configured in a variety of select the input and output configuration for each com- ways. The inputs can be selected from the analog parator, as well as the settings for interrupt generation inputs and two internal voltage references. The digital (see Register24-1). outputs are available at the pin level and can also be The CMSTAT register (Register24-2) provides the out- read through the control register. Multiple output and put results of the comparators. The bits in this register interrupt event generation are also available. A generic are read-only. single comparator from the module is shown in Figure24-1. Key features of the module includes: • Independent comparator control • Programmable input configuration • Output to both pin and register levels • Programmable output polarity • Independent interrupt generation for each comparator with configurable interrupt-on-change FIGURE 24-1: COMPARATOR SIMPLIFIED BLOCK DIAGRAM CCH<1:0> CMPxOUT (CMSTAT<7:6>) CxINB 0 CxINC 1 Interrupt C2INB/C2IND(1) 2 Logic CMPxIF VBG 3 EVPOL<1:0> CREF COE VIN- CxOUT Polarity CxINA 0 VIN+ Cx Logic CVREF 1 CON CPOL Note 1: Comparator 1 uses C2INB as an input to the inverted terminal. Comparator 2 uses C1INB as an input to the inverted terminal.  2010-2017 Microchip Technology Inc. DS30009977G-page 365

PIC18F66K80 FAMILY REGISTER 24-1: CMxCON: COMPARATOR CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 5 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 4-3 EVPOL<1:0>: Interrupt Polarity Select bits 11 = Interrupt generation on any change of the output(1) 10 = Interrupt generation only on high-to-low transition of the output 01 = Interrupt generation only on low-to-high transition of the output 00 = Interrupt generation is disabled bit 2 CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG 10 = Inverting input of comparator connects to C2INB pin(2) 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to C1INB pin(2) Note 1: The CMPxIF is automatically set any time this mode is selected and must be cleared by the application after the initial configuration. 2: Comparator 1 uses C2INB as an input to the inverting terminal. Comparator 2 uses C1INB as an input to the inverted terminal. DS30009977G-page 366  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 24-2: CMSTAT: COMPARATOR STATUS REGISTER R-x R-x U-0 U-0 U-0 U-0 U-0 U-0 CMP2OUT CMP1OUT — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CMP2OUT:CMP1OUT: Comparator x Status bits If CPOL (CMxCON<5>)= 0 (non-inverted polarity): 1 = Comparator x’s VIN+ > VIN- 0 = Comparator x’s VIN+ < VIN- If CPOL = 1 (inverted polarity): 1 = Comparator x’s VIN+ < VIN- 0 = Comparator x’s VIN+ > VIN- bit 4-0 Unimplemented: Read as ‘0’  2010-2017 Microchip Technology Inc. DS30009977G-page 367

PIC18F66K80 FAMILY 24.2 Comparator Operation 24.3 Comparator Response Time A single comparator is shown in Figure24-2, along with Response time is the minimum time, after selecting a the relationship between the analog input levels and new reference voltage or input source, before the com- the digital output. When the analog input at VIN+ is less parator output has a valid level. The response time of than the analog input, VIN-, the output of the compara- the comparator differs from the settling time of the volt- tor is a digital low level. When the analog input at VIN+ age reference. Therefore, both of these times must be is greater than the analog input, VIN-, the output of the considered when determining the total response to a comparator is a digital high level. The shaded areas of comparator input change. Otherwise, the maximum the output of the comparator in Figure24-2 represent delay of the comparators should be used (see the uncertainty due to input offsets and response time. Section31.0 “Electrical Characteristics”). 24.4 Analog Input Connection FIGURE 24-2: SINGLE COMPARATOR Considerations VIN- – A simplified circuit for an analog input is shown in Output Figure24-3. Since the analog pins are connected to a VIN+ + digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may VIN- occur. VIN+ A maximum source impedance of 10k is recommended for the analog sources. Any external component connected to an analog input pin, such as Output a capacitor or a Zener diode, should have very little leakage current. FIGURE 24-3: COMPARATOR ANALOG INPUT MODEL VDD RS VT = 0.6V RIC Comparator <10 k AIN Input VA C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage DS30009977G-page 368  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 24.5 Comparator Control and The external reference is used when CREF=0 Configuration (CMxCON<2>) and VIN+ is connected to the CxINA pin. When external voltage references are used, the Each comparator has up to eight possible combina- comparator module can be configured to have the ref- tions of inputs: up to four external analog inputs and erence sources externally. The reference signal must one of two internal voltage references. be between VSS and VDD and can be applied to either All of the comparators allow a selection of the signal pin of the comparator. from pin, CxINA, or the voltage from the comparator The comparator module also allows the selection of an reference (CVREF) on the non-inverting channel. This is internally generated voltage reference (CVREF) from the compared to either C1INB, CxINC, C2INB or the micro- comparator voltage reference module. This module is controller’s fixed internal reference voltage (VBG, described in more detail in Section25.0 “Comparator 1.024V nominal) on the inverting channel. The compar- Voltage Reference Module”. The reference from the ator inputs and outputs are tied to fixed I/O pins, comparator voltage reference module is only available defined in Table24-1. The available comparator config- when CREF=1. In this mode, the internal voltage urations and their corresponding bit settings are shown reference is applied to the comparator’s VIN+ pin. in Figure24-4. Note: The comparator input pin selected by CCH<1:0> must be configured as an input TABLE 24-1: COMPARATOR INPUTS AND by setting both the corresponding TRIS bit OUTPUTS and the corresponding ANSELx bit in the Comparator Input or Output I/O Pin(†) ANCONx register. C1INA (VIN+) RB0/RD0 24.5.2 COMPARATOR ENABLE AND C1INB (VIN-) RB1/RD1 OUTPUT SELECTION 1 C1INC (VIN-) RA1 The comparator outputs are read through the CMSTAT C2INB(VIN-) RA5/RD3 register. The CMSTAT<6> bit reads the Comparator1 C1OUT RB2/RE1 output, CMSTAT<7> reads the Comparator2 output. These bits are read-only. C2INA(VIN+) RB4/RD2 The comparator outputs may also be directly output to C2INB(VIN-) RA5/RD3 2 the RE2 and RE1 pins by setting the COE bit C2INC(VIN-) RA2 (CMxCON<6>). When enabled, multiplexers in the C2OUT RB3/RE2 output path of the pins switch to the output of the com- † The I/O pin is dependent on package type. parator. While in this mode, the TRISE<2:1> bits still function as the digital output enable bits for the RE2, and RE1 pins. 24.5.1 COMPARATOR ENABLE AND By default, the comparator’s output is at logic high INPUT SELECTION whenever the voltage on VIN+ is greater than on VIN-. Setting the CON bit of the CMxCON register The polarity of the comparator outputs can be inverted (CMxCON<7>) enables the comparator for operation. using the CPOL bit (CMxCON<5>). Clearing the CON bit disables the comparator, resulting The uncertainty of each of the comparators is related to in minimum current consumption. the input offset voltage and the response time given in The CCH<1:0> bits in the CMxCON register the specifications, as discussed in Section24.2 (CMxCON<1:0>) direct either one of three analog input “Comparator Operation”. pins, or the Internal Reference Voltage (VBG), to the comparator, VIN-. Depending on the comparator oper- ating mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly.  2010-2017 Microchip Technology Inc. DS30009977G-page 369

PIC18F66K80 FAMILY FIGURE 24-4: COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx COE VIN- VIN+ Cx Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CON = 1, CREF = 0, CCH<1:0> = 01 COE COE CxINB VIN- CxINC VIN- CxINA VIN+ Cx CxOUT CxINA VIN+ Cx CxOUT Pin Pin Comparator C2INB/C1INB > CxINA Compare Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 10 CON = 1, CREF = 0, CCH<1:0> = 11 COE COE CC12IINNBB / VIN- VBG VIN- CxINA VIN+ Cx CxOUT CxINA VIN+ Cx CxOUT Pin Pin Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 CON = 1, CREF = 1, CCH<1:0> = 01 COE COE CxINB VIN- CxINC VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT Pin Pin Comparator C2INB/C1INB > CVREF Compare Comparator VBG > CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 10 CON = 1, CREF = 1, CCH<1:0> = 11 COE COE CC12IINNBB / VIN- VBG VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT Pin Pin Note 1: VBG is the Internal Reference Voltage (see Table31-2). DS30009977G-page 370  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 24.6 Comparator Interrupts When EVPOL<1:0> = 11, the comparator interrupt flag is set whenever there is a change in the output value of The comparator interrupt flag is set whenever any of either comparator. Software will need to maintain the following occurs: information about the status of the output bits, as read • Low-to-high transition of the comparator output from CMSTAT<7:6>, to determine the actual change • High-to-low transition of the comparator output that occurred. • Any change in the comparator output The CMPxIF<2:0> (PIR4<5:4) bits are the Comparator Interrupt Flags. The CMPxIF bits must be reset by The comparator interrupt selection is done by the clearing them. Since it is also possible to write a ‘1’ to EVPOL<1:0> bits in the CMxCON register this register, a simulated interrupt may be initiated. (CMxCON<4:3>). Table24-2 shows the interrupt generation with respect In order to provide maximum flexibility, the output of the to comparator input voltages and EVPOL bit settings. comparator may be inverted using the CPOL bit in the Both the CMPxIE bits (PIE4<5:4>) and the PEIE bit CMxCON register (CMxCON<5>). This is functionally (INTCON<6>) must be set to enable the interrupt. In identical to reversing the inverting and non-inverting addition, the GIE bit (INTCON<7>) must also be set. If inputs of the comparator for a particular mode. any of these bits are clear, the interrupt is not enabled, An interrupt is generated on the low-to-high or though the CMPxIF bits will still be set if an interrupt high-to-low transition of the comparator output. This condition occurs. mode of interrupt generation is dependent on A simplified diagram of the interrupt section is shown in EVPOL<1:0> in the CMxCON register. When Figure24-3. EVPOL<1:0> = 01 or 10, the interrupt is generated on a low-to-high or high-to-low transition of the comparator Note: CMPxIF will not be set when output. Once the interrupt is generated, it is required to EVPOL<1:0>=00. clear the interrupt flag by software. TABLE 24-2: COMPARATOR INTERRUPT GENERATION Comparator Interrupt CPOL EVPOL<1:0> CxOUT Transition Input Change Generated VIN+ > VIN- Low-to-High No 00 VIN+ < VIN- High-to-Low No VIN+ > VIN- Low-to-High Yes 01 VIN+ < VIN- High-to-Low No 0 VIN+ > VIN- Low-to-High No 10 VIN+ < VIN- High-to-Low Yes VIN+ > VIN- Low-to-High Yes 11 VIN+ < VIN- High-to-Low Yes VIN+ > VIN- High-to-Low No 00 VIN+ < VIN- Low-to-High No VIN+ > VIN- High-to-Low No 01 VIN+ < VIN- Low-to-High Yes 1 VIN+ > VIN- High-to-Low Yes 10 VIN+ < VIN- Low-to-High No VIN+ > VIN- High-to-Low Yes 11 VIN+ < VIN- Low-to-High Yes  2010-2017 Microchip Technology Inc. DS30009977G-page 371

PIC18F66K80 FAMILY 24.7 Comparator Operation To minimize power consumption while in Sleep mode, During Sleep turn off the comparators (CON=0) before entering Sleep. If the device wakes up from Sleep, the contents When a comparator is active and the device is placed of the CMxCON register are not affected. in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will 24.8 Effects of a Reset wake-up the device from Sleep mode, when enabled. Each operational comparator will consume additional A device Reset forces the CMxCON registers to their current. Reset state. This forces both comparators and the voltage reference to the OFF state. TABLE 24-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 CMSTAT CMP2OUT CMP1OUT — — — — — — PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 ANCON1 — ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 PMD2 — — — — MODMD ECANMD CMP2MD CMP1MD Legend: — = unimplemented, read as ‘0’. DS30009977G-page 372  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 25.0 COMPARATOR VOLTAGE EQUATION 25-1: REFERENCE MODULE If CVRSS = 1: The comparator voltage reference is a 32-tap resistor ( CVR<4:0>) CVREF = VREF- + • (VREF+ – VREF-) ladder network that provides a selectable reference 32 voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be If CVRSS = 0: used independently of them. ( CVR<4:0>) A block diagram of the module is shown in Figure25-1. CVREF = AVSS + • (AVDD – AVSS) 32 The resistor ladder is segmented to provide a range of CVREF values and has a power-down function to The comparator reference supply voltage can come conserve power when the reference is not being used. The module’s supply reference can be provided from from either VDD and VSS, or the external VREF+ and either device VDD/VSS or an external voltage reference. VREF- that are multiplexed with RA3 and RA2. The voltage source is selected by the CVRSS bit (CVRCON<5>). 25.1 Configuring the Comparator Voltage Reference The settling time of the comparator voltage reference must be considered when changing the CVREF The comparator voltage reference module is controlled output (see Table31-2 in Section31.0 “Electrical through the CVRCON register (Register25-1). The Characteristics”). comparator voltage reference provides a range of output voltage with 32 levels. The CVR<4:0> selection bits (CVRCON<4:0>) offer a range of output voltages. Equation25-1 shows the how the comparator voltage reference is computed. REGISTER 25-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+–VREF- 0 = Comparator reference source, CVRSRC = AVDD–AVSS bit 4-0 CVR<4:0>: Comparator VREF Value Selection 0  CVR<4:0>  31 bits When CVRSS = 1: CVREF = (VREF-) + (CVR<4:0>/32)  (VREF+ – VREF-) When CVRSS = 0: CVREF = (AVSS) + (CVR<4:0>/32)  (AVDD – AVSS)  2010-2017 Microchip Technology Inc. DS30009977G-page 373

PIC18F66K80 FAMILY FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ AVDD CVRSS = 0 CVR<4:0> R CVREN R R R X U M 32 Steps 1 CVREF o- 2-t 3 R R R CVRSS = 1 VREF- CVRSS = 0 25.2 Voltage Reference Accuracy/Error 25.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RF5 pin by clearing (Figure25-1) keep CVREF from approaching the refer- bit, CVROE (CVRCON<6>). ence source rails. The voltage reference is derived from the reference source; therefore, the CVREF output 25.5 Connection Considerations changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be The voltage reference module operates independently found in Section31.0 “Electrical Characteristics”. of the comparator module. The output of the reference generator may be connected to the RA0 pin if the 25.3 Operation During Sleep CVROE bit is set. Enabling the voltage reference out- put onto RA0 when it is configured as a digital input will When the device wakes up from Sleep through an increase current consumption. Connecting RA0 as a interrupt or a Watchdog Timer time-out, the contents of digital output with CVRSS enabled will also increase the CVRCON register are not affected. To minimize current consumption. current consumption in Sleep mode, the voltage The RA0 pin can be used as a simple D/A output with reference should be disabled. limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure25-2 shows an example buffering technique. DS30009977G-page 374  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 25-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F66K80 CVREF R(1) Module + Voltage RA0 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the Voltage Reference Configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 25-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 TRISA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.  2010-2017 Microchip Technology Inc. DS30009977G-page 375

PIC18F66K80 FAMILY 26.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register26-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned The PIC18F66K80 family of devices has a off” by the user under software control, which High/Low-Voltage Detect module (HLVD). This is a pro- minimizes the current consumption for the device. grammable circuit that sets both a device voltage trip The module’s block diagram is shown in Figure26-1. point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the inter- rupt vector address and the software responds to the interrupt. REGISTER 26-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIRMAG BGVST IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Reference Voltages Stable Status Flag bit 1 = Internal band gap voltage references are stable 0 = Internal band gap voltage references are not stable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: For the electrical specifications, see Parameter D420 in Section31.0 “Electrical Characteristics”. DS30009977G-page 376  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY The module is enabled by setting the HLVDEN bit trip point voltage. The “trip point” voltage is the voltage (HLVDCON<4>). Each time the HLVD module is level at which the device detects a high or low-voltage enabled, the circuitry requires some time to stabilize. event, depending on the configuration of the module. The IRVST bit (HLVDCON<5>) is a read-only bit used When the supply voltage is equal to the trip point, the to indicate when the circuit is stable. The module can voltage tapped off of the resistor array is equal to the only generate an interrupt after the circuit is stable and internal reference voltage generated by the voltage IRVST is set. reference module. The comparator then generates an The VDIRMAG bit (HLVDCON<7>) determines the interrupt signal by setting the HLVDIF bit. overall operation of the module. When VDIRMAG is The trip point voltage is software programmable to any one cleared, the module monitors for drops in VDD below a of 16 values. The trip point is selected by programming the predetermined set point. When the bit is set, the HLVDL<3:0> bits (HLVDCON<3:0>). module monitors for rises in VDD above the set point. The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an 26.1 Operation external source. This mode is enabled when bits, When the HLVD module is enabled, a comparator uses HLVDL<3:0>, are set to ‘1111’. In this state, the an internally generated reference voltage as the set comparator input is multiplexed from the external input point. The set point is compared with the trip point, pin, HLVDIN. This gives users the flexibility of configur- where each node in the resistor divider represents a ing the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. FIGURE 26-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage Reference BOREN<1:0> 1.024V Typical  2010-2017 Microchip Technology Inc. DS30009977G-page 377

PIC18F66K80 FAMILY 26.2 HLVD Setup 26.3 Current Consumption To set up the HLVD module: When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static 1. Select the desired HLVD trip point by writing the current. The total current consumption, when enabled, value to the HLVDL<3:0> bits. is specified in electrical specification Parameter D022B 2. Set the VDIRMAG bit to detect high voltage (Table31-11). (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Depending on the application, the HLVD module does 3. Enable the HLVD module by setting the not need to operate constantly. To reduce current HLVDEN bit. requirements, the HLVD circuitry may only need to be 4. Clear the HLVD interrupt flag (PIR2<2>), which enabled for short periods where the voltage is checked. may have been set from a previous interrupt. After such a check, the module could be disabled. 5. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE bits 26.4 HLVD Start-up Time (PIE2<2> and INTCON<7>, respectively). An interrupt will not be generated until the The internal reference voltage of the HLVD module, IRVST bit is set. specified in electrical specification Parameter 37 (Section31.0 “Electrical Characteristics”), may be Note: Before changing any module settings used by other internal circuitry, such as the (VDIRMAG, HLVDL<3:0>), first disable the programmable Brown-out Reset. If the HLVD or other module (HLVDEN = 0), make the changes circuits using the voltage reference are disabled to and re-enable the module. This prevents lower the device’s current consumption, the reference the generation of false HLVD events. voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification Parameter 37 (Table31-11). The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (see Figure26-2 or Figure26-3). DS30009977G-page 378  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 26-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal reference is stable CASE 2: VDD VHLVD HLVDIF Enable HLVD IRVST TIRVST Internal reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists  2010-2017 Microchip Technology Inc. DS30009977G-page 379

PIC18F66K80 FAMILY FIGURE 26-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 26.5 Applications FIGURE 26-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach VA would indicate a high-voltage detect from, for example, VB 3.3V to 5V (the voltage on USB) and vice versa for a e g detach. This feature could save a design a few extra a t components and an attach signal (input pin). ol V For general battery applications, Figure26-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, Time TA TB which would allow the application to perform “house- keeping tasks” and a controlled shutdown before the Legend: VA = HLVD trip point device voltage exits the valid operating range at TB. VB = Minimum valid device This would give the application a time window, repre- operating voltage sented by the difference between TA and TB, to safely exit. DS30009977G-page 380  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 26.6 Operation During Sleep 26.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 26-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR2 OSCFIF — — — BCLIF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — — — BCLIE HLVDIE TMR3IE TMR3GIE IPR2 OSCFIP — — — BCLIP HLVDIP TMR3IP TMR3GIP TRISA TRISA7(1) TRISA6(1) TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the HLVD module. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 381

PIC18F66K80 FAMILY 27.0 ECAN MODULE 27.1 Module Overview PIC18F66K80 family devices contain an Enhanced The CAN bus module consists of a protocol engine and Controller Area Network (ECAN) module. The ECAN message buffering and control. The CAN protocol module is fully backward compatible with the CAN engine automatically handles all functions for receiving module available in PIC18CXX8 and PIC18FXX8 and transmitting messages on the CAN bus. Messages devices and the ECAN module in PIC18Fxx80 devices. are transmitted by first loading the appropriate data The Controller Area Network (CAN) module is a serial registers. Status and errors can be checked by reading interface which is useful for communicating with other the appropriate registers. Any message detected on peripherals or microcontroller devices. This interface, the CAN bus is checked for errors and then matched or protocol, was designed to allow communications against filters to see if it should be received and stored within noisy environments. in one of the two receive registers. The ECAN module is a communication controller, imple- The CAN module supports the following frame types: menting the CAN 2.0A or B protocol as defined in the • Standard Data Frame BOSCH specification. The module will support CAN1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active • Extended Data Frame versions of the protocol. The module implementation is • Remote Frame a full CAN system; however, the CAN specification is not • Error Frame covered within this data sheet. Refer to the BOSCH CAN • Overload Frame Reception specification for further details. The CAN module uses the RB2/CANTX and The module features are as follows: RB3/CANRX pins to interface with the CAN bus. The • Implementation of the CAN protocol, CAN 1.2, CANTX and CANRX pins can be placed on alternate CAN 2.0A and CAN 2.0B I/Opins by setting the CANMX (CONFIG3H<0>) • DeviceNetTM data bytes filter support Configuration bit. • Standard and extended data frames For the PIC18F2XK80 and PIC18F4XK80, the alter- • 0-8 bytes data length nate pin locations are RC6/CANTX and RC7/CANRX. • Programmable bit rate up to 1 Mbit/sec For the PIC18F6XK80, the alternate pin locations are • Fully backward compatible with the PIC18XXX8 RE4/CANRX and RE5/CANTX. CAN module In normal mode, the CAN module automatically over- • Three modes of operation: rides the appropriate TRIS bit for CANTX. The user - Mode 0 – Legacy mode must ensure that the appropriate TRIS bit for CANRX - Mode 1 – Enhanced Legacy mode with is set. DeviceNet support - Mode 2 – FIFO mode with DeviceNet support 27.1.1 MODULE FUNCTIONALITY • Support for remote frames with automated handling The CAN bus module consists of a protocol engine, • Double-buffered receiver with two prioritized message buffering and control (see Figure 27-1). The received message storage buffers protocol engine can best be understood by defining the • Six buffers programmable as RX and TX types of data frames to be transmitted and received by message buffers the module. • 16 full (standard/extended identifier) acceptance The following sequence illustrates the necessary initial- filters that can be linked to one of four masks ization steps before the ECAN module can be used to • Two full acceptance filter masks that can be transmit or receive a message. Steps can be added or assigned to any filter removed depending on the requirements of the • One full acceptance filter that can be used as either application. an acceptance filter or acceptance filter mask 1. Initial LAT and TRIS bits for RX and TX CAN. • Three dedicated transmit buffers with application specified prioritization and abort capability 2. Ensure that the ECAN module is in Configuration • Programmable wake-up functionality with mode. integrated low-pass filter 3. Select ECAN Operational mode. • Programmable Loopback mode supports self-test 4. Set up the Baud Rate registers. operation 5. Set up the Filter and Mask registers. • Signaling via interrupt capabilities for all CAN 6. Set the ECAN module to normal mode or any receiver and transmitter error states other mode required by the application logic. • Programmable clock source • Programmable link to timer module for time-stamping and network synchronization • Low-power Sleep mode DS30009977G-page 382  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 27-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS k 16 - 4 to 1 MUXs s a M e 0 cM TXB0 TXB1 TXB2 Ac(RceXpFta0n-RceX FF0ilt5e)rs VCC ceptanRX A MODE 0 c A MSGREQABTFMLOATXERRMTXBUFF MESSAGE MSGREQABTFMLOATXERRMTXBUFF MESSAGE MSGREQABTFMLOATXERRMTXBUFF MESSAGE ccep Acceptance Filters RXF15 e Mask1 t (RMXFO0D6E-R 1X, F215) ptancRXM e c c Message MODE 0 A Queue 2 RX Identifier Buffers M Control A Transmit Byte Sequencer Data Field B MODE 1, 2 Rcv Byte 6 TX/RX Buffers Transmit Option MESSAGE BUFFERS PROTOCOL Receive REC ENGINE Error Counter TEC Transmit Err-Pas Error Bus-Off Counter Transmit<7:0> Receive<8:0> Shift<14:0> {Transmit<5:0>, Receive<8:0>} Comparator Protocol Finite State CRC<14:0> Machine Bit Transmit Clock Timing Logic Generator Logic Configuration TX RX Registers  2010-2017 Microchip Technology Inc. DS30009977G-page 383

PIC18F66K80 FAMILY 27.2 CAN Module Registers 27.2.1 CAN CONTROL AND STATUS REGISTERS Note: Not all CAN registers are available in the The registers described in this section control the Access Bank. overall operation of the CAN module and show its There are many control and data registers associated operational status. with the CAN module. For convenience, their descriptions have been grouped into the following sections: • Control and Status Registers • Dedicated Transmit Buffer Registers • Dedicated Receive Buffer Registers • Programmable TX/RX and Auto RTR Buffers • Baud Rate Control Registers • I/O Control Register • Interrupt Status and Control Registers Detailed descriptions of each register and their usage are described in the following sections. DS30009977G-page 384  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-1: CANCON: CAN CONTROL REGISTER R/W-1 R/W-0 R/W-0 R/S-0 R/W-0 R/W-0 R/W-0 U-0 Mode 0 REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — R/W-1 R/W-0 R/W-0 R/S-0 U0 U-0 U-0 U-0 Mode 1 REQOP2 REQOP1 REQOP0 ABAT — — — — R/W-1 R/W-0 R/W-0 R/S-0 R-0 R-0 R-0 R-0 Mode 2 REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0 bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 REQOP<2:0>: Request CAN Operation Mode bits 1xx = Requests Configuration mode 011 = Requests Listen Only mode 010 = Requests Loopback mode 001 = Disabled/Sleep mode 000 = Requests Normal mode bit 4 ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers)(1) 0 = Transmissions proceeding as normal bit 3-1 Mode 0: WIN<2:0>: Window Address bits These bits select which of the CAN buffers to switch into the Access Bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE<3:0> bits can be copied to the WIN<2:0> bits to select the correct buffer. See Example27-2 for a code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 bit 0 Mode 0: Unimplemented: Read as ‘0’ bit 4-0 Mode 1: Unimplemented: Read as ‘0’ Mode 2: FP<3:0>: FIFO Read Pointer bits These bits point to the message buffer to be read. 0000 = Receive Message Buffer 0 0001 = Receive Message Buffer 1 0010 = Receive Message Buffer 2 0011 = Receive Message Buffer 3 0100 = Receive Message Buffer 4 0101 = Receive Message Buffer 5 0110 = Receive Message Buffer 6 0111 = Receive Message Buffer 7 1000:1111 Reserved Note 1: This bit will clear when all transmissions are aborted.  2010-2017 Microchip Technology Inc. DS30009977G-page 385

PIC18F66K80 FAMILY REGISTER 27-2: CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 R-0 R-0 R-0 R-0 U-0 Mode 0 OPMODE2(1) OPMODE1(1) OPMODE0(1) — ICODE2 ICODE1 ICODE0 — R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1,2 OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 EICODE2 EICODE1 EICODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 OPMODE<2:0>: Operation Mode Status bits(1) 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable/Sleep mode 000 = Normal mode bit 4 Mode 0: Unimplemented: Read as ‘0’ bit 3-1,4-0 Mode 0: ICODE<2:0>: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. By copying ICODE<3:1> to WIN<3:0> (Mode0) or EICODE<4:0> to EWIN<4:0> (Mode 1 and 2), it is possible to select the correct buffer to map into the Access Bank area. See Example27-2 for a code example. To simplify the description, the following table lists all five bits. Mode 0 Mode 1 Mode 2 No interrupt 00000 00000 00000 CAN bus error interrupt 00010 00010 00010 TXB2 interrupt 00100 00100 00100 TXB1 interrupt 00110 00110 00110 TXB0 interrupt 01000 01000 01000 RXB1 interrupt 01010 10001 ----- RXB0 interrupt 01100 10000 10000 Wake-up interrupt 01110 01110 01110 RXB0 interrupt ----- 10000 10000 RXB1 interrupt ----- 10001 10000 RX/TX B0 interrupt ----- 10010 10010(2) RX/TX B1 interrupt ----- 10011 10011(2) RX/TX B2 interrupt ----- 10100 10100(2) RX/TX B3 interrupt ----- 10101 10101(2) RX/TX B4 interrupt ----- 10110 10110(2) RX/TX B5 interrupt ----- 10111 10111(2) bit 0 Mode 0: Unimplemented: Read as ‘0’ bit 4-0 Mode 1, 2: EICODE<4:0>: Interrupt Code bits See ICODE<3:1> above. Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch the CAN module in Disable/Sleep mode before putting the device to Sleep. 2: If the buffer is configured as a receiver, the EICODE bits will contain ‘10000’ upon interrupt. DS30009977G-page 386  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY EXAMPLE 27-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B’10000000’ ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing. ConfigWait: MOVF CANSTAT, W ; Read current mode state. ANDLW B’10000000’ ; Interested in OPMODE bits only. TSTFSZ WREG ; Is it Configuration mode yet? BRA ConfigWait ; No. Continue to wait... ; Module is in Configuration mode now. ; Modify configuration registers as required. ; Switch back to Normal mode to be able to communicate. EXAMPLE 27-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low MOVFF CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred MOVFF CANSTAT, TempCANSTAT ; Save CANSTAT register ; This is required to make sure that ; we use same CANSTAT value rather ; than one changed by another CAN ; interrupt. MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B’00001110’ ADDWF PCL, F ; Perform computed GOTO ; to corresponding interrupt cause BRA NoInterrupt ; 000 = No interrupt BRA ErrorInterrupt ; 001 = Error interrupt BRA TXB2Interrupt ; 010 = TXB2 interrupt BRA TXB1Interrupt ; 011 = TXB1 interrupt BRA TXB0Interrupt ; 100 = TXB0 interrupt BRA RXB1Interrupt ; 101 = RXB1 interrupt BRA RXB0Interrupt ; 110 = RXB0 interrupt ; 111 = Wake-up on interrupt WakeupInterrupt BCF PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here … NoInterrupt … ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error.  2010-2017 Microchip Technology Inc. DS30009977G-page 387

PIC18F66K80 FAMILY EXAMPLE 27-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag … ; Handle error. RETFIE TXB2Interrupt BCF PIR3, TXB2IF ; Clear the interrupt flag GOTO AccessBuffer TXB1Interrupt BCF PIR3, TXB1IF ; Clear the interrupt flag GOTO AccessBuffer TXB0Interrupt BCF PIR3, TXB0IF ; Clear the interrupt flag GOTO AccessBuffer RXB1Interrupt BCF PIR3, RXB1IF ; Clear the interrupt flag GOTO Accessbuffer RXB0Interrupt BCF PIR3, RXB0IF ; Clear the interrupt flag GOTO AccessBuffer AccessBuffer ; This is either TX or RX interrupt ; Copy CANSTAT.ICODE bits to CANCON.WIN bits MOVF TempCANCON, W ; Clear CANCON.WIN bits before copying ; new ones. ANDLW B’11110001’ ; Use previously saved CANCON value to ; make sure same value. MOVWF TempCANCON ; Copy masked value back to TempCANCON MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B’00001110’ ; Use previously saved CANSTAT value ; to make sure same value. IORWF TempCANCON ; Copy ICODE bits to WIN bits. MOVFF TempCANCON, CANCON ; Copy the result to actual CANCON ; Access current buffer… ; User code ; Restore CANCON.WIN bits MOVF CANCON, W ; Preserve current non WIN bits ANDLW B’11110001’ IORWF TempCANCON ; Restore original WIN bits ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source DS30009977G-page 388  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-3: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 MDSEL1(1) MDSEL0(1) FIFOWM(2) EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 MDSEL<1:0>: Mode Select bits(1) 00 = Legacy mode (Mode 0, default) 01 = Enhanced Legacy mode (Mode 1) 10 = Enhanced FIFO mode (Mode 2) 11 = Reserved bit 5 FIFOWM: FIFO High Water Mark bit(2) 1 = Will cause FIFO interrupt when one receive buffer remains 0 = Will cause FIFO interrupt when four receive buffers remain(3) bit 4-0 EWIN<4:0>: Enhanced Window Address bits These bits map the group of 16 banked CAN SFRs into Access Bank addresses, 0F60-0F6Dh. The exact group of registers to map is determined by the binary value of these bits. Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: 00000 = Acceptance Filters 0, 1, 2 and BRGCON2, 3 00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON 00010 = Acceptance Filter Masks, Error and Interrupt Control 00011 = Transmit Buffer 0 00100 = Transmit Buffer 1 00101 = Transmit Buffer 2 00110 = Acceptance Filters 6, 7, 8 00111 = Acceptance Filters 9, 10, 11 01000 = Acceptance Filters 12, 13, 14 01001 = Acceptance Filter 15 01010-01110 = Reserved 01111 = RXINT0, RXINT1 10000 = Receive Buffer 0 10001 = Receive Buffer 1 10010 = TX/RX Buffer 0 10011 = TX/RX Buffer 1 10100 = TX/RX Buffer 2 10101 = TX/RX Buffer 3 10110 = TX/RX Buffer 4 10111 = TX/RX Buffer 5 11000-11111 = Reserved Note 1: These bits can only be changed in Configuration mode. See Register27-1 to change to Configuration mode. 2: This bit is used in Mode 2 only. 3: If FIFO is configured to contain four or less buffers, then the FIFO interrupt will trigger.  2010-2017 Microchip Technology Inc. DS30009977G-page 389

PIC18F66K80 FAMILY REGISTER 27-4: COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1 — RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 2 FIFOEMPTY RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Mode 0: RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 has overflowed 0 = Receive Buffer 0 has not overflowed Mode 1: Unimplemented: Read as ‘0’ Mode 2: FIFOEMPTY: FIFO Not Empty bit 1 = Receive FIFO is not empty 0 = Receive FIFO is empty bit 6 Mode 0: RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 has overflowed 0 = Receive Buffer 1 has not overflowed Mode 1, 2: RXBnOVFL: Receive Buffer n Overflow bit 1 = Receive Buffer n has overflowed 0 = Receive Buffer n has not overflowed bit 5 TXBO: Transmitter Bus-Off bit 1 = Transmit error counter > 255 0 = Transmit error counter 255 bit 4 TXBP: Transmitter Bus Passive bit 1 = Transmit error counter > 127 0 = Transmit error counter 127 bit 3 RXBP: Receiver Bus Passive bit 1 = Receive error counter > 127 0 = Receive error counter 127 bit 2 TXWARN: Transmitter Warning bit 1 = Transmit error counter > 95 0 = Transmit error counter 95 bit 1 RXWARN: Receiver Warning bit 1 = 127  Receive error counter > 95 0 = Receive error counter  95 bit 0 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits. 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set DS30009977G-page 390  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers. REGISTER 27-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0  n  2] R/C-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 Mode 0 TXBIF TXABT(1) TXLARB(1) TXERR(1) TXREQ(2) — TXPRI1(3) TXPRI0(3) R/C-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 Mode 1,2 TXBIF TXABT(1) TXLARB(1) TXERR(1) TXREQ(2) — TXPRI1(3) TXPRI0(3) bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXBIF: Transmit Buffer Interrupt Flag bit 1 = Transmit buffer has completed transmission of a message and may be reloaded 0 = Transmit buffer has not completed transmission of a message bit 6 TXABT: Transmission Aborted Status bit(1) 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit(2) 1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits 0 = Automatically cleared when the message is successfully sent bit 2 Unimplemented: Read as ‘0’ bit 1-0 TXPRI<1:0>: Transmit Priority bits(3) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) Note 1: This bit is automatically cleared when TXREQ is set. 2: While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in software while the bit is set will request a message abort. 3: These bits define the order in which transmit buffers will be transferred. They do not alter the CAN message identifier.  2010-2017 Microchip Technology Inc. DS30009977G-page 391

PIC18F66K80 FAMILY REGISTER 27-6: TXBnSIDH: TRANSMIT BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0  n  2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXIDE = 1). REGISTER 27-7: TXBnSIDL: TRANSMIT BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, LOW BYTE [0  n  2] R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits, EID<20:18> (if EXIDE = 1). bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended ID, SID<10:0> become EID<28:18> 0 = Message will transmit standard ID, EID<17:0> are ignored bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits REGISTER 27-8: TXBnEIDH: TRANSMIT BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0  n  2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier bits (not used when transmitting standard identifier message) DS30009977G-page 392  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-9: TXBnEIDL: TRANSMIT BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0  n  2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier bits (not used when transmitting standard identifier message) REGISTER 27-10: TXBnDm: TRANSMIT BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS [0  n  2, 0  m  7] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TXBnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7.  2010-2017 Microchip Technology Inc. DS30009977G-page 393

PIC18F66K80 FAMILY REGISTER 27-11: TXBnDLC: TRANSMIT BUFFER ‘n’ DATA LENGTH CODE REGISTERS [0  n  2] U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmit Remote Frame Transmission Request bit 1 = Transmitted message will have the TXRTR bit set 0 = Transmitted message will have the TXRTR bit cleared bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 DLC<3:0>: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes REGISTER 27-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TEC<7:0>: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11consecutive recessive bits, the counter value is cleared. DS30009977G-page 394  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY EXAMPLE 27-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected. BANKSELTXB0CON ; One BANKSEL in beginning will make sure that we are ; in correct bank for rest of the buffer access. ; Now load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF TXB0D0 ; Compiler will automatically set “BANKED” bit ; Load rest of data bytes - up to 8 bytes into TXB0 buffer. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF TXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF TXB0SIDH ; No need to load TXB0EIDL:TXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B’00001000’ ; Normal priority; Request transmission MOVWF TXB0CON ; If required, wait for message to get transmitted BTFSC TXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted.  2010-2017 Microchip Technology Inc. DS30009977G-page 395

PIC18F66K80 FAMILY EXAMPLE 27-4: TRANSMITTING A CAN MESSAGE USING WIN BITS ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area. MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON ; register to preserve all other bits. If operation ; mode is already known, there is no need to preserve ; other bits. ANDLW B’11110000’ ; Clear WIN bits. IORLW B’00001000’ ; Select Transmit Buffer 0 MOVWF CANCON ; Apply the changes. ; Now TXB0 is mapped in place of RXB0. All future access to RXB0 registers will actually ; yield TXB0 register values. ; Load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF RXB0D0 ; Access TXB0D0 via RXB0D0 address. ; Load rest of the data bytes - up to 8 bytes into “TXB0” buffer using RXB0 registers. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF RXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF RXB0SIDH ; No need to load RXB0EIDL:RXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B’00001000’ ; Normal priority; Request transmission MOVWF RXB0CON ; If required, wait for message to get transmitted BTFSC RXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted. ; If required, reset the WIN bits to default state. DS30009977G-page 396  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers. REGISTER 27-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 Mode 0 RXFUL(1) RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF(2) FILHIT0 R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1,2 RXFUL(1) RXM1 RTRRO FILHITF4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message bit 6,6-5 Mode 0: RXM<1:0>: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’ 01 = Receive only valid messages with standard identifier; EXIDEN in RXFnSIDL must be ‘0’ 00 = Receive all valid messages as per the EXIDEN bit in the RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters bit 5 Mode 0: RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0>bits, see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received bit 4 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: FILHIT<4:0>: Filter Hit bit 4 This bit combines with other bits to form filter acceptance bits<4:0>. bit 3 Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT<4:0>: Filter Hit bit 3 This bit combines with other bits to form filter acceptance bits<4:0>. Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. After clearing the RXFUL flag, the PIR5 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is not cleared, then RXB0IF is set again. 2: This bit allows the same filter jump table for both RXB0CON and RXB1CON.  2010-2017 Microchip Technology Inc. DS30009977G-page 397

PIC18F66K80 FAMILY REGISTER 27-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT<4:0>: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits<4:0>. bit 1 Mode 0: JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)(2) 1 = Allows jump table offset between 6 and 7 0 = Allows jump table offset between 1 and 0 Mode 1, 2: FILHIT<4:0>: Filter Hit bit 1 This bit combines with other bits to form filter acceptance bits<4:0>. bit 0 Mode 0: FILHIT0: Filter Hit bit 0 This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0. 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Mode 1, 2: FILHIT<4:0>: Filter Hit bit 0 This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. After clearing the RXFUL flag, the PIR5 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is not cleared, then RXB0IF is set again. 2: This bit allows the same filter jump table for both RXB0CON and RXB1CON. DS30009977G-page 398  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 Mode 0 RXFUL(1) RXM1 RXM0 — RXRTRRO FILHIT2 FILHIT1 FILHIT0 R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1,2 RXFUL(1) RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message bit 6-5, 6 Mode 0: RXM<1:0>: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’ 01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’ 00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters bit 5 Mode 0: RXM<1:0>: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0> bits, see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received bit 4 Mode 0: FILHIT24: Filter Hit bit 4 Mode 1, 2: FILHIT<4:0>: Filter Hit bit 4 This bit combines with other bits to form the filter acceptance bits<4:0>. bit 3 Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT<4:0>: Filter Hit bit 3 This bit combines with other bits to form the filter acceptance bits<4:0>. Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full.  2010-2017 Microchip Technology Inc. DS30009977G-page 399

PIC18F66K80 FAMILY REGISTER 27-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER (CONTINUED) bit 2-0 Mode 0: FILHIT<2:0>: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1. 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set Mode 1, 2: FILHIT<4:0>: Filter Hit bits<2:0> These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. REGISTER 27-15: RXBnSIDH: RECEIVE BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0  n  1] R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier bits (if EXID (RXBnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXID = 1). DS30009977G-page 400  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-16: RXBnSIDL: RECEIVE BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, LOW BYTE [0  n  1] R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if EXID = 1). bit 4 SRR: Substitute Remote Request bit bit 3 EXID: Extended Identifier bit 1 = Received message is an extended data frame, SID<10:0> are EID<28:18> 0 = Received message is a standard data frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits REGISTER 27-17: RXBnEIDH: RECEIVE BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0  n  1] R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier bits REGISTER 27-18: RXBnEIDL: RECEIVE BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0  n  1] R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier bits  2010-2017 Microchip Technology Inc. DS30009977G-page 401

PIC18F66K80 FAMILY REGISTER 27-19: RXBnDLC: RECEIVE BUFFER ‘n’ DATA LENGTH CODE REGISTERS [0  n  1] U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 R0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as ‘0’. bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as ‘0’. bit 3-0 DLC<3:0>: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 byte 0000 = Data length = 0 bytes REGISTER 27-20: RXBnDm: RECEIVE BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS [0  n  1, 0  m  7] R-x R-x R-x R-x R-x R-x R-x R-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RXBnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 1 and 0 < m < 7) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7. DS30009977G-page 402  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 REC<7:0>: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications. When RXERRCNT> 127, the module will go into an error-passive state. RXERRCNT does not have the ability to put the module in “bus-off” state. EXAMPLE 27-5: READING A CAN MESSAGE ; Need to read a pending message from RXB0 buffer. ; To receive any message, filter, mask and RXM1:RXM0 bits in RXB0CON registers must be ; programmed correctly. ; ; Make sure that there is a message pending in RXB0. BTFSS RXB0CON, RXFUL ; Does RXB0 contain a message? BRA NoMessage ; No. Handle this situation... ; We have verified that a message is pending in RXB0 buffer. ; If this buffer can receive both Standard or Extended Identifier messages, ; identify type of message received. BTFSS RXB0SIDL, EXID ; Is this Extended Identifier? BRA StandardMessage ; No. This is Standard Identifier message. ; Yes. This is Extended Identifier message. ; Read all 29-bits of Extended Identifier message. ... ; Now read all data bytes MOVFF RXB0DO, MY_DATA_BYTE1 ... ; Once entire message is read, mark the RXB0 that it is read and no longer FULL. BCF RXB0CON, RXFUL ; This will allow CAN Module to load new messages ; into this buffer. ...  2010-2017 Microchip Technology Inc. DS30009977G-page 403

PIC18F66K80 FAMILY 27.2.3.1 Programmable TX/RX and Auto-RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. Note: These registers are not used in Mode 0. REGISTER 27-22: BnCON: TX/RX BUFFER ‘n’ CONTROL REGISTERS IN RECEIVE MODE [0  n  5, TXnEN (BSEL0<n>) = 0](1) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 RXFUL(2) RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RXFUL: Receive Full Status bit(2) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message bit 6 RXM1: Receive Buffer Mode bit 1 = Receive all messages including partial and invalid (acceptance filters are ignored) 0 = Receive all valid messages as per acceptance filters bit 5 RXRTRRO: Read-Only Remote Transmission Request for Received Message bit 1 = Received message is a remote transmission request 0 = Received message is not a remote transmission request bit 4-0 FILHIT<4:0>: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into this buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00001 = Acceptance Filter 1 (RXF1) 00000 = Acceptance Filter 0 (RXF0) Note 1: These registers are available in Mode 1 and 2 only. 2: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. DS30009977G-page 404  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-23: BnCON: TX/RX BUFFER ‘n’ CONTROL REGISTERS IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0<n>) = 1](1) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXBIF(3) TXABT(3) TXLARB(3) TXERR(3) TXREQ(2,4) RTREN TXPRI1(5) TXPRI0(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXBIF: Transmit Buffer Interrupt Flag bit(3) 1 = A message was successfully transmitted 0 = No message was transmitted bit 6 TXABT: Transmission Aborted Status bit(3) 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit(3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit(3) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit(2,4) 1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits 0 = Automatically cleared when the message is successfully sent bit 2 RTREN: Automatic Remote Transmission Request Enable bit 1 = When a remote transmission request is received, TXREQ will be automatically set 0 = When a remote transmission request is received, TXREQ will be unaffected bit 1-0 TXPRI<1:0>: Transmit Priority bits(5) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) Note 1: These registers are available in Mode 1 and 2 only. 2: Clearing this bit in software while the bit is set will request a message abort. 3: This bit is automatically cleared when TXREQ is set. 4: While TXREQ is set or a transmission is in progress, Transmit Buffer registers remain read-only. 5: These bits set the order in which the Transmit Buffer register will be transferred. They do not alter the CAN message identifier.  2010-2017 Microchip Technology Inc. DS30009977G-page 405

PIC18F66K80 FAMILY REGISTER 27-24: BnSIDH: TX/RX BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXIDE = 1). Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-25: BnSIDH: TX/RX BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXIDE = 1). Note 1: These registers are available in Mode 1 and 2 only. DS30009977G-page 406  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-26: BnSIDL: TX/RX BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if EXID = 1). bit 4 SRR: Substitute Remote Transmission Request bit This bit is always ‘1’ when EXID = 1 or equal to the value of RXRTRRO (BnCON<5>) when EXID = 0. bit 3 EXIDE: Extended Identifier Enable bit 1 = Received message is an extended identifier frame (SID<10:0> are EID<28:18>) 0 = Received message is a standard identifier frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-27: BnSIDL: TX/RX BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, LOW BYTE IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits, EID<20:18> (if EXIDE = 1). bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended ID, SID<10:0> bits become EID<28:18> 0 = Received will transmit standard ID, EID<17:0> are ignored bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only.  2010-2017 Microchip Technology Inc. DS30009977G-page 407

PIC18F66K80 FAMILY REGISTER 27-28: BnEIDH: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-29: BnEIDH: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-30: BnEIDL: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. DS30009977G-page 408  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-31: BnEIDL: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 FEID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-32: BnDm: TX/RX BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS IN RECEIVE MODE [0  n  5, 0  m  7, TXnEN (BSEL<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 BnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to B0D7. Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-33: BnDm: TX/RX BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS IN TRANSMIT MODE [0  n  5, 0  m  7, TXnEN (BSEL<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 BnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. Note 1: These registers are available in Mode 1 and 2 only.  2010-2017 Microchip Technology Inc. DS30009977G-page 409

PIC18F66K80 FAMILY REGISTER 27-34: BnDLC: TX/RX BUFFER ‘n’ DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0  n  5, TXnEN (BSEL<n>) = 0](1) U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = This is a remote transmission request 0 = This is not a remote transmission request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as ‘0’. bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as ‘0’. bit 3-0 DLC<3:0>: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 byte 0000 = Data length = 0 bytes Note 1: These registers are available in Mode 1 and 2 only. DS30009977G-page 410  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-35: BnDLC: TX/RX BUFFER ‘n’ DATA LENGTH CODE REGISTERS IN TRANSMIT MODE [0  n  5, TXnEN (BSEL<n>) = 1](1) U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmitter Remote Transmission Request bit 1 = Transmitted message will have the RTR bit set 0 = Transmitted message will have the RTR bit cleared bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 DLC<3:0>: Data Length Code bits 1111-1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 byte 0000 = Data length = 0 bytes Note 1: These registers are available in Mode 1 and 2 only. REGISTER 27-36: BSEL0: BUFFER SELECT REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 B<5:0>TXEN: Buffer 5 to Buffer 0 Transmit Enable bits 1 = Buffer is configured in Transmit mode 0 = Buffer is configured in Receive mode bit 1-0 Unimplemented: Read as ‘0’ Note 1: These registers are available in Mode 1 and 2 only.  2010-2017 Microchip Technology Inc. DS30009977G-page 411

PIC18F66K80 FAMILY 27.2.3.2 Message Acceptance Filters and Masks This section describes the message acceptance filters and masks for the CAN receive buffers. REGISTER 27-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER ‘n’ STANDARD IDENTIFIER FILTER REGISTERS, HIGH BYTE [0  n  15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier Filter bits (if EXIDEN = 0) Extended Identifier Filter bits, EID<28:21> (if EXIDEN = 1). Note 1: Registers, RXF6SIDH:RXF15SIDH, are available in Mode 1 and 2 only. REGISTER 27-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER ‘n’ STANDARD IDENTIFIER FILTER REGISTERS, LOW BYTE [0  n  15](1) R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN(2) — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier Filter bits (if EXIDEN = 0) Extended Identifier Filter bits, EID<20:18> (if EXIDEN = 1). bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDEN: Extended Identifier Filter Enable bit(2) 1 = Filter will only accept extended ID messages 0 = Filter will only accept standard ID messages bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier Filter bits Note 1: Registers, RXF6SIDL:RXF15SIDL, are available in Mode 1 and 2 only. 2: In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value. DS30009977G-page 412  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER ‘n’ EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0  n  15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier Filter bits Note 1: Registers, RXF6EIDH:RXF15EIDH, are available in Mode 1 and 2 only. REGISTER 27-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER ‘n’ EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0  n  15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier Filter bits Note 1: Registers, RXF6EIDL:RXF15EIDL, are available in Mode 1 and 2 only. REGISTER 27-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK ‘n’ STANDARD IDENTIFIER MASK REGISTERS, HIGH BYTE [0  n  1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<28:21>)  2010-2017 Microchip Technology Inc. DS30009977G-page 413

PIC18F66K80 FAMILY REGISTER 27-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK ‘n’ STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0  n  1] R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN(1) — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<20:18>) bit 4 Unimplemented: Read as ‘0’ bit 3 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: EXIDEN: Extended Identifier Filter Enable Mask bit(1) 1 = Messages selected by the EXIDEN bit in RXFnSIDL will be accepted 0 = Both standard and extended identifier messages will be accepted bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier Mask bits Note 1: This bit is available in Mode 1 and 2 only. REGISTER 27-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK ‘n’ EXTENDED IDENTIFIER MASK REGISTERS, HIGH BYTE [0  n  1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier Mask bits REGISTER 27-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK ‘n’ EXTENDED IDENTIFIER MASK REGISTERS, LOW BYTE [0  n  1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier Mask bits DS30009977G-page 414  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER ‘n’ [0  n  1](1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFCON0 RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFCON1 RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RXF<7:0>EN: Receive Filter n Enable bits 0 = Filter is disabled 1 = Filter is enabled Note 1: This register is available in Mode 1 and 2 only. Note: Register27-46 through Register27-51 are writable in Configuration mode only. REGISTER 27-46: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLC4 FLC3 FLC2 FLC1 FLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 FLC<4:0>: Filter Length Count bits Mode 0: Not used; forced to ‘00000’. 00000-10010 =0 18 bits are available for standard data byte filter. Actual number of bits used depends on the DLC<3:0> bits (RXBnDLC<3:0> or BnDLC<3:0> if configured as RX buffer) of the message being received. If DLC<3:0> =0000 No bits will be compared with incoming data bits. If DLC<3:0> =0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC<2:0>, will be com- pared with the corresponding number of data bits of the incoming message. If DLC<3:0> =0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC<3:0>, will be compared with the corresponding number of data bits of the incoming message. If DLC<3:0> =0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC<4:0>, will be compared with the corresponding number of data bits of the incoming message. Note 1: This register is available in Mode 1 and 2 only.  2010-2017 Microchip Technology Inc. DS30009977G-page 415

PIC18F66K80 FAMILY REGISTER 27-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER ‘n’(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON0 F1BP_3 F1BP_2 F1BP_1 F1BP_0 F0BP_3 F0BP_2 F0BP_1 F0BP_0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 RXFBCON1 F3BP_3 F3BP_2 F3BP_1 F3BP_0 F2BP_3 F2BP_2 F2BP_1 F2BP_0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 RXFBCON2 F5BP_3 F5BP_2 F5BP_1 F5BP_0 F4BP_3 F4BP_2 F4BP_1 F4BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON3 F7BP_3 F7BP_2 F7BP_1 F7BP_0 F6BP_3 F6BP_2 F6BP_1 F6BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON4 F9BP_3 F9BP_2 F9BP_1 F9BP_0 F8BP_3 F8BP_2 F8BP_1 F8BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON5 F11BP_3 F11BP_2 F11BP_1 F11BP_0 F10BP_3 F10BP_2 F10BP_1 F10BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON6 F13BP_3 F13BP_2 F13BP_1 F13BP_0 F12BP_3 F12BP_2 F12BP_1 F12BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON7 F15BP_3 F15BP_2 F15BP_1 F15BP_0 F14BP_3 F14BP_2 F14BP_1 F14BP_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 F<15:2>BP_<3:0>: Filter n Buffer Pointer Nibble bits 0000 = Filter n is associated with RXB0 0001 = Filter n is associated with RXB1 0010 = Filter n is associated with B0 0011 = Filter n is associated with B1 ... 0111 = Filter n is associated with B5 1111-1000 = Reserved Note 1: This register is available in Mode 1 and 2 only. DS30009977G-page 416  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FIL3_<1:0>: Filter 3 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL2_<1:0>: Filter 2 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL1_<1:0>: Filter 1 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL0_<1:0>: Filter 0 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: This register is available in Mode 1 and 2 only.  2010-2017 Microchip Technology Inc. DS30009977G-page 417

PIC18F66K80 FAMILY REGISTER 27-49: MSEL1: MASK SELECT REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FIL7_<1:0>: Filter 7 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL6_<1:0>: Filter 6 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL5_<1:0>: Filter 5 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL4_<1:0>: Filter 4 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: This register is available in Mode 1 and 2 only. DS30009977G-page 418  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-50: MSEL2: MASK SELECT REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FIL11_<1:0>: Filter 11 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL10_<1:0>: Filter 10 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL9_<1:0>: Filter 9 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL8_<1:0>: Filter 8 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: This register is available in Mode 1 and 2 only.  2010-2017 Microchip Technology Inc. DS30009977G-page 419

PIC18F66K80 FAMILY REGISTER 27-51: MSEL3: MASK SELECT REGISTER 3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FIL15_<1:0>: Filter 15 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL14_<1:0>: Filter 14 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL13_<1:0>: Filter 13 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL12_<1:0>: Filter 12 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: This register is available in Mode 1 and 2 only. DS30009977G-page 420  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.2.4 CAN BAUD RATE REGISTERS This section describes the CAN Baud Rate registers. Note: These registers are writable in Configuration mode only. REGISTER 27-52: BRGCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SJW<1:0>: Synchronized Jump Width bits 11 = Synchronization jump width time = 4 x TQ 10 = Synchronization jump width time = 3 x TQ 01 = Synchronization jump width time = 2 x TQ 00 = Synchronization jump width time = 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC : : 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC  2010-2017 Microchip Technology Inc. DS30009977G-page 421

PIC18F66K80 FAMILY REGISTER 27-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits 111 = Phase Segment 1 time = 8 x TQ 110 = Phase Segment 1 time = 7 x TQ 101 = Phase Segment 1 time = 6 x TQ 100 = Phase Segment 1 time = 5 x TQ 011 = Phase Segment 1 time = 4 x TQ 010 = Phase Segment 1 time = 3 x TQ 001 = Phase Segment 1 time = 2 x TQ 000 = Phase Segment 1 time = 1 x TQ bit 2-0 PRSEG<2:0>: Propagation Time Select bits 111 = Propagation time = 8 x TQ 110 = Propagation time = 7 x TQ 101 = Propagation time = 6 x TQ 100 = Propagation time = 5 x TQ 011 = Propagation time = 4 x TQ 010 = Propagation time = 3 x TQ 001 = Propagation time = 2 x TQ 000 = Propagation time = 1 x TQ DS30009977G-page 422  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 WAKDIS WAKFIL — — — SEG2PH2(1) SEG2PH1(1) SEG2PH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAKDIS: Wake-up Disable bit 1 = Disable CAN bus activity wake-up feature 0 = Enable CAN bus activity wake-up feature bit 6 WAKFIL: Selects CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 SEG2PH<2:0>: Phase Segment 2 Time Select bits(1) 111 = Phase Segment 2 time = 8 x TQ 110 = Phase Segment 2 time = 7 x TQ 101 = Phase Segment 2 time = 6 x TQ 100 = Phase Segment 2 time = 5 x TQ 011 = Phase Segment 2 time = 4 x TQ 010 = Phase Segment 2 time = 3 x TQ 001 = Phase Segment 2 time = 2 x TQ 000 = Phase Segment 2 time = 1 x TQ Note 1: These bits are ignored if SEG2PHTS bit (BRGCON2<7>) is ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 423

PIC18F66K80 FAMILY 27.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller. REGISTER 27-55: CIOCON: CAN I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 TX2SRC TX2EN ENDRHI(1) CANCAP — — — CLKSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TX2SRC: CANTX2 Pin Data Source bit 1 = CANTX2 pin will output the CAN clock 0 = CANTX2 pin will output CANTX bit 6 TX2EN: CANTX Pin Enable bit 1 = CANTX2 pin will output CANTX or CAN clock as selected by the TX2SRC bit 0 = CANTX2 pin will have digital I/O function bit 5 ENDRHI: Enable Drive High bit(1) 1 = CANTX pin will drive VDD when recessive 0 = CANTX pin will be tri-state when recessive bit 4 CANCAP: CAN Message Receive Capture Enable bit 1 = Enable CAN capture; CAN message receive signal replaces input on RC2/CCP2 0 = Disable CAN capture; RC2/CCP2 input to CCP2 module bit 3-1 Unimplemented: Read as ‘0’ bit 0 CLKSEL: CAN Clock Source Selection bit 1 = Use the oscillator as the source of the CAN system clock 0 = Use the PLL as the source of the CAN system clock Note 1: Always set this bit when using a differential bus to avoid signal crosstalk in CANTX from other nearby pins. DS30009977G-page 424  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section10.0 “Interrupts”. They are duplicated here for convenience. REGISTER 27-56: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 0 IRXIF WAKIF ERRIF TXB2IF TXB1IF(1) TXB0IF(1) RXB1IF RXB0IF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 1,2 IRXIF WAKIF ERRIF TXBnIF TXB1IF(1) TXB0IF(1) RXBnIF FIFOWMIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIF: CAN Bus Error Message Received Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on the CAN bus bit 6 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = Activity on the CAN bus has occurred 0 = No activity on the CAN bus bit 5 ERRIF: CAN Module Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources; refer to Section27.15.6 “Error Interrupt”) 0 = No CAN module errors bit 4 When CAN is in Mode 0: TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message When CAN is in Mode 1 or 2: TXBnIF: Any Transmit Buffer Interrupt Flag bit 1 = One or more transmit buffers have completed transmission of a message and may be reloaded 0 = No transmit buffer is ready for reload bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1) 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1) 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 When CAN is in Mode 0: RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2: RXBnIF: Any Receive Buffer Interrupt Flag bit 1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message bit 0 When CAN is in Mode 0: RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIF: FIFO Watermark Interrupt Flag bit 1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 425

PIC18F66K80 FAMILY REGISTER 27-57: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 0 IRXIE WAKIE ERRIE TXB2IE TXB1IE(1) TXB0IE(1) RXB1IE RXB0IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 1 IRXIE WAKIE ERRIE TXBnIE TXB1IE(1) TXB0IE(1) RXBnIE FIFOWMIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIE: CAN Bus Error Message Received Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN module error interrupt 0 = Disable CAN module error interrupt bit 4 When CAN is in Mode 0: TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt When CAN is in Mode 1 or 2: TXBnIE: CAN Transmit Buffer Interrupts Enable bit 1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 When CAN is in Mode 0: RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2: RXBnIE: CAN Receive Buffer Interrupts Enable bit 1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts bit 0 When CAN is in Mode 0: RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. DS30009977G-page 426  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 27-58: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Mode 0 IRXIP WAKIP ERRIP TXB2IP TXB1IP(1) TXB0IP(1) RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Mode 1,2 IRXIP WAKIP ERRIP TXBnIP TXB1IP(1) TXB0IP(1) RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIP: CAN Bus Error Message Received Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN Module Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 When CAN is in Mode 0: TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: TXBnIP: CAN Transmit Buffer Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 1 When CAN is in Mode 0: RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: RXBnIP: CAN Receive Buffer Interrupts Priority bit 1 = High priority 0 = Low priority bit 0 When CAN is in Mode 0: RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIP: FIFO Watermark Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.  2010-2017 Microchip Technology Inc. DS30009977G-page 427

PIC18F66K80 FAMILY REGISTER 27-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — TXB2IE(2) TXB1IE(2) TXB0IE(2) — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bits(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer interrupt is disabled bit 1-0 Unimplemented: Read as ‘0’ Note 1: This register is available in Mode 1 and 2 only. 2: TXBnIE in PIE5 register must be set to get an interrupt. REGISTER 27-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 B5IE(2) B4IE(2) B3IE(2) B2IE(2) B1IE(2) B0IE(2) RXB1IE(2) RXB0IE(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 B<5:0>IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bits(2) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1-0 RXB<1:0>IE: Dedicated Receive Buffer 1-0 Interrupt Enable bits(2) 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This register is available in Mode 1 and 2 only. 2: Either TXBnIE or RXBnIE, in the PIE5 register, must be set to get an interrupt. DS30009977G-page 428  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.3 CAN Modes of Operation 27.3.2 DISABLE/SLEEP MODE The PIC18F66K80 family has six main modes of In Disable/Sleep mode, the module will not transmit or operation: receive. The module has the ability to set the WAKIF bit due to bus activity; however, any pending interrupts will • Configuration mode remain and the error counters will retain their value. • Disable/Sleep mode If the REQOP<2:0> bits are set to ‘001’, the module will • Normal Operation mode enter the module Disable/Sleep mode. This mode is • Listen Only mode similar to disabling other peripheral modules by turning • Loopback mode off the module enables. This causes the module • Error Recognition mode internal clock to stop unless the module is active (i.e., receiving or transmitting a message). If the module is All modes, except Error Recognition, are requested by active, the module will wait for 11 recessive bits on the setting the REQOP bits (CANCON<7:5>). Error Recog- CAN bus, detect that condition as an Idle bus, then nition mode is requested through the RXM bits of the accept the module Disable/Sleep command. Receive Buffer register(s). Entry into a mode is OPMODE<2:0> = 001 indicates whether the module Acknowledged by monitoring the OPMODE bits. successfully went into the module Disable/Sleep mode. When changing modes, the mode will not actually The WAKIF interrupt is the only module interrupt that is change until all pending message transmissions are still active in the Disable/Sleep mode. If the WAKDIS is complete. Because of this, the user must verify that the cleared and WAKIE is set, the processor will receive an device has actually changed into the requested mode interrupt whenever the module detects recessive to before further operations are executed. dominant transition. On wake-up, the module will auto- matically be set to the previous mode of operation. For 27.3.1 CONFIGURATION MODE example, if the module was switched from Normal to The CAN module has to be initialized before the Disable/Sleep mode on bus activity wake-up, the activation. This is only possible if the module is in the module will automatically enter into Normal mode and Configuration mode. The Configuration mode is the first message that caused the module to wake-up is requested by setting the REQOP2 bit. Only when the lost. The module will not generate any error frame. status bit, OPMODE2, has a high level can the initial- Firmware logic must detect this condition and make ization be performed. Afterwards, the Configuration sure that retransmission is requested. If the processor registers, the acceptance mask registers and the receives a wake-up interrupt while it is sleeping, more acceptance filter registers can be written. The module than one message may get lost. The actual number of is activated by setting the REQOP control bits to zero. messages lost would depend on the processor The module will protect the user from accidentally oscillator start-up time and incoming message bit rate. violating the CAN protocol through programming The TXCAN pin will stay in the recessive state while the errors. All registers which control the configuration of module is in Disable/Sleep mode. the module can not be modified while the module is on-line. The CAN module will not be allowed to enter 27.3.3 NORMAL MODE the Configuration mode while a transmission or recep- This is the standard operating mode of the tion is taking place. The Configuration mode serves as PIC18F66K80 family devices. In this mode, the device a lock to protect the following registers: actively monitors all bus messages and generates • Configuration Registers Acknowledge bits, error frames, etc. This is also the • Functional Mode Selection Registers only mode in which the PIC18F66K80 family devices will transmit messages over the CAN bus. • Bit Timing Registers • Identifier Acceptance Filter Registers • Identifier Acceptance Mask Registers • Filter and Mask Control Registers • Mask Selection Registers In the Configuration mode, the module will not transmit or receive. The error counters are cleared and the inter- rupt flags remain unchanged. The programmer will have access to Configuration registers that are access restricted in other modes. I/O pins will revert to normal I/O functions.  2010-2017 Microchip Technology Inc. DS30009977G-page 429

PIC18F66K80 FAMILY 27.3.4 LISTEN ONLY MODE 27.4 CAN Module Functional Modes Listen Only mode provides a means for the In addition to CAN modes of operation, the ECAN mod- PIC18F66K80 family devices to receive all messages, ule offers a total of 3 functional modes. Each of these including messages with errors. This mode can be modes are identified as Mode 0, Mode 1 and Mode 2. used for bus monitor applications or for detecting the baud rate in ‘hot plugging’ situations. For auto-baud 27.4.1 MODE 0 – LEGACY MODE detection, it is necessary that there are at least two Mode 0 is designed to be fully compatible with CAN other nodes which are communicating with each other. modules used in PIC18CXX8 and PIC18FXX8 devices. The baud rate can be detected empirically by testing This is the default mode of operation on all Reset con- different values until valid messages are received. The ditions. As a result, module code written for the Listen Only mode is a silent mode, meaning no mes- PIC18XX8 CAN module may be used on the ECAN sages will be transmitted while in this state, including module without any code changes. error flags or Acknowledge signals. In Listen Only mode, both valid and invalid messages will be The following is the list of resources available in Mode 0: received, regardless of RXMn bit settings. The filters • Three transmit buffers: TXB0, TXB1 and TXB2 and masks can still be used to allow only particular • Two receive buffers: RXB0 and RXB1 valid messages to be loaded into the Receive registers, • Two acceptance masks, one for each receive or the filter masks can be set to all zeros to allow a mes- buffer: RXM0, RXM1 sage with any identifier to pass. All invalid messages will be received in this mode, regardless of filters and • Six acceptance filters, 2 for RXB0 and 4 for RXB1: masks or RXMn Receive Buffer mode bits.The error RXF0, RXF1, RXF2, RXF3, RXF4, RXF5 counters are reset and deactivated in this state. The 27.4.2 MODE 1 – ENHANCED LEGACY Listen Only mode is activated by setting the mode MODE request bits in the CANCON register. Mode 1 is similar to Mode 0, with the exception 27.3.5 LOOPBACK MODE thatmore resources are available in Mode 1. There are This mode will allow internal transmission of messages 16 acceptance filters and two acceptance mask regis- from the transmit buffers to the receive buffers without ters. Acceptance Filter 15 can be used as either an actually transmitting messages on the CAN bus. This acceptance filter or an acceptance mask register. In mode can be used in system development and testing. addition to three transmit and two receive buffers, there In this mode, the ACK bit is ignored and the device will are six more message buffers. One or more of these allow incoming messages from itself, just as if they additional buffers can be programmed as transmit or were coming from another node. The Loopback mode receive buffers. These additional buffers can also be is a silent mode, meaning no messages will be trans- programmed to automatically handle RTR messages. mitted while in this state, including error flags or Fourteen of sixteen acceptance filter registers can be Acknowledge signals. The TXCAN pin will revert to port dynamically associated to any receive buffer and I/O while the device is in this mode. The filters and acceptance mask register. One can use this capability masks can be used to allow only particular messages to associate more than one filter to any one buffer. to be loaded into the receive registers. The masks can When a receive buffer is programmed to use standard be set to all zeros to provide a mode that accepts all identifier messages, part of the full acceptance filter reg- messages. The Loopback mode is activated by setting ister can be used as a data byte filter. The length of the the mode request bits in the CANCON register. data byte filter is programmable from 0 to 18 bits. This 27.3.6 ERROR RECOGNITION MODE functionality simplifies implementation of high-level protocols, such as the DeviceNet™ protocol. The module can be set to ignore all errors and receive any message. In functional Mode 0, the Error Recogni- The following is the list of resources available in Mode 1: tion mode is activated by setting the RXM<1:0> bits in • Three transmit buffers: TXB0, TXB1 and TXB2 the RXBnCON registers to ‘11’. In this mode, the data • Two receive buffers: RXB0 and RXB1 which is in the message assembly buffer until the error • Six buffers programmable as TX or RX: B0-B5 time, is copied in the receive buffer and can be read via • Automatic RTR handling on B0-B5 the CPU interface. • Sixteen dynamically assigned acceptance filters: RXF0-RXF15 • Two dedicated acceptance mask registers; RXF15 programmable as third mask: RXM0-RXM1, RXF15 • Programmable data filter on standard identifier messages: SDFLC DS30009977G-page 430  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.4.3 MODE 2 – ENHANCED FIFO MODE Each receive buffer contains one Control register (RXBnCON), four Identifier registers (RXBnSIDL, In Mode 2, two or more receive buffers are used to form RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data Length the receive FIFO (first in, first out) buffer. There is no Count register (RXBnDLC) and eight Data Byte one-to-one relationship between the receive buffer and registers (RXBnDm). acceptance filter registers. Any filter that is enabled and linked to any FIFO receive buffer can generate There is also a separate Message Assembly Buffer acceptance and cause FIFO to be updated. (MAB) which acts as an additional receive buffer. MAB is always committed to receiving the next message FIFO length is user-programmable, from 2-8 buffers from the bus and is not directly accessible to user firm- deep. FIFO length is determined by the very first ware. The MAB assembles all incoming messages one programmable buffer that is configured as a transmit by one. A message is transferred to appropriate buffer. For example, if Buffer 2 (B2) is programmed as a receive buffers only if the corresponding acceptance transmit buffer, FIFO consists of RXB0, RXB1, B0 and filter criteria is met. B1, creating a FIFO length of 4. If all programmable buffers are configured as receive buffers, FIFO will have 27.5.3 PROGRAMMABLE the maximum length of 8. TRANSMIT/RECEIVE BUFFERS The following is the list of resources available in Mode 2: The ECAN module implements six new buffers: B0-B5. • Three transmit buffers: TXB0, TXB1 and TXB2 These buffers are individually programmable as either • Two receive buffers: RXB0 and RXB1 transmit or receive buffers. These buffers are available • Six buffers programmable as TX or RX; receive only in Mode 1 and 2. As with dedicated transmit and buffers form FIFO: B0-B5 receive buffers, each of these programmable buffers occupies 14 bytes of SRAM and are mapped into SFR • Automatic RTR handling on B0-B5 memory map. • Sixteen acceptance filters: RXF0-RXF15 Each buffer contains one Control register (BnCON), • Two dedicated acceptance mask registers; four Identifier registers (BnSIDL, BnSIDH, BnEIDL, RXF15 programmable as third mask: BnEIDH), one Data Length Count register (BnDLC) RXM0-RXM1, RXF15 and eight Data Byte registers (BnDm). Each of these • Programmable data filter on standard identifier registers contains two sets of control bits. Depending messages: SDFLC, useful for DeviceNet protocol on whether the buffer is configured as transmit or receive, one would use the corresponding control bit 27.5 CAN Message Buffers set. By default, all buffers are configured as receive buffers. Each buffer can be individually configured as a 27.5.1 DEDICATED TRANSMIT BUFFERS transmit or receive buffer by setting the corresponding The PIC18F66K80 family devices implement three TXENn bit in the BSEL0 register. dedicated transmit buffers – TXB0, TXB1 and TXB2. When configured as transmit buffers, user firmware Each of these buffers occupies 14 bytes of SRAM and may access transmit buffers in any order similar to are mapped into the SFR memory map. These are the accessing dedicated transmit buffers. In receive only transmit buffers available in Mode0. Mode 1 and configuration with Mode 1 enabled, user firmware may 2 may access these and other additional buffers. also access receive buffers in any order required. But Each transmit buffer contains one Control register in Mode 2, all receive buffers are combined to form a (TXBnCON), four Identifier registers (TXBnSIDL, single FIFO. Actual FIFO length is programmable by TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data Length user firmware. Access to FIFO must be done through Count register (TXBnDLC) and eight Data Byte the FIFO Pointer bits (FP<4:0>) in the CANCON registers (TXBnDm). register. It must be noted that there is no hardware protection against out of order FIFO reads. 27.5.2 DEDICATED RECEIVE BUFFERS The PIC18F66K80 family devices implement two dedi- cated receive buffers: RXB0 and RXB1. Each of these buffers occupies 14 bytes of SRAM and are mapped into SFR memory map. These are the only receive buf- fers available in Mode 0. Mode 1 and 2 may access these and other additional buffers.  2010-2017 Microchip Technology Inc. DS30009977G-page 431

PIC18F66K80 FAMILY 27.5.4 PROGRAMMABLE AUTO-RTR Setting the TXREQ bit does not initiate a message BUFFERS transmission; it merely flags a message buffer as ready for transmission. Transmission will start when the In Mode 1 and 2, any of six programmable trans- device detects that the bus is available. The device will mit/receive buffers may be programmed to automati- then begin transmission of the highest priority message cally respond to predefined RTR messages without that is ready. user firmware intervention. Automatic RTR handling is enabled by setting the TX2EN bit in the BSEL0 register When the transmission has completed successfully, the and the RTREN bit in the BnCON register. After this TXREQ bit will be cleared, the TXBnIF bit will be set and setup, when an RTR request is received, the TXREQ an interrupt will be generated if the TXBnIE bit is set. bit is automatically set and the current buffer content is If the message transmission fails, the TXREQ will remain automatically queued for transmission as a RTR set, indicating that the message is still pending for trans- response. As with all transmit buffers, once the TXREQ mission and one of the following condition flags will be bit is set, buffer registers become read-only and any set. If the message started to transmit but encountered writes to them will be ignored. an error condition, the TXERR and the IRXIF bits will be The following outlines the steps required to set and an interrupt will be generated. If the message lost automatically handle RTR messages: arbitration, the TXLARB bit will be set. 1. Set buffer to Transmit mode by setting the 27.6.2 ABORTING TRANSMISSION TXnEN bit to ‘1’ in the BSEL0 register. The MCU can request to abort a message by clearing 2. At least one acceptance filter must be associ- the TXREQ bit associated with the corresponding mes- ated with this buffer and preloaded with the sage buffer (TXBnCON<3> or BnCON<3>). Setting the expected RTR identifier. ABAT bit (CANCON<4>) will request an abort of all 3. Bit, RTREN in the BnCON register, must be set pending messages. If the message has not yet started to ‘1’. transmission, or if the message started but is interrupted 4. Buffer must be preloaded with the data to be by loss of arbitration or an error, the abort will be pro- sent as a RTR response. cessed. The abort is indicated when the module sets the Normally, user firmware will keep buffer data registers TXABT bit for the corresponding buffer (TXBnCON<6> up to date. If firmware attempts to update the buffer or BnCON<6>). If the message has started to transmit, while an automatic RTR response is in the process of it will attempt to transmit the current message fully. If the transmission, all writes to buffers are ignored. current message is transmitted fully and is not lost to arbitration or an error, the TXABT bit will not be set 27.6 CAN Message Transmission because the message was transmitted successfully. Likewise, if a message is being transmitted during an 27.6.1 INITIATING TRANSMISSION abort request and the message is lost to arbitration or an error, the message will not be retransmitted and the For the MCU to have write access to the message buf- TXABT bit will be set, indicating that the message was fer, the TXREQ bit must be clear, indicating that the successfully aborted. message buffer is clear of any pending message to be Once an abort is requested by setting the ABAT or transmitted. At a minimum, the SIDH, SIDL and DLC TXABT bits, it cannot be cleared to cancel the abort registers must be loaded. If data bytes are present in request. Only CAN module hardware or a POR the message, the Data registers must also be loaded. condition can clear it. If the message is to use extended identifiers, the EIDH:EIDL registers must also be loaded and the EXIDE bit set. To initiate message transmission, the TXREQ bit must be set for each buffer to be transmitted. When TXREQ is set, the TXABT, TXLARB and TXERR bits will be cleared. To successfully complete the transmission, there must be at least one node with matching baud rate on the network. DS30009977G-page 432  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.6.3 TRANSMIT PRIORITY transmit buffer with the highest priority will be sent first. If two buffers have the same priority setting, the buffer Transmit priority is a prioritization within the with the highest buffer number will be sent first. There PIC18F66K80 family devices of the pending transmitta- are four levels of transmit priority. If the TXP bits for a ble messages. This is independent from, and not particular message buffer are set to ‘11’, that buffer has related to, any prioritization implicit in the message the highest possible priority. If the TXP bits for a partic- arbitration scheme built into the CAN protocol. Prior to ular message buffer are set to ‘00’, that buffer has the sending the Start-of-Frame (SOF), the priority of all buf- lowest possible priority. fers that are queued for transmission is compared. The FIGURE 27-2: TRANSMIT BUFFERS TXB0 TXB1 TXB2 TXB3-TXB8 E E E E TXREQ TXABT TXLARB TXERR TXB0IF MESSAG TXREQ TXABT TXLARB TXERR TXB1IF MESSAG TXREQ TXABT TXLARB TXERR TXB2IF MESSAG TXREQ TXABT TXLARB TXERR TXB2IF MESSAG Message Queue Control Transmit Byte Sequencer  2010-2017 Microchip Technology Inc. DS30009977G-page 433

PIC18F66K80 FAMILY 27.7 Message Reception Normally, these bits are set to ‘00’ to enable reception of all valid messages as determined by the appropriate 27.7.1 RECEIVING A MESSAGE acceptance filters. In this case, the determination of whether or not to receive standard or extended Of all receive buffers, the MAB is always committed to messages is determined by the EXIDE bit in the accep- receiving the next message from the bus. The MCU tance filter register. In Mode 0, if the RXM bits are set can access one buffer while the other buffer is available to ‘01’ or ‘10’, the receiver will accept only messages for message reception or holding a previously received with standard or extended identifiers, respectively. If an message. acceptance filter has the EXIDE bit set, such that it Note: The entire contents of the MAB are moved does not correspond with the RXM mode, that accep- into the receive buffer once a message is tance filter is rendered useless. In Mode 1 and 2, accepted. This means that regardless of setting EXID in the SIDL Mask register will ensure that the type of identifier (standard or only standard or extended identifiers are received. extended) and the number of data bytes These two modes of RXM bits can be used in systems received, the entire receive buffer is over- where it is known that only standard or extended mes- written with the MAB contents. Therefore, sages will be on the bus. If the RXM bits are set to ‘11’ the contents of all registers in the buffer (RXM1 = 1 in Mode 1 and 2), the buffer will receive all must be assumed to have been modified messages regardless of the values of the acceptance when any message is received. filters. Also, if a message has an error before the end of frame, that portion of the message assembled in the When a message is moved into either of the receive MAB before the error frame will be loaded into the buf- buffers, the associated RXFUL bit is set. This bit must fer. This mode may serve as a valuable debugging tool be cleared by the MCU when it has completed process- for a given CAN network. It should not be used in an ing the message in the buffer in order to allow a new actual system environment as the actual system will message to be received into the buffer. This bit always have some bus errors and all nodes on the bus provides a positive lockout to ensure that the firmware are expected to ignore them. has finished with the message before the module attempts to load a new message into the receive buffer. In Mode 1 and 2, when a programmable buffer is If the receive interrupt is enabled, an interrupt will be configured as a transmit buffer and one or more accep- generated to indicate that a valid message has been tance filters are associated with it, all incoming messages received. matching this acceptance filter criteria will be discarded. To avoid this scenario, user firmware must make sure Once a message is loaded into any matching buffer, that there are no acceptance filters associated with a user firmware may determine exactly what filter caused buffer configured as a transmit buffer. this reception by checking the filter hit bits in the RXBnCON or BnCON registers. In Mode 0, 27.7.2 RECEIVE PRIORITY FILHIT<2:0> of RXBnCON serve as filter hit bits. In When in Mode 0, RXB0 is the higher priority buffer and Mode 1 and 2, FILHIT<4:0> bits of BnCON serve as has two message acceptance filters associated with it. filter hit bits. The same registers also indicate whether RXB1 is the lower priority buffer and has four acceptance the current message is an RTR frame or not. A filters associated with it. The lower number of acceptance received message is considered a standard identifier filters makes the match on RXB0 more restrictive and message if the EXID/EXIDE bit in the RXBnSIDL or the implies a higher priority for that buffer. Additionally, the BnSIDL register is cleared. Conversely, a set EXID bit RXB0CON register can be configured such that if RXB0 indicates an extended identifier message. If the contains a valid message and another valid message is received message is a standard identifier message, received, an overflow error will not occur and the new user firmware needs to read the SIDL and SIDH regis- message will be moved into RXB1 regardless of the ters. In the case of an extended identifier message, acceptance criteria of RXB1. There are also two firmware should read the SIDL, SIDH, EIDL and EIDH programmable acceptance filter masks available, one for registers. If the RXBnDLC or BnDLC register contain each receive buffer (see Section27.5 “CAN Message non-zero data count, user firmware should also read Buffers”). the corresponding number of data bytes by accessing the RXBnDm or the BnDm registers. When a received In Mode 1 and 2, there are a total of 16 acceptance message is an RTR, and if the current buffer is not con- filters available and each can be dynamically assigned figured for automatic RTR handling, user firmware to any of the receive buffers. A buffer with a lower must take appropriate action and respond manually. number has higher priority. Given this, if an incoming message matches with two or more receive buffer Each receive buffer contains RXM bits to set special acceptance criteria, the buffer with the lower number Receive modes. In Mode 0, RXM<1:0> bits in will be loaded with that message. RXBnCON define a total of four Receive modes. In Mode 1 and 2, RXM1 bit, in combination with the EXID mask and filter bit, define the same four receive modes. DS30009977G-page 434  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.7.3 ENHANCED FIFO MODE 27.7.4 TIME-STAMPING When configured for Mode 2, two of the dedicated The CAN module can be programmed to generate a receive buffers in combination with one or more pro- time-stamp for every message that is received. When grammable transmit/receive buffers, are used to create enabled, the module generates a capture signal for a maximum of an 8 buffers deep FIFO buffer. In this CCP1, which in turn captures the value of either Timer1 mode, there is no direct correlation between filters and or Timer3. This value can be used as the message receive buffer registers. Any filter that has been time-stamp. enabled can generate an acceptance. When a To use the time-stamp capability, the CANCAP bit message has been accepted, it is stored in the next (CIOCON<4>) must be set. This replaces the capture available receive buffer register and an internal Write input for CCP1 with the signal generated from the CAN Pointer is incremented. The FIFO can be a maximum module. In addition, CCP1CON<3:0> must be set to of 8 buffers deep. The entire FIFO must consist of con- ‘0011’ to enable the CCP Special Event Trigger for tiguous receive buffers. The FIFO head begins at CAN events. RXB0 buffer and its tail spans toward B5. The maxi- mum length of the FIFO is limited by the presence or 27.8 Message Acceptance Filters absence of the first transmit buffer starting from B0. If a and Masks buffer is configured as a transmit buffer, the FIFO length is reduced accordingly. For instance, if B3 is The message acceptance filters and masks are used to configured as a transmit buffer, the actual FIFO will determine if a message in the Message Assembly Buf- consist of RXB0, RXB1, B0, B1 and B2, a total of 5 buf- fer should be loaded into any of the receive buffers. fers. If B0 is configured as a transmit buffer, the FIFO Once a valid message has been received into the MAB, length will be 2. If none of the programmable buffers the identifier fields of the message are compared to the are configured as a transmit buffer, the FIFO will be filter values. If there is a match, that message will be 8buffers deep. A system that requires more transmit loaded into the appropriate receive buffer. The filter buffers should try to locate transmit buffers at the very masks are used to determine which bits in the identifier end of B0-B5 buffers to maximize available FIFO are examined with the filters. A truth table is shown length. below in Table27-1 that indicates how each bit in the When a message is received in FIFO mode, the inter- identifier is compared to the masks and filters to rupt flag code bits (EICODE<4:0>) in the CANSTAT determine if a message should be loaded into a receive register will have a value of ‘10000’, indicating the buffer. The mask essentially determines which bits to FIFO has received a message. FIFO Pointer bits, apply the acceptance filters to. If any mask bit is set to FP<3:0> in the CANCON register, point to the buffer a zero, then that bit will automatically be accepted that contains data not yet read. The FIFO Pointer bits, regardless of the filter bit. in this sense, serve as the FIFO Read Pointer. The user should use the FP bits and read corresponding buffer TABLE 27-1: FILTER/MASK TRUTH TABLE data. When receive data is no longer needed, the Message Accept or RXFUL bit in the current buffer must be cleared, Mask Filter Identifier Reject causing FP<3:0> to be updated by the module. bit n bit n bit n001 bit n To determine whether FIFO is empty or not, the user may use the FP<3:0> bits to access the RXFUL bit in 0 x x Accept the current buffer. If RXFUL is cleared, the FIFO is con- 1 0 0 Accept sidered to be empty. If it is set, the FIFO may contain 1 0 1 Reject one or more messages. In Mode 2, the module also 1 1 0 Reject provides a bit called FIFO High Water Mark (FIFOWM) in the ECANCON register. This bit can be used to 1 1 1 Accept cause an interrupt whenever the FIFO contains only Legend: x = don’t care one or four empty buffers. The FIFO high water mark In Mode 0, acceptance filters, RXF0 and RXF1, and interrupt can serve as an early warning to a full FIFO filter mask, RXM0, are associated with RXB0. Filters, condition. RXF2, RXF3, RXF4 and RXF5, and mask, RXM1, are associated with RXB1.  2010-2017 Microchip Technology Inc. DS30009977G-page 435

PIC18F66K80 FAMILY In Mode 1 and 2, there are an additional 10 acceptance The coding of the RXB0DBEN bit enables these three filters, RXF6-RXF15, creating a total of 16 available bits to be used similarly to the FILHIT bits and to distin- filters. RXF15 can be used either as an acceptance guish a hit on filter, RXF0 and RXF1, in either RXB0 or filter or acceptance mask register. Each of these after a rollover into RXB1. acceptance filters can be individually enabled or • 111 = Acceptance Filter 1 (RXF1) disabled by setting or clearing the RXFENn bit in the • 110 = Acceptance Filter 0 (RXF0) RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive • 001 = Acceptance Filter 1 (RXF1) buffers. Actual association is made by setting the • 000 = Acceptance Filter 0 (RXF0) appropriate bits in the RXFBCONn register. Each If the RXB0DBEN bit is clear, there are six codes RXFBCONn register contains a nibble for each filter. corresponding to the six filters. If the RXB0DBEN bit is This nibble can be used to associate a specific filter to set, there are six codes corresponding to the six filters, any of available receive buffers. User firmware may plus two additional codes corresponding to RXF0 and associate more than one filter to any one specific RXF1 filters, that rollover into RXB1. receive buffer. In Mode 1 and 2, each buffer control register contains In addition to dynamic filter to buffer association, in 5 bits of filter hit bits (FILHIT<4:0>). A binary value of ‘0’ Mode 1 and 2, each filter can also be dynamically asso- indicates a hit from RXF0 and 15 indicates RXF15. ciated to available Acceptance Mask registers. The If more than one acceptance filter matches, the FILHIT FILn_m bits in the MSELn register can be used to link bits will encode the binary value of the lowest num- a specific acceptance filter to an acceptance mask reg- bered filter that matched. In other words, if filter RXF2 ister. As with filter to buffer association, one can also and filter RXF4 match, FILHIT will be loaded with the associate more than one mask to a specific acceptance value for RXF2. This essentially prioritizes the filter. acceptance filters with a lower number filter having When a filter matches and a message is loaded into the higher priority. Messages are compared to filters in receive buffer, the filter number that enabled the ascending order of filter number. message reception is loaded into the FILHIT bit(s). In The mask and filter registers can only be modified Mode0 for RXB1, the RXB1CON register contains the when the PIC18F66K80 family devices are in FILHIT<2:0> bits. They are coded as follows: Configuration mode. • 101 = Acceptance Filter 5 (RXF5) • 100 = Acceptance Filter 4 (RXF4) • 011 = Acceptance Filter 3 (RXF3) • 010 = Acceptance Filter 2 (RXF2) • 001 = Acceptance Filter 1 (RXF1) • 000 = Acceptance Filter 0 (RXF0) Note: ‘000’ and ‘001’ can only occur if the RXB0DBEN bit is set in the RXB0CON register, allowing RXB0 messages to rollover into RXB1. FIGURE 27-3: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register Acceptance Mask Register RXFn0 RXMn0 RXFn RXMn1 RxRqst 1 RXFn RXMn n n Message Assembly Buffer Identifier DS30009977G-page 436  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.9 Baud Rate Setting The Nominal Bit Time can be thought of as being divided into separate, non-overlapping time segments. All nodes on a given CAN bus must have the same These segments (Figure27-4) include: nominal bit rate. The CAN protocol uses • Synchronization Segment (Sync_Seg) Non-Return-to-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the • Propagation Time Segment (Prop_Seg) receive clock must be recovered by the receiving • Phase Buffer Segment 1 (Phase_Seg1) nodes and synchronized to the transmitter’s clock. • Phase Buffer Segment 2 (Phase_Seg2) As oscillators and transmission time may vary from The time segments (and thus, the Nominal Bit Time) node to node, the receiver must have some type of are, in turn, made up of integer units of time called Time Phase Lock Loop (PLL) synchronized to data transmis- Quanta or TQ (see Figure27-4). By definition, the sion edges to synchronize and maintain the receiver Nominal Bit Time is programmable from a minimum of clock. Since the data is NRZ coded, it is necessary to 8 TQ to a maximum of 25 TQ. Also by definition, the include bit stuffing to ensure that an edge occurs at minimum Nominal Bit Time is 1 s, corresponding to a least every six bit times to maintain the Digital Phase maximum 1 Mb/s rate. The actual duration is given by Lock Loop (DPLL) synchronization. the following relationship: The bit timing of the PIC18F66K80 family is imple- mented using a DPLL that is configured to synchronize EQUATION 27-2: NOMINAL BIT TIME to the incoming data and provides the nominal timing DURATION for the transmitted data. The DPLL breaks each bit time Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + into multiple segments made up of minimal periods of Phase_Seg1 + Phase_Seg2) time called the Time Quanta (TQ). Bus timing functions executed within the bit time frame, The Time Quantum is a fixed unit derived from the such as synchronization to the local oscillator, network oscillator period. It is also defined by the programmable transmission delay compensation and sample point baud rate prescaler, with integer values from 1 to 64, in positioning, are defined by the programmable bit timing addition to a fixed divide-by-two for clock generation. logic of the DPLL. Mathematically, this is: All devices on the CAN bus must use the same bit rate. However, all devices are not required to have the same EQUATION 27-3: TIME QUANTUM master oscillator clock frequency. For the different clock TQ (s) = (2 * (BRP + 1))/FOSC (MHz) frequencies of the individual devices, the bit rate has to or be adjusted by appropriately setting the baud rate TQ (s) = (2 * (BRP + 1)) * TOSC (s) prescaler and number of time quanta in each segment. The “Nominal Bit Rate” is the number of bits transmitted where FOSC is the clock frequency, TOSC is the corresponding oscillator period and BRP is an integer per second, assuming an ideal transmitter with an ideal (0 through 63) represented by the binary values of oscillator, in the absence of resynchronization. The BRGCON1<5:0>. The equation above refers to the nominal bit rate is defined to be a maximum of 1 Mb/s. effective clock frequency used by the microcontroller. If, The “Nominal Bit Time” is defined as: for example, a 10MHz crystal in HS mode is used, then FOSC=10MHz and TOSC=100ns. If the same 10MHz EQUATION 27-1: NOMINAL BIT TIME crystal is used in HS-PLL mode, then the effective TBIT = 1/Nominal Bit Rate frequency is FOSC=40MHz and TOSC=25ns. FIGURE 27-4: BIT TIME PARTITIONING Input Signal Bit SSyynncc Propagation Phase Phase Segment Segment Segment 1 Segment 2 Time Intervals TQ Sample Point Nominal Bit Time  2010-2017 Microchip Technology Inc. DS30009977G-page 437

PIC18F66K80 FAMILY 27.9.1 EXTERNAL CLOCK, INTERNAL The CAN protocol uses a bit-stuffing technique that CLOCK AND MEASURABLE JITTER inserts a bit of a given polarity following five bits with the IN HS-PLL BASED OSCILLATORS opposite polarity. This gives a total of 10 bits transmit- ted without resynchronization (compensation for jitter The microcontroller clock frequency generated from a or phase error). PLL circuit is subject to a jitter, also defined as Phase Jitter or Phase Skew. For its PIC18 Enhanced micro- Given the random nature of the added jitter error, it can controllers, Microchip specifies phase jitter (P ) as be shown that the total error caused by the jitter tends jitter being 2% (Gaussian distribution, within 3 standard to cancel itself over time. For a period of 10 bits, it is deviations, see Parameter F13 in Table31-7) and Total necessary to add only two jitter intervals to correct for Jitter (T ) as being 2*P . jitter induced error: one interval in the beginning of the jitter jitter 10-bit period and another at the end. The overall effect is shown in Figure27-5. FIGURE 27-5: EFFECTS OF PHASE JITTER ON THE MICROCONTROLLER CLOCK AND CAN BIT TIME Nominal Clock Clock with Jitter Phase Skew (Jitter) CAN Bit Time with Jitter CAN Bit Jitter Once these considerations are taken into account, it is For example, assume a CAN bit rate of 125Kb/s, which possible to show that the relation between the jitter and gives an NBT of 8µs. For a 16MHz clock generated the total frequency error can be defined as: from a 4x PLL, the jitter at this clock frequency is: EQUATION 27-4: JITTER AND TOTAL EQUATION 27-5: 16 MHz CLOCK FROM 4x FREQUENCY ERROR PLL JITTER: 1 0.02 f = ------T----j-i--t-t-e--r-------= --2---------P----j-i-t--t-e--r-- 2%1----6--- -M-----H-----z- = ----------------6- = 1.25ns 10NBT 10NBT 1610 and resultant frequency error is: where jitter is expressed in terms of time and NBT is the Nominal Bit Time. EQUATION 27-6: RESULTANT FREQUENCY ERROR: –9 2------------1---.--2---5------1---0----------= 3.12510–5= 0.0031% –6 10810  DS30009977G-page 438  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY Table27-2 shows the relation between the clock This is clearly smaller than the expected drift of a generated by the PLL and the frequency error from crystal oscillator, typically specified at 100ppm or jitter (measured jitter-induced error of 2%, Gaussian 0.01%. If we add jitter to oscillator drift, we have a total distribution, within 3 standard deviations), as a frequency drift of 0.0132%. The total oscillator percentage of the nominal clock frequency. frequency errors for common clock frequencies and bit rates, including both drift and jitter, are shown in Table27-3. TABLE 27-2: FREQUENCY ERROR FROM JITTER AT VARIOUS PLL GENERATED CLOCK SPEEDS Frequency Error at Various Nominal Bit Times (Bit Rates) PLL P T Output jitter jitter 8s 4s 2s 1s (125Kb/s) (250Kb/s) (500Kb/s) (1Mb/s) 40MHz 0.5ns 1ns 0.00125% 0.00250% 0.005% 0.01% 24MHz 0.83ns 1.67ns 0.00209% 0.00418% 0.008% 0.017% 16MHz 1.25ns 2.5ns 0.00313% 0.00625% 0.013% 0.025% TABLE 27-3: TOTAL FREQUENCY ERROR AT VARIOUS PLL GENERATED CLOCK SPEEDS (100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER) Frequency Error at Various Nominal Bit Times (Bit Rates) Nominal PLL Output 8s 4s 2s 1s (125Kb/s) (250Kb/s) (500Kb/s) (1Mb/s) 40MHz 0.01125% 0.01250% 0.015% 0.02% 24MHz 0.01209% 0.01418% 0.018% 0.027% 16MHz 0.01313% 0.01625% 0.023% 0.035%  2010-2017 Microchip Technology Inc. DS30009977G-page 439

PIC18F66K80 FAMILY 27.9.2 TIME QUANTA 27.9.3 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit This part of the bit time is used to synchronize the derived from the oscillator period and baud rate various CAN nodes on the bus. The edge of the input prescaler. Its relationship to TBIT and the Nominal Bit signal is expected to occur during the sync segment. Rate is shown in Example27-6. The duration is 1 TQ. EXAMPLE 27-6: CALCULATING TQ, 27.9.4 PROPAGATION SEGMENT NOMINAL BIT RATE AND This part of the bit time is used to compensate for phys- NOMINAL BIT TIME ical delay times within the network. These delay times consist of the signal propagation time on the bus line TQ (s) = (2 * (BRP + 1))/FOSC (MHz) and the internal delay time of the nodes. The length of TBIT (s) = TQ (s) * number of TQ per bit interval the propagation segment can be programmed from Nominal Bit Rate (bits/s) = 1/TBIT 1TQ to 8 TQ by setting the PRSEG<2:0> bits. This frequency (FOSC) refers to the effective 27.9.5 PHASE BUFFER SEGMENTS frequency used. If, for example, a 10MHz external signal is used along with a PLL, then the effective The phase buffer segments are used to optimally frequency will be 4 x 10MHz which equals 40MHz. locate the sampling point of the received bit within the Nominal Bit Time. The sampling point occurs between Phase Segment 1 and Phase Segment 2. These CASE 1: segments can be lengthened or shortened by the For FOSC = 16 MHz, BRP<5:0> = 00h and resynchronization process. The end of Phase Nominal Bit Time = 8 TQ: Segment1 determines the sampling point within a bit time. Phase Segment 1 is programmable from 1 TQ to TQ = (2 * 1)/16 = 0.125s (125ns) 8 TQ in duration. Phase Segment 2 provides a delay TBIT = 8 * 0.125 = 1s (10-6s) before the next transmitted data transition and is also Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s) programmable from 1 TQ to 8 TQ in duration. However, due to IPT requirements, the actual minimum length of Phase Segment 2 is 2 TQ, or it may be defined to be CASE 2: equal to the greater of Phase Segment 1 or the Information Processing Time (IPT). The sampling point For FOSC = 20 MHz, BRP<5:0> = 01h and should be as late as possible or approximately 80% of Nominal Bit Time = 8 TQ: the bit time. TQ = (2 * 2)/20 = 0.2s (200ns) TBIT = 8 * 0.2 = 1.6s (1.6 * 10-6s) 27.9.6 SAMPLE POINT Nominal Bit Rate = 1/1.6 * 10-6s = 625,000bits/s The sample point is the point of time at which the bus (625Kb/s) level is read and the value of the received bit is deter- mined. The sampling point occurs at the end of Phase Segment1. If the bit timing is slow and contains many CASE 3: TQ, it is possible to specify multiple sampling of the bus line at the sample point. The value of the received bit is For FOSC = 25 MHz, BRP<5:0> = 3Fh and determined to be the value of the majority decision of Nominal Bit Time = 25 TQ: three values. The three samples are taken at the TQ = (2 * 64)/25 = 5.12s sample point and twice before, with a time of TQ/2 TBIT = 25 * 5.12 = 128s (1.28 * 10-4s) between each sample. Nominal Bit Rate = 1/1.28 * 10-4 = 7813 bits/s 27.9.7 INFORMATION PROCESSING TIME (7.8Kb/s) The Information Processing Time (IPT) is the time segment starting at the sample point that is reserved The frequencies of the oscillators in the different nodes for calculation of the subsequent bit level. The CAN must be coordinated in order to provide a system wide specification defines this time to be less than or equal specified Nominal Bit Time. This means that all oscilla- to 2TQ. The PIC18F66K80 family devices define this tors must have a TOSC that is an integral divisor of TQ. time to be 2TQ. Thus, Phase Segment 2 must be at It should also be noted that although the number of TQ least 2 TQ long. is programmable from 4 to 25, the usable minimum is 8TQ. There is no assurance that a bit time of less than 8 TQ in length will operate correctly. DS30009977G-page 440  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.10 Synchronization The phase error of an edge is given by the position of the edge relative to Sync_Seg, measured in TQ. The To compensate for phase shifts between the oscillator phase error is defined in magnitude of TQ as follows: frequencies of each of the nodes on the bus, each CAN • e = 0 if the edge lies within Sync_Seg. controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in • e > 0 if the edge lies before the sample point. the transmitted data is detected, the logic will compare • e < 0 if the edge lies after the sample point of the the location of the edge to the expected time (Syn- previous bit. c_Seg). The circuit will then adjust the values of Phase If the magnitude of the phase error is less than, or equal Segment 1 and Phase Segment 2 as necessary. There to, the programmed value of the Synchronization Jump are two mechanisms used for synchronization. Width, the effect of a resynchronization is the same as that of a hard synchronization. 27.10.1 HARD SYNCHRONIZATION If the magnitude of the phase error is larger than the Hard synchronization is only done when there is a Synchronization Jump Width and if the phase error is recessive to dominant edge during a bus Idle condition, positive, then Phase Segment 1 is lengthened by an indicating the start of a message. After hard synchroni- amount equal to the Synchronization Jump Width. zation, the bit time counters are restarted with Syn- c_Seg. Hard synchronization forces the edge, which If the magnitude of the phase error is larger than the has occurred to lie within the synchronization segment resynchronization jump width and if the phase error is of the restarted bit time. Due to the rules of synchroni- negative, then Phase Segment 2 is shortened by an zation, if a hard synchronization occurs, there will not amount equal to the Synchronization Jump Width. be a resynchronization within that bit time. 27.10.3 SYNCHRONIZATION RULES 27.10.2 RESYNCHRONIZATION • Only one synchronization within one bit time is As a result of resynchronization, Phase Segment 1 allowed. may be lengthened or Phase Segment 2 may be short- • An edge will be used for synchronization only if ened. The amount of lengthening or shortening of the the value detected at the previous sample point phase buffer segments has an upper bound given by (previously read bus value) differs from the bus the Synchronization Jump Width (SJW). The value of value immediately after the edge. the SJW will be added to Phase Segment 1 (see • All other recessive to dominant edges fulfilling Figure27-6) or subtracted from Phase Segment 2 (see rules 1 and 2 will be used for resynchronization, Figure27-7). The SJW is programmable between 1 TQ with the exception that a node transmitting a and 4 TQ. dominant bit will not perform a resynchronization Clocking information will only be derived from reces- as a result of a recessive to dominant edge with a sive to dominant transitions. The property, that only a positive phase error. fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. FIGURE 27-6: LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1) Input Signal Bit Prop Phase Phase Time Sync Segment Segment 1  SJW Segment 2 Segments TQ Sample Point Nominal Bit Length Actual Bit Length  2010-2017 Microchip Technology Inc. DS30009977G-page 441

PIC18F66K80 FAMILY FIGURE 27-7: SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Phase Phase Sync Segment Segment 1 Segment 2  SJW TQ Sample Point Actual Bit Length Nominal Bit Length 27.11 Programming Time Segments By the rules above, the Sync Jump Width could be the maximum of 4 TQ. However, normally a large SJW is Some requirements for programming of the time only necessary when the clock generation of the segments: different nodes is inaccurate or unstable, such as using • Prop_Seg + Phase_Seg 1  Phase_Seg 2 ceramic resonators. Typically, an SJW of 1 is enough. • Phase_Seg 2  Sync Jump Width. 27.12 Oscillator Tolerance For example, assume that a 125 kHz CAN baud rate is desired, using 20MHz for FOSC. With a TOSC of 50 ns, As a rule of thumb, the bit timing requirements allow a baud rate prescaler value of 04h gives a TQ of 500ns. ceramic resonators to be used in applications with To obtain a Nominal Bit Rate of 125 kHz, the Nominal transmission rates of up to 125 Kbit/sec. For the full bus Bit Time must be 8s or 16 TQ. speed range of the CAN protocol, a quartz oscillator is Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Seg required. Refer to ISO11898-1 for oscillator tolerance and 7 TQ for Phase Segment 1 would place the sample requirements. point at 10 TQ after the transition. This leaves 6 TQ for Phase Segment 2. DS30009977G-page 442  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.13 Bit Timing Configuration 27.14.2 ACKNOWLEDGE ERROR Registers In the Acknowledge field of a message, the transmitter checks if the Acknowledge slot (which was sent out as The Baud Rate Control registers (BRGCON1, BRG- a recessive bit) contains a dominant bit. If not, no other CON2, BRGCON3) control the bit timing for the CAN node has received the frame correctly. An Acknowl- bus interface. These registers can only be modified edge error has occurred, an error frame is generated when the PIC18F66K80 family devices are in and the message will have to be repeated. Configuration mode. 27.14.3 FORM ERROR 27.13.1 BRGCON1 If a node detects a dominant bit in one of the four seg- The BRP bits control the baud rate prescaler. The ments, including End-of-Frame (EOF), interframe SJW<1:0> bits select the synchronization jump width in space, Acknowledge delimiter or CRC delimiter, then a terms of multiples of TQ. form error has occurred and an error frame is 27.13.2 BRGCON2 generated. The message is repeated. The PRSEG bits set the length of the propagation seg- 27.14.4 BIT ERROR ment in terms of TQ. The SEG1PH bits set the length of A bit error occurs if a transmitter sends a dominant bit Phase Segment 1 in TQ. The SAM bit controls how and detects a recessive bit, or if it sends a recessive bit many times the RXCAN pin is sampled. Setting this bit and detects a dominant bit, when monitoring the actual to a ‘1’ causes the bus to be sampled three times: twice bus level and comparing it to the just transmitted bit. In at TQ/2 before the sample point and once at the normal the case where the transmitter sends a recessive bit sample point (which is at the end of Phase Segment 1). and a dominant bit is detected during the arbitration The value of the bus is determined to be the value read field and the Acknowledge slot, no bit error is during at least two of the samples. If the SAM bit is set generated because normal arbitration is occurring. to a ‘0’, then the RXCAN pin is sampled only once at the sample point. The SEG2PHTS bit controls how the 27.14.5 STUFF BIT ERROR length of Phase Segment 2 is determined. If this bit is set to a ‘1’, then the length of Phase Segment 2 is lf, between the Start-of-Frame (SOF) and the CRC determined by the SEG2PH bits of BRGCON3. If the delimiter, six consecutive bits with the same polarity are SEG2PHTS bit is set to a ‘0’, then the length of Phase detected, the bit stuffing rule has been violated. A stuff Segment 2 is the greater of Phase Segment 1 and the bit error occurs and an error frame is generated. The information processing time (which is fixed at 2 TQ for message is repeated. the PIC18F66K80 family). 27.14.6 ERROR STATES 27.13.3 BRGCON3 Detected errors are made public to all other nodes via The PHSEG2<2:0> bits set the length (in TQ) of Phase error frames. The transmission of the erroneous mes- Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the sage is aborted and the frame is repeated as soon as SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0> possible. Furthermore, each CAN node is in one of the bits have no effect. three error states; “error-active”, “error-passive” or “bus-off”, according to the value of the internal error 27.14 Error Detection counters. The error-active state is the usual state where the bus node can transmit messages and acti- The CAN protocol provides sophisticated error vate error frames (made of dominant bits) without any detection mechanisms. The following errors can be restrictions. In the error-passive state, messages and detected. passive error frames (made of recessive bits) may be transmitted. The bus-off state makes it temporarily 27.14.1 CRC ERROR impossible for the node to participate in the bus With the Cyclic Redundancy Check (CRC), the trans- communication. During this state, messages can neither mitter calculates special check bits for the bit be received nor transmitted. sequence, from the start of a frame until the end of the 27.14.7 ERROR MODES AND ERROR data field. This CRC sequence is transmitted in the COUNTERS CRC field. The receiving node also calculates the CRC sequence using the same formula and performs a The PIC18F66K80 family devices contain two error comparison to the received sequence. If a mismatch is counters: the Receive Error Counter (RXERRCNT) and detected, a CRC error has occurred and an error frame the Transmit Error Counter (TXERRCNT). The values of is generated. The message is repeated. both counters can be read by the MCU. These counters are incremented or decremented in accordance with the CAN bus specification.  2010-2017 Microchip Technology Inc. DS30009977G-page 443

PIC18F66K80 FAMILY The PIC18F66K80 family devices are error-active if the MCU if the bus remains Idle for 128 x 11 bit times. both error counters are below the error-passive limit of If this is not desired, the error Interrupt Service Routine 128. They are error-passive if at least one of the error should address this. The current Error mode of the counters equals or exceeds 128. They go to bus-off if CAN module can be read by the MCU via the the transmit error counter equals or exceeds the COMSTAT register. bus-off limit of 256. The devices remain in this state Additionally, there is an Error State Warning flag bit, until the bus-off recovery sequence is finished. The EWARN, which is set if at least one of the error count- bus-off recovery sequence consists of 128 occurrences ers equals or exceeds the error warning limit of 96. of 11consecutive recessive bits (see Figure27-8). EWARN is reset if both error counters are less than the Note that the CAN module, after going bus-off, will error warning limit. recover back to error-active without any intervention by FIGURE 27-8: ERROR MODES STATE DIAGRAM Reset Error- RXERRCNT < 128 or TXERRCNT < 128 Active 128 occurrences of 11 consecutive “recessive” bits RXERRCNT  128 or TXERRCNT  128 Error- Passive TXERRCNT > 255 Bus- Off 27.15 CAN Interrupts The interrupts can be broken up into two categories: receive and transmit interrupts. The module has several sources of interrupts. Each of The receive related interrupts are: these interrupts can be individually enabled or dis- abled. The PIR5 register contains interrupt flags. The • Receive Interrupts PIE5 register contains the enables for the 8 main inter- • Wake-up Interrupt rupts. A special set of read-only bits in the CANSTAT • Receiver Overrun Interrupt register, the ICODE bits, can be used in combination • Receiver Warning Interrupt with a jump table for efficient handling of interrupts. • Receiver Error-Passive Interrupt All interrupts have one source, with the exception of the The transmit related interrupts are: error interrupt and buffer interrupts in Mode 1 and 2. Any of the error interrupt sources can set the error interrupt • Transmit Interrupts flag. The source of the error interrupt can be determined • Transmitter Warning Interrupt by reading the Communication Status register, • Transmitter Error-Passive Interrupt COMSTAT. In Mode 1 and 2, there are two interrupt • Bus-Off Interrupt enable/disable and flag bits – one for all transmit buffers and the other for all receive buffers. DS30009977G-page 444  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 27.15.1 INTERRUPT CODE BITS the source of interrupt. In Mode 2, a receive interrupt indicates that the new message is loaded into FIFO. To simplify the interrupt handling process in user firm- FIFO can be read by using FIFO Pointer bits, FP. ware, the ECAN module encodes a special set of bits. In Mode0, these bits are ICODE<3:1> in the CANSTAT TABLE 27-4: VALUES FOR ICODE<2:0> register. In Mode 1 and 2, these bits are EICODE<4:0> in the CANSTAT register. Interrupts are internally prioritized ICODE Interrupt Boolean Expression such that the higher priority interrupts are assigned lower <2:0> values. Once the highest priority interrupt condition has been cleared, the code for the next highest priority inter- 000 None ERR•WAK•TX0•TX1•TX2•RX0•RX1 rupt that is pending (if any) will be reflected by the ICODE 001 Error ERR bits (see Table27-4). Note that only those interrupt sources that have their associated interrupt enable bit set will be reflected in the ICODE bits. 010 TXB2 ERR•TX0•TX1•TX2 In Mode 2, when a receive message interrupt occurs, 011 TXB1 ERR•TX0•TX1 the EICODE bits will always consist of ‘10000’. User firmware may use FIFO Pointer bits to actually access 100 TXB0 ERR•TX0 the next available buffer. 101 RXB1 ERR•TX0•TX1•TX2•RX0•RX1 27.15.2 TRANSMIT INTERRUPT When the transmit interrupt is enabled, an interrupt will 110 RXB0 ERR•TX0•TX1•TX2•RX0 be generated when the associated transmit buffer becomes empty and is ready to be loaded with a new 111 Wake on ERR•TX0•TX1•TX2•RX0•RX1•WAK message. In Mode 0, there are separate interrupt Interrupt enable/disable and flag bits for each of the three Legend: dedicated transmit buffers. The TXBnIF bit will be set to ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE indicate the source of the interrupt. The interrupt is TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE cleared by the MCU, resetting the TXBnIF bit to a ‘0’. In TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE Mode 1 and 2, all transmit buffers share one interrupt TX2 = TXB2IF * TXB2IE enable/disable bit and one flag bit. In Mode 1 and 2, TXB- nIE in PIE5 and TXBnIF in PIR5 indicate when a transmit buffer has completed transmission of its message. 27.15.4 MESSAGE ERROR INTERRUPT TXBnIF, TXBnIE and TXBnIP in PIR5, PIE5 and IPR5, When an error occurs during transmission or reception respectively, are not used in Mode 1 and 2. Individual of a message, the message error flag, IRXIF, will be set transmit buffer interrupts can be enabled or disabled by and if the IRXIE bit is set, an interrupt will be generated. setting or clearing TXBnIE and B0IE register bits. When This is intended to be used to facilitate baud rate a shared interrupt occurs, user firmware must poll the determination when used in conjunction with Listen TXREQ bit of all transmit buffers to detect the source of Only mode. interrupt. 27.15.5 BUS ACTIVITY WAKE-UP 27.15.3 RECEIVE INTERRUPT INTERRUPT When the receive interrupt is enabled, an interrupt will When the PIC18F66K80 family devices are in Sleep be generated when a message has been successfully mode and the bus activity wake-up interrupt is enabled, received and loaded into the associated receive buffer. an interrupt will be generated and the WAKIF bit will be This interrupt is activated immediately after receiving set when activity is detected on the CAN bus. This the End-of-Frame (EOF) field. interrupt causes the PIC18F66K80 family devices to In Mode 0, the RXBnIF bit is set to indicate the source exit Sleep mode. The interrupt is reset by the MCU, of the interrupt. The interrupt is cleared by the MCU, clearing the WAKIF bit. resetting the RXBnIF bit to a ‘0’. 27.15.6 ERROR INTERRUPT In Mode 1 and 2, all receive buffers share RXBnIE, RXBnIF and RXBnIP in PIE5, PIR5 and IPR5, respec- When the CAN module error interrupt (ERRIE in PIE5) tively. Bits, RXBnIE, RXBnIF and RXBnIP, are not is enabled, an interrupt is generated if an overflow con- used. Individual receive buffer interrupts can be con- dition occurs, or if the error state of the transmitter or trolled by the TXBnIE and BIE0 registers. In Mode 1, receiver has changed. The error flags in COMSTAT will when a shared receive interrupt occurs, user firmware indicate one of the following conditions. must poll the RXFUL bit of each receive buffer to detect  2010-2017 Microchip Technology Inc. DS30009977G-page 445

PIC18F66K80 FAMILY 27.15.6.1 Receiver Overflow 27.15.6.3 Transmitter Warning An overflow condition occurs when the MAB has The transmit error counter has reached the MCU assembled a valid received message (the message warning limit of 96. meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available 27.15.6.4 Receiver Bus Passive for loading of a new message. The associated This will occur when the device has gone to the RXBnOVFL bit in the COMSTAT register will be set to error-passive state because the receive error counter is indicate the overflow condition. This bit must be cleared greater or equal to 128. by the MCU. 27.15.6.5 Transmitter Bus Passive 27.15.6.2 Receiver Warning This will occur when the device has gone to the The receive error counter has reached the MCU error-passive state because the transmit error counter warning limit of 96. is greater or equal to 128. 27.15.6.6 Bus-Off The transmit error counter has exceeded 255 and the device has gone to bus-off state. DS30009977G-page 446  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 28.0 SPECIAL FEATURES OF THE 28.1 Configuration Bits CPU The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various The PIC18F66K80 family of devices includes several device configurations. These bits are mapped starting features intended to maximize reliability and minimize at program memory location, 300000h. cost through elimination of external components. These include: The user will note that address, 300000h, is beyond the user program memory space. In fact, it belongs to the • Oscillator Selection configuration memory space (300000h-3FFFFFh), • Resets: which can only be accessed using table reads and - Power-on Reset (POR) table writes. - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) Software programming the Configuration registers is - Brown-out Reset (BOR) done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a • Interrupts self-timed write to the Configuration register. In normal • Watchdog Timer (WDT) and On-Chip Regulator operation mode, a TBLWT instruction with the TBLPTR • Fail-Safe Clock Monitor pointing to the Configuration register sets up the address • Two-Speed Start-up and the data for the Configuration register write. Setting • Code Protection the WR bit starts a long write to the Configuration • ID Locations register. The Configuration registers are written a byte at • In-Circuit Serial Programming™ a time. To write or erase a configuration cell, a TBLWT The oscillator can be configured for the application instruction can write a ‘1’ or a ‘0’ into the cell. For depending on frequency, power, accuracy and cost. All additional details on Flash programming, refer to of the options are discussed in detail in Section3.0 Section7.5 “Writing to Flash Program Memory”. “Oscillator Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F66K80 family of devices has a Watchdog Timer, which is either perma- nently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator (LF-INTOSC) also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its fail- ure. Two-Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits.  2010-2017 Microchip Technology Inc. DS30009977G-page 447

PIC18F66K80 FAMILY TABLE 28-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300000h CONFIG1L — XINST — SOSCSEL1 SOSCSEL0 INTOSCSEL — RETEN -1-1 11-1 300001h CONFIG1H IESO FCMEN — PLLCFG FOSC3 FOSC2 FOSC1 FOSC0 00-0 1000 300002h CONFIG2L — BORPWR1 BORWPR0 BORV1 BORV0 BOREN1 BOREN0 PWRTEN -111 1111 300003h CONFIG2H — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 -111 1111 300005h CONFIG3H MCLRE — — — MSSPMSK T3CKMX(1,3) T0CKMX(1) CANMX 1--- 1qq1 300006h CONFIG4L DEBUG — — BBSIZ0 — — — STVREN 1--1 ---1 300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx 3FFFFFh DEVID2(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Implemented only on the 64-pin devices (PIC18F6XK80). 2: See Register28-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. 3: Maintain as ‘0’ on 28-pin, 40-pin and 44-pin devices. DS30009977G-page 448  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 28-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 U-0 R/P-1 — XINST — SOSCSEL1 SOSCSEL0 INTOSCSEL — RETEN bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode are enabled 0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode) bit 5 Unimplemented: Read as ‘0’ bit 4-3 SOSCSEL<1:0>: SOSC Power Selection and Mode Configuration bits 11 = High-power SOSC circuit is selected 10 = Digital (SCLKI) mode; I/O port functionality of RC0 and RC1 is enabled 01 = Low-power SOSC circuit is selected 00 = Reserved bit 2 INTOSCSEL: LF-INTOSC Low-power Enable bit 1 = LF-INTOSC in High-Power mode during Sleep 0 = LF-INTOSC in Low-Power mode during Sleep bit 1 Unimplemented: Read as ‘0’ bit 0 RETEN: VREG Sleep Enable bit 1 = Ultra low-power regulator is disabled. Regulator power in Sleep mode is controlled by REGSLP (WDTCON<7>). 0 = Ultra low-power regulator is enabled. Regulator power in Sleep mode is controlled by SRETEN (WDTCON<4>).  2010-2017 Microchip Technology Inc. DS30009977G-page 449

PIC18F66K80 FAMILY REGISTER 28-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-1 R/P-0 R/P-0 R/P-0 IESO FCMEN — PLLCFG(1) FOSC3(2) FOSC2(2) FOSC1(2) FOSC0(2) bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 5 Unimplemented: Read as ‘0’ bit 4 PLLCFG: 4X PLL Enable bit(1) 1 = Oscillator is multiplied by 4 0 = Oscillator is used directly bit 3-0 FOSC<3:0>: Oscillator Selection bits(2) 1101 = EC1, EC oscillator (low power, DC-160kHz) 1100 = EC1IO, EC oscillator with CLKOUT function on RA6 (low power, DC-160kHz) 1011 = EC2, EC oscillator (medium power, 160kHz-16MHz) 1010 = EC2IO, EC oscillator with CLKOUT function on RA6 (medium power, 160 kHz-16 MHz) 0101 = EC3, EC oscillator (high power, 16MHz-64MHz) 0100 = EC3IO, EC oscillator with CLKOUT function on RA6 (high power, 16MHz-64MHz) 0011 = HS1, HS oscillator (medium power, 4MHz-16MHz) 0010 = HS2, HS oscillator (high power, 16MHz-25MHz) 0001 = XT oscillator 0000 = LP oscillator 0111 = RC, external RC oscillator 0110 = RCIO, external RC oscillator with CKLOUT function on RA6 1000 = INTIO2, internal RC oscillator 1001 = INTIO1, internal RC oscillator with CLKOUT function on RA6 Note 1: Not valid for the INTIOx PLL mode. 2: INTIO + PLL can be enabled only by the PLLEN bit (OSCTUNE<6>). Other PLL modes can be enabled by either the PLLEN bit or the PLLCFG (CONFIG1H<4>) bit. DS30009977G-page 450  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 28-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — BORPWR1(1) BORPWR0(1) BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2) bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-5 BORPWR<1:0>: BORMV Power-Level bits(1) 11 = ZPBORVMV instead of BORMV is selected 10 = BORMV is set to a high-power level 01 = BORMV is set to a medium power level 00 = BORMV is set to a low-power level bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = BVDD is set to 1.8V 10 = BVDD is set to 2.0V 01 = BVDD is set to 2.7V 00 = BVDD is set to 3.0V bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset is enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset is disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note 1: For the specifications, see Section31.1 “DC Characteristics: Supply Voltage PIC18F66K80 Family (Industrial/Extended)”. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled.  2010-2017 Microchip Technology Inc. DS30009977G-page 451

PIC18F66K80 FAMILY REGISTER 28-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 WDTPS<4:0>: Watchdog Timer Postscale Select bits 11111 = Reserved 10100 = 1:1,048,576 (4,194.304s) 10011 = 1:524,288 (2,097.152s) 10010 = 1:262,144 (1,048.576s) 10001 = 1:131,072 (524.288s) 10000 = 1:65,536 (262.144s) 01111 = 1:32,768 (131.072s) 01110 = 1:16,384 (65.536s) 01101 = 1:8,192 (32.768s) 01100 = 1:4,096 (16.384s) 01011 = 1:2,048 (8.192s) 01010 = 1:1,024 (4.096s) 01001 = 1:512 (2.048s) 01000 = 1:256 (1.024s) 00111 = 1:128 (512 ms) 00110 = 1:64 (256 ms) 00101 = 1:32 (128 ms) 00100 = 1:16 (64 ms) 00011 = 1:8 (32 ms) 00010 = 1:4 (16 ms) 00001 = 1:2 (8 ms) 00000 = 1:1 (4 ms) bit 1-0 WDTEN<1:0>: Watchdog Timer Enable bits 11 = WDT is enabled in hardware; SWDTEN bit is disabled 10 = WDT is controlled by the SWDTEN bit setting 01 = WDT is enabled only while the device is active and is disabled in Sleep mode; SWDTEN bit is disabled 00 = WDT is disabled in hardware; SWDTEN bit is disabled DS30009977G-page 452  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 28-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 MCLRE — — — MSSPMSK T3CKMX(1) T0CKMX(1) CANMX bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin is enabled; RE3 input pin is disabled 0 = RE3 input pin is enabled; MCLR is disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit 1 = 7-Bit Address Masking mode is enabled 0 = 5-Bit Address Masking mode is enabled bit 2 T3CKMX: Timer3 Clock Input MUX bit(1) 1 = Timer3 gets its clock input from the RG2/T3CKI pin on 64-pin packages 0 = Timer3 gets its clock input from the RB5/T3CKI pin on 64-pin packages bit 1 T0CKMX: Timer0 Clock Input MUX bit(1) 1 = Timer0 gets its clock input from the RB5/T0CKI pin on 64-pin packages 0 = Timer0 gets its clock input from the RG4/T0CKI pin on 64-pin packages bit 0 CANMX: ECAN MUX bit 1 = CANTX and CANRX pins are located on RB2 and RB3, respectively 0 = CANTX and CANRX pins are located on RC6 and RC7, respectively (28-pin and 40/44-pin packages) or on RE4 and RE5, respectively (64-pin package) Note 1: These bits are implemented only on the 64-pin devices (PIC18F6XK80); maintain as ‘0’ on 28-pin, 40-pin and 44-pin devices.  2010-2017 Microchip Technology Inc. DS30009977G-page 453

PIC18F66K80 FAMILY REGISTER 28-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 R/P-0 U-0 U-0 U-0 R/P-1 DEBUG — — BBSIZ0 — — — STVREN bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose I/O pins 0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6-5 Unimplemented: Read as ‘0’ bit 4 BBSIZ0: Boot Block Size Select bit 1 = 2 kW boot block size 0 = 1 kW boot block size bit 3-1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause a Reset 0 = Stack full/underflow will not cause a Reset DS30009977G-page 454  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 28-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3 CP2 CP1 CP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit 1 = Block 3 is not code-protected(1) 0 = Block 3 is code-protected(1) bit 2 CP2: Code Protection bit 1 = Block 2 is not code-protected(1) 0 = Block 2 is code-protected(1) bit 1 CP1: Code Protection bit 1 = Block 1 is not code-protected(1) 0 = Block 1 is code-protected(1) bit 0 CP0: Code Protection bit 1 = Block 0 is not code-protected(1) 0 = Block 0, is code-protected(1) Note 1: For the memory size of the blocks, see Figure28-6.  2010-2017 Microchip Technology Inc. DS30009977G-page 455

PIC18F66K80 FAMILY REGISTER 28-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block is not code-protected(1) 0 = Boot block is code-protected(1) bit 5-0 Unimplemented: Read as ‘0’ Note 1: For the memory size of the blocks, see Figure28-6. The boot block size changes with BBSIZ0. DS30009977G-page 456  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 28-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit 1 = Block 3 is not write-protected(1) 0 = Block 3 is write-protected(1) bit 2 WRT2: Write Protection bit 1 = Block 2 is not write-protected(1) 0 = Block 2 is write-protected(1) bit 1 WRT1: Write Protection bit 1 = Block 1 is not write-protected(1) 0 = Block 1 is write-protected(1) bit 0 WRT0: Write Protection bit 1 = Block 0 is not write-protected(1) 0 = Block 0 is write-protected(1) Note 1: For the memory size of the blocks, see Figure28-6.  2010-2017 Microchip Technology Inc. DS30009977G-page 457

PIC18F66K80 FAMILY REGISTER 28-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block is not write-protected(2) 0 = Boot block is write-protected(2) bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers are not write-protected(2) 0 = Configuration registers are write-protected(2) bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode. 2: For the memory size of the blocks, see Figure28-6. DS30009977G-page 458  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 28-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3 EBTR2 EBTR1 EBTR0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit 1 = Block 3 is not protected from table reads executed in other blocks(1) 0 = Block 3 is protected from table reads executed in other blocks(1) bit 2 EBTR2: Table Read Protection bit 1 = Block 2 is not protected from table reads executed in other blocks(1) 0 = Block 2 is protected from table reads executed in other blocks(1) bit 1 EBTR1: Table Read Protection bit 1 = Block 1 is not protected from table reads executed in other blocks(1) 0 = Block 1 is protected from table reads executed in other blocks(1) bit 0 EBTR0: Table Read Protection bit 1 = Block 0 is not protected from table reads executed in other blocks(1) 0 = Block 0 is protected from table reads executed in other blocks(1) Note 1: For the memory size of the blocks, see Figure28-6.  2010-2017 Microchip Technology Inc. DS30009977G-page 459

PIC18F66K80 FAMILY REGISTER 28-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block is not protected from table reads executed in other blocks(1) 0 = Boot block is protected from table reads executed in other blocks(1) bit 5-0 Unimplemented: Read as ‘0’ Note 1: For the memory size of the blocks, see Figure28-6. DS30009977G-page 460  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY REGISTER 28-13: DEVID1: DEVICE ID REGISTER 1 FOR THE PIC18F66K80 FAMILY R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 DEV<2:0>: Device ID bits These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number: 000 = PIC18F46K80, PIC18LF26K80 001 = PIC18F26K80, PIC18LF65K80 010 = PIC18F65K80, PIC18LF45K80 011 = PIC18F45K80, PIC18LF25K80 100 = PIC18F25K80 110 = PIC18LF66K80 111 = PIC18F66K80, PIC18LF46K80 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. REGISTER 28-14: DEVID2: DEVICE ID REGISTER 2 FOR THE PIC18F66K80 FAMILY R R R R R R R R DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 DEV<10:3>: Device ID bits(1) These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence.  2010-2017 Microchip Technology Inc. DS30009977G-page 461

PIC18F66K80 FAMILY 28.2 Watchdog Timer (WDT) The WDT can be operated in one of four modes as determined by WDTEN<1:0> (CONFIG2H<1:0>. The For the PIC18F66K80 family of devices, the WDT is four modes are: driven by the LF-INTOSC source. When the WDT is • WDT Enabled enabled, the clock source is also enabled. The nominal WDT period is 4ms and has the same stability as the • WDT Disabled LF-INTOSC oscillator. • WDT under Software Control, SWDTEN (WDTCON<0>) The 4ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is • WDT selected by a multiplexer, controlled by bits in - Enabled during normal operation Configuration Register 2H. Available periods range - Disabled during Sleep from 4ms to 4,194seconds (about one hour). The Note1: The CLRWDT and SLEEP instructions WDT and postscaler are cleared when any of the clear the WDT and postscaler counts following events occur: a SLEEP or CLRWDT instruction when executed. is executed, the IRCFx bits (OSCCON<6:4>) are changed or a clock failure has occurred. 2: Changing the setting of the IRCFx bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. FIGURE 28-1: WDT BLOCK DIAGRAM WDT Enabled, SWDTEN Disabled WDT Controlled with SWDTEN bit Setting WDT Enabled only while Device Active, Disabled WDT Disabled in Hardware, SWDTEN Disabled WDTEN1 Enable WDT Wake-up from WDTEN0 WDT Counter Power-Manage Modes INTOSC Source 128 Change on IRCFx bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:1,048,576 All Device Resets 4 WDTPS<3:0> Sleep SWDTEN Enable WDT WDTEN<1:0> INTOSC Source DS30009977G-page 462  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 28.2.1 CONTROL REGISTER Register28-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT Enable Configuration bit, but only if the Configuration bit has disabled the WDT. REGISTER 28-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER R/W-0 U-0 R-x R/W-0 U-0 R/W-x R/W-x R/W-0 REGSLP(3) — ULPLVL SRETEN(2) — ULPEN ULPSINK SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 REGSLP: Regulator Voltage Sleep Enable bit(3) 1 = Regulator goes into Low-Power mode when device’s Sleep mode is enabled 0 = Regulator stays in normal mode when device’s Sleep mode is activated bit 6 Unimplemented: Read as ‘0’ bit 5 ULPLVL: Ultra Low-Power Wake-up Output bit Not valid unless ULPEN = 1. 1 = Voltage on RA0 pin > ~ 0.5V 0 = Voltage on RA0 pin < ~ 0.5V. bit 4 SRETEN: Regulator Voltage Sleep Disable bit(2) 1 = If RETEN (CONFIG1L<0>) = 0 and the regulator is enabled, the device goes into Ultra Low-Power mode in Sleep 0 = The regulator is on when device’s Sleep mode is enabled and the Low-Power mode is controlled by REGSLP bit 3 Unimplemented: Read as ‘0’ bit 2 ULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates comparator output 0 = Ultra Low-Power Wake-up module is disabled bit 1 ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit Not valid unless ULPEN = 1. 1 = Ultra Low-Power Wake-up current sink is enabled 0 = Ultra Low-Power Wake-up current sink is disabled bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bits, WDTEN<1:0>, are enabled. 2: This bit is available only when RETEN = 0. 3: This bit is disabled on PIC18LF devices. TABLE 28-2: SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCON IPEN SBOREN CM RI TO PD POR BOR WDTCON REGSLP — ULPLVL SRETEN — ULPEN ULPSINK SWDTEN Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.  2010-2017 Microchip Technology Inc. DS30009977G-page 463

PIC18F66K80 FAMILY 28.3 On-Chip Voltage Regulator FIGURE 28-2: CONNECTIONS FOR THE F AND LF PARTS All of the PIC18F66K80 family devices power their core digital logic at a nominal 3.3V. For designs that are 5V(1) required to operate at a higher typical voltage, such as PIC18F66K80 5V, all family devices incorporate two on-chip regula- tors that allows the device to run its core logic from VDD VDD. Those regulators are: • Normal on-chip regulator VDDCORE/VCAP • Ultra Low-Power, on-chip regulator CF VSS The hardware configuration of these regulators are the same and are explained in Section28.3.1 “Regulator Enable Mode (PIC18FXXKXX devices)”. The regula- 3.3V(1) tors’ only differences relate to when the device enters PIC18LF66K80 Sleep, as explained in Section28.3.1 “Regulator Enable Mode (PIC18FXXKXX devices)”. VDD 28.3.1 REGULATOR ENABLE MODE (PIC18FXXKXX DEVICES) VDDCORE/VCAP(2) On PIC18FXXKXX devices, the regulator is enabled 0.1 F and a low-ESR filter capacitor must be connected to Capacitor the VDDCORE/VCAP pin (see Figure28-2). This helps VSS maintain the regulator’s stability. The recommended value for the filter capacitor is given in Section31.1 “DC Characteristics: Supply Voltage PIC18F66K80 Note 1: These are typical operating voltages. For the full Family (Industrial/Extended)”. operating ranges of VDD and VDDCORE, see Section31.1 “DC Characteristics: Supply 28.3.2 REGULATOR DISABLE MODE Voltage PIC18F66K80 Family (Indus- (PIC18LFXXKXX DEVICES) trial/Extended)”. On PIC18LFXXKXX devices, the regulator is disabled 2: When the regulator is disabled, VDDCORE/VCAP and the power to the core is supplied directly by VDD. must be connected to a 0.1 F capacitor. The voltage levels for VDD must not exceed the speci- fied VDDCORE levels. A 0.1F capacitor should be connected to the VDDCORE/VCAP pin. On the PIC18FXXKXX devices, the overall voltage budget is very tight. The regulator should operate the device down to 1.8V. When VDD drops below 3.3V, the regulator no longer regulates, but the output voltage follows the input until VDD reaches 1.8V. Below this voltage, the output of the regulator output may drop to0V. DS30009977G-page 464  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 28.3.3 OPERATION OF REGULATOR IN The various modes of regulator operation are shown in SLEEP Table28-3. The difference in the two regulators’ operation arises When the ultra low-power regulator is in Sleep mode, with Sleep mode. The ultra low-power regulator gives the internal reference voltages in the chip will be shut the device the lowest current in the Regulator Enabled off and any interrupts referring to the internal reference mode. will not wake up the device. If the BOR or LVD is enabled, the regulator will keep the internal references The on-chip regulator can go into a lower power mode on and the lowest possible current will not be achieved. when the device goes to Sleep by setting the REGSLP bit (WDTCON<7>). This puts the regulator in a standby When using the ultra low-power regulator in Sleep mode so that the device consumes much less current. mode, the device will take about 250s to start executing code after it wakes up. The on-chip regulator can also go into the Ultra Low-Power mode, which consumes the lowest current possible with the regulator enabled. This mode is controlled by the RETEN bit (CONFIG1L<0>) and SRETEN bit (WDTCON<4>). TABLE 28-3: SLEEP MODE REGULATOR SETTINGS(1) REGSLP SRETEN RETEN Device Power Mode WDTCON<7> WDTCON<4> CONFIG1L<0> PIC18FXXK80 Normal Operation (Sleep) 0 x 1 PIC18FXXK80 Low-Power mode (Sleep) 1 x 1 PIC18FXXK80 Normal Operation (Sleep) 0 0 0 PIC18FXXK80 Low-Power mode (Sleep) 1 0 0 PIC18FXXK80 Ultra Low-Power mode (Sleep) x 1 0 PIC18LFXXK80 Reserved(2) x Don’t Care 0 PIC18LFXXK80 Regulator Bypass mode (Sleep)(2) x x 1 Note 1: x — Indicates that VIT status is invalid. 2: The ultra low-power regulator should be disabled (RETEN = 1, ULP disabled) on PIC18LFXXK80 devices to obtain the lowest possible Sleep current.  2010-2017 Microchip Technology Inc. DS30009977G-page 465

PIC18F66K80 FAMILY 28.4 Two-Speed Start-up In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the The Two-Speed Start-up feature helps to minimize the currently selected clock source until the primary clock latency period from oscillator start-up to code execution source becomes available. The setting of the IESO bit by allowing the microcontroller to use the INTOSC is ignored. (LF-INTOSC, MF-INTOSC, HF-INTOSC) oscillator as a clock source until the primary clock source is available. 28.4.1 SPECIAL CONSIDERATIONS FOR It is enabled by setting the IESO Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTOSC oscillator in Two-Speed primary oscillator mode is LP, XT or HS (Crystal-Based Start-up, the device still obeys the normal command modes). Other sources do not require an OST start-up sequences for entering power-managed modes, delay; for these, Two-Speed Start-up should be including multiple SLEEP instructions (refer to disabled. Section4.1.4 “Multiple Sleep Commands”). In When enabled, Resets and wake-ups from Sleep mode practice, this means that user code can change the cause the device to configure itself to run from the SCS<1:0> bit settings or issue SLEEP instructions internal oscillator block as the clock source, following before the OST times out. This would allow an the time-out of the Power-up Timer after a Power-on application to briefly wake-up, perform routine Reset is enabled. This allows almost immediate code “housekeeping” tasks and return to Sleep before the execution while the primary oscillator starts and the device starts to operate from the primary oscillator. OST is running. Once the OST times out, the device User code can also check if the primary clock source is automatically switches to PRI_RUN mode. currently providing the device clocking by checking the To use a higher clock speed on wake-up, the INTOSC status of the OSTS bit (OSCCON<3>). If the bit is set, or postscaler clock sources can be selected to provide the primary oscillator is providing the clock. Otherwise, a higher clock speed by setting bits, IRCF<2:0>, the internal oscillator block is providing the clock during immediately after Reset. For wake-ups from Sleep, the wake-up from Reset or Sleep mode. INTOSC or postscaler clock sources can be selected by setting the IRCF2:0> bits prior to entering Sleep mode. FIGURE 28-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 PC + 6 Wake from Interrupt Event OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS30009977G-page 466  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 28.5 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits, IRCF<2:0>, microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting the IRCF<2:0> bits prior to entering Sleep function is enabled by setting the FCMEN Configuration mode. bit. The FSCM will detect only failures of the primary or When FSCM is enabled, the LF-INTOSC oscillator runs secondary clock sources. If the internal oscillator block at all times to monitor clocks to peripherals and provide fails, no failure would be detected nor would any action a backup clock in the event of a clock failure. Clock be possible. monitoring (shown in Figure28-4) is accomplished by creating a sample clock signal, which is the output from 28.5.1 FSCM AND THE WATCHDOG TIMER the LF-INTOSC divided by 64. This allows ample time Both the FSCM and the WDT are clocked by the between FSCM sample clocks for a peripheral clock INTOSC oscillator. Since the WDT operates with a edge to occur. The peripheral device clock and the separate divider and counter, disabling the WDT has sample clock are presented as inputs to the Clock no effect on the operation of the INTOSC oscillator Monitor (CM) latch. The CM is set on the falling edge of when the FSCM is enabled. the device clock source, but cleared on the rising edge of the sample clock. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. FIGURE 28-4: FSCM BLOCK DIAGRAM Depending on the frequency selected by the IRCF<2:0> bits, this may mean a substantial change in Clock Monitor the speed of code execution. If the WDT is enabled Latch (CM) (edge-triggered) with a small prescale value, a decrease in clock speed Peripheral allows a WDT time-out to occur and a subsequent S Q Clock device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and INTOSC decreasing the likelihood of an erroneous time-out. ÷ 64 C Q Source 28.5.2 EXITING FAIL-SAFE OPERATION (32 s) 488 Hz (2.048 ms) The Fail-Safe condition is terminated by either a device Reset or by entering a power-managed mode. On Clock Reset, the controller starts the primary clock source Failure specified in Configuration Register 1H (with any Detected required start-up delays that are required for the oscillator mode, such as the OST or PLL timer). The Clock failure is tested for on the falling edge of the INTOSC multiplexer provides the device clock until the sample clock. If a sample clock falling edge occurs primary clock source becomes ready (similar to a while CM is still set, a clock failure has been detected Two-Speed Start-up). The clock source is then (Figure28-5). This causes the following: switched to the primary clock (indicated by the OSTS • The FSCM generates an oscillator fail interrupt by bit in the OSCCON register becoming set). The setting bit, OSCFIF (PIR2<7>) Fail-Safe Clock Monitor then resumes monitoring the • The device clock source switches to the internal peripheral clock. oscillator block (OSCCON is not updated to show The primary clock source may never become ready the current clock source – this is the fail-safe during start-up. In this case, operation is clocked by the condition) INTOSC multiplexer. The OSCCON register will remain • The WDT is reset in its Reset state until a power-managed mode is During switchover, the postscaler frequency from the entered. internal oscillator block may not be sufficiently stable for timing-sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shut- down. See Section4.1.4 “Multiple Sleep Commands” and Section28.4.1 “Special Considerations for Using Two-Speed Start-up” for more details.  2010-2017 Microchip Technology Inc. DS30009977G-page 467

PIC18F66K80 FAMILY FIGURE 28-5: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 28.5.3 FSCM INTERRUPTS IN For oscillator modes involving a crystal or resonator POWER-MANAGED MODES (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up By entering a power-managed mode, the clock time considerably longer than the FCSM sample clock multiplexer selects the clock source selected by the time, a false clock failure may be detected. To prevent OSCCON register. Fail-Safe Clock Monitoring of this, the internal oscillator block is automatically config- the power-managed clock source resumes in the ured as the device clock and functions until the primary power-managed mode. clock is stable (when the OST and PLL timers have If an oscillator failure occurs during power-managed timed out). operation, the subsequent events depend on whether This is identical to Two-Speed Start-up mode. Once the or not the oscillator failure interrupt is enabled. If primary clock is stable, the INTOSC returns to its role enabled (OSCFIF=1), code execution will be clocked as the FSCM source. by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. Note: The same logic that prevents false oscilla- tor failure interrupts on POR, or wake from If the interrupt is disabled, subsequent interrupts while Sleep, also prevents the detection of the in Idle mode will cause the CPU to begin executing oscillator’s failure to start at all following instructions while being clocked by the INTOSC these events. This can be avoided by source. monitoring the OSTS bit and using a 28.5.4 POR OR WAKE FROM SLEEP timing routine to determine if the oscillator is taking too long to start. Even so, no The FSCM is designed to detect oscillator failure at any oscillator failure interrupt will be flagged. point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary As noted in Section28.4.1 “Special Considerations device clock is EC, RC or INTOSC modes, monitoring for Using Two-Speed Start-up”, it is also possible to can begin immediately following these events. select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. DS30009977G-page 468  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 28.6 Program Verification and Each of the blocks has three code protection bits Code Protection associated with them. They are: • Code-Protect bit (CPx) The user program memory is divided into four blocks. • Write-Protect bit (WRTx) One of these is a boot block of 1 or 2Kbytes. The • External Block Table Read bit (EBTRx) remainder of the memory is divided into blocks on binary boundaries. Figure28-6 shows the program memory organization for 48, 64, 96 and 128 Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table28-4. FIGURE 28-6: CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F66K80 FAMILY 000000h Code Memory 01FFFFh Device/Memory Size(1) PIC18FX6K80 PIC18FX5K80 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 Address Boot Block Boot Block Boot Block Boot Block 0000h 2kW 2kW Unimplemented Block 0 Block 0 0800h Read as ‘0’ Block 0 7kW Block 0 3kW 1000h 6kW 2kW 1FFFh Block 1 Block 1 2000h 4kW 4kW 3FFFh Block 1 Block 1 Block 2 Block 2 4000h 8kW 8kW 4kW 4kW 5FFFh Block 3 Block 3 6000h 4kW 4kW 7FFFh 200000h Block 2 Block 2 8000h 8kW 8kW BFFFh Block 3 Block 3 C000h 8kW 8kW FFFFh 10000h Configuration 13FFFh and ID 14000h Space 17FFFh 18000h 1BFFFh 1C000h 1FFFFh 3FFFFFh Note 1: Sizes of memory areas are not to scale. 2: Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).  2010-2017 Microchip Technology Inc. DS30009977G-page 469

PIC18F66K80 FAMILY TABLE 28-4: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. 28.6.1 PROGRAM MEMORY allowed to read and will result in reading ‘0’s. CODE PROTECTION Figure28-7 throughFigure28-9 illustrate table write and table read protection. The program memory may be read to, or written from, any location using the table read and table write Note: Code protection bits may only be written instructions. The Device ID may be read with table to a ‘0’ from a ‘1’ state. It is not possible to reads. The Configuration registers may be read and write a ‘1’ to a bit in the ‘0’ state. Code written with the table read and table write instructions. protection bits are only set to ‘1’ by a full chip erase or block erase function. The full In normal execution mode, the CPx bits have no direct chip erase and block erase functions can effect. CPx bits inhibit external reads and writes. A block only be initiated via ICSP or an external of user memory may be protected from table writes if the programmer. Refer to the device WRTx Configuration bit is ‘0’. programming specification for more The EBTRx bits control table reads. For a block of information. user memory with the EBTRx bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. A table read instruction that exe- cutes from a location outside of that block is not FIGURE 28-7: TABLE WRITE (WRTx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 003FFEh TBLWT* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 00BFFEh TBLWT* WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table writes are disabled to Blockn whenever WRTx = 0. DS30009977G-page 470  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 28-8: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. The TABLAT register returns a value of ‘0’. FIGURE 28-9: EXTERNAL BLOCK TABLE READ (EBTRx) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 003FFEh TBLRD* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads are permitted within Blockn, even when EBTRBx = 0. The TABLAT register returns the value of the data at the location, TBLPTR.  2010-2017 Microchip Technology Inc. DS30009977G-page 471

PIC18F66K80 FAMILY 28.6.2 DATA EEPROM 28.8 In-Circuit Serial Programming CODE PROTECTION The PIC18F66K80 family of devices can be serially The entire data EEPROM is protected from external programmed while in the end application circuit. This is reads and writes by two bits: CPD and WRTD. CPD simply done with two lines for clock and data and three inhibits external reads and writes of data EEPROM. other lines for power, ground and the programming WRTD inhibits internal and external writes to data voltage. This allows customers to manufacture boards EEPROM. The CPU can always read data EEPROM with unprogrammed devices and then program the under normal operation, regardless of the protection bit microcontroller just before shipping the product. This settings. also allows the most recent firmware or a custom firmware to be programmed. 28.6.3 CONFIGURATION REGISTER For the various programming modes, see the PROTECTION programming specification The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration 28.9 In-Circuit Debugger registers. In normal execution mode, the WRTC bit is When the DEBUG Configuration bit is programmed to readable only. WRTC can only be written via ICSP or a ‘0’, the In-Circuit Debugger functionality is enabled. an external programmer. This function allows simple debugging functions when 28.7 ID Locations used with MPLAB® IDE. When the microcontroller has this feature enabled, some resources are not available Eight memory locations (200000h-200007h) are for general use. Table28-5 shows which resources are designated as ID locations, where the user can store required by the background debugger. checksum or other code identification numbers. These locations are both readable and writable during normal TABLE 28-5: DEBUGGER RESOURCES execution through the TBLRD and TBLWT instructions I/O Pins: RB6, RB7 or during program/verify. The ID locations can be read when the device is code-protected. Stack: Two levels Program Memory: 512 bytes Data Memory: 10 bytes To use the In-Circuit Debugger function of the micro- controller, the design must implement In-Circuit Serial Programming connections to MCLR/RE3, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third-party development tool companies. DS30009977G-page 472  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 29.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18F66K80 family of devices incorporates the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) 29.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 MCU instruction set adds many enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations Program Counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table29-2 lists cycles with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table29-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1s. If a conditional test is 3. The accessed memory (specified by ‘a’) true, or the Program Counter is changed as a result of an instruction, the instruction execution time is 2 s. The file register designator, ‘f’, specifies which file reg- Two-word branch instructions (if true) would take 3 s. ister is to be used by the instruction. The destination designator, ‘d’, specifies where the result of the Figure29-1 shows the general formats that the instruc- operation is to be placed. If ‘d’ is zero, the result is tions can have. All examples use the convention ‘nnh’ placed in the WREG register. If ‘d’ is one, the result is to represent a hexadecimal number. placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table29-2, All bit-oriented instructions have three operands: lists the standard instructions recognized by the Microchip MPASMTM Assembler. 1. The file register (specified by ‘f’) Section29.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator, ‘b’, selects the number of the bit affected by the operation, while the file register desig- nator, ‘f’, represents the number of the file in which the bit is located.  2010-2017 Microchip Technology Inc. DS30009977G-page 473

PIC18F66K80 FAMILY TABLE 29-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). f 12-bit register file address (000h to FFFh). This is the source address. s f 12-bit register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for Indirect Addressing of register files (source). s z 7-bit offset value for Indirect Addressing of register files (destination). d { } Optional argument. [text] Indicates an Indexed Address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr.  Assigned to. < > Register bit field.  In the set of. italics User-defined term (font is Courier New). DS30009977G-page 474  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC  2010-2017 Microchip Technology Inc. DS30009977G-page 475

PIC18F66K80 FAMILY TABLE 29-2: PIC18F66K80 FAMILY INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS30009977G-page 476  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 29-2: PIC18F66K80 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.  2010-2017 Microchip Technology Inc. DS30009977G-page 477

PIC18F66K80 FAMILY TABLE 29-2: PIC18F66K80 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS30009977G-page 478  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 29.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) + k  W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank. literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ADDLW 15h mode whenever f 95 (5Fh). See Before Instruction Section29.2.3 “Byte-Oriented and W = 10h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 25h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).  2010-2017 Microchip Technology Inc. DS30009977G-page 479

PIC18F66K80 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write to GPR bank. ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: ANDLW 05Fh in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Before Instruction W = A3h Section29.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = 03h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS30009977G-page 480  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if Carry bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number, ‘2n’, is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank. two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1(2) in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q Cycle Activity: Section29.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to Words: 1 ‘n’ Data PC No No No No Cycles: 1 operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2)  2010-2017 Microchip Technology Inc. DS30009977G-page 481

PIC18F66K80 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if Negative bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number, ‘2n’, is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank. incremented to fetch the next instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section29.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to Q Cycle Activity: ‘n’ Data PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No ‘n’ Data operation Before Instruction FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS30009977G-page 482  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number, ‘2n’, is The 2’s complement number, ‘2n’, is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2)  2010-2017 Microchip Technology Inc. DS30009977G-page 483

PIC18F66K80 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number, ‘2n’, is The 2’s complement number, ‘2n’, is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS30009977G-page 484  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number, ‘2n’, Encoding: 1000 bbba ffff ffff to the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section29.2.3 “Byte-Oriented and Decode Read literal Process Write to Bit-Oriented Instructions in Indexed ‘n’ Data PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah  2010-2017 Microchip Technology Inc. DS30009977G-page 485

PIC18F66K80 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction is enabled, this instruction operates in set is enabled, this instruction operates in Indexed Literal Offset Addressing mode Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS30009977G-page 486  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if Overflow bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number, ‘2n’, is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank. instruction, the new address will be PC + 2 + 2n. This instruction is then a If ‘a’ is ‘0’ and the extended instruction two-cycle instruction. set is enabled, this instruction operates in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Cycles: 1(2) Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Q1 Q2 Q3 Q4 Words: 1 Decode Read literal Process Write to PC Cycles: 1 ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: Before Instruction PORTC = 0110 0101 [65h] PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2)  2010-2017 Microchip Technology Inc. DS30009977G-page 487

PIC18F66K80 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>; Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the Zero bit is ‘1’, then the program (STATUS)  STATUSS, will branch. (BSR)  BSRS The 2’s complement number, ‘2n’, is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk 7 0 instruction, the new address will be 2nd word(k<19:8>) 1111 k kkk kkkk kkkk 19 8 PC + 2 + 2n. This instruction is then a Description: Subroutine call of entire 2-Mbyte two-cycle instruction. memory range. First, return address Words: 1 (PC+ 4) is pushed onto the return stack. Cycles: 1(2) If ‘s’ = 1, the W, STATUS and BSR registers are also pushed into their Q Cycle Activity: respective shadow registers, WS, If Jump: STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs (default). Then, the Decode Read literal Process Write to 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data PC CALL is a two-cycle instruction. No No No No Words: 2 operation operation operation operation Cycles: 2 If No Jump: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ’k’<19:8>, Write to PC Example: HERE BZ Jump No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction Example: HERE CALL THERE,1 If Zero = 1; PC = address (Jump) Before Instruction If Zero = 0; PC = address (HERE) PC = address (HERE + 2) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS30009977G-page 488  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f, 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the Watchdog Timer. It also resets the If ‘a’ is ‘0’, the Access Bank is selected. postscaler of the WDT. Status bits, TO If ‘a’ is ‘1’, the BSR is used to select the and PD, are set. GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Cycles: 1 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Q Cycle Activity: WDT Counter = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write WDT Counter = 00h register ‘f’ Data register ‘f’ WDT Postscaler = 0 TO = 1 PD = 1 Example: CLRF FLAG_REG,1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h  2010-2017 Microchip Technology Inc. DS30009977G-page 489

PIC18F66K80 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: f  dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank. instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank. mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Words: 1 Section29.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h W = ECh Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL) DS30009977G-page 490  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) –W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of the W by Description: Compares the contents of data memory performing an unsigned subtraction. location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched If the contents of ‘f’ are less than the instruction is discarded and a NOP is contents of W, then the fetched executed instead, making this a instruction is discarded and a NOP is two-cycle instruction. executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed Section29.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process No Cycles: 1(2) register ‘f’ Data operation Note: 3 cycles if skip and followed If skip: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process No If skip and followed by 2-word instruction: register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; PC = Address (LESS) Before Instruction If REG  W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG  W; PC = Address (GREATER) If REG  W; PC = Address (NGREATER)  2010-2017 Microchip Technology Inc. DS30009977G-page 491

PIC18F66K80 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> > 9] or [DC = 1], then a  [0,1] (W<3:0>) + 6  W<3:0>; else Operation: (f) – 1  dest (W<3:0>)  W<3:0> Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1], then Encoding: 0000 01da ffff ffff (W<7:4>) + 6  W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C =1 result is stored in W. If ‘d’ is ‘1’, the else result is stored back in register ‘f’ (W<7:4>)  W<7:4> (default). Status Affected: C If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Decode Read Process Write to Example 1: DAW register ‘f’ Data destination Before Instruction W = A5h C = 0 Example: DECF CNT, 1, 0 DC = 0 Before Instruction After Instruction CNT = 01h W = 05h Z = 0 C = 1 DC = 0 After Instruction CNT = 00h Example 2: Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS30009977G-page 492  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction If the result is not ‘0’, the next which is already fetched is discarded instruction which is already fetched is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section29.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section29.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT  0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP  0; PC = Address (NZERO)  2010-2017 Microchip Technology Inc. DS30009977G-page 493

PIC18F66K80 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire 2-Mbyte memory incremented. If ‘d’ is ‘0’, the result is range. The 20-bit value ‘k’ is loaded into placed in W. If ‘d’ is ‘1’, the result is PC<20:1>. GOTO is always a two-cycle placed back in register ‘f’ (default). instruction. If ‘a’ is ‘0’, the Access Bank is selected. Words: 2 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates Q1 Q2 Q3 Q4 in Indexed Literal Offset Addressing Decode Read literal No Read literal mode whenever f 95 (5Fh). See ‘k’<7:0>, operation ‘k’<19:8>, Section29.2.3 “Byte-Oriented and Write to PC Bit-Oriented Instructions in Indexed No No No No Literal Offset Mode” for details. operation operation operation operation Words: 1 Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS30009977G-page 494  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result  0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’. (default) If the result is not ‘0’, the next If the result is ‘0’, the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO)  2010-2017 Microchip Technology Inc. DS30009977G-page 495

PIC18F66K80 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank. literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: IORLW 35h in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Before Instruction Section29.2.3 “Byte-Oriented and W = 9Ah Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS30009977G-page 496  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to file select register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 Decode Read literal Process Write If ‘a’ is ‘0’, the Access Bank is selected. ‘k’ MSB Data literal ‘k’ If ‘a’ is ‘1’, the BSR is used to select the MSB to GPR bank. FSRfH If ‘a’ is ‘0’ and the extended instruction Decode Read literal Process Write literal set is enabled, this instruction operates ‘k’ LSB Data ‘k’ to FSRfL in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Example: LFSR 2, 3ABh Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. FSR2H = 03h FSR2L = ABh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h  2010-2017 Microchip Technology Inc. DS30009977G-page 497

PIC18F66K80 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffff s Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffff d of BSR<7:4> always remains ‘0’ Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for Example: MOVLB 5 transferring a data memory location to a peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h After Instruction The MOVFF instruction cannot use the BSR Register = 05h PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS30009977G-page 498  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank. literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: MOVLW 5Ah in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See After Instruction Section29.2.3 “Byte-Oriented and W = 5Ah Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh  2010-2017 Microchip Technology Inc. DS30009977G-page 499

PIC18F66K80 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried out 8-bit literal ‘k’. The 16-bit result is between the contents of W and the placed in the PRODH:PRODL register register file location ‘f’. The 16-bit result is pair. PRODH contains the high byte. stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W is unchanged. W and ‘f’ are unchanged. None of the Status flags are affected. None of the Status flags are affected. Note that neither Overflow nor Carry is Note that neither Overflow nor Carry is possible in this operation. A Zero result possible in this operation. A Zero result is is possible but not detected. possible but not detected. Words: 1 If ‘a’ is ‘0’, the Access Bank is selected. If Cycles: 1 ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set Decode Read Process Write is enabled, this instruction operates in literal ‘k’ Data registers Indexed Literal Offset Addressing mode PRODH: whenever f 95 (5Fh). See PRODL Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: MULLW 0C4h Words: 1 Before Instruction W = E2h Cycles: 1 PRODH = ? Q Cycle Activity: PRODL = ? After Instruction Q1 Q2 Q3 Q4 W = E2h Decode Read Process Write PRODH = ADh register ‘f’ Data registers PRODL = 08h PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS30009977G-page 500  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: Section29.2.3 “Byte-Oriented and None. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h]  2010-2017 Microchip Technology Inc. DS30009977G-page 501

PIC18F66K80 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS30009977G-page 502  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n  PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC + 2 + 2n. This instruction is a Decode Start No No two-cycle instruction. reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2)  2010-2017 Microchip Technology Inc. DS30009977G-page 503

PIC18F66K80 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL; (TOS)  PC, if s = 1, PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  STATUS, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The Program Counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 Global Interrupt Enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers WS, Q1 Q2 Q3 Q4 STATUSS and BSRS are loaded into Decode Read Process POP PC their corresponding registers W, literal ‘k’ Data from stack, STATUS and BSR. If ‘s’ = 0, no update write to W of these registers occurs (default). No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS30009977G-page 504  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC; a  [0,1] if s = 1, (WS)  W, Operation: (f<n>)  dest<n + 1>, (STATUSS)  STATUS, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry flag. popped and the top of the stack (TOS) If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is loaded into the Program Counter. If is ‘1’, the result is stored back in register ‘s’= 1, the contents of the shadow ‘f’ (default). registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is selected. loaded into their corresponding If ‘a’ is ‘1’, the BSR is used to select the registers W, STATUS and BSR. If GPR bank. ‘s’ = 0, no update of these registers occurs (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 2 mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Q Cycle Activity: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1  2010-2017 Microchip Technology Inc. DS30009977G-page 505

PIC18F66K80 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘0’, the Access Bank is selected. register ‘f’ (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f 95 (5Fh). See set is enabled, this instruction operates Section29.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See Literal Offset Mode” for details. Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS30009977G-page 506  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n – 1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank. placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f 95 (5Fh). See per the BSR value. Section29.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111  2010-2017 Microchip Technology Inc. DS30009977G-page 507

PIC18F66K80 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored in is set. The Watchdog Timer and its W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. If with the oscillator stopped. ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates in Q Cycle Activity: Indexed Literal Offset Addressing mode Q1 Q2 Q3 Q4 whenever f 95 (5Fh). See Decode No Process Go to Section29.2.3 “Byte-Oriented and operation Data Sleep Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Example: SLEEP Cycles: 1 Before Instruction TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1 † register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS30009977G-page 508  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the result Q Cycle Activity: is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read Process Write to If ‘a’ is ‘1’, the BSR is used to select the literal ‘k’ Data W GPR bank. If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction operates Before Instruction in Indexed Literal Offset Addressing W = 01h mode whenever f 95 (5Fh). See C = ? Section29.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 01h Literal Offset Mode” for details. C = 1 ; result is positive Z = 0 Words: 1 N = 0 Cycles: 1 Example 2: SUBLW 02h Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 W = 02h C = ? Decode Read Process Write to After Instruction register ‘f’ Data destination W = 00h C = 1 ; result is zero Example 1: SUBWF REG, 1, 0 Z = 1 Before Instruction N = 0 REG = 3 Example 3: SUBLW 02h W = 2 C = ? Before Instruction After Instruction W = 03h REG = 1 C = ? W = 2 After Instruction C = 1 ; result is positive W = FFh ; (2’s complement) Z = 0 C = 0 ; result is negative N = 0 Z = 0 Example 2: SUBWF REG, 0, 0 N = 1 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1  2010-2017 Microchip Technology Inc. DS30009977G-page 509

PIC18F66K80 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section29.2.3 “Byte-Oriented and mode whenever f 95 (5Fh). See Bit-Oriented Instructions in Indexed Section29.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS30009977G-page 510  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR))  TABLAT; MEMORY(00A356h) = 34h TBLPTR – No Change After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR))  TABLAT; TBLPTR = 00A357h (TBLPTR) + 1  TBLPTR Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT; Before Instruction (TBLPTR) – 1  TBLPTR TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1  TBLPTR; MEMORY(01A358h) = 34h (Prog Mem (TBLPTR))  TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR<0> = 0:Least Significant Byte of Program Memory Word TBLPTR<0> = 1:Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT)  2010-2017 Microchip Technology Inc. DS30009977G-page 511

PIC18F66K80 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT)  Holding Register; TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT)  Holding Register; TABLAT = 55h (TBLPTR) + 1  TBLPTR TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT)  Holding Register; (00A356h) = 55h (TBLPTR) – 1  TBLPTR Example 2: TBLWT +*; if TBLWT+*, Before Instruction (TBLPTR) + 1  TBLPTR; TABLAT = 34h (TABLAT)  Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER (01389Bh) = 34h 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Memory Organization” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register) DS30009977G-page 512  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to set is enabled, this instruction operates literal ‘k’ Data W in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: XORLW 0AFh Section29.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = B5h After Instruction Words: 1 W = 1Ah Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT  00h, PC = Address (NZERO)  2010-2017 Microchip Technology Inc. DS30009977G-page 513

PIC18F66K80 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS30009977G-page 514  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 29.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table29-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section29.2.2 “Extended Instruction instruction set, the PIC18F66K80 family of devices also Set”. The opcode field descriptions in Table29-1 provides an optional extension to the core CPU func- (page474) apply to both the standard and extended tionality. The added features include eight additional PIC18 instruction sets. instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are enabled by default on unprogrammed devices. The syntax for these commands is Users must properly set or clear the XINST Configura- provided as a reference for users who tion bit during programming to enable or disable these may be reviewing code that has been features. generated by a compiler. The instructions in the extended set can all be classified as literal operations, which either manipulate 29.2.1 EXTENDED INSTRUCTION SYNTAX the File Select Registers, or use them for Indexed Most of the extended instructions use indexed argu- Addressing. Two of the instructions, ADDFSR and ments, using one of the File Select Registers and some SUBFSR, each have an additional special instantiation offset to specify a source or destination register. When for using FSR2. These versions (ADDULNK and an argument for an instruction serves as part of SUBULNK) allow for automatic return after execution. Indexed Addressing, it is enclosed in square brackets The extended instructions are specifically implemented (“[ ]”). This is done to indicate that the argument is used to optimize re-entrant program code (that is, code that as an index or offset. The MPASM™ Assembler will is recursive or that uses a software stack) written in flag an error if it determines that an index or offset value high-level languages, particularly C. Among other is not bracketed. things, they allow users working in high-level When the extended instruction set is enabled, brackets languages to perform certain operations on data are also used to indicate index arguments in structures more efficiently. These include: byte-oriented and bit-oriented instructions. This is in • Dynamic allocation and deallocation of software addition to other changes in their syntax. For more stack space when entering and leaving details, see Section29.2.3.1 “Extended Instruction subroutines Syntax with Standard PIC18 Commands”. • Function Pointer invocation Note: In the past, square brackets have been • Software Stack Pointer manipulation used to denote optional arguments in the • Manipulation of variables located in a software PIC18 and earlier instruction sets. In this stack text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 29-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None return  2010-2017 Microchip Technology Inc. DS30009977G-page 515

PIC18F66K80 FAMILY 29.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 + k  FSR2, Operation: FSR(f) + k  FSR(f) (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the TOS. Cycles: 1 Q Cycle Activity: The instruction takes two cycles to execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to literal ‘k’ Data FSR This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates Example: ADDFSR 2, 23h only on FSR2. Words: 1 Before Instruction FSR2 = 03FFh Cycles: 2 After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS30009977G-page 516  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0  z  127 s 0  f  4095 Operation: (PC + 2)  TOS, d (W)  PCL, Operation: ((FSR2) + z )  f s d (PCLATH)  PCH, Status Affected: None (PCLATU)  PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffff d Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’, in the first word, to the value s latched into PCH and PCU, of FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data space (000h to FFFh). Unlike CALL, there is no option to update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an Indirect Addressing register, the Q1 Q2 Q3 Q4 value returned will be 00h. Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Before Instruction Decode No No Write PC = address (HERE) operation operation register ‘f’ PCLATH = 10h No dummy (dest) PCLATU = 00h W = 06h read After Instruction PC = 001006h TOS = address (HERE + 2) Example: MOVSF [05h], REG2 PCLATH = 10h PCLATU = 00h Before Instruction W = 06h FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h  2010-2017 Microchip Technology Inc. DS30009977G-page 517

PIC18F66K80 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0  zs  127 Operands: 0k  255 0  z  127 d Operation: k  (FSR2), Operation: ((FSR2) + zs)  ((FSR2) + zd) FSR2 – 1  FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. Description The contents of the source register are FSR2 is decremented by 1 after the moved to the destination register. The operation. addresses of the source and destination registers are determined by adding the This instruction allows users to push 7-bit literal offsets, ‘z ’ or ‘z ’, values onto a software stack. s d respectively, to the value of FSR2. Both Words: 1 registers can be located anywhere in the 4096-byte data memory space Cycles: 1 (000h to FFFh). Q Cycle Activity: The MOVSS instruction cannot use the Q1 Q2 Q3 Q4 PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to destination register. data destination If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the Example: PUSHL 08h resultant destination address points to Before Instruction an Indirect Addressing register, the FSR2H:FSR2L = 01ECh instruction will execute as a NOP. Memory (01ECh) = 00h Words: 2 After Instruction Cycles: 2 FSR2H:FSR2L = 01EBh Q Cycle Activity: Memory (01ECh) = 08h Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS30009977G-page 518  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0  k  63 Operands: 0  k  63 f  [ 0, 1, 2 ] Operation: FSR2 – k  FSR2, Operation: FSRf – k  FSRf (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified contents of the FSR2. A RETURN is then by ‘f’. executed by loading the PC with the TOS. Words: 1 Cycles: 1 The instruction takes two cycles to execute; a NOP is performed during the Q Cycle Activity: second cycle. Q1 Q2 Q3 Q4 This may be thought of as a special case Decode Read Process Write to of the SUBFSR instruction, where f = 3 register ‘f’ Data destination (binary ‘11’); it operates only on FSR2. Words: 1 Example: SUBFSR 2, 23h Cycles: 2 Before Instruction Q Cycle Activity: FSR2 = 03FFh Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to FSR2 = 03DCh register ‘f’ Data destination No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS)  2010-2017 Microchip Technology Inc. DS30009977G-page 519

PIC18F66K80 FAMILY 29.2.3 BYTE-ORIENTED AND 29.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set exten- register argument ‘f’ in the standard byte-oriented and sion may cause legacy applications to bit-oriented commands is replaced with the literal offset value ‘k’. As already noted, this occurs only when ‘f’ is behave erratically or fail entirely. less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing (Section6.6.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within the brackets, will the standard PIC18 instruction set are interpreted. generate an error in the MPASM™ Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (a = 0) or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and a = 0, however, instruction set disabled), when ‘a’ is set on the basis of a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM literal address. For practical purposes, this means that Assembler. all instructions that use the Access RAM bit as an The destination argument ‘d’ functions as before. argument – that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instruc- In the latest versions of the MPASM Assembler, tions – may behave differently when the extended language support for the extended instruction set must instruction set is enabled. be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the When the content of FSR2 is 00h, the boundaries of the source listing. Access RAM are essentially remapped to their original values. This may be useful in creating 29.2.4 CONSIDERATIONS WHEN backward-compatible code. If this technique is used, it ENABLING THE EXTENDED may be necessary to save the value of FSR2 and INSTRUCTION SET restore it when moving back and forth between C and assembly routines in order to preserve the Stack It is important to note that the extensions to the instruc- Pointer. Users must also keep in mind the syntax tion set may not be beneficial to all users. In particular, requirements of the extended instruction set (see users who are not writing code that uses a software Section29.2.3.1 “Extended Instruction Syntax with stack may not benefit from using the extensions to the Standard PIC18 Commands”). instruction set. Although the Indexed Literal Offset mode can be very Additionally, the Indexed Literal Offset Addressing useful for dynamic stack and pointer manipulation, it mode may create issues with legacy applications can also be very annoying if a simple arithmetic opera- written to the PIC18 assembler. This is because tion is carried out on the wrong register. Users who are instructions in the legacy code may attempt to address accustomed to the PIC18 programming must keep in registers in the Access Bank below 5Fh. Since these mind that, when the extended instruction set is addresses are interpreted as literal offsets to FSR2 enabled, register addresses of 5Fh or less are used for when the instruction set extension is enabled, the Indexed Literal Offset Addressing. application may read or write to the wrong data addresses. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset When porting an application to the PIC18F66K80 mode are provided on the following page to show how family, it is very important to consider the type of code. execution is affected. The operand conditions shown in A large, re-entrant application that is written in C and the examples are applicable to all instructions of these would benefit from efficient compilation will do well types. when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS30009977G-page 520  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0  k  95 Operands: 0  f  95 d  [0,1] 0  b  7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ Cycles: 1 is ‘1’, the result is stored back in register ‘f’ (default). Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1 register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Contents Example: ADDWF [OFST],0 of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction Set Indexed SETF W = 37h (Indexed Literal Offset mode) Contents of 0A2Ch = 20h Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh  2010-2017 Microchip Technology Inc. DS30009977G-page 521

PIC18F66K80 FAMILY 29.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set for the PIC18F66K80 family. This includes the • A menu option or dialog box within the MPLAB C18 C Compiler, MPASM assembly language environment that allows the user to configure the and MPLAB Integrated Development Environment language tool and its settings for the project (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended information. instruction set, XINST must be set during programming. DS30009977G-page 522  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 30.0 DEVELOPMENT SUPPORT 30.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for - MPLAB XC Compiler high-performance application development and debug- - MPASMTM Assembler ging. Moving between tools and upgrading from soft- - MPLINKTM Object Linker/ ware simulators to hardware debugging and MPLIBTM Object Librarian programming tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for Various Device Families With complete project management, visual call graphs, • Simulators a configurable watch window and a feature-rich editor that includes code completion and context menus, - MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new • Emulators users. With the ability to support multiple tools on - MPLAB REAL ICE™ In-Circuit Emulator multiple projects with simultaneous debugging, MPLAB • In-Circuit Debuggers/Programmers X IDE is also suitable for the needs of experienced - MPLAB ICD 3 users. - PICkit™ 3 Feature-Rich Editor: • Device Programmers • Color syntax highlighting - MPLAB PM3 Device Programmer • Smart code completion makes suggestions and • Low-Cost Demonstration/Development Boards, provides hints as you type Evaluation Kits and Starter Kits • Automatic code formatting based on user-defined • Third-party development tools rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2010-2017 Microchip Technology Inc. DS30009977G-page 523

PIC18F66K80 FAMILY 30.2 MPLAB XC Compilers 30.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 30.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 30.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS30009977G-page 524  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 30.6 MPLAB X SIM Software Simulator 30.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a The MPLAB X SIM Software Simulator fully supports high-speed USB 2.0 interface and is connected to the symbolic debugging using the MPLAB XCCompilers, target with a connector compatible with the MPLAB and the MPASM and MPLAB Assemblers. The soft- ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ware simulator offers the flexibility to develop and ICD 3 supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 30.9 PICkit 3 In-Circuit development tool. Debugger/Programmer 30.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a Microchip Flash DSC and MCU devices. It debugs and full-speed USB interface and can be connected to the programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com- with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 30.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, The MPLAB PM3 Device Programmer is a universal, Low-Voltage Differential Signal (LVDS) interconnec- CE compliant device programmer with programmable tion (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2010-2017 Microchip Technology Inc. DS30009977G-page 525

PIC18F66K80 FAMILY 30.11 Demonstration/Development 30.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS30009977G-page 526  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on MCLR with respect to VSS..........................................................................................................-0.3V to 9.0V Voltage on any digital only I/O pin with respect to VSS (except VDD)...........................................................-0.3V to 7.5V Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)......-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS (PIC18F66K80).................................................................................. -0.3V to 7.5V Voltage on VDD with respect to VSS (PIC18LF66K80).............................................................................. -0.3V to 3.66V Total power dissipation (Note 1)..................................................................................................................................1W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD).................................................................................................. ±20 mA Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25mA Maximum output current sunk by any PORTD and PORTE I/O pins........................................................................8mA Maximum output current sunk by PORTA<5:0> and any PORTF and PORTG I/O pins...........................................2mA Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins...................................25mA Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8mA Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins.......................2mA Maximum current sunk byall ports combined.......................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010-2017 Microchip Technology Inc. DS30009977G-page 527

PIC18F66K80 FAMILY FIGURE 31-1: VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL/EXTENDED)(1) 6V 5.5V 5V 4V PIC18F66K80 Family ) D D V 3V ( e g 3V a olt 1.8V V 0 4 MHz Frequency 64 MHz Note 1: For VDD values 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz. FIGURE 31-2: VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL/EXTENDED)(1,2) 4V 3.75V 3.6V 3.25V PIC18LF66K80 Family 3V )D 2.5V D V e ( 1.8V g a t ol V 4 MHz 64 MHz Frequency Note 1: When the on-chip voltage regulator is disabled, VDD must be maintained so that VDD 3.6V. 2: For VDD values 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz. DS30009977G-page 528  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.1 DC Characteristics: Supply Voltage PIC18F66K80 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage 1.8 — 3.6 V For LF devices 1.8 — 5.5 V For F devices D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section5.3 “Power-on to Ensure Internal Reset (POR)” for details Power-on Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section5.3 “Power-on to Ensure Internal Reset (POR)” for details Power-on Reset Signal D005 BVDD Brown-out Reset Voltage (High, Medium and Low-Power mode BORV<1:0> = 11(2) 1.69 1.8 1.91 V BORV<1:0> = 10 1.88 2.0 2.12 V BORV<1:0> = 01 2.53 2.7 2.86 V BORV<1:0> = 00 2.82 3.0 3.18 V Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: Device will operate normally until Brown-out Reset occurs, even though VDD may be below VDDMIN.  2010-2017 Microchip Technology Inc. DS30009977G-page 529

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) PIC18LFXXK80 8 400 nA -40°C 13 500 nA +25°C VDD = 1.8V 35 750 nA +60°C (Sleep mode) Regulator Disabled 218 980 nA +85°C 3 6 A +125°C PIC18LFXXK80 14 500 nA -40°C 34 600 nA +25°C VDD = 3.3V 92 850 nA +60°C (Sleep mode) Regulator Disabled 312 1250 nA +85°C 4 8 µA +125°C PIC18FXXK80 200 700 nA -40°C 230 800 nA +25°C VDD = 3.3V 320 1050 nA +60°C (Sleep mode) Regulator Enabled 510 1500 nA +85°C 5 9 µA +125°C PIC18FXXK80 220 1000 nA -40°C 240 1000 nA +25°C VDD = 5V 340 1100 nA +60°C (Sleep mode) Regulator Enabled 540 1580 nA +85°C 5 10 µA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS30009977G-page 530  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LFXXK80 4 8 A -40°C 4 8 A +25°C VDD = 1.8V(4) 4 8 A +60°C Regulator Disabled 5 9 A +85°C 9 12 A +125°C PIC18LFXXK80 7 11 A -40°C 7 11 A +25°C VDD = 3.3V(4) 7 11 A +60°C Regulator Disabled 8 12 A +85°C 13 15 A +125°C FOSC = 31kHz (RC_RUN mode, PIC18FXXK80 51 150 A -40°C LF-INTOSC) 70 150 A +25°C VDD = 3.3V(5) 75 150 A +60°C Regulator Enabled 80 170 A +85°C 88 190 A +125°C PIC18FXXK80 75 180 A -40°C 75 180 A +25°C VDD = 5V(5) 75 180 A +60°C Regulator Enabled 80 190 A +85°C 95 200 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.  2010-2017 Microchip Technology Inc. DS30009977G-page 531

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 274 600 A -40°C 274 600 A +25°C VDD = 1.8V(4) 274 600 A +60°C Regulator Disabled 280 650 A +85°C 290 700 A +125°C PIC18LFXXK80 410 820 A -40°C 410 820 A +25°C VDD = 3.3V(4) 410 820 A +60°C Regulator Disabled 420 840 A +85°C 430 990 A +125°C FOSC = 1MHz (RC_RUN mode, PIC18FXXK80 490 860 A -40°C HF-INTOSC) 490 860 A +25°C VDD = 3.3V(5) 490 860 A +60°C Regulator Enabled 500 890 A +85°C 510 1060 A +125°C PIC18FXXK80 490 910 A -40°C 490 910 A +25°C VDD = 5V(5) 490 910 A +60°C Regulator Enabled 500 970 A +85°C 510 1125 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS30009977G-page 532  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 520 820 µA -40°C 520 820 µA +25°C VDD = 1.8V(4) 520 820 µA +60°C Regulator Disabled 530 880 µA +85°C 540 1000 µA +125°C PIC18LFXXK80 941 1600 µA -40°C 941 1600 µA +25°C VDD = 3.3V(4) 941 1600 µA +60°C Regulator Disabled 950 1610 µA +85°C 960 1800 µA +125°C FOSC = 4MHz (RC_RUN mode, PIC18FXXK80 981 1640 A -40°C HF-INTOSC) 981 1640 A +25°C VDD = 3.3V(5) 981 1640 A +60°C Regulator Enabled 990 1650 A +85°C 1000 1900 A +125°C PIC18FXXK80 1 2.2 mA -40°C 1 2.2 mA +25°C VDD = 5V(5) 1 2.2 mA +60°C Regulator Enabled 1 2.2 mA +85°C 1 2.2 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.  2010-2017 Microchip Technology Inc. DS30009977G-page 533

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 880 1600 nA -40°C 880 1600 nA +25°C VDD = 1.8V(4) 880 1600 nA +60°C Regulator Disabled 1 2 A +85°C 5 10 A +125°C PIC18LFXXK80 1.6 5 A -40°C 1.6 5 A +25°C VDD = 3.3V(4) 1.6 5 A +60°C Regulator Disabled 2 6 A +85°C 7 12 A +125°C FOSC = 31kHz (RC_IDLE mode, PIC18FXXK80 41 130 A -40°C LF-INTOSC) 59 130 A +25°C VDD = 3.3V(5) 64 130 A +60°C Regulator Enabled 70 150 A +85°C 80 175 A +125°C PIC18FXXK80 53 160 A -40°C 62 160 A +25°C VDD = 5V(5) 70 160 A +60°C Regulator Enabled 85 170 A +85°C 100 180 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS30009977G-page 534  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 260 380 A -40°C 260 380 A +25°C VDD = 1.8V(4) 260 380 A +60°C Regulator Disabled 270 390 A +85°C 280 420 A +125°C PIC18LFXXK80 400 500 A -40°C 400 500 A +25°C VDD = 3.3V(4) 400 500 A +60°C Regulator Disabled 410 520 A +85°C 420 580 A +125°C FOSC = 1MHz (RC_IDLE mode, PIC18FXXK80 430 560 A -40°C HF-INTOSC) 430 560 A +25°C VDD = 3.3V(5) 430 560 A +60°C Regulator Enabled 450 580 A +85°C 480 620 A +125°C PIC18FXXK80 450 620 A -40°C 450 620 A +25°C VDD = 5V(5) 450 620 A +60°C Regulator Enabled 470 640 A +85°C 500 680 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.  2010-2017 Microchip Technology Inc. DS30009977G-page 535

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 330 480 A -40°C 330 480 A +25°C VDD = 1.8V(4) 330 480 A +60°C Regulator Disabled 340 500 A +85°C 350 540 A +125°C PIC18LFXXK80 522 720 A -40°C 522 720 A +25°C VDD = 3.3V(4) 522 720 A +60°C Regulator Disabled 540 740 A +85°C 550 780 A +125°C FOSC = 4MHz (RC_IDLE mode, PIC18FXXK80 540 760 A -40°C Internal HF-INTOSC) 540 760 A +25°C VDD = 3.3V(5) 540 760 A +60°C Regulator Enabled 560 780 A +85°C 580 810 A +125°C PIC18FXXK80 600 1250 A -40°C 600 1250 A +25°C VDD = 5V(5) 600 1250 A +60°C Regulator Enabled 610 1300 A +85°C 620 1340 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS30009977G-page 536  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 90 260 A -40°C 90 260 A +25°C VDD = 1.8V(4) 90 260 A +60°C Regulator Disabled 100 270 A +85°C 110 300 A +125°C PIC18LFXXK80 163 540 A -40°C 163 540 A +25°C VDD = 3.3V(4) 163 540 A +60°C Regulator Disabled 170 560 A +85°C 180 600 A +125°C FOSC = 1MHZ (PRI_RUN mode, PIC18FXXK80 201 560 A -40°C EC oscillator) 217 560 A +25°C VDD = 3.3V(5) 224 560 A +60°C Regulator Enabled 228 580 A +85°C 236 620 A +125°C PIC18FXXK80 240 740 A -40°C 240 740 A +25°C VDD = 5V(5) 240 740 A +60°C Regulator Enabled 250 840 A +85°C 260 940 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.  2010-2017 Microchip Technology Inc. DS30009977G-page 537

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 270 600 A -40°C 270 600 A +25°C VDD = 1.8V(4) 270 600 A +60°C Regulator Disabled 300 700 A +85°C 320 850 A +125°C PIC18LFXXK80 540 1000 A -40°C 540 1000 A +25°C VDD = 3.3V(4) 540 1000 A +60°C Regulator Disabled 550 1100 A +85°C 560 1200 A +125°C FOSC = 4MHz (PRI_RUN mode, PIC18FXXK80 566 1020 A -40°C EC oscillator) 585 1020 A +25°C VDD = 3.3V(5) 590 1020 A +60°C Regulator Enabled 595 1120 A +85°C 600 1220 A +125°C PIC18FXXK80 630 2000 A -40°C 630 2000 A +25°C VDD = 5V(5) 630 2000 A +60°C Regulator Enabled 640 2000 A +85°C 650 2000 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS30009977G-page 538  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 2 5 mA -40°C to +125°C VDD = 3.3V(4) Regulator Disabled PIC18FXXK80 2 5 mA -40°C to +125°C VDD = 3.3V(5) FOSC = 16MHZ (PRI_RUN mode, 4 MHz Regulator Enabled EC oscillator with PLL) PIC18FXXK80 2 6 mA -40°C to +125°C VDD = 5.5V(5) Regulator Enabled PIC18LFXXK80 7 11 mA -40°C to +125°C VDD = 3.3V(4) Regulator Disabled PIC18FXXK80 7 11 mA -40°C to +125°C VDD = 3.3V(5) FOSC = 64MHz (PRI_RUN mode, 16 MHz Regulator Enabled EC oscillator with PLL) PIC18FXXK80 8 12 mA -40°C to +125°C VDD = 5.5V(5) Regulator Enabled PIC18LFXXK80 7 11 mA -40°C to +125°C VDD = 3.3V(4) Regulator Disabled PIC18FXXK80 7 11 mA -40°C to +125°C VDD = 3.3V(4) FOSC = 64MHz (PRI_RUN mode, Regulator Enabled EC oscillator) PIC18FXXK80 8 12 mA -40°C to +125°C VDD = 5.5V(5) Regulator Enabled PIC18LFXXK80 2.3 5 mA -40°C to +125°C VDD = 3.3V(4) Regulator Disabled PIC18FXXK80 2.3 5 mA -40°C to +125°C VDD = 3.3V(5) FOSC = 64MHz (PRI_IDLE mode, Regulator Enabled EC oscillator) PIC18FXXK80 2.5 6 mA -40°C to +125°C VDD = 5.5V(5) Regulator Enabled Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.  2010-2017 Microchip Technology Inc. DS30009977G-page 539

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 20 70 µA -40°C 20 70 µA +25°C VDD = 1.8V(4) 20 70 µA +60°C Regulator disabled 25 80 µA +85°C 30 100 µA +125°C PIC18LFXXK80 37 120 µA -40°C 37 120 µA +25°C VDD = 3.3V(4) 37 120 µA +60°C Regulator disabled 40 130 µA +85°C 45 150 µA +125°C FOSC = 1MHz (PRI_IDLE mode, PIC18FXXK80 85 140 µA -40°C EC oscillator) 100 140 µA +25°C VDD = 3.3V(5) 105 140 µA +60°C Regulator enabled 110 150 µA +85°C 120 170 µA +125°C PIC18FXXK80 110 225 µA -40°C 110 225 µA +25°C VDD = 5V(5) 110 225 µA +60°C Regulator enabled 120 230 µA +85°C 130 250 µA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS30009977G-page 540  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 75 160 µA -40°C 75 160 µA +25°C VDD = 1.8V(4) 75 160 µA +60°C Regulator Disabled 76 170 µA +85°C 82 180 µA +125°C PIC18LFXXK80 148 300 µA -40°C 148 300 µA +25°C VDD = 3.3V(4) 148 300 µA +60°C Regulator Disabled 150 400 µA +85°C 157 460 µA +125°C FOSC = 4MHz (PRI_IDLE mode, PIC18FXXK80 187 320 µA -40°C EC oscillator) 204 320 µA +25°C VDD = 3.3V(5) 212 320 µA +60°C Regulator Enabled 218 420 µA +85°C 230 480 µA +125°C PIC18FXXK80 230 500 µA -40°C 230 500 µA +25°C VDD = 5V(5) 230 500 µA +60°C Regulator Enabled 240 600 µA +85°C 250 700 µA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.  2010-2017 Microchip Technology Inc. DS30009977G-page 541

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 2 8 µA -40°C 5 10 µA +25°C VDD = 1.8V(4) 6 15 µA +60°C Regulator Disabled 8 20 µA +85°C 13 30 µA +125°C PIC18LFXXK80 3 15 µA -40°C 16 22 µA +25°C VDD = 3.3V(4) 17 28 µA +60°C Regulator Disabled 19 39 µA +85°C 25 60 µA +125°C FOSC = 32kHz(3) (SEC_RUN mode, PIC18FXXK80 70 170 µA -40°C SOSCSELX = 01) 70 170 µA +25°C VDD = 3.3V(5) 70 170 µA +60°C Regulator Enabled 75 180 µA +85°C 90 190 µA +125°C PIC18FXXK80 75 180 µA -40°C 75 180 µA +25°C VDD = 5V(5) 75 180 µA +60°C Regulator Enabled 80 190 µA +85°C 95 200 µA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS30009977G-page 542  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 1.4 4 µA -40°C 2.4 6 µA +25°C VDD = 1.8V(4) 3.6 10 µA +60°C Regulator Disabled 4.6 12 µA +85°C 9.0 20 µA +125° PIC18LFXXK80 2 5 µA -40°C 10 18 µA +25°C VDD = 3.3V(4) 11 22 µA +60°C Regulator Disabled 13 30 µA +85°C 17 40 µA +125° FOSC = 32kHz(3) (SEC_IDLE mode, PIC18FXXK80 55 150 µA +25°C SOSCSELX = 01) 55 150 µA +60°C VDD = 3.3V(5) 55 150 µA +85°C Regulator Enabled 60 160 µA +125°C 75 170 µA +25°C PIC18FXXK80 53 160 µA -40°C 62 160 µA +25°C VDD = 5V(5) 70 160 µA +60°C Regulator Enabled 85 170 µA +85°C 100 180 µA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.  2010-2017 Microchip Technology Inc. DS30009977G-page 543

PIC18F66K80 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +85°C for industrial (Industrial/Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Module Differential Currents (IWDT, IBOR, IHLVD, IADC) D022 Watchdog Timer IWDT) PIC18LFXXK80 0.4 2 A -40°C to +125°C VDD = 1.8V Regulator Disabled PIC18LFXXK80 0.6 3 A -40°C to +125°C VDD = 3.3V Regulator Disabled PIC18FXXK80 0.6 3 A -40°C to +125°C VDD = 3.3V Regulator Enabled PIC18FXXK80 0.8 4 A -40°C to +125°C VDD = 5.5V Regulator Enabled D022A Brown-out Reset IBOR) PIC18LFXXK80 4.6 20 A -40°C to +125°C VDD = 1.8V Regulator Disabled PIC18FXXK80 4.6 20 A -40°C to +125°C VDD = 3.3V High-Power BOR Regulator Enabled PIC18FXXK80 4.6 20 A -40°C to +125°C VDD = 5.5V Regulator Enabled D022B High/Low-Voltage Detect IHLVD PIC18LFXXK80 3.8 10 A -40°C to +125°C VDD = 1.8V Regulator Disabled PIC18LFXXK80 4.5 12 A -40°C to +125°C VDD = 3.3V Regulator Disabled PIC18FXXK80 3.8 12 A -40°C to +125°C VDD = 3.3V Regulator Enabled PIC18FXXK80 4.9 13 A -40°C to +125°C VDD = 5.5V Regulator Enabled D026 A/D Converter IADC PIC18LFXXK80 0.4 1.5 -40°C to +125°C VDD = 1.8V Regulator Disabled PIC18LFXXK80 0.5 2 A -40°C to +125°C VDD = 3.3V Regulator Disabled A/D on, not converting PIC18FXXK80 0.5 3 A -40°C to +125°C VDD = 3.3V Regulator Enabled PIC18FXXK80 1 3 A -40°C to +125°C VDD = 5.5V Regulator Enabled Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 4: For LF devices, RETEN (CONFIG1L<0>) = 1. 5: For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0. DS30009977G-page 544  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.3 DC Characteristics: PIC18F66K80 Family (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage All I/O Ports: D031 Schmitt Trigger Buffer VSS 0.2 VDD V 1.8V  VDD 5.5V D031A RC3 and RC4 VSS 0.3 VDD V I2C™ enabled D031B VSS 0.8 V SMBus enabled D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.2 VDD V LP, XT, HS modes D033A OSC1 VSS 0.2 VDD V EC modes D034 SOSCI VSS 0.3 VDD V VIH Input High Voltage All I/O Ports: D041 Schmitt Trigger Buffer 0.8 VDD VDD V 1.8V  VDD 5.5V D041A RC3 and RC4 0.7 VDD VDD V I2C enabled D041B 2.1 VDD V SMBus enabled D042 MCLR 0.8 VDD VDD V D043 OSC1 0.9 VDD VDD V RC mode D043A OSC1 0.7 VDD VDD V HS mode D044 SOSCI 0.7 VDD VDD V IIL Input Leakage Current(1) D060 I/O Ports ±50 ±500 nA VSS VPIN VDD, Pin at high-impedance D061 MCLR — ±500 nA Vss VPIN VDD D063 OSC1 — 1 A Vss VPIN VDD IPU Weak Pull-up Current D070 Weak Pull-up Current 50 400 A VDD = 5.5V, VPIN = VSS VOL Output Low Voltage D080 I/O Ports: PORTA, PORTB, PORTC — 0.6 V IOL = 8.5 mA, VDD = 5.5V, -40C to +125C PORTD, PORTE, PORTF, — 0.6 V IOL = 3.5 mA, VDD = 5.5V, PORTG -40C to +125C D083 OSC2/CLKO (EC modes) — 0.6 V IOL = 1.6 mA, VDD = 5.5V, -40C to +125C Note 1: Negative current is defined as current sourced by the pin.  2010-2017 Microchip Technology Inc. DS30009977G-page 545

PIC18F66K80 FAMILY 31.3 DC Characteristics: PIC18F66K80 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VOH Output High Voltage(1) D090 I/O Ports: V PORTA, PORTB, PORTC VDD – 0.7 — V IOH = -3 mA, VDD = 5.5V, -40C to +125C PORTD, PORTE, PORTF, VDD – 0.7 — V IOH = -2 mA, VDD = 5.5V, PORTG -40C to +125C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1 mA, VDD = 5.5V, (INTOSC, EC modes) -40C to +125C Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 Pin — 20 pF In HS mode when external clock is used to drive OSC1 D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing Specifications D102 CB SCL, SDA — 400 pF I2C™ Specification Note 1: Negative current is defined as current sourced by the pin. DS30009977G-page 546  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.4 DC Characteristics: PIC18F66K80 Family (Industrial) Standard Operating Conditions: 1.8V to 5.5V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. D160a IICL Input Low Injection Current 0 — -5(1) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO D160b IICH Input High Injection Current 0 — +5(1) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO D160c ÅIICT Total Input Injection Current -20(1,2) — +20(1,2) mA Absolute instantaneous (sum of all I/O and control sum of all input injection pins) currents from all I/O pins ( IICL + IICH)  IICT Note 1: Injection currents >  0 can affect the A/D results. 2: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted. 31.5 DC Characteristics: CTMU Current Source Specifications Standard Operating Conditions: 1.8V to 5.5V DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max Units Conditions No. IOUT1 CTMU Current Source, — 550 — nA CTMUICON<1:0> = 01 Base Range IOUT2 CTMU Current Source, — 5.5 — A CTMUICON<1:0> = 10 10x Range IOUT3 CTMU Current Source, — 55 — A CTMUICON<1:0> = 11 100x Range Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).  2010-2017 Microchip Technology Inc. DS30009977G-page 547

PIC18F66K80 FAMILY TABLE 31-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP/RE5 pin VDD + 1.5 — 10 V (Note 3, Note 4) D113 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory (Note 2) D120 ED Byte Endurance 100K 1000K — E/W -40C to +125C D121 VDRW VDD for Read/Write 1.8 — 5.5 V Using EECON to read/write PIC18FXXKXX devices 1.8 — 3.6 V Using EECON to read/write PIC18LFXXKXX devices D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +125°C Cycles before Refresh(2) Program Flash Memory D130 EP Cell Endurance 1K 10K — E/W -40C to +125C D131 VPR VDD for Read 1.8 — 5.5 V PIC18FXXKXX devices 1.8 — 3.6 V PIC18LFXXKXX devices D132B VPEW Voltage for Self-Timed Erase or Write Operations VDD 1.8 — 5.5 V PIC18FXXKXX devices D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — — 10 mA Programming D140 TWE Writes per Erase Cycle — — 1 For each physical address † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section8.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if Single-Supply Programming is disabled. 4: The MPLAB® ICD 2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD2. DS30009977G-page 548  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 31-2: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V  VDD  5.5V, -40°C  TA  +125°C Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 40 mV D301 VICM Input Common Mode Voltage — — AVDD V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1) — 675 1200 ns D304 TMC2OV Comparator Mode Change to — — 10 s Output Valid* Note 1: Response time is measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 31-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 1.8V  VDD  5.5V, -40°C  TA  +125°C Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k —  D313 TSET Settling Time(1) — — 10 s Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. TABLE 31-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C  TA  +125°C Param Sym Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage — 3.3 — V CEFC External Filter Capacitor Value 4.7 10 — F Capacitor must be low-ESR, a low series resistance (< 5)  2010-2017 Microchip Technology Inc. DS30009977G-page 549

PIC18F66K80 FAMILY 31.6 AC (Timing) Characteristics 31.6.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS30009977G-page 550  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 31.6.2 TIMING CONDITIONS The temperature and voltages specified in Table31-5 apply to all timing specifications unless otherwise noted. Figure31-3 specifies the load conditions for the timing specifications. TABLE 31-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA +85°C for industrial AC CHARACTERISTICS -40°C  TA +125°C for extended Operating voltage VDD range as described in Section31.1 and Section31.3. FIGURE 31-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50 pF for all pins except OSC2/CLKO/RA6 and including D and E outputs as ports CL = 15 pF for OSC2/CLKO/RA6  2010-2017 Microchip Technology Inc. DS30009977G-page 551

PIC18F66K80 FAMILY 31.6.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 31-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 31-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKIN DC 64 MHz EC, ECIO Oscillator mode Frequency(1) Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 16 MHz HS Oscillator mode 4 16 MHz HS + PLL Oscillator mode 5 33 kHz LP Oscillator mode 1 TOSC External CLKIN Period(1) 15.6 — ns EC, ECIO Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 250 10,000 ns XT Oscillator mode 40 250 ns HS Oscillator mode 62.5 250 ns HS + PLL Oscillator mode 5 200 s LP Oscillator mode 2 TCY Instruction Cycle Time(1) 62.5 — ns TCY = 4/FOSC 3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode TOSH High or Low Time 2.5 — s LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode TOSF Rise or Fall Time — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS30009977G-page 552  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 31-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 5.5V) Param Sym Characteristic Min Typ Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 5 MHz VDD = 1.8-5.5V 4 — 16 MHz VDD = 3.0-5.5V, -40°C to +125°C F11 FSYS On-Chip VCO System Frequency 16 — 20 MHz VDD = 1.8-5.5V 16 — 64 MHz VDD = 3.0-5.5V, -40°C to +125°C F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 CLK CLKOUT Stability (Jitter) -2 — +2 % TABLE 31-8: INTERNAL RC ACCURACY (INTOSC) Standard Operating Conditions (unless otherwise stated) PIC18F66K80 Family Operating temperature -40°C  TA  +125°C Param Min Typ Max Units Conditions No. OA1 HFINTOSC/MFINTOSC Accuracy @ Freq = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz(1) -2 — +2 % +25°C VDD = 3-5.5V -5 — +5 % -40°C to +85°C VDD = 1.8-5.5V -10 — +10 % -40°C to +125°C VDD = 1.8-5.5V OA2 LFINTOSC Accuracy @ Freq = 31 kHz -15 — +15 % -40°C to +125°C VDD = 1.8-5.5V Note 1: Frequency is calibrated at +25°C. OSCTUNE register can be used to compensate for temperature drift.  2010-2017 Microchip Technology Inc. DS30009977G-page 553

PIC18F66K80 FAMILY FIGURE 31-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure31-3 for load conditions. TABLE 31-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns (Note 1) 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 15 30 ns (Note 1) 13 TCKF CLKO Fall Time — 15 30 ns (Note 1) 14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns 15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns 16 TCKH2IOI Port In Hold after CLKO  0 — — ns 17 TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1  (Q2 cycle) to Port Input Invalid 100 — — ns (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1  0 — — ns (I/O in setup time) 20 TIOR Port Output Rise Time — 10 25 ns 21 TIOF Port Output Fall Time — 10 25 ns 22† TINP INTx pin High or Low Time 20 — — ns 23† TRBP RB<7:4> Change INTx High or Low TCY — — ns Time † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC. DS30009977G-page 554  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 31-10: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE  0.25 TCY – 10 — — ns (address setup time) 151 TalL2adl ALE  to Address Out Invalid 5 — — ns (address hold time) 155 TalL2oeL ALE to OE  10 0.125 TCY — ns 160 TadZ2oeL AD High-Z to OE (bus release to OE) 0 — — ns 161 ToeH2adD OE  to AD Driven 0.125 TCY – 5 — — ns 162 TadV2oeH LS Data Valid before OE (data setup time) 20 — — ns 163 ToeH2adl OE  to Data In Invalid (data hold time) 0 — — ns 164 TalH2alL ALE Pulse Width — 0.25 TCY — ns 165 ToeL2oeH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TalH2alH ALE  to ALE  (cycle time) — TCY — ns 167 Tacc Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 Toe OE  to Data Valid — 0.5 TCY – 25 ns 169 TalL2oeH ALE to OE  0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE  0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns FIGURE 31-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure31-3 for load conditions.  2010-2017 Microchip Technology Inc. DS30009977G-page 555

PIC18F66K80 FAMILY FIGURE 31-7: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 31-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period — 4 — ms (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period — 1 — ms 34 TIOZ I/O High-Impedance from MCLR — 2 — s Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — s VDD  BVDD (see D005) 36 TIVRST Time for Internal Reference — 25 — s Voltage to become Stable 37 THLVD High/Low-Voltage Detect Pulse Width 200 — — s VDD  VHLVD 38 TCSD CPU Start-up Time 5 — 10 s 39 TIOBST Time for INTOSC to Stabilize — 1 — s DS30009977G-page 556  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 31-8: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 31-12: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA +125°C for extended Param Sym Characteristic Min Typ Max Units Conditions No. D420 HLVD Voltage on VDD HLVDL<3:0> = 0000 1.80 1.85 1.90 V Transition High-to-Low HLVDL<3:0> = 0001 2.03 2.08 2.13 V HLVDL<3:0> = 0010 2.24 2.29 2.35 V HLVDL<3:0> = 0011 2.40 2.46 2.53 V HLVDL<3:0> = 0100 2.50 2.56 2.62 V HLVDL<3:0> = 0101 2.70 2.77 2.84 V HLVDL<3:0> = 0110 2.82 2.89 2.97 V HLVDL<3:0> = 0111 2.95 3.02 3.10 V HLVDL<3:0> = 1000 3.24 3.32 3.41 V HLVDL<3:0> = 1001 3.42 3.50 3.59 V HLVDL<3:0> = 1010 3.61 3.70 3.79 V HLVDL<3:0> = 1011 3.82 3.91 4.10 V HLVDL<3:0> = 1100 4.06 4.16 4.26 V HLVDL<3:0> = 1101 4.33 4.44 4.55 V HLVDL<3:0> = 1110 4.64 4.75 4.87 V  2010-2017 Microchip Technology Inc. DS30009977G-page 557

PIC18F66K80 FAMILY FIGURE 31-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TxCKI 40 41 42 SOSCO/SCLKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure31-3 for load conditions. TABLE 31-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T1CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 46 TT1L T1CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 47 TT1P T1CKI Input Synchronous Greater of: — ns N = prescale Period 20ns or value (TCY + 40)/N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T1CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T1CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment DS30009977G-page 558  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 31-10: CAPTURE/COMPARE/PWM TIMINGS (ECCP1, ECCP2 MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure31-3 for load conditions. TABLE 31-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP1, ECCP2 MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With prescaler 10 — ns 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With prescaler 10 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns  2010-2017 Microchip Technology Inc. DS30009977G-page 559

PIC18F66K80 FAMILY FIGURE 31-11: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SCK (CKPx = 0) 78 79 SCK (CKPx = 1) 79 78 80 SDO MSb bit 6 - - - - - - 1 LSb 75, 76 SDI MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure31-3 for load conditions. TABLE 31-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns of Byte 2 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time — 25 ns 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time (Master mode) — 25 ns 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge — 50 ns TSCL2DOV DS30009977G-page 560  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 31-12: EXAMPLE SPI MASTER MODE TIMING (CKE=1) 81 SCK (CKPx = 0) 79 73 SCK (CKPx = 1) 80 78 SDO MSb bit 6 - - - - - - 1 LSb 75, 76 SDI MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure31-3 for load conditions. TABLE 31-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns of Byte 2 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time — 25 ns 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time (Master mode) — 25 ns 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge — 50 ns TSCL2DOV 81 TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — ns TDOV2SCL  2010-2017 Microchip Technology Inc. DS30009977G-page 561

PIC18F66K80 FAMILY FIGURE 31-13: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKPx = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - - 1 LSb 75, 76 77 SDI MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure31-3 for load conditions. TABLE 31-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SS to write to SSPBUF 3 TCY — ns 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time — 25 ns 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS  to SDO Output High-impedance 10 50 ns 78 TSCR SCK Output Rise Time (Master mode) — 25 ns 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge — 50 ns TSCL2DOV 83 TSCH2SSH, SS  after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter 73A. 2: Only if Parameter 71A and 72A are used. DS30009977G-page 562  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 31-14: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKPx = 0) 71 72 SCK (CKPx = 1) 80 SDO MSb bit 6 - - - - - - 1 LSb 75, 76 77 SDI MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure31-3 for load conditions. TABLE 31-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input 3 TCY — ns TSSL2SCL 70A TSSL2WB SS to write to SSPBUF 3 TCY — ns 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time — 25 ns 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS  to SDO Output High-Impedance 10 50 ns 78 TSCR SCK Output Rise Time (Master mode) — 25 ns 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge — 50 ns TSCL2DOV 82 TSSL2DOV SDO Data Output Valid after SS  Edge — 50 ns 83 TSCH2SSH, SS  after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter 73A. 2: Only if Parameter 71A and 72A are used.  2010-2017 Microchip Technology Inc. DS30009977G-page 563

PIC18F66K80 FAMILY FIGURE 31-15: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure31-3 for load conditions. TABLE 31-19: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — DS30009977G-page 564  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY FIGURE 31-16: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure31-3 for load conditions. TABLE 31-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s MSSP module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s MSSP module 1.5 TCY — 102 TR SDA and SCL Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock 400 kHz mode 0.6 — s pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before 400 kHz mode 1.3 — s a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCL line is released.  2010-2017 Microchip Technology Inc. DS30009977G-page 565

PIC18F66K80 FAMILY FIGURE 31-17: MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure31-3 for load conditions. TABLE 31-21: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. FIGURE 31-18: MSSP I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure31-3 for load conditions. DS30009977G-page 566  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 31-22: MSSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High 100 kHz mode 2(TOSC)(BRG + 1) — — Time 400 kHz mode 2(TOSC)(BRG + 1) — — 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — — 400 kHz mode 2(TOSC)(BRG + 1) — — 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — — Only relevant for Repeated Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — — Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — — After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — — clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 106 THD:DAT Data Input 100 kHz mode 0 — — Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) — s ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) — — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — — Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — — 1 MHz mode(1) 2(TOSC)(BRG + 1) — — 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start 1 MHz mode(1) — — s D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but Parameter #107250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, Parameter #102 + Parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released.  2010-2017 Microchip Technology Inc. DS30009977G-page 567

PIC18F66K80 FAMILY FIGURE 31-19: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 122 Note: Refer to Figure31-3 for load conditions. TABLE 31-23: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns 122 TDTRF Data Out Rise Time and Fall Time — 20 ns FIGURE 31-20: EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TXx/CKx pin 125 RXx/DTx pin 126 Note: Refer to Figure31-3 for load conditions. TABLE 31-24: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx  (DTx hold time) 10 — ns 126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns DS30009977G-page 568  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY TABLE 31-25: A/D CONVERTER CHARACTERISTICS: PIC18F66K80 FAMILY (INDUSTRIAL/EXTENDED) Param Sym Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 12 bit VREF  5.0V A03 EIL Integral Linearity Error — — ±6.0 LSB VREF  5.0V A04 EDL Differential Linearity Error — ±1 +3.0/-1.0 LSB VREF  5.0V A06 EOFF Offset Error — ±1 ±9 LSB VREF  5.0V A07 EGN Gain Error — <±1 ±8.00 LSB VREF  5.0V A10 — Monotonicity Guaranteed(1) — VSS  VAIN  VREF A20 VREF Reference Voltage Range 3 — VDD – VSS V For 12-bit resolution (VREFH – VREFL) A21 VREFH Reference Voltage High AVSS + 3.0V — AVDD + 0.3V V For 12-bit resolution A22 VREFL Reference Voltage Low AVSS – 0.3V — AVDD – 3.0V V For 12-bit resolution A25 VAIN Analog Input Voltage VREFL — VREFH V A28 AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V A29 AVSS Analog Supply Voltage VSS – 0.3 — VSS + 0.3 V A30 ZAIN Recommended — — 2.5 k Impedance of Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 A During VAIN acquisition. — — 150 A During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage. 2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.  2010-2017 Microchip Technology Inc. DS30009977G-page 569

PIC18F66K80 FAMILY FIGURE 31-21: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 A/D DATA 11 10 9 . . . . . . 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY (Note 1) GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 31-26: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period 0.8 12.5(1) s TOSC based, VREF  3.0V 1.4 25(1) s VDD = 3.0V; TOSC based, VREF full range — 1 s A/D RC mode — 3 s VDD = 3.0V; A/D RC mode 131 TCNV Conversion Time 14 15 TAD (not including acquisition time)(2) 132 TACQ Acquisition Time(3) 1.4 — s -40°C to +125°C 135 TSWC Switching Time from Convert  Sample — (Note 4) TBD TDIS Discharge Time 0.2 — s -40°C to +125°C Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. 4: On the following cycle of the device clock. DS30009977G-page 570  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 28-Lead QFN Example XXXXXXXX 18F25K80 XXXXXXXX /MM e3 YYWWNNN 1010017 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F26K80/SOe3 XXXXXXXXXXXXXXXXXXXX 1010017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC18F26K80-I/SPe3 XXXXXXXXXXXXXXXXX 1010017 YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX PIC18F26K80 XXXXXXXXXXXX -I/SS e3 YYWWNNN 1010017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2017 Microchip Technology Inc. DS30009977G-page 571

PIC18F66K80 FAMILY 32.1 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC18F45K80-I/Pe3 XXXXXXXXXXXXXXXXXX 1010017 XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead QFN Example XXXXXXXXXX 18F45K80 XXXXXXXXXX -I/MLe3 XXXXXXXXXX 1010017 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX 18F45K80 XXXXXXXXXX -I/PTe3Example XXXXXXXXXX 1010017 YYWWNNN 64-Lead QFN XXXXXXXXXX 18F65K80 XXXXXXXXXX -I/MRe3 XXXXXXXXXX 1010017 YYWWNNN 64-Lead TQFP Example XXXXXXXXXX 18F65K80 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 1010017 YYWWNNN DS30009977G-page 572  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY 32.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)(cid:19)(cid:9)(cid:20)(cid:21)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:22)(cid:7)(cid:23)(cid:6)(cid:9)(cid:24)(cid:25)(cid:25)(cid:26)(cid:9)(cid:27)(cid:9)(cid:28)(cid:29)(cid:28)(cid:29)(cid:30)(cid:31) (cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$(cid:16)(cid:18)(cid:20)(cid:4)%& ’(cid:14)(cid:13)((cid:9)(cid:30)(cid:31))(cid:30)(cid:9)!!(cid:9)*(cid:21)+(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)+(cid:23)(cid:13)( (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D D2 EXPOSED PAD e E2 E b 2 2 1 1 K N N L TOPVIEW NOTE1 BOTTOMVIEW A A3 A1 4(cid:25)(cid:19)% (cid:18)(cid:28)55(cid:28)(cid:18),(cid:24),(cid:8)(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)(cid:30)(cid:19)(cid:25) 6 (cid:16)9 (cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:4)(cid:29):.(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)% (cid:7) (cid:4)(cid:29)9(cid:4) (cid:4)(cid:29)(cid:6)(cid:4) (cid:15)(cid:29)(cid:4)(cid:4) (cid:3)%(cid:11)(cid:25)"(cid:22)$$(cid:14) (cid:7)(cid:15) (cid:4)(cid:29)(cid:4)(cid:4) (cid:4)(cid:29)(cid:4)(cid:16) (cid:4)(cid:29)(cid:4). 0(cid:22)(cid:25)%(cid:11)(cid:20)%(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)+ (cid:4)(cid:29)(cid:16)(cid:4)(cid:14)(cid:8),2 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)<(cid:19)"%(cid:23) , :(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 ,#(cid:10)(cid:22) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ,(cid:16) +(cid:29):. +(cid:29)(cid:17)(cid:4) (cid:5)(cid:29)(cid:17)(cid:4) 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) :(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 ,#(cid:10)(cid:22) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2)(cid:16) +(cid:29):. +(cid:29)(cid:17)(cid:4) (cid:5)(cid:29)(cid:17)(cid:4) 0(cid:22)(cid:25)%(cid:11)(cid:20)%(cid:14)<(cid:19)"%(cid:23) ( (cid:4)(cid:29)(cid:16)+ (cid:4)(cid:29)+9 (cid:4)(cid:29)(cid:5)+ 0(cid:22)(cid:25)%(cid:11)(cid:20)%(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) 5 (cid:4)(cid:29)+(cid:4) (cid:4)(cid:29)(cid:5)(cid:4) (cid:4)(cid:29).(cid:4) 0(cid:22)(cid:25)%(cid:11)(cid:20)%(cid:9)%(cid:22)(cid:9),#(cid:10)(cid:22) (cid:13)"(cid:14)(cid:30)(cid:11)" = (cid:4)(cid:29)(cid:16)(cid:4) > > (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:19) (cid:14) (cid:11))(cid:14) (cid:19)(cid:25)(cid:12)!(cid:26)(cid:11)%(cid:13)"(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)’(cid:14)! !(cid:11)(cid:26)(cid:26)(cid:27)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)’(cid:14)$(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)$(cid:22)(cid:21)&(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:15)(cid:16)(cid:5)/  2010-2017 Microchip Technology Inc. DS30009977G-page 573

PIC18F66K80 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)(cid:19)(cid:9)(cid:20)(cid:21)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:22)(cid:7)(cid:23)(cid:6)(cid:9)(cid:24)(cid:25)(cid:25)(cid:26)(cid:9)(cid:27)(cid:9)(cid:28)(cid:29)(cid:28)(cid:29)(cid:30)(cid:31) (cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$(cid:16)(cid:18)(cid:20)(cid:4)%& ’(cid:14)(cid:13)((cid:9)(cid:30)(cid:31))(cid:30)(cid:9)!!(cid:9)*(cid:21)+(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)+(cid:23)(cid:13)( (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) DS30009977G-page 574  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)%!(cid:7)(cid:11)(cid:11)(cid:9)-(cid:17)(cid:13)(cid:11)(cid:14)+(cid:6)(cid:9)(cid:24)%-(cid:26)(cid:9)(cid:27)(cid:9).(cid:14)(cid:8)(cid:6)(cid:19)(cid:9)/(cid:31)0(cid:30)(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$%-1*& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D N E E1 NOTE1 1 2 3 e b h α h φ c A A2 L A1 L1 β 4(cid:25)(cid:19)% (cid:18)(cid:28)55(cid:28)(cid:18),(cid:24),(cid:8)(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)(cid:30)(cid:19)(cid:25) 6 (cid:16)9 (cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:15)(cid:29)(cid:16)(cid:17)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)% (cid:7) > > (cid:16)(cid:29):. (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)(cid:16) (cid:16)(cid:29)(cid:4). > > (cid:3)%(cid:11)(cid:25)"(cid:22)$$(cid:14)(cid:14)? (cid:7)(cid:15) (cid:4)(cid:29)(cid:15)(cid:4) > (cid:4)(cid:29)+(cid:4) 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)<(cid:19)"%(cid:23) , (cid:15)(cid:4)(cid:29)+(cid:4)(cid:14)/(cid:3)0 (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)"%(cid:23) ,(cid:15) (cid:17)(cid:29).(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) (cid:15)(cid:17)(cid:29)(cid:6)(cid:4)(cid:14)/(cid:3)0 0(cid:23)(cid:11)&$(cid:13)(cid:21)(cid:14)@(cid:22)(cid:10)%(cid:19)(cid:22)(cid:25)(cid:11)(cid:26)A (cid:23) (cid:4)(cid:29)(cid:16). > (cid:4)(cid:29)(cid:17). 2(cid:22)(cid:22)%(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) 5 (cid:4)(cid:29)(cid:5)(cid:4) > (cid:15)(cid:29)(cid:16)(cid:17) 2(cid:22)(cid:22)%(cid:10)(cid:21)(cid:19)(cid:25)% 5(cid:15) (cid:15)(cid:29)(cid:5)(cid:4)(cid:14)(cid:8),2 2(cid:22)(cid:22)%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)(cid:24)(cid:22)(cid:10) (cid:3) (cid:4)B > 9B 5(cid:13)(cid:11)"(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:20) (cid:4)(cid:29)(cid:15)9 > (cid:4)(cid:29)++ 5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ( (cid:4)(cid:29)+(cid:15) > (cid:4)(cid:29).(cid:15) (cid:18)(cid:22)(cid:26)"(cid:14)(cid:2)(cid:21)(cid:11)$%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)(cid:24)(cid:22)(cid:10) (cid:4) .B > (cid:15).B (cid:18)(cid:22)(cid:26)"(cid:14)(cid:2)(cid:21)(cid:11)$%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)/(cid:22)%%(cid:22)& (cid:5) .B > (cid:15).B (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) ?(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)$(cid:19)(cid:20)(cid:11)(cid:25)%(cid:14)0(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)%(cid:13)(cid:21)(cid:19) %(cid:19)(cid:20)(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25) (cid:14)(cid:2)(cid:14)(cid:11)(cid:25)"(cid:14),(cid:15)(cid:14)"(cid:22)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)!"(cid:13)(cid:14)&(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:29)(cid:14)(cid:18)(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:14) (cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:13)#(cid:20)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:29)(cid:15).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)"(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)’(cid:14)! !(cid:11)(cid:26)(cid:26)(cid:27)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)’(cid:14)$(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)$(cid:22)(cid:21)&(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4).(cid:16)/  2010-2017 Microchip Technology Inc. DS30009977G-page 575

PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009977G-page 576  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)%(cid:22)(cid:14)++#(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)2(cid:17)(cid:7)(cid:11)(cid:9)1+(cid:4)(cid:5)(cid:14)+(cid:6)(cid:9)(cid:24)%(cid:10)(cid:26)(cid:9)(cid:27)(cid:9)3(cid:30)(cid:30)(cid:9)!(cid:14)(cid:11)(cid:9)"(cid:21)(cid:8)#(cid:9)$%(cid:10)21(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 4(cid:25)(cid:19)% (cid:28)60;,(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)(cid:30)(cid:19)(cid:25) 6 (cid:16)9 (cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:29)(cid:15)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:24)(cid:22)(cid:10)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7) > > (cid:29)(cid:16)(cid:4)(cid:4) (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)(cid:16) (cid:29)(cid:15)(cid:16)(cid:4) (cid:29)(cid:15)+. (cid:29)(cid:15).(cid:4) /(cid:11) (cid:13)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7)(cid:15) (cid:29)(cid:4)(cid:15). > > (cid:3)(cid:23)(cid:22)!(cid:26)"(cid:13)(cid:21)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:23)(cid:22)!(cid:26)"(cid:13)(cid:21)(cid:14)<(cid:19)"%(cid:23) , (cid:29)(cid:16)(cid:6)(cid:4) (cid:29)+(cid:15)(cid:4) (cid:29)++. (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)"%(cid:23) ,(cid:15) (cid:29)(cid:16)(cid:5)(cid:4) (cid:29)(cid:16)9. (cid:29)(cid:16)(cid:6). 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) (cid:15)(cid:29)+(cid:5). (cid:15)(cid:29)+:. (cid:15)(cid:29)(cid:5)(cid:4)(cid:4) (cid:24)(cid:19)(cid:10)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) 5 (cid:29)(cid:15)(cid:15)(cid:4) (cid:29)(cid:15)+(cid:4) (cid:29)(cid:15).(cid:4) 5(cid:13)(cid:11)"(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:20) (cid:29)(cid:4)(cid:4)9 (cid:29)(cid:4)(cid:15)(cid:4) (cid:29)(cid:4)(cid:15). 4(cid:10)(cid:10)(cid:13)(cid:21)(cid:14)5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ((cid:15) (cid:29)(cid:4)(cid:5)(cid:4) (cid:29)(cid:4).(cid:4) (cid:29)(cid:4)(cid:17)(cid:4) 5(cid:22))(cid:13)(cid:21)(cid:14)5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ( (cid:29)(cid:4)(cid:15)(cid:5) (cid:29)(cid:4)(cid:15)9 (cid:29)(cid:4)(cid:16)(cid:16) 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)(cid:8)(cid:22))(cid:14)(cid:3)(cid:10)(cid:11)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:14)? (cid:13)/ > > (cid:29)(cid:5)+(cid:4) (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) ?(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)$(cid:19)(cid:20)(cid:11)(cid:25)%(cid:14)0(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)%(cid:13)(cid:21)(cid:19) %(cid:19)(cid:20)(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25) (cid:14)(cid:2)(cid:14)(cid:11)(cid:25)"(cid:14),(cid:15)(cid:14)"(cid:22)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)!"(cid:13)(cid:14)&(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:29)(cid:14)(cid:18)(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:14) (cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:13)#(cid:20)(cid:13)(cid:13)"(cid:14)(cid:29)(cid:4)(cid:15)(cid:4)C(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)"(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:17)(cid:4)/  2010-2017 Microchip Technology Inc. DS30009977G-page 577

PIC18F66K80 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)%(4(cid:14)+(cid:22)(cid:9)%!(cid:7)(cid:11)(cid:11)(cid:9)-(cid:17)(cid:13)(cid:11)(cid:14)+(cid:6)(cid:9)(cid:24)%%(cid:26)(cid:9)(cid:27)(cid:9)0(cid:31)3(cid:30)(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$%%-(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 4(cid:25)(cid:19)% (cid:18)(cid:28)55(cid:28)(cid:18),(cid:24),(cid:8)(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)(cid:30)(cid:19)(cid:25) 6 (cid:16)9 (cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:4)(cid:29):.(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)% (cid:7) > > (cid:16)(cid:29)(cid:4)(cid:4) (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)(cid:16) (cid:15)(cid:29):. (cid:15)(cid:29)(cid:17). (cid:15)(cid:29)9. (cid:3)%(cid:11)(cid:25)"(cid:22)$$(cid:14) (cid:7)(cid:15) (cid:4)(cid:29)(cid:4). > > 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)<(cid:19)"%(cid:23) , (cid:17)(cid:29)(cid:5)(cid:4) (cid:17)(cid:29)9(cid:4) 9(cid:29)(cid:16)(cid:4) (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)"%(cid:23) ,(cid:15) .(cid:29)(cid:4)(cid:4) .(cid:29)+(cid:4) .(cid:29):(cid:4) 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) (cid:6)(cid:29)(cid:6)(cid:4) (cid:15)(cid:4)(cid:29)(cid:16)(cid:4) (cid:15)(cid:4)(cid:29).(cid:4) 2(cid:22)(cid:22)%(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) 5 (cid:4)(cid:29).. (cid:4)(cid:29)(cid:17). (cid:4)(cid:29)(cid:6). 2(cid:22)(cid:22)%(cid:10)(cid:21)(cid:19)(cid:25)% 5(cid:15) (cid:15)(cid:29)(cid:16).(cid:14)(cid:8),2 5(cid:13)(cid:11)"(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:20) (cid:4)(cid:29)(cid:4)(cid:6) > (cid:4)(cid:29)(cid:16). 2(cid:22)(cid:22)%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13) (cid:3) (cid:4)B (cid:5)B 9B 5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ( (cid:4)(cid:29)(cid:16)(cid:16) > (cid:4)(cid:29)+9 (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25) (cid:14)(cid:2)(cid:14)(cid:11)(cid:25)"(cid:14),(cid:15)(cid:14)"(cid:22)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)!"(cid:13)(cid:14)&(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:29)(cid:14)(cid:18)(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:14) (cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:13)#(cid:20)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:29)(cid:16)(cid:4)(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)"(cid:13)(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)’(cid:14)! !(cid:11)(cid:26)(cid:26)(cid:27)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)’(cid:14)$(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)$(cid:22)(cid:21)&(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:17)+/ DS30009977G-page 578  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2017 Microchip Technology Inc. DS30009977G-page 579

PIC18F66K80 FAMILY )(cid:30)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)2(cid:17)(cid:7)(cid:11)(cid:9)1+(cid:4)(cid:5)(cid:14)+(cid:6)(cid:9)(cid:24)(cid:10)(cid:26)(cid:9)(cid:27)(cid:9)(cid:28)(cid:30)(cid:30)(cid:9)!(cid:14)(cid:11)(cid:9)"(cid:21)(cid:8)#(cid:9)$(cid:10)21(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 4(cid:25)(cid:19)% (cid:28)60;,(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)(cid:30)(cid:19)(cid:25) 6 (cid:5)(cid:4) (cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:29)(cid:15)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:24)(cid:22)(cid:10)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7) > > (cid:29)(cid:16).(cid:4) (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)(cid:16) (cid:29)(cid:15)(cid:16). > (cid:29)(cid:15)(cid:6). /(cid:11) (cid:13)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7)(cid:15) (cid:29)(cid:4)(cid:15). > > (cid:3)(cid:23)(cid:22)!(cid:26)"(cid:13)(cid:21)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:23)(cid:22)!(cid:26)"(cid:13)(cid:21)(cid:14)<(cid:19)"%(cid:23) , (cid:29).(cid:6)(cid:4) > (cid:29):(cid:16). (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)"%(cid:23) ,(cid:15) (cid:29)(cid:5)9. > (cid:29).9(cid:4) 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) (cid:15)(cid:29)(cid:6)9(cid:4) > (cid:16)(cid:29)(cid:4)(cid:6). (cid:24)(cid:19)(cid:10)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) 5 (cid:29)(cid:15)(cid:15). > (cid:29)(cid:16)(cid:4)(cid:4) 5(cid:13)(cid:11)"(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:20) (cid:29)(cid:4)(cid:4)9 > (cid:29)(cid:4)(cid:15). 4(cid:10)(cid:10)(cid:13)(cid:21)(cid:14)5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ((cid:15) (cid:29)(cid:4)+(cid:4) > (cid:29)(cid:4)(cid:17)(cid:4) 5(cid:22))(cid:13)(cid:21)(cid:14)5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ( (cid:29)(cid:4)(cid:15)(cid:5) > (cid:29)(cid:4)(cid:16)+ 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)(cid:8)(cid:22))(cid:14)(cid:3)(cid:10)(cid:11)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:14)? (cid:13)/ > > (cid:29)(cid:17)(cid:4)(cid:4) (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) ?(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)$(cid:19)(cid:20)(cid:11)(cid:25)%(cid:14)0(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)%(cid:13)(cid:21)(cid:19) %(cid:19)(cid:20)(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25) (cid:14)(cid:2)(cid:14)(cid:11)(cid:25)"(cid:14),(cid:15)(cid:14)"(cid:22)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)!"(cid:13)(cid:14)&(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:29)(cid:14)(cid:18)(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:14) (cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:13)#(cid:20)(cid:13)(cid:13)"(cid:14)(cid:29)(cid:4)(cid:15)(cid:4)C(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)"(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:15):/ DS30009977G-page 580  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY ))(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)(cid:19)(cid:9)(cid:20)(cid:21)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:22)(cid:7)(cid:23)(cid:6)(cid:9)(cid:24)(cid:25)(cid:5)(cid:26)(cid:9)(cid:27)(cid:9)(cid:3)(cid:29)(cid:3)(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$(cid:16)(cid:18)(cid:20)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 4(cid:25)(cid:19)% (cid:18)(cid:28)55(cid:28)(cid:18),(cid:24),(cid:8)(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)(cid:30)(cid:19)(cid:25) 6 (cid:5)(cid:5) (cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:4)(cid:29):.(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)% (cid:7) (cid:4)(cid:29)9(cid:4) (cid:4)(cid:29)(cid:6)(cid:4) (cid:15)(cid:29)(cid:4)(cid:4) (cid:3)%(cid:11)(cid:25)"(cid:22)$$(cid:14) (cid:7)(cid:15) (cid:4)(cid:29)(cid:4)(cid:4) (cid:4)(cid:29)(cid:4)(cid:16) (cid:4)(cid:29)(cid:4). 0(cid:22)(cid:25)%(cid:11)(cid:20)%(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)+ (cid:4)(cid:29)(cid:16)(cid:4)(cid:14)(cid:8),2 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)<(cid:19)"%(cid:23) , 9(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 ,#(cid:10)(cid:22) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ,(cid:16) :(cid:29)+(cid:4) :(cid:29)(cid:5). :(cid:29)9(cid:4) 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) 9(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 ,#(cid:10)(cid:22) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2)(cid:16) :(cid:29)+(cid:4) :(cid:29)(cid:5). :(cid:29)9(cid:4) 0(cid:22)(cid:25)%(cid:11)(cid:20)%(cid:14)<(cid:19)"%(cid:23) ( (cid:4)(cid:29)(cid:16). (cid:4)(cid:29)+(cid:4) (cid:4)(cid:29)+9 0(cid:22)(cid:25)%(cid:11)(cid:20)%(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) 5 (cid:4)(cid:29)+(cid:4) (cid:4)(cid:29)(cid:5)(cid:4) (cid:4)(cid:29).(cid:4) 0(cid:22)(cid:25)%(cid:11)(cid:20)%(cid:9)%(cid:22)(cid:9),#(cid:10)(cid:22) (cid:13)"(cid:14)(cid:30)(cid:11)" = (cid:4)(cid:29)(cid:16)(cid:4) > > (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:19) (cid:14) (cid:11))(cid:14) (cid:19)(cid:25)(cid:12)!(cid:26)(cid:11)%(cid:13)"(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)’(cid:14)! !(cid:11)(cid:26)(cid:26)(cid:27)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)’(cid:14)$(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)$(cid:22)(cid:21)&(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:15)(cid:4)+/  2010-2017 Microchip Technology Inc. DS30009977G-page 581

PIC18F66K80 FAMILY ))(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)(cid:19)(cid:9)(cid:20)(cid:21)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:22)(cid:7)(cid:23)(cid:6)(cid:9)(cid:24)(cid:25)(cid:5)(cid:26)(cid:9)(cid:27)(cid:9)(cid:3)(cid:29)(cid:3)(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$(cid:16)(cid:18)(cid:20)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) DS30009977G-page 582  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY ))(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)5((cid:14)+(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)6(cid:7)(cid:15)(cid:22)(cid:9)(cid:24)(cid:10)5(cid:26)(cid:9)(cid:27)(cid:9)7(cid:30)(cid:29)7(cid:30)(cid:29)7(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:19)(cid:9)(cid:2)(cid:31)(cid:30)(cid:30)(cid:9)!!(cid:9)$5(cid:16)(cid:18)(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 4(cid:25)(cid:19)% (cid:18)(cid:28)55(cid:28)(cid:18),(cid:24),(cid:8)(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)5(cid:13)(cid:11)" 6 (cid:5)(cid:5) 5(cid:13)(cid:11)"(cid:14)(cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:4)(cid:29)9(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)% (cid:7) > > (cid:15)(cid:29)(cid:16)(cid:4) (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)(cid:16) (cid:4)(cid:29)(cid:6). (cid:15)(cid:29)(cid:4)(cid:4) (cid:15)(cid:29)(cid:4). (cid:3)%(cid:11)(cid:25)"(cid:22)$$(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:29)(cid:4). > (cid:4)(cid:29)(cid:15). 2(cid:22)(cid:22)%(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) 5 (cid:4)(cid:29)(cid:5). (cid:4)(cid:29):(cid:4) (cid:4)(cid:29)(cid:17). 2(cid:22)(cid:22)%(cid:10)(cid:21)(cid:19)(cid:25)% 5(cid:15) (cid:15)(cid:29)(cid:4)(cid:4)(cid:14)(cid:8),2 2(cid:22)(cid:22)%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13) (cid:3) (cid:4)B +(cid:29).B (cid:17)B 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)<(cid:19)"%(cid:23) , (cid:15)(cid:16)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) (cid:15)(cid:16)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)"%(cid:23) ,(cid:15) (cid:15)(cid:4)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2)(cid:15) (cid:15)(cid:4)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 5(cid:13)(cid:11)"(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:20) (cid:4)(cid:29)(cid:4)(cid:6) > (cid:4)(cid:29)(cid:16)(cid:4) 5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ( (cid:4)(cid:29)+(cid:4) (cid:4)(cid:29)+(cid:17) (cid:4)(cid:29)(cid:5). (cid:18)(cid:22)(cid:26)"(cid:14)(cid:2)(cid:21)(cid:11)$%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)(cid:24)(cid:22)(cid:10) (cid:4) (cid:15)(cid:15)B (cid:15)(cid:16)B (cid:15)+B (cid:18)(cid:22)(cid:26)"(cid:14)(cid:2)(cid:21)(cid:11)$%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)/(cid:22)%%(cid:22)& (cid:5) (cid:15)(cid:15)B (cid:15)(cid:16)B (cid:15)+B (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) 0(cid:23)(cid:11)&$(cid:13)(cid:21) (cid:14)(cid:11)%(cid:14)(cid:20)(cid:22)(cid:21)(cid:25)(cid:13)(cid:21) (cid:14)(cid:11)(cid:21)(cid:13)(cid:14)(cid:22)(cid:10)%(cid:19)(cid:22)(cid:25)(cid:11)(cid:26)D(cid:14) (cid:19)E(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25) (cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:25)"(cid:14),(cid:15)(cid:14)"(cid:22)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)!"(cid:13)(cid:14)&(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:29)(cid:14)(cid:18)(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:14) (cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:13)#(cid:20)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:29)(cid:16).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)"(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)’(cid:14)! !(cid:11)(cid:26)(cid:26)(cid:27)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)’(cid:14)$(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)$(cid:22)(cid:21)&(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:17):/  2010-2017 Microchip Technology Inc. DS30009977G-page 583

PIC18F66K80 FAMILY ))(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)5((cid:14)+(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)6(cid:7)(cid:15)(cid:22)(cid:9)(cid:24)(cid:10)5(cid:26)(cid:9)(cid:27)(cid:9)7(cid:30)(cid:29)7(cid:30)(cid:29)7(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:19)(cid:9)(cid:2)(cid:31)(cid:30)(cid:30)(cid:9)!!(cid:9)$5(cid:16)(cid:18)(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) DS30009977G-page 584  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2017 Microchip Technology Inc. DS30009977G-page 585

PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009977G-page 586  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2017 Microchip Technology Inc. DS30009977G-page 587

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(cid:15)(cid:29)(cid:4)(cid:4) (cid:15)(cid:29)(cid:4). (cid:3)%(cid:11)(cid:25)"(cid:22)$$(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:29)(cid:4). > (cid:4)(cid:29)(cid:15). 2(cid:22)(cid:22)%(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) 5 (cid:4)(cid:29)(cid:5). (cid:4)(cid:29):(cid:4) (cid:4)(cid:29)(cid:17). 2(cid:22)(cid:22)%(cid:10)(cid:21)(cid:19)(cid:25)% 5(cid:15) (cid:15)(cid:29)(cid:4)(cid:4)(cid:14)(cid:8),2 2(cid:22)(cid:22)%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13) (cid:3) (cid:4)B +(cid:29).B (cid:17)B 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)<(cid:19)"%(cid:23) , (cid:15)(cid:16)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) (cid:15)(cid:16)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)"%(cid:23) ,(cid:15) (cid:15)(cid:4)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2)(cid:15) (cid:15)(cid:4)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 5(cid:13)(cid:11)"(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:20) (cid:4)(cid:29)(cid:4)(cid:6) > (cid:4)(cid:29)(cid:16)(cid:4) 5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ( (cid:4)(cid:29)(cid:15)(cid:17) (cid:4)(cid:29)(cid:16)(cid:16) (cid:4)(cid:29)(cid:16)(cid:17) (cid:18)(cid:22)(cid:26)"(cid:14)(cid:2)(cid:21)(cid:11)$%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)(cid:24)(cid:22)(cid:10) (cid:4) (cid:15)(cid:15)B (cid:15)(cid:16)B (cid:15)+B (cid:18)(cid:22)(cid:26)"(cid:14)(cid:2)(cid:21)(cid:11)$%(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)/(cid:22)%%(cid:22)& (cid:5) (cid:15)(cid:15)B (cid:15)(cid:16)B (cid:15)+B (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) 0(cid:23)(cid:11)&$(cid:13)(cid:21) (cid:14)(cid:11)%(cid:14)(cid:20)(cid:22)(cid:21)(cid:25)(cid:13)(cid:21) (cid:14)(cid:11)(cid:21)(cid:13)(cid:14)(cid:22)(cid:10)%(cid:19)(cid:22)(cid:25)(cid:11)(cid:26)D(cid:14) (cid:19)E(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25) (cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:25)"(cid:14),(cid:15)(cid:14)"(cid:22)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)!"(cid:13)(cid:14)&(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:29)(cid:14)(cid:18)(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:14) (cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:13)#(cid:20)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:29)(cid:16).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)"(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)’(cid:14)! !(cid:11)(cid:26)(cid:26)(cid:27)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)’(cid:14)$(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)$(cid:22)(cid:21)&(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)9./ DS30009977G-page 588  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY (cid:28))(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)5((cid:14)+(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)6(cid:7)(cid:15)(cid:22)(cid:9)(cid:24)(cid:10)5(cid:26)(cid:9)(cid:27)(cid:9)7(cid:30)(cid:29)7(cid:30)(cid:29)7(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:19)(cid:9)(cid:2)(cid:31)(cid:30)(cid:30)(cid:9)!!(cid:9)$5(cid:16)(cid:18)(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)  2010-2017 Microchip Technology Inc. DS30009977G-page 589

PIC18F66K80 FAMILY APPENDIX A: REVISION HISTORY Revision A (August 2010) Original data sheet for PIC18F66K80 family devices. Revision B (December 2010) Changes to Section31.0 “Electrical Characteristics” and minor text edits throughout document. Revision C (January 2011) Section2.0 “Guidelines for Getting Started with PIC18FXXKXX Microcontrollers” was added to the data sheet. Changes to Section31.0 “Electrical Characteristics” for PIC18F66K80 family devices. Minor text edits throughout document. Revision D (November 2011) Preliminary conditions have been deleted from document. Revision E (February 2012) Added all Data Sheet erratas. Added Current Injection specifications to Section31.0 “Electrical Characteristics”. Revision F (February 2012) Updated the Reset value for the IOCB register. Revision G (October 2017) Updated Figure 11-2; Registers 23-1, 23-2, 27-2, 27-5 and 27-55; Sections 11.1.3 and 31.3; Tables 4-1, 31-2 and 31-25. Updated Product Identification section. Added 19.3.5: Compare Mode Interrupt Timing. Removed nanoWatt. DS30009977G-page 590  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY APPENDIX B: MIGRATION TO other families to the PIC18F66K80 without many PIC18F66K80 FAMILY changes. The differences between the device families are listed in TableB-1 and TableB-2. For more details Devices in the PIC18F66K80, PIC18F4580, on migrating to the PIC18F66K80, refer to PIC18F4680 and 18F8680 families are similar in their “PIC18FXX80 to PIC18FXXK80 Migration Guide” functions and features. Code can be migrated from the (DS39982). TABLE B-1: NOTABLE DIFFERENCES BETWEEN 28, 40 AND 44-PIN DEVICES – PIC18F66K80, PIC18F4580 AND PIC18F4680 FAMILIES Characteristic PIC18F66K80 Family PIC18F4680 Family PIC18F4580 Family Max Operating Frequency 64 MHz 40 MHz 40 MHz Max Program Memory 64 Kbytes 64 Kbytes 32 Kbytes Data Memory (bytes) 3,648 3,328 1,536 CTMU Yes No No SOSC Oscillator Options Low-power oscillator option for SOSC No options No options T1CKI Clock T1CKI can be used as a clock without No No enabling the SOSC oscillator INTOSC Up to 16 MHz Up to 8 MHz Up to 8 MHz Timers Two 8-bit, three 16-bit One 8-bit, three 16-bit One 8-bit, three 16-bit ECCP One for all devices 40 and 44-pin devices – One 40 and 44-pin devices – One 28-pin devices – None 28-pin devices – None CCP Four One One Data EEPROM (bytes) 1,024 1,024 256 WDT Prescale Options 22 16 16 5V Operation 18FXXK80 parts – 5V operation Yes Yes 18LFXXK80 parts – 3.3V operation XLP Yes No No Regulator 18FXXK80 parts – Yes No No 18LFXXK80 parts – No Low-Power BOR Yes No No A/D Converter 12-bit signed differential 10-bit 10-bit A/D Channels 28-pin devices – 8 Channels 8 Channels for 28-pin devices/ 8 Channels for 28-pin devices/ 40 and 44-pin devices – 11 Channels 11 Channels for 40 and 44-pin devices11 Channels for 40 and 44-pin devices Internal Temp Sensor Yes No No EUSART Two One One Comparators Two 28-pin devices – None 28-pin devices – None 40 and 44-pin devices – Two 40 and 44-pin devices – Two Oscillator Options 14 Nine Nine Ultra Low-Power Wake-up Yes No No (ULPW) Adjustable Slew Rate for I/O Yes No No PLL Available for all oscillator options Available only for high-speed crystal Available only for high-speed and internal oscillator crystal and internal oscillator TXM Modulator No No No  2010-2017 Microchip Technology Inc. DS30009977G-page 591

PIC18F66K80 FAMILY TABLE B-2: NOTABLE DIFFERENCES BETWEEN 64-PIN DEVICES – PIC18F66K80 AND PIC18F8680 FAMILIES Characteristic PIC18F66K80 Family PIC18F8680 Family Max Operating Frequency 64 MHz 40 MHz Max Program Memory 64K 64K Data Memory (bytes) 3,648 3,328 CTMU Yes No SOSC Oscillator Options Low-power oscillator option for SOSC No options T1CKI Clock T1CKI can be used as a clock without No enabling the SOSC oscillator INTOSC Up to 16 MHz No Internal Oscillator SPI/I2C™ 1 Module 1 Module Timers Two 8-bit, Three 16-bit Two 8-bit, Three 16-bit ECCP 1 1 CCP 4 1 Data EEPROM (bytes) 1,024 1,024 WDT Prescale Options 22 16 5V Operation 18FXXK80 parts – 5V operation Yes 18LFXXK80 parts – 3.3V operation XLP Yes No On-Chip 3.3V Regulator 18FXXK80 parts – Yes No 18LFXXK80 parts – No Low-Power BOR Yes No A/D Converter 12-bit signed differential 10-bit A/D Channels 15 Channels 12 Channels Internal Temp Sensor Yes No EUSART Two One Comparators Two Two Oscillator Options 14 Seven Ultra Low-Power Wake-up (ULPW) Yes No Adjustable Slew Rate for I/O Yes No PLL Available for all oscillator options Available for only high-speed crystal and external oscillator Data Signal Modulator Yes No DS30009977G-page 592  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2010-2017 Microchip Technology Inc. DS30009977G-page 593

PIC18F66K80 FAMILY NOTES: DS30009977G-page 594  2010-2017 Microchip Technology Inc.

PIC18F66K80 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, such as pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18F66K80-I/MR 301 = Industrial temp., Range QFN package, Extended VDD limits, QTP pattern #301. b) PIC18F66K80-I/PT = Industrial temp., TQFP package, Extended VDD limits. Device(1,2) PIC18F25K80, PIC18F26K80, PIC18F45K80, PIC18F46K80, PIC18F65K80, PIC18F66K80 VDD range 1.8V to 5V PIC18LF25K80, PIC18LF26K80, PIC18LF45K80, PIC18LF46K80, PIC18F65K80, PIC18F66K80 VDD range 1.8V to 3.6V Temperature Range I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package P = PDIP Plastic Dual In-Line Note1: F = Standard Voltage Range ML = QFN Plastic Quad Flat, No Lead Package LF = Low Voltage Range MM = 28-pin QFN Plastic Quad Flat, No Lead Package 2: T = in tape and reel, TQFP MR = 64-pin QFN Plastic Quad Flat, No Lead Package packages only. SO = SOIC Plastic Small Outline SP = SPDIP Skinny Plastic Dual In-Line SS = SSOP Plastic Shrink Small Outline PT = TQFP Plastic Thin Quad Flatpack Pattern a) QTP, SQTP, Code or Special Requirements (blank otherwise)  2010-2017 Microchip Technology Inc. DS30009977G-page 595

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT ensure that your application meets with your specifications. logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, MICROCHIP MAKES NO REPRESENTATIONS OR Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK WARRANTIES OF ANY KIND WHETHER EXPRESS OR MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST IMPLIED, WRITTEN OR ORAL, STATUTORY OR logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 OTHERWISE, RELATED TO THE INFORMATION, logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are QUALITY, PERFORMANCE, MERCHANTABILITY OR registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Microchip Tempe, Arizona; Gresham, Oregon and design centers in California Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademark of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip Technology analog products. In addition, Microchip’s quality system for the design Inc., in other countries. and manufacture of development systems is ISO 9001:2000 certified. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2010-2017, Microchip Technology Incorporated, All Rights Reserved. CERTIFIED BY DNV ISBN: 978-1-5224-2330-0 == ISO/TS 16949 == DS30009977G-page 596  2010-2017 Microchip Technology Inc.

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office China - Xiamen Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 86-592-2388138 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 86-592-2388130 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon China - Zhuhai Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 86-756-3210040 Tel: 45-4450-2828 Technical Support: Tel: 852-2943-5100 Fax: 86-756-3210049 Fax: 45-4485-2829 http://www.microchip.com/ Fax: 852-2401-3431 India - Bangalore Finland - Espoo support Australia - Sydney Tel: 91-80-3090-4444 Tel: 358-9-4520-820 Web Address: Tel: 61-2-9868-6733 Fax: 91-80-3090-4123 www.microchip.com France - Paris Fax: 61-2-9868-6755 India - New Delhi Tel: 33-1-69-53-63-20 Atlanta China - Beijing Tel: 91-11-4160-8631 Fax: 33-1-69-30-90-79 Duluth, GA Tel: 86-10-8569-7000 Fax: 91-11-4160-8632 Tel: 678-957-9614 Germany - Garching Fax: 678-957-1455 Fax: 86-10-8528-2104 India - Pune Tel: 49-8931-9700 China - Chengdu Tel: 91-20-3019-1500 Germany - Haan Austin, TX Tel: 86-28-8665-5511 Tel: 49-2129-3766400 Tel: 512-257-3370 Japan - Osaka Fax: 86-28-8665-7889 Tel: 81-6-6152-7160 Germany - Heilbronn Boston China - Chongqing Fax: 81-6-6152-9310 Tel: 49-7131-67-3636 Westborough, MA Tel: 86-23-8980-9588 Tel: 774-760-0087 Japan - Tokyo Germany - Karlsruhe Fax: 86-23-8980-9500 Tel: 81-3-6880- 3770 Tel: 49-721-625370 Fax: 774-760-0088 China - Dongguan Fax: 81-3-6880-3771 Germany - Munich CItahsiccaa,g IoL Tel: 86-769-8702-9880 Korea - Daegu Tel: 49-89-627-144-0 Tel: 630-285-0071 China - Guangzhou Tel: 82-53-744-4301 Fax: 49-89-627-144-44 Tel: 86-20-8755-8029 Fax: 82-53-744-4302 Fax: 630-285-0075 Germany - Rosenheim China - Hangzhou Korea - Seoul Tel: 49-8031-354-560 Dallas Tel: 86-571-8792-8115 Tel: 82-2-554-7200 Addison, TX Israel - Ra’anana Tel: 972-818-7423 Fax: 86-571-8792-8116 Fax: 82-2-558-5932 or Tel: 972-9-744-7705 82-2-558-5934 Fax: 972-818-2924 China - Hong Kong SAR Italy - Milan Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 39-0331-742611 Detroit Novi, MI Fax: 852-2401-3431 Tel: 60-3-6201-9857 Fax: 39-0331-466781 Fax: 60-3-6201-9859 Tel: 248-848-4000 China - Nanjing Italy - Padova Tel: 86-25-8473-2460 Malaysia - Penang Tel: 39-049-7625286 Houston, TX Fax: 86-25-8473-2470 Tel: 60-4-227-8870 Tel: 281-894-5983 Netherlands - Drunen Fax: 60-4-227-4068 China - Qingdao Tel: 31-416-690399 Indianapolis Noblesville, IN Tel: 86-532-8502-7355 Philippines - Manila Fax: 31-416-690340 Fax: 86-532-8502-7205 Tel: 63-2-634-9065 Tel: 317-773-8323 Norway - Trondheim Fax: 63-2-634-9069 Fax: 317-773-5453 China - Shanghai Tel: 47-7289-7561 Tel: 317-536-2380 Tel: 86-21-3326-8000 Singapore Poland - Warsaw Fax: 86-21-3326-8021 Tel: 65-6334-8870 Los Angeles Tel: 48-22-3325737 Fax: 65-6334-8850 Mission Viejo, CA China - Shenyang Romania - Bucharest Tel: 949-462-9523 Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 40-21-407-87-50 Fax: 949-462-9608 Fax: 86-24-2334-2393 Tel: 886-3-5778-366 Tel: 951-273-7800 China - Shenzhen Fax: 886-3-5770-955 Spain - Madrid Tel: 34-91-708-08-90 Raleigh, NC Tel: 86-755-8864-2200 Taiwan - Kaohsiung Fax: 34-91-708-08-91 Tel: 919-844-7510 Fax: 86-755-8203-1760 Tel: 886-7-213-7830 Sweden - Gothenberg New York, NY China - Wuhan Taiwan - Taipei Tel: 46-31-704-60-40 Tel: 631-435-6000 Tel: 86-27-5980-5300 Tel: 886-2-2508-8600 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Sweden - Stockholm San Jose, CA Tel: 46-8-5090-4654 Tel: 408-735-9110 China - Xian Thailand - Bangkok Tel: 408-436-4270 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 UK - Wokingham Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Tel: 44-118-921-5800 Canada - Toronto Fax: 44-118-921-5820 Tel: 905-695-1980 Fax: 905-695-2078  2010-2017 Microchip Technology Inc. DS30009977G-page 597 10/10/17

1.0 Device Overview........................................................................................................................................................................10 2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers.........................................................................................43 3.0 Oscillator Configurations............................................................................................................................................................48 4.0 Power-Managed Modes.............................................................................................................................................................61 5.0 Reset..........................................................................................................................................................................................75 6.0 Memory Organization.................................................................................................................................................................97 7.0 Flash Program Memory............................................................................................................................................................125 8.0 Data EEPROM Memory...........................................................................................................................................................134 9.0 8 x 8 Hardware Multiplier..........................................................................................................................................................140 10.0 Interrupts..................................................................................................................................................................................142 11.0 I/O Ports...................................................................................................................................................................................165 12.0 Data Signal Modulator..............................................................................................................................................................189 13.0 Timer0 Module.........................................................................................................................................................................199 14.0 Timer1 Module.........................................................................................................................................................................202 15.0 Timer2 Module.........................................................................................................................................................................214 16.0 Timer3 Module.........................................................................................................................................................................217 17.0 Timer4 Modules........................................................................................................................................................................227 18.0 Charge Time Measurement Unit (CTMU)................................................................................................................................229 19.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................247 20.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................259 21.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................281 22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................326 23.0 12-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................350 24.0 Comparator Module..................................................................................................................................................................365 25.0 Comparator Voltage Reference Module...................................................................................................................................373 26.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................376 27.0 ECAN Module...........................................................................................................................................................................382 28.0 Special Features of the CPU....................................................................................................................................................447 29.0 Instruction Set Summary..........................................................................................................................................................473 30.0 Development Support...............................................................................................................................................................523 31.0 Electrical Characteristics..........................................................................................................................................................527 32.0 Packaging Information..............................................................................................................................................................571 Appendix A: Revision History.............................................................................................................................................................590 Appendix B: Migration to PIC18F66K80 Family.................................................................................................................................591 The Microchip Web Site.....................................................................................................................................................................593 Customer Change Notification Service..............................................................................................................................................593 Customer Support..............................................................................................................................................................................593 Product Identification System............................................................................................................................................................595  2010-2017 Microchip Technology Inc. DS30009977G-page 598