PIC18F2480/2580/4480/4580 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc. DS39637D

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39637D-page 2 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology Power-Managed Modes: Peripheral Highlights: • Run: CPU on, Peripherals on • High-Current Sink/Source 25mA/25mA • Idle: CPU off, Peripherals on • Three External Interrupts • Sleep: CPU off, Peripherals off • One Capture/Compare/PWM (CCP) module • Idle mode Currents Down to 6.1μA Typical • Enhanced Capture/Compare/PWM (ECCP) module • Sleep mode Current Down to 0.2μA Typical (40/44-pin devices only): • Timer1 Oscillator: 1μA, 32kHz, 2V - One, two or four PWM outputs • Watchdog Timer: 1.7μA - Selectable polarity • Two-Speed Oscillator Start-up - Programmable dead time - Auto-shutdown and auto-restart Flexible Oscillator Structure: • Master Synchronous Serial Port (MSSP) module • Four Crystal modes, up to 40MHz Supporting 3-Wire SPI (all 4 modes) and I2C™ • 4x Phase Lock Loop (PLL) – Available for Crystal Master and Slave modes and Internal Oscillators) • Enhanced Addressable USART module • Two External RC modes, up to 4 MHz - Supports RS-485, RS-232 and LIN/J2602 • Two External Clock modes, up to 40 MHz - RS-232 operation using internal oscillator • Internal Oscillator Block: block - Fast wake from Sleep and Idle, 1 μs typical - Auto-wake-up on Start bit - 8 user-selectable frequencies, from 31kHz to 8MHz - Auto-Baud Detect - Provides a complete range of clock speeds, • 10-Bit, up to 11-Channel Analog-to-Digital from 31kHz to 32MHz when used with PLL Converter (A/D) module, up to 100 ksps - User-tunable to compensate for frequency drift - Auto-acquisition capability • Secondary Oscillator using Timer1 @ 32 kHz - Conversion available during Sleep • Fail-Safe Clock Monitor • Dual Analog Comparators with Input Multiplexing - Allows for safe shutdown if peripheral clock stops ECAN Technology Module Features: Special Microcontroller Features: • Message Bit Rates up to 1 Mbps • Conforms to CAN 2.0B Active Specification • C Compiler Optimized Architecture with Optional Extended Instruction Set • Fully Backward Compatible with PIC18XXX8 CAN modules • 100,000 Erase/Write Cycle Enhanced Flash Program Memory Typical • Three Modes of Operation: • 1,000,000 Erase/Write Cycle Data EEPROM - Legacy, Enhanced Legacy, FIFO Memory Typical • Three Dedicated Transmit Buffers with Prioritization • Flash/Data EEPROM Retention: > 40 Years • Two Dedicated Receive Buffers • Self-Programmable under Software Control • Six Programmable Receive/Transmit Buffers • Priority Levels for Interrupts • Three Full 29-Bit Acceptance Masks • 8 x 8 Single-Cycle Hardware Multiplier • 16 Full 29-Bit Acceptance Filters w/Dynamic • Extended Watchdog Timer (WDT): Association - Programmable period from 41ms to 131s • DeviceNet™ Data Byte Filter Support • Single-Supply 5V In-Circuit Serial • Automatic Remote Frame Handling Programming™ (ICSP™) via Two Pins • Advanced Error Management Features • In-Circuit Debug (ICD) via Two Pins • Wide Operating Voltage Range: 2.0V to 5.5V Program Memory Data Memory CCP/ MSSP RT Device (Fblyatsehs) #I nSsintrgulec-tWionosrd (SbRytAesM) E(EbPyRteOs)M I/O A1/D0- B(ciht) (EPCWCMP) SPI MI2aCs™ter USA Comp. 8T/i1m6e-brsit E PIC18F2480 16K 8192 768 256 25 8 1/0 Y Y 1 0 1/3 PIC18F2580 32K 16384 1536 256 25 8 1/0 Y Y 1 0 1/3 PIC18F4480 16K 8192 768 256 36 11 1/1 Y Y 1 2 1/3 PIC18F4580 32K 16384 1536 256 36 11 1/1 Y Y 1 2 1/3 © 2009 Microchip Technology Inc. DS39637D-page 3

PIC18F2480/2580/4480/4580 Pin Diagrams 28-Pin SPDIP, SOIC MCLR/VPP/RE3 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6/KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PGM RA2/AN2/VREF- 4 25 RB4/KBI0/AN9 RA3/AN3/VREF+ 5 00 24 RB3/CANRX 88 RA4/T0CKI 6 45 23 RB2/INT2/CANTX RA5/AN4/SS/HLVDIN 7 F2F2 22 RB1/INT1/AN8 VSS 8 1818 21 RB0/INT0/AN10 OSC1/CLKI/RA7 9 CC 20 VDD OSC2/CLKO/RA6 10 PIPI 19 VSS RC0/T1OSO/T13CKI 11 18 RC7/RX/DT RC1/T1OSI 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA 28-Pin QFN RE3GDGCGMN9 N1N0V/PPBI3/PBI2/PBI1/PBI0/A AAR/KKKK A1/A0/CLB7/B6/B5/B4/ RRMRRRR 28272625242322 RA2/AN2/VREF- 1 21 RB3/CANRX RA3/AN3/VREF+ 2 20 RB2/INT2/CANTX RA4/T0CKI 3 PIC18F2480 19 RB1/INT1/AN8 RA5/AN4/SS/HLVDIN 4 18 RB0/INT0/AN10 PIC18F2580 VSS 5 17 VDD OSC1/CLKI/RA7 6 16 VSS OSC2/CLKO/RA6 7 15 RC7/RX/DT 8 91011121314 OSO/T13CKIRC1/T1OSIRC2/CCP1C3/SCK/SCLC4/SDI/SDARC5/SDORC6/TX/CK 1 RR T 0/ C R 40-Pin PDIP MCLR/VPP/RE3 1 40 RB7/KBI3/PGD RA0/AN0/CVREF 2 39 RB6/KBI2/PGC RA1/AN1 3 38 RB5/KBI1/PGM RA2/AN2/VREF- 4 37 RB4/KBI0/AN9 RA3/AN3/VREF+ 5 36 RB3/CANRX RA4/T0CKI 6 35 RB2/INT2/CANTX RA5/AN4/SS/HLVDIN 7 34 RB1/INT1/AN8 RE0/RD/AN5 8 33 RB0/INT0/FLT0/AN10 00 RE1/WR/AN6/C1OUT 9 88 32 VDD 45 RE2/CS/AN7/C2OUT 10 44 31 VSS VDD 11 8F8F 30 RD7/PSP7/P1D VSS 12 C1C1 29 RD6/PSP6/P1C OSC1/CLKI/RA7 13 PIPI 28 RD5/PSP5/P1B OSC2/CLKO/RA6 14 27 RD4/PSP4/ECCP1/P1A RC0/T1OSO/T13CKI 15 26 RC7/RX/DT RC1/T1OSI 16 25 RC6/TX/CK RC2/CCP1 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0/C1IN+ 19 22 RD3/PSP3/C2IN- RD1/PSP1/C1IN- 20 21 RD2/PSP2/C2IN+ DS39637D-page 4 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 Pin Diagrams (Continued) 44-Pin TQFP N-N+N-N+ X/CKDODI/SDASP3/C2ISP2/C2ISP1/C1ISP0/C1ICK/SCLCP11OSI TSSPPPPSCT 6/5/4/3/2/1/0/3/2/1/ CCCDDDDCCCC RRRRRRRRRRN 43210987654 44444333333 RC7/RX/DT 1 33 NC RD4/PSP4/ECCP1/P1A 2 32 RC0/T1OSO/T13CKI RD5/PSP5/P1B 3 31 OSC2/CLKO/RA6 RD6/PSP6/P1C 4 30 OSC1/CLKI/RA7 RD7/PSP7/P1D 5 PIC18F4480 29 VSS VSS 6 PIC18F4580 28 VDD VDD 7 27 RE2/CS/AN7/C2OUT RB0/INT0/FLT0/AN10 8 26 RE1/WR/AN6/C1OUT RB1/INT1/AN8 9 25 RE0/RD/AN5 RB2/INT2/CANTX 10 24 RA5/AN4/SS/HLVDIN RB3/CANRX 11 23 RA4/T0CKI 23456789012 11111111222 NCNCRB4/KBI0/AN9RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDMCLR/V/RE3PPRA0/AN0/CVREFRA1/AN1RA2/AN2/V-REFRA3/AN3/V+REF 44-Pin QFN(1) KI X/CKDODI/SDASP3/C2IN-SP2/C2IN+SP1/C1IN-SP0/C1IN+CK/SCLCP11OSI1OSO/T13C TSSPPPPSCTT 6/5/4/3/2/1/0/3/2/1/0/ CCCDDDDCCCC RRRRRRRRRRR 43210987654 44444333333 RC7/RX/DT 1 33 OSC2/CLKO/RA6 RD4/PSP4/ECCP1/P1A 2 32 OSC1/CLKI/RA7 RD5/PSP5/P1B 3 31 VSS RD6/PSP6/P1C 4 30 AVSS RD7/PSP7/P1D 5 PIC18F4480 29 VDD VSS 6 PIC18F4580 28 AVDD AVDD 7 27 RE2/CS/AN7/C2OUT VDD 8 26 RE1/WR/AN6/C1OUT RB0/INT0/FLT0/AN10 9 25 RE0/RD/AN5 RB1/INT1/AN8 10 24 RA5/AN4/SS/HLVDIN RB2/INT2/CANTX 11 23 RA4/T0CKI 23456789012 11111111222 RB3/CANRXNCRB4/KBI0/AN9RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDMCLR/V/RE3PPRA0/AN0/CVREFRA1/AN1RA2/AN2/V-REFRA3/AN3/V+REF Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS. © 2009 Microchip Technology Inc. DS39637D-page 5

PIC18F2480/2580/4480/4580 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Guidelines for Getting Started with PIC18F Microcontrollers.....................................................................................................25 3.0 Oscillator Configurations............................................................................................................................................................29 4.0 Power-Managed Modes.............................................................................................................................................................39 5.0 Reset..........................................................................................................................................................................................47 6.0 Memory Organization.................................................................................................................................................................67 7.0 Flash Program Memory............................................................................................................................................................101 8.0 Data EEPROM Memory...........................................................................................................................................................111 9.0 8 x 8 Hardware Multiplier..........................................................................................................................................................117 10.0 Interrupts..................................................................................................................................................................................119 11.0 I/O Ports...................................................................................................................................................................................135 12.0 Timer0 Module.........................................................................................................................................................................151 13.0 Timer1 Module.........................................................................................................................................................................155 14.0 Timer2 Module.........................................................................................................................................................................161 15.0 Timer3 Module.........................................................................................................................................................................163 16.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................167 17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................177 18.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................191 19.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART).......................................................................................231 20.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................253 21.0 Comparator Module..................................................................................................................................................................263 22.0 Comparator Voltage Reference Module...................................................................................................................................269 23.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................273 24.0 ECAN Module...........................................................................................................................................................................279 25.0 Special Features of the CPU....................................................................................................................................................349 26.0 Instruction Set Summary..........................................................................................................................................................367 27.0 Development Support...............................................................................................................................................................417 28.0 Electrical Characteristics..........................................................................................................................................................421 29.0 Packaging Information..............................................................................................................................................................459 Appendix A: Revision History.............................................................................................................................................................471 Appendix B: Device Differences.........................................................................................................................................................471 Appendix C: Conversion Considerations...........................................................................................................................................472 Appendix D: Migration from Baseline to Enhanced Devices..............................................................................................................472 Appendix E: Migration From Mid-Range to Enhanced Devices.........................................................................................................473 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................473 The Microchip Web Site.....................................................................................................................................................................487 Customer Change Notification Service..............................................................................................................................................487 Customer Support..............................................................................................................................................................................487 Reader Response..............................................................................................................................................................................488 PIC18F2480/2580/4480/4580 Product Identification System............................................................................................................489 DS39637D-page 6 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2009 Microchip Technology Inc. DS39637D-page 7

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 8 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device specific information for the following devices: All of the devices in the PIC18F2480/2580/4480/4580 family offer ten different oscillator options, allowing • PIC18F2480 users a wide range of choices in developing application • PIC18F2580 hardware. These include: • PIC18F4480 • Four Crystal modes, using crystals or ceramic • PIC18F4580 resonators This family of devices offers the advantages of all • Two External Clock modes, offering the option of PIC18 microcontrollers – namely, high computational using two pins (oscillator input and a divide-by-4 performance at an economical price – with the addition clock output) or one pin (oscillator input, with the of high-endurance, Enhanced Flash program second pin reassigned as general I/O) memory.In addition to these features, the • Two External RC Oscillator modes with the same PIC18F2480/2580/4480/4580 family introduces design pin options as the External Clock modes enhancements that make these microcontrollers a • An internal oscillator block which provides an logical choice for many high-performance, 8MHz clock (±2% accuracy) and an INTRC power-sensitive applications. source (approximately 31kHz, stable over temperature and VDD), as well as a range of 1.1 New Core Features 6 user-selectable clock frequencies, between 125kHz to 4MHz, for a total of 8 clock 1.1.1 nanoWatt TECHNOLOGY frequencies. This option frees the two oscillator All of the devices in the PIC18F2480/2580/4480/4580 pins for use as additional general purpose I/O. family incorporate a range of features that can signifi- • A Phase Lock Loop (PLL) frequency multiplier, cantly reduce power consumption during operation. available to both the high-speed crystal and Key items include: internal oscillator modes, which allows clock speeds of up to 40MHz. Used with the internal • Alternate Run Modes: By clocking the controller oscillator, the PLL gives users a complete from the Timer1 source or the internal oscillator selection of clock speeds, from 31kHz to block, power consumption during code execution 32MHz – all without using an external crystal or can be reduced by as much as 90%. clock circuit. • Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still Besides its availability as a clock source, the internal active. In these states, power consumption can be oscillator block provides a stable reference source that reduced even further, to as little as 4% of normal gives the family additional features for robust operation requirements. operation: • On-the-Fly Mode Switching: The • Fail-Safe Clock Monitor: This option constantly power-managed modes are invoked by user code monitors the main clock source against a refer- during operation, allowing the user to incorporate ence signal provided by the internal oscillator. If a power-saving ideas into their application’s clock failure occurs, the controller is switched to software design. the internal oscillator block, allowing for continued • Lower Consumption in Key Modules: The low-speed operation or a safe application power requirements for both Timer1 and the shutdown. Watchdog Timer have been reduced by up to • Two-Speed Start-up: This option allows the 80%, with typical values of 1.1 and 2.1μA, internal oscillator to serve as the clock source respectively. from Power-on Reset, or wake-up from Sleep • Extended Instruction Set: In addition to the mode, until the primary clock source is available. standard 75 instructions of the PIC18 instruction set, PIC18F2480/2580/4480/4580 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. © 2009 Microchip Technology Inc. DS39637D-page 9

PIC18F2480/2580/4480/4580 1.2 Other Special Features 1.3 Details on Individual Family Members • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are Devices in the PIC18F2480/2580/4480/4580 family are rated to last for many thousands of erase/write available in 28-pin (PIC18F2X80) and 40/44-pin cycles – up to 100,000 for program memory and (PIC18F4X80) packages. Block diagrams for the two 1,000,000 for EEPROM. Data retention without groups are shown in Figure1-1 and Figure1-2. refresh is conservatively estimated to be greater The devices are differentiated from each other in six than 40 years. ways: • Self-Programmability: These devices can write to their own program memory spaces under inter- 1. Flash program memory (16Kbytes for nal software control. By using a bootloader routine PIC18FX480 devices; 32Kbytes for located in the protected Boot Block at the top of PIC18FX580 devices). program memory, it becomes possible to create 2. A/D channels (8 for PIC18F2X80 devices; 11 for an application that can update itself in the field. PIC18F4X80 devices). • Extended Instruction Set: The 3. I/O ports (3 bidirectional ports and 1 input only PIC18F2480/2580/4480/4580 family introduces port on PIC18F2X80 devices; 5 bidirectional an optional extension to the PIC18 instruction set, ports on PIC18F4X80 devices). which adds 8 new instructions and an Indexed 4. CCP and Enhanced CCP implementation Addressing mode. This extension, enabled as a (PIC18F2X80 devices have 1 standard CCP device configuration option, has been specifically module; PIC18F4X80 devices have one designed to optimize re-entrant application code standard CCP module and one ECCP module). originally developed in high-level languages, such 5. Parallel Slave Port (present only on as C. PIC18F4X80 devices). • Enhanced CCP Module: In PWM mode, this 6. PIC18F4X80 devices provide two comparators. module provides 1, 2 or 4 modulated outputs for All other features for devices in this family are identical. controlling half-bridge and full-bridge drivers. These are summarized in Table1-1. Other features include auto-shutdown, for disabling PWM outputs on interrupt or other select The pinouts for all devices are listed in Table1-2 and conditions and auto-restart, to reactivate outputs Table1-3. once the condition has cleared. Like all Microchip PIC18 devices, members of the • Enhanced Addressable USART: This serial PIC18F2480/2580/4480/4580 family are available as communication module is capable of standard both standard and low-voltage devices. Standard RS-232 operation and provides support for the devices with Enhanced Flash memory, designated with LIN/J2602 bus protocol. Other enhancements an “F” in the part number (such as PIC18F2580), include automatic baud rate detection and a 16-bit accommodate an operating VDD range of 4.2V to 5.5V. Baud Rate Generator for improved resolution. Low-voltage parts, designated by “LF” (such as When the microcontroller is using the internal PIC18LF2580), function over an extended VDD range oscillator block, the EUSART provides stable of 2.0V to 5.5V. operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4ms to over 131 seconds, that is stable across operating voltage and temperature. DS39637D-page 10 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 1-1: DEVICE FEATURES Features PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16384 32768 16384 32768 Program Memory (Instructions) 8192 16384 8192 16384 Data Memory (Bytes) 768 1536 768 1536 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 1 1 1 1 Enhanced Capture/ 0 0 1 1 Compare/PWM Modules ECAN Module 1 1 1 1 Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications (PSP) No No Yes Yes 10-Bit Analog-to-Digital Module 8 Input Channels 8 Input Channels 11 Input Channels 11 Input Channels Comparators 0 0 2 2 Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Programmable High/ Yes Yes Yes Yes Low-Voltage Detect Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set Instruction Set Instruction Set Instruction Set Enabled Enabled Enabled Enabled Packages 28-pin SPDIP 28-pin SPDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 44-pin QFN 44-pin QFN 28-pin QFN 28-pin QFN 44-pin TQFP 44-pin TQFP © 2009 Microchip Technology Inc. DS39637D-page 11

PIC18F2480/2580/4480/4580 FIGURE 1-1: PIC18F2480/2580 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch PORTA inc/dec logic 8 8 RA0/AN0 Data Memory RA1/AN1 21 PCLAT U PCLATH (.7, 1.5Kbytes) RA2/AN2/VREF- RA3/AN3/VREF+ 20 Address Latch RA4/T0CKI PCU PCH PCL RA5/AN4/SS/HLVDIN Program Counter 12 OSC2/CLKO/RA6 Data Address<12> OSC1/CLKI/RA7 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (16/32Kbytes) FSR1 Data Latch FSR2 12 PORTB RB0/INT0/AN10 inc/dec 8 logic RB1/INT1/AN8 Table Latch RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 Address Instruction Bus <16> ROM Latch Decode RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State Machine Decode & Control Signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T13CKI 3 8 RC1/T1OSI RC2/CCP1 BITOP W RC3/SCK/SCL 8 8 8 RC4/SDI/SDA OSC1(2) OInsBtcleoilrlcnakatolr PoTwimere-rup 8 8 RRRCCC675///TRSXDX//OCDKT OSC2(2) Oscillator ALU<8> INTRC Start-up Timer T1OSI Oscillator Power-on 8 Reset 8 MHz T1OSO Oscillator Watchdog Timer MCLR(1) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBeafnedr eGnacpe PORTE In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor MCLR/VPP/RE3(1) BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 ADC Comparator CCP1 ECCP1 MSSP EUSART ECAN 10-Bit Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section3.0 “Oscillator Configurations” for additional information. DS39637D-page 12 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 1-2: PIC18F4480/4580 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0/CVREF Data Latch RA1/AN1 inc/dec logic 8 8 RA2/AN2/VREF- Data Memory RA3/AN3/VREF+ 21 PCLAT U PCLATH (.7, 1.5Kbytes) RA4/T0CKI RA5/AN4/SS/HLVDIN 20 Address Latch OSC2/CLKO/RA6 PCU PCH PCL OSC1/CLKI/RA7 Program Counter 12 Data Address<12> PORTB 31 Level Stack RB0/INT0/FLT0/AN10 Address Latch 4 12 4 RB1/INT1/AN8 BSR Access Program Memory STKPTR FSR0 Bank RB2/INT2/CANTX (16/32Kbytes) FSR1 RB3/CANRX Data Latch FSR2 12 RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 IR RC3/SCK/SCL RC4/SDI/SDA 8 RC5/SDO Instruction State Machine RC6/TX/CK Decode & Control Signals RC7/RX/DT Control PRODH PRODL 8 x 8 Multiply 3 8 PORTD RD0/PSP0/C1IN+ BITOP W RD1/PSP1/C1IN- 8 8 8 RD2/PSP2/C2IN+ RD3/PSP3/C2IN- OSC1(2) OInsBtcleoilrlcnakatolr PoTwimere-rup 8 8 RRDD45//PPSSPP45//EPC1CBP1/P1A OSC2(2) Oscillator ALU<8> RD6/PSP6/P1C INTRC Start-up Timer RD7/PSP7/P1D T1OSI Oscillator Power-on 8 Reset 8 MHz T1OSO Oscillator Watchdog PORTE Timer RE0/RD/AN5 MCLR(1) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBeafnedr eGnacpe RREE21//CWSR/A/ANN76/C/C21OOUUTT In-Circuit Fail-Safe MCLR/VPP/RE3(1) VDD,VSS Debugger Clock Monitor BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 ADC Comparator CCP1 ECCP1 MSSP EUSART ECAN 10-Bit Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section3.0 “Oscillator Configurations” for additional information. © 2009 Microchip Technology Inc. DS39637D-page 13

PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name SPDIP, Description QFN Type Type SOIC MCLR/VPP/RE3 1 26 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI/RA7 9 6 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 10 7 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer DS39637D-page 14 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SPDIP, Description QFN Type Type SOIC PORTA is a bidirectional I/O port. RA0/AN0 2 27 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 3 28 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 4 1 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 5 2 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 6 3 RA4 I/O TTL Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4/SS/ 7 4 HLVDIN RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer © 2009 Microchip Technology Inc. DS39637D-page 15

PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SPDIP, Description QFN Type Type SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/ AN10 21 18 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. AN10 I Analog Analog Input 10. RB1/INT1/AN8 22 19 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. AN8 I Analog Analog Input 8. RB2/INT2/CANTX 23 20 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. CANTX O TTL CAN bus TX. RB3/CANRX 24 21 RB3 I/O TTL Digital I/O. CANRX I TTL CAN bus RX. RB4/KBI0/AN9 25 22 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN9 I Analog Analog Input 9. RB5/KBI1/PGM 26 23 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 27 24 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 28 25 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer DS39637D-page 16 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SPDIP, Description QFN Type Type SOIC PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 11 8 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI 12 9 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. RC2/CCP1 13 10 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK/SCL 14 11 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O I2C Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 15 12 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O I2C I2C data I/O. RC5/SDO 16 13 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 17 14 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 18 15 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). RE3 — — — — See MCLR/VPP/RE3 pin. VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer © 2009 Microchip Technology Inc. DS39637D-page 17

PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type MCLR/VPP/RE3 1 18 18 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI/RA7 13 32 30 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer DS39637D-page 18 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTA is a bidirectional I/O port. RA0/AN0/CVREF 2 19 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. CVREF O Analog Analog comparator reference output. RA1/AN1 3 20 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 4 21 21 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 5 22 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 6 23 23 RA4 I/O TTL Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4/SS/ 7 24 24 HLVDIN RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer © 2009 Microchip Technology Inc. DS39637D-page 19

PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/ 33 9 8 AN10 I/O TTL Digital I/O. RB0 I ST External Interrupt 0. INT0 I ST Enhanced PWM Fault input (ECCP1 module). FLT0 I Analog Analog input 10. AN10 RB1/INT1/AN8 34 10 9 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. AN8 I Analog Analog input 8. RB2/INT2/CANTX 35 11 10 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. CANTX O TTL CAN bus TX. RB3/CANRX 36 12 11 RB3 I/O TTL Digital I/O. CANRX I TTL CAN bus RX. RB4/KBI0/AN9 37 14 14 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN9 I Analog Analog Input 9. RB5/KBI1/PGM 38 15 15 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer DS39637D-page 20 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 15 34 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI 16 35 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. RC2/CCP1 17 36 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK/SCL 18 37 37 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O I2C Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 23 42 42 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O I2C I2C data I/O. RC5/SDO 24 43 43 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 26 1 1 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer © 2009 Microchip Technology Inc. DS39637D-page 21

PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled. RD0/PSP0/C1IN+ 19 38 38 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. C1IN+ I Analog Comparator 1 input (+). RD1/PSP1/C1IN- 20 39 39 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. C1IN- I Analog Comparator 1 input (-) RD2/PSP2/C2IN+ 21 40 40 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. C2IN+ I Analog Comparator 2 input (+). RD3/PSP3/C2IN- 22 41 41 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. C2IN- I Analog Comparator 2 input (-). RD4/PSP4/ECCP1/ 27 2 2 P1A RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. ECCP1 I/O ST Capture 2 input/Compare 2 output/PWM2 output. P1A O TTL ECCP1 PWM Output A. RD5/PSP5/P1B 28 3 3 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. P1B O TTL ECCP1 PWM Output B. RD6/PSP6/P1C 29 4 4 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. P1C O TTL ECCP1 PWM Output C. RD7/PSP7/P1D 30 5 5 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. P1D O TTL ECCP1 PWM Output D. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer DS39637D-page 22 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTE is a bidirectional I/O port. RE0/RD/AN5 8 25 25 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port (see also WR and CS pins). AN5 I Analog Analog Input 5. RE1/WR/AN6/C1OUT 9 26 26 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port (see CS and RD pins). AN6 I Analog Analog Input 6. C1OUT O TTL Comparator 1 output. RE2/CS/AN7/C2OUT 10 27 27 RE2 I/O ST Digital I/O. CS I TTL Chip select control for Parallel Slave Port (see related RD and WR). AN7 I Analog Analog Input 7. C2OUT O TTL Comparator 2 output. RE3 — — — — — See MCLR/VPP/RE3 pin. VSS 12, 6, 30, 6, 29 P — Ground reference for logic and I/O pins. 31 31 VDD 11, 7, 8, 7, 28 P — Positive supply for logic and I/O pins. 32 28, 29 NC — 13 12, 13, — — No connect. 33, 34 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus input buffer © 2009 Microchip Technology Inc. DS39637D-page 23

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 24 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH PIC18F MINIMUM CONNECTIONS MICROCONTROLLERS C2(1) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F2480/2580/4480/4580 R1 DD SS family of 8-bit microcontrollers requires attention to a V V R2 minimal set of device pin connections before MCLR proceeding with development. C1 VDD The following pins must always be connected: PIC18FXXXX C3(1) • All VDD and VSS pins VSS (see Section2.2 “Power Supply Pins”) VSS C6(1) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(1) C4(1) These pins must also be connected if they are being used in the end application: • PGC/PGD pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes Key (all values are recommendations): (see Section2.4 “ICSP Pins”) C1 through C6: 0.1 µF, 20V ceramic • OSCI and OSCO pins when an external oscillator R1: 10 kΩ source is used R2: 100Ω to 470Ω (see Section2.5 “External Oscillator Pins”) Note 1: The example shown is for a PIC18F device Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; • VREF+/VREF- pins are used when external voltage adjust the number of decoupling capacitors reference for analog modules is implemented appropriately. Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1. © 2009 Microchip Technology Inc. DS39637D-page 25

PIC18F2480/2580/4480/4580 2.2 Power Supply Pins 2.2.2 TANK CAPACITORS On boards with power traces running longer than 2.2.1 DECOUPLING CAPACITORS sixinches in length, it is suggested to use a tank capac- The use of decoupling capacitors on every pair of itor for integrated circuits, including microcontrollers, to power supply pins, such as VDD, VSS, AVDD and supply a local power source. The value of the tank AVSS, is required. capacitor should be determined based on the trace resistance that connects the power supply source to Consider the following criteria when using decoupling the device, and the maximum current drawn by the capacitors: device in the application. In other words, select the tank • Value and type of capacitor: A 0.1 μF (100 nF), capacitor so that it meets the acceptable voltage sag at 10-20V capacitor is recommended. The capacitor the device. Typical values range from 4.7μF to 47μF. should be a low-ESR device, with a resonance frequency in the range of 200MHz and higher. 2.2.3 CONSIDERATIONS WHEN USING Ceramic capacitors are recommended. BOR • Placement on the printed circuit board: The When the Brown-out Reset (BOR) feature is enabled, decoupling capacitors should be placed as close a sudden change in VDD may result in a spontaneous to the pins as possible. It is recommended to BOR event. This can happen when the microcontroller place the capacitors on the same side of the is operating under normal operating conditions, regard- board as the device. If space is constricted, the less of what the BOR set point has been programmed capacitor can be placed on another layer on the to, and even if VDD does not approach the set point. PCB using a via; however, ensure that the trace The precipitating factor in these BOR events is a rise or length from the pin to the capacitor is no greater fall in VDD with a slew rate faster than 0.15V/μs. than 0.25inch (6mm). An application that incorporates adequate decoupling • Handling high-frequency noise: If the board is between the power supplies will not experience such experiencing high-frequency noise (upward of rapid voltage changes. Additionally, the use of an tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling electrolytic tank capacitor across VDD and VSS, as described above, will be helpful in preventing high slew capacitor. The value of the second capacitor can rate transitions. be in the range of 0.01μF to 0.001μF. Place this second capacitor next to each primary decoupling If the application has components that turn on or off, capacitor. In high-speed circuit designs, consider and share the same VDD circuit as the microcontroller, implementing a decade pair of capacitances as the BOR can be disabled in software by using the close to the power and ground pins as possible SBOREN bit before switching the component. After- (e.g., 0.1μF in parallel with 0.001μF). wards, allow a small delay before re-enabling the BOR. • Maximizing performance: On the board layout By doing this, it is ensured that the BOR is disabled from the power supply circuit, run the power and during the interval that might cause high slew rate return traces to the decoupling capacitors first, changes of VDD. and then to the device pins. This ensures that the Note: Not all devices incorporate software BOR decoupling capacitors are first in the power chain. control. See Section5.0 “Reset” for Equally important is to keep the trace length device-specific information. between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. DS39637D-page 26 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 2.3 Master Clear (MCLR) Pin 2.4 ICSP Pins The MCLR pin provides two specific device The PGC and PGD pins are used for In-Circuit Serial functions: Device Reset, and Device Programming Programming™ (ICSP™) and debugging purposes. It and Debugging. If programming and debugging are is recommended to keep the trace length between the not required in the end application, a direct ICSP connector and the ICSP pins on the device as connection to VDD may be all that is required. The short as possible. If the ICSP connector is expected to addition of other components, to help increase the experience an ESD event, a series resistor is recom- application’s resistance to spurious Resets from mended, with the value in the range of a few tens of voltage sags, may be beneficial. A typical ohms, not to exceed 100Ω. configuration is shown in Figure2-1. Other circuit Pull-up resistors, series diodes, and capacitors on the designs may be implemented, depending on the PGC and PGD pins are not recommended as they will application’s requirements. interfere with the programmer/debugger communica- During programming and debugging, the resistance tions to the device. If such discrete components are an and capacitance that can be added to the pin must be application requirement, they should be removed from considered. Device programmers and debuggers drive the circuit during programming and debugging. Alter- the MCLR pin. Consequently, specific voltage levels natively, refer to the AC/DC characteristics and timing (VIH and VIL) and fast signal transitions must not be requirements information in the respective device adversely affected. Therefore, specific values of R1 Flash programming specification for information on and C1 will need to be adjusted based on the capacitive loading limits and pin input voltage high (VIH) application and PCB requirements. For example, it is and input low (VIL) requirements. recommended that the capacitor, C1, be isolated from For device emulation, ensure that the “Communication the MCLR pin during programming and debugging Channel Select” (i.e., PGCx/PGDx pins) programmed operations by using a jumper (Figure2-2). The jumper into the device matches the physical connections for is replaced for normal run-time operations. the ICSP to the Microchip debugger/emulator tool. Any components associated with the MCLR pin For more information on available Microchip should be placed within 0.25 inch (6mm) of the pin. development tools connection requirements, refer to Section27.0 “Development Support”. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R1 R2 MCLR JP PIC18FXXXX C1 Note 1: R1≤ 10kΩ is recommended. A suggested starting value is 10kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2≤ 470Ω will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. © 2009 Microchip Technology Inc. DS39637D-page 27

PIC18F2480/2580/4480/4580 2.5 External Oscillator Pins FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR Many microcontrollers have options for at least two CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts: Section3.0 “Oscillator Configurations” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSC1 Oscillator of the board. C1 ` OSC2 Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power T1OSO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board T1OS I Timer1 Oscillator where the crystal is placed. Crystal ` Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With T1 Oscillator: C1 T1 Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins and other signals Bottom Layer in close proximity to the oscillator are benign (i.e., free Copper Pour of high frequencies, short rise and fall times, and other (tied to ground) similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.6 Unused I/Os DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low. DS39637D-page 28 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 3.0 OSCILLATOR FIGURE 3-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) 3.1 Oscillator Types PIC18F2480/2580/4480/4580 devices can be operated C1(1) OSC1 in ten different oscillator modes. The user can program To the Configuration bits, FOSC<3:0>, in Configuration Internal Register 1H to select one of these ten modes: XTAL RF(3) Logic 1. LP Low-Power Crystal Sleep 2. XT Crystal/Resonator RS(2) 3. HS High-Speed Crystal/Resonator C2(1) OSC2 PIC18FXXXX 4. HSPLL High-Speed Crystal/Resonator Note 1: See Table3-1 and Table3-2 for initial values of with PLL Enabled C1 and C2. 5. RC External Resistor/Capacitor with 2: A series resistor (RS) may be required for AT strip cut crystals. FOSC/4 Output on RA6 3: RF varies with the oscillator mode chosen. 6. RCIO External Resistor/Capacitor with I/O on RA6 7. INTIO1 Internal Oscillator with FOSC/4 Output TABLE 3-1: CAPACITOR SELECTION FOR on RA6 and I/O on RA7 CERAMIC RESONATORS 8. INTIO2 Internal Oscillator with I/O on RA6 and RA7 Typical Capacitor Values Used: 9. EC External Clock with FOSC/4 Output Mode Freq OSC1 OSC2 10. ECIO External Clock with I/O on RA6 XT 455 kHz 56 pF 56 pF 2.0 MHz 47 pF 47 pF 3.2 Crystal Oscillator/Ceramic 4.0 MHz 33 pF 33 pF Resonators HS 8.0 MHz 27 pF 27 pF In XT, LP, HS or HSPLL Oscillator modes, a crystal or 16.0 MHz 22 pF 22 pF ceramic resonator is connected to the OSC1 and Capacitor values are for design guidance only. OSC2 pins to establish oscillation. Figure3-1 shows These capacitors were tested with the resonators the pin connections. listed below for basic start-up and operation. These The oscillator design requires the use of a parallel values are not optimized. resonant crystal. Different capacitor values may be required to produce Note: Use of a series resonant crystal may give acceptable oscillator operation. The user should test a frequency out of the crystal the performance of the oscillator over the expected manufacturer’s specifications. VDD and temperature range for the application. See the notes on page 30 for additional information. Resonators Used: 455 kHz 4.0 MHz 2.0 MHz 8.0 MHz 16.0 MHz Note: When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330Ω. © 2009 Microchip Technology Inc. DS39637D-page 29

PIC18F2480/2580/4480/4580 TABLE 3-2: CAPACITOR SELECTION FOR An external clock source may also be connected to the CRYSTAL OSCILLATOR OSC1 pin in the HS mode, as shown in Figure3-2. Typical Capacitor Values FIGURE 3-2: EXTERNAL CLOCK Crystal Tested: Osc Type INPUT OPERATION Freq C1 C2 (HS OSCILLATOR CONFIGURATION) LP 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF XT 1 MHz 33 pF 33 pF Clock from OSC1 4 MHz 27 pF 27 pF Ext. System PIC18FXXXX (HS Mode) HS 4 MHz 27 pF 27 pF Open OSC2 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF 3.3 External Clock Input Capacitor values are for design guidance only. These capacitors were tested with the crystals listed The EC and ECIO Oscillator modes require an external below for basic start-up and operation. These values clock source to be connected to the OSC1 pin. There is are not optimized. no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. Different capacitor values may be required to produce acceptable oscillator operation. The user should test In the EC Oscillator mode, the oscillator frequency the performance of the oscillator over the expected divided by 4 is available on the OSC2 pin. This signal VDD and temperature range for the application. may be used for test purposes or to synchronize other logic. Figure3-3 shows the pin connections for the EC See the notes following this table for additional Oscillator mode. information. Crystals Used: FIGURE 3-3: EXTERNAL CLOCK 32 kHz 4 MHz INPUT OPERATION 200 kHz 8 MHz (EC CONFIGURATION) 1 MHz 20 MHz Clock from OSC1/CLKI Ext. System PIC18FXXXX Note1: Higher capacitance increases the stability of the oscillator but also increases the FOSC/4 OSC2/CLKO start-up time. 2: When operating below 3V VDD, or when The ECIO Oscillator mode functions like the EC mode, using certain ceramic resonators at any except that the OSC2 pin becomes an additional voltage, it may be necessary to use the general purpose I/O pin. The I/O pin becomes bit 6 of HS mode or switch to a crystal oscillator. PORTA (RA6). Figure3-4 shows the pin connections for the ECIO Oscillator mode. 3: Since each resonator/crystal has its own characteristics, the user should consult FIGURE 3-4: EXTERNAL CLOCK the resonator/crystal manufacturer for appropriate values of external INPUT OPERATION components. (ECIO CONFIGURATION) 4: Rs may be required to avoid overdriving crystals with low drive level specification. Clock from OSC1/CLKI 5: Always verify oscillator performance over Ext. System PIC18FXXXX the VDD and temperature range that is RA6 I/O (OSC2) expected for the application. DS39637D-page 30 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 3.4 RC Oscillator 3.5 PLL Frequency Multiplier For timing insensitive applications, the “RC” and A Phase Locked Loop (PLL) circuit is provided as an “RCIO” device options offer additional cost savings. option for users who wish to use a lower frequency The actual oscillator frequency is a function of several oscillator circuit or to clock the device up to its highest factors: rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due • supply voltage to high-frequency crystals or users who require higher • values of the external resistor (REXT) and clock speeds from an internal oscillator. capacitor (CEXT) • operating temperature 3.5.1 HSPLL OSCILLATOR MODE Given the same device, operating voltage and tempera- The HSPLL mode makes use of the HS mode oscillator ture and component values, there will also be unit-to-unit for frequencies up to 10 MHz. A PLL then multiplies the frequency variations. These are due to factors such as: oscillator output frequency by 4 to produce an internal • normal manufacturing variation clock frequency up to 40 MHz. • difference in lead frame capacitance between The PLL is only available to the crystal oscillator when package types (especially for low CEXT values) the FOSC<3:0> Configuration bits are programmed for • variations within the tolerance of limits of REXT HSPLL mode (= 0110). and CEXT FIGURE 3-7: PLL BLOCK DIAGRAM In the RC Oscillator mode, the oscillator frequency (HS MODE) divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other HS Osc Enable logic. Figure3-5 shows how the R/C combination is PLL Enable connected. (from Configuration Register 1H) FIGURE 3-5: RC OSCILLATOR MODE OSC2 VDD HS Mode FIN CoPmhpaasreator OSC1 Crystal FOUT REXT Osc Internal OSC1 Clock Loop Filter CEXT PIC18FXXXX VSS OSC2/CLKO FOSC/4 ÷4 VCO SYSCLK X Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ U M CEXT > 20 pF The RCIO Oscillator mode (Figure3-6) functions like the RC mode, except that the OSC2 pin becomes an 3.5.2 PLL AND INTOSC additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). The PLL is also available to the internal oscillator block in selected oscillator modes. In this configuration, the FIGURE 3-6: RCIO OSCILLATOR MODE PLL is enabled in software and generates a clock output of up to 32MHz. The operation of INTOSC with VDD the PLL is described in Section3.6.4 “PLL in INTOSC Modes”. REXT Internal OSC1 Clock CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF © 2009 Microchip Technology Inc. DS39637D-page 31

PIC18F2480/2580/4480/4580 3.6 Internal Oscillator Block When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new The PIC18F2480/2580/4480/4580 devices include an frequency. The INTRC clock will reach the new internal oscillator block which generates two different frequency within 8 clock cycles (approximately clock signals; either can be used as the micro- 8*32μs=256μs). Code execution continues during controller’s clock source. This may eliminate the need this shift. There is no indication that the shift has for external oscillator circuits on the OSC1 and/or occurred. OSC2 pins. The OSCTUNE register also implements the INTSRC The main output (INTOSC) is an 8MHz clock source, and PLLEN bits, which control certain features of the which can be used to directly drive the device clock. It internal oscillator block. The INTSRC bit allows users also drives a postscaler, which can provide a range of to select which internal oscillator provides the clock clock frequencies from 31kHz to 4MHz. The INTOSC source when the 31kHz frequency option is selected. output is enabled when a clock frequency from 125kHz This is covered in greater detail in Section3.7.1 to 8MHz is selected. “Oscillator Control Register”. The other clock source is the internal RC oscillator The PLLEN bit controls the operation of the frequency (INTRC), which provides a nominal 31kHz output. multiplier, PLL, in internal oscillator modes. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the 3.6.4 PLL IN INTOSC MODES following are enabled: The 4x frequency multiplier can be used with the inter- • Power-up Timer nal oscillator block to produce faster device clock • Fail-Safe Clock Monitor speeds than are normally possible with an internal • Watchdog Timer oscillator. When enabled, the PLL produces a clock speed of up to 32MHz. • Two-Speed Start-up Unlike HSPLL mode, the PLL is controlled through These features are discussed in greater detail in software. The control bit, PLLEN (OSCTUNE<6>), is Section25.0 “Special Features of the CPU”. used to enable or disable its operation. If PLL is The clock source frequency (INTOSC direct, INTRC enabled and a Two-Speed Start-up from wake is direct or INTOSC postscaler) is selected by configuring performed, execution is delayed until the PLL starts. the IRCF bits of the OSCCON register(Register3-2). The PLL is available when the device is configured to 3.6.1 INTIO MODES use the internal oscillator block as its primary clock source (FOSC<3:0> = 1001 or 1000). Additionally, the Using the internal oscillator as the clock source elimi- PLL will only function when the selected output fre- nates the need for up to two external oscillator pins, quency is either 4MHz or 8MHz (OSCCON<6:4> = 111 which can then be used for digital I/O. Two distinct or 110). If both of these conditions are not met, the PLL configurations are available: is disabled. • In INTIO1 mode, the OSC2 pin outputs FOSC/4, The PLLEN control bit is only functional in those internal while OSC1 functions as RA7 for digital input and oscillator modes where the PLL is available. In all other output. modes, it is forced to ‘0’ and is effectively unavailable. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and 3.6.5 INTOSC FREQUENCY DRIFT output. The factory calibrates the internal oscillator block output (INTOSC) for 8MHz. However, this frequency 3.6.2 INTOSC OUTPUT FREQUENCY may drift as VDD or temperature changes, which can The internal oscillator block is calibrated at the factory affect the controller operation in a variety of ways. It is to produce an INTOSC output frequency of 8.0MHz. possible to adjust the INTOSC frequency by modifying The INTRC oscillator operates independently of the the value in the OSCTUNE register. This has no effect INTOSC source. Any changes in INTOSC across volt- on the INTRC clock source frequency. age and temperature are not necessarily reflected by Tuning the INTOSC source requires knowing when to changes in INTRC and vice versa. make the adjustment, in which direction it should be made, and in some cases, how large a change is 3.6.3 OSCTUNE REGISTER needed. Three compensation techniques are The internal oscillator’s output has been calibrated at discussed in Section3.6.5.1 “Compensating with the factory but can be adjusted in the user’s applica- the EUSART”, Section3.6.5.2 “Compensating with tion. This is done by writing to the OSCTUNE register the Timers” and Section3.6.5.3 “Compensating (Register3-1). with the CCP Module in Capture Mode”, but other techniques may be used. DS39637D-page 32 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 8MHz INTOSC source (divide-by-256 enabled) 0 = 31kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4MHz and 8MHz only) 0 = PLL disabled bit 5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency • • • • 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • • • 10000 = Minimum frequency Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See text for details. 3.6.5.1 Compensating with the EUSART is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement An adjustment may be required when the EUSART the OSCTUNE register. begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors 3.6.5.3 Compensating with the CCP Module indicate that the device clock frequency is too high. To in Capture Mode adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors A CCP module can use free-running Timer1 (or in data may suggest that the clock speed is too low. To Timer3), clocked by the internal oscillator block and an compensate, increment OSCTUNE to increase the external event with a known period (i.e., AC power clock frequency. frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use 3.6.5.2 Compensating with the Timers later. When the second event causes a capture, the time of the first event is subtracted from the time of the This technique compares device clock speed to some second event. Since the period of the external event is reference clock. Two timers may be used; one timer is known, the time difference between events can be clocked by the peripheral clock, while the other is calculated. clocked by a fixed reference source, such as the Timer1 oscillator. If the measured time is much greater than the calculated time, the internal oscillator block is running Both timers are cleared, but the timer clocked by the too fast. To compensate, decrement the OSCTUNE reference generates interrupts. When an interrupt register. If the measured time is much less than the occurs, the internally clocked timer is read and both calculated time, the internal oscillator block is running timers are cleared. If the internally clocked timer value too slow. To compensate, increment the OSCTUNE register. © 2009 Microchip Technology Inc. DS39637D-page 33

PIC18F2480/2580/4480/4580 3.7 Clock Sources and Oscillator The secondary oscillators are those external sources Switching not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the Like previous PIC18 devices, the controller is placed in a power-managed mode. PIC18F2480/2580/4480/4580 family includes a feature PIC18F2480/2580/4480/4580 devices offer the Timer1 that allows the device clock source to be switched from oscillator as a secondary oscillator. This oscillator, in all the main oscillator to an alternate low-frequency clock power-managed modes, is often the time base for source. PIC18F2480/2580/4480/4580 devices offer functions such as a Real-Time Clock (RTC). two alternate clock sources. When an alternate clock source is enabled, the various power-managed Most often, a 32.768kHz watch crystal is connected operating modes are available. between the RC0/T1OSO/T13CKI and RC1/T1OSI pins. Like the LP Oscillator mode circuit, loading Essentially, there are three clock sources for these capacitors are also connected from each pin to ground. devices: The Timer1 oscillator is discussed in greater detail in • Primary oscillators Section13.3 “Timer1 Oscillator”. • Secondary oscillators In addition to being a primary clock source, the internal • Internal oscillator block oscillator block is available as a power-managed The primary oscillators include the external crystal mode clock source. The INTRC source is also used as and resonator modes, the external RC modes, the the clock source for several special features, such as external clock modes and the internal oscillator block. the WDT and Fail-Safe Clock Monitor. The particular mode is defined by the FOSC<3:0> The clock sources for the PIC18F2480/2580/4480/4580 Configuration bits. The details of these modes are devices are shown in Figure3-8. See Section25.0 covered earlier in this chapter. “Special Features of the CPU” for Configuration register details. FIGURE 3-8: PIC18F2480/2580/4480/4580 CLOCK DIAGRAM Primary Oscillator LP, XT, HS, RC, EC OSC2 Sleep HSPLL, INTOSC/PLL 4 x PLL OSC1 OSCTUNE<6> Secondary Oscillator T1OSC X Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator OSCCON<6:4> Internal Oscillator OSCCON<6:4> 8 MHz CPU 111 4 MHz Internal 110 Oscillator 2 MHz IDLEN S8Bo lMuorHcckze 8 MHz stscaler 5010 M kHHzz 110001101MUX CColonctrkol INTRC (INTOSC) Po 250 kHz 010 FOSC<3:0> OSCCON< 1:0> Source 125 kHz 001 Clock Source Option 31 kHz (INTRC) 1 31 kHz 000 for Other Modules 0 OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up DS39637D-page 34 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 3.7.1 OSCILLATOR CONTROL REGISTER The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP The OSCCON register (Register3-2) controls several instruction is executed. aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section4.0 The System Clock Select bits, SCS<1:0>, select the “Power-Managed Modes”. clock source. The available clock sources are the primary clock (defined by the FOSC<3:0> Configura- Note 1: The Timer1 oscillator must be enabled to tion bits), the secondary clock (Timer1 oscillator) and select the secondary clock source. The the internal oscillator block. The clock source changes Timer1 oscillator is enabled by setting the immediately after one or more of the bits is written to, T1OSCEN bit in the Timer1 Control regis- following a brief clock transition interval. The SCS bits ter (T1CON<3>). If the Timer1 oscillator is are cleared on all forms of Reset. not enabled, then any attempt to select a The Internal Oscillator Frequency Select bits, secondary clock source when executing a IRCF<2:0>, select the frequency output of the internal SLEEP instruction will be ignored. oscillator block to drive the device clock. The choices 2: It is recommended that the Timer1 are the INTRC source, the INTOSC source (8MHz) or oscillator be operating and stable before one of the frequencies derived from the INTOSC post- executing the SLEEP instruction, or a very scaler (31kHz to 4MHz). If the internal oscillator block long delay may occur while the Timer1 is supplying the device clock, changing the states of oscillator starts. these bits will have an immediate change on the inter- nal oscillator’s output. On device Resets, the default 3.7.2 OSCILLATOR TRANSITIONS output frequency of the internal oscillator block is set at PIC18F2480/2580/4480/4580 devices contain circuitry 1MHz. to prevent clock “glitches” when switching between When an output frequency of 31kHz is selected clock sources. A short pause in the device clock occurs (IRCF<2:0> = 000), users may choose which internal during the clock switch. The length of this pause is the oscillator acts as the source. This is done with the sum of two cycles of the old clock source and three to INTSRC bit in the OSCTUNE register (OSCTUNE<7>). four cycles of the new clock source. This formula Setting this bit selects INTOSC as a 31.25kHz clock assumes that the new clock source is stable. source by enabling the divide-by-256 output of the Clock transitions are discussed in greater detail in INTOSC postscaler. Clearing INTSRC selects INTRC Section4.1.2 “Entering Power-Managed Modes”. (nominally 31kHz) as the clock source. This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer (OST) has timed out and the primary clock is providing the device clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabi- lized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2009 Microchip Technology Inc. DS39637D-page 35

PIC18F2480/2580/4480/4580 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8MHz (INTOSC drives clock directly) 110 = 4MHz 101 = 2MHz 100 = 1MHz(3) 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable and the frequency is provided by one of the RC modes 0 = INTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Primary oscillator Note 1: Depends on state of the IESO Configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. DS39637D-page 36 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 3.8 Effects of Power-Managed Modes Timer1 oscillator may be operating to support a on the Various Clock Sources Real-Time Clock (RTC). Other features may be operat- ing that do not require a device clock source (i.e., When PRI_IDLE mode is selected, the designated MSSP slave, PSP, INTx pins and others). Peripherals primary oscillator continues to run without interruption. that may add significant current consumption are listed For all other power-managed modes, the oscillator in Section28.2 “DC Characteristics: Power Down using the OSC1 pin is disabled. The OSC1 pin (and and Supply Current”. OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and 3.9 Power-up Delays SEC_IDLE), the Timer1 oscillator is operating and Power-up delays are controlled by two timers, so that no providing the device clock. The Timer1 oscillator may external Reset circuitry is required for most applications. also run in all power-managed modes if required to The delays ensure that the device is kept in Reset until clock Timer1 or Timer3. the device power supply is stable under normal circum- In internal oscillator modes (RC_RUN and RC_IDLE), stances and the primary clock is operating and stable. the internal oscillator block provides the device clock For additional information on power-up delays, see source. The 31kHz INTRC output can be used directly Section5.5 “Device Reset Timers”. to provide the clock and may be enabled to support The first timer is the Power-up Timer (PWRT), which various special features, regardless of the provides a fixed delay on power-up (parameter 33, power-managed mode (see Section25.2 “Watchdog Table28-10). It is enabled by clearing (= 0) the Timer (WDT)”, Section25.3 “Two-Speed Start-up” PWRTEN Configuration bit. and Section25.4 “Fail-Safe Clock Monitor” for more information on WDT, Two-Speed Start-up and Fail-Safe The second timer is the Oscillator Start-up Timer Clock Monitor. The INTOSC output at 8MHz may be (OST), intended to keep the chip in Reset until the used directly to clock the device or may be divided crystal oscillator is stable (LP, XT and HS modes). The down by the postscaler. The INTOSC output is disabled OST does this by counting 1024 oscillator cycles if the clock is provided directly from the INTRC output. before allowing the oscillator to clock the device. The INTOSC output is enabled for Two-Speed Start-up When the HSPLL Oscillator mode is selected, the at 1 MHz after a Reset. device is kept in Reset for an additional 2ms, following If the Sleep mode is selected, all clock sources are the HS mode OST delay, so the PLL can lock to the stopped. Since all the transistor switching currents incoming clock frequency. have been stopped, Sleep mode achieves the lowest There is a delay of interval, TCSD (parameter 38, current consumption of the device (only leakage Table28-10), following POR, while the controller currents). becomes ready to execute instructions. This delay runs Enabling any on-chip feature that will operate during concurrently with any other delays. This may be the Sleep will increase the current consumed during Sleep. only delay that occurs when any of the EC, RC or INTIO The INTRC is required to support WDT operation. The modes are used as the primary clock source. TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table5-2 in Section5.0 “Reset”, for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. DS39637D-page 37

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 38 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three PIC18F2480/2580/4480/4580 devices offer a total of clock sources for power-managed modes. They are: seven operating modes for more efficient power management. These modes provide a variety of • The primary clock, as defined by the FOSC<3:0> options for selective power conservation in applications Configuration bits where resources may be limited (i.e., battery-powered • The secondary clock (the Timer1 oscillator) devices). • The internal oscillator block (for RC modes) There are three categories of power-managed modes: 4.1.2 ENTERING POWER-MANAGED • Run modes MODES • Idle modes Switching from one power-managed mode to another • Sleep mode begins by loading the OSCCON register. The These categories define which portions of the device SCS<1:0> bits select the clock source and determine are clocked, and sometimes, what speed. The Run and which Run or Idle mode is to be used. Changing these Idle modes may use any of the three available clock bits causes an immediate switch to the new clock sources (primary, secondary or internal oscillator source, assuming that it is running. The switch may block); the Sleep mode does not use a clock source. also be subject to clock transition delays. These are The power-managed modes include several discussed in Section4.1.3 “Clock Transitions and power-saving features offered on previous PIC® Status Indicators” and subsequent sections. devices. One is the clock switching feature, offered in Entry to the power-managed Idle or Sleep modes is other PIC18 devices, allowing the controller to use the triggered by the execution of a SLEEP instruction. The Timer1 oscillator in place of the primary oscillator. Also actual mode that results depends on the status of the included is the Sleep mode, offered by all PIC devices, IDLEN bit. where all device clocks are stopped. Depending on the current mode and the mode being switched to, a change to a power-managed mode does 4.1 Selecting Power-Managed Modes not always require setting all of these bits. Many Selecting a power-managed mode requires two transitions may be done by changing the oscillator decisions: if the CPU is to be clocked or not and the select bits, or changing the IDLEN bit, prior to issuing a selection of a clock source. The IDLEN bit SLEEP instruction. If the IDLEN bit is already (OSCCON<7>) controls CPU clocking, while the configured correctly, it may only be necessary to SCS<1:0> bits (OSCCON<1:0>) select the clock perform a SLEEP instruction to switch to the desired source. The individual modes, bit settings, clock sources mode. and affected modules are summarized in Table4-1. TABLE 4-1: POWER-MANAGED MODES OSCCON<7,1:0> Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(2): This is the normal full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. DS39637D-page 39

PIC18F2480/2580/4480/4580 4.1.3 CLOCK TRANSITIONS AND STATUS Upon resuming normal operation after waking form INDICATORS Sleep or Idle, the internal state machines require at least one TCY delay before another SLEEP instruction The length of the transition between clock sources is can be executed. If two back-to-back SLEEP instruc- the sum of two cycles of the old clock source and three tions need to be executed, the process shown in to four cycles of the new clock source. This formula Example4-1 should be used. assumes that the new clock source is stable. Three bits indicate the current clock source and its EXAMPLE 4-1: EXECUTING status. They are: BACK-TO-BACK SLEEP • OSTS (OSCCON<3>) INSTRUCTIONS • IOFS (OSCCON<2>) SLEEP • T1RUN (T1CON<6>) NOP ; Wait at least 1 Tcy before In general, only one of these bits will be set while in a executing another SLEEP instruction given power-managed mode. When the OSTS bit is SLEEP set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is provid- 4.2 Run Modes ing a stable 8MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is In the Run modes, clocks to both the core and set, the Timer1 oscillator is providing the clock. If none peripherals are active. The difference between these of these bits are set, then either the INTRC clock modes is the clock source. source is clocking the device, or the INTOSC source is not yet stable. 4.2.1 PRI_RUN MODE If the internal oscillator block is configured as the The PRI_RUN mode is the normal, full-power execution primary clock source by the FOSC<3:0> Configuration mode of the microcontroller. This is also the default bits, then both the OSTS and IOFS bits may be set mode upon a device Reset, unless Two-Speed Start-up when in PRI_RUN or PRI_IDLE modes. This indicates is enabled (see Section25.3 “Two-Speed Start-up” for that the primary clock (INTOSC output) is generating a details). In this mode, the OSTS bit is set. The IOFS bit stable 8MHz output. Entering another RC may be set if the internal oscillator block is the primary power-managed mode at the same frequency would clock source (see Section3.7.1 “Oscillator Control clear the OSTS bit. Register”). Note1: Caution should be used when modifying a 4.2.2 SEC_RUN MODE single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed The SEC_RUN mode is the compatible mode to the than is supported by the low VDD. “clock switching” feature offered in other PIC18 Improper device operation may result if devices. In this mode, the CPU and peripherals are the VDD/FOSC specifications are violated. clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a 2: Executing a SLEEP instruction does not high accuracy clock source. necessarily place the device into Sleep mode. It acts as the trigger to place the SEC_RUN mode is entered by setting the SCS<1:0> controller into either the Sleep mode, or bits to ‘01’. The device clock source is switched to the one of the Idle modes, depending on the Timer1 oscillator (see Figure4-1), the primary oscilla- setting of the IDLEN bit. tor is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. 4.1.4 MULTIPLE SLEEP COMMANDS Note: The Timer1 oscillator should already be The power-managed mode that is invoked with the running prior to entering SEC_RUN mode. SLEEP instruction is determined by the setting of the If the T1OSCEN bit is not set when the IDLEN bit at the time the instruction is executed. If SCS<1:0> bits are set to ‘01’, entry to another SLEEP instruction is executed, the device will SEC_RUN mode will not occur. If the enter the power-managed mode specified by IDLEN at Timer1 oscillator is enabled but not yet that time. If IDLEN has changed, the device will enter the running, device clocks will be delayed until new power-managed mode specified by the new setting. the oscillator has started. In such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result. DS39637D-page 40 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 On transitions from SEC_RUN mode to PRI_RUN Figure4-2). When the clock switch is complete, the mode, the peripherals and CPU continue to be clocked T1RUN bit is cleared, the OSTS bit is set and the from the Timer1 oscillator while the primary clock is primary clock is providing the clock. The IDLEN and started. When the primary clock becomes ready, a SCS bits are not affected by the wake-up; the Timer1 clock switch back to the primary clock occurs (see oscillator continues to run. FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 SCS<1:0> Bits Changed OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 4.2.3 RC_RUN MODE This mode is entered by setting SCS1 to ‘1’. Although it is ignored, it is recommended that SCS0 also be In RC_RUN mode, the CPU and peripherals are cleared; this is to maintain software compatibility with clocked from the internal oscillator block using the future devices. When the clock source is switched to INTOSC multiplexer; the primary clock is shut down. the INTOSC multiplexer (see Figure4-3), the primary When using the INTRC source, this mode provides the oscillator is shut down and the OSTS bit is cleared. The best power conservation of all the Run modes, while IRCF bits may be modified at any time to immediately still executing code. It works well for user applications change the clock speed. which are not highly timing-sensitive or do not require high-speed clocks at all times. Note: Caution should be used when modifying a If the primary clock source is the internal oscillator single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed block (either INTRC or INTOSC), there are no distin- guishable differences between PRI_RUN and than is supported by the low VDD. Improper device operation may result if RC_RUN modes during execution. However, a clock switch delay will occur during entry to, and exit from, the VDD/FOSC specifications are violated. RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2009 Microchip Technology Inc. DS39637D-page 41

PIC18F2480/2580/4480/4580 If the IRCF bits and the INTSRC bit are all clear, the On transitions from RC_RUN mode to PRI_RUN mode, INTOSC output is not enabled and the IOFS bit will the device continues to be clocked from the INTOSC remain clear; there will be no indication of the current multiplexer while the primary clock is started. When the clock source. The INTRC source is providing the primary clock becomes ready, a clock switch to the device clocks. primary clock occurs (see Figure4-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS If the IRCF bits are changed from all clear (thus, bit is set and the primary clock is providing the device enabling the INTOSC output) or if INTSRC is set, the clock. The IDLEN and SCS bits are not affected by the IOFS bit becomes set after the INTOSC output switch. The INTRC source will continue to run if either becomes stable. Clocks to the device continue while the WDT or the Fail-Safe Clock Monitor is enabled. the INTOSC source stabilizes after an interval of TIOBST. If the IRCF bits were previously at a non-zero value or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 SCS<1:0> Bits Changed OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39637D-page 42 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode in the The Idle modes allow the controller’s CPU to be PIC18F2480/2580/4480/4580 devices is identical to selectively shut down while the peripherals continue to the legacy Sleep mode offered in all other PIC devices. operate. Selecting a particular Idle mode allows users It is entered by clearing the IDLEN bit (the default state to further manage power consumption. on device Reset) and executing the SLEEP instruction. If the IDLEN bit is set to ‘1’ when a SLEEP instruction is This shuts down the selected oscillator (Figure4-5). All executed, the peripherals will be clocked from the clock clock source status bits are cleared. source selected using the SCS<1:0> bits; however, the Entering the Sleep mode from any other mode does not CPU will not be clocked. The clock source status bits are require a clock switch. This is because no clocks are not affected. Setting IDLEN and executing a SLEEP needed once the controller has entered Sleep. If the instruction provides a quick method of switching from a WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode. operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue continue to run. to operate. If the Timer1 oscillator is enabled, it will also When a wake event occurs in Sleep mode (by interrupt, continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS1:SCS0 bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure4-6), or it will be clocked time-out or a Reset. When a wake event occurs, CPU from the internal oscillator block if either the Two-Speed execution is delayed by an interval of TCSD Start-up or the Fail-Safe Clock Monitor are enabled (parameter38, Table28-10) while it becomes ready to (see Section25.0 “Special Features of the CPU”). In execute code. When the CPU begins executing code, either case, the OSTS bit is set when the primary clock it resumes with the same clock source for the current is providing the device clocks. The IDLEN and SCS bits Idle mode. For example, when waking from RC_IDLE are not affected by the wake-up. mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 PLL Clock TOST(1) TPLL(1) Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS Bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39637D-page 43

PIC18F2480/2580/4480/4580 4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing-sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation with its more ting the IDLEN bit and executing a SLEEP instruction. If accurate primary clock source, since the clock source the device is in another Run mode, set the IDLEN bit does not have to “warm up” or transition from another first, then set the SCS<1:0> bits to ‘01’ and execute oscillator. SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, PRI_IDLE mode is entered from PRI_RUN mode by the OSTS bit is cleared and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCS bits and execute SLEEP. be clocked from the Timer1 oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the Timer1 oscillator. The by the FOSC<3:0> Configuration bits. The OSTS bit IDLEN and SCS bits are not affected by the wake-up; remains set (see Figure4-7). the Timer1 oscillator continues to run (see Figure4-8). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval TCSD is running prior to entering SEC_IDLE mode. required between the wake event and when code If the T1OSCEN bit is not set when the execution starts. This is required to allow the CPU to SLEEP instruction is executed, the SLEEP become ready to execute instructions. After the instruction will be ignored and entry to wake-up, the OSTS bit remains set. The IDLEN and SEC_IDLE mode will not occur. If the SCS bits are not affected by the wake-up (see Timer1 oscillator is enabled but not yet Figure4-8). running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event DS39637D-page 44 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 4.4.3 RC_IDLE MODE On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the In RC_IDLE mode, the CPU is disabled but the periph- GIE/GIEH bit (INTCON<7>) is set. Otherwise, code erals continue to be clocked from the internal oscillator execution continues or resumes without branching block using the INTOSC multiplexer. This mode allows (see Section10.0 “Interrupts”). for controllable power conservation during Idle periods. A fixed delay of interval, TCSD, following the wake event From RC_RUN, this mode is entered by setting the is required when leaving Sleep and Idle modes. This IDLEN bit and executing a SLEEP instruction. If the delay is required for the CPU to prepare for execution. device is in another Run mode, first set IDLEN, then set Instruction execution resumes on the first clock cycle the SCS1 bit and execute SLEEP. Although its value is following this delay. ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future 4.5.2 EXIT BY WDT TIME-OUT devices. The INTOSC multiplexer may be used to select a higher clock frequency, by modifying the IRCF A WDT time-out will cause different actions depending bits, before executing the SLEEP instruction. When the on which power-managed mode the device is in when clock source is switched to the INTOSC multiplexer, the the time-out occurs. primary oscillator is shut down and the OSTS bit is If the device is not executing code (all Idle modes and cleared. Sleep mode), the time-out will result in an exit from the If the IRCF bits are set to any non-zero value or the power-managed mode (see Section4.2 “Run INTSRC bit is set, the INTOSC output is enabled. The Modes” and Section4.3 “Sleep Mode”). If the device IOFS bit becomes set, after the INTOSC output is executing code (all Run modes), the time-out will becomes stable, after an interval of TIOBST result in a WDT Reset (see Section25.2 “Watchdog (parameter39, Table28-10). Clocks to the peripherals Timer (WDT)”). continue while the INTOSC source stabilizes. If the The WDT timer and postscaler are cleared by execut- IRCF bits were previously at a non-zero value, or ing a SLEEP or CLRWDT instruction, the loss of a INTSRC was set before the SLEEP instruction was currently selected clock source (if the Fail-Safe Clock executed and the INTOSC source was already stable, Monitor is enabled) and modifying the IRCF bits in the the IOFS bit will remain set. If the IRCF bits and OSCCON register if the internal oscillator block is the INTSRC are all clear, the INTOSC output will not be device clock source. enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. 4.5.3 EXIT BY RESET When a wake event occurs, the peripherals continue to Normally, the device is held in Reset by the Oscillator be clocked from the INTOSC multiplexer. After a delay Start-up Timer (OST) until the primary clock becomes of TCSD following the wake event, the CPU begins exe- ready. At that time, the OSTS bit is set and the device cuting code being clocked by the INTOSC multiplexer. begins executing code. If the internal oscillator block is The IDLEN and SCS bits are not affected by the the new clock source, the IOFS bit is set instead. wake-up. The INTRC source will continue to run if The exit delay time from Reset to the start of code either the WDT or the Fail-Safe Clock Monitor is execution depends on both the clock sources before enabled. and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are 4.5 Exiting Idle and Sleep Modes summarized in Table4-2. An exit from Sleep mode or any of the Idle modes is Code execution can begin before the primary clock triggered by an interrupt, a Reset or a WDT time-out. becomes ready. If either the Two-Speed Start-up (see This section discusses the triggers that cause exits Section25.3 “Two-Speed Start-up”) or Fail-Safe from power-managed modes. The clocking subsystem Clock Monitor (see Section25.4 “Fail-Safe Clock actions are discussed in each of the power-managed Monitor”) is enabled, the device may begin execution modes (see Section4.2 “Run Modes”, Section4.3 as soon as the Reset source has cleared. Execution is “Sleep Mode” and Section4.4 “Idle Modes”). clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the 4.5.1 EXIT BY INTERRUPT internal oscillator block until either the primary clock Any of the available interrupt sources can cause the becomes ready or a power-managed mode is entered device to exit from an Idle mode or the Sleep mode to before the primary clock becomes ready; the primary a Run mode. To enable this functionality, an interrupt clock is then shut down. source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. DS39637D-page 45

PIC18F2480/2580/4480/4580 4.5.4 EXIT WITHOUT AN OSCILLATOR In these instances, the primary clock source either START-UP DELAY does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not Certain exits from power-managed modes do not require an oscillator start-up delay (RC, EC and INTIO invoke the OST at all. There are two cases: Oscillator modes). However, a fixed delay of interval, • PRI_IDLE mode where the primary clock source TCSD, following the wake event is still required when is not stopped; and leaving Sleep and Idle modes to allow the CPU to • the primary clock source is not any of the LP, XT, prepare for execution. Instruction execution resumes HS or HSPLL modes. on the first clock cycle following this delay. TABLE 4-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Clock Source Clock Ready Status Exit Delay Before Wake-up After Wake-up bit (OSCCON) LP, XT, HS HSPLL OSTS Primary Device Clock EC, RC TCSD(2) (PRI_IDLE mode) INTRC(1) — INTOSC(3) IOFS LP, XT, HS TOST(4) HSPLL TOST + trc(4) OSTS T1OSC or INTRC(1) EC, RC TCSD(2) INTRC(1) — INTOSC(3) TIOBST(5) IOFS LP, XT, HS TOST(5) HSPLL TOST + trc(4) OSTS INTOSC(3) EC, RC TCSD(2) INTRC(1) — INTOSC(3) None IOFS LP, XT, HS TOST(4) HSPLL TOST + trc(4) OSTS None EC, RC (Sleep mode) TCSD(2) INTRC(1) — INTOSC(3) TIOBST(5) IOFS Note 1: In this instance, refers specifically to the 31kHz INTRC clock source. 2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section4.4 “Idle Modes”). 3: Includes both the INTOSC 8MHz source and postscaler derived frequencies. 4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is also designated as TPLL. 5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period. DS39637D-page 46 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 5.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure5-1. The PIC18F2480/2580/4480/4580 devices differentiate between various kinds of Reset: 5.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register5-1). The lower five bits of the regis- c) MCLR Reset during power-managed modes ter indicate that a specific Reset event has occurred. In d) Watchdog Timer (WDT) Reset (during most cases, these bits can only be cleared by the event execution) and must be set by the application after the event. The e) Programmable Brown-out Reset (BOR) state of these flag bits, taken together, can be read to f) RESET Instruction indicate the type of Reset that just occurred. This is described in more detail in Section5.6 “Reset State g) Stack Full Reset of Registers”. h) Stack Underflow Reset The RCON register also has control bits for setting This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the POR and BOR, and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in start-up timers. Stack Reset events are covered in Section10.0 “Interrupts”. BOR is covered in Section6.1.2.4 “Stack Full and Underflow Resets”. Section5.4 “Brown-out Reset (BOR)”. WDT Resets are covered in Section25.2 “Watchdog Timer (WDT)”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset BOREN S OST/PWRT OST 1024 Cycles Chip_Reset 10-Bit Ripple Counter R Q OSC1 32 μs PWRT 65.5 ms INTRC(1) 11-Bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table5-2 for time-out situations. © 2009 Microchip Technology Inc. DS39637D-page 47

PIC18F2480/2580/4480/4580 REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and reads as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section5.6 “Reset State of Registers” for additional information. Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39637D-page 48 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 5.2 Master Clear Reset (MCLR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. The MCLR pin is not driven low by any internal Resets, D R including the WDT. R1 MCLR In PIC18F2480/2580/4480/4580 devices, the MCLR input can be disabled with the MCLRE Configuration C PIC18FXXXX bit. When MCLR is disabled, the pin becomes a digital input. See Section11.5 “PORTE, TRISE and LATE Registers” for more information. Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. 5.3 Power-on Reset (POR) The diode D helps discharge the capacitor A Power-on Reset pulse is generated on-chip quickly when VDD powers down. whenever VDD rises above a certain threshold. This 2: R < 40kΩ is recommended to make sure that the voltage drop across R does not violate allows the device to start in the initialized state when the device’s electrical specification. VDD is adequate for operation. 3: R1 ≥ 1 kΩ will limit any current flowing into To take advantage of the POR circuitry, tie the MCLR MCLR from external capacitor C, in the event pin through a resistor (1kΩ to 10kΩ) to VDD. This will of MCLR/VPP pin breakdown, due to Electro- eliminate external RC components usually needed to static Discharge (ESD) or Electrical create a Power-on Reset delay. A minimum rise rate for Overstress (EOS). VDD is specified (parameter D004). For a slow rise time, see Figure5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. © 2009 Microchip Technology Inc. DS39637D-page 49

PIC18F2480/2580/4480/4580 5.4 Brown-out Reset (BOR) Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its PIC18F2480/2580/4480/4580 devices implement a environment without having to reprogram the device to BOR circuit that provides the user with a number of change BOR configuration. It also allows the user to configuration and power-saving options. The BOR is tailor device power consumption in software by elimi- controlled by the BORV<1:0> and BOREN<1:0> nating the incremental current that the BOR consumes. Configuration bits. There are a total of four BOR While the BOR current is typically very small, it may configurations which are summarized in Table5-1. have some impact in low-power applications. The BOR threshold is set by the BORV<1:0> bits. If Note: Even when BOR is under software control, BOR is enabled (any values of BOREN<1:0>, except the Brown-out Reset voltage level is still ‘00’), any drop of VDD below VBOR (parameter D005) set by the BORV<1:0> Configuration bits. for greater than TBOR (parameter 35) will reset the It cannot be changed in software. device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in 5.4.2 DETECTING BOR Brown-out Reset until VDD rises above VBOR. When Brown-out Reset is enabled, the BOR bit always If the Power-up Timer is enabled, it will be invoked after resets to ‘0’ on any Brown-out Reset or Power-on VDD rises above VBOR; it then will keep the chip in Reset event. This makes it difficult to determine if a Reset for an additional time delay, TPWRT Brown-out Reset event has occurred just by reading (parameter33). If VDD drops below VBOR while the the state of BOR alone. A more reliable method is to Power-up Timer is running, the chip will go back into a simultaneously check the state of both POR and BOR. Brown-out Reset and the Power-up Timer will be This assumes that the POR bit is reset to ‘1’ in software initialized. Once VDD rises above VBOR, the Power-up immediately after any Power-on Reset event. IF BOR Timer will execute the additional time delay. is ‘0’ while POR is ‘1’, it can be reliably assumed that a BOR and the Power-on Timer (PWRT) are Brown-out Reset event has occurred. independently configured. Enabling a Brown-out Reset does not automatically enable the PWRT. 5.4.3 DISABLING BOR IN SLEEP MODE When BOREN<1:0> = 10, the BOR remains under 5.4.1 SOFTWARE ENABLED BOR hardware control and operates as previously When BOREN<1:0> = 01, the BOR can be enabled or described. Whenever the device enters Sleep mode, disabled by the user in software. This is done with the however, the BOR is automatically disabled. When the control bit, SBOREN (RCON<6>). Setting SBOREN device returns to any other operating mode, BOR is enables the BOR to function as previously described. automatically re-enabled. Clearing SBOREN disables the BOR entirely. The This mode allows for applications to recover from SBOREN bit operates only in this mode; otherwise it is brown-out situations, while actively executing code, read as ‘0’. when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. TABLE 5-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled in software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. DS39637D-page 50 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 5.5 Device Reset Timers 5.5.3 PLL LOCK TIME-OUT PIC18F2480/2580/4480/4580 devices incorporate With the PLL enabled in its PLL mode, the time-out three separate on-chip timers that help regulate the sequence following a Power-on Reset is slightly differ- Power-on Reset process. Their main function is to ent from other oscillator modes. A separate timer is ensure that the device clock is stable before code is used to provide a fixed time-out that is sufficient for the executed. These timers are: PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the • Power-up Timer (PWRT) oscillator start-up time-out. • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 5.5.1 POWER-UP TIMER (PWRT) 1. After the POR pulse has cleared, PWRT The Power-up Timer (PWRT) of the PIC18F2480/2580/ time-out is invoked (if enabled). 4480/4580 devices is an 11-bit counter which uses the 2. Then, the OST is activated. INTRC source as the clock input. This yields an approximate time interval of 2048x32μs=65.6ms. The total time-out will vary based on oscillator configu- While the PWRT is counting, the device is held in ration and the status of the PWRT. Figure5-3, Reset. Figure5-4, Figure5-5, Figure5-6 and Figure5-7 all depict time-out sequences on power-up, with the The power-up time delay depends on the INTRC clock Power-up Timer enabled and the device operating in and will vary from chip-to-chip due to temperature and HS Oscillator mode. Figures5-3 through5-6 also apply process variation. See DC parameter 33 for details. to devices operating in XT or LP modes. For devices in The PWRT is enabled by clearing the PWRTEN RC mode and with the PWRT disabled, on the other Configuration bit. hand, there will be no time-out at all. 5.5.2 OSCILLATOR START-UP TIMER Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bring- (OST) ing MCLR high will begin execution immediately The Oscillator Start-up Timer (OST) provides a (Figure5-5). This is useful for testing purposes or to 1024oscillator cycle (from OSC1 input) delay after the synchronize more than one PIC18FXXXX device PWRT delay is over (parameter 33). This ensures that operating in parallel. the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset or on exit from most power-managed modes. TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. DS39637D-page 51

PIC18F2480/2580/4480/4580 FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39637D-page 52 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2009 Microchip Technology Inc. DS39637D-page 53

PIC18F2480/2580/4480/4580 5.6 Reset State of Registers Reset situations, as indicated in Table5-3. These bits are used in software to determine the nature of the Most registers are unaffected by a Reset. Their status Reset. is unknown on a Power-on Reset and unchanged by all Table5-4 describes the Reset states for all of the other Resets. The other registers are forced to a “Reset Special Function Registers. These are categorized by state” depending on the type of Reset that occurred. Power-on and Brown-out Resets, Master Clear and Most registers are not affected by a WDT wake-up, WDT Resets and WDT wake-ups. since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter(1) SBOREN RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR Reset during 0000h u(2) u 1 u u u u u Power-Managed Run modes MCLR Reset during 0000h u(2) u 1 0 u u u u Power-Managed Idle modes and Sleep mode WDT Time-out during Full Power 0000h u(2) u 0 u u u u u or Power-Managed Run modes MCLR Reset during Full-Power 0000h u(2) u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset 0000h u(2) u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u(2) u u u u u u 1 actual Reset, STVREN = 0) WDT Time-out during PC + 2 u(2) u 0 0 u u u u Power-Managed Idle or Sleep modes Interrupt Exit from PC + 2 u(2) u u 0 u u u u Power-Managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN<1:0> Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’. DS39637D-page 54 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets TOSU 2480 2580 4480 4580 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2480 2580 4480 4580 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2480 2580 4480 4580 ---0 0000 ---0 0000 ---u uuuu PCLATH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu PCL 2480 2580 4480 4580 0000 0000 0000 0000 PC + 2(2) TBLPTRU 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu TBLPTRH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu TABLAT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu PRODH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2480 2580 4480 4580 0000 000x 0000 000u uuuu uuuu(1) INTCON2 2480 2580 4480 4580 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 2480 2580 4480 4580 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 2480 2580 4480 4580 N/A N/A N/A POSTINC0 2480 2580 4480 4580 N/A N/A N/A POSTDEC0 2480 2580 4480 4580 N/A N/A N/A PREINC0 2480 2580 4480 4580 N/A N/A N/A PLUSW0 2480 2580 4480 4580 N/A N/A N/A FSR0H 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu FSR0L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2480 2580 4480 4580 N/A N/A N/A POSTINC1 2480 2580 4480 4580 N/A N/A N/A POSTDEC1 2480 2580 4480 4580 N/A N/A N/A PREINC1 2480 2580 4480 4580 N/A N/A N/A PLUSW1 2480 2580 4480 4580 N/A N/A N/A FSR1H 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu FSR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. DS39637D-page 55

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets BSR 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu INDF2 2480 2580 4480 4580 N/A N/A N/A POSTINC2 2480 2580 4480 4580 N/A N/A N/A POSTDEC2 2480 2580 4480 4580 N/A N/A N/A PREINC2 2480 2580 4480 4580 N/A N/A N/A PLUSW2 2480 2580 4480 4580 N/A N/A N/A FSR2H 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu FSR2L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2480 2580 4480 4580 ---x xxxx ---u uuuu ---u uuuu TMR0H 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu TMR0L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu OSCCON 2480 2580 4480 4580 0100 q000 0100 00q0 uuuu uuqu HLVDCON 2480 2580 4480 4580 0-00 0101 0-00 0101 0-uu uuuu WDTCON 2480 2580 4480 4580 ---- ---0 ---- ---0 ---- ---u RCON(4) 2480 2580 4480 4580 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2480 2580 4480 4580 0000 0000 u0uu uuuu uuuu uuuu TMR2 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu PR2 2480 2580 4480 4580 1111 1111 1111 1111 1111 1111 T2CON 2480 2580 4480 4580 -000 0000 -000 0000 -uuu uuuu SSPBUF 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu SSPCON1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu SSPCON2 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu ADRESH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu ADCON1 2480 2580 4480 4580 --00 0qqq --00 0qqq --uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. DS39637D-page 56 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets ADCON2 2480 2580 4480 4580 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu ECCPR1H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu ECCPR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu ECCP1CON 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu BAUDCON 2480 2580 4480 4580 01-0 0-00 01-0 0-00 --uu uuuu ECCP1DEL 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu CVRCON 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu CMCON 2480 2580 4480 4580 0000 0111 0000 0111 uuuu uuuu TMR3H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 2480 2580 4480 4580 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu SPBRG 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RCREG 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu TXREG 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu TXSTA 2480 2580 4480 4580 0000 0010 0000 0010 uuuu uuuu RCSTA 2480 2580 4480 4580 0000 000x 0000 000x uuuu uuuu EEADR 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu EEDATA 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu EECON2 2480 2580 4480 4580 0000 0000 0000 0000 0000 0000 EECON1 2480 2580 4480 4580 xx-0 x000 uu-0 u000 uu-0 u000 IPR3 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu PIR3 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu PIE3 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu IPR2 2480 2580 4480 4580 11-1 1111 11-1 1111 uu-u uuuu 2480 2580 4480 4580 1--1 111- 1--1 111- u--u uuu- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. DS39637D-page 57

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets PIR2 2480 2580 4480 4580 00-0 0000 00-0 0000 uu-u uuuu(1) 2480 2580 4480 4580 0--0 000- 0--0 000- u--u uuu-(1) PIE2 2480 2580 4480 4580 00-0 0000 00-0 0000 uu-u uuuu 2480 2580 4480 4580 0--0 000- 0--0 000- u--u uuu- IPR1 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu 2480 2580 4480 4580 -111 1111 -111 1111 -uuu uuuu PIR1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu(1) 2480 2580 4480 4580 -000 0000 -000 0000 -uuu uuuu PIE1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu 2480 2580 4480 4580 -000 0000 -000 0000 -uuu uuuu OSCTUNE 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu TRISE 2480 2580 4480 4580 0000 -111 0000 -111 uuuu -uuu TRISD 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu TRISC 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu TRISB 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2480 2580 4480 4580 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATE 2480 2580 4480 4580 ---- -xxx ---- -uuu ---- -uuu LATD 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 2480 2580 4480 4580 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTE 2480 2580 4480 4580 ---- x000 ---- x000 ---- uuuu PORTD 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2480 2580 4480 4580 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) ECANCON 2480 2580 4480 4580 0001 0000 0001 0000 uuuu uuuu TXERRCNT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXERRCNT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu COMSTAT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu CIOCON 2480 2580 4480 4580 --00 ---- --00 ---- --uu ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. DS39637D-page 58 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets BRGCON3 2480 2580 4480 4580 00-- -000 00-- -000 uu-- -uuu BRGCON2 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu BRGCON1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu CANCON 2480 2580 4480 4580 1000 000- 1000 000- uuuu uuu- CANSTAT 2480 2580 4480 4580 100- 000- 100- 000- uuu- uuu- RXB0D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0DLC 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu RXB0EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON 2480 2580 4480 4580 000- 0000 000- 0000 uuu- uuuu RXB1D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu RXB1EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. DS39637D-page 59

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets RXB1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON 2480 2580 4480 4580 000- 0000 000- 0000 uuu- uuuu TXB0D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0DLC 2480 2580 4480 4580 -x-- xxxx -u-- uuuu -u-- uuuu TXB0EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu TXB0SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu TXB0SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON 2480 2580 4480 4580 0000 0-00 0000 0-00 uuuu u-uu TXB1D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC 2480 2580 4480 4580 -x-- xxxx -u-- uuuu -u-- uuuu TXB1EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- uu-u TXB1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu TXB1CON 2480 2580 4480 4580 0000 0-00 0000 0-00 uuuu u-uu TXB2D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. DS39637D-page 60 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets TXB2D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2DLC 2480 2580 4480 4580 -x-- xxxx -u-- uuuu -u-- uuuu TXB2EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL 2480 2580 4480 4580 xxxx x-xx uuuu u-uu -uuu uuuu TXB2SIDH 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu TXB2CON 2480 2580 4480 4580 0000 0-00 0000 0-00 uuuu u-uu RXM1EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXM1EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXM1SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXM1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXM0SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. DS39637D-page 61

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets RXF3SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF2SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF1SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF0SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF0SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu B5EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B5SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu B5SIDH(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu B5CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu B4D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. DS39637D-page 62 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets B4D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu B4EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu B4SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu B3D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu B3EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu B3SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B3CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu B2D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. DS39637D-page 63

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets B2D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu B2EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu B2SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu B1D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu B1EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu B1SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B1CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu B0D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. DS39637D-page 64 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets B0EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu B0SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu TXBIE(6) 2480 2580 4480 4580 ---0 00-- ---u uu-- ---u uu-- BIE0(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu BSEL0(6) 2480 2580 4480 4580 0000 00-- 0000 00-- uuuu uu-- MSEL3(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu MSEL2(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu MSEL1(6) 2480 2580 4480 4580 0000 0101 0000 0101 uuuu uuuu MSEL0(6) 2480 2580 4480 4580 0101 0000 0101 0000 uuuu uuuu SDFLC(6) 2480 2580 4480 4580 ---0 0000 ---0 0000 -u-- uuuu RXFCON1(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXFCON0(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXFBCON7(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXFBCON6(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXFBCON5(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXFBCON4(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXFBCON3(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXFBCON2(6) 2480 2580 4480 4580 0001 0001 0001 0001 uuuu uuuu RXFBCON1(6) 2480 2580 4480 4580 0001 0001 0001 0001 uuuu uuuu RXFBCON0(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu RXF15EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF15EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF15SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF15SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF14EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF14EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF14SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF14SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. DS39637D-page 65

PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets RXF13EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF13EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF13SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF13SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF12EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF12EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF12SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF12SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF11SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF11SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF10EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF10EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF10SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu RXF10SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF9EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF9EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF9SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu RXF9SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF8EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF8EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF8SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu RXF8SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF7EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF7EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF7SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu RXF7SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF6EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF6EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu RXF6SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu RXF6SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. DS39637D-page 66 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are three types of memory in PIC18 Enhanced PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory upper boundary of the physically implemented memory • Data RAM and the 2-Mbyte address will return all ‘0’s (a NOP • Data EEPROM instruction). As Harvard architecture devices, the data and program The PIC18F2480 and PIC18F4480 each have memories use separate busses; this allows for con- 16Kbytes of Flash memory and can store up to current access of the two memory spaces. The data 8,192single-word instructions. The PIC18F2580 and EEPROM, for practical purposes, can be regarded as PIC18F4580 each have 32Kbytes of Flash memory a peripheral device, since it is addressed and accessed and can store up to 16,384 single-word instructions. through a set of control registers. PIC18 devices have two interrupt vectors. The Reset Additional detailed information on the operation of the vector address is at 0000h and the interrupt vector Flash program memory is provided in Section7.0 addresses are at 0008h and 0018h. “Flash Program Memory”. Data EEPROM is dis- The program memory maps for PIC18FX480 and cussed separately in Section8.0 “Data EEPROM PIC18FX580 devices are shown in Figure6-1. Memory”. FIGURE 6-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2480/2580/4480/4580 DEVICES PIC18FX480 PIC18FX580 PC<20:0> PC<20:0> CALL,RCALL,RETURN 21 CALL,RCALL,RETURN 21 RETFIE,RETLW RETFIE,RETLW Stack Level 1 Stack Level 1 ••• ••• Stack Level 31 Stack Level 31 Reset Vector 0000h Reset Vector 0000h High-Priority Interrupt Vector 0008h High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h Low-Priority Interrupt Vector 0018h On-Chip Program Memory 3FFFh On-Chip 4000h Program Memory e e ac ac p p S S y y or or m m e 7FFFh e M M er 80000h er Us Us Read ‘0’ Read ‘0’ 1FFFFFh 1FFFFFh 200000h 200000h © 2009 Microchip Technology Inc. DS39637D-page 67

PIC18F2480/2580/4480/4580 6.1.1 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the low byte, known as the PCL register, is both readable Top-Of-Stack (TOF) Special File Registers. Data can and writable. The high byte, or PCH register, contains also be pushed to, or popped from the stack, using the PC<15:8> bits; it is not directly readable or writable. these registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack; register contains the PC<20:16> bits; it is also not the Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack; the contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section6.1.4.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full or has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 6.1.2.1 Top-of-Stack Access a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is readable and writable. A set of three registers, The CALL, RCALL and GOTO program branch TOSU:TOSH:TOSL, hold the contents of the stack loca- instructions write to the program counter directly. For tion pointed to by the STKPTR register (Figure6-2). This these instructions, the contents of PCLATH and allows users to implement a software stack if necessary. PCLATU are not transferred to the program counter. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL 6.1.2 RETURN ADDRESS STACK registers. These values can be placed on a user-defined The return address stack allows any combination of up software stack. At return time, the software can return to 31 program calls and interrupts to occur. The PC is these values to TOSU:TOSH:TOSL and do a return. pushed onto the stack when a CALL or RCALL instruc- The user must disable the global interrupt enable bits tion is executed or an interrupt is Acknowledged. The while accessing the stack to prevent inadvertent stack PC value is pulled off the stack on a RETURN, RETLW corruption. or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 DS39637D-page 68 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 6.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register6-1) contains the Stack to the PC and sets the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bits. The value set until cleared by software or until a POR occurs. of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 6.1.2.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack Over- the stack without disturbing normal program execution flow Reset Enable) Configuration bit. (Refer to is a desirable feature. The PIC18 instruction set Section25.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by decre- Any additional pushes will not overwrite the 31st push menting the Stack Pointer. The previous value pushed and STKPTR will remain at 31. onto the stack then becomes the TOS value. REGISTER 6-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. © 2009 Microchip Technology Inc. DS39637D-page 69

PIC18F2480/2580/4480/4580 6.1.2.4 Stack Full and Underflow Resets 6.1.4 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow will set the appropriate STKFUL or program memory. For PIC18 devices, look-up tables STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 6.1.4.1 Computed GOTO 6.1.3 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example6-2. WREG and BSR registers, to provide a “fast return” option for interrupts. Each stack is only one level deep A look-up table can be formed with an ADDWF PCL and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The current value of the corresponding register when the W register is loaded with an offset into the table before processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the will push values into the stack registers. The values in called routine is the ADDWF PCL instruction. The next the registers are then loaded back into their associated instruction executed will be one of the RETLW nn registers, if the RETFIE, FAST instruction is used to instructions, that returns the value ‘nn’ to the calling return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of stack registers cannot be used reliably to return from bytes that the program counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low-priority interrupt, the stack In this method, only one data byte may be stored in register values stored by the low-priority interrupt will each instruction location and room on the return be overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 6-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example6-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 6.1.4.2 Table Reads and Table Writes EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word by using table reads and writes. The • Table Pointer (TBLPTR) register specifies the byte • address and the Table Latch (TABLAT) register con- tains the data that is read from or written to program SUB1 • memory. Data is transferred to or from program • memory one byte at a time. RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Table read and table write operations are discussed further in Section7.1 “Table Reads and Table Writes”. DS39637D-page 70 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an inter- pipelined in such a manner that a fetch takes one nal or external source, is internally divided by four to instruction cycle, while the decode and execute take generate four non-overlapping quadrature clocks (Q1, another instruction cycle. However, due to the Q2, Q3 and Q4). Internally, the Program Counter (PC) pipelining, each instruction effectively executes in one is incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to from the program memory and latched into the Instruc- change (e.g., GOTO), then two cycles are required to tion Register (IR) during Q4. The instruction is decoded complete the instruction (Example6-3). and executed during the following Q1 through Q4. The A fetch cycle begins with the program counter clocks and instruction execution flow are shown in incrementing in Q1. Figure6-3. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 Phase Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. DS39637D-page 71

PIC18F2480/2580/4480/4580 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute pro- MEMORY gram memory address embedded into the instruction. Since instructions are always stored on word bound- The program memory is addressed in bytes. Instruc- aries, the data contained in the instruction is a word tions are stored as two bytes or four bytes in program address. The word address is written to PC<20:1>, memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure6-4 shows how the with an even address (LSB = 0). To maintain alignment instruction, GOTO 0006h, is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSB will always read ‘0’ (see Section6.1.1 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure6-4 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section26.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-4: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, The standard PIC18 instruction set has four, two-word a NOP is executed instead. This is necessary for cases instructions: CALL, MOVFF, GOTO and LSFR. In all when the two-word instruction is preceded by a condi- cases, the second word of the instructions always has tional instruction that changes the PC. Example6-4 ‘1111’ as its four Most Significant bits; the other 12 bits shows how this works. are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction spec- Note: See Section6.5 “Program Memory and ifies a special form of NOP. If the instruction is executed the Extended Instruction Set” for infor- mation on two-word instructions in the in proper sequence – immediately after the first word – the data in the second word is accessed and used by extended instruction set. EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code DS39637D-page 72 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 6.3 Data Memory Organization 6.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.6 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16 banks that contain 256 bytes each; of the Bank Pointer, known as the Bank Select Register PIC18F2480/2580/4480/4580 devices implement all (BSR). This SFR holds the 4 Most Significant bits of a 16 banks. Figure6-6 shows the data memory location’s address; the instruction itself includes the organization for the PIC18F2480/2580/4480/4580 8Least Significant bits. Only the four lower bits of the devices. BSR are implemented (BSR<3:0>). The upper four bits The data memory contains Special Function Registers are unused; they will always read ‘0’ and cannot be (SFRs) and General Purpose Registers (GPRs). The written to. The BSR can be loaded directly by using the SFRs are used for control and status of the controller MOVLB instruction. and peripheral functions, while GPRs are used for data The value of the BSR indicates the bank in data mem- storage and scratchpad operations in the user’s appli- ory; the 8 bits in the instruction show the location in the cation. Any read of an unimplemented location will read bank and can be thought of as an offset from the bank’s as ‘0’s. lower boundary. The relationship between the BSR’s The instruction set and architecture allow operations value and the bank division in data memory is shown in across all banks. The entire data memory may be Figure6-7. accessed by Direct, Indirect or Indexed Addressing Since up to 16 registers may share the same low-order modes. Addressing modes are discussed later in this address, the user must always be careful to ensure that subsection. the proper bank is selected before performing a data To ensure that commonly used registers (SFRs and read or write. For example, writing what should be select GPRs) can be accessed in a single cycle, PIC18 program data to an 8-bit address of F9h, while the BSR devices implement an Access Bank. This is a 256-byte is 0Fh will end up resetting the Program Counter. memory space that provides fast access to SFRs and While any bank can be selected, only those banks that the lower portion of GPR Bank 0 without using the are actually implemented can be read or written to. BSR. Section6.3.2 “Access Bank” provides a Writes to unimplemented banks are ignored, while detailed description of the Access RAM. reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure6-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. DS39637D-page 73

PIC18F2480/2580/4480/4580 FIGURE 6-5: DATA MEMORY MAP FOR PIC18F2480/4480 DEVICES When a = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 128 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 128 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR When a = 1: FFh 2FFh = 0011 00h 300h The BSR specifies the Bank Bank 3 used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 FFh 4FFh = 0101 00h 500h Bank 5 FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 5Fh FFh Unimplemented 7FFh Access RAM High 60h = 1000 00h Read as ‘0’ 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h 900h Bank 9 FFh 9FFh = 1010 00h A00h Bank 10 FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 CAN SFRs DFFh FFh 00h E00h = 1110 Bank 14 CAN SFRs FFh EFFh = 1111 00h CAN SFRs FF50F0hh Bank 15 F60h FFh SFR FFFh DS39637D-page 74 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 6-6: DATA MEMORY MAP FOR PIC18F2580/4580 DEVICES When a = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 128 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 128 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR When a = 1: FFh 2FFh = 0011 00h 300h The BSR specifies the Bank Bank 3 GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh = 0101 00h 500h Bank 5 GPR FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 5Fh FFh 7FFh Access RAM High 60h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h 900h Bank 9 Unimplemented Read as ‘0’ FFh 9FFh = 1010 00h A00h Bank 10 FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 CAN SFRs DFFh FFh 00h E00h = 1110 Bank 14 CAN SFRs FFh EFFh = 1111 00h CAN SFRs FF50F0hh Bank 15 F60h FFh SFR FFFh © 2009 Microchip Technology Inc. DS39637D-page 75

PIC18F2480/2580/4480/4580 FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) Data Memory From Opcode(2) 7 0 000h 00h 7 0 0 0 0 0 0 0 1 1 Bank 0 FFh 1 1 1 1 1 1 1 1 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK however, the instruction is forced to use the Access Bank address map; the current value of the BSR is While the use of the BSR with an embedded 8-bit ignored entirely. address allows users to address the entire range of data memory, it also means that the user must always Using this “forced” addressing allows the instruction to ensure that the correct bank is selected. Otherwise, operate on a data address in a single cycle, without data may be read from or written to the wrong location. updating the BSR first. For 8-bit addresses of 80h and This can be disastrous if a GPR is the intended target above, this means that users can evaluate and operate of an operation, but an SFR is written to instead. on SFRs more efficiently. The Access RAM below 80h Verifying and/or changing the BSR for each read or is a good place for data values that the user might need write to data memory can become very inefficient. to access rapidly, such as immediate computational results or common program variables. Access RAM To streamline access for the most commonly used data also allows for faster and more code efficient context memory locations, the data memory is configured with saving and switching of variables. an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different The Access Bank consists of the first 128 bytes of when the extended instruction set is enabled (XINST memory (00h-7Fh) in Bank 0 and the last 128 bytes of Configuration bit = 1). This is discussed in more detail memory (80h-FFh) in Block 15. The lower half is known in Section6.6.3 “Mapping the Access Bank in as the “Access RAM” and is composed of GPRs. The Indexed Literal Offset Mode”. upper half is where the device’s SFRs are mapped. 6.3.3 GENERAL PURPOSE These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion REGISTER FILE by an 8-bit address (Figure6-6). PIC18 devices may have banked memory in the GPR The Access Bank is used by core PIC18 instructions area. This is data RAM, which is available for use by all that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0 the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom uses the BSR and the 8-bit address included in the of the SFR area. GPRs are not initialized by a opcode for the data memory address. When ‘a’ is ‘0’ Power-on Reset and are unchanged on all other Resets. DS39637D-page 76 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 6.3.4 SPECIAL FUNCTION REGISTERS peripheral functions. The reset and interrupt registers are described in their respective chapters, while the The Special Function Registers (SFRs) are registers ALU’s STATUS register is described later in this used by the CPU and peripheral modules for controlling section. Registers related to the operation of a the desired operation of the device. These registers are peripheral feature are described in the chapter for that implemented as static RAM. SFRs start at the top of peripheral. data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these The SFRs are typically distributed among the registers is given in Table6-1 and Table6-2. peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(3) FBFh ECCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(3) FBEh ECCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H(1) F9Ch — FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L(1) F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh ECCP1CON(1) F9Ah — FF9h PCL FD9h FSR2L FB9h — F99h — FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h — FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL F97h — FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(1) F96h TRISE(1) FF5h TABLAT FD5h T0CON FB5h CVRCON(1) F95h TRISD(1) FF4h PRODH FD4h — FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h — FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h — FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh — FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh — FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE(1) FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD(1) FEBh PLUSW0(3) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh — F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h — FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2(3) F87h — FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h — FE5h POSTDEC1(3) FC5h SSPCON2 FA5h IPR3 F85h — FE4h PREINC1(3) FC4h ADRESH FA4h PIR3 F84h PORTE FE3h PLUSW1(3) FC3h ADRESL FA3h PIE3 F83h PORTD(1) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. DS39637D-page 77

PIC18F2480/2580/4480/4580 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address Name Address Name Address Name F7Fh — F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL F7Eh — F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH F7Dh — F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch — F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh — F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah — F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h — F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h — F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh CANCON_RO1 F2Fh CANCON_RO3 F0Fh RXF3EIDL F6Eh CANSTAT F4Eh CANSTAT_RO1 F2Eh CANSTAT_RO3 F0Eh RXF3EIDH F6Dh RXB0D7 F4DH TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. DS39637D-page 78 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address Name Address Name Address Name EFFh — EDFh — EBFh — E9Fh — EFEh — EDEh — EBEh — E9Eh — EFDh — EDDh — EBDh — E9Dh — EFCh — EDCh — EBCh — E9Ch — EFBh — EDBh — EBBh — E9Bh — EFAh — EDAh — EBAh — E9Ah — EF9h — ED9h — EB9h — E99h — EF8h — ED8h — EB8h — E98h — EF7h — ED7h — EB7h — E97h — EF6h — ED6h — EB6h — E96h — EF5h — ED5h — EB5h — E95h — EF4h — ED4h — EB4h — E94h — EF3h — ED3h — EB3h — E93h — EF2h — ED2h — EB2h — E92h — EF1h — ED1h — EB1h — E91h — EF0h — ED0h — EB0h — E90h — EEFh — ECFh — EAFh — E8Fh — EEEh — ECEh — EAEh — E8Eh — EEDh — ECDh — EADh — E8Dh — EECh — ECCh — EACh — E8Ch — EEBh — ECBh — EABh — E8Bh — EEAh — ECAh — EAAh — E8Ah — EE9h — EC9h — EA9h — E89h — EE8h — EC8h — EA8h — E88h — EE7h — EC7h — EA7h — E87h — EE6h — EC6h — EA6h — E86h — EE5h — EC5h — EA5h — E85h — EE4h — EC4h — EA4h — E84h — EE3h — EC3h — EA3h — E83h — EE2h — EC2h — EA2h — E82h — EE1h — EC1h — EA1h — E81h — EE0h — EC0h — EA0h — E80h — Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. DS39637D-page 79

PIC18F2480/2580/4480/4580 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address Name Address Name Address Name E7Fh CANCON_RO4 E6Fh CANCON_RO5 E5Fh CANCON_RO6 E4Fh CANCON_RO7 E7Eh CANSTAT_RO4 E6Eh CANSTAT_RO5 E5Eh CANSTAT_RO6 E4Eh CANSTAT_RO7 E7Dh B5D7(2) E6Dh B4D7(2) E5Dh B3D7(2) E4Dh B2D7(2) E7Ch B5D6(2) E6Ch B4D6(2) E5Ch B3D6(2) E4Ch B2D6(2) E7Bh B5D5(2) E6Bh B4D5(2) E5Bh B3D5(2) E4Bh B2D5(2) E7Ah B5D4(2) E6Ah B4D4(2) E5Ah B3D4(2) E4Ah B2D4(2) E79h B5D3(2) E69h B4D3(2) E59h B3D3(2) E49h B2D3(2) E78h B5D2(2) E68h B4D2(2) E58h B3D2(2) E48h B2D2(2) E77h B5D1(2) E67h B4D1(2) E57h B3D1(2) E47h B2D1(2) E76h B5D0(2) E66h B4D0(2) E56h B3D0(2) E46h B2D0(2) E75h B5DLC(2) E65h B4DLC(2) E55h B3DLC(2) E45h B2DLC(2) E74h B5EIDL(2) E64h B4EIDL(2) E54h B3EIDL(2) E44h B2EIDL(2) E73h B5EIDH(2) E63h B4EIDH(2) E53h B3EIDH(2) E43h B2EIDH(2) E72h B5SIDL(2) E62h B4SIDL(2) E52h B3SIDL(2) E42h B2SIDL(2) E71h B5SIDH(2) E61h B4SIDH(2) E51h B3SIDH(2) E41h B2SIDH(2) E70h B5CON (2) E60h B4CON(2) E50h B3CON(2) E40h B2CON(2) E3Fh CANCON_RO8 E2Fh CANCON_RO9 E1Fh — E0Fh — E3Eh CANSTAT_RO8 E2Eh CANSTAT_RO9 E1Eh — E0Eh — E3Dh B1D7(2) E2Dh B0D7(2) E1Dh — E0Dh — E3Ch B1D6(2) E2Ch B0D6(2) E1Ch — E0Ch — E3Bh B1D5(2) E2Bh B0D5(2) E1Bh — E0Bh — E3Ah B1D4(2) E2Ah B0D4(2) E1Ah — E0Ah — E39h B1D3(2) E29h B0D3(2) E19h — E09h — E38h B1D2(2) E28h B0D2(2) E18h — E08h — E37h B1D1(2) E27h B0D1(2) E17h — E07h — E36h B1D0(2) E26h B0D0(2) E16h — E06h — E35h B1DLC(2) E25h B0DLC(2) E15h — E05h — E34h B1EIDL(2) E24h B0EIDL(2) E14h — E04h — E33h B1EIDH(2) E23h B0EIDH(2) E13h — E03h — E32h B1SIDL(2) E22h B0SIDL(2) E12h — E02h — E31h B1SIDH(2) E21h B0SIDH(2) E11h — E01h — E30h B1CON(2) E20h B0CON(2) E10h — E00h — Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. DS39637D-page 80 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address Name Address Name Address Name DFFh — DDFh — DBFh — D9Fh — DFEh — DDEh — DBEh — D9Eh — DFDh — DDDh — DBDh — D9Dh — DFCh TXBIE DDCh — DBCh — D9Ch — DFBh — DDBh — DBBh — D9Bh — DFAh BIE0 DDAh — DBAh — D9Ah — DF9h — DD9h — DB9h — D99h — DF8h BSEL0 DD8h SDFLC DB8h — D98h — DF7h — DD7h — DB7h — D97h — DF6h — DD6h — DB6h — D96h — DF5h — DD5h RXFCON1 DB5h — D95h — DF4h — DD4h RXFCON0 DB4h — D94h — DF3h MSEL3 DD3h — DB3h — D93h RXF15EIDL DF2h MSEL2 DD2h — DB2h — D92h RXF15EIDH DF1h MSEL1 DD1h — DB1h — D91h RXF15SIDL DF0h MSEL0 DD0h — DB0h — D90h RXF15SIDH DEFh — DCFh — DAFh — D8Fh — DEEh — DCEh — DAEh — D8Eh — DEDh — DCDh — DADh — D8Dh — DECh — DCCh — DACh — D8Ch — DEBh — DCBh — DABh — D8Bh RXF14EIDL DEAh — DCAh — DAAh — D8Ah RXF14EIDH DE9h — DC9h — DA9h — D89h RXF14SIDL DE8h — DC8h — DA8h — D88h RXF14SIDH DE7h RXFBCON7 DC7h — DA7h — D87h RXF13EIDL DE6h RXFBCON6 DC6h — DA6h — D86h RXF13EIDH DE5h RXFBCON5 DC5h — DA5h — D85h RXF13SIDL DE4h RXFBCON4 DC4h — DA4h — D84h RXF13SIDH DE3h RXFBCON3 DC3h — DA3h — D83h RXF12EIDL DE2h RXFBCON2 DC2h — DA2h — D82h RXF12EIDH DE1h RXFBCON1 DC1h — DA1h — D81h RXF12SIDL DE0h RXFBCON0 DC0h — DA0h — D80h RXF12SIDH Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. DS39637D-page 81

PIC18F2480/2580/4480/4580 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name D7Fh — D7Eh — D7Dh — D7Ch — D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh — D6Eh — D6Dh — D6Ch — D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7SIDL D64h RXF7SIDH D63h RXF6EIDL D62h RXF6EIDH D61h RXF6SIDL D60h RXF6SIDH Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. DS39637D-page 82 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 55, 68 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 55, 68 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 55, 68 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 55, 69 PCLATU — — bit 21(1) Holding Register for PC<20:16> ---0 0000 55, 68 PCLATH Holding Register for PC<15:8> 0000 0000 55, 68 PCL PC Low Byte (PC<7:0>) 0000 0000 55, 68 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 55, 109 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 55, 109 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 55, 109 TABLAT Program Memory Table Latch 0000 0000 55, 109 PRODH Product Register High Byte xxxx xxxx 55, 117 PRODL Product Register Low Byte xxxx xxxx 55, 117 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 55, 121 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 55, 122 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 55, 123 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 55, 96 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 55, 97 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 55, 97 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 55, 97 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register), value of N/A 55, 97 FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- xxxx 55, 96 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 55, 96 WREG Working Register xxxx xxxx 55 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 55, 96 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 55, 97 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 55, 97 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 55, 97 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register), value of N/A 55, 97 FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- xxxx 55, 96 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 55, 96 BSR — — — — Bank Select Register ---- 0000 56, 73 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 56, 96 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 56, 97 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 56, 97 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 56, 97 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register), value of N/A 56, 97 FSR2 offset by W Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 83

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- xxxx 56, 96 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 56, 96 STATUS — — — N OV Z DC C ---x xxxx 56, 94 TMR0H Timer0 Register High Byte 0000 0000 56, 153 TMR0L Timer0 Register Low Byte xxxx xxxx 56, 153 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 56, 153 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 36, 56 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 56, 273 WDTCON — — — — — — — SWDTEN --- ---0 56, 359 RCON IPEN SBOREN(2) — RI TO PD POR BOR 0q-1 11q0 56, 133 TMR1H Timer1 Register High Byte xxxx xxxx 56, 159 TMR1L Timer1 Register Low Byte 0000 0000 56, 159 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 56, 155 TMR2 Timer2 Register 1111 1111 56, 162 PR2 Timer2 Period Register -000 0000 56, 159 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 56, 161 SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 56, 199 SSPADD MSSP Address Register in I2C Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 56, 199 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 56, 201 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 56, 202 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 56, 203 ADRESH A/D Result Register High Byte xxxx xxxx 56, 262 ADRESL A/D Result Register Low Byte xxxx xxxx 56, 262 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 56, 253 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 56, 254 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 57, 255 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 57, 172 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 57, 172 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 57, 167 ECCPR1H(9) Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 57, 171 ECCPR1L(9) Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 57, 171 ECCP1CON(9) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 57, 172 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0000 57, 234 ECCP1DEL(9) PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3) 0000 0000 57, 187 ECCP1AS(9) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3) 0000 0000 57, 187 CVRCON(9) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 57, 269 CMCON(9) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 57, 263 TMR3H Timer3 Register High Byte xxxx xxxx 57, 165 TMR3L Timer3 Register Low Byte xxxx xxxx 57, 165 T3CON RD16 T3ECCP1(9) T3CKPS1 T3CKPS0 T3CCP1(9) T3SYNC TMR3CS TMR3ON 0000 0000 57, 165 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. DS39637D-page 84 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: SPBRGH EUSART Baud Rate Generator High Byte 0000 0000 57, 236 SPBRG EUSART Baud Rate Generator 0000 0000 57, 236 RCREG EUSART Receive Register 0000 0000 57, 244 TXREG EUSART Transmit Register 0000 0000 57, 241 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 57, 243 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 57, 243 EEADR EEPROM Address Register 0000 0000 57, 111 EEDATA EEPROM Data Register 0000 0000 57, 111 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 57, 111 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 57, 111 IPR3 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP 1111 1111 57, 132 Mode 0 IPR3 IRXIP WAKIP ERRIP TXBnIP TXB1IP(8) TXB0IP(8) RXBnIP FIFOWMIP 1111 1111 57, 132 Mode 1, 2 PIR3 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 0000 0000 57, 126 Mode 0 PIR3 IRXIF WAKIF ERRIF TXBnIF TXB1IF(8) TXB0IF(8) RXBnIF FIFOWMIF 0000 0000 57, 126 Mode 1, 2 PIE3 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE 0000 0000 57, 129 Mode 0 PIE3 IRXIE WAKIE ERRIE TXBnIE TXB1IE(8) TXB0IE(8) RXBnIE FIFOMWIE 0000 0000 57, 129 Mode 1, 2 IPR2 OSCFIP CMIP(9) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(9) 11-1 1111 57, 131 PIR2 OSCFIF CMIF(9) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(9) 00-0 0000 58, 125 PIE2 OSCFIE CMIE(9) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(9) 00-0 0000 58, 128 IPR1 PSPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 58, 130 PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 58, 124 PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 58, 127 OSCTUNE INTSRC PLLEN(4) — TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 33, 58 TRISE(3) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 58, 146 TRISD(3) PORTD Data Direction Register 1111 1111 58, 143 TRISC PORTC Data Direction Register 1111 1111 58, 141 TRISB PORTB Data Direction Register 1111 1111 58, 138 TRISA TRISA7(6) TRISA6(6) PORTA Data Direction Register 1111 1111 58, 135 LATE(3) — — — — — LATE2 LATE1 LATE0 ---- -xxx 58, 146 LATD(3) LATD Output Latch Register xxxx xxxx 58, 143 LATC LATC Output Latch Register xxxx xxxx 58, 141 LATB LATB Output Latch Register xxxx xxxx 58, 138 LATA LATA7(6) LATA6(6) LATA Output Latch Register xxxx xxxx 58, 135 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 85

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: PORTE(3) — — — — RE3(5) RE2(3) RE1(3) RE0(3) ---- xxxx 58, 150 PORTD(3) PORTD Data Direction Register xxxx xxxx 58, 143 PORTC PORTC Data Direction Register xxxx xxxx 58, 141 PORTB PORTB Data Direction Register xxxx xxxx 58, 138 PORTA RA7(6) RA6(6) PORTA Data Direction Register xx00 0000 58, 135 ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 0001 000 58, 286 TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 0000 0000 58, 291 RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0000 0000 58, 299 COMSTAT RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 58, 287 Mode 0 COMSTAT — RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN -000 0000 58, 287 Mode 1 COMSTAT FIFOEMPTY RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 58, 287 Mode 2 CIOCON — — ENDRHI CANCAP — — — — --00 ---- 58, 320 BRGCON3 WAKDIS WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 00-- -000 59, 319 BRGCON2 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 59, 318 BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000 59, 317 CANCON REQOP2 REQOP1 REQOP0 ABAT WIN2(7) WIN1(7) WIN0(7) —(7) 1000 000- 59, 282 Mode 0 CANCON REQOP2 REQOP1 REQOP0 ABAT —(7) —(7) —(7) —(7) 1000 ---- 59, 282 Mode 1 CANCON REQOP2 REQOP1 REQOP0 ABAT FP3(7) FP2(7) FP1(7) FP0(7) 1000 0000 59, 282 Mode 2 CANSTAT OPMODE2 OPMODE1 OPMODE0 —(7) ICODE3(7) ICODE2(7) ICODE1(7) —(7) 000- 0000 59, 283 Mode 0 CANSTAT OPMODE2 OPMODE1 OPMODE0 EICODE4(7) EICODE3(7) EICODE2(7) EICODE1(7) EICODE0(7) 0000 0000 59, 283 Modes 1, 2 RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx 59, 298 RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 xxxx xxxx 59, 298 RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 xxxx xxxx 59, 298 RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 xxxx xxxx 59, 298 RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 xxxx xxxx 59, 298 RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 xxxx xxxx 59, 298 RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 xxxx xxxx 59, 298 RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 xxxx xxxx 59, 298 RXB0DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 59, 298 RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 59, 297 RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 59, 297 RXB0SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 59, 297 RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 59, 296 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. DS39637D-page 86 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: RXB0CON RXFUL RXM1 RXM0(7) —(7) RXRTRRO(7) RXBODBEN(7) JTOFF(7) FILHIT0(7) 000- 0000 59, 293 Mode 0 RXB0CON RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 59, 293 Mode 1, 2 RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 xxxx xxxx 59, 298 RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 xxxx xxxx 59, 298 RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx 59, 298 RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx 59, 298 RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx 59, 298 RXB1D2 RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 xxxx xxxx 59, 298 RXB1D1 RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 xxxx xxxx 59, 298 RXB1D0 RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 xxxx xxxx 59, 298 RXB1DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 59, 298 RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 59, 297 RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 59, 297 RXB1SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx xxxx 59, 297 RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 296 RXB1CON RXFUL RXM1 RXM0(7) —(7) RXRTRRO(7) FILHIT2(7) FILHIT1(7) FILHIT0(7) 000- 0000 60, 293 Mode 0 RXB1CON RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 60, 293 Mode 1, 2 TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 xxxx xxxx 60, 290 TXB0D6 TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 xxxx xxxx 60, 290 TXB0D5 TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 xxxx xxxx 60, 290 TXB0D4 TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 xxxx xxxx 60, 290 TXB0D3 TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 xxxx xxxx 60, 290 TXB0D2 TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 xxxx xxxx 60, 290 TXB0D1 TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 xxxx xxxx 60, 290 TXB0D0 TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 xxxx xxxx 60, 290 TXB0DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 60, 291 TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 290 TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 289 TXB0SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 60, 289 TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 289 TXB0CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 60, 288 TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx xxxx 60, 290 TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 xxxx xxxx 60, 290 TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 xxxx xxxx 60, 290 TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 xxxx xxxx 60, 290 TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxxx xxxx 60, 290 TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 xxxx xxxx 60, 290 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 87

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx 60, 290 TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx 60, 290 TXB1DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 60, 291 TXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 60, 290 TXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 60, 289 TXB1SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 60, 289 TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 60, 289 TXB1CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 60, 288 TXB2D7 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 60, 290 TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx 61, 290 TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx 61, 290 TXB2D4 TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx 61, 290 TXB2D3 TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx 61, 290 TXB2D2 TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx 61, 290 TXB2D1 TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx 61, 290 TXB2D0 TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx 61, 290 TXB2DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 61, 291 TXB2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 61, 290 TXB2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 61, 289 TXB2SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx x-xx 61, 289 TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxx- x-xx 61, 289 TXB2CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 61, 288 RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 61, 310 RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 61, 310 RXM1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 61, 310 RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 61, 310 RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 61, 310 RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 61, 310 RXM0SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 61, 310 RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 61, 309 RXF5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 61, 309 RXF5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 61, 309 RXF5SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 61, 308 RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 61, 308 RXF4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 61, 309 RXF4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 61, 309 RXF4SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 61, 308 RXF4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 61, 308 RXF3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 61, 309 RXF3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 61, 309 RXF3SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 62, 308 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. DS39637D-page 88 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 62, 308 RXF2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 62, 309 RXF2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 62, 309 RXF2SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 62, 308 RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 62, 308 RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 62, 309 RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 62, 309 RXF1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 62, 308 RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 62, 308 RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 62, 309 RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 62, 309 RXF0SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 62, 308 RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 62, 308 B5D7(8) B5D77 B5D76 B5D75 B5D74 B5D73 B5D72 B5D71 B5D70 xxxx xxxx 62, 305 B5D6(8) B5D67 B5D66 B5D65 B5D64 B5D63 B5D62 B5D61 B5D60 xxxx xxxx 62, 305 B5D5(8) B5D57 B5D56 B5D55 B5D54 B5D53 B5D52 B5D51 B5D50 xxxx xxxx 62, 305 B5D4(8) B5D47 B5D46 B5D45 B5D44 B5D43 B5D42 B5D41 B5D40 xxxx xxxx 62, 305 B5D3(8) B5D37 B5D36 B5D35 B5D34 B5D33 B5D32 B5D31 B5D30 xxxx xxxx 62, 305 B5D2(8) B5D27 B5D26 B5D25 B5D24 B5D23 B5D22 B5D21 B5D20 xxxx xxxx 62, 305 B5D1(8) B5D17 B5D16 B5D15 B5D14 B5D13 B5D12 B5D11 B5D10 xxxx xxxx 62, 305 B5D0(8) B5D07 B5D06 B5D05 B5D04 B5D03 B5D02 B5D01 B5D00 xxxx xxxx 62, 305 B5DLC(8) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 62, 307 Receive mode B5DLC(8) — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 62, 307 Transmit mode B5EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 62, 305 B5EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 62, 304 B5SIDL(8) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 62, 303 Receive mode B5SIDL(8) SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 62, 303 Transmit mode B5SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx x-xx 62, 302 B5CON(8) RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 62, 301 Receive mode B5CON(8) TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 62, 301 Transmit mode B4D7(8) B4D77 B4D76 B4D75 B4D74 B4D73 B4D72 B4D71 B4D70 xxxx xxxx 62, 305 B4D6(8) B4D67 B4D66 B4D65 B4D64 B4D63 B4D62 B4D61 B4D60 xxxx xxxx 62, 305 B4D5(8) B4D57 B4D56 B4D55 B4D54 B4D53 B4D52 B4D51 B4D50 xxxx xxxx 62, 305 B4D4(8) B4D47 B4D46 B4D45 B4D44 B4D43 B4D42 B4D41 B4D40 xxxx xxxx 63, 305 B4D3(8) B4D37 B4D36 B4D35 B4D34 B4D33 B4D32 B4D31 B4D30 xxxx xxxx 63, 305 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 89

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: B4D2(8) B4D27 B4D26 B4D25 B4D24 B4D23 B4D22 B4D21 B4D20 xxxx xxxx 63, 305 B4D1(8) B4D17 B4D16 B4D15 B4D14 B4D13 B4D12 B4D11 B4D10 xxxx xxxx 63, 305 B4D0(8) B4D07 B4D06 B4D05 B4D04 B4D03 B4D02 B4D01 B4D00 xxxx xxxx 62, 305 B4DLC(8) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 63, 307 Receive mode B4DLC(8) — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 63, 307 Transmit mode B4EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 63, 305 B4EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 63, 304 B4SIDL(8) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 63, 303 Receive mode B4SIDL(8) SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 63, 303 Transmit mode B4SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 63, 302 B4CON(8) RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 63, 301 Receive mode B4CON(8) TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 63, 301 Transmit mode B3D7(8) B3D77 B3D76 B3D75 B3D74 B3D73 B3D72 B3D71 B3D70 xxxx xxxx 63, 305 B3D6(8) B3D67 B3D66 B3D65 B3D64 B3D63 B3D62 B3D61 B3D60 xxxx xxxx 63, 305 B3D5(8) B3D57 B3D56 B3D55 B3D54 B3D53 B3D52 B3D51 B3D50 xxxx xxxx 63, 305 B3D4(8) B3D47 B3D46 B3D45 B3D44 B3D43 B3D42 B3D41 B3D40 xxxx xxxx 63, 305 B3D3(8) B3D37 B3D36 B3D35 B3D34 B3D33 B3D32 B3D31 B3D30 xxxx xxxx 63, 305 B3D2(8) B3D27 B3D26 B3D25 B3D24 B3D23 B3D22 B3D21 B3D20 xxxx xxxx 63, 305 B3D1(8) B3D17 B3D16 B3D15 B3D14 B3D13 B3D12 B3D11 B3D10 xxxx xxxx 63, 305 B3D0(8) B3D07 B3D06 B3D05 B3D04 B3D03 B3D02 B3D01 B3D00 xxxx xxxx 63, 305 B3DLC(8) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 63, 307 Receive mode B3DLC(8) — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 63, 307 Transmit mode B3EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 63, 305 B3EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 63, 304 B3SIDL(8) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 63, 303 Receive mode B3SIDL(8) SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 63, 303 Transmit mode B3SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 63, 302 B3CON(8) RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 63, 301 Receive mode B3CON(8) TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 63, 301 Transmit mode B2D7(8) B2D77 B2D76 B2D75 B2D74 B2D73 B2D72 B2D71 B2D70 xxxx xxxx 63, 305 B2D6(8) B2D67 B2D66 B2D65 B2D64 B2D63 B2D62 B2D61 B2D60 xxxx xxxx 63, 305 B2D5(8) B2D57 B2D56 B2D55 B2D54 B2D53 B2D52 B2D51 B2D50 xxxx xxxx 63, 305 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. DS39637D-page 90 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: B2D4(8) B2D47 B2D46 B2D45 B2D44 B2D43 B2D42 B2D41 B2D40 xxxx xxxx 63, 305 B2D3(8) B2D37 B2D36 B2D35 B2D34 B2D33 B2D32 B2D31 B2D30 xxxx xxxx 63, 305 B2D2(8) B2D27 B2D26 B2D25 B2D24 B2D23 B2D22 B2D21 B2D20 xxxx xxxx 63, 305 B2D1(8) B2D17 B2D16 B2D15 B2D14 B2D13 B2D12 B2D11 B2D10 xxxx xxxx 64, 305 B2D0(8) B2D07 B2D06 B2D05 B2D04 B2D03 B2D02 B2D01 B2D00 xxxx xxxx 64, 305 B2DLC(8) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 64, 307 Receive mode B2DLC(8) — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 64, 307 Transmit mode B2EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 64, 305 B2EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 64, 304 B2SIDL(8) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 64, 303 Receive mode B2SIDL(8) SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 64, 303 Transmit mode B2SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 64, 302 B2CON(8) RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 64, 301 Receive mode B2CON(8) TXBIF RXM1 TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 64, 301 Transmit mode B1D7(8) B1D77 B1D76 B1D75 B1D74 B1D73 B1D72 B1D71 B1D70 xxxx xxxx 64, 305 B1D6(8) B1D67 B1D66 B1D65 B1D64 B1D63 B1D62 B1D61 B1D60 xxxx xxxx 64, 305 B1D5(8) B1D57 B1D56 B1D55 B1D54 B1D53 B1D52 B1D51 B1D50 xxxx xxxx 64, 305 B1D4(8) B1D47 B1D46 B1D45 B1D44 B1D43 B1D42 B1D41 B1D40 xxxx xxxx 64, 305 B1D3(8) B1D37 B1D36 B1D35 B1D34 B1D33 B1D32 B1D31 B1D30 xxxx xxxx 64, 305 B1D2(8) B1D27 B1D26 B1D25 B1D24 B1D23 B1D22 B1D21 B1D20 xxxx xxxx 64, 305 B1D1(8) B1D17 B1D16 B1D15 B1D14 B1D13 B1D12 B1D11 B1D10 xxxx xxxx 64, 305 B1D0(8) B1D07 B1D06 B1D05 B1D04 B1D03 B1D02 B1D01 B1D00 xxxx xxxx 64, 305 B1DLC(8) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 64, 307 Receive mode B1DLC(8) — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 64, 307 Transmit mode B1EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 64, 305 B1EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 64, 304 B1SIDL(8) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 64, 303 Receive mode B1SIDL(8) SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 64, 303 Transmit mode B1SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 64, 302 B1CON(8) RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 64, 301 Receive mode B1CON(8) TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 64, 301 Transmit mode Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 91

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: B0D7(8) B0D77 B0D76 B0D75 B0D74 B0D73 B0D72 B0D71 B0D70 xxxx xxxx 64, 305 B0D6(8) B0D67 B0D66 B0D65 B0D64 B0D63 B0D62 B0D61 B0D60 xxxx xxxx 64, 305 B0D5(8) B0D57 B0D56 B0D55 B0D54 B0D53 B0D52 B0D51 B0D50 xxxx xxxx 64, 305 B0D4(8) B0D47 B0D46 B0D45 B0D44 B0D43 B0D42 B0D41 B0D40 xxxx xxxx 64, 305 B0D3(8) B0D37 B0D36 B0D35 B0D34 B0D33 B0D32 B0D31 B0D30 xxxx xxxx 64, 305 B0D2(8) B0D27 B0D26 B0D25 B0D24 B0D23 B0D22 B0D21 B0D20 xxxx xxxx 64, 305 B0D1(8) B0D17 B0D16 B0D15 B0D14 B0D13 B0D12 B0D11 B0D10 xxxx xxxx 64, 305 B0D0(8) B0D07 B0D06 B0D05 B0D04 B0D03 B0D02 B0D01 B0D00 xxxx xxxx 64, 305 B0DLC(8) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 64, 307 Receive mode B0DLC(8) — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 64, 307 Transmit mode B0EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 65, 305 B0EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 65, 304 B0SIDL(8) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 65, 303 Receive mode B0SIDL(8) SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 65, 303 Transmit mode B0SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 65, 302 B0CON(8) RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 64, 301 Receive mode B0CON(8) TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 64, 301 Transmit mode TXBIE — — — TXB2IE TXB1IE TXB0IE — — ---0 00-- 65, 324 BIE0 B5IE B4IE B3IE B2IE B1IE B0IE RXB1IE RXB0IE 0000 0000 65, 324 BSEL0 B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN — — 0000 00-- 65, 307 MSEL3 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 0000 0000 65, 316 MSEL2 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 0000 0000 65, 315 MSEL1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 0000 0101 65, 314 MSEL0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 0101 0000 65, 313 RXFBCON7 F15BP_3 F15BP_2 F15BP_1 F15BP_0 F14BP_3 F14BP_2 F14BP_1 F14BP_0 0000 0000 65, 312 RXFBCON6 F13BP_3 F13BP_2 F13BP_1 F13BP_0 F12BP_3 F12BP_2 F12BP_1 F12BP_0 0000 0000 65, 312 RXFBCON5 F11BP_3 F11BP_2 F11BP_1 F11BP_0 F10BP_3 F10BP_2 F10BP_1 F10BP_0 0000 0000 65, 312 RXFBCON4 F9BP_3 F9BP_2 F9BP_1 F9BP_0 F8BP_3 F8BP_2 F8BP_1 F8BP_0 0000 0000 65, 312 RXFBCON3 F7BP_3 F7BP_2 F7BP_1 F7BP_0 F6BP_3 F6BP_2 F6BP_1 F6BP_0 0000 0000 65, 312 RXFBCON2 F5BP_3 F5BP_2 F5BP_1 F5BP_0 F4BP_3 F4BP_2 F4BP_1 F4BP_0 0001 0001 65, 312 RXFBCON1 F3BP_3 F3BP_2 F3BP_1 F3BP_0 F2BP_3 F2BP_2 F2BP_1 F2BP_0 0001 0001 65, 312 RXFBCON0 F1BP_3 F1BP_2 F1BP_1 F1BP_0 F0BP_3 F0BP_2 F0BP_1 F0BP_0 0000 0000 65, 312 SDFLC — — — FLC4 FLC3 FLC2 FLC1 FLC0 ---0 0000 65, 312 RXFCON1 RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN 0000 0000 65, 311 RXFCON0 RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN 0000 0000 65, 311 RXF15EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 65, 309 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. DS39637D-page 92 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Page: RXF15EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 65, 309 RXF15SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 65, 308 RXF15SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 65, 309 RXF14EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 65, 309 RXF14EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 65, 309 RXF14SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 65, 308 RXF14SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 65, 309 RXF13EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 RXF13EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 66, 309 RXF13SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 66, 308 RXF13SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 66, 309 RXF12EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 RXF12EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 66, 309 RXF12SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 66, 308 RXF12SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 66, 309 RXF11EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 RXF11EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 66, 309 RXF11SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 66, 308 RXF11SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 66, 309 RXF10EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 RXF10EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 66, 309 RXF10SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 66, 308 RXF10SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 66, 309 RXF9EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 RXF9EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 66, 309 RXF9SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 66, 308 RXF9SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 66, 309 RXF8EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 RXF8EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 66, 309 RXF8SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 66, 308 RXF8SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 66, 309 RXF7EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 RXF7EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 66, 309 RXF7SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 66, 308 RXF7SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 66, 309 RXF6EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 RXF6EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 66, 309 RXF6SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xxx- x-xx 66, 308 RXF6SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 66, 309 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7>=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 93

PIC18F2480/2580/4480/4580 6.3.5 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register6-2, contains register, because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an instruc- the instruction set summaries in Table26-2 and tion that affects the Z, DC, C, OV or N bits, the results Table26-3. of the instruction are not written; instead, the status is updated according to the instruction performed. There- Note: The C and DC bits operate as the borrow fore, the result of an instruction with the STATUS and digit borrow bits respectively in register as its destination may be different than subtraction. intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). REGISTER 6-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. 2: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. DS39637D-page 94 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 6.4 Data Addressing Modes Purpose Register File”) or a location in the Access Bank (Section6.3.2 “Access Bank”) as the data Note: The execution of some instructions in the source for the instruction. core PIC18 instruction set are changed The Access RAM bit ‘a’ determines how the address is when the PIC18 extended instruction interpreted. When ‘a’ is ‘1’, the contents of the BSR setis enabled. See Section6.6 “Data (Section6.3.1 “Bank Select Register (BSR)”) are Memory and the Extended Instruction used with the address to determine the complete 12-bit Set” for more information. address of the register. When ‘a’ is ‘0’, the address is While the program memory can be addressed in only interpreted as being a register in the Access Bank. one way – through the program counter – information Addressing that uses the Access RAM is sometimes in the data memory space can be addressed in several also known as Direct Forced Addressing mode. ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their depending on which operands are used and whether or opcodes. In these cases, the BSR is ignored entirely. not the extended instruction set is enabled. The destination of the operation’s results is determined The addressing modes are: by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are • Inherent stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Literal the W register. Instructions without the ‘d’ argument • Direct have a destination that is implicit in the instruction; their • Indirect destination is either the target register being operated An additional addressing mode, Indexed Literal Offset, on or the W register. is available when the extended instruction set is 6.4.3 INDIRECT ADDRESSING enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section6.6.1 “Indexed Indirect Addressing allows the user to access a location Addressing with Literal Offset”. in data memory without giving a fixed address in the instruction. This is done by using File Select Registers 6.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written ADDRESSING to. Since the FSRs are themselves located in RAM as Many PIC18 control instructions do not need any Special File Registers, they can also be directly manip- argument at all; they either perform an operation that ulated under program control. This makes FSRs very globally affects the device or they operate implicitly on useful in implementing data structures, such as tables one register. This addressing mode is known as and arrays in data memory. Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also imple- and DAW. mented with Indirect File Operands (INDFs) that permit Other instructions work in a similar way but require an automatic manipulation of the pointer value with additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting known as Literal Addressing mode because they with another value. This allows for efficient code, using require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM include ADDLW and MOVLW which, respectively, add or bank in Example6-5. move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit EXAMPLE 6-5: HOW TO CLEAR RAM program memory address. (BANK 1) USING INDIRECT ADDRESSING 6.4.2 DIRECT ADDRESSING LFSR FSR0, 100h ; Direct Addressing specifies all or part of the source NEXT CLRF POSTINC0 ; Clear INDF and/or destination address of the operation within the ; register then opcode itself. The options are specified by the ; inc pointer arguments accompanying the instruction. BTFSS FSR0H,1 ; All done with ; Bank1? In the core PIC18 instruction set, bit-oriented and BRA NEXT ; NO, clear next byte-oriented instructions use some version of Direct CONTINUE ; YES, continue Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section6.3.3 “General © 2009 Microchip Technology Inc. DS39637D-page 95

PIC18F2480/2580/4480/4580 6.4.3.1 FSR Registers and the mapped in the SFR space, but are not physically imple- INDF Operand mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. At the core of Indirect Addressing are three sets of A read from INDF1, for example, reads the data at the registers: FSR0, FSR1 and FSR2. Each represents a address indicated by FSR1H:FSR1L. Instructions that pair of 8-bit registers, FSRnH and FSRnL. The four use the INDF registers as operands actually use the upper bits of the FSRnH register are not used, so each contents of their corresponding FSR as a pointer to the FSR pair holds a 12-bit value. This represents a value instruction’s target. The INDF operand is just a that can address the entire range of the data memory convenient way of using the pointer. in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current Indirect Addressing is accomplished with a set of contents of the BSR and the Access RAM bit have no Indirect File Operands, INDF0 through INDF2. These effect on determining the target address. can be thought of as “virtual” registers: they are FIGURE 6-8: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h ECCh. This means the contents of BBaannkk 1144 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory DS39637D-page 96 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 6.4.3.2 FSR Registers and POSTINC, 6.4.3.3 Operations by FSRs on FSRs POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For also has four additional indirect operands. Like INDF, example, using an FSR to point to one of the virtual these are “virtual” registers that cannot be indirectly registers will not result in successful operations. As a read or written to. Accessing these registers actually specific case, assume that FSR0H:FSR0L contains accesses the associated FSR register pair, but also FE7h, the address of INDF1. Attempts to read the performs a specific action on its stored value. They are: value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as • POSTDEC: accesses the FSR value, then the operand will result in a NOP. automatically decrements it by 1 afterwards • POSTINC: accesses the FSR value, then On the other hand, using the virtual registers to write to automatically increments it by 1 afterwards an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any • PREINC: increments the FSR value by 1, then incrementing or decrementing. Thus, writing to INDF2 uses it in the operation or POSTDEC2 will write the same value to the • PLUSW: adds the signed value of the W register FSR2H:FSR2L. (range of -127 to 128) to that of the FSR and uses the new value in the operation. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct In this context, accessing an INDF register, uses the operations. Users should proceed cautiously when value in the FSR registers without changing them. working on these registers, particularly if their code Similarly, accessing a PLUSW register gives the FSR uses Indirect Addressing. value offset by that in the W register; neither value is actually changed in the operation. Accessing the other Similarly, operations by Indirect Addressing are gener- virtual registers changes the value of the FSR ally permitted on all other SFRs. Users should exercise registers. the appropriate caution that they do not inadvertently change settings that might affect the operation of the Operations on the FSRs with POSTDEC, POSTINC device. and PREINC affect the entire register pair; that is, roll- overs of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2009 Microchip Technology Inc. DS39637D-page 97

PIC18F2480/2580/4480/4580 6.5 Program Memory and the When using the extended instruction set, this Extended Instruction Set addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); The operation of program memory is unaffected by the and use of the extended instruction set. • The file address argument is less than or equal to Enabling the extended instruction set adds eight 5Fh. additional two-word commands to the existing Under these conditions, the file address of the instruc- PIC18instruction set: ADDFSR, ADDULNK, CALLW, tion is not interpreted as the lower byte of an address MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These (used with the BSR in Direct Addressing), or as an 8-bit instructions are executed as described in address in the Access Bank. Instead, the value is Section6.2.4 “Two-Word Instructions”. interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of 6.6 Data Memory and the Extended FSR2 are added to obtain the target address of the Instruction Set operation. Enabling the PIC18 extended instruction set (XINST 6.6.2 INSTRUCTIONS AFFECTED BY Configuration bit = 1) significantly changes certain INDEXED LITERAL OFFSET MODE aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 Any of the core PIC18 instructions that can use Direct instructions is different. This is due to the introduction of Addressing are potentially affected by the Indexed a new addressing mode for the data memory space. This Literal Offset Addressing mode. This includes all mode also alters the behavior of Indirect Addressing byte-oriented and bit-oriented instructions, or almost using FSR2 and its associated operands. one-half of the standard PIC18 instruction set. Instruc- tions that only use Inherent or Literal Addressing What does not change is just as important. The size of modes are unaffected. the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Additionally, byte-oriented and bit-oriented instructions Core PIC18 instructions can still operate in both Direct are not affected if they use the Access Bank (Access and Indirect Addressing mode; inherent and literal RAM bit is ‘1’), or include a file address of 60h or above. instructions do not change at all. Indirect Addressing Instructions meeting these criteria will continue to with FSR0 and FSR1 also remains unchanged. execute as before. A comparison of the different possible addressing modes when the extended 6.6.1 INDEXED ADDRESSING WITH instruction set is enabled in shown in Figure6-9. LITERAL OFFSET Those who desire to use byte-oriented or bit-oriented Enabling the PIC18 extended instruction set changes instructions in the Indexed Literal Offset mode should the behavior of Indirect Addressing using the FSR2 note the changes to assembler syntax for this mode. register pair and its associated file operands. Under the This is described in more detail in Section26.2.1 proper conditions, instructions that use the Access “Extended Instruction Syntax”. Bank – that is, most bit-oriented and byte-oriented – instructions – can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. DS39637D-page 98 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When a = 0 and f ≥ 60h: The instruction executes in 060h Bank 0 Direct Forced mode. ‘f’ is inter- 080h preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 through 60h the SFRs, or locations F60h to Bank 14 0FFh (Bank 15) of data Valid range for ‘f’ memory. FFh Locations below 60h are not F00h Access RAM available in this addressing Bank 15 F60h mode. SFRs FFFh Data Memory When a = 0 and f ≤ 5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 080h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F60h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 080h Direct mode (also known as Direct Long mode). ‘f’ is 100h interpreted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. DS39637D-page 99

PIC18F2480/2580/4480/4580 6.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. Any indirect or effectively changes how the lower half of Access RAM indexed operation that explicitly uses any of the indirect (00h to 7Fh) is mapped. Rather than containing just the file operands (including FSR2) will continue to operate contents of the bottom half of Bank 0, this mode maps as standard Indirect Addressing. Any instruction that the contents from Bank 0 and a user-defined “window” uses the Access Bank, but includes a register address that can be located anywhere in the data memory of greater than 05Fh, will use Direct Addressing and space. The value of FSR2 establishes the lower bound- the normal Access Bank map. ary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). 6.6.4 BSR IN INDEXED LITERAL OFFSET Addresses in the Access RAM above 5Fh are mapped MODE as previously described (see Section6.3.2 “Access Bank”). An example of Access Bank remapping in this Although the Access Bank is remapped when the addressing mode is shown in Figure6-10. extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing using the BSR to select the data memory bank operates in the same manner as previously described. FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a 000h FSR2H:FSR2L = 120h Bank 0 Locations in the region from the FSR2 Pointer 100h (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Special File Registers at 60h F60h through FFFh are mapped to 60h through Bank 2 FFh, as usual. through SFRs Bank 0 addresses below Bank 14 5Fh are not available in FFh this mode. They can still Access Bank be addressed by using the F00h BSR. Bank 15 F60h SFRs FFFh Data Memory DS39637D-page 100 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable, during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 8 bytes at a time. Program memory is erased The program memory space is 16 bits wide, while the in blocks of 64 bytes at a time. A bulk erase operation data RAM space is 8 bits wide. Table reads and table may not be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and place it into the data RAM space. or erase, therefore, code cannot execute. An internal Figure7-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section7.5 “Writing to Flash Program Memory”. Figure7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. DS39637D-page 101

PIC18F2480/2580/4480/4580 FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in Section7.5 “Writing to Flash Program Memory”. 7.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase opera- Several control registers are used in conjunction with tion is initiated on the next WR command. When FREE the TBLRD and TBLWT instructions. These include the: is clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register On power-up, the WREN bit is clear. The WRERR bit is • TABLAT register set in hardware when the WREN bit is set and cleared • TBLPTR registers when the internal programming timer expires and the write operation is complete. 7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is The EECON1 register (Register7-1) is the control read as ‘1’. This can indicate that a write register for memory accesses. The EECON2 register is operation was prematurely terminated by not a physical register; it is used exclusively in the a Reset, or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The WR control bit initiates write operations. The bit The EEPGD control bit determines if the access will be cannot be cleared, only set, in software; it is cleared in a program or data EEPROM memory access. When hardware at the completion of the write operation. clear, any subsequent operations will operate on the Note: The EEIF Interrupt Flag bit (PIR2<4>) is data EEPROM memory. When set, any subsequent set when the write is complete. It must be operations will operate on the program memory. cleared in software. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section25.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. DS39637D-page 102 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. DS39637D-page 103

PIC18F2480/2580/4480/4580 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch register is used to Flash program memory. hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR memory and data RAM. determine which byte is read from program memory into TABLAT. 7.2.3 TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the five LSbs of the Table Pointer register (TBLPTR<4:0>) determine which of The Table Pointer (TBLPTR) register addresses a byte the 32 program memory holding registers is written to. within the program memory. The TBLPTR is comprised When the timed write to program memory begins (via of three SFR registers: Table Pointer Upper Byte, Table the WR bit), the 16 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:6>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 32 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section7.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the Device ID, the user ID and the Configuration bits. 16MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least The Table Pointer, TBLPTR, is used by the TBLRD and Significant bits (TBLPTR<5:0>) are ignored. TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table opera- Figure7-3 describes the relevant boundaries of tion. These operations are shown in Table7-1. These TBLPTR based on Flash program memory operations. operations on the TBLPTR only affect the low-order 21bits. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE/WRITE TABLE WRITE TBLPTR<21:6> TBLPTR<5:0> TABLE READ – TBLPTR<21:0> DS39637D-page 104 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 7.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and place it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVF WORD_ODD © 2009 Microchip Technology Inc. DS39637D-page 105

PIC18F2480/2580/4480/4580 7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP control, can larger blocks of program memory be program memory location is: bulk erased. Word erase in the Flash array is not 1. Load Table Pointer register with address of row supported. being erased. When initiating an erase sequence from the micro- 2. Set the EECON1 register for the erase operation: controller itself, a block of 64 bytes of program memory • set EEPGD bit to point to program memory; is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory; TBLPTR<21:5> point to the block being erased. • set WREN bit to enable writes; TBLPTR<4:0> are ignored. • set FREE bit to enable the erase. The EECON1 register commands the erase operation. 3. Disable interrupts. The EEPGD bit must be set to point to the Flash 4. Write 55h to EECON2. program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2. operation. 6. Set the WR bit. This will begin the row erase cycle. For protection, the write initiate sequence for EECON2 must be used. 7. The CPU will stall for duration of the erase (about 2ms using internal timer). A long write is necessary for erasing the internal Flash. 8. Re-enable interrupts. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39637D-page 106 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 7.5 Writing to Flash Program Memory The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long The minimum programming block is 16 words or write cycle. The long write will be terminated by the 32bytes. Word or byte programming is not supported. internal programming timer. Table writes are used internally to load the holding The EEPROM on-chip timer controls the write time. registers needed to program the Flash memory. There The write/erase voltages are generated by an on-chip are 32 holding registers used by the table writes for charge pump, rated to operate over the voltage range programming. of the device. Since the Table Latch (TABLAT) is only a single byte, the Note: The default value of the holding registers on TBLWT instruction may need to be executed 32times for device Resets and after write operations is each programming operation. All of the table write oper- FFh. A write of FFh to a holding register ations will essentially be short writes because only the does not modify that byte. This means that holding registers are written. At the end of updating the individual bytes of program memory may be 32 holding registers, the EECON1 register must be modified, provided that the change does not written to in order to start the programming operation attempt to change any bit from a ‘0’ to a ‘1’. with a long write. When modifying individual bytes, it is not necessary to load all 32 holding registers before executing a write operation. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxxxF Holding Register Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 64 bytes into RAM. 12. The CPU will stall for duration of the write (about 2ms using internal timer). After writing to the 2. Update data values in RAM as necessary. holding registers, it will be set to 0xFF. 3. Load Table Pointer register with address being 13. Repeat the question three more times. erased. 14. Re-enable interrupts. 4. Execute the row erase procedure. 15. Verify the memory (table read). 5. Load Table Pointer register with address of first byte being written. This procedure will require about 6ms to update one 6. Write the 32 bytes into the holding registers with row of 64 bytes of memory. An example of the required auto-increment. code is given in Example7-3. 7. Set the EECON1 register for the write operation: Note: Before setting the WR bit, the Table • set EEPGD bit to point to program memory; Pointer address needs to be within the • clear the CFGS bit to access program memory; intended address range of the 32 bytes in the holding register. • set WREN to enable byte writes. © 2009 Microchip Technology Inc. DS39637D-page 107

PIC18F2480/2580/4480/4580 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW D’4’ MOVWF COUNTER1 WRITE_BUFFER_BACK MOVLW D’64 ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS DS39637D-page 108 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1,EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) DECFSZ COUNTER1 BRA WRITE_BUFFER_BACK BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory 7.5.2 WRITE VERIFY 7.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the mem- To protect against spurious writes to Flash program ory should be verified against the original value. This memory, the write initiate sequence must also be should be used in applications where excessive writes followed. See Section25.0 “Special Features of the can stress bits near the specification limit. CPU” for more detail. 7.5.3 UNEXPECTED TERMINATION OF 7.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section25.5 “Program Verification and Code location just programmed should be verified and repro- Protection” for details on code protection of Flash grammed if needed. If the write operation is interrupted program memory. by a MCLR Reset or a WDT time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TBLPTRU — — bit21(3) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 55 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 55 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 55 TABLAT Program Memory Table Latch 55 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 55 EECON2 EEPROM Control Register 2 (not a physical register) 57 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 57 IPR2 OSCFIP CMIP(2) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) 57 PIR2 OSCFIF CMIF(2) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) 58 PIE2 OSCFIE CMIE(2) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(1) 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4X80 devices only. 2: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 3: This bit is available only in Test mode and Serial Programming mode. © 2009 Microchip Technology Inc. DS39637D-page 109

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 110 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 8.0 DATA EEPROM MEMORY The EECON1 register (Register8-1) is the control register for data and program memory access. Control The data EEPROM is a nonvolatile memory array, bit, EEPGD, determines if the access will be to program separate from the data RAM and program memory, that or data EEPROM memory. When clear, operations will is used for long-term storage of program data. It is not access the data EEPROM memory. When set, program directly mapped in either the register file or program memory is accessed. memory space, but is indirectly addressed through the Control bit, CFGS, determines if the access will be to Special Function Registers (SFRs). The EEPROM is the Configuration registers or to program memory/data readable and writable during normal operation over the EEPROM memory. When set, subsequent operations entire VDD range. access Configuration registers. When CFGS is clear, Four SFRs are used to read and write to the data the EEPGD bit selects either program Flash or data EEPROM, as well as the program memory. They are: EEPROM memory. • EECON1 The WREN bit, when set, will allow a write operation. • EECON2 On power-up, the WREN bit is clear. The WRERR bit is • EEDATA set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the • EEADR write operation is complete. The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds Note: During normal operation, the WRERR is the 8-bit data for read/write and the EEADR register read as ‘1’. This can indicate that a write holds the address of the EEPROM location being operation was prematurely terminated by accessed. a Reset, or a write operation was attempted improperly. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the The WR control bit initiates write operations. The bit location and writes the new data (erase-before-write). cannot be cleared, only set, in software; it is cleared in The write time is controlled by an on-chip timer; it will hardware at the completion of the write operation. vary with voltage and temperature, as well as from chip Note: The EEIF interrupt flag bit (PIR2<4>) is set to chip. Please refer to parameter D122 (Table28-1 in when the write is complete. It must be Section28.0 “Electrical Characteristics”) for exact cleared in software. limits. Control bits, RD and WR, start read and erase/write 8.1 EEADR Register operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the The EEADR register is used to address the data operation. EEPROM for read and write operations. The 8-bit The RD bit cannot be set when accessing program range of the register can address a memory range of memory (EEPGD = 1). Program memory is read using 256 bytes (00h to FFh). table read instructions. See Section7.1 “Table Reads 8.2 EECON1 and EECON2 Registers and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is Access to the data EEPROM is controlled by two used exclusively in the memory write and erase registers: EECON1 and EECON2. These are the same sequences. Reading EECON2 will read all ‘0’s. registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2009 Microchip Technology Inc. DS39637D-page 111

PIC18F2480/2580/4480/4580 REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39637D-page 112 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 8.3 Reading the Data EEPROM Additionally, the WREN bit in EECON1 must be set to Memory enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- To read a data memory location, the user must write the cution (i.e., runaway programs). The WREN bit should address to the EEADR register, clear the EEPGD be kept clear at all times, except when updating the control bit (EECON1<7>) and then set control bit, RD EEPROM. The WREN bit is not cleared byhardware. (EECON1<0>). The data is available on the very next After a write sequence has been initiated, EECON1, instruction cycle; therefore, the EEDATA register can EEADR and EEDATA cannot be modified. The WR bit be read by the next instruction. EEDATA will hold this will be inhibited from being set unless the WREN bit is value until another read operation, or until it is written to set. The WREN bit must be set on a previous instruc- by the user (during a write operation). tion. Both WR and WREN cannot be set with the same The basic process is shown in Example8-1. instruction. At the completion of the write cycle, the WR bit is 8.4 Writing to the Data EEPROM cleared in hardware and the EEPROM Interrupt Flag bit Memory (EEIF) is set. The user may either enable this interrupt, or poll this bit. EEIF must be cleared by software. To write an EEPROM data location, the address must first be written to the EEADR register and the data 8.5 Write Verify written to the EEDATA register. The sequence in Example8-2 must be followed to initiate the write cycle. Depending on the application, good programming The write will not begin if this sequence is not exactly practice may dictate that the value written to the mem- followed (write 55h to EECON2, write 0AAh to ory should be verified against the original value. This EECON2, then set WR bit) for each byte. It is strongly should be used in applications where excessive writes recommended that interrupts be disabled during this can stress bits near the specification limit. codesegment. EXAMPLE 8-1: DATA EEPROM READ MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA EXAMPLE 8-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set) © 2009 Microchip Technology Inc. DS39637D-page 113

PIC18F2480/2580/4480/4580 8.6 Operation During Code-Protect 8.8 Using the Data EEPROM Data EEPROM memory has its own code-protect bits in The data EEPROM is a high-endurance, byte address- Configuration Words. External read and write able array that has been optimized for the storage of operations are disabled if code protection is enabled. frequently changing information (e.g., program variables or other data that are updated often). The microcontroller itself can both read and write to the Frequently changing values will typically be updated internal data EEPROM, regardless of the state of the more often than specification D124. If this is not the code-protect Configuration bit. Refer to Section25.0 case, an array refresh must be performed. For this “Special Features of the CPU” for additional reason, variables that change infrequently (such as information. constants, IDs, calibration, etc.) should be stored in Flash program memory. 8.7 Protection Against Spurious Write A simple data EEPROM refresh routine is shown in There are conditions when the device may not want to Example8-3. write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have Note: If data EEPROM is only used to store constants and/or data that changes rarely, been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked an array refresh is likely not required. See during the Power-up Timer period (TPWRT, specification D124. parameter33). The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes LOOP ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS39637D-page 114 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 EEADR EEPROM Address Register 57 EEDATA EEPROM Data Register 57 EECON2 EEPROM Control Register 2 (not a physical register) 57 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 57 IPR2 OSCFIP CMIP(1) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(1) 57 PIR2 OSCFIF CMIF(1) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) 58 PIE2 OSCFIE CMIE(1) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(1) 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. © 2009 Microchip Technology Inc. DS39637D-page 115

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 116 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 9.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 9-2: 8 x 8 SIGNED register. MULTIPLY ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W MULWF ARG2 ; ARG1 * ARG2 -> advantages of higher computational throughput and ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table9-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 9.2 Operation Example9-1 shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the signed bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 μs Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 μs 6 μs Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs 16 x 16 signed Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs © 2009 Microchip Technology Inc. DS39637D-page 117

PIC18F2480/2580/4480/4580 Example9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED unsigned multiplication. Equation9-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) + MULTIPLICATION (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216) = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + EXAMPLE 9-4: 16 x 16 SIGNED (ARG1L • ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 9-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L,W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example9-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation9-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES3:RES0). To account for the signed bits of the SIGN_ARG1 arguments, the MSb for each argument pair is tested BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? and the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39637D-page 118 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 10.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are The PIC18F2480/2580/4480/4580 devices have compatible with PIC® mid-range devices. In Compati- multiple interrupt sources and an interrupt priority bility mode, the interrupt priority bits for each source feature that allows each interrupt source to be assigned have no effect. INTCON<6> is the PEIE bit, which a high-priority level or a low-priority level. The high- enables/disables all peripheral interrupt sources. INT- priority interrupt vector is at 000008h and the low- CON<7> is the GIE bit, which enables/disables all priority interrupt vector is at 000018h. High-priority interrupt sources. All interrupts branch to address interrupt events will interrupt any low-priority interrupts 000008h in Compatibility mode. that may be in progress. When an interrupt is responded to, the global interrupt There are ten registers which are used to control enable bit is cleared to disable further interrupts. If the interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a low- • INTCON priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address • PIE1, PIE2, PIE3 (000008h or 000018h). Once in the Interrupt Service • IPR1, IPR2, IPR3 Routine, the source(s) of the interrupt can be deter- It is recommended that the Microchip header files mined by polling the interrupt flag bits. The interrupt supplied with MPLAB® IDE be used for the symbolic bit flag bits must be cleared in software before re-enabling names in these registers. This allows the assembler/ interrupts to avoid recursive interrupts. compiler to automatically take care of the placement of The “return from interrupt” instruction, RETFIE, exits these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL Each interrupt source has three bits to control its if priority levels are used), which re-enables interrupts. operation. The functions of these bits are: For external interrupt events, such as the INTx pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set, regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify any of the Interrupt Control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is enabled, cause erratic microcontroller behavior. there are two bits which enable interrupts globally. Set- ting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. DS39637D-page 119

PIC18F2480/2580/4480/4580 FIGURE 10-1: INTERRUPT LOGIC Wake-up if in Sleep Mode TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU INT1IF Vector to Location INT1IE Peripheral Interrupt Flag bit INT1IP 0008h Peripheral Interrupt Enable bit INT2IF Peripheral Interrupt Priority bit INT2IE INT2IP TMR1IF GIEH/GIE TMR1IE TMR1IP IPE XXXXIF IPEN XXXXIE GIEL/PEIE XXXXIP IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU TMR0IF Vector to Location TMR0IE 0018h TMR1IF TMR0IP TMR1IE TMR1IP RBIF RBIE XXXXIF RBIP GIEL/PEIE XXXXIE XXXXIP GIE/GEIH INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP DS39637D-page 120 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 10.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers, which contain various enable, priority and interrupt enable bit. User software should flag bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all high-priority interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. DS39637D-page 121

PIC18F2480/2580/4480/4580 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39637D-page 122 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. DS39637D-page 123

PIC18F2480/2580/4480/4580 10.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the global peripheral interrupts. Due to the number of peripheral interrupt enable bit, GIE (INTCON<7>). interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). 2: User software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: This bit is reserved on PIC18F2X80 devices; always maintain this bit clear. DS39637D-page 124 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF(1) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6 CMIF: Comparator Interrupt Flag bit(1) 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete, or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the High/Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 ECCP1IF: CCPx Interrupt Flag bit(1) Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: These bits are available in PIC18F4X80 and reserved in PIC18F2X80 devices. © 2009 Microchip Technology Inc. DS39637D-page 125

PIC18F2480/2580/4480/4580 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 0 IRXIF WAKIF ERRIF TXB2IF TXB1IF(1) TXB0IF(1) RXB1IF RXB0IF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 1,2 IRXIF WAKIF ERRIF TXBnIF TXB1IF(1) TXB0IF(1) RXBnIF FIFOWMIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus bit 6 WAKIF: CAN bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus bit 5 ERRIF: CAN bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors bit 4 When CAN is in Mode 0: TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message When CAN is in Mode 1 or 2: TXBnIF: Any Transmit Buffer Interrupt Flag bit 1 = One or more transmit buffers have completed transmission of a message and may be reloaded 0 = No transmit buffer is ready for reload bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1) 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1) 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 When CAN is in Mode 0: RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2: RXBnIF: Any Receive Buffer Interrupt Flag bit 1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message bit 0 When CAN is in Mode 0: RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIF: FIFO Watermark Interrupt Flag bit(1) 1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. DS39637D-page 126 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is reserved on PIC18F2X80 devices; always maintain this bit clear. © 2009 Microchip Technology Inc. DS39637D-page 127

PIC18F2480/2580/4480/4580 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE(1) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 ECCP1IE: CCP1 Interrupt Enable bit(2) 1 = Enabled 0 = Disabled Note 1: This bit is available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 2: This bit is available in PIC18F4X80 devices only. DS39637D-page 128 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 0 IRXIE WAKIE ERRIE TXB2IE TXB1IE(1) TXB0IE(1) RXB1IE RXB0IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 1,2 IRXIE WAKIE ERRIE TXBnIE TXB1IE(1) TXB0IE(1) RXBnIE FIFOWMIE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt bit 4 When CAN is in Mode 0: TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt When CAN is in Mode 1 or 2: TXBnIE: CAN Transmit Buffer Interrupts Enable bit 1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 When CAN is in Mode 0: RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2: RXBnIE: CAN Receive Buffer Interrupts Enable bit 1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts bit 0 When CAN is in Mode 0: RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit(1) 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. © 2009 Microchip Technology Inc. DS39637D-page 129

PIC18F2480/2580/4480/4580 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is reserved on PIC18F2X80 devices; always maintain this bit set. DS39637D-page 130 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP(1) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 ECCP1IP: CCP1 Interrupt Priority bit(2) 1 = High priority 0 = Low priority Note 1: This bit is available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 2: This bit is available in PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 131

PIC18F2480/2580/4480/4580 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Mode 0 IRXIP WAKIP ERRIP TXB2IP TXB1IP(1) TXB0IP(1) RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Mode 1,2 IRXIP WAKIP ERRIP TXBnIP TXB1IP(1) TXB0IP(1) RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 When CAN is in Mode 0: TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: TXBnIP: CAN Transmit Buffer Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 1 When CAN is in Mode 0: RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: RXBnIP: CAN Receive Buffer Interrupts Priority bit 1 = High priority 0 = Low priority bit 0 When CAN is in Mode 0: RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIP: FIFO Watermark Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. DS39637D-page 132 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 10.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 10-13: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) For details of bit operation, see Register5-1. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register5-1. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register5-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register5-1. bit 1 POR: Power-on Reset Status bit(2) For details of bit operation, see Register5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register5-1. Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See Register5-1 for additional information. © 2009 Microchip Technology Inc. DS39637D-page 133

PIC18F2480/2580/4480/4580 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and In 8-bit mode (which is the default), an overflow in the RB2/INT2 pins are edge-triggered. If the corresponding TMR0 register (FFh→00h) will set flag bit TMR0IF. In INTEDGx bit in the INTCON2 register is set (= 1), the 16-bit mode, an overflow in the TMR0H:TMR0L regis- interrupt is triggered by a rising edge; if the bit is clear, ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt the trigger is on the falling edge. When a valid edge can be enabled/disabled by setting/clearing enable bit appears on the RBx/INTx pin, the corresponding flag TMR0IE (INTCON<5>). Interrupt priority for Timer0 is bit, INTxF, is set. This interrupt can be disabled by determined by the value contained in the interrupt clearing the corresponding enable bit, INTxE. Flag bit, priority bit, TMR0IP (INTCON2<2>). See Section14.0 INTxF, must be cleared in software in the Interrupt “Timer2 Module” for further details on the Timer0 Service Routine before re-enabling the interrupt. module. All external interrupts (INT0, INT1 and INT2) can wake- 10.8 PORTB Interrupt-on-Change up the processor from the power-managed modes, if bit INTxE was set prior to going into power-managed An input change on PORTB<7:4> sets flag bit, RBIF modes. If the Global Interrupt Enable bit, GIE, is set, (INTCON<0>). The interrupt can be enabled/disabled the processor will branch to the interrupt vector by setting/clearing enable bit, RBIE (INTCON<3>). following wake-up. Interrupt priority for PORTB interrupt-on-change is Interrupt priority for INT1 and INT2 is determined by determined by the value contained in the interrupt the value contained in the interrupt priority bits, priority bit, RBIP (INTCON2<0>). INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is 10.9 Context Saving During Interrupts always a high-priority interrupt source. During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (See Section6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS39637D-page 134 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 11.0 I/O PORTS 11.1 PORTA, TRISA and LATA Registers Depending on the device selected and features PORTA is an 8-bit wide, bidirectional port. The enabled, there are up to five ports available. Some pins corresponding Data Direction register is TRISA. Setting of the I/O ports are multiplexed with an alternate a TRISA bit (= 1) will make the corresponding PORTA function from the peripheral features on the device. In pin an input (i.e., put the corresponding output driver in general, when a peripheral is enabled, that pin may not a high-impedance mode). Clearing a TRISA bit (= 0) be used as a general purpose I/O pin. will make the corresponding PORTA pin an output (i.e., put the contents of the Output Latch register on the Each port has three registers for its operation. These selected pin). registers are: Reading the PORTA register reads the status of the • TRIS register (Data Direction register) pins, whereas writing to it, will write to the port latch. • PORT register (reads the levels on the pins of the device) The Output Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA • LAT register (Output Latch register) register read and write the latched output value for The Output Latch register (LAT) is useful for read- PORTA. modify-write operations on the value that the I/O pins The RA4 pin is multiplexed with the Timer0 module are driving. clock input to become the RA4/T0CKI pin. Pins, RA6 A simplified model of a generic I/O port, without the and RA7, are multiplexed with the main oscillator pins; interfaces to other peripherals, is shown in Figure11-1. they are enabled as oscillator or I/O pins by the selec- tion of the main oscillator in Configuration Register 1H FIGURE 11-1: GENERIC I/O PORT (see Section25.1 “Configuration Bits” for details). OPERATION When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. RD LAT The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the Data comparator voltage reference output. The operation of Bus D Q pins, RA<3:0> and RA5 as A/D Converter inputs, is WR LAT I/O pin(1) selected by clearing/setting the control bits in the orPORT CK ADCON1 register (A/D Control Register 1). Data Latch Note: On a Power-on Reset, RA5 and RA<3:0> D Q are configured as analog inputs and read as ‘0’. RA4 is configured as a digital input. WR TRIS CK All other PORTA pins have TTL input levels and full TRIS Latch Input CMOS output drivers. Buffer The TRISA register controls the direction of the RA RD TRIS pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are Q D maintained set when using them as analog inputs. ENEN EXAMPLE 11-1: INITIALIZING PORTA RD PORT CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches Note1: I/O pins have diode protection to VDD and VSS. CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 0Fh ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs © 2009 Microchip Technology Inc. DS39637D-page 135

PIC18F2480/2580/4480/4580 TABLE 11-1: PORTA I/O SUMMARY Pin Name Function I/O TRIS Buffer Description RA0/AN0/CVREF RA0 OUT 0 DIG LATA<0> data output. IN 1 TTL PORTA<0> data input. AN0 IN 1 ANA A/D Input Channel 0. Enabled on POR; this analog input overrides the digital input (read as clear – low level). CVREF(1) OUT x ANA Comparator voltage reference analog output. Enabling this analog output overrides the digital I/O (read as clear – low level). RA1/AN1 RA1 OUT 0 DIG LATA<1> data output. IN 1 TTL PORTA<1> data input. AN1 IN 1 ANA A/D Input Channel 1. Enabled on POR; this analog input overrides the digital input (read as clear – low level). RA2/AN2/VREF- RA2 OUT 0 DIG LATA<2> data output. IN 1 TTL PORTA<2> data input. AN2 IN 1 ANA A/D Input Channel 2. Enabled on POR; this analog input overrides the digital input (read as clear – low level). VREF- IN 1 ANA A/D and comparator negative voltage analog input. RA3/AN3/VREF+ RA3 OUT 0 DIG LATA<3> data output. IN 1 TTL PORTA<3> data input. AN3 IN 1 ANA A/D Input Channel 3. Enabled on POR; this analog input overrides the digital input (read as clear – low level). VREF+ IN 1 ANA A/D and comparator positive voltage analog input. RA4/T0CKI RA4 OUT 0 DIG LATA<4> data output. IN 1 TTL PORTA<4> data input. T0CKI IN 1 ST Timer0 clock input. RA5/AN4/SS/HLVDIN RA5 OUT 0 DIG LATA<5> data output. IN 1 TTL PORTA<5> data input. AN4 IN 1 ANA A/D Input Channel 4. Enabled on POR; this analog input overrides the digital input (read as clear – low level). SS IN 1 TTL Slave select input for MSSP. HLVDIN IN 1 ANA High/Low-Voltage Detect external trip point input. OSC2/CLKO/RA6 OSC2 OUT x ANA Output connection; selected by FOSC<3:0> Configuration bits. Enabling OSC2 overrides digital I/O. CLKO OUT x DIG Output connection; selected by FOSC<3:0> Configuration bits. Enabling CLKO overrides digital I/O (FOSC/4). RA6 OUT 0 DIG LATA<6> data output. IN 1 TTL PORTA<6> data input. OSC1/CLKI/RA7 OSC1 IN x ANA Main oscillator input connection determined by FOSC<3:0> Configuration bits. Enabling OSC1 overrides digital I/O. CLKI IN x ANA Main clock input connection determined by FOSC<3:0> Configuration bits. Enabling CLKI overrides digital I/O. RA7 OUT 0 DIG LATA<7> data output. IN 1 TTL PORTA<7> data input. Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: Available on 40/44-pin devices only. DS39637D-page 136 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 58 LATA LATA7(1) LATA6(1) LATA Output Latch Register 58 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 58 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 56 CVRCON(2) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: These registers are unimplemented on PIC18F2X80 devices. © 2009 Microchip Technology Inc. DS39637D-page 137

PIC18F2480/2580/4480/4580 11.2 PORTB, TRISB and LATB Four of the PORTB pins (RB<7:4>) have an interrupt- Registers on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin PORTB is an 8-bit wide, bidirectional port. The corre- configured as an output is excluded from the interrupt- sponding Data Direction register is TRISB. Setting a on-change comparison). The input pins (of RB<7:4>) TRISB bit (= 1) will make the corresponding PORTB are compared with the old value latched on the last pin an input (i.e., put the corresponding output driver in read of PORTB. The “mismatch” outputs of RB<7:4> a high-impedance mode). Clearing a TRISB bit (= 0) are ORed together to generate the RB Port Change will make the corresponding PORTB pin an output (i.e., Interrupt with Flag bit, RBIF (INTCON<0>). put the contents of the output latch on the selected pin). This interrupt can wake the device from Sleep. The The Output Latch register (LATB) is also memory user, in the Interrupt Service Routine, can clear the mapped. Read-modify-write operations on the LATB interrupt in the following manner: register read and write the latched output value for a) Any read or write of PORTB (except with the PORTB. MOVFF (ANY), PORTB instruction). This will Pins, RB2 through RB3, are multiplexed with the ECAN end the mismatch condition. peripheral. Refer to Section24.0 “ECAN Module” for b) 1 TCY. proper settings of TRISB when CAN is enabled. c) Clear flag bit, RBIF. EXAMPLE 11-2: INITIALIZING PORTB A mismatch condition will continue to set flag bit, RBIF. Reading PORTB and waiting 1 TCY will end the CLRF PORTB ; Initialize PORTB by mismatch condition and allow flag bit, RBIF, to be ; clearing output cleared. ; data latches CLRF LATB ; Alternate method The interrupt-on-change feature is recommended for ; to clear output wake-up on key depression operation and operations ; data latches where PORTB is only used for the interrupt-on-change MOVLW 0Eh ; Set RB<4:0> as feature. Polling of PORTB is not recommended while MOVWF ADCON1 ; digital I/O pins using the interrupt-on-change feature. ; (required if config bit ; PBADEN is set) MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device resets. Note: On a Power-on Reset, RB4, RB1 and RB0 are configured as analog inputs by default and read as ‘0’; RB<7:5> and RB<3:2> are configured as digital inputs. DS39637D-page 138 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 11-3: PORTB I/O SUMMARY Pin Name Function I/O TRIS Buffer Description RB0/INT0/FLT0/AN10 RB0 OUT 0 DIG LATB<0> data output. IN 1 TTL PORTB<0> data input. Weak pull-up available only in this mode. INT0 IN 1 ST External Interrupt 0 input. FLT0(1) IN 1 ST Enhanced PWM Fault input. AN10 IN 1 ANA A/D Input Channel 10. Enabled on POR, this analog input overrides the digital input (read as clear – low level). RB1/INT1/AN8 RB1 OUT 0 DIG LATB<1> data output. IN 1 TTL PORTB<1> data input. Weak pull-up available only in this mode. INT1 IN 1 ST External Interrupt 1 input. AN8 IN 1 ANA A/D Input Channel 8. Enabled on POR; this analog input overrides the digital input (read as clear – low level). RB2/INT2/CANTX RB2 OUT x DIG LATB<2> data output. IN 1 TTL PORTB<2> data input. Weak pull-up available only in this mode. INT2 IN 1 ST External Interrupt 2 input. CANTX OUT 1 DIG CAN transmit signal output. The CAN interface overrides the TRIS<2> control when enabled. RB3/CANRX RB3 OUT 0 DIG LATB<3> data output. IN 1 TTL PORTB<3> data input. Weak pull-up available only in this mode. CANRX IN 1 ST CAN receive signal input. Pin must be configured as a digital input by setting TRISB<3>. RB4/KBI0/AN9 RB4 OUT 0 DIG LATB<4> data output. IN 1 TTL PORTB<4> data input. Weak pull-up available only in this mode. KBI0 IN 1 TTL Interrupt-on-pin change. AN9 IN 1 ANA A/D Input Channel 9. Enabled on POR; this analog input overrides the digital input (read as clear – low level). RB5/KBI1/PGM RB5 OUT 0 DIG LATB<5> data output. IN 1 TTL PORTB<5> data input. Weak pull-up available only in this mode. KBI1 IN 1 TTL Interrupt-on-pin change. PGM IN x ST Low-Voltage Programming mode entry (ICSP™). Enabling this function overrides digital output. RB6/KBI2/PGC RB6 OUT 0 DIG LATB<6> data output. IN 1 TTL PORTB<6> data input. Weak pull-up available only in this mode. KBI2 IN 1 TTL Interrupt-on-pin change. PGC IN x ST Low-Voltage Programming mode entry (ICSP) clock input. RB7/KBI3/PGD RB7 OUT 0 DIG LATB<7> data output. IN 1 TTL PORTB<7> data input. Weak pull-up available only in this mode. KBI3 IN 1 TTL Interrupt-on-pin change. PGD OUT x DIG Low-Voltage Programming mode entry (ICSP) clock output. IN x ST Low-Voltage Programming mode entry (ICSP) clock input. Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: Available on 40/44-pin devices only. © 2009 Microchip Technology Inc. DS39637D-page 139

PIC18F2480/2580/4480/4580 TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 58 LATB LATB Output Latch Register 58 TRISB PORTB Data Direction Register 58 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 55 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 55 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. DS39637D-page 140 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 11.3 PORTC, TRISC and LATC Note: On a Power-on Reset, these pins are Registers configured as digital inputs. PORTC is an 8-bit wide, bidirectional port. The corre- The contents of the TRISC register are affected by sponding Data Direction register is TRISC. Setting a peripheral overrides. Reading TRISC always returns TRISC bit (= 1) will make the corresponding PORTC the current contents, even though a peripheral device pin an input (i.e., put the corresponding output driver in may be overriding one or more of the pins. a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., EXAMPLE 11-3: INITIALIZING PORTC put the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by The Output Latch register (LATC) is also memory ; clearing output mapped. Read-modify-write operations on the LATC ; data latches register read and write the latched output value for CLRF LATC ; Alternate method ; to clear output PORTC. ; data latches PORTC is multiplexed with several peripheral functions MOVLW 0CFh ; Value used to (Table11-5). The pins have Schmitt Trigger input ; initialize data buffers. ; direction MOVWF TRISC ; Set RC<3:0> as inputs When enabling peripheral functions, care should be ; RC<5:4> as outputs taken in defining TRIS bits for each PORTC pin. Some ; RC<7:6> as inputs peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. DS39637D-page 141

PIC18F2480/2580/4480/4580 TABLE 11-5: PORTC I/O SUMMARY Pin Name Function I/O TRIS Buffer Description RC0/T1OSO/ RC0 OUT 0 DIG LATC<0> data output. T13CKI IN 1 ST PORTC<0> data input. T1OSO OUT x ANA Timer1 oscillator output – overrides the TRIS<0> control when enabled. T13CKI IN 1 ST Timer1/Timer3 clock input. RC1/T1OSI RC1 OUT 0 DIG LATC<1> data output. IN 1 ST PORTC<1> data input. T1OSI IN x ANA Timer1 oscillator input – overrides the TRIS<1> control when enabled. RC2/CCP1 RC2 OUT 0 DIG LATC<2> data output. IN 1 ST PORTC<2> data input. CCP1 OUT 0 DIG CCP1 compare output. IN 1 ST CCP1 capture input. RC3/SCK/SCL RC3 OUT 0 DIG LATC<3> data output. IN 1 ST PORTC<3> data input. SCK OUT 0 DIG SPI clock output (MSSP module) – must have TRIS set to ‘1’ to allow MSSP module to control the bidirectional communication. IN 1 ST SPI clock input (MSSP module). SCL OUT 0 DIG I2C™/SM bus clock output (MSSP module) – must have TRIS set to ‘1’ to allow MSSP module to control the bidirectional communication. IN 1 I2C™/SMB I2C/SM bus clock input. RC4/SDI/SDA RC4 OUT 0 DIG LATC<4> data output. IN 1 ST PORTC<4> data input. SDI IN 1 ST SPI data input (MSSP module). SDA OUT 1 DIG I2C/SM bus data output (MSSP module) – must have TRIS set to ‘1’ to allow MSSP module to control the bidirectional communication. IN 1 I2C/SMB I2C/SM bus data input (MSSP module) – must have TRIS set to ‘1’ to allow MSSP module to control the bidirectional communication. RC5/SDO RC5 OUT 0 DIG LATC<5> data output. IN 1 ST PORTC<5> data input. SDO OUT 0 DIG SPI data output (MSSP module). RC6/TX/CK RC6 OUT 0 DIG LATC<6> data output. IN 1 ST PORTC<6> data input. TX OUT 0 DIG EUSART data output. CK OUT 1 DIG EUSART synchronous clock output – must have TRIS set to ‘1’ to enable EUSART to control the bidirectional communication. IN 1 ST EUSART synchronous clock input. RC7/RX/DT RC7 OUT 0 DIG LATC<7> data output. IN 1 ST PORTC<7> data input. RX IN 1 ST EUSART asynchronous data input. DT OUT 1 DIG EUSART synchronous data output – must have TRIS set to ‘1’ to enable EUSART to control the bidirectional communication. IN 1 ST EUSART synchronous data input. Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 58 LATC LATC Output Latch Register 58 TRISC PORTC Data Direction Register 58 DS39637D-page 142 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 11.4 PORTD, TRISD and LATD PORTD can also be configured as an 8-bit wide micro- Registers processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input Note: PORTD is only available on PIC18F4X80 buffers are TTL. See Section11.6 “Parallel Slave devices. Port” for additional information on the Parallel Slave Port (PSP). PORTD is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISD. Setting a EXAMPLE 11-4: INITIALIZING PORTD TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in CLRF PORTD ; Initialize PORTD by a high-impedance mode). Clearing a TRISD bit (= 0) ; clearing output ; data latches will make the corresponding PORTD pin an output (i.e., CLRF LATD ; Alternate method put the contents of the output latch on the selected pin). ; to clear output The Output Latch register (LATD) is also memory ; data latches mapped. Read-modify-write operations on the LATD MOVLW 0CFh ; Value used to register read and write the latched output value for ; initialize data PORTD. ; direction MOVWF TRISD ; Set RD<3:0> as inputs All pins on PORTD are implemented with Schmitt ; RD<5:4> as outputs Trigger input buffers. Each pin is individually ; RD<7:6> as inputs configurable as an input or output. Four of the PORTD pins are multiplexed with outputs P1A, P1B, P1C and P1D of the Enhanced CCP module. The operation of these additional PWM output pins is covered in greater detail in Section17.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. Four of the PORTD pins are multiplexed with the input pins of the comparators. The operation of these input pins is covered in greater detail in Section21.0 “Comparator Module”. Note: On a Power-on Reset, these pins are configured as analog inputs. © 2009 Microchip Technology Inc. DS39637D-page 143

PIC18F2480/2580/4480/4580 TABLE 11-7: PORTD I/O SUMMARY Pin Name Function I/O TRIS Buffer Description RD0/PSP0/ RD0 OUT 0 DIG LATD<0> data output. C1IN+ IN 1 ST PORTD<0> data input. PSP0 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled). C1IN+ IN 1 ANA Comparator 1 Positive Input B. Default on POR. This analog input overrides the digital input (read as clear – low level). RD1/PSP1/ RD1 OUT 0 DIG LATD<1> data output. C1IN- IN 1 ST PORTD<1> data input. PSP1 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled). C1IN- IN 1 ANA Comparator 1 negative input. Default on POR. This analog input overrides the digital input (read as clear – low level). RD2/PSP2/ RD2 OUT 0 DIG LATD<2> data output. C2IN+ IN 1 ST PORTD<2> data input. PSP2 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled). C2IN+ IN 1 ANA Comparator 2 positive input. Default on POR. This analog input overrides the digital input (read as clear – low level). RD3/PSP3/ RD3 OUT 0 DIG LATD<3> data output. C2IN- IN 1 ST PORTD<3> data input. PSP3 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled). C2IN- IN 1 ANA Comparator 2 negative input. Default input on POR. This analog input overrides the digital input (read as clear – low level). RD4/PSP4/ RD4 OUT 0 DIG LATD<4> data output. ECCP1/P1A IN 1 ST PORTD<4> data input. PSP4 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled). ECCP1 OUT 0 DIG ECCP1 compare output. IN 1 ST ECCP1 capture input. P1A OUT 0 DIG ECCP1 Enhanced PWM output, Channel A. RD5/PSP5/ RD5 OUT 0 DIG LATD<5> data output. P1B IN 1 ST PORTD<5> data input. PSP5 OUT X DIG Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled). P1B OUT 0 DIG ECCP1 Enhanced PWM output, Channel B. RD6/PSP6/ RD6 OUT 0 DIG LATD<6> data output. P1C IN 1 ST PORTD<6> data input. PSP6 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled). P1C OUT 0 DIG ECCP1 Enhanced PWM output, Channel C. RD7/PSP7/ RD7 OUT 0 DIG LATD<7> data output. P1D IN 1 ST PORTD<7> data input. PSP7 OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled). P1D OUT 0 DIG ECCP1 Enhanced PWM output, channel D. Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input DS39637D-page 144 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 58 LATD(1) LATD Output Latch Register 58 TRISD(1) PORTD Data Direction Register 58 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 58 ECCP1CON(1) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 145

PIC18F2480/2580/4480/4580 11.5 PORTE, TRISE and LATE The fourth pin of PORTE (MCLR/VPP/RE3) is an input Registers only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin Depending on the particular PIC18F2480/2580/4480/ (MCLRE=0), it functions as a digital input only pin. As 4580 device selected, PORTE is implemented in two such, it does not have TRIS or LAT bits associated with different ways. its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, RE3 also For PIC18F4X80 devices, PORTE is a 4-bit wide port. functions as the programming voltage input during Three pins (RE0/RD/AN5, RE1/WR/AN6/C1OUT and programming. RE2/CS/AN7/C2OUT) are individually configurable as inputs or outputs. These pins have Schmitt Trigger Note: On a Power-on Reset, RE3 is enabled as input buffers. When selected as an analog input, these a digital input only if Master Clear pins will read as ‘0’s. functionality is disabled. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding EXAMPLE 11-5: INITIALIZING PORTE PORTE pin an input (i.e., put the corresponding output CLRF PORTE ; Initialize PORTE by driver in a high-impedance mode). Clearing a TRISE bit ; clearing output (= 0) will make the corresponding PORTE pin an output ; data latches (i.e., put the contents of the output latch on the selected CLRF LATE ; Alternate method pin). ; to clear output ; data latches TRISE controls the direction of the RE pins, even when MOVLW 0Ah ; Configure A/D they are being used as analog inputs. The user must MOVWF ADCON1 ; for digital inputs make sure to keep the pins configured as inputs when MOVLW 03h ; Value used to using them as analog inputs. ; initialize data ; direction Note: On a Power-on Reset, RE<2:0> are MOVLW 07h ; Turn off configured as analog inputs. MOVWF CMCON ; comparators MOVWF TRISC ; Set RE<0> as inputs The upper four bits of the TRISE register also control ; RE<1> as outputs the operation of the Parallel Slave Port. Their operation ; RE<2> as inputs is explained in Register11-1. The Output Latch register (LATE) is also memory 11.5.1 PORTE IN 28-PIN DEVICES mapped. Read-modify-write operations on the LATE register, read and write the latched output value for For PIC18F2X80 devices, PORTE is only available PORTE. when Master Clear functionality is disabled (MCLRE=0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described. DS39637D-page 146 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 11-1: TRISE REGISTER (PIC18F4X80 DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode bit 3 Unimplemented: Read as ‘0’ bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output © 2009 Microchip Technology Inc. DS39637D-page 147

PIC18F2480/2580/4480/4580 TABLE 11-9: PORTE I/O SUMMARY Pin Name Function I/O TRIS Buffer Description RE0/RD/AN5 RE0 OUT 0 DIG LATE<0> data output. IN 1 ST PORTE<0> data input. RD IN 1 TTL PSP read enable input. AN5 IN 1 ANA A/D Input Channel 5. Enabled on POR; this analog input overrides the digital input (read as clear – low level). RE1/WR/AN6/C1OUT RE1 OUT 0 DIG LATE<1> data output. IN 1 ST PORTE<1> data input. WR IN 1 TTL PSP write enable input. AN6 IN 1 ANA A/D Input Channel 6. Enabled on POR; this analog input overrides the digital input (read as clear – low level). C1OUT OUT 0 DIG Comparator 1 output. RE2/CS/AN7/C2OUT RE2 OUT 0 DIG LATE<2> data output. IN 1 ST PORTE<2> data input. CS IN 1 TTL PSP chip select input. AN7 IN 1 ANA A/D Input Channel 7. Enabled on POR; this analog input overrides the digital input (read as clear – low level). C2OUT OUT 0 DIG Comparator 2 output. MCLR/VPP/RE3 MCLR IN x ST External Reset input. Disabled when MCLRE Configuration bit is ‘1’. VPP IN x ANA High-voltage detection; used by ICSP™ operation. RE3 IN 1 ST PORTE<3> data input. Disabled when MCLRE Configuration bit is ‘0’. Legend: PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTE(3) — — — — RE3(1,2) RE2 RE1 RE0 58 LATE(2) — — — — — LATE Output Latch Register 58 TRISE(3) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 58 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 56 CMCON(3) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both PIC18F2X80 and PIC18F4X80 devices. All other bits are implemented only when PORTE is implemented (i.e., PIC18F4X80 devices). 3: These registers are unimplemented on PIC18F2X80 devices. DS39637D-page 148 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 11.6 Parallel Slave Port The timing for the control signals in Write and Read modes is shown in Figure11-3 and Figure11-4, Note: The Parallel Slave Port is only available on respectively. PIC18F4X80 devices. FIGURE 11-2: PORTD AND PORTE In addition to its function as a general I/O port, PORTD BLOCK DIAGRAM can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is con- (PARALLEL SLAVE PORT) trolled by the 4 upper bits of the TRISE register (Register11-1). Setting control bit, PSPMODE One bit of PORTD (TRISE<4>), enables PSP operation, as long as the Data Bus Enhanced CCP module is not operating in dual output D Q or quad output PWM mode. In Slave mode, the port is RDx pin asynchronously readable and writable by the external WR LATD CK or world. WR PORTD Data Latch TTL The PSP can directly interface to an 8-bit micro- processor data bus. The external microprocessor can Q D read or write the PORTD latch as an 8-bit latch. Setting the control bit PSPMODE enables the PORTE I/O pins RD PORTD ENEN to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits of RD LATD the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port Configuration bits, Set Interrupt Flag PFCG<3:0> (ADCON1<3:0>), must also be set to PSPIF (PIR1<7>) ‘1010’. A write to the PSP occurs when both the CS and WR PORTE Pins lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set Read TTL RD when the write ends. Chip Select A read from the PSP occurs when both the CS and RD TTL CS lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data Write TTL WR to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the Note: I/O pins have diode protection to VDD and VSS. PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. © 2009 Microchip Technology Inc. DS39637D-page 149

PIC18F2480/2580/4480/4580 FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 58 LATD(1) LATD Output Latch Register 58 TRISD(1) PORTD Data Direction Register 58 PORTE(1) — — — — RE3 RE2 RE1 RE0 58 LATE(1) — — — — — LATE Output Latch Register 58 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 58 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 56 CMCON(1) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These registers are available on PIC18F4X80 devices only. DS39637D-page 150 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software-selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-bit counter in both 8-bit or 16-bit modes mode is shown in Figure12-1. Figure12-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin input edge 0 = Internal clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. DS39637D-page 151

PIC18F2480/2580/4480/4580 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter; the timer/counter. mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode, the module increments 12.2 Timer0 Reads and Writes in on every clock by default unless a different prescaler 16-Bit Mode value is selected (see Section12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhib- TMR0H is not the actual high byte of Timer0 in 16-bit ited for the following two instruction cycles. The user mode; it is actually a buffered version of the real high can work around this by writing an adjusted value to the byte of Timer0, which is not directly readable nor TMR0 register. writable (refer to Figure12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In Counter mode, Timer0 increments either on Timer0 without having to verify that the read of the high every rising or falling edge of pin, RA4/T0CKI. The and low byte were valid, due to a rollover between incrementing edge is determined by the Timer0 Source successive reads of the high and low byte. Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external Similarly, a write to the high byte of Timer0 must also clock input are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) 8 T0CS 3 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 T0CKI pin 1 ProPgrreasmcamlearble 0 SICynntleoccr nwkasitlh TMR0L HTigMh RB0yte 8 onT OMSvReet0r fIlFow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39637D-page 152 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>) which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before re- TMR0, BSF TMR0, etc.) clear the prescaler count. enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TMR0L Timer0 Register Low Byte 56 TMR0H Timer0 Register High Byte 56 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 56 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 58 Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39637D-page 153

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 154 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 13.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure13-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure13-2. features: The module incorporates its own low-power oscillator • Software-selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt-on-overflow Timer1 is controlled through the T1CON Control • Module Reset on CCP Special Event Trigger register (Register13-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. DS39637D-page 155

PIC18F2480/2580/4480/4580 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI and RC0/ • Synchronous Counter T1OSO/T13CKI pins become inputs. This means the • Asynchronous Counter values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte TMSRet1 IF (CCP Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator 11 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS<1:0> On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte TMSRet1 IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39637D-page 156 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 13.2 Timer1 16-Bit Read/Write Mode TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(1-4) Timer1 can be configured for 16-bit reads and writes (see Figure13-2). When the RD16 control bit Osc Type Freq C1 C2 (T1CON<7>) is set, the address for TMR1H is mapped LP 32kHz 27pF 27pF to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Note1: Microchip suggests these values as a Timer1 into the Timer1 High Byte Buffer register. This starting point in validating the oscillator provides the user with the ability to accurately read all circuit. 16 bits of Timer1 without having to determine whether 2: Higher capacitance increases the stability a read of the high byte, followed by a read of the low of the oscillator but also increases the byte, has become invalid due to a rollover between start-up time. reads. 3: Since each resonator/crystal has its own A write to the high byte of Timer1 must also take place characteristics, the user should consult through the TMR1H Buffer register. The Timer1 high the resonator/crystal manufacturer for byte is updated with the contents of TMR1H when a appropriate values of external write occurs to TMR1L. This allows a user to write all components. 16 bits to both the high and low bytes of Timer1 at once. 4: Capacitor values are for design guidance The high byte of Timer1 is not directly readable or only. writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. 13.3.1 USING TIMER1 AS A CLOCK Writes to TMR1H do not clear the Timer1 prescaler. SOURCE The prescaler is only cleared on writes to TMR1L. The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select 13.3 Timer1 Oscillator bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device An on-chip crystal oscillator circuit is incorporated switches to SEC_RUN mode; both the CPU and between pins, T1OSI (input) and T1OSO (amplifier peripherals are clocked from the Timer1 oscillator. If the output). It is enabled by setting the Timer1 Oscillator IDLEN bit (OSCCON<7>) is cleared and a SLEEP Enable bit, T1OSCEN (T1CON<3>). The oscillator is a instruction is executed, the device enters SEC_IDLE low-power circuit rated for 32kHz crystals. It will mode. Additional details are available in Section4.0 continue to run during all power-managed modes. The “Power-Managed Modes”. circuit for a typical LP oscillator is shown in Figure13-3. Whenever the Timer1 oscillator is providing the clock Table13-1 shows the capacitor selection for the Timer1 source, the Timer1 system clock status flag, T1RUN oscillator. (T1CON<6>), is set. This can be used to determine the The user must provide a software time delay to ensure controller’s current clocking mode. It can also indicate proper start-up of the Timer1 oscillator. the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the FIGURE 13-3: EXTERNAL Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being COMPONENTS FOR THE provided by the Timer1 oscillator or another source. TIMER1 LP OSCILLATOR 13.3.2 LOW-POWER TIMER1 OPTION C1 PIC18FXXXX 33 pF The Timer1 oscillator can operate at two distinct levels T1OSI of power consumption based on device configuration. When the LPT1OSC Configuration bit is set, the Timer1 XTAL oscillator operates in a low-power mode. When 32.768 kHz LPT1OSC is not set, Timer1 operates at a higher power level. Power consumption for a particular mode is rela- T1OSO tively constant, regardless of the device’s operating C2 mode. The default Timer1 configuration is the higher 33 pF power mode. Note: See the Notes with Table13-1 for additional As the low-power Timer1 mode tends to be more information about capacitor selection. sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. © 2009 Microchip Technology Inc. DS39637D-page 157

PIC18F2480/2580/4480/4580 13.3.3 TIMER1 OSCILLATOR LAYOUT 13.5 Resetting Timer1 Using the CCP CONSIDERATIONS Special Event Trigger The Timer1 oscillator circuit draws very little power If either of the CCP modules is configured in Compare during operation. Due to the low-power nature of the mode to generate a Special Event Trigger oscillator, it may also be sensitive to rapidly changing (CCP1M<3:0> or CCP2M<3:0>=1011), this signal signals in close proximity. will reset Timer1. The trigger from ECCP1 will also start The oscillator circuit, shown in Figure13-3, should be an A/D conversion if the A/D module is enabled (see located as close as possible to the microcontroller. Section16.3.4 “Special Event Trigger” for more There should be no circuits passing within the oscillator information.). circuit boundaries other than VSS or VDD. The module must be configured as either a timer or a If a high-speed circuit must be located near the oscilla- synchronous counter to take advantage of this feature. tor (such as the CCP1 pin in Output Compare or PWM When used this way, the CCPRH:CCPRL register pair mode, or the primary oscillator using the OSC2 pin), a effectively becomes a period register for Timer1. grounded guard ring around the oscillator circuit, as If Timer1 is running in Asynchronous Counter mode, shown in Figure13-4, may be helpful when used on a this Reset operation may not work. single-sided PCB or in addition to a ground plane. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take FIGURE 13-4: OSCILLATOR CIRCUIT precedence. WITH GROUNDED GUARD RING Note: The special event triggers from the ECCP1 module will not set the TMR1IF VDD interrupt flag bit (PIR1<0>). VSS 13.6 Using Timer1 as a Real-Time OSC1 Clock OSC2 Adding an external LP oscillator to Timer1 (such as the one described in Section13.3 “Timer1 Oscillator”) gives users the option to include RTC functionality to their applications. This is accomplished with an RC0 inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate RC1 the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can RC2 completely eliminate the need for a separate RTC device and battery backup. Note: Not drawn to scale. The application code routine, RTCisr, shown in Example13-1, demonstrates a simple method to 13.4 Timer1 Interrupt increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 The TMR1 register pair (TMR1H:TMR1L) increments register pair to overflow triggers the interrupt and calls from 0000h to FFFFh and rolls over to 0000h. The the routine, which increments the seconds counter by Timer1 interrupt, if enabled, is generated on overflow, one; additional counters for minutes and hours are which is latched in interrupt flag bit, TMR1IF incremented as the previous counter overflow. (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, Since the register pair is 16 bits wide, counting up to TMR1IE (PIE1<0>). overflow the register directly from a 32.768kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to pre- load it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. DS39637D-page 158 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1OSC ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done MOVLW .01 ; Reset hours to 1 MOVWF hours RETURN ; Done TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TMR1L Timer1 Register Low Byte 56 TMR1H TImer1 Register High Byte 56 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on PIC18F2X80 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39637D-page 159

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 160 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 module timer incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 2-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by- • 8-Bit Timer and Period registers (TMR2 and PR2, 16 prescale options; these are selected by the prescaler respectively) control bits, T2CKPS<1:0> (T2CON<1:0>). The value of • Readable and writable (both registers) TMR2 is compared to that of the Period register, PR2, on • Software programmable prescaler (1:1, 1:4 and each clock cycle. When the two values match, the com- 1:16) parator generates a match signal as the timer output. • Software programmable postscaler (1:1 through This signal also resets the value of TMR2 to 00h on the 1:16) next cycle and drives the output counter/postscaler (see • Interrupt on TMR2 to PR2 match Section14.2 “Timer2 Interrupt”). • Optional use as the shift clock for the MSSP The TMR2 and PR2 registers are both directly readable module and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. The module is controlled through the T2CON register Both the prescaler and postscaler counters are cleared (Register14-1), which enables or disables the timer on the following events: and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON • a write to the TMR2 register (T2CON<2>), to minimize power consumption. • a write to the T2CON register A simplified block diagram of the module is shown in • any device Reset (Power-on Reset, MCLR Reset, Figure14-1. Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2009 Microchip Technology Inc. DS39637D-page 161

PIC18F2480/2580/4480/4580 14.2 Timer2 Interrupt 14.3 TMR2 Output Timer2 also can generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) the CCP modules, where it is used as a time base for provides the input for the 4-bit output counter/post- operations in PWM mode. scaler. This counter generates the TMR2 match inter- Timer2 can be optionally used as the shift clock source rupt flag which is latched in TMR2IF (PIR1<1>). The for the MSSP module operating in SPI mode. Addi- interrupt is enabled by setting the TMR2 Match Inter- tional information is provided in Section18.0 “Master rupt Enable bit, TMR2IE (PIE1<1>). Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TMR2 Timer2 Register 56 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 56 PR2 Timer2 Period Register 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are unimplemented on PIC18F2X80 devices; always maintain these bits clear. DS39637D-page 162 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. A block diagram of the module’s The Timer3 module timer/counter incorporates these operation in Read/Write mode is shown in Figure15-2. features: The Timer3 module is controlled through the T3CON • Software-selectable operation as a 16-bit timer or register (Register15-1). It also selects the clock source counter options for the CCP modules (see Section16.1.1 • Readable and writable 8-bit registers (TMR3H “CCP Modules and Timer Resources” for more and TMR3L) information). • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3ECCP1:T3CCP1: Timer3 and Timer1 to CCP/ECCP Enable bits(1) 1x =Timer3 is the capture/compare clock source for both CCP and ECCP modules 01 =Timer3 is the capture/compare clock source for ECCP; Timer1 is the capture/compare clock source for CCP 00 = Timer1 is the capture/compare clock source for both CCP and ECCP modules bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Note 1: These bits and the ECCP module are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. DS39637D-page 163

PIC18F2480/2580/4480/4580 15.1 Timer3 Operation cycle (Fosc/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input Timer3 can operate in one of three modes: or the Timer1 oscillator if enabled. • Timer As with Timer1, the RC1/T1OSI and RC0/T1OSO/ • Synchronous Counter T13CKI pins become inputs when the Timer1 oscillator • Asynchronous Counter is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS<1:0> T3SYNC TMR3ON CCP/ECCP Special Event Trigger Clear TMR3 TMR3 Set T3ECCP1 TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 clock input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS<1:0> On/Off T3SYNC TMR3ON CCP/ECCP Special Event Trigger Clear TMR3 TMR3 Set T3ECCP1 TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39637D-page 164 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure15-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in the interrupt flag bit, TMR3IF from TMR3L will load the contents of the high byte of (PIR2<1>). This interrupt can be enabled or disabled Timer3 into the Timer3 High Byte Buffer register. This by setting or clearing the Timer3 Interrupt Enable bit, provides the user with the ability to accurately read all TMR3IE (PIE2<1>). 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low 15.5 Resetting Timer3 Using the CCP byte, has become invalid due to a rollover between Special Event Trigger reads. If the ECCP1 module is configured to generate a A write to the high byte of Timer3 must also take place special event trigger in Compare mode through the TMR3H Buffer register. The Timer3 high (ECCP1M<3:0>=1011), this signal will reset Timer3. byte is updated with the contents of TMR3H when a It will also start an A/D conversion if the A/D module is write occurs to TMR3L. This allows a user to write all enabled (see Section16.3.4 “Special Event Trigger” 16 bits to both the high and low bytes of Timer3 at once. for more information.). The high byte of Timer3 is not directly readable or The module must be configured as either a timer or writable in this mode. All reads and writes must take synchronous counter to take advantage of this feature. place through the Timer3 High Byte Buffer register. When used this way, the ECCPR2H:ECCPR2L register Writes to TMR3H do not clear the Timer3 prescaler. pair effectively becomes a period register for Timer3. The prescaler is only cleared on writes to TMR3L. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source In the event that a write to Timer3 coincides with a Special Event Trigger from a CCP module, the write will The Timer1 internal oscillator may be used as the clock take precedence. source for Timer3. The Timer1 oscillator is enabled by Note: The special event triggers from the setting the T1OSCEN (T1CON<3>) bit. To use it as the ECCP1 module will not set the TMR3IF Timer3 clock source, the TMR3CS bit must also be set. interrupt flag bit (PIR1<0>). As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section13.0 “Timer1 Module”. TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR2 OSCFIF CMIF(2) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(2) 58 PIE2 OSCFIE CMIE(2) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(2) 58 IPR2 OSCFIP CMIP(2) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(2) 57 TMR3L Timer3 Register Low Byte 57 TMR3H Timer3 Register High Byte 57 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56 T3CON RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. Note 1: These bits are available in PIC18F4X80 devices only. 2: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. © 2009 Microchip Technology Inc. DS39637D-page 165

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 166 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 16.0 CAPTURE/COMPARE/PWM The CCP1 module contains a 16-bit register which can (CCP) MODULES operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. PIC18F2480/2580 devices have one CCP module. For the sake of clarity, all CCP module operation in the PIC18F4480/4580 devices have two CCP following sections is described with respect to CCP1, (Capture/Compare/PWM) modules. CCP1, discussed but is equally applicable to ECCP1. in this chapter, implements standard Capture, Capture and Compare operations described in this Compare and Pulse-Width Modulation (PWM) modes. chapter apply to all standard and Enhanced CCP ECCP1 implements an Enhanced PWM mode. The modules. The operations of PWM mode, described in ECCP implementation is discussed in Section17.0 Section16.4 “PWM Mode”, apply to ECCP1 only. “Enhanced Capture/Compare/PWM (ECCP) Module”. REGISTER 16-1: CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DC1B<1:0>: CCP1 Module PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DC1B<9:2>) of the duty cycle are found in CCPR1L. bit 3-0 CCP1M<3:0>: CCP1 Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP1 module) 0001 = Reserved 0010 = Compare mode; toggle output on match (CCP1IF bit is set) 0011 = Reserved 0100 = Capture mode; every falling edge or CAN message received (time-stamp)(1) 0101 = Capture mode; every rising edge or CAN message received (time-stamp)(1) 0110 = Capture mode; every 4th rising edge or every 4th CAN message received (time-stamp)(1) 0111 = Capture mode; every 16th rising edge or every 16th CAN message received (time-stamp)(1) 1000 = Compare mode; initialize CCP1 pin low; on compare match, force CCP1 pin high (CCPIF bit is set) 1001 = Compare mode; initialize CCP pin high; on compare match, force CCP1 pin low (CCPIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCP1IF bit is set, CCP1 pin reflects I/O state) 1011 = Compare mode; trigger special event; reset timer (TMR1 or TMR3, CCP1IF bit is set) 11xx = PWM mode Note 1: Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source. © 2009 Microchip Technology Inc. DS39637D-page 167

PIC18F2480/2580/4480/4580 16.1 CCP Module Configuration TABLE 16-1: CCP MODE – TIMER RESOURCE Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a CCP/ECCP Mode Timer Resource data register (CCPRx). The data register, in turn, is Capture Timer1 or Timer3 comprised of two 8-bit registers: CCPRxL (low byte) Compare Timer1 or Timer3 and CCPRxH (high byte). All registers are both PWM Timer2 readable and writable. The assignment of a particular timer to a module is 16.1.1 CCP MODULES AND TIMER determined by the Timer to CCP enable bits in the RESOURCES T3CON register (Register15-1). Both modules may be The CCP modules utilize Timers 1, 2 or 3, depending active at any given time and may share the same timer on the mode selected. Timer1 and Timer3 are available resource if they are configured to operate in the same to modules in Capture or Compare modes, while mode (Capture/Compare or PWM) at the same time. Timer2 is available for modules in PWM mode. The interactions between the two modules are summarized in Figure16-1 and Figure16-2. TABLE 16-2: INTERACTIONS BETWEEN CCP1 AND ECCP1 FOR TIMER RESOURCES CCP1 Mode ECCP1 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. Time base can be different for each CCP. Capture Compare CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on trigger event can also be done. Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Compare Either module can be configured for the Special Event Trigger to reset the time base. Automatic A/D conversions on ECCP1 trigger event can be done. Conflicts may occur if both modules are using the same time base. Capture PWM(1) None Compare PWM(1) None PWM(1) Capture None PWM(1) Compare None PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). Note 1: Includes standard and Enhanced PWM operation. DS39637D-page 168 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 16.2 Capture Mode 16.2.4 CCP PRESCALER In Capture mode, the CCPR1H:CCPR1L register pair There are four prescaler settings in Capture mode; they captures the 16-bit value of the TMR1 or TMR3 regis- are specified as part of the operating mode selected by ters when an event occurs on the CCP1 pin (RB3 or the mode select bits (CCP1M<3:0>). Whenever the RC1, depending on device configuration). An event is CCP module is turned off or the CCP module is not in defined as one of the following: Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. • every falling edge Switching from one capture prescaler to another may • every rising edge generate an interrupt. Also, the prescaler counter will • every 4th rising edge not be cleared; therefore, the first capture may be from • every 16th rising edge a non-zero prescaler. Example16-1 shows the recom- The event is selected by the mode select bits, mended method for switching between capture CCP1M<3:0> (CCP1CON<3:0>). When a capture is prescalers. This example also clears the prescaler made, the interrupt request flag bit, CCP1IF (PIR2<1>), counter and will not generate the “false” interrupt. is set; it must be cleared in software. If another capture 16.2.5 CAN MESSAGE TIME-STAMP occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured The CAN capture event occurs when a message is value. received in any of the receive buffers. When config- ured, the CAN module provides the trigger to the CCP1 16.2.1 CCP1/ECCP1 PIN CONFIGURATION module to cause a capture event. This feature is In Capture mode, the appropriate CCP1/ECCP1 pin provided to “time-stamp” the received CAN messages. should be configured as an input by setting the This feature is enabled by setting the CANCAP bit of corresponding TRIS direction bit. the CAN I/O Control register (CIOCON<4>). The message receive signal from the CAN module then Note: If RC2/CCP1 or RD4/PSP4/ECCP1/P1A takes the place of the events on RC2/CCP1. is configured as an output, a write to the port can cause a capture condition. If this feature is selected, then four different capture options for CCP1M<3:0> are available: 16.2.2 TIMER1/TIMER3 MODE SELECTION • 0100 – every time a CAN message is received The timers that are to be used with the capture feature • 0101 – every time a CAN message is received (Timer1 and/or Timer3) must be running in Timer mode • 0110 – every 4th time a CAN message is or Synchronized Counter mode. In Asynchronous received Counter mode, the capture operation may not work. • 0111 – capture mode, every 16th time a CAN The timer to be used with each CCP module is selected message is received in the T3CON register (see Section16.1.1 “CCP Modules and Timer Resources”). EXAMPLE 16-1: CHANGING BETWEEN 16.2.3 SOFTWARE INTERRUPT CAPTURE PRESCALERS When the Capture mode is changed, a false capture CLRF CCP1CON ; Turn CCP module off interrupt may be generated. The user should keep the MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode CCPxIE interrupt enable bit clear to avoid false inter- ; value and CCP ON rupts. The interrupt flag bit, CCPxIF, should also be MOVWF CCP1CON ; Load CCP1CON with cleared following any such change in operating mode. ; this value © 2009 Microchip Technology Inc. DS39637D-page 169

PIC18F2480/2580/4480/4580 FIGURE 16-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF T3ECCP1 TMR3 Enable CCP1 pin Prescaler and CCPR1H CCPR1L ÷ 1, 4, 16 Edge Detect TMR1 T3ECCP1 Enable 4 TMR1H TMR1L CCP1CON<3:0> Set ECCP1IF 4 Q1:Q4 4 ECCP1CON<3:0> T3CCP1 TMR3H TMR3L T3ECCP1 TMR3 Enable ECCP1 pin Prescaler and ECCPR1H ECCPR1L ÷ 1, 4, 16 Edge Detect TMR1 Enable T3ECCP1 TMR1H TMR1L T3CCP1 DS39637D-page 170 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 16.3 Compare Mode 16.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is Timer1 and/or Timer3 must be running in Timer mode constantly compared against either the TMR1 or TMR3 or Synchronized Counter mode if the CCP module is register pair value. When a match occurs, the CCP1 using the compare feature. In Asynchronous Counter pin can be: mode, the compare operation may not work. • driven high 16.3.3 SOFTWARE INTERRUPT MODE • driven low When the Generate Software Interrupt mode is chosen • toggled (high-to-low or low-to-high) (CCP1M<3:0> = 1010), the CCP1 pin is not affected. • remain unchanged (that is, reflects the state of the Only a CCP interrupt is generated, if enabled, and the I/O latch) CCP1IE bit is set. The action on the pin is based on the value of the mode 16.3.4 SPECIAL EVENT TRIGGER select bits (ECCP1M<3:0>). At the same time, the interrupt flag bit, ECCP1IF, is set. Both CCP modules are equipped with a Special Event Trigger. This is an internal hardware signal generated 16.3.1 CCP PIN CONFIGURATION in Compare mode to trigger actions by other modules. The user must configure the CCP1 pin as an output by The Special Event Trigger is enabled by selecting clearing the appropriate TRIS bit. the Compare Special Event Trigger mode (CCP1M<3:0>=1011). Note: Clearing the CCP1CON register will force For either CCP module, the Special Event Trigger the RC2 compare output latch (depending resets the Timer register pair for whichever timer on device configuration) to the default low resource is currently assigned as the module’s time level. This is not the PORTC I/O data base. This allows the CCPR1 registers to serve as a latch. programmable period register for either timer. FIGURE 16-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger CCPR1H CCPR1L Set CCP1IF (Timer1 Reset) CCP1 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP1CON<3:0> 0 TMR1H TMR1L 0 1 TMR3H TMR3L 1 Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) T3CCP1 T3ECCP1 Set CCP1IF ECCP1 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable ECCPR1H ECCPR1L ECCP1CON<3:0> © 2009 Microchip Technology Inc. DS39637D-page 171

PIC18F2480/2580/4480/4580 TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 RCON IPEN SBOREN(3) — RI TO PD POR BOR 56 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR2 OSCFIP CMIP(2) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(2) 58 PIR2 OSCFIF CMIF(2) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(2) 58 PIE2 OSCFIE CMIE(2) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(2) 57 TRISB PORTB Data Direction Register 58 TRISC PORTC Data Direction Register 58 TMR1L Timer1 Register Low Byte 56 TMR1H Timer1 Register High Byte 56 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56 TMR3H Timer3 Register High Byte 57 TMR3L Timer3 Register Low Byte 57 T3CON RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON 57 CCPR1L Capture/Compare/PWM Register 1 Low Byte 57 CCPR1H Capture/Compare/PWM Register 1 High Byte 57 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 57 ECCPR1L(1) Enhanced Capture/Compare/PWM Register 1 Low Byte 57 ECCPR1H(1) Enhanced Capture/Compare/PWM Register 1 High Byte 57 ECCP1CON(1) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture, compare, Timer1 or Timer3. Note 1: These bits or registers are available on PIC18F4X80 devices only. 2: These bits are available on PIC18F4X80 devices and reserved on PIC18F2X80 devices. 3: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. DS39637D-page 172 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 16.4 PWM Mode FIGURE 16-4: PWM OUTPUT In Pulse-Width Modulation (PWM) mode, the CCP1 pin Period produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP1 pin an output. Duty Cycle Note: Clearing the CCP1CON register will force TMR2 = PR2 the RC2 output latch (depending on TMR2 = Duty Cycle device configuration) to the default low TMR2 = PR2 level. This is not the PORTC I/O data latch. 16.4.1 PWM PERIOD Figure16-3 shows a simplified block diagram of the The PWM period is specified by writing to the PR2 CCP module in PWM mode. (PR4) register. The PWM period can be calculated For a step-by-step procedure on how to set up the CCP using the following formula. module for PWM operation, see Section16.4.4 “Setup for PWM Operation”. EQUATION 16-1: PWM Period = (PR2) + 1] • 4 • TOSC • FIGURE 16-3: SIMPLIFIED PWM BLOCK (TMR2 Prescale Value) DIAGRAM PWM frequency is defined as 1/[PWM period]. CCP1CON<5:4> Duty Cycle Registers When TMR1 (TMR3) is equal to PR2 (PR2), the following three events occur on the next increment CCPR1L cycle: • TMR2 is cleared • The CCP1 pin is set (exception: if PWM duty CCPR1H (Slave) cycle=0%, the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into Comparator R Q CCPR1H RC2/CCP1 Note: The Timer2 postscalers (see Section14.0 PORTC<2> TMR2 (Note 1) “Timer2 Module”) are not used in the S determination of the PWM frequency. The postscaler could be used to have a servo Comparator TRISC<2> update rate at a different frequency than Clear Timer, CCP1 pin and the PWM output. latch D.C. PR2 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the Note1: The 8-bit TMR2 value is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create the CCPR1L register and to the CCP1CON<5:4> bits. Up 10-bit time base. to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> bits contain the two LSbs. This 10-bit value is represented by A PWM output (Figure16-4) has a time base (period) CCPR1L:CCP1CON<5:4>. The following equation is and a time that the output stays high (duty cycle). The used to calculate the PWM duty cycle in time. frequency of the PWM is the inverse of the period (1/period). EQUATION 16-2: PWM Duty Cycle=(CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. © 2009 Microchip Technology Inc. DS39637D-page 173

PIC18F2480/2580/4480/4580 The CCPR1H register and a 2-bit internal latch are EQUATION 16-3: used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM log⎛FOSC⎞ operation. ⎝FPWM⎠ PWM Resolution (max) = bits When the CCPR1H and 2-bit latch match TMR2, log(2) concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Note: If the PWM duty cycle value is longer than The maximum PWM resolution (bits) for a given PWM the PWM period, the CCP1 pin will not be frequency is given by the equation. cleared. TABLE 16-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 16.4.3 PWM AUTO-SHUTDOWN 16.4.4 SETUP FOR PWM OPERATION (ECCP1 ONLY) The following steps should be taken when configuring The PWM auto-shutdown features of the Enhanced the CCP module for PWM operation: CCP module are available to ECCP1 in 1. Set the PWM period by writing to the PR2 PIC18F4480/4580 (40/44-pin) devices. The operation register. of this feature is discussed in detail in Section17.4.7 2. Set the PWM duty cycle by writing to the “Enhanced PWM Auto-Shutdown”. CCPR1L register and CCP1CON<5:4> bits. Auto-shutdown features are not available for CCP1. 3. Make the CCP1 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. DS39637D-page 174 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 16-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 RCON IPEN SBOREN(2) — RI TO PD POR BOR 56 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TRISB PORTB Data Direction Register 58 TRISC PORTC Data Direction Register 58 TMR2 Timer2 Register 56 PR2 Timer2 Period Register 56 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 56 CCPR1L Capture/Compare/PWM Register 1 Low Byte 57 CCPR1H Capture/Compare/PWM Register 1 High Byte 57 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 57 ECCPR1L(1) Enhanced Capture/Compare/PWM Register 1 Low Byte 57 ECCPR1H(1) Enhanced Capture/Compare/PWM Register 1 High Byte 57 ECCP1CON(1) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: These registers are unimplemented on PIC18F2X80 devices. 2: The SBOREN bit is only available when CONFIG2L<1:0>=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. © 2009 Microchip Technology Inc. DS39637D-page 175

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 176 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 17.0 ENHANCED Enhanced features are discussed in detail in CAPTURE/COMPARE/PWM Section17.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of the (ECCP) MODULE ECCP module are the same as described for the standard CCP module. Note: The ECCP1 module is implemented only in PIC18F4X80 (40/44-pin) devices. The control register for the Enhanced CCP module is shown in Register17-1. It differs from the CCP1CON In PIC18F4480/4580 devices, ECCP1 is implemented register in PIC18F2480/2580 devices in that the two as a standard CCP module with Enhanced PWM Most Significant bits are implemented to control PWM capabilities. These include the provision for 2 or functionality. 4output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The REGISTER 17-1: ECCP1CON REGISTER (ECCP1 MODULE, PIC18F4480/4580 DEVICES) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 EPWM1M<1:0>: Enhanced PWM Output Configuration bits If ECCP1M<3:2> = 00, 01, 10: xx =P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If ECCP1M<3:2> = 11: 00 =Single output: P1A modulated; P1B, P1C, P1D assigned as port pins 01 =Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 =Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 EDC1B<1:0>: ECCP1 Module PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in ECCPR1L. bit 3-0 ECCP1M<3:0>: Enhanced CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP1 module) 0001 = Reserved 0010 = Compare mode; toggle output on match 0011 = Reserved 0100 = Capture mode; every falling edge 0101 = Capture mode; every rising edge 0110 = Capture mode; every 4th rising edge 0111 = Capture mode; every 16th rising edge 1000 = Compare mode; initialize ECCP1 pin low; set output on compare match (set ECCP1IF) 1001 = Compare mode; initialize ECCP1 pin high; clear output on compare match (set ECCP1IF) 1010 = Compare mode; generate software interrupt only; ECCP1 pin reverts to I/O state 1011 = Compare mode; trigger special event (ECCP1 resets TMR1 or TMR3, sets ECCP1IF bit and starts the A/D conversion on ECCP1 match) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. DS39637D-page 177

PIC18F2480/2580/4480/4580 In addition to the expanded range of modes available 17.2 Capture and Compare Modes through the CCP1CON register, the ECCP module has two additional registers associated with Enhanced Except for the operation of the Special Event Trigger PWM operation and auto-shutdown features. They are: discussed below, the Capture and Compare modes of the ECCP1 module are identical in operation to that of • ECCP1DEL (Dead-Band Delay) CCP1. These are discussed in detail in Section16.2 • ECCP1AS (Auto-Shutdown Control) “Capture Mode” and Section16.3 “Compare Mode”. 17.1 ECCP Outputs and Configuration 17.2.1 SPECIAL EVENT TRIGGER The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. The Special Event Trigger output of ECCP1 resets the These outputs, designated P1A through P1D, are TMR1 or TMR3 register pair, depending on which timer multiplexed with I/O pins on PORTC and PORTD. The resource is currently selected. This allows the ECCP1 outputs that are active depend on the CCP operating register to effectively be a 16-bit programmable period mode selected. The pin assignments are summarized register for Timer1 or Timer3. The Special Event in Table17-1. Trigger for ECCP1 can also start an A/D conversion. In order to start the conversion, the A/D Converter must To configure the I/O pins as PWM outputs, the proper be previously enabled. PWM mode must be selected by setting the EPWM1M<1:0> and CCP1M<3:0> bits. The appropriate 17.3 Standard PWM Mode TRISC and TRISD direction bits for the port pins must also be set as outputs. When configured in Single Output mode, the ECCP module functions identically to the standard CCP 17.1.1 ECCP MODULES AND TIMER module in PWM mode, as described in Section16.4 RESOURCES “PWM Mode”. This is also sometimes referred to as Like the standard CCP modules, the ECCP module can “Compatible CCP” mode, as in Table17-1. utilize Timers 1, 2 or 3, depending on the mode Note: When setting up single output PWM opera- selected. Timer1 and Timer3 are available for modules tions, users are free to use either of the in Capture or Compare modes, while Timer2 is processes described in Section16.4.4 available for modules in PWM mode. Interactions “Setup for PWM Operation” or between the standard and Enhanced CCP modules are Section17.4.9 “Setup for PWM Opera- identical to those described for standard CCP modules. tion”. The latter is more generic, but will Additional details on timer resources are provided in work for either single or multi-output PWM. Section16.1.1 “CCP Modules and Timer Resources”. TABLE 17-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES CCP1CON ECCP Mode RD4 RD5 RD6 RD7 Configuration All PIC18F4480/4580 Devices: Compatible CCP 00xx 11xx CCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7 Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. DS39637D-page 178 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 17.4 Enhanced PWM Mode 17.4.1 PWM PERIOD The Enhanced PWM mode provides additional PWM The PWM period is specified by writing to the PR2 output options for a broader range of control applica- register. The PWM period can be calculated using the tions. The module is a backward compatible version of following equation. the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to EQUATION 17-1: select the polarity of the signal (either active-high or PWM Period = [(PR2) + 1] • 4 • TOSC • active-low). The module’s output mode and polarity are (TMR2 Prescale Value) configured by setting the EPWM1M<1:0> and CCP1M<3:0> bits of the ECCP1CON register. PWM frequency is defined as 1/[PWM period]. When Figure17-1 shows a simplified block diagram of PWM TMR2 is equal to PR2, the following three events occur operation. All control registers are double-buffered and on the next increment cycle: are loaded at the beginning of a new PWM cycle (the • TMR2 is cleared period boundary when Timer2 resets) in order to • The ECCP1 pin is set (if PWM duty cycle=0%, prevent glitches on any of the outputs. The exception is the ECCP1 pin will not be set) the ECCP PWM Dead-Band Delay register, • The PWM duty cycle is copied from ECCPR1L ECCP1DEL, which is loaded at either the duty cycle into ECCPR1H boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until Note: The Timer2 postscaler (see Section14.0 the assigned timer resets instead of starting immedi- “Timer2 Module”) is not used in the ately. This means that Enhanced PWM waveforms do determination of the PWM frequency. The not exactly match the standard PWM waveforms, but postscaler could be used to have a servo are instead offset by one full instruction cycle (4 TOSC). update rate at a different frequency than As before, the user must manually configure the the PWM output. appropriate TRIS bits for output. FIGURE 17-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> EPWM1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 ECCPR1L ECCP1/P1A ECCP1/P1A TRISD<4> ECCPR1H (Slave) P1B P1B Output TRISD<5> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISD<6> P1D P1D Comparator Clear Timer, TRISD<7> set ECCP1 pin and latch D.C. PR2 ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. DS39637D-page 179

PIC18F2480/2580/4480/4580 17.4.2 PWM DUTY CYCLE EQUATION 17-3: The PWM duty cycle is specified by writing to the log(FOSC) ECCPR1L register and to the ECCP1CON<5:4> bits. FPWM Up to 10-bit resolution is available. The ECCPR1L PWM Resolution (max) = bits log(2) contains the eight MSbs and the ECCP1CON<5:4> bits contain the two LSbs. This 10-bit value is represented by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle is calculated by the following equation. Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be EQUATION 17-2: cleared. PWM Duty Cycle = (ECCPR1L:ECCP1CON<5:4> • 17.4.3 PWM OUTPUT CONFIGURATIONS TOSC • (TMR2 Prescale Value) The EPWM1M<1:0> bits in the ECCP1CON register allow one of four configurations: ECCPR1L and ECCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into • Single Output ECCPR1H until a match between PR2 and TMR2 • Half-Bridge Output occurs (i.e., the period is complete). In PWM mode, • Full-Bridge Output, Forward mode ECCPR1H is a read-only register. • Full-Bridge Output, Reverse mode The ECCPR1H register and a 2-bit internal latch are The Single Output mode is the standard PWM mode used to double-buffer the PWM duty cycle. This discussed in Section17.4 “Enhanced PWM Mode”. double-buffering is essential for glitchless PWM opera- The Half-Bridge and Full-Bridge Output modes are tion. When the ECCPR1H and 2-bit latch match TMR2, covered in detail in the sections that follow. concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the ECCP1 pin is cleared. The The general relationship of the outputs in all maximum PWM resolution (bits) for a given PWM configurations is summarized in Figure17-2. frequency is given by the following equation. TABLE 17-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39637D-page 180 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 17-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 Duty PR2 + 1 ECCP1CON SIGNAL Cycle <7:6> Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive FIGURE 17-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 PR2 + 1 Duty ECCP1CON SIGNAL Cycle <7:6> Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section17.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. DS39637D-page 181

PIC18F2480/2580/4480/4580 17.4.4 HALF-BRIDGE MODE FIGURE 17-4: HALF-BRIDGE PWM OUTPUT In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output Period Period signal is output on the P1A pin, while the complemen- tary PWM output signal is output on the P1B pin Duty Cycle (Figure17-4). This mode can be used for half-bridge P1A(2) applications, as shown in Figure17-5, or for full-bridge td applications where four power switches are being td modulated with two PWM signals. P1B(2) In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through (1) (1) (1) current in half-bridge power devices. The value of bits, PDC<6:0>, sets the number of instruction cycles before td = Dead-Band Delay the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section17.4.6 PR2 register. “Programmable Dead-Band Delay” for more details 2: Output signals are shown as active-high. of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTD<4> and PORTD<5> data latches, the TRISD<4> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 17-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) PIC18F2X80/4X80 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F2X80/4X80 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS39637D-page 182 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 17.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<5>, PORTD<6> and In Full-Bridge Output mode, four pins are used as PORTD<7> data latches. The TRISD<4>, TRISD<5>, outputs; however, only two outputs are active at a time. TRISD<6> and TRISD<7> bits must be cleared to In the Forward mode, pin P1A is continuously active make the P1A, P1B, P1C and P1D pins outputs. and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure17-6. FIGURE 17-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. DS39637D-page 183

PIC18F2480/2580/4480/4580 FIGURE 17-7: EXAMPLE OF FULL-BRIDGE OUTPUT APPLICATION V+ PIC18F2X80/4X80 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 17.4.5.1 Direction Change in Full-Bridge Figure17-9 shows an example where the PWM direc- Output Mode tion changes from forward to reverse at a near 100% duty cycle. At time t1, the outputs, P1A and P1D, In the Full-Bridge Output mode, the EPWM1M1 bit in become inactive, while output, P1C, becomes active. In the CCP1CON register allows the user to control the this example, since the turn-off time of the power forward/reverse direction. When the application firm- devices is longer than the turn-on time, a shoot-through ware changes this direction control bit, the module will current may flow through power devices, QC and QD assume the new direction on the next PWM cycle. (see Figure17-7), for the duration of ‘t’. The same Just before the end of the current PWM period, the phenomenon will occur to power devices, QA and QB, modulated outputs (P1B and P1D) are placed in their for PWM direction change from reverse to forward. inactive state, while the unmodulated outputs (P1A and If changing PWM direction at high duty cycle is required P1C) are switched to drive in the opposite direction. for an application, one of the following requirements This occurs in a time interval of (4 TOSC * (Timer2 must be met: Prescale Value) before the next PWM period begins. The Timer2 prescaler will be either 1, 4 or 16, depend- 1. Reduce PWM for a PWM period before ing on the value of the T2CKPS bits (T2CON<1:0>). changing directions. During the interval from the switch of the unmodulated 2. Use switch drivers that can drive the switches off outputs to the beginning of the next period, the faster than they can drive them on. modulated outputs (P1B and P1D) remain inactive. Other options to prevent shoot-through current may This relationship is shown in Figure17-8. exist. Note that in the Full-Bridge Output mode, the CCP1 module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39637D-page 184 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 17-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 17-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC t (2) ON External Switch C(1) t (3) OFF External Switch D(1) Potential t = t – t (2,3) OFF ON Shoot-Through Current(1) Note 1: All signals are shown as active-high. 2: t is the turn-on delay of power switch QC and its driver. ON 3: t is the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. DS39637D-page 185

PIC18F2480/2580/4480/4580 17.4.6 PROGRAMMABLE DEAD-BAND When a shutdown occurs, the output pins are DELAY asynchronously placed in their shutdown states, specified by the PSSAC<1:0> and PSS1BD<1:0> bits Note: Programmable dead-band delay is not (ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/P1D) implemented in PIC18F2X80 devices with may be set to drive high, drive low or be tri-stated (not standard CCP modules. driving). The ECCPASE bit (ECCP1AS<7>) is also set to In half-bridge applications where all power switches are hold the Enhanced PWM outputs in their shutdown modulated at the PWM frequency at all times, the power states. switches normally require more time to turn off than to The ECCPASE bit is set by hardware when a shutdown turn on. If both the upper and lower power switches are event occurs. If automatic restarts are not enabled, the switched at the same time (one turned on and the other ECCPASE bit is cleared by firmware when the cause of turned off), both switches may be on for a short period of the shutdown clears. If automatic restarts are enabled, time until one switch completely turns off. During this the ECCPASE bit is automatically cleared when the brief interval, a very high current (shoot-through current) cause of the auto-shutdown has cleared. may flow through both power switches, shorting the If the ECCPASE bit is set when a PWM period begins, bridge supply. To avoid this potentially destructive the PWM outputs remain in their shutdown state for that shoot-through current from flowing during switching, entire PWM period. When the ECCPASE bit is cleared, turning on either of the power switches is normally the PWM outputs will return to normal operation at the delayed to allow the other switch to completely turn off. beginning of the next PWM period. In the Half-Bridge Output mode, a digitally program- Note: Writing to the ECCPASE bit is disabled mable, dead-band delay is available to avoid while a shutdown condition is active. shoot-through current from destroying the bridge power switches. The delay occurs at the signal transi- tion from the non-active state to the active state (see Note: If the dead-band delay value is increased Figure17-4 for illustration). Bits, PDC<6:0< of the after the dead-band time has elapsed, that ECCP1DEL register (Register17-2), set the delay new value takes effect immediately. This period in terms of microcontroller instruction cycles happens even if the PWM pulse is high (TCY or 4 TOSC). These bits are not available on and can appear to be a glitch. Dead-band PIC18F2X80 devices, as the standard CCP module values must be changed during the does not support half-bridge operation. dead-band time or before ECCP is active 17.4.7 ENHANCED PWM AUTO-SHUTDOWN When the CCP1 is programmed for any of the Enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. A shutdown event can be caused by either of the comparator modules, a low level on the RB0/INT0/FLT0/AN10 pin, or any combination of these three sources. The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a digital signal on the INT0 pin can also trigger a shutdown. The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The auto-shutdown sources to be used are selected using the ECCPAS<2:0> bits (ECCP1AS<6:4>). DS39637D-page 186 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 17-2: ECCP1DEL: ECCP PWM DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits(1) Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Note 1: Reserved on PIC18F2X80 devices; maintain these bits clear. REGISTER 17-3: ECCP1AS: ECCP AUTO-SHUTDOWN CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits 111 = RB0 or Comparator 1 or Comparator 2 110 = RB0 or Comparator 2 101 = RB0 or Comparator 1 100 = RB0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled bit 3-2 PSSAC<1:0>: Pins, A and C, Shutdown State Control bits 1x = Pins, A and C, tri-state (PIC18F4X80 devices) 01 = Drive Pins, A and C, to ‘1’ 00 = Drive Pins, A and C, to ‘0’ bit 1-0 PSSBD<1:0>: Pins, B and D, Shutdown State Control bits(1) 1x = Pins, B and D, tri-state 01 = Drive Pins, B and D, to ‘1’ 00 = Drive Pins, B and D, to ‘0’ Note 1: Reserved on PIC18F2X80 devices; maintain these bits clear. © 2009 Microchip Technology Inc. DS39637D-page 187

PIC18F2480/2580/4480/4580 17.4.7.1 Auto-Shutdown and Auto-Restart 17.4.8 START-UP CONSIDERATIONS The auto-shutdown feature can be configured to allow When the ECCP module is used in the PWM mode, the automatic restarts of the module following a shutdown application hardware must use the proper external pull-up event. This is enabled by setting the PRSEN bit of the and/or pull-down resistors on the PWM output pins. When ECCP1DEL register (ECCP1DEL<7>). the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits In Shutdown mode with PRSEN = 1 (Figure17-10), the must keep the power switch devices in the off state until ECCPASE bit will remain set for as long as the cause the microcontroller drives the I/O pins with the proper of the shutdown continues. When the shutdown condi- signal levels, or activates the PWM output(s). tion clears, the ECCP1ASE bit is cleared. If PRSEN =0 (Figure17-11), once a shutdown condition occurs, the The CCP1M<1:0> bits (ECCP1CON<1:0>) allow the ECCPASE bit will remain set until it is cleared by user to choose whether the PWM output signals are firmware. Once ECCPASE is cleared, the Enhanced active-high or active-low for each pair of PWM output PWM will resume at the beginning of the next PWM pins (P1A/P1C and P1B/P1D). The PWM output period. polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configura- Note: Writing to the ECCPASE bit is disabled tion while the PWM pins are configured as outputs is while a shutdown condition is active. not recommended, since it may result in damage to the Independent of the PRSEN bit setting, if the application circuits. auto-shutdown source is one of the comparators, the The P1A, P1B, P1C and P1D output latches may not be shutdown condition is a level. The ECCPASE bit in the proper states when the PWM module is initialized. cannot be cleared as long as the cause of the shutdown Enabling the PWM pins for output at the same time as persists. the ECCP module may cause damage to the applica- The Auto-Shutdown mode can be forced by writing a ‘1’ tion circuit. The ECCP module must be enabled in the to the ECCPASE bit. proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The com- pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 17-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) PWM Period ShutdownEvent ECCPASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes FIGURE 17-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) PWM Period ShutdownEvent ECCPASE bit PWM Activity Normal PWM ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes DS39637D-page 188 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 17.4.9 SETUP FOR PWM OPERATION 7. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). The following steps should be taken when configuring 8. Configure and start TMR2: the ECCP module for PWM operation: • Clear the TMR2 interrupt flag bit by clearing 1. Configure the PWM pins, P1A and P1B (and the TMR2IF bit (PIR1<1>). P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). 2. Set the PWM period by loading the PR2 register. • Enable Timer2 by setting the TMR2ON bit 3. Configure the ECCP1 module for the desired (T2CON<2>). PWM mode and configuration by loading the ECCP1CON register with the appropriate 9. Enable PWM outputs after a new PWM cycle values: has started: • Select one of the available output • Wait until TMRn overflows (TMRnIF bit is set). configurations and direction with the • Enable the ECCP1/P1A, P1B, P1C and/or EPWM1M<1:0> bits. P1D pin outputs by clearing the respective TRIS bits. • Select the polarities of the PWM output signals with the ECCP1M<3:0> bits. • Clear the ECCPASE bit (ECCP1AS<7>). 4. Set the PWM duty cycle by loading the 17.4.10 EFFECTS OF A RESET ECCPR1L register and ECCP1CON<5:4> bits. 5. For Half-Bridge Output mode, set the Both Power-on Reset and subsequent Resets will force dead-band delay by loading ECCP1DEL<6:0> all ports to Input mode and the CCP registers to their with the appropriate value. Reset states. 6. If auto-shutdown operation is required, load the This forces the Enhanced CCP module to reset to a ECCP1AS register: state compatible with the standard CCP module. • Select the auto-shutdown sources using the ECCPAS<2:0> bits. • Select the shutdown states of the PWM output pins using PSSAC<1:0> and PSSBD<1:0> bits. • Set the ECCPASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. © 2009 Microchip Technology Inc. DS39637D-page 189

PIC18F2480/2580/4480/4580 TABLE 17-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 RCON IPEN SBOREN — RI TO PD POR BOR 56 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR2 OSCFIP CMIP(3) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(3) 57 PIR2 OSCFIF CMIF(3) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(3) 58 PIE2 OSCFIE CMIE(3) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(3) 58 TRISB PORTB Data Direction Register 58 TRISC PORTC Data Direction Register 58 TRISD(1) PORTD Data Direction Register 58 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 56 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 56 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56 TMR2 Timer2 Module Register 56 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 56 PR2 Timer2 Period Register 56 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 57 TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 57 T3CON RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON 57 ECCPR1L(2) Enhanced Capture/Compare/PWM Register 1 (LSB) 57 ECCPR1H(2) Enhanced Capture/Compare/PWM Register 1 (MSB) 57 ECCP1CON(2) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 57 ECCP1AS(2) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 57 ECCP1DEL(2) PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: These bits are available on PIC18F4X80 devices only. 2: These bits or registers are unimplemented in PIC18F2X80 devices; always maintain these bit clear. 3: These bits are available on PIC18F4X80 and reserved on PIC18F2X80 devices. DS39637D-page 190 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.0 MASTER SYNCHRONOUS 18.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish 18.1 Master SSP (MSSP) Module communication, typically three pins are used: Overview • Serial Data Out (SDO) – RC5/SDO • Serial Data In (SDI) – RC4/SDI/SDA The Master Synchronous Serial Port (MSSP) module is • Serial Clock (SCK) – RC3/SCK/SCL a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave devices may be serial EEPROMs, shift registers, mode of operation: display drivers, A/D Converters, etc. The MSSP • Slave Select (SS) – RA5/AN4/SS/HLVDIN module can operate in one of two modes: Figure18-1 shows the block diagram of the MSSP • Serial Peripheral Interface (SPI) module when operating in SPI mode. • Inter-Integrated Circuit (I2C) - Full Master mode FIGURE 18-1: MSSP BLOCK DIAGRAM - Slave mode (with general address call) (SPIMODE) The I2C interface supports the following modes in Internal hardware: Data Bus • Master mode Read Write • Multi-Master mode • Slave mode SSPBUF reg 18.2 Control Registers The MSSP module has three associated registers. SSPSR reg These include a status register (SSPSTAT) and two SDI bit 0 Shift control registers (SSPCON1 and SSPCON2). The use Clock of these registers and their individual configuration bits differ significantly depending on whether the MSSP SDO module is operated in SPI or I2C mode. Additional details are provided under the individual SS Control sections. Enable SS Edge Select 2 Clock Select SSPM<3:0> SMP:CKE 2 4 (T M R 2 O u tp u t) 2 Edge Select SCK Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit © 2009 Microchip Technology Inc. DS39637D-page 191

PIC18F2480/2580/4480/4580 18.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together, • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer Register and the SSPIF interrupt is set. (SSPBUF) During transmission, the SSPBUF is not double- • MSSP Shift Register (SSPSR) – Not directly buffered. A write to SSPBUF will write to both SSPBUF accessible and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 regis- ter is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 18-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty DS39637D-page 192 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 18-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over- flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins(2) bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only. © 2009 Microchip Technology Inc. DS39637D-page 193

PIC18F2480/2580/4480/4580 18.3.2 OPERATION the WCOL bit so that it can be determined if the follow- ing write(s) to the SSPBUF register completed When initializing the SPI, several options need to be successfully. specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). When the application software is expecting to receive These control bits allow the following to be specified: valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The • Master mode (SCK is the clock output) Buffer Full bit, BF (SSPSTAT<0>), indicates when • Slave mode (SCK is the clock input) SSPBUF has been loaded with the received data • Clock Polarity (Idle state of SCK) (transmission is complete). When the SSPBUF is read, • Data Input Sample Phase (middle or end of data the BF bit is cleared. This data may be irrelevant if the output time) SPI is only a transmitter. Generally, the MSSP interrupt • Clock Edge (output data on rising/falling edge of is used to determine when the transmission/reception SCK) has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, • Clock Rate (Master mode only) then software polling can be done to ensure that a write • Slave Select mode (Slave mode only) collision does not occur. Example18-1 shows the The MSSP consists of a Transmit/Receive Shift regis- loading of the SSPBUF (SSPSR) for data transmission. ter (SSPSR) and a Buffer register (SSPBUF). The The SSPSR is not directly readable or writable and can SSPSR shifts the data in and out of the device, MSb only be accessed by addressing the SSPBUF register. first. The SSPBUF holds the data that was written to the Additionally, the MSSP Status register (SSPSTAT) SSPSR until the received data is ready. Once the 8 bits indicates the various status conditions. of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF Note: The SSPBUF register cannot be used with (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are read-modify-write instructions such as set. This double-buffering of the received data BCF, BTFSC and COMF, etc. (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the Note: To avoid lost data in Master mode, a read of SSPBUF register during transmission/reception of data the SSPBUF must be performed to clear the will be ignored and the write collision detect bit, WCOL Buffer Full (BF) detect bit (SSPSTAT<0>) (SSPCON1<7>), will be set. User software must clear between each transmission. EXAMPLE 18-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS39637D-page 194 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.3.3 ENABLING SPI I/O 18.3.4 TYPICAL CONNECTION To enable the serial port, MSSP Enable bit, SSPEN Figure18-2 shows a typical connection between two (SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, reinitialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their pro- configures the SDI, SDO, SCK and SS pins as serial grammed clock edge and latched on the opposite edge port pins. For the pins to behave as the serial port func- of the clock. Both processors should be programmed to tion, some must have their data direction bits (in the the same Clock Polarity (CKP), then both controllers TRIS register) appropriately programmed as follows: would send and receive data at the same time. Whether the data is meaningful (or dummy data) • SDI is automatically controlled by the SPI module depends on the application software. This leads to • SDO must have TRISC<5> bit cleared three scenarios for data transmission: • SCK (Master mode) must have TRISC<3> bit • Master sends data – Slave sends dummy data cleared • Master sends data – Slave sends data • SCK (Slave mode) must have TRISC<3> bit set • Master sends dummy data – Slave sends data • SS must have TRISF<7> bit set Note: When the module is enabled and in Any serial port function that is not desired may be Master mode (CKE, SSPSTAT<6> = 1), a overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. small glitch of approximately half a TCY may be seen on the SCK pin. To resolve this, keep the SCK pin as an input while setting SPEN. Then, configure the SCK pin as an output (TRISC<3> = 0). FIGURE 18-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 © 2009 Microchip Technology Inc. DS39637D-page 195

PIC18F2480/2580/4480/4580 18.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, The master can initiate the data transfer at any time would give waveforms for SPI communication as because it controls the SCK. The master determines shown in Figure18-3, Figure18-5 and Figure18-6, when the slave (Processor 2, Figure18-2) is to where the MSB is transmitted first. In Master mode, the broadcast data by the software protocol. SPI clock rate (bit rate) is user-programmable to be one In Master mode, the data is transmitted/received as of the following: soon as the SSPBUF register is written to. If the SPI is • FOSC/4 (or TCY) only going to receive, the SDO output could be dis- abled (programmed as an input). The SSPSR register • FOSC/16 (or 4 • TCY) will continue to shift in the signal present on the SDI pin • FOSC/64 (or 16 • TCY) at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPBUF register as This allows a maximum data rate (at 40 MHz) of if a normal received byte (interrupts and status bits 10.00Mbps. appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. Figure18-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 18-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2↓ SSPBUF DS39637D-page 196 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.3.6 SLAVE MODE must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When In Slave mode, the data is transmitted and received as the SS pin goes high, the SDO pin is no longer driven the external clock pulses appear on SCK. When the even if in the middle of a transmitted byte and becomes last bit is latched, the SSPIF interrupt flag bit is set. a floating output. External pull-up/pull-down resistors Before enabling the module in SPI Slave mode, the may be desirable depending on the application. clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle Note 1: When the SPI is in Slave mode with SS pin state is determined by the CKP bit (SSPCON1<4>). control enabled (SSPCON<3:0>=0100), the SPI module will reset if the SS pin is set While in Slave mode, the external clock is supplied by to VDD. the external clock source on the SCK pin. This external clock must meet the minimum high and low times as 2: If the SPI is used in Slave mode with CKE specified in the electrical specifications. set, then the SS pin control must be enabled. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up When the SPI module resets, the bit counter is forced from Sleep. to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. 18.3.7 SLAVE SELECT To emulate two-wire communication, the SDO pin can SYNCHRONIZATION be connected to the SDI pin. When the SPI needs to The SS pin allows a Synchronous Slave mode. The operate as a receiver, the SDO pin can be configured SPI must be in Slave mode with SS pin control enabled as an input. This disables transmissions from the SDO. (SSPCON1<3:0> = 04h). The pin must not be driven The SDI can always be left as an input (SDI function) low for the SS pin to function as an input. The data latch since it cannot create a bus conflict. FIGURE 18-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2↓ SSPBUF © 2009 Microchip Technology Inc. DS39637D-page 197

PIC18F2480/2580/4480/4580 FIGURE 18-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 18-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF DS39637D-page 198 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.3.8 OPERATION IN POWER-MANAGED 18.3.9 EFFECTS OF A RESET MODES A Reset disables the MSSP module and terminates the In SPI Master mode, module clocks may be operating current transfer. at a different speed than when in full-power mode; in 18.3.10 BUS MODE COMPATIBILITY the case of the Sleep mode, all clocks are halted. Table18-1 shows the compatibility between the In most power-managed modes, a clock is provided to standard SPI modes and the states of the CKP and the peripherals. That clock should be from the primary CKE control bits. clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section3.7 TABLE 18-1: SPI BUS MODES “Clock Sources and Oscillator Switching” for additional information. Control Bits State Standard SPI Mode In most cases, the speed that the master clocks SPI Terminology CKP CKE data is not important; however, this should be evaluated for each system. 0, 0 0 1 If MSSP interrupts are enabled, they can wake the con- 0, 1 0 0 troller from Sleep mode, or one of the Idle modes, when 1, 0 1 1 the master completes sending data. If an exit from 1, 1 1 0 Sleep or Idle mode is not desired, MSSP interrupts should be disabled. There is also a SMP bit which controls when the data is sampled. If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/ Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. TABLE 18-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TRISA PORTA Data Direction Register 58 TRISC PORTC Data Direction Register 58 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 56 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 56 SSPSTAT SMP CKE D/A P S R/W UA BF 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in PIC18F2X80 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39637D-page 199

PIC18F2480/2580/4480/4580 18.4 I2C Mode 18.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPSR) – Not directly • Serial Clock (SCL) – RC3/SCK/SCL accessible • Serial Data (SDA) – RC4/SDI/SDA • MSSP Address Register (SSPADD) The user must configure these pins as inputs or outputs SSPCON1, SSPCON2 and SSPSTAT are the control through the TRISC<4:3> bits. and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and FIGURE 18-7: MSSP BLOCK DIAGRAM writable. The lower 6 bits of the SSPSTAT are read-only. (I2C™ MODE) The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or Internal out. SSPBUF is the buffer register to which data bytes Data Bus are written to or read from. Read Write SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode. SSPBUF reg When the MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Shift SCL Clock Generator reload value. In receive operations, SSPSR and SSPBUF together, SSPSR reg create a double-buffered receiver. When SSPSR SDA MSb LSb receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. Match Detect Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT reg) DS39637D-page 200 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 18-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (I2C mode only)(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Receive mode: 1 = Receive complete, SSPBUF is full 0 = Receive is not complete, SSPBUF is empty In Transmit mode: 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. © 2009 Microchip Technology Inc. DS39637D-page 201

PIC18F2480/2580/4480/4580 REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note 1: When enabled, the SDA and SCL pins must be properly configured as input or output. 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. DS39637D-page 202 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(2) 1 = Initiates Acknowledge sequence on SDA and SCL pins and transmits the ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(2) 1 = Initiates Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only(2) 1 = Initiates Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(2) In Master mode: 1 = Initiates Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: For bits, ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). © 2009 Microchip Technology Inc. DS39637D-page 203

PIC18F2480/2580/4480/4580 18.4.2 OPERATION 18.4.3.1 Addressing The MSSP module functions are enabled by setting the Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: clock (SCL) line. The value of register, SSPSR<7:1>, is compared to the value of the SSPADD register. The • I2C Master mode, clock = (FOSC/4) x (SSPADD+1) address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is Idle set (interrupt is generated, if enabled) on the Selection of any I2C mode with the SSPEN bit set, falling edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, In 10-Bit Addressing mode, two address bytes need to provided these pins are programmed to inputs by be received by the slave. The five Most Significant bits setting the appropriate TRISC bits. To ensure proper (MSbs) of the first address byte specify if this is a 10-bit operation of the module, pull-up resistors must be address. Bit, R/W (SSPSTAT<2>), must specify a write provided externally to the SCL and SDA pins. so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal 18.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two In Slave mode, the SCL and SDA pins must be config- MSbs of the address. The sequence of events for ured as inputs (TRISC<4:3> set). The MSSP module 10-bit addressing is as follows, with steps 7 through will override the input state with the output data when 9 for the slave-transmitter: required (slave-transmitter). 1. Receive first (high) byte of address (bits, SSPIF, The I2C Slave mode hardware will always generate an BF and UA (SSPSTAT<1>), are set). interrupt on an address match. Through the mode 2. Update the SSPADD register with second (low) select bits, the user can also choose to interrupt on byte of address (clears bit, UA, and releases the Start and Stop bits SCL line). When an address is matched, or the data transfer after 3. Read the SSPBUF register (clears bit, BF) and an address match is received, the hardware automati- clear flag bit, SSPIF. cally will generate the Acknowledge (ACK) pulse and 4. Receive second (low) byte of address (bits, load the SSPBUF register with the received value SSPIF, BF and UA, are set). currently in the SSPSR register. 5. Update the SSPADD register with the first (high) Any combination of the following conditions will cause byte of address. If match releases SCL line, this the MSSP module not to give this ACK pulse: will clear bit, UA. • The Buffer Full bit, BF (SSPSTAT<0>), was set 6. Read the SSPBUF register (clears bit BF) and before the transfer was received. clear flag bit, SSPIF. • The overflow bit, SSPOV (SSPCON<6>), was set 7. Receive Repeated Start condition. before the transfer was received. 8. Receive first (high) byte of address (bits, SSPIF and BF, are set). In this case, the SSPSR register value is not loaded into the SSPBUF, but bit, SSPIF (PIR1<3>), is set. The 9. Read the SSPBUF register (clears bit, BF) and BF bit is cleared by reading the SSPBUF register, while clear flag bit, SSPIF. bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. DS39637D-page 204 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.4.3.2 Reception 18.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section18.4.4 “Clock When the address byte overflow condition exists, then Stretching” for more details). By stretching the clock, the no Acknowledge (ACK) pulse is given. An overflow the master will be unable to assert another clock pulse condition is defined as either bit, BF (SSPSTAT<0>), is until the slave is done preparing the transmit data. The set, or bit, SSPOV (SSPCON1<6>), is set. transmit data must be loaded into the SSPBUF register An MSSP interrupt is generated for each data transfer which also loads the SSPSR register. Then, the RC3/ byte. Flag bit, SSPIF (PIR1<3>), must be cleared in SCK/SCL pin should be enabled by setting bit, CKP software. The SSPSTAT register is used to determine (SSPCON1<4>). The eight data bits are shifted out on the status of the byte. the falling edge of the SCL input. This ensures that the If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL SDA signal is valid during the SCL high time will be held low (clock stretch) following each data (Figure18-9). transfer. The clock must be released by setting bit, CKP The ACK pulse from the master-receiver is latched on (SSPCON<4>). See Section18.4.4 “Clock the rising edge of the ninth SCL input pulse. If the SDA Stretching” for more details. line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin, RC3/SCK/SCL, must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. © 2009 Microchip Technology Inc. DS39637D-page 205

PIC18F2480/2580/4480/4580 2 FIGURE 18-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D6D5D4 234 Cleared in softwarSSPBUF is read 7 D 1 K 9 = 0 AC W 8 R/ A1 7 2 )0 A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e ot r A6 2 s n e SDAA7 SCL1S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) CKP (SSPCON1<4>) (CKP do DS39637D-page 206 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 2 FIGURE 18-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o Data D1 7 Fr Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S D0 8 m S o 1 Fr D 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft ding CKP is set in software D7 1 SCL held lowwhile CPUresponds to SSPIF Clear by rea K C A 9 1 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g eivin A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < < T 1 A R T DA CL S SPIF (PI F (SSPS KP S S S B C © 2009 Microchip Technology Inc. DS39637D-page 207

PIC18F2480/2580/4480/4580 FIGURE 18-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. 0 D 8 1 D 7 e Byte 3D2 6 softwar a D 5 n eceive Dat D5D4 34 Cleared i R 6 D 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKSDA11110A9A8A7A6A5A4A3A2A1 SCL1234567891234567S SSPIF (PIR1<3>) Cleared in softwareCleared in software BF (SSPSTAT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag SSPOV (SSPCON1<6>) UA (SSPSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdatedKP (SSPCON1<4>) (CKP does not reset to ‘’ when SEN = )00 C DS39637D-page 208 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 2 FIGURE 18-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘1’ Receive First Byte of AddressTransmitting Data ByteR/W = 1 0ACK1111A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/e First Byte of Address 110A9A8 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv 11 12 AT<0>) AT<1>) ON1<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPST UA (SSPST CKP (SSPC © 2009 Microchip Technology Inc. DS39637D-page 209

PIC18F2480/2580/4480/4580 18.4.4 CLOCK STRETCHING 18.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7 and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. 7-Bit Slave Transmit mode implements clock stretch- The SEN bit (SSPCON2<0>) allows clock stretching to ing by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 18.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-Bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure18-9). ninth clock at the end of the ACK sequence if the BF Note1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge of automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be held low. The CKP bit being cleared to ‘0’ will assert cleared and clock stretching will not the SCL line low. The CKP bit must be set in the user’s occur. ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR 2: The CKP bit can be set in software regardless of the state of the BF bit. and read the contents of the SSPBUF before the master device can initiate another receive sequence. 18.4.4.4 Clock Stretching for 10-Bit Slave This will prevent buffer overruns from occurring (see Transmit Mode Figure18-13). In 10-Bit Slave Transmit mode, clock stretching is con- Note1: If the user reads the contents of the trolled during the first two address sequences by the SSPBUF before the falling edge of the state of the UA bit, just as it is in 10-Bit Slave Receive ninth clock, thus clearing the BF bit, the mode. The first two addresses are followed by a third CKP bit will not be cleared and clock address sequence, which contains the high-order bits stretching will not occur. of the 10-bit address and the R/W bit set to ‘1’. After 2: The CKP bit can be set in software the third address sequence is performed, the UA bit is regardless of the state of the BF bit. The not set, the module is now configured in Transmit user should be careful to clear the BF bit mode and clock stretching is controlled by the BF flag in the ISR before the next receive as in 7-Bit Slave Transmit mode (see Figure18-11). sequence in order to prevent an overflow condition. 18.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs, and if the user hasn’t cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39637D-page 210 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.4.4.5 Clock Synchronization and already asserted the SCL line. The SCL output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This When the CKP bit is cleared, the SCL output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, setting the CKP bit will not assert the minimum high time requirement for SCL (see SCL output low until the SCL output is already Figure18-12). sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 18-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX – 1 SCL Master device CKP asserts clock Master device deasserts clock WR SSPCON © 2009 Microchip Technology Inc. DS39637D-page 211

PIC18F2480/2580/4480/4580 2 FIGURE 18-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 2 A 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 >) A7 1 0>) ON1<6 1<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP (SSPCON DS39637D-page 212 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 18-14: I2C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lobecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s D 8 1 D 7 e Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPADD register beforethe falling edge of the ninth clock will haveno effect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of AddressW = 0 A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/ SDA11110A9A8 SCL12345678S SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) SSPBUF is written withcontents of SSPSR SSPOV (SSPCON1<6>) UA (SSPSTAT<1>) UA is set indicating thatthe SSPADD needs to beupdated KP (SSPCON1<4>) C © 2009 Microchip Technology Inc. DS39637D-page 213

PIC18F2480/2580/4480/4580 18.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), The addressing procedure for the I2C bus is such that the SSPIF interrupt flag bit is set. the first byte after the Start condition usually deter- mines which device will be the slave addressed by the When the interrupt is serviced, the source for the master. The exception is the general call address which interrupt can be checked by reading the contents of the can address all devices. When this address is used, all SSPBUF. The value can be used to determine if the devices should, in theory, respond with an address was device-specific or a general call address. Acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the half of the address is not necessary, the UA bit will not General Call Enable bit (GCEN) is enabled be set and the slave will begin receiving data after the (SSPCON2<7> set). Following a Start bit detect, 8 bits Acknowledge (Figure18-15). are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 18-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS39637D-page 214 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start Master mode of operation is supported by interrupt condition is complete. In this case, the generation on the detection of the Start and Stop SSPBUF will not be written to and the conditions. The Stop (P) and Start (S) bits are cleared WCOL bit will be set, indicating that a write from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is to the SSPBUF did not occur. set or the bus is Idle, with both the S and P bits clear. The following events will cause the MSSP Interrupt In Firmware Controlled Master mode, user code Flag bit, SSPIF, to be set (MSSP interrupt, if enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmitted 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 18-16: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e SSPSR Detce) MSb LSb L ur e Oo abl WCk s SCL Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT); Clock Arbitration Set SSPIF, BCLIF; Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) End of XMIT/RCV © 2009 Microchip Technology Inc. DS39637D-page 215

PIC18F2480/2580/4480/4580 18.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPCON2 register (SSPCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted con- 7. The user loads the SSPBUF with eight bits of tains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all 8 bits are logic ‘1’ Thus, the first byte transmitted is a 7-bit slave transmitted. address followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDA, while SCL outputs the slave device and writes its value into the serial clock. Serial data is received 8 bits at a time. After SSPCON2 register (SSPCON2<6>). each byte is received, an Acknowledge bit is transmit- ted. Start and Stop conditions indicate the beginning 10. The MSSP module generates an interrupt at the and end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode oper- 11. The user generates a Stop condition by setting ation is used to set the SCL clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPCON2<2>). Section18.4.7 “Baud Rate” for more details. 12. Interrupt is generated once the Stop condition is complete. DS39637D-page 216 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.4.7 BAUD RATE Once the given operation is complete (i.e., transmis- In I2C Master mode, the Baud Rate Generator (BRG) sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure18-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically Table18-3 demonstrates clock rates based on begin counting. The BRG counts down and stops until instruction cycles and the BRG value loaded into another reload has taken place. The BRG count is SSPADD. decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 18-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<6:0> SSPM<3:0> Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 18-3: I2C™ CLOCK RATE W/BRG FSCL FCY FCY*2 BRG Value (2 Rollovers of BRG) 10 MHz 20 MHz 19h 400 kHz 10 MHz 20 MHz 20h 312.5 kHz 10 MHz 20 MHz 64h 100 kHz 4 MHz 8 MHz 0Ah 400 kHz 4 MHz 8 MHz 0Dh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1 MHz 2 MHz 03h 333 kHz 1 MHz 2 MHz 0Ah 100 kHz © 2009 Microchip Technology Inc. DS39637D-page 217

PIC18F2480/2580/4480/4580 18.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure18-18). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 18-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS39637D-page 218 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.4.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDA and SCL pins are already sam- To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, Condition Enable bit, SEN (SSPCON2<0>). If the SDA the SCL line is sampled low before the and SCL pins are sampled high, the Baud Rate Gener- SDA line is driven low, a bus collision ator is reloaded with the contents of SSPADD<6:0> occurs, the Bus Collision Interrupt Flag, and starts its count. If SCL and SDA are both sampled BCLIF, is set, the Start condition is aborted high when the Baud Rate Generator times out (TBRG), and the I2C module is reset into its Idle the SDA pin is driven low. The action of the SDA being state. driven low while SCL is high is the Start condition and 18.4.8.1 WCOL Status Flag causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the If the user writes the SSPBUF when a Start sequence contents of SSPADD<6:0> and resumes its count. is in progress, the WCOL is set and the contents of the When the Baud Rate Generator times out (TBRG), the buffer are unchanged (the write doesn’t occur). SEN bit (SSPCON2<0>) will be automatically cleared Note: Because queueing of events is not by hardware, the Baud Rate Generator is suspended, allowed, writing to the lower 5 bits of leaving the SDA line held low and the Start condition is SSPCON2 is disabled until the Start complete. condition is complete. FIGURE 18-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S © 2009 Microchip Technology Inc. DS39637D-page 219

PIC18F2480/2580/4480/4580 18.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDA is sampled low when SCL goes the SCL pin is asserted low. When the SCL pin is sam- from low-to-high. pled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The • SCL goes low before SDA is SDA pin is released (brought high) for one Baud Rate asserted low. This may indicate that Generator count (TBRG). When the Baud Rate Genera- another master is attempting to tor times out, and if SDA is sampled high, the SCL pin transmit a data ‘1’. will be deasserted (brought high). When SCL is sam- Immediately following the SSPIF bit getting set, the user pled high, the Baud Rate Generator is reloaded with may write the SSPBUF with the 7-bit address in 7-bit the contents of SSPADD<6:0> and begins counting. mode, or the default first address in 10-bit mode. After SDA and SCL must be sampled high for one TBRG. the first eight bits are transmitted and an ACK is This action is then followed by assertion of the SDA pin received, the user may then transmit an additional eight (SDA = 0) for one TBRG while SCL is high. Following bits of address (10-bit mode) or eight bits of data (7-bit this, the RSEN bit (SSPCON2<1>) will be automatically mode). cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a 18.4.9.1 WCOL Status Flag Start condition is detected on the SDA and SCL pins, If the user writes the SSPBUF when a Repeated Start the S bit (SSPSTAT<3>) will be set. The SSPIF bit will sequence is in progress, the WCOL is set and the not be set until the Baud Rate Generator has timed out. contents of the buffer are unchanged (the write doesn’t occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. FIGURE 18-20: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG SDA 1st bit Falling edge of ninth clock, Write to SSPBUF occurs here end of XMIT TBRG SCL TBRG Sr = Repeated Start DS39637D-page 220 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.4.10 I2C MASTER MODE 18.4.10.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is Transmission of a data byte, a 7-bit address or the cleared when the slave has sent an Acknowledge other half of a 10-bit address is accomplished by simply (ACK=0) and is set when the slave does not Acknowl- writing a value to the SSPBUF register. This action will edge (ACK = 1). A slave sends an Acknowledge when set the Buffer Full flag bit, BF, and allow the Baud Rate it has recognized its address (including a general call), Generator to begin counting and start the next trans- or when the slave has properly received its data. mission. Each bit of address/data will be shifted out 18.4.11 I2C MASTER MODE RECEPTION onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter Master mode reception is enabled by programming the 106). SCL is held low for one Baud Rate Generator roll- Receive Enable bit, RCEN (SSPCON2<3>). over count (TBRG). Data should be valid before SCL is released high (see data setup time specification Note: The MSSP module must be in an Idle state parameter 107). When the SCL pin is released high, it before the RCEN bit is set or the RCEN bit is held that way for TBRG. The data on the SDA pin will be disregarded. must remain stable for that duration and some hold The Baud Rate Generator begins counting and on each time after the next falling edge of SCL. After the eighth rollover, the state of the SCL pin changes (high-to-low/ bit is shifted out (the falling edge of the eighth clock), low-to-high) and data is shifted into the SSPSR. After the BF flag is cleared and the master releases SDA. the falling edge of the eighth clock, the receive enable This allows the slave device being addressed to flag is automatically cleared, the contents of the respond with an ACK bit during the ninth bit time if an SSPSR are loaded into the SSPBUF, the BF flag bit is address match occurred, or if data was received set, the SSPIF flag bit is set and the Baud Rate properly. The status of ACK is written into the ACKDT Generator is suspended from counting, holding SCL bit on the falling edge of the ninth clock. If the master low. The MSSP is now in Idle state awaiting the next receives an Acknowledge, the Acknowledge status bit, command. When the buffer is read by the CPU, the BF ACKSTAT, is cleared. If not, the bit is set. After the ninth flag bit is automatically cleared. The user can then clock, the SSPIF bit is set and the master clock (Baud send an Acknowledge bit at the end of reception by Rate Generator) is suspended until the next data byte setting the Acknowledge sequence enable bit, ACKEN is loaded into the SSPBUF, leaving SCL low and SDA (SSPCON2<4>). unchanged (Figure18-21). 18.4.11.1 BF Status Flag After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all seven In receive operation, the BF bit is set when an address address bits and the R/W bit are completed. On the fall- or data byte is loaded into SSPBUF from SSPSR. It is ing edge of the eighth clock, the master will deassert cleared when the SSPBUF register is read. the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the 18.4.11.2 SSPOV Status Flag master will sample the SDA pin to see if the address In receive operation, the SSPOV bit is set when 8 bits was recognized by a slave. The status of the ACK bit is are received into the SSPSR and the BF flag bit is loaded into the ACKSTAT status bit (SSPCON2<6>). already set from a previous reception. Following the falling edge of the ninth clock transmis- sion of the address, the SSPIF flag is set, the BF flag is 18.4.11.3 WCOL Status Flag cleared and the Baud Rate Generator is turned off until If the user writes the SSPBUF when a receive is another write to the SSPBUF takes place, holding SCL already in progress (i.e., SSPSR is still shifting in a data low and allowing SDA to float. byte), the WCOL bit is set and the contents of the buffer 18.4.10.1 BF Status Flag are unchanged (the write doesn’t occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 18.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buf- fer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2009 Microchip Technology Inc. DS39637D-page 221

PIC18F2480/2580/4480/4580 FIGURE 18-21: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routinefrom MSSP interrupt SSPBUF is written in software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re W = 0 A W, 9 ware R/ A1 ss and R/ 78 d by hard ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared in software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS39637D-page 222 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 18-22: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from Masterer configured as a receiverSDA = ACKDT = SDA = ACKDT = 10ogramming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus masterACK is not sentterminatestransfer899678756512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of AcknowledgeSet SSPIF interruptSet SSPIF interruptsequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr ACK from Slave R/W = 1A1ACK 978 Write to SSPCON2<0>(SEN = ),1begin Start Condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 631245SCLS SSPIF Cleared in softwareSDA = , SCL = 01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN © 2009 Microchip Technology Inc. DS39637D-page 223

PIC18F2480/2580/4480/4580 18.4.12 ACKNOWLEDGE SEQUENCE 18.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge sequence enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/ (SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is sam- erate an Acknowledge, then the ACKDT bit should be pled low, the Baud Rate Generator is reloaded and cleared. If not, the user should set the ACKDT bit before counts down to 0. When the Baud Rate Generator starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is SCL pin is sampled high (clock arbitration), the Baud sampled high while SCL is high, the P bit Rate Generator counts for TBRG; the SCL pin is then (SSPSTAT<4>) is set. A TBRG later, the PEN bit is pulled low. Following this, the ACKEN bit is automatically cleared and the SSPIF bit is set (Figure18-24). cleared, the Baud Rate Generator is turned off and the 18.4.13.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure18-23). If the user writes the SSPBUF when a Stop sequence 18.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 18-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in Set SSPIF at the Cleared in software end of receive software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 18-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high, P bit (SSPSTAT<4>) is set Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. DS39637D-page 224 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.4.14 SLEEP OPERATION 18.4.17 MULTI-MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 18.4.15 EFFECT OF A RESET outputs a ‘1’ on SDA, by letting SDA float high, and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 18.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF, and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure18-25). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge monitored for arbitration to see if the signal level is the condition was in progress when the bus collision expected output level. This check is performed in occurred, the condition is aborted, the SDA and SCL hardware with the result placed in the BCLIF bit. lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user ser- The states where arbitration can be lost are: vices the bus collision Interrupt Service Routine, and if • Address Transfer the I2C bus is free, the user can resume communication • Data Transfer by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 18-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data doesn’t match what is driven while SCL = 0 by another source by the master; bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF © 2009 Microchip Technology Inc. DS39637D-page 225

PIC18F2480/2580/4480/4580 18.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure18-28). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL is sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure18-26). counts down to 0 and during this time, if the SCL pins b) SCL is sampled low before SDA is asserted low are sampled as ‘0’, a bus collision does not occur. At (Figure18-27). the end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus masters can assert a Start condition at the If the SDA pin is already low, or the SCL pin is already exact same time. Therefore, one master low, then all of the following occur: will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus • the BCLIF flag is set; and collision because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address (Figure18-26) following the Start condition. If the address The Start condition begins with the SDA and SCL pins is the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 18-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 MSSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS39637D-page 226 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 18-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 18-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software © 2009 Microchip Technology Inc. DS39637D-page 227

PIC18F2480/2580/4480/4580 18.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, see Figure18-29). If SDA is sampled high, the BRG is During a Repeated Start condition, a bus collision reloaded and begins counting. If SDA goes from high-to- occurs if: low before the BRG times out, no bus collision occurs a) A low level is sampled on SDA when SCL goes because no two masters can assert SDA at exactly the from a low level to a high level. same time. b) SCL goes low before SDA is asserted low, indi- If SCL goes from high-to-low before the BRG times out, cating that another master is attempting to and SDA has not already been asserted, a bus collision transmit a data ‘1’. occurs. In this case, another master is attempting to When the user deasserts SDA and the pin is allowed to transmit a data ‘1’ during the Repeated Start condition, float high, the BRG is loaded with SSPADD<6:0> and see Figure18-30. counts down to 0. The SCL pin is then deasserted and If, at the end of the BRG time-out, both SCL and SDA when sampled high, the SDA pin is sampled. are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 18-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 18-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF DS39637D-page 228 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 18.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure18-31). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure18-32). FIGURE 18-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 18-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’ © 2009 Microchip Technology Inc. DS39637D-page 229

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 230 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 19.0 ENHANCED UNIVERSAL The pins of the Enhanced USART are multiplexed with SYNCHRONOUS RECEIVER PORTC. In order to configure RC6/TX/CK and RC7/RX/DT as a USART: TRANSMITTER (EUSART) • bit, SPEN (RCSTA<7>), must be set (= 1) The Universal Synchronous Asynchronous Receiver • bit, TRISC<7>, must be set (= 1) Transmitter (USART) module is one of the two serial • bit, TRISC<6>, must be cleared (= 0) for I/O modules. (USART is also known as a Serial Asynchronous and Synchronous Master modes, Communications Interface or SCI.) The USART can be or set (= 1) for Synchronous Slave mode configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as Note: The EUSART control will automatically CRT terminals and personal computers. It can also be reconfigure the pin from input to output as needed. configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D The operation of the Enhanced USART module is or D/A integrated circuits, serial EEPROMs and so on. controlled through three registers: The EUSART module implements additional features, • Transmit Status and Control (TXSTA) including automatic baud rate detection and calibra- • Receive Status and Control (RCSTA) tion, automatic wake-up on Sync Break reception and • Baud Rate Control (BAUDCON) 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus These are detailed on the following pages in (LIN/J2602 bus) systems. Register19-1, Register19-2 and Register19-3, respectively. The EUSART can be configured in the following modes: • Asynchronous (full-duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission • Synchronous – Master (half-duplex) with selectable clock polarity • Synchronous – Slave (half-duplex) with selectable clock polarity © 2009 Microchip Technology Inc. DS39637D-page 231

PIC18F2480/2580/4480/4580 REGISTER 19-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39637D-page 232 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 19-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be an address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. DS39637D-page 233

PIC18F2480/2580/4480/4580 REGISTER 19-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39637D-page 234 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 19.1 Baud Rate Generator (BRG) Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This The BRG is a dedicated, 8-bit or 16-bit generator that ensures the BRG does not wait for a timer overflow supports both the Asynchronous and Synchronous before outputting the new baud rate. modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) Note: BRG value of ‘0’ is not supported. selects 16-bit mode. 19.1.1 OPERATION IN POWER-MANAGED The SPBRGH:SPBRG register pair controls the period MODES of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also The device clock is used to generate the desired baud control the baud rate. In Synchronous mode, BRGH is rate. When one of the power-managed modes is ignored. Table19-1 shows the formula for computation entered, the new clock source may be operating at a of the baud rate for different EUSART modes which different frequency. This may require an adjustment to only apply in Master mode (internally generated clock). the value in the SPBRG register pair. Given the desired baud rate and FOSC, the nearest 19.1.2 SAMPLING integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table19-1. From this, The data on the RX pin is sampled three times by a the error in baud rate can be determined. An example majority detect circuit to determine if a high or a low calculation is shown in Example19-1. Typical baud level is present at the RX pin when SYNC is clear or rates and error values for the various Asynchronous when BRG16 and BRGH are both not set. The data on modes are shown in Table19-2. It may be the RX pin is sampled once when SYNC is set or when advantageous to use the high baud rate (BRGH = 1) or BRGH16 and BRGH are both set. the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. TABLE 19-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair © 2009 Microchip Technology Inc. DS39637D-page 235

PIC18F2480/2580/4480/4580 EXAMPLE 19-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 19-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39637D-page 236 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — © 2009 Microchip Technology Inc. DS39637D-page 237

PIC18F2480/2580/4480/4580 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39637D-page 238 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 19.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure19-1) begins whenever a Start bit is received Some combinations of oscillator and the ABDEN bit is set. The calculation is frequency and EUSART baud rates are self-averaging. not possible due to bit error rates. Overall system timing and communication baud In the Auto-Baud Rate Detect (ABD) mode, the clock to rates must be taken into consideration the BRG is reversed. Rather than the BRG clocking the when using the Auto-Baud Rate incoming RX signal, the RX signal is timing the BRG. In Detection feature. ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial 3: To maximize baud rate range, it is recom- byte stream. mended to set the BRG16 bit if the auto-baud feature is used. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detection must receive a byte with the value 55h TABLE 19-4: BRG COUNTER (ASCII “U”, which is also the LIN/J2602 bus Sync CLOCK RATES character) in order to calculate the proper bit rate. The BRG16 BRGH BRG Counter Clock measurement is taken over both a low and a high bit time in order to minimize any effects caused by asym- 0 0 FOSC/512 metry of the incoming signal. After a Start bit, the SPBRG begins counting up, using the preselected 0 1 FOSC/128 clock source on the first rising edge of RX. After eight 1 0 FOSC/128 bits on the RX pin or the fifth rising edge, an accumu- 1 1 FOSC/32 lated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once the 5th edge is 19.1.3.1 ABD and EUSART Transmission seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. Since the BRG clock is reversed during ABD acquisi- tion, the EUSART transmitter cannot be used during If a rollover of the BRG occurs (an overflow from FFFFh ABD. This means that whenever the ABDEN bit is set, to 0000h), the event is trapped by the ABDOVF status TXREG cannot be written to. Users should also ensure bit (BAUDCON<7>). It is set in hardware by BRG roll- that ABDEN does not become set during a transmit overs and can be set or cleared by the user in software. sequence. Failing to do this may result in unpredictable ABD mode remains active after rollover events and the EUSART operation. ABDEN bit remains set (Figure19-2). While calibrating the baud rate period, the BRG regis- ters are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock can be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG1 and SPBRGH1 as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table19-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. © 2009 Microchip Technology Inc. DS39637D-page 239

PIC18F2480/2580/4480/4580 FIGURE 19-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX Pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 19-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX Pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39637D-page 240 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 19.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty The Asynchronous mode of operation is selected by and the TXIF flag bit (PIR1<4>) is set. This interrupt can clearing the SYNC bit (TXSTA<4>). In this mode, the be enabled or disabled by setting or clearing the interrupt EUSART uses standard Non-Return-to-Zero (NRZ) enable bit, TXIE (PIE1<4>). TXIF will be set regardless of format (one Start bit, eight or nine data bits and one Stop the state of TXIE; it cannot be cleared in software. TXIF bit). The most common data format is 8 bits. An on-chip is also not cleared immediately upon loading TXREG, but dedicated 8-bit/16-bit Baud Rate Generator can be used becomes valid in the second instruction cycle following to derive standard baud rate frequencies from the the load instruction. Polling TXIF immediately following a oscillator. load of TXREG will return invalid results. The EUSART transmits and receives the LSb first. The While TXIF indicates the status of the TXREG register, EUSART’s transmitter and receiver are functionally another bit, TRMT (TXSTA<1>), shows the status of independent but use the same data format and baud the TSR register. TRMT is a read-only bit which is set rate. The Baud Rate Generator produces a clock, either when the TSR register is empty. No interrupt logic is x16 or x64 of the bit shift rate depending on the BRGH tied to this bit so the user has to poll this bit in order to and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity determine if the TSR register is empty. is not supported by the hardware, but can be implemented in software and stored as the 9th data bit. Note1: The TSR register is not mapped in data When operating in Asynchronous mode, the EUSART memory so it is not available to the user. module consists of the following important elements: 2: Flag bit, TXIF, is set when enable bit, In Asynchronous mode, clock polarity is selected with TXEN, is set. the TXCKP bit (BAUDCON<4>). Setting TXCKP sets To set up an Asynchronous Transmission: the Idle state on CK as high, while clearing the bit sets 1. Initialize the SPBRGH:SPBRG registers for the the Idle state as low. Data polarity is selected with the appropriate baud rate. Set or clear the BRGH RXDTP bit (BAUDCON<5>). and BRG16 bits, as required, to achieve the Setting RXDTP inverts data on RX, while clearing the desired baud rate. bit has no affect on received data. 2. Enable the asynchronous serial port by clearing • Baud Rate Generator bit, SYNC, and setting bit, SPEN. • Sampling Circuit 3. If interrupts are desired, set enable bit, TXIE. • Asynchronous Transmitter 4. If 9-bit transmission is desired, set transmit bit, • Asynchronous Receiver TX9. Can be used as address/data bit. • Auto-Wake-up on Sync Break Character 5. Enable the transmission by setting bit, TXEN, • 12-Bit Break Character Transmit which will also set bit, TXIF. • Auto-Baud Rate Detection 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. 19.2.1 EUSART ASYNCHRONOUS 7. Load data to the TXREG register (starts TRANSMITTER transmission). The EUSART transmitter block diagram is shown in 8. If using interrupts, ensure that the GIE and PEIE bits Figure19-3. The heart of the transmitter is the Transmit in the INTCON register (INTCON<7:6>) are set. (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). © 2009 Microchip Technology Inc. DS39637D-page 241

PIC18F2480/2580/4480/4580 FIGURE 19-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register TX Pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGH SPBRG TX9 Baud Rate Generator TX9D FIGURE 19-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 19-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS39637D-page 242 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 TXREG EUSART Transmit Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: Reserved in PIC18F2X80 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39637D-page 243

PIC18F2480/2580/4480/4580 19.2.2 EUSART ASYNCHRONOUS 19.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure19-6. This mode would typically be used in RS-485 systems. The data is received on the RX pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGH:SPBRG registers for the whereas the main receive serial shifter operates at the appropriate baud rate. Set or clear the BRGH bit rate or at FOSC. This mode would typically be used and BRG16 bits, as required, to achieve the in RS-232 systems. desired baud rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRGH:SPBRG registers for the the SYNC bit and setting the SPEN bit. appropriate baud rate. Set or clear the BRGH 3. If interrupts are required, set the RCEN bit and and BRG16 bits, as required, to achieve the select the desired priority level with the RCIP bit. desired baud rate. 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit, SYNC, and setting bit, SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit, RCIE. 7. The RCIF bit will be set when reception is 4. If 9-bit reception is desired, set bit, RX9. complete. The interrupt will be Acknowledged if 5. Enable the reception by setting bit, CREN. the RCIE and GIE bits are set. 6. Flag bit, RCIF, will be set when reception is com- 8. Read the RCSTA register to determine if any plete and an interrupt will be generated if enable error occurred during reception, as well as read bit, RCIE, was set. bit 9 of data (if applicable). 7. Read the RCSTA register to get the 9th bit (if 9. Read RCREG to determine if the device is being enabled) and determine if any error occurred addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREG register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 19-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG ÷ o6r4 MSb RSR Register LSb ÷ 16 or Stop (8) 7 • • • 1 0 Start Baud Rate Generator ÷ 4 RX9 Pin Buffer Data and Control Recovery RX RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE DS39637D-page 244 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 19-7: ASYNCHRONOUS RECEPTION RX (pin) Sbtiatrt bit 0 bit 1 bit 7/8 Stop Sbtaitrt bit 0 bit 7/8 Stop Sbtaitrt bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (overrun) bit to be set. TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 RCREG EUSART Receive Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register, High Byte 57 SPBRG EUSART Baud Rate Generator Register, Low Byte 57 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Reserved in PIC18F2X80 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39637D-page 245

PIC18F2480/2580/4480/4580 19.2.4 AUTO-WAKE-UP ON SYNC BREAK End-of-Character (EOC) and cause data or framing CHARACTER errors. To work properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h During Sleep mode, all clocks to the EUSART are (8bits) for standard RS-232 devices or 000h (12 bits) for suspended. Because of this, the Baud Rate Generator LIN/J2602 bus. is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the con- Oscillator start-up time must also be considered, troller to wake-up due to activity on the RX/DT line, especially in applications using oscillators with longer while the EUSART is operating in Asynchronous mode. start-up intervals (i.e., XT or HS mode). The Sync Break (or Wake-up Signal) character must be of suffi- The auto-wake-up feature is enabled by setting the cient length and be followed by a sufficient interval to WUE bit (BAUDCON<1>). Once set, the typical receive allow enough time for the selected oscillator to start sequence on RX/DT is disabled and the EUSART and provide proper initialization of the EUSART. remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event con- 19.2.4.2 Special Considerations Using sists of a high-to-low transition on the RX/DT line. (This the WUE Bit coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol.) The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of Following a wake-up event, the module generates an received data. As noted, setting the WUE bit places the RCIF interrupt. The interrupt is generated synchro- EUSART in an Idle mode. The wake-up event causes nously to the Q clocks in normal operating modes a receive interrupt by setting the RCIF bit. The WUE bit (Figure19-8) and asynchronously, if the device is in is cleared after this when a rising edge is seen on Sleep mode (Figure19-9). The interrupt condition is RX/DT. The interrupt condition is then cleared by read- cleared by reading the RCREG register. ing the RCREG register. Ordinarily, the data in RCREG The WUE bit is automatically cleared once a low-to-high will be dummy data and should be discarded. transition is observed on the RX line following the The fact that the WUE bit has been cleared (or is still wake-up event. At this point, the EUSART module is in set) and the RCIF flag is set should not be used as an Idle mode and returns to normal operation. This signals indicator of the integrity of the data in RCREG. Users to the user that the Sync Break event is over. should consider implementing a parallel method in firmware to verify received data integrity. 19.2.4.1 Special Considerations Using To assure that no actual data is lost, check the RCIDL Auto-Wake-up bit to verify that a receive operation is not in process. If Since auto-wake-up functions by sensing rising edge a receive operation is not occurring, the WUE bit may transitions on RX/DT, information with any state then be set just prior to entering the Sleep mode. changes before the Stop bit may signal a false FIGURE 19-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RX/DT Line RCIF Cleared due to user read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 19-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RX/DT Line Note 1 RCIF Cleared due to user read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS39637D-page 246 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 19.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The Enhanced EUSART module has the capability of 2. Set the TXEN and SENDB bits to set up the sending the special Break character sequences that Break character. are required by the LIN/J2602 bus standard. The Break 3. Load the TXREG with a dummy character to character transmit consists of a Start bit, followed by initiate transmission (the value is ignored). twelve ‘0’ bits and a Stop bit. The Frame Break charac- 4. Write ‘55h’ to TXREG to load the Sync character ter is sent whenever the SENDB and TXEN bits into the transmit FIFO buffer. (TXSTA<3> and TXSTA<5>) are set while the Transmit 5. After the Break has been sent, the SENDB bit is Shift register is loaded with data. Note that the value of reset by hardware. The Sync character now data written to TXREG will be ignored and all ‘0’s will transmits in the preconfigured mode. be transmitted. When the TXREG becomes empty, as indicated by the The SENDB bit is automatically reset by hardware after TXIF, the next data byte can be written to TXREG. the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte 19.2.6 RECEIVING A BREAK CHARACTER following the Break character (typically, the Sync The Enhanced USART module can receive a Break character in the LIN/J2602 specification). character in two ways. Note that the data value written to the TXREG for the The first method forces configuration of the baud rate Break character is ignored. The write simply serves the at a frequency of 9/13 the typical speed. This allows for purpose of initiating the proper sequence. the Stop bit transition to be at the correct sampling loca- The TRMT bit indicates when the transmit operation is tion (13 bits for Break versus Start bit and 8 data bits for active or Idle, just as it does during normal transmis- typical data). sion. See Figure19-10 for the timing of the Break The second method uses the auto-wake-up feature character sequence. described in Section19.2.4 “Auto-Wake-up on Sync 19.2.5.1 Break and Sync Transmit Sequence Break Character”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, The following sequence will send a message frame cause an RCIF interrupt and receive the next data byte header made up of a Break, followed by an Auto-Baud followed by another interrupt. Sync byte. This sequence is typical of a LIN/J2602 bus Note that following a Break character, the user will master. typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. FIGURE 19-10: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) © 2009 Microchip Technology Inc. DS39637D-page 247

PIC18F2480/2580/4480/4580 19.3 EUSART Synchronous Once the TXREG register transfers the data to the TSR Master Mode register (occurs in one TCYCLE), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can The Master mode indicates that the processor trans- be enabled or disabled by setting or clearing the inter- mits the master clock on the CK line. The Synchronous rupt enable bit, TXIE (PIE1<4>). TXIF is set regardless Master mode is entered by setting the CSRC bit of the state of enable bit TXIE; it cannot be cleared in (TXSTA<7>). In this mode, the data is transmitted in a software. It will reset only when new data is loaded into half-duplex manner (i.e., transmission and reception do the TXREG register. not occur at the same time). When transmitting data, While flag bit, TXIF, indicates the status of the TXREG the reception is inhibited and vice versa. Synchronous register, another bit, TRMT (TXSTA<1>), shows the mode is entered by setting bit, SYNC (TXSTA<4>). In status of the TSR register. TRMT is a read-only bit which addition, enable bit, SPEN (RCSTA<7>), is set in order is set when the TSR is empty. No interrupt logic is tied to to configure the TX and RX pins to CK (clock) and DT this bit so the user has to poll this bit in order to (data) lines, respectively. determine if the TSR register is empty. The TSR is not The Master mode indicates that the processor trans- mapped in data memory so it is not available to the user. mits the master clock on the CK line. Clock polarity is To set up a Synchronous Master Transmission: selected with the SCKP bit (BAUDCON<4>). Setting SCKP sets the Idle state on CK as high, while clearing 1. Initialize the SPBRGH:SPBRG registers for the the bit sets the Idle state as low. This option is provided appropriate baud rate. Set or clear the BRG16 to support Microwire devices with this module. bit, as required, to achieve the desired baud rate. 19.3.1 EUSART SYNCHRONOUS MASTER 2. Enable the synchronous master serial port by TRANSMISSION setting bits, SYNC, SPEN and CSRC. The EUSART transmitter block diagram is shown in 3. If interrupts are desired, set enable bit, TXIE. Figure19-3. The heart of the transmitter is the Transmit 4. If 9-bit transmission is desired, set bit, TX9. (Serial) Shift Register (TSR). The Shift register obtains 5. Enable the transmission by setting bit, TXEN. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREG. The TXREG register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the last 7. Start transmission by loading data to the TXREG bit has been transmitted from the previous load. As register. soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 19-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. DS39637D-page 248 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 19-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 TXREG EUSART Transmit Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register, High Byte 57 SPBRG EUSART Baud Rate Generator Register, Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: Reserved in PIC18F2X80 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39637D-page 249

PIC18F2480/2580/4480/4580 19.3.2 EUSART SYNCHRONOUS 3. Ensure bits, CREN and SREN, are clear. MASTER RECEPTION 4. If interrupts are desired, set enable bit, RCIE. 5. If 9-bit reception is desired, set bit, RX9. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit, SREN. SREN (RCSTA<5>), or the Continuous Receive For continuous reception, set bit, CREN. Enable bit, CREN (RCSTA<4>). Data is sampled on the 7. Interrupt flag bit, RCIF, will be set when RX pin on the falling edge of the clock. reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is 8. Read the RCSTA register to get the 9th bit (if continuous until CREN is cleared. If both bits are set, enabled) and determine if any error occurred then CREN takes precedence. during reception. To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the RCREG register. 1. Initialize the SPBRGH:SPBRG registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRG16 bit, CREN. bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE 2. Enable the synchronous master serial port by bits in the INTCON register (INTCON<7:6>) are setting bits, SYNC, SPEN and CSRC. set. FIGURE 19-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC7/TX/CK pin (SCKP = 0) RC7/TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0. TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 RCREG EUSART Receive Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: Reserved in PIC18F2X80 devices; always maintain these bits clear. DS39637D-page 250 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 19.4 EUSART Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit CSRC. CSRC (TXSTA<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CK pin (instead of being supplied 3. If interrupts are desired, set enable bit, TXIE. internally in Master mode). This allows the device to 4. If 9-bit transmission is desired, set bit, TX9. transfer or receive data while in any low-power mode. 5. Enable the transmission by setting enable bit, TXEN. 19.4.1 EUSART SYNCHRONOUS 6. If 9-bit transmission is selected, the ninth bit SLAVE TRANSMIT should be loaded in bit, TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the modes are identical, except in the case of the Sleep TXREGx register. mode. 8. If using interrupts, ensure that the GIE and PEIE If two words are written to the TXREG and then the bits in the INTCON register (INTCON<7:6>) are SLEEP instruction is executed, the following will occur: set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in the TXREG register. c) Flag bit, TXIF, will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. e) If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 TXREG EUSART Transmit Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: Reserved in PIC18F2X80 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. DS39637D-page 251

PIC18F2480/2580/4480/4580 19.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCIE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCIF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit, RCIE, was set. RCREG register. If the RCIE enable bit is set, the inter- 6. Read the RCSTA register to get the 9th bit (if rupt generated will wake the chip from the low-power enabled) and determine if any error occurred mode. If the global interrupt is enabled, the program will during reception. branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 RCREG EUSART Receive Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: Reserved in PIC18F2X80 devices; always maintain these bits clear. DS39637D-page 252 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 20.0 10-BIT ANALOG-TO-DIGITAL The module has five registers: CONVERTER (A/D) MODULE • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) The Analog-to-Digital (A/D) Converter module has • A/D Control Register 0 (ADCON0) 8inputs for the PIC18F2X80 devices and 11 for the PIC18F4X80 devices. This module allows conversion • A/D Control Register 1 (ADCON1) of an analog input signal to a corresponding 10-bit • A/D Control Register 2 (ADCON2) digital number. The ADCON0 register, shown in Register20-1, controls the operation of the A/D module. The ADCON1 register, shown in Register20-2, configures the functions of the port pins. The ADCON2 register, shown in Register20-3, configures the A/D clock source, programmed acquisition time and justification. REGISTER 20-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Unused 1100 = Unused 1101 = Unused 1110 = Unused 1111 = Unused bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Note 1: These channels are not implemented on PIC18F2X80 devices. 2: Performing a conversion on unimplemented channels will return full-scale measurements. © 2009 Microchip Technology Inc. DS39637D-page 253

PIC18F2480/2580/4480/4580 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W-q(1) R/W-q(1) R/W-q(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits: PCFG<3:0> N10 N9 N8 (2)N7 (2)N6 (2)N5 N4 N3 N2 N1 N0 A A A A A A A A A A A 0000(1) A A A A A A A A A A A 0001 A A A A A A A A A A A 0010 A A A A A A A A A A A 0011 A A A A A A A A A A A 0100 A A A A A A A A A A A 0101 D A A A A A A A A A A 0110 D D A A A A A A A A A 0111(1) D D D A A A A A A A A 1000 D D D D A A A A A A A 1001 D D D D D A A A A A A 1010 D D D D D D A A A A A 1011 D D D D D D D A A A A 1100 D D D D D D D D A A A 1101 D D D D D D D D D A A 1110 D D D D D D D D D D A 1111 D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: The POR value of the PCFG bits depends on the value of the PBADEN bit in Configuration Register 3H. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. 2: AN5 through AN7 are available only on PIC18F4X80 devices. DS39637D-page 254 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2009 Microchip Technology Inc. DS39637D-page 255

PIC18F2480/2580/4480/4580 The analog reference voltage is software-selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (AVDD and AVSS), or the voltage level on the conversion in progress is aborted. RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D Converter can be The A/D Converter has a unique feature of being able configured as an analog input, or as a digital I/O. The to operate while the device is in Sleep mode. To oper- ADRESH and ADRESL registers contain the result of ate in Sleep, the A/D conversion clock must be derived the A/D conversion. When the A/D conversion is com- from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is The output of the sample and hold is the input into the cleared and A/D Interrupt Flag bit, ADIF, is set. The converter, which generates the result via successive block diagram of the A/D module is shown in approximation. Figure20-1. FIGURE 20-1: A/D BLOCK DIAGRAM CHS<3:0> 1010 AN10 1001 AN9 1000 AN8 0111 AN7(1) 0110 AN6(1) 0101 AN5(1) 0100 AN4 VAIN 10-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG<1:0> AN1 AVDD(2) 0000 AN0 X0 VREF+ X1 Reference 1X Voltage VREF- 0X AVSS(2) Note 1: Channels, AN5 through AN7, are not available on PIC18F2X80 devices. 2: I/O pins have diode protection to VDD and VSS. DS39637D-page 256 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 The value in the ADRESH/ADRESL registers is not 2. Configure A/D interrupt (if desired): modified for a Power-on Reset. The ADRESH/ADRESL • Clear ADIF bit registers will contain unknown data after a Power-on • Set ADIE bit Reset. • Set GIE bit After the A/D module has been configured as desired, 3. Wait the required acquisition time (if required). the selected channel must be acquired before the con- 4. Start conversion: version is started. The analog input channels must have their corresponding TRIS bits selected as an • Set GO/DONE bit (ADCON0 register) input. To determine acquisition time, see Section20.1 5. Wait for A/D conversion to complete, by either: “A/D Acquisition Requirements”. After this acquisi- • Polling for the GO/DONE bit to be cleared tion time has elapsed, the A/D conversion can be OR started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual • Waiting for the A/D interrupt start of the conversion. 6. Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. The following steps should be followed to perform an A/D conversion: 7. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is 1. Configure the A/D module: defined as TAD. A minimum wait of 2 TAD is • Configure analog pins, voltage reference and required before next acquisition starts. digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D acquisition time (ADCON2) • Select A/D conversion clock (ADCON2) • Turn on A/D module (ADCON0) FIGURE 20-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L E1A0K0A nGAE CHOLD = 120 pF VSS Legend: CPIN = Input Capacitance 6V VT = Threshold Voltage 5V ILEAKAGE = Leakage Current at the pin due to VDD 4V various junctions 3V RIC = Interconnect Resistance 2V SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance 5 6 7 8 9 10 11 Sampling Switch (kΩ) © 2009 Microchip Technology Inc. DS39637D-page 257

PIC18F2480/2580/4480/4580 20.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation20-1 may be used. This equation assumes For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure20-2. The Example20-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 120 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5 kΩ. After the analog input channel is VDD = 5V → Rss = 7 kΩ selected (changed), the channel must be sampled for Temperature = 50°C (system max.) at least the minimum acquisition time before starting a VHOLD = 0V @ time = 0 conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 20-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 20-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 20-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 5 μs TCOFF = (Temp – 25°C)(0.05 μs/°C) (50°C – 25°C)(0.05 μs/°C) 1.25 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) μs -(120 pF) (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) μs 9.61 μs TACQ = 5 μs + 1.25 μs + 9.61 μs 12.86 μs DS39637D-page 258 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 20.2 Selecting and Configuring 20.3 Selecting the A/D Conversion Automatic Acquisition Time Clock The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The acquisition time that occurs each time the GO/DONE A/D conversion requires 11 TAD per 10-bit conversion. bit is set. The source of the A/D conversion clock is software-selectable. There are seven possible options When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensur- for TAD: ing the required acquisition time has passed between • 2 TOSC selecting the desired input channel and setting the • 4 TOSC GO/DONE bit. This occurs when the ACQT<2:0> bits • 8 TOSC (ADCON2<5:3>) remain in their Reset state (‘000’) and • 16 TOSC is compatible with devices that do not offer programmable acquisition times. • 32 TOSC • 64 TOSC If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. • Internal RC Oscillator When the GO/DONE bit is set, the A/D module For correct A/D conversions, the A/D conversion clock continues to sample the input for the selected acquisition (TAD) must be as short as possible, but greater than the time, then automatically begins a conversion. Since the minimum TAD (approximately 2μs, see parameter 130 acquisition time is programmed, there may be no need for more information). to wait for an acquisition time between selecting a Table20-1 shows the resultant TAD times derived from channel and setting the GO/DONE bit. the device operating frequencies and the A/D clock In either case, when the conversion is completed, the source selected. GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18F2X80/4X80 PIC18LF2X80/4X80(4) 2 TOSC 000 2.86 MHz 1.43 kHz 4 TOSC 100 5.71 MHz 2.86 MHz 8 TOSC 001 11.43 MHz 5.72 MHz 16 TOSC 101 22.86 MHz 11.43 MHz 32 TOSC 010 40.0 MHz 22.86 MHz 64 TOSC 110 40.0 MHz 22.86 MHz RC(3) x11 1.00 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 1.2 ms. 2: The RC source has a typical TAD time of 2.5 ms. 3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power (PIC18LFXXXX) devices only. © 2009 Microchip Technology Inc. DS39637D-page 259

PIC18F2480/2580/4480/4580 20.4 Operation in Power-Managed 20.5 Configuring Analog Port Pins Modes The ADCON1, TRISA, TRISB and TRISE registers all The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as conversion clock is determined in part, by the clock analog inputs must have their corresponding TRIS bits source and frequency while in a power-managed set (input). If the TRIS bit is cleared (output), the digital mode. output level (VOH or VOL) will be converted. If the A/D is expected to operate while the device is in The A/D operation is independent of the state of the a power-managed mode, the ACQT<2:0> and CHS<3:0> bits and the TRIS bits. ADCS<2:0> bits in ADCON2 should be updated in Note1: When reading the PORT register, all pins accordance with the clock source to be used in that configured as analog input channels will mode. After entering the mode, an A/D acquisition or read as cleared (a low level). Pins config- conversion may be started. Once started, the device ured as digital inputs will convert an should continue to be clocked by the same clock analog input. Analog levels on a digitally source until the conversion has been completed. configured input will be accurately If desired, the device may be placed into the converted. corresponding Idle mode during the conversion. If the 2: Analog levels on any pin defined as a device clock frequency is less than 1MHz, the A/D RC digital input may cause the digital input clock source should be selected. buffer to consume current out of the Operation in the Sleep mode requires the A/D FRC device’s specification limits. clock to be selected. If bits, ACQT<2:0>, are set to 3: The PBADEN bit in Configuration ‘000’ and a conversion is started, the conversion will be Register3H configures PORTB pins to delayed one instruction cycle to allow execution of the reset as analog or digital pins by control- SLEEP instruction and entry to Sleep mode. The IDLEN ling how the PCFG bits in ADCON1 are bit (OSCCON<7>) must have already been cleared reset. prior to starting the conversion. DS39637D-page 260 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 20.6 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register Figure20-3 shows the operation of the A/D Converter pair will NOT be updated with the partially completed after the GO/DONE bit has been set and the A/D conversion sample. This means the ACQT<2:0> bits are cleared. A conversion is started ADRESH:ADRESL registers will continue to contain after the following instruction to allow entry into Sleep the value of the last completed conversion (or the last mode before the conversion begins. value written to the ADRESH:ADRESL registers). Figure20-4 shows the operation of the A/D Converter After the A/D conversion is completed or aborted, a after the GO/DONE bit has been set and the 2TAD wait is required before the next acquisition can ACQT<2:0> bits are set to ‘010’ and selecting a 4 TAD be started. After this wait, acquisition on the selected acquisition time before the conversion starts. channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 20-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 20-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. © 2009 Microchip Technology Inc. DS39637D-page 261

PIC18F2480/2580/4480/4580 20.7 Use of the CCP1 Trigger software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input chan- An A/D conversion can be started by the “Special Event nel must be selected and the minimum acquisition Trigger” of the ECCP1 module. This requires that the period is either timed by the user, or an appropriate ECCP1M<3:0> bits (ECCP1CON<3:0>) be pro- TACQ time selected before the “Special Event Trigger” grammed as ‘1011’ and that the A/D module is enabled sets the GO/DONE bit (starts a conversion). (ADON bit is set). When the trigger occurs, the If the A/D module is not enabled (ADON is cleared), the GO/DONE bit will be set, starting the A/D acquisition “Special Event Trigger” will be ignored by the A/D and conversion and the Timer1 (or Timer3) counter will module, but will still reset the Timer1 (or Timer3) coun- be reset to zero. Timer1 (or Timer3) is reset to automat- ter. ically repeat the A/D acquisition period with minimal TABLE 20-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(5) 57 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(5) 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(5) 58 ADRESH A/D Result Register High Byte 56 ADRESL A/D Result Register Low Byte 56 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 56 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 56 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 57 PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 58 TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Register 58 PORTB Read PORTB pins, Write LATB Latch 58 TRISB PORTB Data Direction Register 58 LATB PORTB Output Data Latch 58 PORTE(4) — — — — RE3(3) Read PORTE pins, Write LATE(1) 58 TRISE(4) IBF OBF IBOV PSPMODE — PORTE Data Direction 58 LATE(4) — — — — — LATE2 LATE1 LATE0 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These bits are unimplemented on PIC18F2X80 devices; always maintain these bits clear. 2: These pins may be configured as port pins depending on the Oscillator mode selected. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. 4: These registers are not implemented on PIC18F2X80 devices. 5: These bits are available on PIC18F4X80 and reserved on PIC18F2X80 devices. DS39637D-page 262 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 21.0 COMPARATOR MODULE The CMCON register (Register21-1) selects the comparator input and output configuration. Block The analog comparator module contains two diagrams of the various comparator configurations are comparators that can be configured in a variety of shown in Figure21-1. ways. The inputs can be selected from the analog inputs multiplexed with pins, RA0 through RA5, as well as the on-chip voltage reference (see Section22.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110: 1 = C1 VIN- connects to RD0/PSP0/C1IN+ C2 VIN- connects to RD2/PSP2/C2IN+ 0 = C1 VIN- connects to RD1/PSP1/C1IN- C2 VIN- connects to RD3/PSP3/C2IN- bit 2-0 CM<2:0>: Comparator Mode bits Figure21-1 shows the Comparator modes and the CM<2:0> bit settings. © 2009 Microchip Technology Inc. DS39637D-page 263

PIC18F2480/2580/4480/4580 21.1 Comparator Configuration changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section28.0 “Electrical Characteristics”. tors, shown in Figure21-1. Bits, CM<2:0> of the CMCON register, are used to select these modes. The Note: Comparator interrupts should be disabled TRISA register controls the data direction of the com- during a Comparator mode change; parator pins for each mode. If the Comparator mode is otherwise, a false interrupt may occur. FIGURE 21-1: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) Comparators Off CM<2:0> = 000 CM<2:0> = 111 RD1/PSP1/C1IN- A VIN- RD1/PSP1/C1IN- D VIN- Off RD0/PSP0/C1IN+ A VIN+ C1 O(Rfefad as ‘0’) RD0/PSP0/C1IN+ D VIN+ C1 (Read as ‘0’) RD3/PSP3/C2IN- A VIN- RD3/PSP3/C2IN- D VIN- Off RD2/PSP2/C2IN+ A VIN+ C2 O(Rfef ad as ‘0’) RD2/PSP2/C2IN+ D VIN+ C2 (Read as ‘0’) Two Independent Comparators Two Independent Comparators with Outputs CM<2:0> = 010 CM<2:0> = 011 RD1/PSP1/C1IN- A VIN- RD1/PSP1/C1IN- A VIN- RD0/PSP0/C1IN+ A VIN+ C1 C1OUT RD0/PSP0/C1IN+ A VIN+ C1 C1OUT RE1/WR/AN6/C1OUT* RD3/PSP3/C2IN- A VIN- A VIN+ C2 C2OUT RD3/PSP3/C2IN- A VIN- RD2/PSP2/C2IN+ RD2/PSP2/C2IN+ A VIN+ C2 C2OUT RE2/CS/AN7/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM<2:0> = 100 CM<2:0> = 101 RD1/PSP1/C1IN- A VIN- RD1/PSP1/C1IN- A VIN- RD0/PSP0/C1IN+ A VIN+ C1 C1OUT RD0/PSP0/C1IN+ A VIN+ C1 C1OUT RE1/WR/AN6/C1OUT* RD3/PSP3/C2IN- A VIN- RD2/PSP2/C2IN+ D VIN+ C2 C2OUT RD3/PSP3/C2IN- A VIN- RD2/PSP2/C2IN+ D VIN+ C2 C2OUT RE2/CS/AN7/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM<2:0> = 001 CM<2:0> = 110 RD1/PSP1/ RD1/PSP1/C1IN- A VIN- C1OUT C1IN- A CIS = 0 VIN- RD0/PSP0/C1IN+ A VIN+ C1 RCD1I0N/P+SP0/ A CIS = 1 VIN+ C1 C1OUT RE1/WR/AN6/C1OUT* RD3/PSP3/ A C2IN- CIS = 0 VIN- RD3/PSP3/C2IN- D VIN- RCD2I2N/P+SP2/ A CIS = 1 VIN+ C2 C2OUT Off RD2/PSP2/C2IN+ D VIN+ C2 (Read as ‘0’) CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs. DS39637D-page 264 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 21.2 Comparator Operation 21.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure21-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the com- the digital output. When the analog input at VIN+ is less parator voltage reference module. This module is than the analog input VIN-, the output of the comparator described in more detail in Section22.0 “Comparator is a digital low level. When the analog input at VIN+ is Voltage Reference Module”. greater than the analog input, VIN-, the output of the The internal reference is only available in the mode comparator is a digital high level. The shaded areas of where four inputs are multiplexed to two comparators the output of the comparator in Figure21-2 represent (CM<2:0>=110). In this mode, the internal voltage the uncertainty, due to input offsets and response time. reference is applied to the VIN+ pin of both comparators. 21.3 Comparator Reference 21.4 Comparator Response Time Depending on the comparator operating mode, either an external or internal voltage reference may be used. Response time is the minimum time, after selecting a The analog signal present at VIN- is compared to the new reference voltage or input source, before the signal at VIN+ and the digital output of the comparator comparator output has a valid level. If the internal is adjusted accordingly (Figure21-2). reference is changed, the maximum delay of the internal voltage reference must be considered when FIGURE 21-2: SINGLE COMPARATOR using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section28.0 “Electrical Characteristics”). VIN+ + 21.5 Comparator Outputs Output VIN- – The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RE1 and RE2 I/O pins. When enabled, multiplexers in the output path of the RE1 and RE2 pins will switch and the output of each pin will be the unsynchronized output of the VIN- comparator. The uncertainty of each of the comparators is related to the input offset voltage and VIN+ the response time given in the specifications. Figure21-3 shows the comparator output block diagram. Output The TRISE bits will still function as an output enable/ disable for the RE1 and RE2 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). 21.3.1 EXTERNAL REFERENCE SIGNAL Note1: When reading the PORT register, all pins When external voltage references are used, the configured as analog inputs will read as a comparator module can be configured to have the com- ‘0’. Pins configured as digital inputs will parators operate from the same or different reference convert an analog input according to the sources. However, threshold detector applications may Schmitt Trigger input specification. require the same reference. The reference signal must be between VSS and VDD and can be applied to either 2: Analog levels on any pin defined as a pin of the comparator(s). digital input may cause the input buffer to consume more current than is specified. © 2009 Microchip Technology Inc. DS39637D-page 265

PIC18F2480/2580/4480/4580 FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port Pins P TI To RE1 or UL - RE2 Pin M D Q Bus CxINV Data Read CMCON EN D Q Set CMIF bit EN CL From other Reset Comparator 21.6 Comparator Interrupts 21.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The While the comparator is powered up, higher Sleep CMIF bit must be reset by clearing it. Since it is also currents than shown in the power-down current possible to write a ‘1’ to this register, a simulated specification will occur. Each operational comparator interrupt may be initiated. will consume additional current, as shown in the com- Both the CMIE bit (PIE2<6>) and the PEIE bit parator specifications. To minimize power consumption (INTCON<6>) must be set to enable the interrupt. In while in Sleep mode, turn off the comparators addition, the GIE bit (INTCON<7>) must also be set. If (CM<2:0>=111) before entering Sleep. If the device any of these bits are clear, the interrupt is not enabled, wakes up from Sleep, the contents of the CMCON though the CMIF bit will still be set if an interrupt register are not affected. condition occurs. 21.8 Effects of a Reset Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a A device Reset forces the CMCON register to its Reset read operation is being executed (start of state, causing the comparator module to be in the Com- the Q2 cycle), then the CMIF (PIR parator Reset mode (CM<2:0>=000). This ensures registers) interrupt flag may not get set. that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at The user, in the Interrupt Service Routine, can clear the Reset time. The comparators are powered down during interrupt in the following manner: the Reset interval. a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit, CMIF. Reading CMCON will end the mismatch condition and allow flag bit, CMIF, to be cleared. DS39637D-page 266 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 21.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10kΩ is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure21-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 21-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: CMCON(3) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 57 CVRCON(3) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 57 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 58 IPR2 OSCFIP CMIP(2) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP 57 PIR2 OSCFIF CMIF(2) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF 58 PIE2 OSCFIE CMIE(2) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE 58 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 58 LATA LATA7(1) LATA6(1) LATA Data Output Register 58 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PORTA pins are enabled based on oscillator configuration. 2: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 3: These registers are unimplemented on PIC18F2X80 devices. © 2009 Microchip Technology Inc. DS39637D-page 267

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 268 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 22.0 COMPARATOR VOLTAGE each with 16 distinct levels. The range to be used is REFERENCE MODULE selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps The comparator voltage reference is a 16-tap resistor selected by the CVREF Selection bits (CVR<3:0>), with ladder network that provides a selectable reference one range offering finer resolution. The equations used voltage. Although its primary purpose is to provide a to calculate the output of the comparator voltage reference for the analog comparators, it may also be reference are as follows: used independently of them. If CVRR = 1: A block diagram is of the module shown in CVREF = ((CVR<3:0>)/24) x CVRSRC Figure22-1.The resistor ladder is segmented to If CVRR = 0: provide two ranges of CVREF values and has a CVREF = (CVDD x 1/4) + (((CVR<3:0>)/32) x power-down function to conserve power when the CVRSRC) reference is not being used. The module’s supply The comparator reference supply voltage can come reference can be provided from either device VDD/VSS or an external voltage reference. from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit 22.1 Configuring the Comparator (CVRCON<4>). Voltage Reference The settling time of the comparator voltage reference The voltage reference module is controlled through the must be considered when changing the CVREF output CVRCON register (Register22-1). The comparator (see Table28-3 in Section28.0 “Electrical voltage reference provides two ranges of output voltage, Characteristics”). REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA0/AN0/CVREF pin 0 = CVREF voltage is disconnected from the RA0/AN0/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0 ≤ (CVR<3:0>) ≤ 15) When CVRR = 1: CVREF = ((CVR<3:0>)/24) • (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) • (CVRSRC) Note 1: CVROE overrides the TRISA<0> bit setting. If enabled for output, RA2 must also be configured as an input by setting TRISA<2> to ‘1’. © 2009 Microchip Technology Inc. DS39637D-page 269

PIC18F2480/2580/4480/4580 FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U 16 Steps M 1 CVREF o 6 t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 22.2 Voltage Reference Accuracy/Error 22.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA0 pin by clearing (Figure22-1) keep CVREF from approaching the bit, CVROE (CVRCON<6>), and selects the high-voltage reference source rails. The voltage reference is derived range by clearing bit, CVRR (CVRCON<5>). The CVR from the reference source; therefore, the CVREF output value select bits are also cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 22.5 Connection Considerations found in Section28.0 “Electrical Characteristics”. The voltage reference module operates independently 22.3 Operation During Sleep of the comparator module. The output of the reference generator may be connected to the RA0 pin if the When the device wakes up from Sleep through an TRISA<0> bit and the CVROE bit are both set. interrupt or a Watchdog Timer time-out, the contents of Enabling the voltage reference output onto the RA0 the CVRCON register are not affected. To minimize pin, with an input signal present, will increase current current consumption in Sleep mode, the voltage consumption. Connecting RA0 as a digital output with reference should be disabled. CVRSS enabled will also increase current consumption. The RA0 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure22-2 shows an example buffering technique. DS39637D-page 270 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F4X80 CVREF R(1) Module + Voltage RA0 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: CVRCON(2) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 57 CMCON(2) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 57 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 58 Legend: Shaded cells are not used with the comparator voltage reference. Note 1: PORTA pins are enabled based on oscillator configuration. 2: These registers are unimplemented on PIC18F2X80 devices. © 2009 Microchip Technology Inc. DS39637D-page 271

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 272 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 23.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register23-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned PIC18F2480/2580/4480/4580 devices have a off” by the user under software control, which High/Low-Voltage Detect module (HLVD). This is a minimizes the current consumption for the device. programmable circuit that allows the user to specify The block diagram for the HLVD module is shown in both a device voltage trip point and the direction of Figure23-1. change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. REGISTER 23-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL<3:0>: High/Low-Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = 4.48V-4.69V 1101 = 4.23V-4.43V 1100 = 4.01V-4.20V 1011 = 3.81V-3.99V 1010 = 3.63V-3.80V 1001 = 3.46V-3.63V 1000 = 3.31V-3.47V 0111 = 3.05V-3.19V 0110 = 2.82V-2.95V 0101 = 2.72V-2.85V 0100 = 2.54V-2.66V 0011 = 2.38V-2.49V 0010 = 2.31V-2.42V 0001 = 2.18V-2.28V 0000 = 2.12V-2.22V Note 1: HLVDL<3:0> modes that result in a trip point below the valid operating voltage of the device are not tested. © 2009 Microchip Technology Inc. DS39637D-page 273

PIC18F2480/2580/4480/4580 The module is enabled by setting the HLVDEN bit. level at which the device detects a high or low-voltage Each time that the HLVD module is enabled, the event, depending on the configuration of the module. circuitry requires some time to stabilize. The IRVST bit When the supply voltage is equal to the trip point, the is a read-only bit and is used to indicate when the circuit voltage tapped off of the resistor array is equal to the is stable. The module can only generate an interrupt internal reference voltage generated by the voltage after the circuit is stable and IRVST is set. reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The VDIRMAG bit determines the overall operation of the module. When VDIRMAG is cleared, the module The trip point voltage is software programmable to any monitors for drops in VDD below a predetermined set one of 16 values. The trip point is selected by point. When the bit is set, the module monitors for rises programming the HLVDL<3:0> bits (HLVDCON<3:0>). in VDD above the set point. The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an 23.1 Operation external source. This mode is enabled when bits, HLVDL<3:0>, are set to ‘1111’. In this state, the com- When the HLVD module is enabled, a comparator uses parator input is multiplexed from the external input pin, an internally generated reference voltage as the set HLVDIN. This gives users flexibility because it allows point. The set point is compared with the trip point them to configure the High/Low-Voltage Detect interrupt where each node in the resistor divider represents a to occur at any voltage in the valid operating range. trip point voltage. The “trip point” voltage is the voltage FIGURE 23-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDIN HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o 6 t 1 HLVDEN Internal Voltage BOREN Reference DS39637D-page 274 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 23.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only module: need to be enabled for short periods where the voltage 1. Disable the module by clearing the HLVDEN bit is checked. After doing the check, the HLVD module (HLVDCON<4>). may be disabled. 2. Write the value to the HLVDL<3:0> bits that select the desired HLVD trip point. 23.4 HLVD Start-up Time 3. Set the VDIRMAG bit to detect high voltage The internal reference voltage of the HLVD module, (VDIRMAG = 1) or low voltage (VDIRMAG = 0). specified in electrical specification parameter D420, 4. Enable the HLVD module by setting the may be used by other internal circuitry, such as the HLVDEN bit. Programmable Brown-out Reset. If the HLVD or other 5. Clear the HLVD interrupt flag (PIR2<2>), which circuits using the voltage reference are disabled to may have been set from a previous interrupt. lower the device’s current consumption, the reference 6. Enable the HLVD interrupt if interrupts are voltage circuit will require time to become stable before desired by setting the HLVDIE and GIE bits a low or high-voltage condition can be reliably (PIE<2> and INTCON<7>). An interrupt will not detected. This start-up time, TIRVST, is an interval that be generated until the IRVST bit is set. is independent of device clock speed. It is specified in electrical specification parameter 36. 23.3 Current Consumption The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For When the module is enabled, the HLVD comparator this reason, brief excursions beyond the set point may and voltage divider are enabled and will consume static not be detected during this interval. Refer to current. The total current consumption, when enabled, Figure23-2 or Figure23-3. is specified in electrical specification parameter D022B. FIGURE 23-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VDD VLVD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists © 2009 Microchip Technology Inc. DS39637D-page 275

PIC18F2480/2580/4480/4580 FIGURE 23-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 23.5 Applications FIGURE 23-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, the ability to detect a drop below, or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach VA would indicate a high-voltage detect from, for example, VB 3.3V to 5V (the voltage on USB) and vice versa for a e g detach. This feature could save a design a few extra a t components and an attach signal (input pin). ol V For general battery applications, Figure23-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, Time TA TB which would allow the application to perform “house- keeping tasks” and perform a controlled shutdown Legend: VA = HLVD trip point before the device voltage exits the valid operating VB = Minimum valid device range at TB. The HLVD, thus, would give the applica- operating voltage tion a time window, represented by the difference between TA and TB, to safely exit. DS39637D-page 276 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 23.6 Operation During Sleep 23.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 23-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 56 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF ECCP1IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE ECCP1IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP ECCP1IP 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. © 2009 Microchip Technology Inc. DS39637D-page 277

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 278 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.0 ECAN MODULE 24.1 Module Overview PIC18F2480/2580/4480/4580 devices contain an The CAN bus module consists of a protocol engine and Enhanced Controller Area Network (ECAN) module. message buffering and control. The CAN protocol The ECAN module is fully backward compatible with engine automatically handles all functions for receiving the CAN module available in PIC18CXX8 and and transmitting messages on the CAN bus. Messages PIC18FXX8 devices. are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading The Controller Area Network (CAN) module is a serial the appropriate registers. Any message detected on interface which is useful for communicating with other the CAN bus is checked for errors and then matched peripherals or microcontroller devices. This interface, against filters to see if it should be received and stored or protocol, was designed to allow communications in one of the two receive registers. within noisy environments. The CAN module supports the following frame types: The ECAN module is a communication controller, imple- menting the CAN 2.0A or B protocol as defined in the • Standard Data Frame BOSCH specification. The module will support CAN1.2, • Extended Data Frame CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active • Remote Frame versions of the protocol. The module implementation is • Error Frame a full CAN system; however, the CAN specification is not • Overload Frame Reception covered within this data sheet. Refer to the BOSCH CAN specification for further details. The CAN module uses the RB2/CANTX and RB3/ CANRX pins to interface with the CAN bus. In normal The module features are as follows: mode, the CAN module automatically overrides • Implementation of the CAN protocol, CAN 1.2, TRISB<2>. The user must ensure that TRISB<3> is CAN 2.0A and CAN 2.0B set. • DeviceNetTM data bytes filter support • Standard and extended data frames 24.1.1 MODULE FUNCTIONALITY • 0-8 bytes data length The CAN bus module consists of a protocol engine, • Programmable bit rate up to 1 Mbit/sec message buffering and control (see Figure 24-1). The • Fully backward compatible with the PIC18XXX8 protocol engine can best be understood by defining the CAN module types of data frames to be transmitted and received by • Three modes of operation: the module. - Mode 0 – Legacy mode The following sequence illustrates the necessary initial- - Mode 1 – Enhanced Legacy mode with ization steps before the ECAN module can be used to DeviceNet support transmit or receive a message. Steps can be added or - Mode 2 – FIFO mode with DeviceNet support removed depending on the requirements of the • Support for remote frames with automated handling application. • Double-buffered receiver with two prioritized 1. Initial LAT and TRIS bits for RX and TX CAN. received message storage buffers 2. Ensure that the ECAN module is in Configuration • Six buffers programmable as RX and TX mode. message buffers 3. Select ECAN Operational mode. • 16 full (standard/extended identifier) acceptance 4. Set up the Baud Rate registers. filters that can be linked to one of four masks • Two full acceptance filter masks that can be 5. Set up the Filter and Mask registers. assigned to any filter 6. Set the ECAN module to normal mode or any • One full acceptance filter that can be used as either other mode required by the application logic. an acceptance filter or acceptance filter mask • Three dedicated transmit buffers with application specified prioritization and abort capability • Programmable wake-up functionality with integrated low-pass filter • Programmable Loopback mode supports self-test operation • Signaling via interrupt capabilities for all CAN receiver and transmitter error states • Programmable clock source • Programmable link to timer module for time-stamping and network synchronization • Low-power Sleep mode © 2009 Microchip Technology Inc. DS39637D-page 279

PIC18F2480/2580/4480/4580 FIGURE 24-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS k 16 - 4 to 1 MUXs s a M e 0 cM TXB0 TXB1 TXB2 Ac(RceXpFta0n-RceX FF0ilt5e)rs VCC ceptanRX A MODE 0 c A MSGREQABTFMLOATXERRMTXBUFF MESSAGE MSGREQABTFMLOATXERRMTXBUFF MESSAGE MSGREQABTFMLOATXERRMTXBUFF MESSAGE ccep Acceptance Filters RXF15 e Mask1 t (RMXFO0D6E-R 1X, F215) ptancRXM e c c Message MODE 0 A Queue 2 RX Identifier Buffers M Control A Transmit Byte Sequencer Data Field B MODE 1, 2 Rcv Byte 6 TX/RX Buffers Transmit Option MESSAGE BUFFERS PROTOCOL Receive REC ENGINE Error Counter TEC Transmit Err-Pas Error Bus-Off Counter Transmit<7:0> Receive<8:0> Shift<14:0> {Transmit<5:0>, Receive<8:0>} Comparator Protocol Finite State CRC<14:0> Machine Bit Transmit Clock Timing Logic Generator Logic Configuration TX RX Registers DS39637D-page 280 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.2 CAN Module Registers 24.2.1 CAN CONTROL AND STATUS REGISTERS Note: Not all CAN registers are available in the The registers described in this section control the Access Bank. overall operation of the CAN module and show its There are many control and data registers associated operational status. with the CAN module. For convenience, their descriptions have been grouped into the following sections: • Control and Status Registers • Dedicated Transmit Buffer Registers • Dedicated Receive Buffer Registers • Programmable TX/RX and Auto RTR Buffers • Baud Rate Control Registers • I/O Control Register • Interrupt Status and Control Registers Detailed descriptions of each register and their usage are described in the following sections. © 2009 Microchip Technology Inc. DS39637D-page 281

PIC18F2480/2580/4480/4580 REGISTER 24-1: CANCON: CAN CONTROL REGISTER R/W-1 R/W-0 R/W-0 R/S-0 R/W-0 R/W-0 R/W-0 U-0 Mode 0 REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — R/W-1 R/W-0 R/W-0 R/S-0 U0 U-0 U-0 U-0 Mode 1 REQOP2 REQOP1 REQOP0 ABAT — — — — R/W-1 R/W-0 R/W-0 R/S-0 R-0 R-0 R-0 R-0 Mode 2 REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0 bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 REQOP<2:0>: Request CAN Operation Mode bits 1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Disabled/Sleep mode 000 = Request Normal mode bit 4 ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers)(1) 0 = Transmissions proceeding as normal bit 3-1 Mode 0: WIN<2:0>: Window Address bits These bits select which of the CAN buffers to switch into the Access Bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE<3:0> bits can be copied to the WIN<2:0> bits to select the correct buffer. See Example24-2 for a code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 bit 0 Unimplemented: Read as ‘0’ bit 4-0 Mode 1: Unimplemented: Read as ‘0’ Mode 2: FP<3:0>: FIFO Read Pointer bits These bits point to the message buffer to be read. 0000 = Receive Message Buffer 0 0001 = Receive Message Buffer 1 0010 = Receive Message Buffer 2 0011 = Receive Message Buffer 3 0100 = Receive Message Buffer 4 0101 = Receive Message Buffer 5 0110 = Receive Message Buffer 6 0111 = Receive Message Buffer 7 1000:1111 Reserved Note 1: This bit will clear when all transmissions are aborted. DS39637D-page 282 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-2: CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 R-0 R-0 R-0 R-0 U-0 Mode 0 OPMODE2(1) OPMODE1(1) OPMODE0(1) — ICODE3 ICODE2 ICODE1 — R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1,2 OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 EICODE2 EICODE1 EICODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 OPMODE<2:0>: Operation Mode Status bits(1) 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable/Sleep mode 000 = Normal mode bit 4 Mode 0: Unimplemented: Read as ‘0’ bit 3-1 ICODE<3:1>: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. By copying ICODE<3:1> to WIN<3:0> (Mode0) or EICODE<4:0> to EWIN<4:0> (Mode 1 and 2), it is possible to select the correct buffer to map into the Access Bank area. See Example24-2 for a code example. To simplify the description, the following table lists all five bits. Mode 0 Mode 1 Mode 2 No interrupt 00000 00000 00000 CAN bus error interrupt 00010 00010 00010 TXB2 interrupt 00100 00100 00100 TXB1 interrupt 00110 00110 00110 TXB0 interrupt 01000 01000 01000 RXB1 interrupt 01010 10001 ----- RXB0 interrupt 01100 10000 10000 Wake-up interrupt 00010 01110 01110 RXB0 interrupt ----- 10000 10000 RXB1 interrupt ----- 10001 10000 RX/TX B0 interrupt ----- 10010 10010(2) RX/TX B1 interrupt ----- 10011 10011(2) RX/TX B2 interrupt ----- 10100 10100(2) RX/TX B3 interrupt ----- 10101 10101(2) RX/TX B4 interrupt ----- 10110 10110(2) RX/TX B5 interrupt ----- 10111 10111(2) bit 0 Unimplemented: Read as ‘0’ bit 4-0 Mode 1, 2: EICODE<4:0>: Interrupt Code bits See ICODE<3:1> above. Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch CAN module in Disable/Sleep mode before putting device to Sleep. 2: If buffer is configured as receiver, EICODE bits will contain ‘10000’ upon interrupt. © 2009 Microchip Technology Inc. DS39637D-page 283

PIC18F2480/2580/4480/4580 EXAMPLE 24-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B’10000000’ ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing. ConfigWait: MOVF CANSTAT, W ; Read current mode state. ANDLW B’10000000’ ; Interested in OPMODE bits only. TSTFSZ WREG ; Is it Configuration mode yet? BRA ConfigWait ; No. Continue to wait... ; Module is in Configuration mode now. ; Modify configuration registers as required. ; Switch back to Normal mode to be able to communicate. EXAMPLE 24-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low MOVFF CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred MOVFF CANSTAT, TempCANSTAT ; Save CANSTAT register ; This is required to make sure that ; we use same CANSTAT value rather ; than one changed by another CAN ; interrupt. MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B’00001110’ ADDWF PCL, F ; Perform computed GOTO ; to corresponding interrupt cause BRA NoInterrupt ; 000 = No interrupt BRA ErrorInterrupt ; 001 = Error interrupt BRA TXB2Interrupt ; 010 = TXB2 interrupt BRA TXB1Interrupt ; 011 = TXB1 interrupt BRA TXB0Interrupt ; 100 = TXB0 interrupt BRA RXB1Interrupt ; 101 = RXB1 interrupt BRA RXB0Interrupt ; 110 = RXB0 interrupt ; 111 = Wake-up on interrupt WakeupInterrupt BCF PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here … NoInterrupt … ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error. DS39637D-page 284 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 EXAMPLE 24-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag … ; Handle error. RETFIE TXB2Interrupt BCF PIR3, TXB2IF ; Clear the interrupt flag GOTO AccessBuffer TXB1Interrupt BCF PIR3, TXB1IF ; Clear the interrupt flag GOTO AccessBuffer TXB0Interrupt BCF PIR3, TXB0IF ; Clear the interrupt flag GOTO AccessBuffer RXB1Interrupt BCF PIR3, RXB1IF ; Clear the interrupt flag GOTO Accessbuffer RXB0Interrupt BCF PIR3, RXB0IF ; Clear the interrupt flag GOTO AccessBuffer AccessBuffer ; This is either TX or RX interrupt ; Copy CANSTAT.ICODE bits to CANCON.WIN bits MOVF TempCANCON, W ; Clear CANCON.WIN bits before copying ; new ones. ANDLW B’11110001’ ; Use previously saved CANCON value to ; make sure same value. MOVWF TempCANCON ; Copy masked value back to TempCANCON MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B’00001110’ ; Use previously saved CANSTAT value ; to make sure same value. IORWF TempCANCON ; Copy ICODE bits to WIN bits. MOVFF TempCANCON, CANCON ; Copy the result to actual CANCON ; Access current buffer… ; User code ; Restore CANCON.WIN bits MOVF CANCON, W ; Preserve current non WIN bits ANDLW B’11110001’ IORWF TempCANCON ; Restore original WIN bits ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source © 2009 Microchip Technology Inc. DS39637D-page 285

PIC18F2480/2580/4480/4580 REGISTER 24-3: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 MDSEL1(1) MDSEL0(1) FIFOWM(2) EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 MDSEL<1:0>: Mode Select bits(1) 00 = Legacy mode (Mode 0, default) 01 = Enhanced Legacy mode (Mode 1) 10 = Enhanced FIFO mode (Mode 2) 11 = Reserved bit 5 FIFOWM: FIFO High Water Mark bit(2) 1 = Will cause FIFO interrupt when one receive buffer remains 0 = Will cause FIFO interrupt when four receive buffers remain(3) bit 4-0 EWIN<4:0>: Enhanced Window Address bits These bits map the group of 16 banked CAN SFRs into Access Bank addresses 0F60-0F6Dh. The exact group of registers to map is determined by the binary value of these bits. Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: 00000 = Acceptance Filters 0, 1, 2 and BRGCON2, 3 00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON 00010 = Acceptance Filter Masks, Error and Interrupt Control 00011 = Transmit Buffer 0 00100 = Transmit Buffer 1 00101 = Transmit Buffer 2 00110 = Acceptance Filters 6, 7, 8 00111 = Acceptance Filters 9, 10, 11 01000 = Acceptance Filters 12, 13, 14 01001 = Acceptance Filters 15 01010-01110 = Reserved 01111 = RXINT0, RXINT1 10000 = Receive Buffer 0 10001 = Receive Buffer 1 10010 = TX/RX Buffer 0 10011 = TX/RX Buffer 1 10100 = TX/RX Buffer 2 10101 = TX/RX Buffer 3 10110 = TX/RX Buffer 4 10111 = TX/RX Buffer 5 11000-11111 = Reserved Note 1: These bits can only be changed in Configuration mode. See Register24-1 to change to Configuration mode. 2: This bit is used in Mode 2 only. 3: If FIFO is configured to contain four or less buffers, then the FIFO interrupt will trigger. DS39637D-page 286 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-4: COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1 — RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 2 FIFOEMPTY RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Mode 0: RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowed Mode 1: Unimplemented: Read as ‘0’ Mode 2: FIFOEMPTY: FIFO Not Empty bit 1 = Receive FIFO is not empty 0 = Receive FIFO is empty bit 6 Mode 0: RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed Mode 1, 2: RXBnOVFL: Receive Buffer n Overflow bit 1 = Receive Buffer n has overflowed 0 = Receive Buffer n has not overflowed bit 5 TXBO: Transmitter Bus-Off bit 1 = Transmit error counter > 255 0 = Transmit error counter ≤ 255 bit 4 TXBP: Transmitter Bus Passive bit 1 = Transmit error counter > 127 0 = Transmit error counter ≤ 127 bit 3 RXBP: Receiver Bus Passive bit 1 = Receive error counter > 127 0 = Receive error counter ≤ 127 bit 2 TXWARN: Transmitter Warning bit 1 = Transmit error counter > 95 0 = Transmit error counter ≤ 95 bit 1 RXWARN: Receiver Warning bit 1 = 127 ≥ Receive error counter > 95 0 = Receive error counter ≤ 95 bit 0 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits. 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set © 2009 Microchip Technology Inc. DS39637D-page 287

PIC18F2480/2580/4480/4580 24.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers. REGISTER 24-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 ≤ n ≤ 2] U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 Mode 0 — TXABT(1) TXLARB(1) TXERR(1) TXREQ(2) — TXPRI1(3) TXPRI0(3) R/C-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 Mode 1,2 TXBIF TXABT(1) TXLARB(1) TXERR(1) TXREQ(2) — TXPRI1(3) TXPRI0(3) bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: TXBIF: Transmit Buffer Interrupt Flag bit 1 = Transmit buffer has completed transmission of message and may be reloaded 0 = Transmit buffer has not completed transmission of a message bit 6 TXABT: Transmission Aborted Status bit(1) 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit(2) 1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits. 0 = Automatically cleared when the message is successfully sent bit 2 Unimplemented: Read as ‘0’ bit 1-0 TXPRI<1:0>: Transmit Priority bits(3) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) Note 1: This bit is automatically cleared when TXREQ is set. 2: While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in software while the bit is set will request a message abort. 3: These bits define the order in which transmit buffers will be transferred. They do not alter the CAN message identifier. DS39637D-page 288 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits EID<28:21> (if EXIDE = 1). REGISTER 24-7: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 2] R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits EID<20:18> (if EXIDE = 1). bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended ID, SID<10:0> become EID<28:18> 0 = Message will transmit standard ID, EID<17:0> are ignored bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits REGISTER 24-8: TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier bits (not used when transmitting standard identifier message) © 2009 Microchip Technology Inc. DS39637D-page 289

PIC18F2480/2580/4480/4580 REGISTER 24-9: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier bits (not used when transmitting standard identifier message) REGISTER 24-10: TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS [0 ≤ n ≤ 2, 0 ≤ m ≤ 7] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TXBnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 ≤ m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. DS39637D-page 290 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-11: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 2] U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmit Remote Frame Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 DLC<3:0>: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes REGISTER 24-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TEC<7:0>: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11consecutive recessive bits, the counter value is cleared. © 2009 Microchip Technology Inc. DS39637D-page 291

PIC18F2480/2580/4480/4580 EXAMPLE 24-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected. BANKSEL TXB0CON ; One BANKSEL in beginning will make sure that we are ; in correct bank for rest of the buffer access. ; Now load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF TXB0D0 ; Compiler will automatically set “BANKED” bit ; Load rest of data bytes - up to 8 bytes into TXB0 buffer. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF TXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF TXB0SIDH ; No need to load TXB0EIDL:TXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B’00001000’ ; Normal priority; Request transmission MOVWF TXB0CON ; If required, wait for message to get transmitted BTFSC TXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted. EXAMPLE 24-4: TRANSMITTING A CAN MESSAGE USING WIN BITS ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area. MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON ; register to preserve all other bits. If operation ; mode is already known, there is no need to preserve ; other bits. ANDLW B’11110000’ ; Clear WIN bits. IORLW B’00001000’ ; Select Transmit Buffer 0 MOVWF CANCON ; Apply the changes. ; Now TXB0 is mapped in place of RXB0. All future access to RXB0 registers will actually ; yield TXB0 register values. ; Load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF RXB0D0 ; Access TXB0D0 via RXB0D0 address. ; Load rest of the data bytes - up to 8 bytes into “TXB0” buffer using RXB0 registers. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF RXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF RXB0SIDH ; No need to load RXB0EIDL:RXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B’00001000’ ; Normal priority; Request transmission MOVWF RXB0CON ; If required, wait for message to get transmitted BTFSC RXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted. ; If required, reset the WIN bits to default state. DS39637D-page 292 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers. REGISTER 24-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 Mode 0 RXFUL(1) RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF(2) FILHIT0 R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1,2 RXFUL(1) RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message bit 6 Mode 0: RXM1: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’ 01 = Receive only valid messages with standard identifier; EXIDEN in RXFnSIDL must be ‘0’ 00 = Receive all valid messages as per EXIDEN bit in the RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters bit 5 Mode 0: RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0>bits, see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received bit 4 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: FILHIT4: Filter Hit bit 4 This bit combines with other bits to form filter acceptance bits<4:0>. bit 3 Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT3: Filter Hit bit 3 This bit combines with other bits to form filter acceptance bits<4:0>. Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. After clearing the RXFUL flag, the PIR3 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is not cleared, then RXB0IF is set again. 2: This bit allows same filter jump table for both RXB0CON and RXB1CON. © 2009 Microchip Technology Inc. DS39637D-page 293

PIC18F2480/2580/4480/4580 REGISTER 24-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT2: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits<4:0>. bit 1 Mode 0: JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)(2) 1 = Allows jump table offset between 6 and 7 0 = Allows jump table offset between 1 and 0 Mode 1, 2: FILHIT1: Filter Hit bit 1 This bit combines with other bits to form filter acceptance bits<4:0>. bit 0 Mode 0: FILHIT0: Filter Hit bit 0 This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0. 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Mode 1, 2: FILHIT0: Filter Hit bit 0 This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. After clearing the RXFUL flag, the PIR3 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is not cleared, then RXB0IF is set again. 2: This bit allows same filter jump table for both RXB0CON and RXB1CON. DS39637D-page 294 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 Mode 0 RXFUL(1) RXM1 RXM0 — RXRTRRO FILHIT2 FILHIT1 FILHIT0 R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1,2 RXFUL(1) RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message bit 6 Mode 0: RXM1: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’ 01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’ 00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters bit 5 Mode 0: RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0> bits, see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received bit 4 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: FILHIT4: Filter Hit bit 4 This bit combines with other bits to form the filter acceptance bits<4:0>. bit 3 Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT3: Filter Hit bit 3 This bit combines with other bits to form the filter acceptance bits<4:0>. Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. © 2009 Microchip Technology Inc. DS39637D-page 295

PIC18F2480/2580/4480/4580 REGISTER 24-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER (CONTINUED) bit 2-0 Mode 0: FILHIT<2:0>: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1. 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set Mode 1, 2: FILHIT<2:0> Filter Hit bits <2:0> These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. REGISTER 24-15: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 1] R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier bits (if EXID (RXBnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXID = 1). DS39637D-page 296 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-16: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 1] R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if EXID = 1). bit 4 SRR: Substitute Remote Request bit This bit is always ‘1’ when EXID = 1 or equal to the value of RXRTRRO (RBXnCON<3>) when EXID = 0. bit 3 EXID: Extended Identifier bit 1 = Received message is an extended data frame, SID<10:0> are EID<28:18 > 0 = Received message is a standard data frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits REGISTER 24-17: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 1] R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier bits REGISTER 24-18: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 1] R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier bits © 2009 Microchip Technology Inc. DS39637D-page 297

PIC18F2480/2580/4480/4580 REGISTER 24-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 1] U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as ‘0’. bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as ‘0’. bit 3-0 DLC<3:0>: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes REGISTER 24-20: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS [0 ≤ n ≤ 1, 0 ≤ m ≤ 7] R-x R-x R-x R-x R-x R-x R-x R-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RXBnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7. DS39637D-page 298 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 REC<7:0>: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications. When RXERRCNT> 127, the module will go into an error-passive state. RXERRCNT does not have the ability to put the module in “bus-off” state. EXAMPLE 24-5: READING A CAN MESSAGE ; Need to read a pending message from RXB0 buffer. ; To receive any message, filter, mask and RXM1:RXM0 bits in RXB0CON registers must be ; programmed correctly. ; ; Make sure that there is a message pending in RXB0. BTFSS RXB0CON, RXFUL ; Does RXB0 contain a message? BRA NoMessage ; No. Handle this situation... ; We have verified that a message is pending in RXB0 buffer. ; If this buffer can receive both Standard or Extended Identifier messages, ; identify type of message received. BTFSS RXB0SIDL, EXID ; Is this Extended Identifier? BRA StandardMessage ; No. This is Standard Identifier message. ; Yes. This is Extended Identifier message. ; Read all 29-bits of Extended Identifier message. ... ; Now read all data bytes MOVFF RXB0DO, MY_DATA_BYTE1 ... ; Once entire message is read, mark the RXB0 that it is read and no longer FULL. BCF RXB0CON, RXFUL ; This will allow CAN Module to load new messages ; into this buffer. ... © 2009 Microchip Technology Inc. DS39637D-page 299

PIC18F2480/2580/4480/4580 24.2.3.1 Programmable TX/RX and Auto-RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. Note: These registers are not used in Mode 0. REGISTER 24-22: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 RXFUL(2) RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RXFUL: Receive Full Status bit(2) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message bit 6 RXM1: Receive Buffer Mode bit 1 = Receive all messages including partial and invalid (acceptance filters are ignored) 0 = Receive all valid messages as per acceptance filters bit 5 RXRTRRO: Read-Only Remote Transmission Request for Received Message bit 1 = Received message is a remote transmission request 0 = Received message is not a remote transmission request bit 4-0 FILHIT<4:0>: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into this buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00001 = Acceptance Filter 1 (RXF1) 00000 = Acceptance Filter 0 (RXF0) Note 1: These registers are available in Mode 1 and 2 only. 2: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered full. DS39637D-page 300 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXBIF(3) TXABT(3) TXLARB(3) TXERR(3) TXREQ(2,4) RTREN TXPRI1(5) TXPRI0(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXBIF: Transmit Buffer Interrupt Flag bit(3) 1 = A message is successfully transmitted 0 = No message was transmitted bit 6 TXABT: Transmission Aborted Status bit(3) 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit(3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit(3) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit(2,4) 1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits 0 = Automatically cleared when the message is successfully sent bit 2 RTREN: Automatic Remote Transmission Request Enable bit 1 = When a remote transmission request is received, TXREQ will be automatically set 0 = When a remote transmission request is received, TXREQ will be unaffected bit 1-0 TXPRI<1:0>: Transmit Priority bits(5) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) Note 1: These registers are available in Mode 1 and 2 only. 2: Clearing this bit in software while the bit is set will request a message abort. 3: This bit is automatically cleared when TXREQ is set. 4: While TXREQ is set or a transmission is in progress, Transmit Buffer registers remain read-only. 5: These bits set the order in which the Transmit Buffer register will be transferred. They do not alter the CAN message identifier. © 2009 Microchip Technology Inc. DS39637D-page 301

PIC18F2480/2580/4480/4580 REGISTER 24-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXIDE = 1). Note 1: These registers are available in Mode 1 and 2 only. REGISTER 24-25: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if EXIDE = 1). Note 1: These registers are available in Mode 1 and 2 only. DS39637D-page 302 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if EXID = 1). bit 4 SRR: Substitute Remote Transmission Request bit This bit is always ‘1’ when EXID = 1 or equal to the value of RXRTRRO (BnCON<5>) when EXID = 0. bit 3 EXID: Extended Identifier Enable bit 1 = Received message is an extended identifier frame (SID<10:0> are EID<28:18>) 0 = Received message is a standard identifier frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 24-27: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXIDE = 0) Extended Identifier bits, EID<20:18> (if EXIDE = 1). bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Received message is an extended identifier frame (SID<10:0> are EID<28:18>) 0 = Received message is a standard identifier frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. © 2009 Microchip Technology Inc. DS39637D-page 303

PIC18F2480/2580/4480/4580 REGISTER 24-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 24-29: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 24-30: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. DS39637D-page 304 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-31: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only. REGISTER 24-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE [0 ≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 BnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to B0D7. Note 1: These registers are available in Mode 1 and 2 only. REGISTER 24-33: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN TRANSMIT MODE [0 ≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 BnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. Note 1: These registers are available in Mode 1 and 2 only. © 2009 Microchip Technology Inc. DS39637D-page 305

PIC18F2480/2580/4480/4580 REGISTER 24-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0](1) U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = This is a remote transmission request 0 = This is not a remote transmission request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as ‘0’. bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as ‘0’. bit 3-0 DLC<3:0>: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes Note 1: These registers are available in Mode 1 and 2 only. DS39637D-page 306 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-35: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 1](1) U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmitter Remote Transmission Request bit 1 = Transmitted message will have RTR bit set 0 = Transmitted message will have RTR bit cleared bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 DLC<3:0>: Data Length Code bits 1111-1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes Note 1: These registers are available in Mode 1 and 2 only. REGISTER 24-36: BSEL0: BUFFER SELECT REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 B5TXEN:B0TXEN: Buffer 5 to Buffer 0 Transmit Enable bit 1 = Buffer is configured in Transmit mode 0 = Buffer is configured in Receive mode bit 1-0 Unimplemented: Read as ‘0’ Note 1: These registers are available in Mode 1 and 2 only. © 2009 Microchip Technology Inc. DS39637D-page 307

PIC18F2480/2580/4480/4580 24.2.3.2 Message Acceptance Filters and Masks This section describes the message acceptance filters and masks for the CAN receive buffers. REGISTER 24-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER REGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier Filter bits (if EXIDEN = 0) Extended Identifier Filter bits, EID<28:21> (if EXIDEN = 1). Note 1: Registers, RXF6SIDH:RXF15SIDH, are available in Mode 1 and 2 only. REGISTER 24-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER REGISTERS, LOW BYTE [0 ≤ n ≤ 15](1) R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN(2) — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier Filter bits (if EXIDEN = 0) Extended Identifier Filter bits, EID<20:18> (if EXIDEN = 1). bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDEN: Extended Identifier Filter Enable bit(2) 1 = Filter will only accept extended ID messages 0 = Filter will only accept standard ID messages bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier Filter bits Note 1: Registers, RXF6SIDL:RXF15SIDL, are available in Mode 1 and 2 only. 2: In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value. DS39637D-page 308 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier Filter bits Note 1: Registers, RXF6EIDH:RXF15EIDH, are available in Mode 1 and 2 only. REGISTER 24-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier Filter bits Note 1: Registers, RXF6EIDL:RXF15EIDL, are available in Mode 1 and 2 only. REGISTER 24-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, HIGH BYTE [0 ≤ n ≤ 1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SID<10:3>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<28:21>) © 2009 Microchip Technology Inc. DS39637D-page 309

PIC18F2480/2580/4480/4580 REGISTER 24-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0 ≤ n ≤ 1] R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN(1) — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<20:18>) bit 4 Unimplemented: Read as ‘0’ bit 3 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: EXIDEN: Extended Identifier Filter Enable Mask bit(1) 1 = Messages selected by the EXIDEN bit in RXFnSIDL will be accepted 0 = Both standard and extended identifier messages will be accepted bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier Mask bits Note 1: This bit is available in Mode 1 and 2 only. REGISTER 24-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK REGISTERS, HIGH BYTE [0 ≤ n ≤ 1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<15:8>: Extended Identifier Mask bits REGISTER 24-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK REGISTERS, LOW BYTE [0 ≤ n ≤ 1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EID<7:0>: Extended Identifier Mask bits DS39637D-page 310 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 ≤ n ≤ 1](1) R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RXFCON0 RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 RXFCON1 RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RXFnEN: Receive Filter n Enable bits 0 = Filter is disabled 1 = Filter is enabled Note 1: This register is available in Mode 1 and 2 only. Note: Register24-46 through Register24-51 are writable in Configuration mode only. REGISTER 24-46: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLC4 FLC3 FLC2 FLC1 FLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 FLC<4:0>: Filter Length Count bits Mode 0: Not used; forced to ‘00000’. 00000-10010 =0 18 bits are available for standard data byte filter. Actual number of bits used depends on the DLC<3:0> bits (RXBnDLC<3:0> or BnDLC<3:0> if configured as RX buffer) of the message being received. If DLC<3:0> =0000 No bits will be compared with incoming data bits. If DLC<3:0> =0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC<2:0>, will be com- pared with the corresponding number of data bits of the incoming message. If DLC<3:0> =0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC<3:0>, will be compared with the corresponding number of data bits of the incoming message. If DLC<3:0> =0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC<4:0>, will be compared with the corresponding number of data bits of the incoming message. Note 1: This register is available in Mode 1 and 2 only. © 2009 Microchip Technology Inc. DS39637D-page 311

PIC18F2480/2580/4480/4580 REGISTER 24-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER n(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON0 F1BP_3 F1BP_2 F1BP_1 F1BP_0 F0BP_3 F0BP_2 F0BP_1 F0BP_0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 RXFBCON1 F3BP_3 F3BP_2 F3BP_1 F3BP_0 F2BP_3 F2BP_2 F2BP_1 F2BP_0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 RXFBCON2 F5BP_3 F5BP_2 F5BP_1 F5BP_0 F4BP_3 F4BP_2 F4BP_1 F4BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON3 F7BP_3 F7BP_2 F7BP_1 F7BP_0 F6BP_3 F6BP_2 F6BP_1 F6BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON4 F9BP_3 F9BP_2 F9BP_1 F9BP_0 F8BP_3 F8BP_2 F8BP_1 F8BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON5 F11BP_3 F11BP_2 F11BP_1 F11BP_0 F10BP_3 F10BP_2 F10BP_1 F10BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON6 F13BP_3 F13BP_2 F13BP_1 F13BP_0 F12BP_3 F12BP_2 F12BP_1 F12BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON7 F15BP_3 F15BP_2 F15BP_1 F15BP_0 F14BP_3 F14BP_2 F14BP_1 F14BP_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 FnBP_<3:0>: Filter n Buffer Pointer Nibble bits 0000 = Filter n is associated with RXB0 0001 = Filter n is associated with RXB1 0010 = Filter n is associated with B0 0011 = Filter n is associated with B1 ... 0111 = Filter n is associated with B5 1111-1000 = Reserved Note 1: This register is available in Mode 1 and 2 only. DS39637D-page 312 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FIL3_<1:0>: Filter 3 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL2_<1:0>: Filter 2 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL1_<1:0>: Filter 1 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL0_<1:0>: Filter 0 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: This register is available in Mode 1 and 2 only. © 2009 Microchip Technology Inc. DS39637D-page 313

PIC18F2480/2580/4480/4580 REGISTER 24-49: MSEL1: MASK SELECT REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FIL7_<1:0>: Filter 7 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL6_<1:0>: Filter 6 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL5_<1:0>: Filter 5 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL4_<1:0>: Filter 4 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: This register is available in Mode 1 and 2 only. DS39637D-page 314 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-50: MSEL2: MASK SELECT REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FIL11_<1:0>: Filter 11 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL10_<1:0>: Filter 10 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL9_<1:0>: Filter 9 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL8_<1:0>: Filter 8 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: This register is available in Mode 1 and 2 only. © 2009 Microchip Technology Inc. DS39637D-page 315

PIC18F2480/2580/4480/4580 REGISTER 24-51: MSEL3: MASK SELECT REGISTER 3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FIL15_<1:0>: Filter 15 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL14_<1:0>: Filter 14 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL13_<1:0>: Filter 13 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL12_<1:0>: Filter 12 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note 1: This register is available in Mode 1 and 2 only. DS39637D-page 316 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.2.4 CAN BAUD RATE REGISTERS This section describes the CAN Baud Rate registers. Note: These registers are writable in Configuration mode only. REGISTER 24-52: BRGCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SJW<1:0>: Synchronized Jump Width bits 11 = Synchronization jump width time = 4 x TQ 10 = Synchronization jump width time = 3 x TQ 01 = Synchronization jump width time = 2 x TQ 00 = Synchronization jump width time = 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC : : 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC © 2009 Microchip Technology Inc. DS39637D-page 317

PIC18F2480/2580/4480/4580 REGISTER 24-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits 111 = Phase Segment 1 time = 8 x TQ 110 = Phase Segment 1 time = 7 x TQ 101 = Phase Segment 1 time = 6 x TQ 100 = Phase Segment 1 time = 5 x TQ 011 = Phase Segment 1 time = 4 x TQ 010 = Phase Segment 1 time = 3 x TQ 001 = Phase Segment 1 time = 2 x TQ 000 = Phase Segment 1 time = 1 x TQ bit 2-0 PRSEG<2:0>: Propagation Time Select bits 111 = Propagation time = 8 x TQ 110 = Propagation time = 7 x TQ 101 = Propagation time = 6 x TQ 100 = Propagation time = 5 x TQ 011 = Propagation time = 4 x TQ 010 = Propagation time = 3 x TQ 001 = Propagation time = 2 x TQ 000 = Propagation time = 1 x TQ DS39637D-page 318 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 WAKDIS WAKFIL — — — SEG2PH2(1) SEG2PH1(1) SEG2PH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAKDIS: Wake-up Disable bit 1 = Disable CAN bus activity wake-up feature 0 = Enable CAN bus activity wake-up feature bit 6 WAKFIL: Selects CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 SEG2PH<2:0>: Phase Segment 2 Time Select bits(1) 111 = Phase Segment 2 time = 8 x TQ 110 = Phase Segment 2 time = 7 x TQ 101 = Phase Segment 2 time = 6 x TQ 100 = Phase Segment 2 time = 5 x TQ 011 = Phase Segment 2 time = 4 x TQ 010 = Phase Segment 2 time = 3 x TQ 001 = Phase Segment 2 time = 2 x TQ 000 = Phase Segment 2 time = 1 x TQ Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is ‘0’. © 2009 Microchip Technology Inc. DS39637D-page 319

PIC18F2480/2580/4480/4580 24.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller. REGISTER 24-55: CIOCON: CAN I/O CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — ENDRHI(1) CANCAP — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ENDRHI: Enable Drive High bit(1) 1 = CANTX pin will drive VDD when recessive 0 = CANTX pin will be tri-state when recessive bit 4 CANCAP: CAN Message Receive Capture Enable bit 1 = Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1 0 = Disable CAN capture, RC2/CCP1 input to CCP1 module bit 3-0 Unimplemented: Read as ‘0’ Note 1: Always set this bit when using a differential bus to avoid signal crosstalk in CANTX from other nearby pins. DS39637D-page 320 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section10.0 “Interrupts”. They are duplicated here for convenience. REGISTER 24-56: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 0 IRXIF WAKIF ERRIF TXB2IF TXB1IF(1) TXB0IF(1) RXB1IF RXB0IF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 1,2 IRXIF WAKIF ERRIF TXBnIF TXB1IF(1) TXB0IF(1) RXBnIF FIFOWMIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIF: CAN Bus Error Message Received Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus bit 6 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus bit 5 ERRIF: CAN Module Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources; refer to Section24.15.6 “Error Interrupt”) 0 = No CAN module errors bit 4 When CAN is in Mode 0: TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message When CAN is in Mode 1 or 2: TXBnIF: Any Transmit Buffer Interrupt Flag bit 1 = One or more transmit buffers have completed transmission of a message and may be reloaded 0 = No transmit buffer is ready for reload bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1) 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1) 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 When CAN is in Mode 0: RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2: RXBnIF: Any Receive Buffer Interrupt Flag bit 1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message bit 0 When CAN is in Mode 0: RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIF: FIFO Watermark Interrupt Flag bit 1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. © 2009 Microchip Technology Inc. DS39637D-page 321

PIC18F2480/2580/4480/4580 REGISTER 24-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 0 IRXIE WAKIE ERRIE TXB2IE TXB1IE(1) TXB0IE(1) RXB1IE RXB0IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Mode 1 IRXIE WAKIE ERRIE TXBnIE TXB1IE(1) TXB0IE(1) RXBnIE FIFOWMIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIE: CAN Bus Error Message Received Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN module error interrupt 0 = Disable CAN module error interrupt bit 4 When CAN is in Mode 0: TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt When CAN is in Mode 1 or 2: TXBnIE: CAN Transmit Buffer Interrupts Enable bit 1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 When CAN is in Mode 0: RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2: RXBnIE: CAN Receive Buffer Interrupts Enable bit 1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts bit 0 When CAN is in Mode 0: RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. DS39637D-page 322 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 24-58: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Mode 0 IRXIP WAKIP ERRIP TXB2IP TXB1IP(1) TXB0IP(1) RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Mode 1,2 IRXIP WAKIP ERRIP TXBnIP TXB1IP(1) TXB0IP(1) RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIP: CAN Bus Error Message Received Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN Module Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 When CAN is in Mode 0: TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: TXBnIP: CAN Transmit Buffer Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 1 When CAN is in Mode 0: RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: RXBnIP: CAN Receive Buffer Interrupts Priority bit 1 = High priority 0 = Low priority bit 0 When CAN is in Mode 0: RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIP: FIFO Watermark Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. © 2009 Microchip Technology Inc. DS39637D-page 323

PIC18F2480/2580/4480/4580 REGISTER 24-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — TXB2IE(2) TXB1IE(2) TXB0IE(2) — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bits(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer interrupt is disabled bit 1-0 Unimplemented: Read as ‘0’ Note 1: This register is available in Mode 1 and 2 only. 2: TXBnIE in PIE3 register must be set to get an interrupt. REGISTER 24-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 B5IE(2) B4IE(2) B3IE(2) B2IE(2) B1IE(2) B0IE(2) RXB1IE(2) RXB0IE(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 B5IE:B0IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bits(2) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1-0 RXB1IE:RXB0IE: Dedicated Receive Buffer 1-0 Interrupt Enable bits(2) 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This register is available in Mode 1 and 2 only. 2: Either TXBnIE or RXBnIE in the PIE3 register must be set to get an interrupt. DS39637D-page 324 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 24-1: CAN CONTROLLER REGISTER MAP Address(1) Name Address Name Address Name Address Name F7Fh SPBRGH(3) F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL F7Eh BAUDCON(3) F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH F7Dh —(4) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch —(4) F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh —(4) F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah —(4) F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h ECCP1DEL(3) F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h —(4) F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh CANCON_RO1(2) F2Fh CANCON_RO3(2) F0Fh RXF3EIDL F6Eh CANSTAT F4Eh CANSTAT_RO1(2) F2Eh CANSTAT_RO3(2) F0Eh RXF3EIDH F6Dh RXB0D7 F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’. © 2009 Microchip Technology Inc. DS39637D-page 325

PIC18F2480/2580/4480/4580 TABLE 24-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name Address Name Address Name Address Name EFFh —(4) EDFh —(4) EBFh —(4) E9Fh —(4) EFEh —(4) EDEh —(4) EBEh —(4) E9Eh —(4) EFDh —(4) EDDh —(4) EBDh —(4) E9Dh —(4) EFCh —(4) EDCh —(4) EBCh —(4) E9Ch —(4) EFBh —(4) EDBh —(4) EBBh —(4) E9Bh —(4) EFAh —(4) EDAh —(4) EBAh —(4) E9Ah —(4) EF9h —(4) ED9h —(4) EB9h —(4) E99h —(4) EF8h —(4) ED8h —(4) EB8h —(4) E98h —(4) EF7h —(4) ED7h —(4) EB7h —(4) E97h —(4) EF6h —(4) ED6h —(4) EB6h —(4) E96h —(4) EF5h —(4) ED5h —(4) EB5h —(4) E95h —(4) EF4h —(4) ED4h —(4) EB4h —(4) E94h —(4) EF3h —(4) ED3h —(4) EB3h —(4) E93h —(4) EF2h —(4) ED2h —(4) EB2h —(4) E92h —(4) EF1h —(4) ED1h —(4) EB1h —(4) E91h —(4) EF0h —(4) ED0h —(4) EB0h —(4) E90h —(4) EEFh —(4) ECFh —(4) EAFh —(4) E8Fh —(4) EEEh —(4) ECEh —(4) EAEh —(4) E8Eh —(4) EEDh —(4) ECDh —(4) EADh —(4) E8Dh —(4) EECh —(4) ECCh —(4) EACh —(4) E8Ch —(4) EEBh —(4) ECBh —(4) EABh —(4) E8Bh —(4) EEAh —(4) ECAh —(4) EAAh —(4) E8Ah —(4) EE9h —(4) EC9h —(4) EA9h —(4) E89h —(4) EE8h —(4) EC8h —(4) EA8h —(4) E88h —(4) EE7h —(4) EC7h —(4) EA7h —(4) E87h —(4) EE6h —(4) EC6h —(4) EA6h —(4) E86h —(4) EE5h —(4) EC5h —(4) EA5h —(4) E85h —(4) EE4h —(4) EC4h —(4) EA4h —(4) E84h —(4) EE3h —(4) EC3h —(4) EA3h —(4) E83h —(4) EE2h —(4) EC2h —(4) EA2h —(4) E82h —(4) EE1h —(4) EC1h —(4) EA1h —(4) E81h —(4) EE0h —(4) EC0h —(4) EA0h —(4) E80h —(4) Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’. DS39637D-page 326 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 24-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name Address Name Address Name Address Name E7Fh CANCON_RO4(2) E5Fh CANCON_RO6(2) E3Fh CANCON_RO8(2) E1Fh —(4) E7Eh CANSTAT_RO4(2) E5Eh CANSTAT_RO6(2) E3Eh CANSTAT_RO8(2) E1Eh —(4) E7Dh B5D7 E5Dh B3D7 E3Dh B1D7 E1Dh —(4) E7Ch B5D6 E5Ch B3D6 E3Ch B1D6 E1Ch —(4) E7Bh B5D5 E5Bh B3D5 E3Bh B1D5 E1Bh —(4) E7Ah B5D4 E5Ah B3D4 E3Ah B1D4 E1Ah —(4) E79h B5D3 E59h B3D3 E39h B1D3 E19h —(4) E78h B5D2 E58h B3D2 E38h B1D2 E18h —(4) E77h B5D1 E57h B3D1 E37h B1D1 E17h —(4) E76h B5D0 E56h B3D0 E36h B1D0 E16h —(4) E75h B5DLC E55h B3DLC E35h B1DLC E15h —(4) E74h B5EIDL E54h B3EIDL E34h B1EIDL E14h —(4) E73h B5EIDH E53h B3EIDH E33h B1EIDH E13h —(4) E72h B5SIDL E52h B3SIDL E32h B1SIDL E12h —(4) E71h B5SIDH E51h B3SIDH E31h B1SIDH E11h —(4) E70h B5CON E50h B3CON E30h B1CON E10h —(4) E6Fh CANCON_RO5 E4Fh CANCON_RO7 E2Fh CANCON_RO9 E0Fh —(4) E6Eh CANSTAT_RO5 E4Eh CANSTAT_RO7 E2Eh CANSTAT_RO9 E0Eh —(4) E6Dh B4D7 E4Dh B2D7 E2Dh B0D7 E0Dh —(4) E6Ch B4D6 E4Ch B2D6 E2Ch B0D6 E0Ch —(4) E6Bh B4D5 E4Bh B2D5 E2Bh B0D5 E0Bh —(4) E6Ah B4D4 E4Ah B2D4 E2Ah B0D4 E0Ah —(4) E69h B4D3 E49h B2D3 E29h B0D3 E09h —(4) E68h B4D2 E48h B2D2 E28h B0D2 E08h —(4) E67h B4D1 E47h B2D1 E27h B0D1 E07h —(4) E66h B4D0 E46h B2D0 E26h B0D0 E06h —(4) E65h B4DLC E45h B2DLC E25h B0DLC E05h —(4) E64h B4EIDL E44h B2EIDL E24h B0EIDL E04h —(4) E63h B4EIDH E43h B2EIDH E23h B0EIDH E03h —(4) E62h B4SIDL E42h B2SIDL E22h B0SIDL E02h —(4) E61h B4SIDH E41h B2SIDH E21h B0SIDH E01h —(4) E60h B4CON E40h B2CON E20h B0CON E00h —(4) Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’. © 2009 Microchip Technology Inc. DS39637D-page 327

PIC18F2480/2580/4480/4580 TABLE 24-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name Address Name Address Name Address Name DFFh —(4) DDFh —(4) DBFh —(4) D9Fh —(4) DFEh —(4) DDEh —(4) DBEh —(4) D9Eh —(4) DFDh —(4) DDDh —(4) DBDh —(4) D9Dh —(4) DFCh TXBIE DDCh —(4) DBCh —(4) D9Ch —(4) DFBh —(4) DDBh —(4) DBBh —(4) D9Bh —(4) DFAh BIE0 DDAh —(4) DBAh —(4) D9Ah —(4) DF9h —(4) DD9h —(4) DB9h —(4) D99h —(4) DF8h BSEL0 DD8h SDFLC DB8h —(4) D98h —(4) DF7h —(4) DD7h —(4) DB7h —(4) D97h —(4) DF6h —(4) DD6h —(4) DB6h —(4) D96h —(4) DF5h —(4) DD5h RXFCON1 DB5h —(4) D95h —(4) DF4h —(4) DD4h RXFCON0 DB4h —(4) D94h —(4) DF3h MSEL3 DD3h —(4) DB3h —(4) D93h RXF15EIDL DF2h MSEL2 DD2h —(4) DB2h —(4) D92h RXF15EIDH DF1h MSEL1 DD1h —(4) DB1h —(4) D91h RXF15SIDL DF0h MSEL0 DD0h —(4) DB0h —(4) D90h RXF15SIDH DEFh —(4) DCFh —(4) DAFh —(4) D8Fh —(4) DEEh —(4) DCEh —(4) DAEh —(4) D8Eh —(4) DEDh —(4) DCDh —(4) DADh —(4) D8Dh —(4) DECh —(4) DCCh —(4) DACh —(4) D8Ch —(4) DEBh —(4) DCBh —(4) DABh —(4) D8Bh RXF14EIDL DEAh —(4) DCAh —(4) DAAh —(4) D8Ah RXF14EIDH DE9h —(4) DC9h —(4) DA9h —(4) D89h RXF14SIDL DE8h —(4) DC8h —(4) DA8h —(4) D88h RXF14SIDH DE7h RXFBCON7 DC7h —(4) DA7h —(4) D87h RXF13EIDL DE6h RXFBCON6 DC6h —(4) DA6h —(4) D86h RXF13EIDH DE5h RXFBCON5 DC5h —(4) DA5h —(4) D85h RXF13SIDL DE4h RXFBCON4 DC4h —(4) DA4h —(4) D84h RXF13SIDH DE3h RXFBCON3 DC3h —(4) DA3h —(4) D83h RXF12EIDL DE2h RXFBCON2 DC2h —(4) DA2h —(4) D82h RXF12EIDH DE1h RXFBCON1 DC1h —(4) DA1h —(4) D81h RXF12SIDL DE0h RXFBCON0 DC0h —(4) DA0h —(4) D80h RXF12SIDH Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’. DS39637D-page 328 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 24-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name D7Fh —(4) D7Eh —(4) D7Dh —(4) D7Ch —(4) D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh —(4) D6Eh —(4) D6Dh —(4) D6Ch —(4) D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7SIDL D64h RXF7SIDH D63h RXF6EIDL D62h RXF6EIDH D61h RXF6SIDL D60h RXF6SIDH Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’. © 2009 Microchip Technology Inc. DS39637D-page 329

PIC18F2480/2580/4480/4580 24.3 CAN Modes of Operation 24.3.2 DISABLE/SLEEP MODE The PIC18F2480/2580/4480/4580 has six main modes In Disable/Sleep mode, the module will not transmit or of operation: receive. The module has the ability to set the WAKIF bit due to bus activity; however, any pending interrupts will • Configuration mode remain and the error counters will retain their value. • Disable/Sleep mode If the REQOP<2:0> bits are set to ‘001’, the module will • Normal Operation mode enter the module Disable/Sleep mode. This mode is • Listen Only mode similar to disabling other peripheral modules by turning • Loopback mode off the module enables. This causes the module • Error Recognition mode internal clock to stop unless the module is active (i.e., receiving or transmitting a message). If the module is All modes, except Error Recognition, are requested by active, the module will wait for 11 recessive bits on the setting the REQOP bits (CANCON<7:5>). Error Recog- CAN bus, detect that condition as an Idle bus, then nition mode is requested through the RXM bits of the accept the module Disable/Sleep command. Receive Buffer register(s). Entry into a mode is OPMODE<2:0> = 001 indicates whether the module Acknowledged by monitoring the OPMODE bits. successfully went into the module Disable/Sleep mode. When changing modes, the mode will not actually The WAKIF interrupt is the only module interrupt that is change until all pending message transmissions are still active in the Disable/Sleep mode. If the WAKDIS is complete. Because of this, the user must verify that the cleared and WAKIE is set, the processor will receive an device has actually changed into the requested mode interrupt whenever the module detects recessive to before further operations are executed. dominant transition. On wake-up, the module will auto- matically be set to the previous mode of operation. For 24.3.1 CONFIGURATION MODE example, if the module was switched from Normal to The CAN module has to be initialized before the Disable/Sleep mode on bus activity wake-up, the activation. This is only possible if the module is in the module will automatically enter into Normal mode and Configuration mode. The Configuration mode is the first message that caused the module to wake-up is requested by setting the REQOP2 bit. Only when the lost. The module will not generate any error frame. status bit, OPMODE2, has a high level can the initial- Firmware logic must detect this condition and make ization be performed. Afterwards, the Configuration sure that retransmission is requested. If the processor registers, the acceptance mask registers and the receives a wake-up interrupt while it is sleeping, more acceptance filter registers can be written. The module than one message may get lost. The actual number of is activated by setting the REQOP control bits to zero. messages lost would depend on the processor The module will protect the user from accidentally oscillator start-up time and incoming message bit rate. violating the CAN protocol through programming The TXCAN pin will stay in the recessive state while the errors. All registers which control the configuration of module is in Disable/Sleep mode. the module can not be modified while the module is on- line. The CAN module will not be allowed to enter the 24.3.3 NORMAL MODE Configuration mode while a transmission or reception This is the standard operating mode of the is taking place. The Configuration mode serves as a PIC18F2480/2580/4480/4580 devices. In this mode, lock to protect the following registers: the device actively monitors all bus messages and gen- • Configuration Registers erates Acknowledge bits, error frames, etc. This is also • Functional Mode Selection Registers the only mode in which the PIC18F2480/2580/4480/ 4580 devices will transmit messages over the CAN • Bit Timing Registers bus. • Identifier Acceptance Filter Registers • Identifier Acceptance Mask Registers • Filter and Mask Control Registers • Mask Selection Registers In the Configuration mode, the module will not transmit or receive. The error counters are cleared and the inter- rupt flags remain unchanged. The programmer will have access to Configuration registers that are access restricted in other modes. I/O pins will revert to normal I/O functions. DS39637D-page 330 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.3.4 LISTEN ONLY MODE 24.4 CAN Module Functional Modes Listen Only mode provides a means for the In addition to CAN modes of operation, the ECAN mod- PIC18F2480/2580/4480/4580 devices to receive all ule offers a total of 3 functional modes. Each of these messages, including messages with errors. This mode modes are identified as Mode 0, Mode 1 and Mode 2. can be used for bus monitor applications or for detecting the baud rate in ‘hot plugging’ situations. For 24.4.1 MODE 0 – LEGACY MODE auto-baud detection, it is necessary that there are at Mode 0 is designed to be fully compatible with CAN least two other nodes which are communicating with modules used in PIC18CXX8 and PIC18FXX8 devices. each other. The baud rate can be detected empirically This is the default mode of operation on all Reset con- by testing different values until valid messages are ditions. As a result, module code written for the received. The Listen Only mode is a silent mode, PIC18XX8 CAN module may be used on the ECAN meaning no messages will be transmitted while in this module without any code changes. state, including error flags or Acknowledge signals. The filters and masks can be used to allow only particular The following is the list of resources available in Mode 0: messages to be loaded into the receive registers or the • Three transmit buffers: TXB0, TXB1 and TXB2 filter masks can be set to all zeros to allow a message • Two receive buffers: RXB0 and RXB1 with any identifier to pass. The error counters are reset • Two acceptance masks, one for each receive buf- and deactivated in this state. The Listen Only mode is fer: RXM0, RXM1 activated by setting the mode request bits in the CANCON register. • Six acceptance filters, 2 for RXB0 and 4 for RXB1: RXF0, RXF1, RXF2, RXF3, RXF4, RXF5 24.3.5 LOOPBACK MODE 24.4.2 MODE 1 – ENHANCED LEGACY This mode will allow internal transmission of messages MODE from the transmit buffers to the receive buffers without actually transmitting messages on the CAN bus. This Mode 1 is similar to Mode 0, with the exception mode can be used in system development and testing. thatmore resources are available in Mode 1. There are In this mode, the ACK bit is ignored and the device will 16 acceptance filters and two acceptance mask regis- allow incoming messages from itself, just as if they ters. Acceptance Filter 15 can be used as either an were coming from another node. The Loopback mode acceptance filter or an acceptance mask register. In is a silent mode, meaning no messages will be trans- addition to three transmit and two receive buffers, there mitted while in this state, including error flags or are six more message buffers. One or more of these Acknowledge signals. The TXCAN pin will revert to port additional buffers can be programmed as transmit or I/O while the device is in this mode. The filters and receive buffers. These additional buffers can also be masks can be used to allow only particular messages programmed to automatically handle RTR messages. to be loaded into the receive registers. The masks can Fourteen of sixteen acceptance filter registers can be be set to all zeros to provide a mode that accepts all dynamically associated to any receive buffer and messages. The Loopback mode is activated by setting acceptance mask register. One can use this capability the mode request bits in the CANCON register. to associate more than one filter to any one buffer. 24.3.6 ERROR RECOGNITION MODE When a receive buffer is programmed to use standard identifier messages, part of the full acceptance filter reg- The module can be set to ignore all errors and receive ister can be used as a data byte filter. The length of the any message. In functional Mode 0, the Error Recogni- data byte filter is programmable from 0 to 18 bits. This tion mode is activated by setting the RXM<1:0> bits in functionality simplifies implementation of high-level the RXBnCON registers to ‘11’. In this mode, the data protocols, such as the DeviceNet™ protocol. which is in the message assembly buffer until the error time, is copied in the receive buffer and can be read via The following is the list of resources available in Mode 1: the CPU interface. • Three transmit buffers: TXB0, TXB1 and TXB2 • Two receive buffers: RXB0 and RXB1 • Six buffers programmable as TX or RX: B0-B5 • Automatic RTR handling on B0-B5 • Sixteen dynamically assigned acceptance filters: RXF0-RXF15 • Two dedicated acceptance mask registers; RXF15 programmable as third mask: RXM0-RXM1, RXF15 • Programmable data filter on standard identifier messages: SDFLC © 2009 Microchip Technology Inc. DS39637D-page 331

PIC18F2480/2580/4480/4580 24.4.3 MODE 2 – ENHANCED FIFO MODE Each receive buffer contains one Control register (RXBnCON), four Identifier registers (RXBnSIDL, In Mode 2, two or more receive buffers are used to form RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data Length the receive FIFO (first in, first out) buffer. There is no Count register (RXBnDLC) and eight Data Byte one-to-one relationship between the receive buffer and registers (RXBnDm). acceptance filter registers. Any filter that is enabled and linked to any FIFO receive buffer can generate There is also a separate Message Assembly Buffer acceptance and cause FIFO to be updated. (MAB) which acts as an additional receive buffer. MAB is always committed to receiving the next message FIFO length is user-programmable, from 2-8 buffers from the bus and is not directly accessible to user firm- deep. FIFO length is determined by the very first pro- ware. The MAB assembles all incoming messages one grammable buffer that is configured as a transmit buf- by one. A message is transferred to appropriate fer. For example, if Buffer 2 (B2) is programmed as a receive buffers only if the corresponding acceptance transmit buffer, FIFO consists of RXB0, RXB1, B0 and filter criteria is met. B1 – creating a FIFO length of 4. If all programmable buffers are configured as receive buffers, FIFO will 24.5.3 PROGRAMMABLE TRANSMIT/ have the maximum length of 8. RECEIVE BUFFERS The following is the list of resources available in Mode 2: The ECAN module implements six new buffers: B0-B5. • Three transmit buffers: TXB0, TXB1 and TXB2 These buffers are individually programmable as either • Two receive buffers: RXB0 and RXB1 transmit or receive buffers. These buffers are available • Six buffers programmable as TX or RX; receive only in Mode 1 and 2. As with dedicated transmit and buffers form FIFO: B0-B5 receive buffers, each of these programmable buffers occupies 14 bytes of SRAM and are mapped into SFR • Automatic RTR handling on B0-B5 memory map. • Sixteen acceptance filters: RXF0-RXF15 Each buffer contains one Control register (BnCON), • Two dedicated acceptance mask registers; four Identifier registers (BnSIDL, BnSIDH, BnEIDL, RXF15 programmable as third mask: BnEIDH), one Data Length Count register (BnDLC) RXM0-RXM1, RXF15 and eight Data Byte registers (BnDm). Each of these • Programmable data filter on standard identifier registers contains two sets of control bits. Depending messages: SDFLC, useful for DeviceNet protocol on whether the buffer is configured as transmit or receive, one would use the corresponding control bit 24.5 CAN Message Buffers set. By default, all buffers are configured as receive buffers. Each buffer can be individually configured as a 24.5.1 DEDICATED TRANSMIT BUFFERS transmit or receive buffer by setting the corresponding The PIC18F2480/2580/4480/4580 devices implement TXENn bit in the BSEL0 register. three dedicated transmit buffers – TXB0, TXB1 and When configured as transmit buffers, user firmware TXB2. Each of these buffers occupies 14 bytes of may access transmit buffers in any order similar to SRAM and are mapped into the SFR memory map. accessing dedicated transmit buffers. In receive These are the only transmit buffers available in configuration with Mode 1 enabled, user firmware may Mode0. Mode 1 and 2 may access these and other also access receive buffers in any order required. But additional buffers. in Mode 2, all receive buffers are combined to form a Each transmit buffer contains one Control register single FIFO. Actual FIFO length is programmable by (TXBnCON), four Identifier registers (TXBnSIDL, user firmware. Access to FIFO must be done through TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data Length the FIFO Pointer bits (FP<4:0>) in the CANCON Count register (TXBnDLC) and eight Data Byte register. It must be noted that there is no hardware registers (TXBnDm). protection against out of order FIFO reads. 24.5.2 DEDICATED RECEIVE BUFFERS The PIC18F2480/2580/4480/4580 devices implement two dedicated receive buffers: RXB0 and RXB1. Each of these buffers occupies 14 bytes of SRAM and are mapped into SFR memory map. These are the only receive buffers available in Mode 0. Mode 1 and 2 may access these and other additional buffers. DS39637D-page 332 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.5.4 PROGRAMMABLE AUTO-RTR Setting the TXREQ bit does not initiate a message BUFFERS transmission; it merely flags a message buffer as ready for transmission. Transmission will start when the In Mode 1 and 2, any of six programmable transmit/ device detects that the bus is available. The device will receive buffers may be programmed to automatically then begin transmission of the highest priority message respond to predefined RTR messages without user that is ready. firmware intervention. Automatic RTR handling is enabled by setting the TXnEN bit in the BSEL0 register When the transmission has completed successfully, the and the RTREN bit in the BnCON register. After this TXREQ bit will be cleared, the TXBnIF bit will be set and setup, when an RTR request is received, the TXREQ an interrupt will be generated if the TXBnIE bit is set. bit is automatically set and the current buffer content is If the message transmission fails, the TXREQ will remain automatically queued for transmission as a RTR set, indicating that the message is still pending for trans- response. As with all transmit buffers, once the TXREQ mission and one of the following condition flags will be bit is set, buffer registers become read-only and any set. If the message started to transmit but encountered writes to them will be ignored. an error condition, the TXERR and the IRXIF bits will be The following outlines the steps required to set and an interrupt will be generated. If the message lost automatically handle RTR messages: arbitration, the TXLARB bit will be set. 1. Set buffer to Transmit mode by setting the 24.6.2 ABORTING TRANSMISSION TXnEN bit to ‘1’ in BSEL0 register. The MCU can request to abort a message by clearing 2. At least one acceptance filter must be associ- the TXREQ bit associated with the corresponding mes- ated with this buffer and preloaded with the sage buffer (TXBnCON<3> or BnCON<3>). Setting the expected RTR identifier. ABAT bit (CANCON<4>) will request an abort of all 3. Bit, RTREN in the BnCON register, must be set pending messages. If the message has not yet started to ‘1’. transmission, or if the message started but is inter- 4. Buffer must be preloaded with the data to be rupted by loss of arbitration or an error, the abort will be sent as a RTR response. processed. The abort is indicated when the module Normally, user firmware will keep buffer data registers sets the TXABT bit for the corresponding buffer up to date. If firmware attempts to update the buffer (TXBnCON<6> or BnCON<6>). If the message has while an automatic RTR response is in the process of started to transmit, it will attempt to transmit the current transmission, all writes to buffers are ignored. message fully. If the current message is transmitted fully and is not lost to arbitration or an error, the TXABT 24.6 CAN Message Transmission bit will not be set because the message was transmit- ted successfully. Likewise, if a message is being trans- 24.6.1 INITIATING TRANSMISSION mitted during an abort request and the message is lost to arbitration or an error, the message will not be For the MCU to have write access to the message buf- retransmitted and the TXABT bit will be set, indicating fer, the TXREQ bit must be clear, indicating that the that the message was successfully aborted. message buffer is clear of any pending message to be Once an abort is requested by setting the ABAT or transmitted. At a minimum, the SIDH, SIDL and DLC TXABT bits, it cannot be cleared to cancel the abort registers must be loaded. If data bytes are present in request. Only CAN module hardware or a POR the message, the Data registers must also be loaded. condition can clear it. If the message is to use extended identifiers, the EIDH:EIDL registers must also be loaded and the EXIDE bit set. To initiate message transmission, the TXREQ bit must be set for each buffer to be transmitted. When TXREQ is set, the TXABT, TXLARB and TXERR bits will be cleared. To successfully complete the transmission, there must be at least one node with matching baud rate on the network. © 2009 Microchip Technology Inc. DS39637D-page 333

PIC18F2480/2580/4480/4580 24.6.3 TRANSMIT PRIORITY The transmit buffer with the highest priority will be sent first. If two buffers have the same priority setting, the Transmit priority is a prioritization within the buffer with the highest buffer number will be sent first. PIC18F2480/2580/4480/4580 devices of the pending There are four levels of transmit priority. If the TXP bits transmittable messages. This is independent from and for a particular message buffer are set to ‘11’, that buf- not related to any prioritization implicit in the message fer has the highest possible priority. If the TXP bits for arbitration scheme built into the CAN protocol. Prior to a particular message buffer are set to ‘00’, that buffer sending the Start-Of-Frame (SOF), the priority of all has the lowest possible priority. buffers that are queued for transmission is compared. FIGURE 24-2: TRANSMIT BUFFERS TXB0 TXB1 TXB2 TXB3 - TXB8 E E E E TXREQ TXABT TXLARB TXERR TXB0IF MESSAG TXREQ TXABT TXLARB TXERR TXB1IF MESSAG TXREQ TXABT TXLARB TXERR TXB2IF MESSAG TXREQ TXABT TXLARB TXERR TXB2IF MESSAG Message Queue Control Transmit Byte Sequencer DS39637D-page 334 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.7 Message Reception Normally, these bits are set to ‘00’ to enable reception of all valid messages as determined by the appropriate 24.7.1 RECEIVING A MESSAGE acceptance filters. In this case, the determination of whether or not to receive standard or extended mes- Of all receive buffers, the MAB is always committed to sages is determined by the EXIDE bit in the accep- receiving the next message from the bus. The MCU tance filter register. In Mode 0, if the RXM bits are set can access one buffer while the other buffer is available to ‘01’ or ‘10’, the receiver will accept only messages for message reception or holding a previously received with standard or extended identifiers, respectively. If an message. acceptance filter has the EXIDE bit set such that it does Note: The entire contents of the MAB are moved not correspond with the RXM mode, that acceptance into the receive buffer once a message is filter is rendered useless. In Mode 1 and 2, setting accepted. This means that regardless of EXID in the SIDL Mask register will ensure that only the type of identifier (standard or standard or extended identifiers are received. These extended) and the number of data bytes two modes of RXM bits can be used in systems where received, the entire receive buffer is over- it is known that only standard or extended messages written with the MAB contents. Therefore, will be on the bus. If the RXM bits are set to ‘11’ (RXM1 the contents of all registers in the buffer = 1 in Mode 1 and 2), the buffer will receive all mes- must be assumed to have been modified sages regardless of the values of the acceptance fil- when any message is received. ters. Also, if a message has an error before the end of frame, that portion of the message assembled in the When a message is moved into either of the receive MAB before the error frame will be loaded into the buf- buffers, the associated RXFUL bit is set. This bit must fer. This mode may serve as a valuable debugging tool be cleared by the MCU when it has completed process- for a given CAN network. It should not be used in an ing the message in the buffer in order to allow a new actual system environment as the actual system will message to be received into the buffer. This bit always have some bus errors and all nodes on the bus provides a positive lockout to ensure that the firmware are expected to ignore them. has finished with the message before the module attempts to load a new message into the receive buffer. In Mode 1 and 2, when a programmable buffer is If the receive interrupt is enabled, an interrupt will be configured as a transmit buffer and one or more accep- generated to indicate that a valid message has been tance filters are associated with it, all incoming messages received. matching this acceptance filter criteria will be discarded. To avoid this scenario, user firmware must make sure Once a message is loaded into any matching buffer, that there are no acceptance filters associated with a user firmware may determine exactly what filter caused buffer configured as a transmit buffer. this reception by checking the filter hit bits in the RXBnCON or BnCON registers. In Mode 0, 24.7.2 RECEIVE PRIORITY FILHIT<3:0> of RXBnCON serve as filter hit bits. In Mode 1 and 2, FILHIT<4:0> bits of BnCON serve as fil- When in Mode 0, RXB0 is the higher priority buffer and ter hit bits. The same registers also indicate whether has two message acceptance filters associated with it. the current message is an RTR frame or not. A RXB1 is the lower priority buffer and has four acceptance received message is considered a standard identifier filters associated with it. The lower number of acceptance message if the EXID bit in the RXBnSIDL or the filters makes the match on RXB0 more restrictive and BnSIDL register is cleared. Conversely, a set EXID bit implies a higher priority for that buffer. Additionally, the indicates an extended identifier message. If the RXB0CON register can be configured such that if RXB0 received message is a standard identifier message, contains a valid message and another valid message is user firmware needs to read the SIDL and SIDH regis- received, an overflow error will not occur and the new ters. In the case of an extended identifier message, message will be moved into RXB1 regardless of the firmware should read the SIDL, SIDH, EIDL and EIDH acceptance criteria of RXB1. There are also two registers. If the RXBnDLC or BnDLC register contain programmable acceptance filter masks available, one for non-zero data count, user firmware should also read each receive buffer (see Section24.5 “CAN Message the corresponding number of data bytes by accessing Buffers”). the RXBnDm or the BnDm registers. When a received In Mode 1 and 2, there are a total of 16 acceptance message is an RTR and if the current buffer is not con- filters available and each can be dynamically assigned figured for automatic RTR handling, user firmware to any of the receive buffers. A buffer with a lower must take appropriate action and respond manually. number has higher priority. Given this, if an incoming Each receive buffer contains RXM bits to set special message matches with two or more receive buffer Receive modes. In Mode 0, RXM<1:0> bits in acceptance criteria, the buffer with the lower number RXBnCON define a total of four Receive modes. In will be loaded with that message. Mode 1 and 2, RXM1 bit, in combination with the EXID mask and filter bit, define the same four receive modes. © 2009 Microchip Technology Inc. DS39637D-page 335

PIC18F2480/2580/4480/4580 24.7.3 ENHANCED FIFO MODE 24.7.4 TIME-STAMPING When configured for Mode 2, two of the dedicated The CAN module can be programmed to generate a receive buffers in combination with one or more pro- time-stamp for every message that is received. When grammable transmit/receive buffers, are used to create enabled, the module generates a capture signal for a maximum of an 8 buffer deep FIFO buffer. In this CCP1, which in turn captures the value of either Timer1 mode, there is no direct correlation between filters and or Timer3. This value can be used as the message receive buffer registers. Any filter that has been time-stamp. enabled can generate an acceptance. When a mes- To use the time-stamp capability, the CANCAP bit sage has been accepted, it is stored in the next avail- (CIOCON<4>) must be set. This replaces the capture able receive buffer register and an internal Write input for CCP1 with the signal generated from the CAN Pointer is incremented. The FIFO can be a maximum module. In addition, CCP1CON<3:0> must be set to of 8 buffers deep. The entire FIFO must consist of con- ‘0011’ to enable the CCP Special Event Trigger for tiguous receive buffers. The FIFO head begins at CAN events. RXB0 buffer and its tail spans toward B5. The maxi- mum length of the FIFO is limited by the presence or 24.8 Message Acceptance Filters absence of the first transmit buffer starting from B0. If a and Masks buffer is configured as a transmit buffer, the FIFO length is reduced accordingly. For instance, if B3 is The message acceptance filters and masks are used to configured as a transmit buffer, the actual FIFO will determine if a message in the Message Assembly Buf- consist of RXB0, RXB1, B0, B1 and B2, a total of 5 buf- fer should be loaded into any of the receive buffers. fers. If B0 is configured as a transmit buffer, the FIFO Once a valid message has been received into the MAB, length will be 2. If none of the programmable buffers the identifier fields of the message are compared to the are configured as a transmit buffer, the FIFO will be filter values. If there is a match, that message will be 8buffers deep. A system that requires more transmit loaded into the appropriate receive buffer. The filter buffers should try to locate transmit buffers at the very masks are used to determine which bits in the identifier end of B0-B5 buffers to maximize available FIFO are examined with the filters. A truth table is shown length. below in Table24-2 that indicates how each bit in the When a message is received in FIFO mode, the inter- identifier is compared to the masks and filters to deter- rupt flag code bits (EICODE<4:0>) in the CANSTAT mine if a message should be loaded into a receive buf- register will have a value of ‘10000’, indicating the fer. The mask essentially determines which bits to FIFO has received a message. FIFO Pointer bits, apply the acceptance filters to. If any mask bit is set to FP<3:0> in the CANCON register, point to the buffer a zero, then that bit will automatically be accepted that contains data not yet read. The FIFO Pointer bits, regardless of the filter bit. in this sense, serve as the FIFO Read Pointer. The user should use FP bits and read corresponding buffer data. TABLE 24-2: FILTER/MASK TRUTH TABLE When receive data is no longer needed, the RXFUL bit Message Accept or in the current buffer must be cleared, causing FP<3:0> Mask Filter Identifier Reject to be updated by the module. bit n bit n bit n001 bit n To determine whether FIFO is empty or not, the user may use the FP<3:0> bits to access the RXFUL bit in 0 x x Accept the current buffer. If RXFUL is cleared, the FIFO is con- 1 0 0 Accept sidered to be empty. If it is set, the FIFO may contain 1 0 1 Reject one or more messages. In Mode 2, the module also 1 1 0 Reject provides a bit called FIFO High Water Mark (FIFOWM) in the ECANCON register. This bit can be used to 1 1 1 Accept cause an interrupt whenever the FIFO contains only Legend: x = don’t care one or four empty buffers. The FIFO high water mark In Mode 0, acceptance filters, RXF0 and RXF1, and interrupt can serve as an early warning to a full FIFO filter mask, RXM0, are associated with RXB0. Filters, condition. RXF2, RXF3, RXF4 and RXF5, and mask, RXM1, are associated with RXB1. DS39637D-page 336 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 In Mode 1 and 2, there are an additional 10 acceptance The coding of the RXB0DBEN bit enables these three filters, RXF6-RXF15, creating a total of 16 available bits to be used similarly to the FILHIT bits and to distin- filters. RXF15 can be used either as an acceptance guish a hit on filter, RXF0 and RXF1, in either RXB0 or filter or acceptance mask register. Each of these after a rollover into RXB1. acceptance filters can be individually enabled or • 111 = Acceptance Filter 1 (RXF1) disabled by setting or clearing the RXFENn bit in the • 110 = Acceptance Filter 0 (RXF0) RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive • 001 = Acceptance Filter 1 (RXF1) buffers. Actual association is made by setting the • 000 = Acceptance Filter 0 (RXF0) appropriate bits in the RXFBCONn register. Each If the RXB0DBEN bit is clear, there are six codes RXFBCONn register contains a nibble for each filter. corresponding to the six filters. If the RXB0DBEN bit is This nibble can be used to associate a specific filter to set, there are six codes corresponding to the six filters, any of available receive buffers. User firmware may plus two additional codes corresponding to RXF0 and associate more than one filter to any one specific RXF1 filters, that rollover into RXB1. receive buffer. In Mode 1 and 2, each buffer control register contains In addition to dynamic filter to buffer association, in 5 bits of filter hit bits (FILHIT<4:0>). A binary value of ‘0’ Mode 1 and 2, each filter can also be dynamically asso- indicates a hit from RXF0 and 15 indicates RXF15. ciated to available Acceptance Mask registers. The If more than one acceptance filter matches, the FILHIT FILn_m bits in the MSELn register can be used to link bits will encode the binary value of the lowest num- a specific acceptance filter to an acceptance mask reg- bered filter that matched. In other words, if filter RXF2 ister. As with filter to buffer association, one can also and filter RXF4 match, FILHIT will be loaded with the associate more than one mask to a specific acceptance value for RXF2. This essentially prioritizes the filter. acceptance filters with a lower number filter having When a filter matches and a message is loaded into the higher priority. Messages are compared to filters in receive buffer, the filter number that enabled the mes- ascending order of filter number. sage reception is loaded into the FILHIT bit(s). In The mask and filter registers can only be modified Mode0 for RXB1, the RXB1CON register contains the when the PIC18F2480/2580/4480/4580 devices are in FILHIT<2:0> bits. They are coded as follows: Configuration mode. • 101 = Acceptance Filter 5 (RXF5) • 100 = Acceptance Filter 4 (RXF4) • 011 = Acceptance Filter 3 (RXF3) • 010 = Acceptance Filter 2 (RXF2) • 001 = Acceptance Filter 1 (RXF1) • 000 = Acceptance Filter 0 (RXF0) Note: ‘000’ and ‘001’ can only occur if the RXB0DBEN bit is set in the RXB0CON register, allowing RXB0 messages to rollover into RXB1. FIGURE 24-3: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register Acceptance Mask Register RXFn0 RXMn0 RXFn RXMn1 RxRqst 1 RXFn RXMn n n Message Assembly Buffer Identifier © 2009 Microchip Technology Inc. DS39637D-page 337

PIC18F2480/2580/4480/4580 24.9 Baud Rate Setting The Nominal Bit Time can be thought of as being divided into separate, non-overlapping time segments. All nodes on a given CAN bus must have the same These segments (Figure24-4) include: nominal bit rate. The CAN protocol uses Non-Return- • Synchronization Segment (Sync_Seg) to-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock • Propagation Time Segment (Prop_Seg) must be recovered by the receiving nodes and • Phase Buffer Segment 1 (Phase_Seg1) synchronized to the transmitter’s clock. • Phase Buffer Segment 2 (Phase_Seg2) As oscillators and transmission time may vary from The time segments (and thus, the Nominal Bit Time) node to node, the receiver must have some type of are, in turn, made up of integer units of time called Time Phase Lock Loop (PLL) synchronized to data transmis- Quanta or TQ (see Figure24-4). By definition, the sion edges to synchronize and maintain the receiver Nominal Bit Time is programmable from a minimum of clock. Since the data is NRZ coded, it is necessary to 8 TQ to a maximum of 25 TQ. Also by definition, the include bit stuffing to ensure that an edge occurs at minimum Nominal Bit Time is 1 μs, corresponding to a least every six bit times to maintain the Digital Phase maximum 1 Mb/s rate. The actual duration is given by Lock Loop (DPLL) synchronization. the following relationship. The bit timing of the PIC18F2480/2580/4480/4580 is implemented using a DPLL that is configured to syn- EQUATION 24-2: chronize to the incoming data and provides the nominal Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + timing for the transmitted data. The DPLL breaks each Phase_Seg1 + Phase_Seg2) bit time into multiple segments made up of minimal periods of time called the Time Quanta (TQ). The Time Quantum is a fixed unit derived from the Bus timing functions executed within the bit time frame, oscillator period. It is also defined by the programmable such as synchronization to the local oscillator, network baud rate prescaler, with integer values from 1 to 64, in transmission delay compensation and sample point addition to a fixed divide-by-two for clock generation. positioning, are defined by the programmable bit timing Mathematically, this is: logic of the DPLL. EQUATION 24-3: All devices on the CAN bus must use the same bit rate. However, all devices are not required to have the same TQ (μs) = (2 * (BRP+1))/FOSC (MHz) master oscillator clock frequency. For the different clock or frequencies of the individual devices, the bit rate has to TQ (μs) = (2 * (BRP+1)) * TOSC (μs) be adjusted by appropriately setting the baud rate prescaler and number of time quanta in each segment. where FOSC is the clock frequency, TOSC is the corresponding oscillator period and BRP is an integer The Nominal Bit Rate is the number of bits transmitted (0 through 63) represented by the binary values of per second, assuming an ideal transmitter with an ideal BRGCON1<5:0>. The equation above refers to the oscillator, in the absence of resynchronization. The effective clock frequency used by the microcontroller. If, nominal bit rate is defined to be a maximum of 1 Mb/s. for example, a 10MHz crystal in HS mode is used, then The Nominal Bit Time is defined as: FOSC=10MHz and TOSC=100ns. If the same 10MHz crystal is used in HS-PLL mode, then the effective EQUATION 24-1: frequency is FOSC=40MHz and TOSC=25ns. TBIT = 1/Nominal Bit Rate FIGURE 24-4: BIT TIME PARTITIONING Input Signal Bit SSyynncc Propagation Phase Phase Segment Segment Segment 1 Segment 2 Time Intervals TQ Sample Point Nominal Bit Time DS39637D-page 338 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.9.1 EXTERNAL CLOCK, INTERNAL The CAN protocol uses a bit-stuffing technique that CLOCK AND MEASURABLE JITTER inserts a bit of a given polarity following five bits with the IN HS-PLL BASED OSCILLATORS opposite polarity. This gives a total of 10 bits transmit- ted without re-synchronization (compensation for jitter The microcontroller clock frequency generated from a or phase error). PLL circuit is subject to a jitter, also defined as Phase Jitter or Phase Skew. For its PIC18 Enhanced micro- Given the random nature of the jitter error added, it can controllers, Microchip specifies phase jitter (P ) as be shown that the total error caused by the jitter tends jitter being 2% (Gaussian distribution, within 3 standard to cancel itself over time. For a period of 10 bits, it is deviations, see parameter F13 in Table28-7) and Total necessary to add only two jitter intervals to correct for Jitter (T ) as being 2*P . jitter-induced error: one interval in the beginning of the jitter jitter 10-bit period and another at the end. The overall effect is shown in Figure24-5. FIGURE 24-5: EFFECTS OF PHASE JITTER ON THE MICROCONTROLLER CLOCK AND CAN BIT TIME Nominal Clock Clock with Jitter Phase Skew (Jitter) CAN Bit Time with Jitter CAN Bit Jitter Once these considerations are taken into account, it is For example, assume a CAN bit rate of 125Kb/s, which possible to show that the relation between the jitter and gives an NBT of 8µs. For a 16MHz clock generated the total frequency error can be defined as: from a 4x PLL, the jitter at this clock frequency is: T 2×P 1 0.02 Δf = ----------j-i--t-t-e--r-------= ---------------j-i--t-t-e--r-- 2%×1---6--- --M-----H-----z- = ----------------6- = 1.25ns 10×NBT 10×NBT 16×10 and resultant frequency error is: where jitter is expressed in terms of time and NBT is the Nominal Bit Time. 2×(1.25×10–9) –5 ---------------------------------------= 3.125×10 = 0.0031% –6 10×(8×10 ) © 2009 Microchip Technology Inc. DS39637D-page 339

PIC18F2480/2580/4480/4580 Table24-3 shows the relation between the clock This is clearly smaller than the expected drift of a generated by the PLL and the frequency error from crystal oscillator, typically specified at 100ppm or jitter (measured jitter-induced error of 2%, Gaussian 0.01%. If we add jitter to oscillator drift, we have a total distribution, within 3 standard deviations), as a frequency drift of 0.0132%. The total oscillator percentage of the nominal clock frequency. frequency errors for common clock frequencies and bit rates, including both drift and jitter, are shown in Table24-4. TABLE 24-3: FREQUENCY ERROR FROM JITTER AT VARIOUS PLL-GENERATED CLOCK SPEEDS Frequency Error at Various Nominal Bit Times (Bit Rates) PLL P T Output jitter jitter 8μs 4μs 2μs 1μs (125Kb/s) (250Kb/s) (500Kb/s) (1Mb/s) 40MHz 0.5ns 1ns 0.00125% 0.00250% 0.005% 0.01% 24MHz 0.83ns 1.67ns 0.00209% 0.00418% 0.008% 0.017% 16MHz 1.25ns 2.5ns 0.00313% 0.00625% 0.013% 0.025% TABLE 24-4: TOTAL FREQUENCY ERROR AT VARIOUS PLL-GENERATED CLOCK SPEEDS (100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER) Frequency Error at Various Nominal Bit Times (Bit Rates) Nominal PLL Output 8μs 4μs 2μs 1μs (125Kb/s) (250Kb/s) (500Kb/s) (1Mb/s) 40MHz 0.01125% 0.01250% 0.015% 0.02% 24MHz 0.01209% 0.01418% 0.018% 0.027% 16MHz 0.01313% 0.01625% 0.023% 0.035% DS39637D-page 340 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.9.2 TIME QUANTA 24.9.3 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit This part of the bit time is used to synchronize the derived from the oscillator period and baud rate various CAN nodes on the bus. The edge of the input prescaler. Its relationship to TBIT and the Nominal Bit signal is expected to occur during the sync segment. Rate is shown in Example24-6. The duration is 1 TQ. EXAMPLE 24-6: CALCULATING TQ, 24.9.4 PROPAGATION SEGMENT NOMINAL BIT RATE AND This part of the bit time is used to compensate for phys- NOMINAL BIT TIME ical delay times within the network. These delay times consist of the signal propagation time on the bus line TQ (μs) = (2 * (BRP+1))/FOSC (MHz) and the internal delay time of the nodes. The length of TBIT (μs) = TQ (μs) * number of TQ per bit interval the propagation segment can be programmed from Nominal Bit Rate (bits/s) = 1/TBIT 1TQ to 8 TQ by setting the PRSEG<2:0> bits. This frequency (FOSC) refers to the effective 24.9.5 PHASE BUFFER SEGMENTS frequency used. If, for example, a 10MHz external signal is used along with a PLL, then the effective The phase buffer segments are used to optimally frequency will be 4 x 10MHz which equals 40MHz. locate the sampling point of the received bit within the nominal bit time. The sampling point occurs between Phase Segment 1 and Phase Segment 2. These CASE 1: segments can be lengthened or shortened by the For FOSC = 16 MHz, BRP<5:0> = 00h and resynchronization process. The end of Phase Nominal Bit Time = 8 TQ: Segment1 determines the sampling point within a bit time. Phase Segment 1 is programmable from 1 TQ to TQ = (2 * 1)/16 = 0.125μs (125ns) 8 TQ in duration. Phase Segment 2 provides a delay TBIT = 8 * 0.125 = 1μs (10-6s) before the next transmitted data transition and is also Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s) programmable from 1 TQ to 8 TQ in duration. However, due to IPT requirements, the actual minimum length of Phase Segment 2 is 2 TQ, or it may be defined to be CASE 2: equal to the greater of Phase Segment 1 or the Information Processing Time (IPT). The sampling point For FOSC = 20 MHz, BRP<5:0> = 01h and should be as late as possible or approximately 80% of Nominal Bit Time = 8 TQ: the bit time. TQ = (2 * 2)/20 = 0.2μs (200ns) TBIT = 8 * 0.2 = 1.6μs (1.6 * 10-6s) 24.9.6 SAMPLE POINT Nominal Bit Rate = 1/1.6 * 10-6s = 625,000bits/s The sample point is the point of time at which the bus (625Kb/s) level is read and the value of the received bit is deter- mined. The sampling point occurs at the end of Phase Segment1. If the bit timing is slow and contains many CASE 3: TQ, it is possible to specify multiple sampling of the bus line at the sample point. The value of the received bit is For FOSC = 25 MHz, BRP<5:0> = 3Fh and determined to be the value of the majority decision of Nominal Bit Time = 25 TQ: three values. The three samples are taken at the sam- TQ = (2 * 64)/25 = 5.12μs ple point and twice before, with a time of TQ/2 between TBIT = 25 * 5.12 = 128μs (1.28 * 10-4s) each sample. Nominal Bit Rate = 1/1.28 * 10-4 = 7813 bits/s 24.9.7 INFORMATION PROCESSING TIME (7.8Kb/s) The Information Processing Time (IPT) is the time segment starting at the sample point that is reserved The frequencies of the oscillators in the different nodes for calculation of the subsequent bit level. The CAN must be coordinated in order to provide a system wide specification defines this time to be less than or equal specified nominal bit time. This means that all oscilla- to 2TQ. The PIC18F2480/2580/4480/4580 devices tors must have a TOSC that is an integral divisor of TQ. define this time to be 2TQ. Thus, Phase Segment 2 It should also be noted that although the number of TQ must be at least 2 TQ long. is programmable from 4 to 25, the usable minimum is 8TQ. There is no assurance that a bit time of less than 8 TQ in length will operate correctly. © 2009 Microchip Technology Inc. DS39637D-page 341

PIC18F2480/2580/4480/4580 24.10 Synchronization The phase error of an edge is given by the position of the edge relative to Sync_Seg, measured in TQ. The To compensate for phase shifts between the oscillator phase error is defined in magnitude of TQ as follows: frequencies of each of the nodes on the bus, each CAN • e = 0 if the edge lies within Sync_Seg. controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in • e > 0 if the edge lies before the sample point. the transmitted data is detected, the logic will compare • e < 0 if the edge lies after the sample point of the the location of the edge to the expected time previous bit. (Sync_Seg). The circuit will then adjust the values of If the magnitude of the phase error is less than, or equal Phase Segment 1 and Phase Segment 2 as necessary. to, the programmed value of the Synchronization Jump There are two mechanisms used for synchronization. Width, the effect of a resynchronization is the same as that of a hard synchronization. 24.10.1 HARD SYNCHRONIZATION If the magnitude of the phase error is larger than the Hard synchronization is only done when there is a Synchronization Jump Width and if the phase error is recessive to dominant edge during a bus Idle condition, positive, then Phase Segment 1 is lengthened by an indicating the start of a message. After hard synchroni- amount equal to the Synchronization Jump Width. zation, the bit time counters are restarted with Sync_Seg. Hard synchronization forces the edge, If the magnitude of the phase error is larger than the which has occurred to lie within the synchronization resynchronization jump width and if the phase error is segment of the restarted bit time. Due to the rules of negative, then Phase Segment 2 is shortened by an synchronization, if a hard synchronization occurs, there amount equal to the Synchronization Jump Width. will not be a resynchronization within that bit time. 24.10.3 SYNCHRONIZATION RULES 24.10.2 RESYNCHRONIZATION • Only one synchronization within one bit time is As a result of resynchronization, Phase Segment 1 allowed. may be lengthened or Phase Segment 2 may be short- • An edge will be used for synchronization only if ened. The amount of lengthening or shortening of the the value detected at the previous sample point phase buffer segments has an upper bound given by (previously read bus value) differs from the bus the Synchronization Jump Width (SJW). The value of value immediately after the edge. the SJW will be added to Phase Segment 1 (see • All other recessive to dominant edges fulfilling Figure24-6) or subtracted from Phase Segment 2 (see rules 1 and 2 will be used for resynchronization, Figure24-7). The SJW is programmable between 1 TQ with the exception that a node transmitting a and 4 TQ. dominant bit will not perform a resynchronization Clocking information will only be derived from reces- as a result of a recessive to dominant edge with a sive to dominant transitions. The property, that only a positive phase error. fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. DS39637D-page 342 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 24-6: LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1) Input Signal Bit Prop Phase Phase Time Sync Segment Segment 1 ≤ SJW Segment 2 Segments TQ Sample Point Nominal Bit Length Actual Bit Length FIGURE 24-7: SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Phase Phase Sync Segment Segment 1 Segment 2 ≤ SJW TQ Sample Point Actual Bit Length Nominal Bit Length 24.11 Programming Time Segments By the rules above, the Sync Jump Width could be the maximum of 4 TQ. However, normally a large SJW is Some requirements for programming of the time only necessary when the clock generation of the segments: different nodes is inaccurate or unstable, such as using • Prop_Seg + Phase_Seg 1 ≥ Phase_Seg 2 ceramic resonators. Typically, an SJW of 1 is enough. • Phase_Seg 2 ≥ Sync Jump Width. 24.12 Oscillator Tolerance For example, assume that a 125 kHz CAN baud rate is desired, using 20MHz for FOSC. With a TOSC of 50 ns, As a rule of thumb, the bit timing requirements allow a baud rate prescaler value of 04h gives a TQ of 500ns. ceramic resonators to be used in applications with To obtain a Nominal Bit Rate of 125 kHz, the Nominal transmission rates of up to 125 Kbit/sec. For the full bus Bit Time must be 8μs or 16 TQ. speed range of the CAN protocol, a quartz oscillator is Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Seg required. Refer to ISO11898-1 for oscillator tolerance and 7 TQ for Phase Segment 1 would place the sample requirements. point at 10 TQ after the transition. This leaves 6 TQ for Phase Segment 2. © 2009 Microchip Technology Inc. DS39637D-page 343

PIC18F2480/2580/4480/4580 24.13 Bit Timing Configuration 24.14.2 ACKNOWLEDGE ERROR Registers In the Acknowledge field of a message, the transmitter checks if the Acknowledge slot (which was sent out as The Baud Rate Control registers (BRGCON1, a recessive bit) contains a dominant bit. If not, no other BRGCON2, BRGCON3) control the bit timing for the node has received the frame correctly. An Acknowl- CAN bus interface. These registers can only be modi- edge error has occurred, an error frame is generated fied when the PIC18F2480/2580/4480/4580 devices and the message will have to be repeated. are in Configuration mode. 24.14.3 FORM ERROR 24.13.1 BRGCON1 If a node detects a dominant bit in one of the four seg- The BRP bits control the baud rate prescaler. The ments, including End-Of-Frame (EOF), interframe SJW<1:0> bits select the synchronization jump width in space, Acknowledge delimiter or CRC delimiter, then a terms of multiples of TQ. form error has occurred and an error frame is 24.13.2 BRGCON2 generated. The message is repeated. The PRSEG bits set the length of the propagation seg- 24.14.4 BIT ERROR ment in terms of TQ. The SEG1PH bits set the length of A bit error occurs if a transmitter sends a dominant bit Phase Segment 1 in TQ. The SAM bit controls how and detects a recessive bit, or if it sends a recessive bit many times the RXCAN pin is sampled. Setting this bit and detects a dominant bit, when monitoring the actual to a ‘1’ causes the bus to be sampled three times: twice bus level and comparing it to the just transmitted bit. In at TQ/2 before the sample point and once at the normal the case where the transmitter sends a recessive bit sample point (which is at the end of Phase Segment 1). and a dominant bit is detected during the arbitration The value of the bus is determined to be the value read field and the Acknowledge slot, no bit error is during at least two of the samples. If the SAM bit is set generated because normal arbitration is occurring. to a ‘0’, then the RXCAN pin is sampled only once at the sample point. The SEG2PHTS bit controls how the 24.14.5 STUFF BIT ERROR length of Phase Segment 2 is determined. If this bit is set to a ‘1’, then the length of Phase Segment 2 is lf, between the Start-Of-Frame (SOF) and the CRC determined by the SEG2PH bits of BRGCON3. If the delimiter, six consecutive bits with the same polarity are SEG2PHTS bit is set to a ‘0’, then the length of Phase detected, the bit stuffing rule has been violated. A stuff Segment 2 is the greater of Phase Segment 1 and the bit error occurs and an error frame is generated. The information processing time (which is fixed at 2 TQ for message is repeated. the PIC18F2480/2580/4480/4580). 24.14.6 ERROR STATES 24.13.3 BRGCON3 Detected errors are made public to all other nodes via The PHSEG2<2:0> bits set the length (in TQ) of Phase error frames. The transmission of the erroneous mes- Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the sage is aborted and the frame is repeated as soon as SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0> possible. Furthermore, each CAN node is in one of the bits have no effect. three error states; “error-active”, “error-passive” or “bus-off”, according to the value of the internal error 24.14 Error Detection counters. The error-active state is the usual state where the bus node can transmit messages and acti- The CAN protocol provides sophisticated error vate error frames (made of dominant bits) without any detection mechanisms. The following errors can be restrictions. In the error-passive state, messages and detected. passive error frames (made of recessive bits) may be transmitted. The bus-off state makes it temporarily 24.14.1 CRC ERROR impossible for the node to participate in the bus With the Cyclic Redundancy Check (CRC), the trans- communication. During this state, messages can neither mitter calculates special check bits for the bit be received nor transmitted. sequence, from the start of a frame until the end of the 24.14.7 ERROR MODES AND ERROR data field. This CRC sequence is transmitted in the COUNTERS CRC field. The receiving node also calculates the CRC sequence using the same formula and performs a The PIC18F2480/2580/4480/4580 devices contain two comparison to the received sequence. If a mismatch is error counters: the Receive Error Counter (RXERRCNT) detected, a CRC error has occurred and an error frame and the Transmit Error Counter (TXERRCNT). The is generated. The message is repeated. values of both counters can be read by the MCU. These counters are incremented or decremented in accordance with the CAN bus specification. DS39637D-page 344 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 The PIC18F2480/2580/4480/4580 devices are error- the MCU if the bus remains Idle for 128 x 11 bit times. active if both error counters are below the error-passive If this is not desired, the error Interrupt Service Routine limit of 128. They are error-passive if at least one of the should address this. The current Error mode of the error counters equals or exceeds 128. They go to bus- CAN module can be read by the MCU via the off if the transmit error counter equals or exceeds the COMSTAT register. bus-off limit of 256. The devices remain in this state Additionally, there is an Error State Warning flag bit, until the bus-off recovery sequence is finished. The EWARN, which is set if at least one of the error coun- bus-off recovery sequence consists of 128 occurrences ters equals or exceeds the error warning limit of 96. of 11 consecutive recessive bits (see Figure24-8). EWARN is reset if both error counters are less than the Note that the CAN module, after going bus-off, will error warning limit. recover back to error-active without any intervention by FIGURE 24-8: ERROR MODES STATE DIAGRAM Reset Error- RXERRCNT < 128 or TXERRCNT < 128 Active 128 occurrences of 11 consecutive “recessive” bits RXERRCNT ≥ 128 or TXERRCNT ≥ 128 Error- Passive TXERRCNT > 255 Bus- Off 24.15 CAN Interrupts The interrupts can be broken up into two categories: receive and transmit interrupts. The module has several sources of interrupts. Each of The receive related interrupts are: these interrupts can be individually enabled or dis- abled. The PIR3 register contains interrupt flags. The • Receive Interrupts PIE3 register contains the enables for the 8 main inter- • Wake-up Interrupt rupts. A special set of read-only bits in the CANSTAT • Receiver Overrun Interrupt register, the ICODE bits, can be used in combination • Receiver Warning Interrupt with a jump table for efficient handling of interrupts. • Receiver Error-Passive Interrupt All interrupts have one source, with the exception of the error interrupt and buffer interrupts in Mode 1 and 2. Any The transmit related interrupts are: of the error interrupt sources can set the error interrupt • Transmit Interrupts flag. The source of the error interrupt can be determined • Transmitter Warning Interrupt by reading the Communication Status register, • Transmitter Error-Passive Interrupt COMSTAT. In Mode 1 and 2, there are two interrupt • Bus-Off Interrupt enable/disable and flag bits – one for all transmit buffers and the other for all receive buffers. © 2009 Microchip Technology Inc. DS39637D-page 345

PIC18F2480/2580/4480/4580 24.15.1 INTERRUPT CODE BITS TABLE 24-5: VALUES FOR ICODE<2:0> To simplify the interrupt handling process in user firm- ICODE Interrupt Boolean Expression ware, the ECAN module encodes a special set of bits. In <2:0> Mode0, these bits are ICODE<3:1> in the CANSTAT register. In Mode 1 and 2, these bits are EICODE<4:0> in 000 None ERR•WAK•TX0•TX1•TX2•RX0•RX1 the CANSTAT register. Interrupts are internally prioritized such that the higher priority interrupts are assigned lower 001 Error ERR values. Once the highest priority interrupt condition has been cleared, the code for the next highest priority inter- 010 TXB2 ERR•TX0•TX1•TX2 rupt that is pending (if any) will be reflected by the ICODE bits (see Table24-5). Note that only those interrupt 011 TXB1 ERR•TX0•TX1 sources that have their associated interrupt enable bit set will be reflected in the ICODE bits. 100 TXB0 ERR•TX0 In Mode 2, when a receive message interrupt occurs, 101 RXB1 ERR•TX0•TX1•TX2•RX0•RX1 the EICODE bits will always consist of ‘10000’. User firmware may use FIFO Pointer bits to actually access 110 RXB0 ERR•TX0•TX1•TX2•RX0 the next available buffer. Wake on 24.15.2 TRANSMIT INTERRUPT 111 Interrupt ERR•TX0•TX1•TX2•RX0•RX1•WAK When the transmit interrupt is enabled, an interrupt will Legend: be generated when the associated transmit buffer ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE becomes empty and is ready to be loaded with a new TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE message. In Mode 0, there are separate interrupt enable/ TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE disable and flag bits for each of the three dedicated trans- TX2 = TXB2IF * TXB2IE mit buffers. The TXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the MCU, resetting the TXBnIF bit to a ‘0’. In Mode 1 and 2, 24.15.4 MESSAGE ERROR INTERRUPT all transmit buffers share one interrupt enable/disable bit When an error occurs during transmission or reception and one flag bit. In Mode 1 and 2, TXBIE in PIE3 and of a message, the message error flag, IRXIF, will be set TXBIF in PIR3 indicate when a transmit buffer has com- and if the IRXIE bit is set, an interrupt will be generated. pleted transmission of its message. TXBnIF, TXBnIE and This is intended to be used to facilitate baud rate TXBnIP in PIR3, PIE3 and IPR3, respectively, are not determination when used in conjunction with Listen used in Mode 1 and 2. Individual transmit buffer interrupts Only mode. can be enabled or disabled by setting or clearing TXBIE and B0IE register bits. When a shared interrupt occurs, 24.15.5 BUS ACTIVITY WAKE-UP user firmware must poll the TXREQ bit of all transmit INTERRUPT buffers to detect the source of interrupt. When the PIC18F2480/2580/4480/4580 devices are in 24.15.3 RECEIVE INTERRUPT Sleep mode and the bus activity wake-up interrupt is enabled, an interrupt will be generated and the WAKIF When the receive interrupt is enabled, an interrupt will bit will be set when activity is detected on the CAN bus. be generated when a message has been successfully This interrupt causes the PIC18F2480/2580/4480/ received and loaded into the associated receive buffer. 4580 devices to exit Sleep mode. The interrupt is reset This interrupt is activated immediately after receiving by the MCU, clearing the WAKIF bit. the End-Of-Frame (EOF) field. In Mode 0, the RXBnIF bit is set to indicate the source 24.15.6 ERROR INTERRUPT of the interrupt. The interrupt is cleared by the MCU, When the CAN module error interrupt (ERRIE in PIE3) resetting the RXBnIF bit to a ‘0’. is enabled, an interrupt is generated if an overflow con- In Mode 1 and 2, all receive buffers share RXBIE, dition occurs, or if the error state of the transmitter or RXBIF and RXBIP in PIE3, PIR3 and IPR3, respec- receiver has changed. The error flags in COMSTAT will tively. Bits, RXBnIE, RXBnIF and RXBnIP, are not indicate one of the following conditions. used. Individual receive buffer interrupts can be con- trolled by the TXBIE and BIE0 registers. In Mode 1, when a shared receive interrupt occurs, user firmware must poll the RXFUL bit of each receive buffer to detect the source of interrupt. In Mode 2, a receive interrupt indicates that the new message is loaded into FIFO. FIFO can be read by using FIFO Pointer bits, FP. DS39637D-page 346 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 24.15.6.1 Receiver Overflow 24.15.6.3 Transmitter Warning An overflow condition occurs when the MAB has The transmit error counter has reached the MCU assembled a valid received message (the message warning limit of 96. meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available 24.15.6.4 Receiver Bus Passive for loading of a new message. The associated This will occur when the device has gone to the error- RXBnOVFL bit in the COMSTAT register will be set to passive state because the receive error counter is indicate the overflow condition. This bit must be cleared greater or equal to 128. by the MCU. 24.15.6.5 Transmitter Bus Passive 24.15.6.2 Receiver Warning This will occur when the device has gone to the error- The receive error counter has reached the MCU passive state because the transmit error counter is warning limit of 96. greater or equal to 128. 24.15.6.6 Bus-Off The transmit error counter has exceeded 255 and the device has gone to bus-off state. © 2009 Microchip Technology Inc. DS39637D-page 347

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 348 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 25.0 SPECIAL FEATURES OF The inclusion of an internal RC oscillator also provides THE CPU the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for PIC18F2480/2580/4480/4580 devices include several background monitoring of the peripheral clock and features intended to maximize reliability and minimize automatic switchover in the event of its failure. Two- cost through elimination of external components. Speed Start-up enables code to be executed almost These are: immediately on start-up, while the primary clock source completes its start-up delays. • Oscillator Selection All of these features are enabled and configured by • Resets: setting the appropriate Configuration register bits. - Power-on Reset (POR) - Power-up Timer (PWRT) 25.1 Configuration Bits - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various • Interrupts device configurations. These bits are mapped starting • Watchdog Timer (WDT) at program memory location 300000h. • Fail-Safe Clock Monitor The user will note that address 300000h is beyond the • Two-Speed Start-up user program memory space. In fact, it belongs to the • Code Protection configuration memory space (300000h-3FFFFFh), which • ID Locations can only be accessed using table reads and table writes. • In-Circuit Serial Programming Programming the Configuration registers is done in a The oscillator can be configured for the application manner similar to programming the Flash memory. The depending on frequency, power, accuracy and cost. All WR bit in the EECON1 register starts a self-timed write of the options are discussed in detail in Section3.0 to the Configuration register. In normal operation “Oscillator Configurations”. mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the A complete discussion of device Resets and interrupts data for the Configuration register write. Setting the WR is available in previous sections of this data sheet. bit starts a long write to the Configuration register. The In addition to their Power-up and Oscillator Start-up Configuration registers are written a byte at a time. To Timers provided for Resets, PIC18F2480/2580/4480/ write or erase a configuration cell, a TBLWT instruction 4580 devices have a Watchdog Timer, which is either can write a ‘1’ or a ‘0’ into the cell. For additional details permanently enabled via the Configuration bits or on Flash programming, refer to Section7.5 “Writing software controlled (if configured as disabled). to Flash Program Memory”. TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN — 1--- -01- 300006h CONFIG4L DEBUG XINST — BBSIZ — LVP — STVREN 10-0 -1-1 300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: See Register25-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. © 2009 Microchip Technology Inc. DS39637D-page 349

PIC18F2480/2580/4480/4580 REGISTER 25-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator DS39637D-page 350 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 25-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1 BORV0 BOREN1(1) BOREN0(1) PWRTEN(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits 11 = VBOR set to 2.1V 10 = VBOR set to 2.8V 01 = VBOR set to 4.3V 00 = VBOR set to 4.6V bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. © 2009 Microchip Technology Inc. DS39637D-page 351

PIC18F2480/2580/4480/4580 REGISTER 25-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) DS39637D-page 352 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 25-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 U-0 MCLRE — — — — LPT1OSC PBADEN — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Read as ‘0’ bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 Unimplemented: Read as ‘0’ REGISTER 25-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 U-0 R/P-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST — BBSIZ — LVP — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5 Unimplemented: Read as ‘0’ bit 4 BBSIZ: Boot Block Size Select Bit 0 01 = 2K words (4 Kbytes) boot block 00 = 1K words (2 Kbytes) boot block bit 3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP™ Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset © 2009 Microchip Technology Inc. DS39637D-page 353

PIC18F2480/2580/4480/4580 REGISTER 25-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) not code-protected 0 = Block 3 (006000-007FFFh) code-protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code-protected 0 = Block 2 (004000-005FFFh) code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) not code-protected 0 = Block 1 (002000-003FFFh) code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000800-001FFFh) not code-protected 0 = Block 0 (000800-001FFFh) code-protected Note 1: Unimplemented in PIC18FX480 devices; maintain this bit set. REGISTER 25-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0007FFh) not code-protected 0 = Boot Block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ DS39637D-page 354 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 25-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (006000-007FFFh) not write-protected 0 = Block 3 (006000-007FFFh) write-protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 (004000-005FFFh) not write-protected 0 = Block 2 (004000-005FFFh) write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) not write-protected 0 = Block 1 (002000-003FFFh) write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 (000800-001FFFh) not write-protected 0 = Block 0 (000800-001FFFh) write-protected Note 1: Unimplemented in PIC18FX480 devices; maintain this bit set. REGISTER 25-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block (000000-0007FFh) not write-protected 0 = Boot Block (000000-0007FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode. © 2009 Microchip Technology Inc. DS39637D-page 355

PIC18F2480/2580/4480/4580 REGISTER 25-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1,2) EBTR2(1,2) EBTR1(2) EBTR0(2) bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1,2) 1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks 0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1,2) 1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks 0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit(2) 1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks 0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit(2) 1 = Block 0 (000800-001FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800-001FFFh) protected from table reads executed in other blocks Note 1: Unimplemented in PIC18FX480 devices; maintain this bit set. 2: It is recommended to enable the corresponding CPx bit to protect the block from external read operations. REGISTER 25-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB(1) — — — — — — bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit(1) 1 = Boot Block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot Block (000000-0007FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Note 1: It is recommended to enable the corresponding CPx bit to protect the block from external read operations. DS39637D-page 356 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 25-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2480/2580/4480/4580 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits 111 = PIC18F2480 110 = PIC18F2580 101 = PIC18F4480 100 = PIC18F4580 bit 4-0 REV<3:0>: Revision ID bits These bits are used to indicate the device revision. REGISTER 25-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2480/2580/4480/4580 R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-0 DEV<10:3>: Device ID bits These bits are used with the DEV<2:0> bits in Device ID Register 1 to identify the part number. 0001 1010 = PIC18F2480/2580/4480/4580 devices Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence. © 2009 Microchip Technology Inc. DS39637D-page 357

PIC18F2480/2580/4480/4580 25.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For PIC18F2480/2580/4480/4580 devices, the WDT is when executed. driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal 2: Changing the setting of the IRCF bits WDT period is 4ms and has the same stability as the (OSCCON<6:4>) clears the WDT and INTRC oscillator. postscaler counts. The 4ms period of the WDT is multiplied by a 16-bit 3: When a CLRWDT instruction is executed, postscaler. Any output of the WDT postscaler is the postscaler count will be cleared. selected by a multiplexer, controlled by bits in Configu- ration Register 2H. Available periods range from 4ms 25.2.1 CONTROL REGISTER to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events Register25-14 shows the WDTCON register. This is a occur: a SLEEP or CLRWDT instruction is executed, the readable and writable register which contains a control IRCF bits (OSCCON<6:4>) are changed or a clock bit that allows software to override the WDT enable failure has occurred. Configuration bit, but only if the Configuration bit has disabled the WDT. . FIGURE 25-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT INTRC Control WDTEN WDT Counter INTRC Source ÷128 Wake-up from Power Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets WDT 4 WDTPS<3:0> Sleep DS39637D-page 358 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 REGISTER 25-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 25-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: RCON IPEN SBOREN — RI TO PD POR BOR 54 WDTCON — — — — — — — SWDTEN 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. © 2009 Microchip Technology Inc. DS39637D-page 359

PIC18F2480/2580/4480/4580 25.3 Two-Speed Start-up Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the The Two-Speed Start-up feature helps to minimize the IRCF2:IRCF0 bits prior to entering Sleep mode. latency period from oscillator start-up to code execution In all other power-managed modes, Two-Speed Start-up by allowing the microcontroller to use the INTRC is not used. The device will be clocked by the currently oscillator as a clock source until the primary clock selected clock source until the primary clock source source is available. It is enabled by setting the IESO becomes available. The setting of the IESO bit is Configuration bit. ignored. Two-Speed Start-up should be enabled only if the primary oscillator mode is LP, XT, HS or HSPLL (Crystal- 25.3.1 SPECIAL CONSIDERATIONS FOR Based modes). Other sources do not require an USING TWO-SPEED START-UP Oscillator Start-up Timer delay; for these, Two-Speed While using the INTRC oscillator in Two-Speed Start-up, Start-up should be disabled. the device still obeys the normal command sequences When enabled, Resets and wake-ups from Sleep mode for entering power-managed modes, including serial cause the device to configure itself to run from the SLEEP instructions (refer to Section4.1.4 “Multiple internal oscillator block as the clock source, following Sleep Commands”). In practice, this means that user the time-out of the Power-up Timer after a Power-on code can change the SCS<1:0> bit settings or issue Reset is enabled. This allows almost immediate code SLEEP instructions before the OST times out. This would execution while the primary oscillator starts and the allow an application to briefly wake-up, perform routine OST is running. Once the OST times out, the device “housekeeping” tasks and return to Sleep before the automatically switches to PRI_RUN mode. device starts to operate from the primary oscillator. Because the OSCCON register is cleared on Reset User code can also check if the primary clock source is events, the INTOSC (or postscaler) clock source is not currently providing the device clocking by checking the initially available after a Reset event; the INTRC clock status of the OSTS bit (OSCCON<3>). If the bit is set, is used directly at its base frequency. To use a higher the primary oscillator is providing the clock. Otherwise, clock speed on wake-up, the INTOSC or postscaler the internal oscillator block is providing the clock during clock sources can be selected to provide a higher clock wake-up from Reset or Sleep mode. speed by setting bits, IRCF<2:0>, immediately after FIGURE 25-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake from Interrupt Event OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39637D-page 360 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 25.4 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits, IRCF<2:0>, microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting the IRCF<2:0> bits prior to entering Sleep function is enabled by setting the FCMEN Configuration mode. bit. The FSCM will detect failures of the primary or second- When FSCM is enabled, the INTRC oscillator runs at ary clock sources only. If the internal oscillator block all times to monitor clocks to peripherals and provide a fails, no failure would be detected, nor would any action backup clock in the event of a clock failure. Clock be possible. monitoring (shown in Figure25-3) is accomplished by creating a sample clock signal, which is the INTRC out- 25.4.1 FSCM AND THE WATCHDOG TIMER put divided by 64. This allows ample time between Both the FSCM and the WDT are clocked by the FSCM sample clocks for a peripheral clock edge to INTRC oscillator. Since the WDT operates with a occur. The peripheral device clock and the sample separate divider and counter, disabling the WDT has clock are presented as inputs to the Clock Monitor no effect on the operation of the INTRC oscillator when (CM) latch. The CM is set on the falling edge of the the FSCM is enabled. device clock source, but cleared on the rising edge of the sample clock. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. FIGURE 25-3: FSCM BLOCK DIAGRAM Depending on the frequency selected by the IRCF<2:0> bits, this may mean a substantial change in Clock Monitor the speed of code execution. If the WDT is enabled Latch (CM) (edge-triggered) with a small prescale value, a decrease in clock speed Peripheral allows a WDT time-out to occur and a subsequent S Q Clock device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and INTRC decreasing the likelihood of an erroneous time-out. ÷ 64 C Q Source 25.4.2 EXITING FAIL-SAFE OPERATION (32 μs) 488 Hz (2.048 ms) The Fail-Safe condition is terminated by either a device Reset or by entering a power-managed mode. On Clock Reset, the controller starts the primary clock source Failure specified in Configuration Register 1H (with any Detected required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The Clock failure is tested for on the falling edge of the INTOSC multiplexer provides the device clock until the sample clock. If a sample clock falling edge occurs primary clock source becomes ready (similar to a Two- while CM is still set, a clock failure has been detected Speed Start-up). The clock source is then switched to (Figure25-4). This causes the following: the primary clock (indicated by the OSTS bit in the • the FSCM generates an oscillator fail interrupt by OSCCON register becoming set). The Fail-Safe Clock setting bit, OSCFIF (PIR2<7>); Monitor then resumes monitoring the peripheral clock. • the device clock source is switched to the internal The primary clock source may never become ready oscillator block (OSCCON is not updated to show during start-up. In this case, operation is clocked by the the current clock source – this is the Fail-Safe INTOSC multiplexer. The OSCCON register will remain condition); and in its Reset state until a power-managed mode is • the WDT is reset. entered. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing-sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shut- down. See Section4.1.4 “Multiple Sleep Commands” and Section25.3.1 “Special Considerations for Using Two-Speed Start-up” for more details. © 2009 Microchip Technology Inc. DS39637D-page 361

PIC18F2480/2580/4480/4580 FIGURE 25-4: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 25.4.3 FSCM INTERRUPTS IN For oscillator modes involving a crystal or resonator POWER-MANAGED MODES (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up By entering a power-managed mode, the clock time considerably longer than the FCSM sample clock multiplexer selects the clock source selected by the time, a false clock failure may be detected. To prevent OSCCON register. Fail-Safe Clock Monitoring of this, the internal oscillator block is automatically thepower-managed clock source resumes in the configured as the device clock and functions until the power-managed mode. primary clock is stable (the OST and PLL timers have If an oscillator failure occurs during power-managed timed out). This is identical to Two-Speed Start-up operation, the subsequent events depend on whether mode. Once the primary clock is stable, the INTRC or not the oscillator failure interrupt is enabled. If returns to its role as the FSCM source. enabled (OSCFIF=1), code execution will be clocked Note: The same logic that prevents false oscilla- by the INTOSC multiplexer. An automatic transition tor failure interrupts on POR, or wake from back to the failed clock source will not occur. Sleep, will also prevent the detection of If the interrupt is disabled, subsequent interrupts while the oscillator’s failure to start at all follow- in Idle mode will cause the CPU to begin executing ing these events. This can be avoided by instructions while being clocked by the INTOSC monitoring the OSTS bit and using a source. timing routine to determine if the oscillator is taking too long to start. Even so, no 25.4.4 POR OR WAKE-UP FROM SLEEP oscillator failure interrupt will be flagged. The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset As noted in Section25.3.1 “Special Considerations (POR) or low-power Sleep mode. When the primary for Using Two-Speed Start-up”, it is also possible to device clock is EC, RC or INTRC modes, monitoring select another clock configuration and enter an alternate can begin immediately following these events. power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. DS39637D-page 362 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 25.5 Program Verification and Each of the five blocks has three code protection bits Code Protection associated with them. They are: • Code-Protect bit (CPn) The overall structure of the code protection on the • Write-Protect bit (WRTn) PIC18 Flash devices differs significantly from other PIC® devices. • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. Figure25-5 shows the program memory organization One of these is a boot block of 2 Kbytes. The remainder for 16 and 32-Kbyte devices and the specific code of the memory is divided into four blocks on binary protection bit associated with each block. The actual boundaries. locations of the bits are summarized in Table25-3. FIGURE 25-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2480/2580/4480/4580 Address MEMORY SIZE/DEVICE Range 32 Kbytes 16 Kbytes Block Code Protection (PIC18F2580/4580) (PIC18F2480/4480) Controlled by: BBSIZ 0 1 0 1 000000h Boot Block Boot Block 0007FFh 1kW Boot Block 1kW Boot Block CPB, WRTB, EBRTB 000800h 2kW 2kW (Boot Block) 000FFFh Block 0 Block 0 001000h 3kW Block 0 3kW Block 0 CP0, WRT0, EBRT0 001FFFh 2kW 2kW (Block 0) 002000h Block 1 Block 1 Block 1 Block 1 CP!, WRT1, EBRT1 4kW 4kW 4kW 4kW (Block 1) 003FFFh 004000h Block 2 Block 2 CP2, WRT2, EBRT2 4kW 4kW (Block 2) 005FFFh 006000h Block 3 Block 3 CP3, WRT3, EBTR3 4kW 4kW (Block 3) 007FFFh 008000h Unimplemented Unimplemented Read ‘0’s Read ‘0’s Unimplemented Unimplemented (Unimplemented Memory Space) Read ‘0’s Read ‘0’s 1FFFFFh © 2009 Microchip Technology Inc. DS39637D-page 363

PIC18F2480/2580/4480/4580 TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3* CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3* WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3* EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. * Unimplemented in PIC18FX480 devices; maintain this bit set. 25.5.1 PROGRAM MEMORY A table read instruction that executes from a location CODE PROTECTION outside of that block is not allowed to read and will result in reading ‘0’s. Figures25-6 through25-8 The program memory may be read to or written from illustrate table write and table read protection. any location using the table read and table write instructions. The Device ID may be read with table Note: Code protection bits may only be written to reads. The Configuration registers may be read and a ‘0’ from a ‘1’ state. It is not possible to written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full In normal execution mode, the CPn bits have no direct chip erase or block erase function. The full effect. CPn bits inhibit external reads and writes. A chip erase and block erase functions can block of user memory may be protected from table only be initiated via ICSP or an external writes if the WRTn Configuration bit is ‘0’. The EBTRn programmer. bits control table reads. For a block of user memory with the EBTRn bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. FIGURE 25-6: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 003FFEh TBLWT* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 00BFFEh TBLWT* WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table writes disabled to Blockn whenever WRTn = 0. DS39637D-page 364 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 25-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. FIGURE 25-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 003FFEh TBLRD* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. © 2009 Microchip Technology Inc. DS39637D-page 365

PIC18F2480/2580/4480/4580 25.5.2 DATA EEPROM To use the In-Circuit Debugger function of the micro- CODE PROTECTION controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP/RE3, VDD, The entire data EEPROM is protected from external VSS, RB7 and RB6. This will interface to the In-Circuit reads and writes by two bits: CPD and WRTD. CPD debugger module available from Microchip or one of inhibits external reads and writes of data EEPROM. the third party development tool companies. WRTD inhibits internal and external writes to data EEPROM. The CPU can continue to read and write 25.9 Single-Supply ICSP Programming data EEPROM regardless of the protection bit settings. The LVP Configuration bit enables Single-Supply ICSP 25.5.3 CONFIGURATION REGISTER Programming (formerly known as Low-Voltage ICSP PROTECTION Programming or LVP). When Single-Supply Program- The Configuration registers can be write-protected. ming is enabled, the microcontroller can be The WRTC bit controls protection of the Configuration programmed without requiring high voltage being registers. In normal execution mode, the WRTC bit is applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/ readable only. WRTC can only be written via ICSP or PGM pin is then dedicated to controlling Program mode an external programmer. entry and is not available as a general purpose I/O pin. While programming using Single-Supply Program- 25.6 ID Locations ming, VDD is applied to the MCLR/VPP/RE3 pin as in normal execution mode. To enter Programming mode, Eight memory locations (200000h-200007h) are VDD is applied to the PGM pin. designated as ID locations, where the user can store checksum or other code identification numbers. These Note 1: High-voltage programming is always avail- locations are both readable and writable during normal able, regardless of the state of the LVP bit, execution through the TBLRD and TBLWT instructions by applying VIHH to the MCLR pin. or during program/verify. The ID locations can be read 2: While in Low-Voltage ICSP Programming when the device is code-protected. mode, the RB5 pin can no longer be used as a general purpose I/O pin and should 25.7 In-Circuit Serial Programming be held low during normal operation. PIC18F2480/2580/4480/4580 microcontrollers can be 3: When using Low-Voltage ICSP Program- serially programmed while in the end application circuit. ming (LVP) and the pull-ups on PORTB This is simply done with two lines for clock and data are enabled, bit 5 in the TRISB register and three other lines for power, ground and the must be cleared to disable the pull-up on programming voltage. This allows customers to manu- RB5 and ensure the proper operation of facture boards with unprogrammed devices and then the device. program the microcontroller just before shipping the 4: If the device Master Clear is disabled, product. This also allows the most recent firmware or a verify that either of the following is done to custom firmware to be programmed. ensure proper entry into ICSP mode: a) disable Low-Voltage Programming 25.8 In-Circuit Debugger (CONFIG4l<2> = 0); or When the DEBUG Configuration bit is programmed to b) make certain that RB5/PGM is held a ‘0’, the In-Circuit Debugger functionality is enabled. low during entry into ICSP. This function allows simple debugging functions when If Single-Supply ICSP Programming mode will not be used with MPLAB® IDE. When the microcontroller has used, the LVP bit can be cleared. RB5/KBI1/PGM then this feature enabled, some resources are not available becomes available as the digital I/O pin, RB5. The LVP for general use. Table25-4 shows which resources are bit may be set or cleared only when using standard required by the background debugger. high-voltage programming (VIHH applied to the MCLR/ VPP/RE3 pin). Once LVP has been disabled, only the TABLE 25-4: DEBUGGER RESOURCES standard high-voltage programming is available and I/O pins: RB6, RB7 must be used to program the device. Stack: 2 levels Memory that is not code-protected can be erased using Note: Memory resources listed in MPLAB® IDE. either a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required. If a block erase is to be performed when using Low-Voltage Programming, the device must be supplied with VDD of 4.5V to 5.5V. DS39637D-page 366 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 26.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: PIC18F2480/2580/4480/4580 devices incorporate the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) 26.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations program counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table26-2 lists cycles with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table26-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1μs. If a conditional test is true, or the program counter is changed as a result of 3. The accessed memory (specified by ‘a’) an instruction, the instruction execution time is 2 μs. The file register designator, ‘f’, specifies which file Two-word branch instructions (if true) would take 3 μs. register is to be used by the instruction. The destination Figure26-1 shows the general formats that the instruc- designator, ‘d’, specifies where the result of the opera- tions can have. All examples use the convention ‘nnh’ tion is to be placed. If ‘d’ is ‘0’, the result is placed in the to represent a hexadecimal number. WREG register. If ‘d’ is ‘1’, the result is placed in the file register specified in the instruction. The instruction set summary, shown in Table26-2, lists the standard instructions recognized by the Microchip All bit-oriented instructions have three operands: MPASM Assembler. 1. The file register (specified by ‘f’) Section26.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator, ‘b’, selects the number of the bit affected by the operation, while the file register desig- nator, ‘f’, represents the number of the file in which the bit is located. © 2009 Microchip Technology Inc. DS39637D-page 367

PIC18F2480/2580/4480/4580 TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label Label name mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User-defined term (font is Courier New). DS39637D-page 368 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2009 Microchip Technology Inc. DS39637D-page 369

PIC18F2480/2580/4480/4580 TABLE 26-2: PIC18FXXXX INSTRUCTION SET Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Movefs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination)2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39637D-page 370 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. © 2009 Microchip Technology Inc. DS39637D-page 371

PIC18F2480/2580/4480/4580 TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit)2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None 5 TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None 5 TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None 5 TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None 5 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39637D-page 372 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) + k → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: ADDLW 15h Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = 10h After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). © 2009 Microchip Technology Inc. DS39637D-page 373

PIC18F2480/2580/4480/4580 ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory Q Cycle Activity: location ‘f’. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read literal Process Write to W If ‘a’ is ‘1’, the BSR is used to select the ‘k’ Data GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: ANDLW 05Fh in Indexed Literal Offset Addressing Before Instruction mode whenever f ≤ 95 (5Fh). See W = A3h Section26.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 03h Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39637D-page 374 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if Carry bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ‘1’, then the program Description: The contents of W are AND’ed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’. incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank. two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1(2) in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section26.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to PC Words: 1 ‘n’ Data Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h REG = C2h PC = address (HERE) After Instruction After Instruction W = 02h If Carry = 1; REG = C2h PC = address (HERE + 12) If Carry = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39637D-page 375

PIC18F2480/2580/4480/4580 BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if Negative bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank. incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC + 2 + 2n. This instruction is then a in Indexed Literal Offset Addressing two-cycle instruction. mode whenever f ≤ 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 If Jump: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC Q Cycle Activity: ‘n’ Data Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No Before Instruction ‘n’ Data operation FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39637D-page 376 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39637D-page 377

PIC18F2480/2580/4480/4580 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39637D-page 378 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 Operation: (PC) + 2 + 2n → PC a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Cycles: 2 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section26.2.3 “Byte-Oriented and Decode Read literal Process Write to PC Bit-Oriented Instructions in Indexed ‘n’ Data Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah © 2009 Microchip Technology Inc. DS39637D-page 379

PIC18F2480/2580/4480/4580 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction is enabled, this instruction operates in set is enabled, this instruction operates Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39637D-page 380 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: if Overflow bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will If ‘a’ is ‘1’, the BSR is used to select the have incremented to fetch the next GPR bank. instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Cycles: 1(2) Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39637D-page 381

PIC18F2480/2580/4480/4580 BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>; Status Affected: None if s = 1, Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS, will branch. (BSR) → BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 PC + 2 + 2n. This instruction is then a 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 two-cycle instruction. Description: Subroutine call of entire 2-Mbyte Words: 1 memory range. First, return address (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and Q Cycle Activity: BSR registers are also pushed into their If Jump: respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs. Then, the 20-bit value ‘k’ Decode Read literal Process Write to PC is loaded into PC<20:1>. CALL is a two- ‘n’ Data cycle instruction. No No No No Words: 2 operation operation operation operation If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ‘k’<19:8>, Example: HERE BZ Jump Write to PC No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction If Zero = 1; Example: HERE CALL THERE,1 PC = address (Jump) If Zero = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39637D-page 382 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f, 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the post- If ‘a’ is ‘1’, the BSR is used to select the scaler of the WDT. Status bits TO and GPR bank. PD are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1 in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section26.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Cycles: 1 Example: CLRWDT Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WDT Counter = ? After Instruction Decode Read Process Write WDT Counter = 00h register ‘f’ Data register ‘f’ WDT Postscaler = 0 TO = 1 PD = 1 Example: CLRF FLAG_REG,1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h © 2009 Microchip Technology Inc. DS39637D-page 383

PIC18F2480/2580/4480/4580 COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f) → dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘1’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘0’, the result is performing an unsigned subtraction. stored back in register ‘f’. If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank. instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘0’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank. mode whenever f ≤ 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section26.2.3 “Byte-Oriented and set is enabled, this instruction operates Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode” for details. mode whenever f ≤ 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: 3 cycles if skip and followed register ‘f’ Data destination by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h W = ECh Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39637D-page 384 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) − (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory Description: Compares the contents of data memory location ‘f’ to the contents of the W by location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the If the contents of ‘f’ are less than the contents of WREG, then the fetched contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Note: 3 cycles if skip and followed Section26.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process No register ‘f’ Data operation Note: 3 cycles if skip and followed by a 2-word instruction. If skip: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No operation operation operation operation Decode Read Process No register ‘f’ Data operation If skip and followed by 2-word instruction: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; Before Instruction PC = Address (LESS) If REG ≥ W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2009 Microchip Technology Inc. DS39637D-page 385

PIC18F2480/2580/4480/4580 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> >9] or [DC = 1] then, a ∈ [0,1] (W<3:0>) + 6 → W<3:0>; else, Operation: (f) – 1 → dest (W<3:0>) → W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> >9] or [C = 1] then, Encoding: 0000 01da ffff ffff (W<7:4>) + 6 → W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C = 1, result is stored in W. If ‘d’ is ‘1’, the else, result is stored back in register ‘f’. (W<7:4>) → W<7:4> If ‘a’ is ‘0’, the Access Bank is selected. Status Affected: C If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘0’ and the extended instruction Description: DAW adjusts the eight-bit value in W, set is enabled, this instruction operates resulting from the earlier addition of two in Indexed Literal Offset Addressing variables (each in packed BCD format) mode whenever f ≤ 95 (5Fh). See and produces a correct packed BCD Section26.2.3 “Byte-Oriented and result. Bit-Oriented Instructions in Indexed Words: 1 Literal Offset Mode” for details. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write Q1 Q2 Q3 Q4 register W Data W Decode Read Process Write to Example 1: register ‘f’ Data destination DAW Before Instruction Example: DECF CNT, 1, 0 W = A5h C = 0 Before Instruction DC = 0 CNT = 01h After Instruction Z = 0 W = 05h After Instruction C = 1 CNT = 00h DC = 0 Z = 1 Example 2: Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39637D-page 386 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is ‘0’, the next instruction If the result is not ‘0’, the next which is already fetched is discarded instruction which is already fetched is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section26.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Bit-Oriented Instructions in Indexed Section26.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT ≠ 0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP ≠ 0; PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39637D-page 387

PIC18F2480/2580/4480/4580 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k → PC<20:1> a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff Description: The contents of register ‘f’ are Description: GOTO allows an unconditional branch incremented. If ‘d’ is ‘0’, the result is anywhere within entire placed in W. If ‘d’ is ‘1’, the result is 2-Mbyte memory range. The 20-bit placed back in register ‘f’. value ‘k’ is loaded into PC<20:1>. GOTO is always a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 2 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section26.2.3 “Byte-Oriented and Decode Read literal No Read literal Bit-Oriented Instructions in Indexed ‘k’<7:0>, operation ‘k’<19:8>, Literal Offset Mode” for details. Write to PC Words: 1 No No No No operation operation operation operation Cycles: 1 Q Cycle Activity: Example: GOTO THERE Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to PC = Address (THERE) register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39637D-page 388 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result ≠ 0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is not ‘0’, the next If the result is ‘0’, the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2009 Microchip Technology Inc. DS39637D-page 389

PIC18F2480/2580/4480/4580 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) .OR. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: IORLW 35h Section26.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 9Ah Literal Offset Mode” for details. After Instruction Words: 1 W = BFh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39637D-page 390 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] a ∈ [0,1] Operation: k → FSRf Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to file select register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’. Location ‘f’ Q Cycle Activity: can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write GPR bank. ‘k’ MSB Data literal ‘k’ MSB to If ‘a’ is ‘0’ and the extended instruction FSRfH set is enabled, this instruction operates in Indexed Literal Offset Addressing Decode Read literal Process Write literal mode whenever f ≤ 95 (5Fh). See ‘k’ LSB Data ‘k’ to FSRfL Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Example: LFSR 2, 3ABh Literal Offset Mode” for details. After Instruction Words: 1 FSR2H = 03h Cycles: 1 FSR2L = ABh Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h © 2009 Microchip Technology Inc. DS39637D-page 391

PIC18F2480/2580/4480/4580 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ f ≤ 4095 d Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’, regardless of the value of k :k . Description: The contents of source register ‘f ’ are 7 4 s moved to destination register ‘f ’. Words: 1 d Location of source ‘f ’ can be anywhere s Cycles: 1 in the 4096-byte data space (000h to FFFh) and location of destination ‘f ’ Q Cycle Activity: d can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for Example: MOVLB 5 transferring a data memory location to a peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h After Instruction The MOVFF instruction cannot use the BSR Register = 05h PCL, TOSU, TOSH or TOSL as the destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39637D-page 392 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: k → W Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Decode Read Process Write to W literal ‘k’ Data If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f ≤ 95 (5Fh). See After Instruction Section26.2.3 “Byte-Oriented and W = 5Ah Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh © 2009 Microchip Technology Inc. DS39637D-page 393

PIC18F2480/2580/4480/4580 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x k → PRODH:PRODL Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in the PRODH:PRODL register register file location ‘f’. The 16-bit pair. PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the high byte. Both W and ‘f’ are None of the Status flags are affected. unchanged. Note that neither overflow nor carry is None of the Status flags are affected. possible in this operation. A zero result is possible but not detected. Note that neither overflow nor carry is possible in this operation. A zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended Decode Read Process Write instruction set is enabled, this literal ‘k’ Data registers instruction operates in Indexed Literal PRODH: Offset Addressing mode whenever PRODL f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Example: MULLW 0C4h Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = E2h Words: 1 PRODH = ? PRODL = ? Cycles: 1 After Instruction Q Cycle Activity: W = E2h PRODH = ADh Q1 Q2 Q3 Q4 PRODL = 08h Decode Read Process Write register ‘f’ Data registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39637D-page 394 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Example: Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] © 2009 Microchip Technology Inc. DS39637D-page 395

PIC18F2480/2580/4480/4580 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39637D-page 396 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n → PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC+2+2n. This instruction is a two-cycle instruction. Decode Start No No Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) © 2009 Microchip Technology Inc. DS39637D-page 397

PIC18F2480/2580/4480/4580 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL; (TOS) → PC, if s = 1, PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged. Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS, are loaded into their corresponding registers, W, Decode Read Process POP PC STATUS and BSR. If ‘s’ = 0, no update literal ‘k’ Data from stack, of these registers occurs. Write to W No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 CALL TABLE ; W contains table Decode No No POP PC ; offset value operation operation from stack ; W now has Set GIEH or ; table value GIEL : TABLE No No No No ADDWF PCL ; W = offset operation operation operation operation RETLW k0 ; Begin table RETLW k1 ; Example: RETFIE 1 : : After Interrupt RETLW kn ; End of table PC = TOS W = WS Before Instruction BSR = BSRS W = 07h STATUS = STATUSS GIE/GIEH, PEIE/GIEL = 1 After Instruction W = value of kn DS39637D-page 398 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (TOS) → PC; a ∈ [0,1] if s = 1, (WS) → W, Operation: (f<n>) → dest<n + 1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’. registers, WS, STATUSS and BSRS, If ‘a’ is ‘0’, the Access Bank is are loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, STATUS and BSR. If select the GPR bank. ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs. set is enabled, this instruction Words: 1 operates in Indexed Literal Offset Addressing mode whenever Cycles: 2 f ≤ 95 (5Fh). See Section26.2.3 Q Cycle Activity: “Byte-Oriented and Bit-Oriented Q1 Q2 Q3 Q4 Instructions in Indexed Literal Offset Decode No Process POP PC Mode” for details. operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Interrupt Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2009 Microchip Technology Inc. DS39637D-page 399

PIC18F2480/2580/4480/4580 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’. flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’. GPR bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank. in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates Section26.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See Literal Offset Mode” for details. Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39637D-page 400 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n – 1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank. placed back in register ‘f’. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See per the BSR value. Section26.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2009 Microchip Technology Inc. DS39637D-page 401

PIC18F2480/2580/4480/4580 SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: 00h → WDT, a ∈ [0,1] 0 → WDT postscaler, 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down Status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out Status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’. The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. with the oscillator stopped. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing Q1 Q2 Q3 Q4 mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Decode No Process Go to Bit-Oriented Instructions in Indexed operation Data Sleep Literal Offset Mode” for details. Words: 1 Example: SLEEP Cycles: 1 Before Instruction TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1 † register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 Before Instruction † If WDT causes wake-up, this bit is cleared. REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39637D-page 402 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k – (W) → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the Q Cycle Activity: result is stored back in register ‘f’. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to W GPR bank. literal ‘k’ Data If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction operates in Indexed Literal Offset Addressing Before Instruction mode whenever f ≤ 95 (5Fh). See W = 01h C = ? Section26.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 01h Literal Offset Mode” for details. C = 1 ; result is positive Words: 1 Z = 0 N = 0 Cycles: 1 Example 2: SUBLW 02h Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 W = 02h Decode Read Process Write to C = ? register ‘f’ Data destination After Instruction W = 00h Example 1: SUBWF REG, 1, 0 C = 1 ; result is zero Before Instruction Z = 1 N = 0 REG = 3 W = 2 Example 3: SUBLW 02h C = ? Before Instruction After Instruction W = 03h REG = 1 C = ? W = 2 C = 1 ; result is positive After Instruction Z = 0 W = FFh; (2’s complement) N = 0 C = 0 ; result is negative Example 2: SUBWF REG, 0, 0 Z = 0 N = 1 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2009 Microchip Technology Inc. DS39637D-page 403

PIC18F2480/2580/4480/4580 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement Description: The upper and lower nibbles of register method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’. is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39637D-page 404 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR)) → TABLAT, MEMORY(00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR)) → TABLAT, TBLPTR = 00A357h (TBLPTR) + 1 → TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, Before Instruction (TBLPTR) – 1 → TBLPTR; TABLAT = 0AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1 → TBLPTR, MEMORY(01A358h) = 34h (Prog Mem (TBLPTR)) → TABLAT; After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer, called Table Pointer (TBLPTR), is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write TABLAT) Memory) © 2009 Microchip Technology Inc. DS39637D-page 405

PIC18F2480/2580/4480/4580 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT) → Holding Register, TBLPTR = 00A356h TBLPTR – No Change; HOLDING REGISTER (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT) → Holding Register, TABLAT = 55h (TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT) → Holding Register, (00A356h) = 55h (TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*; if TBLWT+*, (TBLPTR) + 1 → TBLPTR, Before Instruction TABLAT = 34h (TABLAT) → Holding Register; TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of the (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written (01389Bh) = 34h to. The holding registers are used to pro- gram the contents of Program Memory (P.M.). (Refer to Section7.0 “Flash Pro- gram Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operation operationoperation operation (Read (Write to TABLAT) Holding Register ) DS39637D-page 406 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to W set is enabled, this instruction operates literal ‘k’ Data in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Example: XORLW 0AFh Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = B5h Words: 1 After Instruction W = 1Ah Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39637D-page 407

PIC18F2480/2580/4480/4580 XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39637D-page 408 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 26.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table26-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section26.2.2 “Extended Instruction instruction set, PIC18F2480/2580/4480/4580 devices Set”. The opcode field descriptions in Table26-1 apply also provide an optional extension to the core CPU to both the standard and extended PIC18 instruction functionality. The added features include eight addi- sets. tional instructions that augment indirect and indexed addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing mode for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features are disabled by default. To these instructions directly in assembler. enable them, users must set the XINST Configuration The syntax for these commands is pro- bit. vided as a reference for users who may be The instructions in the extended set can all be reviewing code that has been generated classified as literal operations, which either manipulate by a compiler. the File Select Registers or use them for indexed addressing. Two of the instructions, ADDFSR and 26.2.1 EXTENDED INSTRUCTION SYNTAX SUBFSR, each have an additional special instantiation Most of the extended instructions use indexed argu- for using FSR2. These versions (ADDULNK and ments, using one of the File Select Registers and some SUBULNK) allow for automatic return after execution. offset to specify a source or destination register. When The extended instructions are specifically implemented an argument for an instruction serves as part of to optimize re-entrant program code (that is, code that indexed addressing, it is enclosed in square brackets is recursive or that uses a software stack) written in (“[ ]”). This is done to indicate that the argument is used high-level languages, particularly C. Among other as an index or offset. MPASM™ Assembler will flag an things, they allow users working in high-level error if it determines that an index or offset value is not languages to perform certain operations on data bracketed. structures more efficiently. These include: When the extended instruction set is enabled, brackets • dynamic allocation and de-allocation of software are also used to indicate index arguments in byte- stack space when entering and leaving oriented and bit-oriented instructions. This is in addition subroutines to other changes in their syntax. For more details, see • function pointer invocation Section26.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”. • software Stack Pointer manipulation • manipulation of variables located in a software Note: In the past, square brackets have been stack used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination)2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return © 2009 Microchip Technology Inc. DS39637D-page 409

PIC18F2480/2580/4480/4580 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2, Operation: FSR(f) + k → FSR(f) PC = (TOS) Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the TOS. Cycles: 1 The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during the Q1 Q2 Q3 Q4 second cycle. Decode Read Process Write to This may be thought of as a special case literal ‘k’ Data FSR of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Example: ADDFSR 2, 23h Cycles: 2 Before Instruction FSR2 = 03FFh Q Cycle Activity: After Instruction FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h TOS = 02AFh After Instruction FSR2 = 0422h PC = 02AFh TOS = TOS – 1 Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). DS39637D-page 410 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0 ≤ z ≤ 127 s 0 ≤ f ≤ 4095 Operation: (PC + 2) → TOS, d (W) → PCL, Operation: ((FSR2) + z ) → f s d (PCLATH) → PCH, Status Affected: None (PCLATU) → PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The contents of W are written to PCL; the d actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of latched into PCH and PCU, s FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘f ’ in the second word. Both addresses new next instruction is fetched. d can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, STATUS or BSR. The MOVSF instruction cannot use the Words: 1 PCL, TOSU, TOSH or TOSL as the destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the Q1 Q2 Q3 Q4 value returned will be 00h. Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Before Instruction Decode No No Write PC = address (HERE) operation operation register ‘f’ PCLATH = 10h PCLATU = 00h No dummy (dest) W = 06h read After Instruction PC = 001006h TOS = address (HERE + 2) Example: MOVSF [05h], REG2 PCLATH = 10h PCLATU = 00h Before Instruction W = 06h FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h © 2009 Microchip Technology Inc. DS39637D-page 411

PIC18F2480/2580/4480/4580 MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255 0 ≤ z ≤ 127 d Operation: k → (FSR2), Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1→ FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s Description: The 8-bit literal ‘k’ is written to the data 2nd word (dest.) 1111 xxxx xzzz zzzzd memory address specified by FSR2. FSR2 is Description The contents of the source register are decremented by 1 after the operation. moved to the destination register. The This instruction allows users to push values addresses of the source and destination onto a software stack. registers are determined by adding the 7-bit literal offsets ‘z ’ or ‘z ’, Words: 1 s d respectively, to the value of FSR2. Both Cycles: 1 registers can be located anywhere in Q Cycle Activity: the 4096-byte data memory space (000h to FFFh). Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to PCL, TOSU, TOSH or TOSL as the data destination destination register. If the resultant source address points to an indirect addressing register, the Example: PUSHL 08h value returned will be 00h. If the Before Instruction resultant destination address points to FSR2H:FSR2L = 01ECh an indirect addressing register, the Memory (01ECh) = 00h instruction will execute as a NOP. After Instruction Words: 2 FSR2H:FSR2L = 01EBh Cycles: 2 Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39637D-page 412 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 ∈ f [ 0, 1, 2 ] Operation: FSR2 – k → FSR2 Operation: FSRf – k → FSRf (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified contents of the FSR2. A RETURN is then by ‘f’. executed by loading the PC with the TOS. Words: 1 The instruction takes two cycles to execute; Cycles: 1 a NOP is performed during the second cycle. Q Cycle Activity: This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary Q1 Q2 Q3 Q4 ‘11’); it operates only on FSR2. Decode Read Process Write to Words: 1 register ‘f’ Data destination Cycles: 2 Q Cycle Activity: Example: SUBFSR 2, 23h Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write to FSR2 = 03FFh register ‘f’ Data destination After Instruction No No No No FSR2 = 03DCh Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2009 Microchip Technology Inc. DS39637D-page 413

PIC18F2480/2580/4480/4580 26.2.3 BYTE-ORIENTED AND 26.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set register argument, ‘f’, in the standard byte-oriented and extension may cause legacy applications bit-oriented commands is replaced with the literal offset to behave erratically or fail entirely. value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing mode (Section6.6.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an the standard PIC18 instruction set are interpreted. error in the MPASM™ Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (a = 0), or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and a = 0, however, instruction set disabled) when ‘a’ is set on the basis of a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM literal address. For practical purposes, this means that Assembler. all instructions that use the Access RAM bit as an The destination argument, ‘d’, functions as before. argument – that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instructions In the latest versions of the MPASM assembler, – may behave differently when the extended instruction language support for the extended instruction set must set is enabled. be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the When the content of FSR2 is 00h, the boundaries of the source listing. Access RAM are essentially remapped to their original values. This may be useful in creating backward 26.2.4 CONSIDERATIONS WHEN compatible code. If this technique is used, it may be ENABLING THE EXTENDED necessary to save the value of FSR2 and restore it INSTRUCTION SET when moving back and forth between ‘C’ and assembly routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the instruc- must also keep in mind the syntax requirements of the tion set may not be beneficial to all users. In particular, extended instruction set (see Section26.2.3.1 users who are not writing code that uses a software “Extended Instruction Syntax with Standard PIC18 stack may not benefit from using the extensions to the Commands”). instruction set. Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing can be very useful for dynamic stack and pointer mode may create issues with legacy applications manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address register. Users who are accustomed to the PIC18 registers in the Access Bank below 5Fh. Since these programming must keep in mind that, when the addresses are interpreted as literal offsets to FSR2 extended instruction set is enabled, register addresses when the instruction set extension is enabled, the of 5Fh or less are used for Indexed Literal Offset application may read or write to the wrong data Addressing. addresses. Representative examples of typical byte-oriented and When porting an application to the PIC18F2480/2580/ bit-oriented instructions in the Indexed Literal Offset 4480/4580, it is very important to consider the type of Addressing mode are provided on the following page to code. A large, re-entrant application that is written in ‘C’ show how execution is affected. The operand and would benefit from efficient compilation will do well conditions shown in the examples are applicable to all when using the instruction set extensions. Legacy instructions of these types. applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39637D-page 414 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 Operands: 0 ≤ f ≤ 95 d ∈ [0,1] 0 ≤ b ≤ 7 a = 0 a = 0 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2 + k))<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the contents Description: Bit ‘b’ of the register indicated by FSR2, of the register indicated by FSR2, offset by the offset by the value ‘k’, is set. value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, Cycles: 1 the result is stored back in register ‘f’. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write to Example: BSF [FLAG_OFST], 7 Data destination Before Instruction FLAG_OFST = 0Ah Example: ADDWF [OFST],0 FSR2 = 0A00h Contents Before Instruction of 0A0Ah = 55h W = 17h After Instruction OFST = 2Ch Contents FSR2 = 0A00h of 0A0Ah = D5h Contents of 0A2Ch = 20h After Instruction W = 37h Contents of 0A2Ch = 20h Set Indexed SETF (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2009 Microchip Technology Inc. DS39637D-page 415

PIC18F2480/2580/4480/4580 26.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set of the PIC18F2480/2580/4480/4580 family of • A menu option, or dialog box within the devices. This includes the MPLAB C18 Ccompiler, environment, that allows the user to configure the MPASM assembly language and MPLAB Integrated language tool and its settings for the project Development Environment (IDE). • A command line option When selecting a target device for software develop- • A directive in the source code ment, MPLAB IDE will automatically set default Config- uration bits for that device. The default setting for the These options vary between different compilers, XINST Configuration bit is ‘0’, disabling the extended assemblers and development environments. Users are instruction set and Indexed Literal Offset Addressing encouraged to review the documentation accompany- mode. For proper execution of applications developed ing their development systems for the appropriate to take advantage of the extended instruction set, information. XINST must be set during programming. DS39637D-page 416 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 27.0 DEVELOPMENT SUPPORT 27.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. Advance Information © 2009 Microchip Technology Inc. DS39637D-page 417

PIC18F2480/2580/4480/4580 27.2 MPLAB C Compilers for Various 27.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 27.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 27.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 27.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Advance Information DS39637D-page 418 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 27.7 MPLAB SIM Software Simulator 27.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 27.10 PICkit 3 In-Circuit Debugger/ Programmer and 27.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables. Advance Information © 2009 Microchip Technology Inc. DS39637D-page 419

PIC18F2480/2580/4480/4580 27.11 PICkit 2 Development 27.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 27.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. Advance Information DS39637D-page 420 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/RE3 pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39637D-page 421

PIC18F2480/2580/4480/4580 FIGURE 28-1: PIC18F2480/2580/4480/4580 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V 5.0V PIC18F2X80/4X80 4.5V e 4.2V g 4.0V a t ol 3.5V Industrial and V Extended Devices 3.0V Industrial Devices 2.5V Only 2.0V 25 MHz 40 MHz Frequency FIGURE 28-2: PIC18LF2480/2580/4480/4580 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LF2X80/4X80 4.5V e 4.2V g 4.0V a t ol 3.5V V 3.0V 2.5V 2.0V 4 MHz 40 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. DS39637D-page 422 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 2 8.1 DC Characteristics: Supply Voltage PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. VDD Supply Voltage D001 PIC18LF2X80/4X80 2.0 — 5.5 V PIC18F2X80/4X80 4.2 — 5.5 V D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D001D AVSS Analog Ground Voltage VSS – 0.3 — VSS + 0.3 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See section on Power-on Reset for details to ensure Internal Power-on Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset for details to ensure Internal Power-on Reset Signal VBOR Brown-out Reset Voltage D005 PIC18LF2X80/4X80 BORV<1:0> = 11 2.00 2.1 2.16 V BORV<1:0> = 10 2.65 2.79 2.93 V D005 All Devices BORV<1:0> = 01(2) 4.11 4.33 4.55 V BORV<1:0> = 00 4.36 4.59 4.82 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: With BOR enabled, full-speed operation (FOSC = 40 MHz) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency. © 2009 Microchip Technology Inc. DS39637D-page 423

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) PIC18LF2X80/4X80 0.2 1.0 μA -40°C 0.2 1.0 μA +25°C VDD = 2.0V 0.3 4.0 μA +60°C (Sleep mode) 0.4 6.0 μA +85°C PIC18LF2X80/4X80 0.2 1.5 μA -40°C 0.2 2.0 μA +25°C VDD = 3.0V 0.4 5.0 μA +60°C (Sleep mode) 0.5 8.0 μA +85°C All devices 0.2 2.0 μA -40°C 0.2 2.0 μA +25°C VDD = 5.0V 0.6 9.0 μA +60°C (Sleep mode) 1.0 15 μA +85°C Extended devices only 52.00 132.00 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39637D-page 424 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LF2X80/4X80 19 31 μA -40°C 21 31 μA +25°C VDD = 2.0V 22 31 μA +85°C PIC18LF2X80/4X80 57 60 μA -40°C 47 60 μA +25°C VDD = 3.0V FOSC = 31kHz (RC_RUN mode, 42 60 μA +85°C Internal oscillator source) All devices 150 170 μA -40°C 113 170 μA +25°C VDD = 5.0V 98 170 μA +85°C Extended devices only 170 280 μA +125°C PIC18LF2X80/4X80 530 1030 μA -40°C 550 1030 μA +25°C VDD = 2.0V 560 1030 μA +85°C PIC18LF2X80/4X80 940 1150 μA -40°C 900 1150 μA +25°C VDD = 3.0V FOSC = 1MHz (RC_RUN mode, 880.0 1150 μA +85°C Internal oscillator source) All devices 1.8 2.3 mA -40°C 1.7 2.3 mA +25°C VDD = 5.0V 1.7 2.3 mA +85°C Extended devices only 2.6 3.6 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. © 2009 Microchip Technology Inc. DS39637D-page 425

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LF2X80/4X80 1.5 2.1 mA -40°C 1.5 2.1 mA +25°C VDD = 2.0V 1.5 2.1 mA +85°C PIC18LF2X80/4X80 2.4 3.3 mA -40°C 2.4 3.3 mA +25°C VDD = 3.0V FOSC = 4MHz (RC_RUN mode, 2.4 3.3 mA +85°C Internal oscillator source) All devices 4.4 5.3 mA -40°C 4.4 5.3 mA +25°C VDD = 5.0V 4.4 5.3 mA +85°C Extended devices only 9.2 11 mA +125°C PIC18LF2X80/4X80 6.1 8.4 μA -40°C 6.7 8.4 μA +25°C VDD = 2.0V 7.4 21 μA +85°C PIC18LF2X80/4X80 9.6 12 μA -40°C 11 12 μA +25°C VDD = 3.0V FOSC = 31kHz (RC_IDLE mode, 12 33 μA +85°C Internal oscillator source) All devices 20 28 μA -40°C 22 28 μA +25°C VDD = 5.0V 24 55 μA +85°C Extended devices only 84 200 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39637D-page 426 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LF2X80/4X80 300 390 μA -40°C 320 390 μA +25°C VDD = 2.0V 330 390 μA +85°C PIC18LF2X80/4X80 450 550 μA -40°C 470 550 μA +25°C VDD = 3.0V FOSC = 1MHz (RC_IDLE mode, 490 550 μA +85°C Internal oscillator source) All devices 840 1030 μA -40°C 880 1030 μA +25°C VDD = 5.0V 900 1030 μA +85°C Extended devices only 2.8 3.2 mA +125°C PIC18LF2X80/4X80 760 1050 μA -40°C 790 1050 μA +25°C VDD = 2.0V 810 1050 μA +85°C PIC18LF2X80/4X80 1.2 1.5 mA -40°C 1.2 1.5 mA +25°C VDD = 3.0V FOSC = 4MHz (RC_IDLE mode, 1.3 1.5 mA +85°C Internal oscillator source) All devices 2.2 2.7 mA -40°C 2.3 2.7 mA +25°C VDD = 5.0V 2.3 2.7 mA +85°C Extended devices only 4.7 5.5 mA +125°C PIC18LF2X80/4X80 410 550 μA -40°C 420 550 μA +25°C VDD = 2.0V 420 550 μA +85°C PIC18LF2X80/4X80 870 830 μA -40°C 770 830 μA +25°C VDD = 3.0V FOSC = 1MHZ (PRI_RUN, 720 830 μA +85°C EC oscillator) All devices 1.8 3.3 mA -40°C 1.6 3.3 mA +25°C VDD = 5.0V 1.5 3.3 mA +85°C Extended devices only 1.5 3.3 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. © 2009 Microchip Technology Inc. DS39637D-page 427

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LF2X80/4X80 1.4 2.2 mA -40°C 1.4 2.2 mA +25°C VDD = 2.0V 1.4 2.2 mA +85°C PIC18LF2X80/4X80 2.3 3.3 mA -40°C 2.3 3.3 mA +25°C VDD = 3.0V FOSC = 4MHz (PRI_RUN, 2.3 3.3 mA +85°C EC oscillator) All devices 4.5 6.6 mA -40°C 4.3 6.6 mA +25°C VDD = 5.0V 4.3 6.6 mA +85°C Extended devices only 5 7.7 mA +125°C 15 23 mA +125°C VDD = 4.2V FOSC = 25MHz 20 31 mA +125°C (PRI_RUN, VDD = 5.0V EC oscillator) All devices 30 38 mA -40°C 31 38 mA +25°C VDD = 4.2V 31 38 mA +85°C FOSC = 40MHZ (PRI_RUN, All devices 37 44 mA -40°C EC oscillator) 38 44 mA +25°C VDD = 5.0V 39 44 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39637D-page 428 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LF2X80/4X80 160 220 μA -40°C 170 220 μA +25°C VDD = 2.0V 170 220 μA +85°C PIC18LF2X80/4X80 250 330 μA -40°C 260 330 μA +25°C VDD = 3.0V FOSC = 1MHz (PRI_IDLE mode, 260 330 μA +85°C EC oscillator) All devices 460 550 μA -40°C 470 550 μA +25°C VDD = 5.0V 480 550 μA +85°C Extended devices only 790 920 μA +125°C PIC18LF2X80/4X80 640 715 μA -40°C 650 715 μA +25°C VDD = 2.0V 660 715 μA +85°C PIC18LF2X80/4X80 0.98 1.4 mA -40°C 1 1.4 mA +25°C VDD = 3.0V FOSC = 4MHz (PRI_IDLE mode, 1.1 1.4 mA +85°C EC oscillator) All devices 1.9 2.2 mA -40°C 1.9 2.2 mA +25°C VDD = 5.0V 1.9 2.2 mA +85°C Extended devices only 2.1 2.4 mA +125°C 9.5 11 mA +125°C VDD = 4.2V FOSC = 25MHz 14 16 mA +125°C (PRI_IDLE mode, VDD = 5.0V EC oscillator) All devices 15 18 mA -40°C 16 18 mA +25°C VDD = 4.2 V 16 18 mA +85°C FOSC = 40MHz (PRI_IDLE mode, All devices 19 22 mA -40°C EC oscillator) 19 22 mA +25°C VDD = 5.0V 20 22 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. © 2009 Microchip Technology Inc. DS39637D-page 429

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LF2X80/4X80 19 44 μA -40°C 20 44 μA +25°C VDD = 2.0V 22 44 μA +85°C PIC18LF2X80/4X80 56 71 μA -40°C FOSC = 32kHz 45 71 μA +25°C VDD = 3.0V (SEC_RUN mode, 41 71 μA +85°C Timer1 as clock)(4) All devices 140 165 μA -40°C 106 165 μA +25°C VDD = 5.0V 95 165 μA +85°C PIC18LF2X80/4X80 6.1 13 μA -40°C 6.6 13 μA +25°C VDD = 2.0V 7.7 13 μA +85°C PIC18LF2X80/4X80 9.3 33 μA -40°C FOSC = 32kHz 9.4 33 μA +25°C VDD = 3.0V (SEC_IDLE mode, 11 33 μA +85°C Timer1 as clock)(4) All devices 17 50 μA -40°C 17 50 μA +25°C VDD = 5.0V 20 50 μA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39637D-page 430 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD) D022 Watchdog Timer 1.7 7.6 μA -40°C (ΔIWDT) 2.1 8 μA +25°C VDD = 2.0V 2.6 8.4 μA +85°C 2.2 11.4 μA -40°C 2.4 12 μA +25°C VDD = 3.0V 2.8 12.6 μA +85°C 2.9 14.3 μA -40°C 3.1 15 μA +25°C VDD = 5.0V 3.3 15.8 μA +85°C 7.80 19 μA +125°C D022A Brown-out Reset 17 75 μA -40°C to +85°C VDD = 3.0V (ΔIBOR) 47 92 μA -40°C to +85°C 30 58 μA +125°C VDD = 5.0V 0 2 μA -40°C to +85°C Sleep mode 0 5 μA -40°C to +125°C BOREN<1:0> D022B High/Low-Voltage Detect 14 47 μA -40°C to +85°C VDD = 2.0V (ΔILVD) 18 58 μA -40°C to +85°C VDD = 3.0V 21 69 μA -40°C to +85°C VDD = 5.0V 19 50 μA +125°C D025 Timer1 Oscillator 1.0 8 μA -40°C (ΔIOSCB) 1.1 8 μA +25°C VDD = 2.0V 32kHz on Timer1(4) 1.1 8 μA +85°C 1.2 8.2 μA -40°C 1.3 8.2 μA +25°C VDD = 3.0V 32kHz on Timer1(4) 1.2 8.2 μA +85°C 1.8 10 μA -40°C 1.9 10 μA +25°C VDD = 5.0V 32kHz on Timer1(4) 1.9 10 μA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. © 2009 Microchip Technology Inc. DS39637D-page 431

PIC18F2480/2580/4480/4580 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) PIC18LF2480/2580/4480/4580 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. D026 A/D Converter 1.0 2.0 μA -40°C to +85°C VDD = 2.0V (ΔIAD) 1.0 2.0 μA -40°C to +85°C VDD = 3.0V A/D on, not converting 1.0 2.0 μA -40°C to +85°C VDD = 5.0V 2.0 8.0 μA -40°C to +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption.The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula, Ir = VDD/2REXT (mA), with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39637D-page 432 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 28.3 DC Characteristics: PIC18F2480/2580/4480/4580 (Industrial) PIC18LF2480/2580/4480/4580 (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O Ports: D030 with TTL Buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V D031A RC3 and RC4 VSS 0.3 Vdd V I2C™ enabled D031B VSS 0.8 V SMBus enabled D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V RC, EC modes(1) D033B OSC1 VSS 0.3 V XT, LP modes D034 T13CKI VSS 0.3 V VIH Input High Voltage I/O Ports: D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V D041A RC3 and RC4 0.7 VDD VDD V I2C™ enabled D041B 2.1 VDD V SMBus enabled, VDD ≥ 3V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC mode D043B OSC1 0.9 VDD VDD V RC mode(1) D043C OSC1 1.6 VDD V XT, LP modes D044 T13CKI 1.6 VDD V IIL Input Leakage Current(2,3) D060 I/O Ports — ±200 nA VDD < 5.5V, VSS ≤ VPIN ≤ VDD, Pin at high-impedance — ±50 nA VDD < 3V, VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR — ±1 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±1 μA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB Weak Pull-up Current 50 400 μA VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2009 Microchip Technology Inc. DS39637D-page 433

PIC18F2480/2580/4480/4580 28.3 DC Characteristics: PIC18F2480/2580/4480/4580 (Industrial) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40°C to +85°C VOH Output High Voltage(3) D090 I/O Ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, (RC, RCIO, EC, ECIO modes) VDD = 4.5V, -40°C to +85°C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 Pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA — 400 pF I2C™ Specification Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS39637D-page 434 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC Characteristics Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP/RE3 Pin 9.00 — 13.25 V (Note 3) D113 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C to +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(2) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP™ port D132A VIW VDD for Externally Timed Erase 4.5 — 5.5 V Using ICSP port or Write D132B VPEW VDD for Self-Timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133 TIE ICSP Block Erase Cycle Time — 4 — ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time 1 — — ms VDD > 4.5V (externally timed) D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section8.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if Single-Supply Programming is disabled. © 2009 Microchip Technology Inc. DS39637D-page 435

PIC18F2480/2580/4480/4580 TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) -40°C < TA < +125°C for extended Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1)* — 150 400 ns PIC18FXXXX D303A — 150 600 ns PIC18LFXXXX, VDD = 2.0V D304 TMC2OV Comparator Mode Change to — — 10 μs Output Valid* Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from VSS to VDD. TABLE 28-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) -40°C < TA < +125°C for extended Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/4 LSb Low Range (CVRR = 1) — — 1/2 LSb High Range (CVRR = 0) D312 VRUR Unit Resistor Value (R) — 2k — Ω D313 TSET Settling Time(1) — — 10 μs Note 1: Settling time measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’. DS39637D-page 436 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be VLVD cleared in software) (HLVDIF set by hardware) HLVDIF TABLE 28-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C < TA < +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D420 HLVD Voltage on VDD LVV = 0000 2.12 2.17 2.22 V Transition High-to-Low LVV = 0001 2.18 2.23 2.28 V LVV = 0010 2.31 2.36 2.42 V LVV = 0011 2.38 2.44 2.49 V LVV = 0100 2.54 2.60 2.66 V LVV = 0101 2.72 2.79 2.85 V LVV = 0110 2.82 2.89 2.95 V LVV = 0111 3.05 3.12 3.19 V LVV = 1000 3.31 3.39 3.47 V LVV = 1001 3.46 3.55 3.63 V LVV = 1010 3.63 3.71 3.80 V LVV = 1011 3.81 3.90 3.99 V LVV = 1100 4.01 4.11 4.20 V LVV = 1101 4.23 4.33 4.43 V LVV = 1110 4.48 4.59 4.69 V LVV = 1111 1.14 1.2 1.26 V © 2009 Microchip Technology Inc. DS39637D-page 437

PIC18F2480/2580/4480/4580 28.4 AC (Timing) Characteristics 28.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS39637D-page 438 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 28.4.2 TIMING CONDITIONS Note: Because of space limitations, the generic The temperature and voltages specified in Table28-5 terms “PIC18FXXXX” and “PIC18LFXXXX” apply to all timing specifications unless otherwise are used throughout this section to refer to noted. Figure28-4 specifies the load conditions for the the PIC18F2480/2580/4480/4580 and timing specifications. PIC18LF2480/2580/4480/4580 families of devices specifically and only those devices. TABLE 28-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial AC CHARACTERISTICS -40°C < TA < +125°C for extended Operating voltage VDD range as described in DC spec Section28.1 and Section28.3. LF parts operate for industrial temperatures only. FIGURE 28-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports © 2009 Microchip Technology Inc. DS39637D-page 439

PIC18F2480/2580/4480/4580 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 28-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator mode DC 25 MHz HS Oscillator mode DC 31.25 kHz LP Oscillator mode DC 40 MHz EC Oscillator mode Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 10 MHz HSPLL Oscillator mode 5 200 kHz LP Oscillator mode 1 TOSC External CLKI Period(1) 1000 — ns XT, RC Oscillator mode 40 — ns HS Oscillator mode 32 — μs LP Oscillator mode 25 — ns EC Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 250 1 μs XT Oscillator mode 40 250 ns HS Oscillator mode 100 250 ns HSPLL Oscillator mode 5 200 μs LP Oscillator mode 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial 160 — ns TCY = 4/FOSC, Extended 3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode TOSH High or Low Time 2.5 — μs LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode TOSF Rise or Fall Time — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS39637D-page 440 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 TABLE 28-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only F12 t PLL Start-up Time (lock time) — — 2 ms rc F13 ΔCLK CLKO Stability (jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F2480/2580/4480/4580 (INDUSTRIAL) PIC18LF2480/2580/4480/4580 (INDUSTRIAL) Standard Operating Conditions (unless otherwise stated) PIC18F2480/2580/4480/4580 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial) -40°C < TA < +125°C for extended Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC18LF2X80/4X80 -2 +/-1 2 % +25°C VDD = 2.7-3.3V -5 — 5 % -10°C to +85°C VDD = 2.7-3.3V -10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3V PIC18F2X80/4X80 -2 +/-1 2 % +25°C VDD = 4.5-5.5V -5 — 5 % -10°C to +85°C VDD = 4.5-5.5V -10 +/-1 10 % -40°C to +85°C VDD = 4.5-5.5V INTRC Accuracy @ Freq = 31 kHz PIC18LF2X80/4X80 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V PIC18F2X80/4X80 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. © 2009 Microchip Technology Inc. DS39637D-page 441

PIC18F2480/2580/4480/4580 FIGURE 28-6: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure28-4 for load conditions. TABLE 28-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TOSH2CK OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) H 12 TCKR CLKO Rise Time — 35 100 ns (Note 1) 13 TCKF CLKO Fall Time — 35 100 ns (Note 1) 14 TCKL2IOV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TCKH2IOI Port In Hold after CLKO ↑ 0 — — ns (Note 1) 17 TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1 ↑ (Q2 cycle) to Port PIC18FXXXX 100 — — ns 18A Input Invalid (I/O in hold PIC18LFXXXX 200 — — ns VDD = 2.0V time) 19 TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in 0 — — ns setup time) 20 TIOR Port Output Rise Time PIC18FXXXX — 10 25 ns 20A PIC18LFXXXX — — 60 ns VDD = 2.0V 21 TIOF Port Output Fall Time PIC18FXXXX — 10 25 ns 21A PIC18LFXXXX — — 60 ns VDD = 2.0V 22† TINP INTx Pin High or Low Time TCY — — ns 23† TRBP RB<7:4> Change INTx High or Low Time TCY — — ns 24† TRCP RC<7:4> Change INTx High or Low Time 20 ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39637D-page 442 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins FIGURE 28-8: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference 36 Voltage Stable TABLE 28-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Sym Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 3.4 4.0 4.6 ms (no postscaler) 32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 55.6 65.5 75 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — μs Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005) 36 TIRVST Time for Internal Reference Voltage — 20 50 μs to become Stable 37 TLVD High/Low-Voltage Detect Pulse 200 — — μs VDD ≤ VLVD Width 38 TCSD CPU Start-up Time — 10 — μs 39 TIOBST Time for INTOSC to Stabilize — 1 — μs © 2009 Microchip Technology Inc. DS39637D-page 443

PIC18F2480/2580/4480/4580 FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 TABLE 28-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale value 20ns or (1, 2, 4,..., 256) (TCY + 40)/N 45 TT1H T13CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 46 TT1L T13CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 47 TT1P T13CKI Input Synchronous Greater of: — ns N = prescale value Period 20ns or (1, 2, 4, 8) (TCY + 40)/N Asynchronous 60 — ns FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMR Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — I Timer Increment DS39637D-page 444 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 TABLE 28-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Sym Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + — ns Time 20 With prescaler PIC18FXXXX 10 — ns PIC18LFXXXX 20 — ns VDD = 2.0V 51 TCCH CCPx Input High No prescaler 0.5 TCY + — ns Time 20 With prescaler PIC18FXXXX 10 — ns PIC18LFXXXX 20 — ns VDD = 2.0V 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1,4 or 16) 53 TCCR CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 54 TCCF CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V © 2009 Microchip Technology Inc. DS39637D-page 445

PIC18F2480/2580/4480/4580 FIGURE 28-11: PARALLEL SLAVE PORT TIMING (PIC18F4480/4580) RE2/CS RE0/RD RE1/WR 65 RD<7:0> 62 64 63 TABLE 28-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4480/4580) Param. Symbol Characteristic Min Max Units Conditions No. 62 TDTV2WRH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TWRH2DTI WR ↑ or CS ↑ to Data–In Invalid PIC18FXXXX 20 — ns (hold time) PIC18LFXXXX 35 — ns VDD = 2.0V 64 TRDL2DTV RD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TRDH2DTI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TIBFINH Inhibit of the IBF Flag bit being Cleared from WR ↑ or CS ↑ — 3 TCY DS39637D-page 446 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-12: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SCK (CKP = 0) 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 TABLE 28-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time — 25 ns 80 TSCH2DOV, SDO Data Output Valid after PIC18FXXXX — 50 ns TSCL2DOV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V © 2009 Microchip Technology Inc. DS39637D-page 447

PIC18F2480/2580/4480/4580 FIGURE 28-13: EXAMPLE SPI MASTER MODE TIMING (CKE=1) 81 SCK (CKP = 0) 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 TABLE 28-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time — 25 ns 80 TSCH2DOV, SDO Data Output Valid after PIC18FXXXX — 50 ns TSCL2DOV SCK Edge PIC18LFXXXX 100 ns VDD = 2.0V 81 TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — ns TDOV2SCL DS39637D-page 448 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-14: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 80 79 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 73 TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH SS ↓ to SCK ↓ or SCK ↑ Input 3 TCY — ns , TSSL2SCL 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS ↑ to SDO Output High-Impedance 10 50 ns 80 TSCH2DOV SDO Data Output Valid after SCK PIC18FXXXX — 50 ns , Edge PIC18LFXXXX 100 ns VDD = 2.0V TSCL2DOV 83 TscH2ssH SS ↑ after SCK Edge 1.5 TCY + 40 — ns , TscL2ssH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39637D-page 449

PIC18F2480/2580/4480/4580 FIGURE 28-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 TABLE 28-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input 3 TCY — ns TSSL2SCL 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the fIrst Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS↑ to SDO Output High-Impedance 10 50 ns 80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXXXX — 50 ns TSCL2DOV Edge PIC18LFXXXX — 100 ns VDD = 2.0V 82 TSSL2DOV SDO Data Output Valid after SS ↓ PIC18FXXXX — 50 ns Edge PIC18LFXXXX — 100 ns VDD = 2.0V 83 TSCH2SSH, SS ↑ after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39637D-page 450 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-16: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition TABLE 28-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 28-17: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out © 2009 Microchip Technology Inc. DS39637D-page 451

PIC18F2480/2580/4480/4580 TABLE 28-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXXX must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs PIC18FXXXX must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup 100 kHz mode 4.7 — μs Only relevant for Repeated Time 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition Hold 100 kHz mode 4.0 — μs After this period, the first clock Time 400 kHz mode 0.6 — μs pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup 100 kHz mode 4.7 — μs Time 400 kHz mode 0.6 — μs 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS39637D-page 452 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-18: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition TABLE 28-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Repeated Start condi- Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — tion 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 28-19: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out © 2009 Microchip Technology Inc. DS39637D-page 453

PIC18F2480/2580/4480/4580 TABLE 28-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High 100 kHz mode 2(TOSC)(BRG + 1) — ms Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time Repeated Start 400 kHz mode 2(TOSC)(BRG + 1) — ms condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released. DS39637D-page 454 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK Pin 121 121 RC7/RX/DT Pin 120 122 TABLE 28-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 TCKRF Clock Out Rise Time and Fall Time PIC18FXXXX — 20 ns (Master mode) PIC18LFXXXX — 50 ns VDD = 2.0V 122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V FIGURE 28-21: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK Pin 125 RC7/RX/DT Pin 126 Note: Refer to Figure28-4 for load conditions. TABLE 28-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns © 2009 Microchip Technology Inc. DS39637D-page 455

PIC18F2480/2580/4480/4580 TABLE 28-24: A/D CONVERTER CHARACTERISTICS: PIC18F2480/2580/4480/4580 (INDUSTRIAL) PIC18LF2480/2580/4480/4580 (INDUSTRIAL) Param Sym Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±2 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — A20 ΔVREF Reference Voltage Range 3 — AVDD – AVSS V For 10-bit resolution (VREFH – VREFL) A21 VREFH Reference Voltage High AVSS + 3.0V — AVDD + 0.3V V For 10-bit resolution A22 VREFL Reference Voltage Low AVSS – 0.3V — AVDD – 3.0V V For 10-bit resolution A25 VAIN Analog Input Voltage VREFL — VREFH V A28 AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V A29 AVSS Analog Supply Voltage VSS – 0.3 — VSS + 0.3 V A30 ZAIN Recommended Impedance of — — 2.5 kΩ Analog Voltage Source A40 IAD A/D Conversion PIC18FXXXX — 180 — μA Average current Current (VDD) consumption when A/D is on (Note 2) PIC18LFXXXX — 90 — μA VDD = 2.0V; average current consumption when A/D is on (Note 2) A50 IREF VREF Input Current (Note 3) — — ±5 μA During VAIN acquisi- — — ±150 μA tion. During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source. DS39637D-page 456 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 FIGURE 28-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 28-25: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μs VDD = 2.0V; TOSC based, VREF full range PIC18FXXXX — 1 μs A/D RC mode PIC18LFXXXX — 3 μs VDD = 2.0V; A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 1.4 — μs -40°C to +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) — 136 TAMP Amplifier Settling Time (Note 5) 1 — μs This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES register may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (AVDD to AVSS or AVSS to AVDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. 5: See Section20.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input voltage has changed more than 1 LSb. © 2009 Microchip Technology Inc. DS39637D-page 457

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 458 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC18F2580-I/SPe3 XXXXXXXXXXXXXXXXX 0910017 YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F2580-E/SOe3 XXXXXXXXXXXXXXXXXXXX 0910017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN Example XXXXXXXX 18F2580 XXXXXXXX -I/MLe3 YYWWNNN 0910017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS39637D-page 459

PIC18F2480/2580/4480/4580 29.1 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC18F4580-I/Pe3 XXXXXXXXXXXXXXXXXX 0910017 XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP Example XXXXXXXXXX PIC18F4580 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 0910017 YYWWNNN 44-Lead QFN Example XXXXXXXXXX PIC18F4580 XXXXXXXXXX -I/MLe3 XXXXXXXXXX 0910017 YYWWNNN DS39637D-page 460 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 29.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1 © 2009 Microchip Technology Inc. DS39637D-page 461

PIC18F2480/2580/4480/4580 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)#(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)#(cid:24)(cid:9)(cid:25)(cid:9)$(cid:12)(cid:8)(cid:6)%(cid:9)&’((cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)#(cid:22)) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e b h α h φ c A A2 L A1 L1 β 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)?(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:3)(cid:20)(cid:4)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)-(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:4)(cid:20)-(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:5)(cid:20)(cid:29)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:5)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:23)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)< = (cid:4)(cid:20)-- 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)B = (cid:30)(cid:29)B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)B = (cid:30)(cid:29)B !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:3)1 DS39637D-page 462 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7),(cid:6)(cid:9)(cid:23)-(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)./.(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)*+! 0(cid:12)(cid:18)1(cid:9)(cid:27)’(((cid:9)(cid:28)(cid:28)(cid:9))(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13),(cid:18)1 !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)(cid:29)1 © 2009 Microchip Technology Inc. DS39637D-page 463

PIC18F2480/2580/4480/4580 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7),(cid:6)(cid:9)(cid:23)-(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)./.(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)*+! 0(cid:12)(cid:18)1(cid:9)(cid:27)’(((cid:9)(cid:28)(cid:28)(cid:9))(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13),(cid:18)1 !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS39637D-page 464 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 2(cid:27)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9).(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:29) = (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:29)(cid:24)(cid:4) = (cid:20)?(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)<(cid:29) = (cid:20)(cid:29)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)<(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) = (cid:20)(cid:3)(cid:4)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< = (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:5)(cid:4)(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)?1 © 2009 Microchip Technology Inc. DS39637D-page 465

PIC18F2480/2580/4480/4580 22(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)31(cid:12)(cid:13)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)4(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)3(cid:24)(cid:9)(cid:25)(cid:9)5(cid:27)/5(cid:27)/5(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)3*+(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B -(cid:20)(cid:29)B (cid:5)B : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)D(cid:2)!(cid:7)E(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1 DS39637D-page 466 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 22(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)31(cid:12)(cid:13)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)4(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)3(cid:24)(cid:9)(cid:25)(cid:9)5(cid:27)/5(cid:27)/5(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)3*+(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS39637D-page 467

PIC18F2480/2580/4480/4580 22(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7),(cid:6)(cid:9)(cid:23)-(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)/(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)*+! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-< ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)-1 DS39637D-page 468 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 22(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7),(cid:6)(cid:9)(cid:23)-(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)/(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)*+! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS39637D-page 469

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 470 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (July 2004) The differences between the devices listed in this data Original data sheet for PIC18F2480/2580/4480/4580 sheet are shown in TableB-1. devices. Revision B (August 2006) Edits to Table6-1 in Section6.0 “Memory Organization” and trademarking updated. Revision C (March 2007) Edits to Table6-1 in Section6.0 “Memory Organiza- tion”, pin name change in Section22.5 “Connection Considerations”, updates to Section 27.3 “DC Charac- teristics”, changes to SPI Mode Requirements in Figure28-12 and Figure28-13, and Table28-14 through Table28-17, and there have been minor updates to the data sheet text, including trademarking updates. Revision D (November 2009) Removed Preliminary from the Condition tags. Various edits throughout the data sheet text. TABLE B-1: DEVICE DIFFERENCES Features PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580 Program Memory (Bytes) 16384 32768 16384 32768 Program Memory (Instructions) 8192 16384 8291 16384 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 1 1 1 1 Enhanced Capture/Compare/ 0 0 1 1 PWM Modules Parallel Communications (PSP) No No Yes Yes 10-bit Analog-to-Digital Module 8 input channels 8 input channels 11 input channels 11 input channels Packages 28-pin SPDIP 28-pin SPDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 44-pin TQFP 44-pin TQFP 28-pin QFN 28-pin QFN 44-pin QFN 44-pin QFN © 2009 Microchip Technology Inc. DS39637D-page 471

PIC18F2480/2580/4480/4580 APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the This section discusses how to migrate from a Baseline ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device are due to the differences in the process technology (i.e., PIC18FXXX). used. An example of this type of conversion is from a The following are the list of modifications over the PIC16C74A to a PIC16C74B. PIC16C5X microcontroller family: Not Applicable Not Currently Available DS39637D-page 472 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices enhanced devices (i.e., PIC18FXXX) is provided in (i.e., PIC17CXXX) and the enhanced devices AN716, “Migrating Designs from PIC16C74A/74B to (i.e., PIC18FXXX) is provided in AN726, “PIC17CXXX PIC18C442.” The changes discussed, while device to PIC18CXXX Migration.” This Application Note is specific, are generally applicable to all mid-range to available as Literature Number DS00726. enhanced device migrations. This Application Note is available as Literature Number DS00716. © 2009 Microchip Technology Inc. DS39637D-page 473

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 474 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 INDEX A Bit Timing Configuration Registers BRGCON1 ...............................................................344 A/D ...................................................................................253 BRGCON2 ...............................................................344 A/D Converter Interrupt, Configuring .......................257 BRGCON3 ...............................................................344 Acquisition Requirements ........................................258 Block Diagrams ADCON0 Register ....................................................253 A/D ...........................................................................256 ADCON1 Register ....................................................253 Analog Input Model ..................................................257 ADCON2 Register ....................................................253 Baud Rate Generator ..............................................217 ADRESH Register ............................................253, 256 CAN Buffers and Protocol Engine ...........................280 ADRESL Register ....................................................253 Capture Mode Operation .........................................170 Analog Port Pins, Configuring ..................................260 Comparator I/O Operating Modes ...........................264 Associated Registers ...............................................262 Comparator Output ..................................................266 Automatic Acquisition Time ......................................259 Comparator Voltage Reference ...............................270 Calculating the Minimum Required Comparator Voltage Reference Acquisition Time ..............................................258 Output Buffer Example ....................................271 Configuring the Module ............................................257 Compare Mode Operation .......................................171 Conversion Clock (TAD) Selection ...........................259 Device Clock ..............................................................34 Conversion Status (GO/DONE Bit) ..........................256 Enhanced PWM .......................................................179 Conversions .............................................................261 EUSART Receive ....................................................244 Converter Characteristics ........................................456 EUSART Transmit ...................................................242 Operation in Power-Managed Modes ......................260 External Power-on Reset Circuit Special Event Trigger (CCP) ....................................262 Special Event Trigger (ECCP) .................................178 (Slow VDD Power-up) ........................................49 Fail-Safe Clock Monitor ...........................................361 Use of the CCP1 Trigger ..........................................262 Generic I/O Port .......................................................135 Absolute Maximum Ratings .............................................421 High/Low-Voltage Detect with External Input ..........274 AC (Timing) Characteristics .............................................438 MSSP (I2C Master Mode) ........................................215 Load Conditions for Device Timing MSSP (I2C Mode) ....................................................200 Specifications ...................................................439 MSSP (SPI Mode) ...................................................191 Parameter Symbology .............................................438 On-Chip Reset Circuit ................................................47 Temperature and Voltage Specifications .................439 PIC18F2480/2580 .....................................................12 Timing Conditions ....................................................439 PIC18F4480/4580 .....................................................13 Access Bank ......................................................................76 PLL (HS Mode) ..........................................................31 Mapping with Indexed Literal Offset Mode ...............100 PORTD and PORTE (Parallel Slave Port) ...............149 ACKSTAT ........................................................................221 PWM Operation (Simplified) ....................................173 ACKSTAT Status Flag .....................................................221 Reads From Flash Program Memory ......................105 ADCON0 Register ............................................................253 Single Comparator ...................................................265 GO/DONE Bit ...........................................................256 Table Read Operation .............................................101 ADCON1 Register ............................................................253 Table Write Operation .............................................102 ADCON2 Register ............................................................253 Table Writes to Flash Program Memory ..................107 ADDFSR ..........................................................................410 Timer0 in 16-Bit Mode .............................................152 ADDLW ............................................................................373 Timer0 in 8-Bit Mode ...............................................152 ADDULNK ........................................................................410 Timer1 .....................................................................156 ADDWF ............................................................................373 Timer1 (16-Bit Read/Write Mode) ............................156 ADDWFC .........................................................................374 Timer2 .....................................................................162 ADRESH Register ............................................................253 Timer3 .....................................................................164 ADRESL Register ....................................................253, 256 Timer3 (16-Bit Read/Write Mode) ............................164 Analog-to-Digital Converter. See A/D. Transmit Buffers ......................................................334 and BSR ...........................................................................100 Watchdog Timer ......................................................358 ANDLW ............................................................................374 Block Diagrams Comparator Analog Input Model ............267 ANDWF ............................................................................375 BN ....................................................................................376 Assembler BNC .................................................................................377 MPASM Assembler ..................................................418 BNN .................................................................................377 Auto-Wake-up on Sync Break Character .........................246 BNOV ..............................................................................378 B BNZ .................................................................................378 Bank Select Register (BSR) ...............................................73 BOR. See Brown-out Reset. Baud Rate Generator .......................................................217 BOV .................................................................................381 Baud Rate Generator (BRG) ............................................235 BRA .................................................................................379 BC ....................................................................................375 BRG. See Baud Rate Generator. BCF ..................................................................................376 Brown-out Reset (BOR) .....................................................50 BF ....................................................................................221 Detecting ...................................................................50 BF Status Flag .................................................................221 Disabling in Sleep Mode ............................................50 Software Enabled ......................................................50 © 2009 Microchip Technology Inc. DS39637D-page 475

PIC18F2480/2580/4480/4580 BSF ..................................................................................379 Transmitting a CAN Message Using WIN Bits .........292 BTFSC .............................................................................380 WIN and ICODE Bits Usage in Interrupt Service BTFSS ..............................................................................380 Routine to Access TX/RX Buffers ....................284 BTG ..................................................................................381 Writing to Flash Program Memory ...................108–109 BZ .....................................................................................382 Code Protection ...............................................................349 COMF ..............................................................................384 C Comparator ......................................................................263 C Compilers Analog Input Connection Considerations ................267 MPLAB C18 .............................................................418 Associated Registers ...............................................267 CALL ................................................................................382 Configuration ...........................................................264 CALLW .............................................................................411 Effects of a Reset ....................................................266 CAN Module Interrupts .................................................................266 External-Internal Clock in HS-PLL Operation .................................................................265 Based Oscillators .............................................339 Operation During Sleep ...........................................266 Capture (CCP Module) .....................................................169 Outputs ....................................................................265 Associated Registers ...............................................172 Reference ................................................................265 CCP1/ECCP1 Pin Configuration ..............................169 External Signal ................................................265 CCPR1H:CCPR1L Registers ...................................169 Internal Signal ..................................................265 Software Interrupt ....................................................169 Response Time ........................................................265 Timer1/Timer3 Mode Selection ................................169 Comparator Specifications ...............................................436 Capture (ECCP Module) ..................................................178 Comparator Voltage Reference .......................................269 Capture/Compare/PWM (CCP) ........................................167 Accuracy and Error ..................................................270 Capture Mode. See Capture. Associated Registers ...............................................271 CCP Mode and Timer Resources ............................168 Configuring ..............................................................269 CCPRxH Register ....................................................168 Connection Considerations ......................................270 CCPRxL Register .....................................................168 Effects of a Reset ....................................................270 Compare Mode. See Compare. Operation During Sleep ...........................................270 Interaction Between CCP1 and ECCP1 Compare (CCP Module) ..................................................171 for Timer Resources ........................................168 Associated Registers ...............................................172 Module Configuration ...............................................168 CCP Pin Configuration .............................................171 PWM Mode. See PWM. CCPR1 Register ......................................................171 Clock Sources ....................................................................34 Software Interrupt ....................................................171 Selecting the 31 kHz Source ......................................35 Special Event Trigger ..............................165, 171, 262 Selection Using OSCCON Register ...........................35 Timer1/Timer3 Mode Selection ................................171 Clocking Scheme/Instruction Cycle ....................................71 Compare (ECCP Module) ................................................178 CLRF ................................................................................383 Special Event Trigger ..............................................178 CLRWDT ..........................................................................383 Configuration Bits ............................................................349 Code Examples Configuration Mode .........................................................330 16 x 16 Signed Multiply Routine ..............................118 Configuration Register Protection ....................................366 16 x 16 Unsigned Multiply Routine ..........................118 Context Saving During Interrupts .....................................134 8 x 8 Signed Multiply Routine ..................................117 Conversion Considerations ..............................................472 8 x 8 Unsigned Multiply Routine ..............................117 CPFSEQ ..........................................................................384 Changing Between Capture Prescalers ...................169 CPFSGT ..........................................................................385 Changing to Configuration Mode .............................284 CPFSLT ...........................................................................385 Computed GOTO Using an Offset Value ...................70 Crystal Oscillator/Ceramic Resonator ................................29 Data EEPROM Read ...............................................113 Customer Change Notification Service ............................486 Data EEPROM Refresh Routine ..............................114 Customer Notification Service .........................................486 Data EEPROM Write ...............................................113 Customer Support ............................................................486 Erasing a Flash Program Memory Row ...................106 D Fast Register Stack ....................................................70 How to Clear RAM (Bank 1) Using Data Addressing Modes ....................................................95 Indirect Addressing ............................................95 Comparing Addressing Modes with the Implementing a Real-Time Clock Using Extended Instruction Set Enabled .....................99 a Timer1 Interrupt Service ...............................159 Direct .........................................................................95 Initializing PORTA ....................................................135 Indexed Literal Offset ................................................98 Initializing PORTB ....................................................138 Indirect .......................................................................95 Initializing PORTC ....................................................141 Inherent and Literal ....................................................95 Initializing PORTD ....................................................143 Data EEPROM Code Protection ......................................366 Initializing PORTE ....................................................146 Data EEPROM Memory ...................................................111 Loading the SSPBUF (SSPSR) Register .................194 Associated Registers ...............................................115 Reading a CAN Message ........................................299 EEADR Register ......................................................111 Reading a Flash Program Memory Word ................105 EECON1 and EECON2 Registers ...........................111 Saving STATUS, WREG and BSR Operation During Code-Protect ...............................114 Registers in RAM .............................................134 Protection Against Spurious Write ...........................114 Transmitting a CAN Message Using Reading ...................................................................113 Banked Method ................................................292 Using .......................................................................114 DS39637D-page 476 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 Write Verify ..............................................................113 Dedicated CAN Transmit Buffer Registers ..............288 Writing ......................................................................113 Disable Mode ...........................................................330 Data Memory .....................................................................73 Error Detection ........................................................344 Access Bank ..............................................................76 Acknowledge ...................................................344 and the Extended Instruction Set ...............................98 Bit ....................................................................344 Bank Select Register (BSR) .......................................73 CRC .................................................................344 General Purpose Registers ........................................76 Error Modes and Counters ..............................344 Map for PIC18F2480/4480 .........................................74 Error States .....................................................344 Map for PIC18F2580/4580 .........................................75 Form ................................................................344 Special Function Registers ........................................77 Stuff Bit ............................................................344 DAW .................................................................................386 Error Modes State (diagram) ...................................345 DC Characteristics ...........................................................433 Error Recognition Mode ...........................................331 Power-Down and Supply Current ............................424 Filter-Mask Truth (table) ..........................................336 Supply Voltage .........................................................423 Functional Modes ....................................................331 DCFSNZ ..........................................................................387 Mode 0 (Legacy Mode) ....................................331 DECF ...............................................................................386 Mode 1 (Enhanced Legacy Mode) ..................331 DECFSZ ...........................................................................387 Mode 2 (Enhanced FIFO Mode) ......................332 Development Support ......................................................417 Information Processing Time (IPT) ..........................341 Device Differences ...........................................................471 Lengthening a Bit Period .........................................343 Device Overview ..................................................................9 Listen Only Mode .....................................................331 Features (table) ..........................................................11 Loopback Mode .......................................................331 Device Reset Timers ..........................................................51 Message Acceptance Filters and Masks .........308, 336 Oscillator Start-up Timer (OST) .................................51 Message Acceptance Mask and PLL Lock Time-out .....................................................51 Filter Operation ................................................337 Power-up Timer (PWRT) ...........................................51 Message Reception .................................................335 Direct Addressing ...............................................................96 Enhanced FIFO Mode .....................................336 Priority .............................................................335 E Time-Stamping ................................................336 ECAN Module ..................................................................279 Normal Mode ...........................................................330 Baud Rate Setting ....................................................338 Oscillator Tolerance .................................................343 Bit Time Partitioning .................................................338 Overview ..................................................................279 Bit Timing Configuration Registers ..........................344 Phase Buffer Segments ...........................................341 Calculating TQ, Nominal Bit Rate and Programmable TX/RX and Auto-RTR Buffers .........300 Nominal Bit Time .............................................341 Programming Time Segments .................................343 CAN Baud Rate Registers .......................................317 Propagation Segment ..............................................341 CAN Control and Status Registers ..........................281 Sample Point ...........................................................341 CAN Controller Register Map ..................................325 Shortening a Bit Period ............................................343 CAN I/O Control Register .........................................320 Synchronization .......................................................342 CAN Interrupt Registers ...........................................321 Hard .................................................................342 CAN Interrupts .........................................................345 Resynchronization ...........................................342 Acknowledge ...................................................347 Rules ...............................................................342 Bus Activity Wake-up .......................................346 Synchronization Segment ........................................341 Bus-Off .............................................................347 Time Quanta ............................................................341 Code Bits .........................................................346 Values for ICODE (table) .........................................346 Error .................................................................346 ECCP Message Error .................................................346 Capture and Compare Modes .................................178 Receive ............................................................346 Standard PWM Mode ..............................................178 Receiver Bus Passive ......................................347 Effect on Standard Instructions ..........................................98 Receiver Overflow ...........................................347 Effect on Standard PIC Instructions .................................414 Receiver Warning ............................................347 Effects of Power-Managed Modes on Transmit ...........................................................346 Various Clock Sources ..............................................37 Transmitter Bus Passive ..................................347 Electrical Characteristics .................................................421 Transmitter Warning ........................................347 Enhanced Capture/Compare/PWM (ECCP) ....................177 CAN Message Buffers .............................................332 Capture Mode. See Capture (ECCP Module). Dedicated Receive ...........................................332 Outputs and Configuration .......................................178 Dedicated Transmit ..........................................332 Pin Configurations for ECCP Modes .......................178 Programmable Auto-RTR ................................333 PWM Mode. See PWM (ECCP Module). Programmable Transmit/Receive ....................332 Timer Resources .....................................................178 CAN Message Transmission ...................................333 Enhanced PWM Mode. See PWM (ECCP Module). .......179 Aborting ...........................................................333 Enhanced Universal Synchronous Receiver Initiating ...........................................................333 Transmitter (EUSART). See EUSART. Priority ..............................................................334 Equations CAN Modes of Operation .........................................330 A/D Acquisition Time ...............................................258 CAN Registers .........................................................281 A/D Minimum Charging Time ..................................258 Configuration Mode ..................................................330 Errata ...................................................................................7 Dedicated CAN Receive Buffer Registers ...............293 © 2009 Microchip Technology Inc. DS39637D-page 477

PIC18F2480/2580/4480/4580 Error Recognition Mode ...................................................330 G EUSART GOTO ..............................................................................388 Asynchronous Mode ................................................241 Associated Registers, Receive ........................245 H Associated Registers, Transmit .......................243 Hardware Multiplier Auto-Wake-up on Sync Break ..........................246 Introduction ..............................................................117 Break Character Sequence ..............................247 Operation .................................................................117 Receiver ...........................................................244 Performance Comparison ........................................117 Setting up 9-Bit Mode with Address Detect .....244 High/Low-Voltage Detect .................................................273 Transmitter .......................................................241 Applications .............................................................276 Baud Rate Generator (BRG) Associated Registers ...............................................277 Associated Registers .......................................236 Characteristics .........................................................437 Auto-Baud Rate Detect ....................................239 Current Consumption ...............................................275 Baud Rate Error, Calculating ...........................236 Effects of a Reset ....................................................277 Baud Rates, Asynchronous Modes ..................237 Operation .................................................................274 High Baud Rate Select (BRGH Bit) ..................235 During Sleep ....................................................277 Operation in Power-Managed Mode ................235 Setup .......................................................................275 Sampling ..........................................................235 Start-up Time ...........................................................275 Synchronous Master Mode ......................................248 Typical Application ...................................................276 Associated Registers, Receive ........................250 HLVD. See High/Low-Voltage Detect. .............................273 Associated Registers, Transmit .......................249 Reception .........................................................250 I Transmission ....................................................248 I/O Ports ...........................................................................135 Synchronous Slave Mode ........................................251 I2C Mode (MSSP) Associated Registers, Receive ........................252 Acknowledge Sequence Timing ..............................224 Associated Registers, Transmit .......................251 Baud Rate Generator ..............................................217 Reception .........................................................252 Bus Collision Transmission ....................................................251 During a Repeated Start Condition ..................228 Extended Instruction Set During a Stop Condition ..................................229 ADDFSR ..................................................................410 Clock Arbitration ......................................................218 ADDULNK ................................................................410 Clock Stretching .......................................................210 CALLW .....................................................................411 10-Bit Slave Receive Mode (SEN = 1) ............210 MOVSF ....................................................................411 10-Bit Slave Transmit Mode ............................210 MOVSS ....................................................................412 7-Bit Slave Receive Mode (SEN = 1) ..............210 PUSHL .....................................................................412 7-Bit Slave Transmit Mode ..............................210 SUBFSR ..................................................................413 Clock Synchronization and the CKP Bit SUBULNK ................................................................413 (SEN = 1) .........................................................211 External Clock Input ...........................................................30 Effect of a Reset ......................................................225 F General Call Address Support .................................214 I2C Clock Rate w/BRG .............................................217 Fail-Safe Clock Monitor ............................................349, 361 Master Mode ............................................................215 Interrupts in Power-Managed Modes .......................362 Operation .........................................................216 POR or Wake-up from Sleep ...................................362 Reception ........................................................221 WDT During Oscillator Failure .................................361 Repeated Start Condition Timing ....................220 Fast Register Stack ............................................................70 Start Condition .................................................219 Firmware Instructions .......................................................367 Transmission ...................................................221 Flash Program Memory ....................................................101 Transmit Sequence .........................................216 Associated Registers ...............................................109 Multi-Master Communication, Bus Collision Control Registers .....................................................102 and Arbitration .................................................225 EECON1 and EECON2 ...................................102 Multi-Master Mode ...................................................225 TABLAT (Table Latch) Register .......................104 Operation .................................................................204 TBLPTR (Table Pointer) Register ....................104 Read/Write Bit Information (R/W Bit) ...............204, 205 Erase Sequence ......................................................106 Registers .................................................................200 Erasing .....................................................................106 Serial Clock (RC3/SCK/SCL) ...................................205 Operation During Code-Protect ...............................109 Slave Mode ..............................................................204 Reading ....................................................................105 Addressing .......................................................204 Table Pointer Reception ........................................................205 Boundaries Based on Operation ......................104 Transmission ...................................................205 Table Pointer Boundaries ........................................104 Sleep Operation .......................................................225 Table Reads and Table Writes ................................101 Stop Condition Timing .............................................224 Write Sequence .......................................................107 ID Locations .............................................................349, 366 Writing To .................................................................107 INCF ................................................................................388 Protection Against Spurious Writes .................109 INCFSZ ............................................................................389 Unexpected Termination ..................................109 In-Circuit Debugger ..........................................................366 Write Verify ......................................................109 In-Circuit Serial Programming (ICSP) ......................349, 366 FSCM. See Fail-Safe Clock Monitor. DS39637D-page 478 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 Indexed Literal Offset Addressing Mode ..........................414 RESET .....................................................................397 and Standard PIC18 Instructions .............................414 RETFIE ....................................................................398 Indexed Literal Offset Mode .......................................98, 100 RETLW ....................................................................398 Indirect Addressing ............................................................96 RETURN ..................................................................399 INFSNZ ............................................................................389 RLCF .......................................................................399 Initialization Conditions for all Registers ......................55–66 RLNCF .....................................................................400 Instruction Cycle ................................................................71 RRCF .......................................................................400 Instruction Flow/Pipelining .................................................71 RRNCF ....................................................................401 Instruction Set ..................................................................367 SETF .......................................................................401 ADDLW ....................................................................373 SETF (Indexed Literal Offset mode) ........................415 ADDWF ....................................................................373 SLEEP .....................................................................402 ADDWF (Indexed Literal Offset mode) ....................415 Standard Instructions ...............................................367 ADDWFC .................................................................374 SUBFWB .................................................................402 ANDLW ....................................................................374 SUBLW ....................................................................403 ANDWF ....................................................................375 SUBWF ....................................................................403 BC ............................................................................375 SUBWFB .................................................................404 BCF ..........................................................................376 Summary Table .......................................................370 BN ............................................................................376 SWAPF ....................................................................404 BNC .........................................................................377 TBLRD .....................................................................405 BNN .........................................................................377 TBLWT ....................................................................406 BNOV .......................................................................378 TSTFSZ ...................................................................407 BNZ ..........................................................................378 XORLW ...................................................................407 BOV .........................................................................381 XORWF ...................................................................408 BRA ..........................................................................379 INTCON Registers ...........................................................121 BSF ..........................................................................379 Inter-Integrated Circuit. See I2C. BSF (Indexed Literal Offset mode) ..........................415 Internal Oscillator Block .....................................................32 BTFSC .....................................................................380 Adjustment .................................................................32 BTFSS .....................................................................380 INTIO Modes .............................................................32 BTG ..........................................................................381 INTOSC Output Frequency .......................................32 BZ ............................................................................382 OSCTUNE Register ...................................................32 CALL ........................................................................382 Internal RC Oscillator CLRF ........................................................................383 Use with WDT ..........................................................358 CLRWDT ..................................................................383 Internet Address ..............................................................486 COMF ......................................................................384 Interrupt Sources .............................................................349 CPFSEQ ..................................................................384 A/D Conversion Complete .......................................257 CPFSGT ..................................................................385 Capture Complete (CCP) ........................................169 CPFSLT ...................................................................385 Compare Complete (CCP) ......................................171 DAW .........................................................................386 ECAN Module ..........................................................345 DCFSNZ ..................................................................387 Interrupt-on-Change (RB7:RB4) ..............................138 DECF .......................................................................386 INTx Pin ...................................................................134 DECFSZ ...................................................................387 PORTB, Interrupt-on-Change ..................................134 Extended Instructions ..............................................409 TMR0 .......................................................................134 and Using MPLAB Tools ..................................416 TMR0 Overflow ........................................................153 Considerations when Enabling ........................414 TMR1 Overflow ........................................................155 Syntax ..............................................................409 TMR2 to PR2 Match (PWM) ............................173, 179 General Format ........................................................369 TMR3 Overflow ................................................163, 165 GOTO ......................................................................388 Interrupts .........................................................................119 INCF .........................................................................388 Logic (diagram) ........................................................120 INCFSZ ....................................................................389 INTOSC Frequency Drift ....................................................32 INFSNZ ....................................................................389 INTOSC, INTRC. See Internal Oscillator Block. IORLW .....................................................................390 IORLW .............................................................................390 IORWF .....................................................................390 IORWF .............................................................................390 LFSR ........................................................................391 IPR Registers ...................................................................130 MOVF .......................................................................391 L MOVFF ....................................................................392 MOVLB ....................................................................392 LFSR ...............................................................................391 MOVLW ...................................................................393 Listen Only Mode .............................................................330 MOVWF ...................................................................393 Loopback Mode ...............................................................330 MULLW ....................................................................394 Low-Voltage ICSP Programming See MULWF ....................................................................394 Single-Supply ICSP Programming. NEGF .......................................................................395 M NOP .........................................................................395 POP .........................................................................396 Master Clear Reset (MCLR) ..............................................49 PUSH .......................................................................396 Master Synchronous Serial Port (MSSP). See MSSP. RCALL .....................................................................397 © 2009 Microchip Technology Inc. DS39637D-page 479

PIC18F2480/2580/4480/4580 Memory Organization .........................................................67 PORTD ....................................................................149 Data Memory .............................................................73 RD (Read Input) .......................................................149 Program Memory .......................................................67 Select (PSPMODE Bit) ....................................143, 149 Memory Programming Requirements ..............................435 WR (Write Input) ......................................................149 Microchip Internet Web Site .............................................486 PIE Registers ...................................................................127 Migration from Baseline to Enhanced Devices ................472 Pin Functions Migration from High-End to Enhanced Devices ...............473 MCLR/VPP/RE3 ...................................................14, 18 Migration from Mid-Range to Enhanced Devices .............473 OSC1/CLKI/RA7 ..................................................14, 18 MOVF ...............................................................................391 OSC2/CLKO/RA6 ................................................14, 18 MOVFF .............................................................................392 RA0/AN0 ....................................................................15 MOVLB .............................................................................392 RA0/AN0/CVREF ........................................................19 MOVLW ............................................................................393 RA1/AN1 ..............................................................15, 19 MOVSF ............................................................................411 RA2/AN2/VREF- ...................................................15, 19 MOVSS ............................................................................412 RA3/AN3/VREF+ ..................................................15, 19 MOVWF ...........................................................................393 RA4/T0CKI ..........................................................15, 19 MPLAB ASM30 Assembler, Linker, Librarian ..................418 RA5/AN4/SS/HLVDIN ..........................................15, 19 MPLAB Integrated Development RB0/INT0/AN10 .........................................................16 Environment Software ..............................................417 RB0/INT0/FLT0/AN10 ................................................20 MPLAB PM3 Device Programmer ....................................420 RB1/INT1/AN8 .....................................................16, 20 MPLAB REAL ICE In-Circuit Emulator System ................419 RB2/INT2/CANTX ................................................16, 20 MPLINK Object Linker/MPLIB Object Librarian ...............418 RB3/CANRX ........................................................16, 20 MSSP RB4/KBI0/AN9 .....................................................16, 20 ACK Pulse ........................................................204, 205 RB5/KBI1/PGM ....................................................16, 20 Control Registers (general) ......................................191 RB6/KBI2/PGC ....................................................16, 20 I2C Mode. See I2C Mode. RB7/KBI3/PGD ....................................................16, 20 Module Overview .....................................................191 RC0/T1OSO/T13CKI ...........................................17, 21 SPI Master/Slave Connection ..................................195 RC1/T1OSI ..........................................................17, 21 SPI Mode. See SPI Mode. RC2/CCP1 ...........................................................17, 21 SSPBUF ...................................................................196 RC3/SCK/SCL .....................................................17, 21 SSPSR .....................................................................196 RC4/SDI/SDA ......................................................17, 21 MULLW ............................................................................394 RC5/SDO .............................................................17, 21 MULWF ............................................................................394 RC6/TX/CK ..........................................................17, 21 RC7/RX/DT ..........................................................17, 21 N RD0/PSP0/C1IN+ ......................................................22 NEGF ...............................................................................395 RD1/PSP1/C1IN- .......................................................22 NOP .................................................................................395 RD2/PSP2/C2IN+ ......................................................22 Normal Operation Mode ...................................................330 RD3/PSP3/C2IN- .......................................................22 RD4/PSP4/ECCP1/P1A .............................................22 O RD5/PSP5/P1B .........................................................22 Opcode Field Descriptions ...............................................368 RD6/PSP6/P1C .........................................................22 Oscillator Configuration ......................................................29 RD7/PSP7/P1D .........................................................22 EC ..............................................................................29 RE0/RD/AN5 ..............................................................23 ECIO ..........................................................................29 RE1/WR/AN6/C1OUT ................................................23 HS ..............................................................................29 RE2/CS/AN7/C2OUT .................................................23 HSPLL ........................................................................29 VDD ......................................................................17, 23 Internal Oscillator Block .............................................32 VSS ......................................................................17, 23 INTIO1 .......................................................................29 Pinout I/O Descriptions INTIO2 .......................................................................29 PIC18F2480/2580 .....................................................14 LP ...............................................................................29 PIC18F4480/4580 .....................................................18 RC ..............................................................................29 PIR Registers ...................................................................124 RCIO ..........................................................................29 PLL XT ..............................................................................29 Use with INTOSC ......................................................31 Oscillator Selection ..........................................................349 PLL Frequency Multiplier ...................................................31 Oscillator Start-up Timer (OST) ...................................37, 51 HSPLL Oscillator Mode .............................................31 Oscillator Switching ............................................................34 In INTOSC Modes .....................................................32 Oscillator Transitions ..........................................................35 PLL Lock Time-out .............................................................51 Oscillator, Timer1 .....................................................155, 165 POP .................................................................................396 Oscillator, Timer3 .............................................................163 POR. See Power-on Reset. P PORTA Associated Registers ...............................................137 Packaging Information .....................................................459 I/O Summary ............................................................136 Details ......................................................................461 LATA Register .........................................................135 Marking ....................................................................459 PORTA Register ......................................................135 Parallel Slave Port (PSP) .........................................143, 149 TRISA Register ........................................................135 Associated Registers ...............................................150 CS (Chip Select) ......................................................149 DS39637D-page 480 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 PORTB Prescaler, Timer0 ............................................................153 Associated Registers ...............................................140 Assignment (PSA Bit) ..............................................153 I/O Summary ............................................................139 Rate Select (T0PS2:T0PS0 Bits) .............................153 LATB Register ..........................................................138 Switching Between Timer0 and WDT ......................153 PORTB Register ......................................................138 Prescaler, Timer2 ............................................................174 TRISB Register ........................................................138 PRI_IDLE Mode .................................................................44 PORTC PRI_RUN Mode .................................................................40 Associated Registers ...............................................142 Program Counter ...............................................................68 I/O Summary ............................................................142 PCL, PCH and PCU Registers ..................................68 LATC Register .........................................................141 PCLATH and PCLATU Registers ..............................68 PORTC Register ......................................................141 Program Memory RC3/SCK/SCL Pin ...................................................205 and the Extended Instruction Set ..............................98 TRISC Register ........................................................141 Code Protection .......................................................364 PORTD Instructions ................................................................72 Associated Registers ...............................................145 Two-Word ..........................................................72 I/O Summary ............................................................144 Interrupt Vector ..........................................................67 LATD Register .........................................................143 Look-up Tables ..........................................................70 Parallel Slave Port (PSP) Function ..........................143 Map and Stack (diagram) ..........................................67 PORTD Register ......................................................143 Reset Vector ..............................................................67 TRISD Register ........................................................143 Program Verification and Code Protection ......................363 PORTE Associated Registers ...............................................364 Associated Registers ...............................................148 Programming, Device Instructions ...................................367 I/O Summary ............................................................148 PSP. See Parallel Slave Port. LATE Register ..........................................................146 Pulse-Width Modulation. See PWM (CCP Module) PORTE Register ......................................................146 and PWM (ECCP Module). PSP Mode Select (PSPMODE Bit) ..........................143 PUSH ...............................................................................396 TRISE Register ........................................................146 PUSH and POP Instructions ..............................................69 Postscaler, WDT PUSHL .............................................................................412 Assignment (PSA Bit) ..............................................153 PWM (CCP Module) ........................................................173 Rate Select (T0PS2:T0PS0 Bits) .............................153 Associated Registers ...............................................175 Switching Between Timer0 and WDT ......................153 Auto-Shutdown ........................................................174 Power-Managed Modes .....................................................39 CCPR1H:CCPR1L Registers ..................................173 and A/D Operation ...................................................260 Duty Cycle ...............................................................173 and EUSART Operation ...........................................235 Example Frequencies/Resolutions ..........................174 and Multiple Sleep Commands ..................................40 Period ......................................................................173 Clock Transitions and Status Indicators .....................40 Setup for PWM Operation .......................................174 Effects on Clock Sources ...........................................37 TMR2 to PR2 Match ................................................173 Entering ......................................................................39 PWM (ECCP Module) ......................................................179 Exiting Idle and Sleep Modes ....................................45 Associated Registers ...............................................190 by Interrupt .........................................................45 Direction Change in Full-Bridge Output Mode .........184 by Reset .............................................................45 Duty Cycle ...............................................................180 by WDT Time-out ...............................................45 ECCPR1H:ECCPR1L Registers ..............................179 Without an Oscillator Start-up Delay ..................46 Effects of a Reset ....................................................189 Idle Modes .................................................................43 Enhanced PWM Auto-Shutdown .............................186 PRI_IDLE ...........................................................44 Example Frequencies/Resolutions ..........................180 RC_IDLE ............................................................45 Full-Bridge Application Example ..............................184 SEC_IDLE .........................................................44 Full-Bridge Mode .....................................................183 Run Modes .................................................................40 Half-Bridge Mode .....................................................182 PRI_RUN ...........................................................40 Half-Bridge Output Mode Applications Example .....182 RC_RUN ............................................................41 Output Configurations ..............................................180 SEC_RUN ..........................................................40 Output Relationships (Active-High) .........................181 Selecting ....................................................................39 Output Relationships (Active-Low) ..........................181 Sleep Mode ................................................................43 Period ......................................................................179 Summary (table) ........................................................39 Programmable Dead-Band Delay ............................186 Power-on Reset (POR) ......................................................49 Start-up Considerations ...........................................188 Oscillator Start-up Timer (OST) .................................51 TMR2 to PR2 Match ................................................179 Power-up Timer (PWRT) ...........................................51 Q Time-out Sequence ....................................................51 Power-up Delays ................................................................37 Q Clock ....................................................................174, 180 Power-up Timer (PWRT) .............................................37, 51 R Prescaler Timer2 ......................................................................180 RAM. See Data Memory. Prescaler, Capture ...........................................................169 RC Oscillator ......................................................................31 RCIO Oscillator Mode ................................................31 © 2009 Microchip Technology Inc. DS39637D-page 481

PIC18F2480/2580/4480/4580 RC_IDLE Mode ..................................................................45 ECCP1AS (ECCP Auto-Shutdown Control) ............187 RC_RUN Mode ..................................................................41 ECCP1CON (Enhanced RCALL ..............................................................................397 Capture/Compare/PWM Control) ....................177 RCON Register ECCP1DEL (ECCP PWM Dead-Band Delay) .........187 Bit Status During Initialization ....................................54 EECON1 (Data EEPROM Control 1) ...............103, 112 Reader Response ............................................................487 HLVDCON (HLVD Control) ......................................273 Receiver Warning .............................................................347 INTCON (Interrupt Control) ......................................121 Register File .......................................................................76 INTCON2 (Interrupt Control 2) .................................122 Register File Summary .................................................83–93 INTCON3 (Interrupt Control 3) .................................123 Registers IPR1 (Peripheral Interrupt Priority 1) .......................130 ADCON0 (A/D Control 0) .........................................253 IPR2 (Peripheral Interrupt Priority 2) .......................131 ADCON1 (A/D Control 1) .........................................254 IPR3 (Peripheral Interrupt Priority 3) ...............132, 323 ADCON2 (A/D Control 2) .........................................255 MSEL0 (Mask Select 0) ...........................................313 BAUDCON (Baud Rate Control) ..............................234 MSEL1 (Mask Select 1) ...........................................314 BIE0 (Buffer Interrupt Enable 0) ...............................324 MSEL2 (Mask Select 2) ...........................................315 BnCON (TX/RX Buffer n Control, MSEL3 (Mask Select 3) ...........................................316 Receive Mode) .................................................300 OSCCON (Oscillator Control) ....................................36 BnCON (TX/RX Buffer n Control, OSCTUNE (Oscillator Tuning) ...................................33 Transmit Mode) ................................................301 PIE1 (Peripheral Interrupt Enable 1) ........................127 BnDLC (TX/RX Buffer n Data Length Code PIE2 (Peripheral Interrupt Enable 2) ........................128 in Receive Mode) .............................................306 PIE3 (Peripheral Interrupt Enable 3) ................129, 322 BnDLC (TX/RX Buffer n Data Length Code PIR1 (Peripheral Interrupt Request (Flag) 1) ...........124 in Transmit Mode) ............................................307 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........125 BnDm (TX/RX Buffer n Data Field Byte m PIR3 (Peripheral Interrupt Request (Flag) 3) ...126, 321 in Receive Mode) .............................................305 RCON (Reset Control) .......................................48, 133 BnDm (TX/RX Buffer n Data Field Byte m RCSTA (Receive Status and Control) .....................233 in Transmit Mode) ............................................305 RXB0CON (Receive Buffer 0 Control) .....................293 BnEIDH (TX/RX Buffer n Extended Identifier, RXB1CON (Receive Buffer 1 Control) .....................295 High Byte in Receive Mode) ............................304 RXBnDLC (Receive Buffer n BnEIDH (TX/RX Buffer n Extended Identifier, Data Length Code) ..........................................298 High Byte in Transmit Mode) ...........................304 RXBnDm (Receive Buffer n Data Field Byte m) ......298 BnEIDL (TX/RX Buffer n Extended Identifier, RXBnEIDH (Receive Buffer n Low Byte in Receive Mode) .....................304, 305 Extended Identifier, High Byte) ........................297 BnSIDH (TX/RX Buffer n Standard Identifier, RXBnEIDL (Receive Buffer n High Byte in Receive Mode) ............................302 Extended Identifier, Low Byte) .........................297 BnSIDH (TX/RX Buffer n Standard Identifier, RXBnSIDH (Receive Buffer n High Byte in Transmit Mode) ...........................302 Standard Identifier, High Byte) ........................296 BnSIDL (TX/RX Buffer n Standard Identifier, RXBnSIDL (Receive Buffer n Low Byte in Receive Mode) .............................303 Standard Identifier, Low Byte) .........................297 BRGCON1 (Baud Rate Control 1) ...........................317 RXERRCNT (Receive Error Count) .........................299 BRGCON2 (Baud Rate Control 2) ...........................318 RXFBCONn (Receive Filter Buffer Control n) ..........312 BRGCON3 (Baud Rate Control 3) ...........................319 RXFCONn (Receive Filter Control n) .......................311 BSEL0 (Buffer Select 0) ...........................................307 RXFnEIDH (Receive Acceptance Filter n CANCON (CAN Control) ..........................................282 Extended Identifier, High Byte) ........................309 CANSTAT (CAN Status) ..........................................283 RXFnEIDL (Receive Acceptance Filter n CCP1CON (Capture/Compare/PWM Control) .........167 Extended Identifier, Low Byte) .........................309 CIOCON (CAN I/O Control) .....................................320 RXFnSIDH (Receive Acceptance Filter n CMCON (Comparator Control) ................................263 Standard Identifier Filter, High Byte) ...............308 COMSTAT (CAN Communication Status) ...............287 RXFnSIDL (Receive Acceptance Filter n CONFIG1H (Configuration 1 High) ..........................350 Standard Identifier Filter, Low Byte) ................308 CONFIG2H (Configuration 2 High) ..........................352 RXMnEIDH (Receive Acceptance Mask n CONFIG2L (Configuration 2 Low) ............................351 Extended Identifier Mask, High Byte) ..............310 CONFIG3H (Configuration 3 High) ..........................353 RXMnEIDL (Receive Acceptance Mask n CONFIG4L (Configuration 4 Low) ............................353 Extended Identifier Mask, Low Byte) ...............310 CONFIG5H (Configuration 5 High) ..........................354 RXMnSIDH (Receive Acceptance Mask n CONFIG5L (Configuration 5 Low) ............................354 Standard Identifier Mask, High Byte) ...............309 CONFIG6H (Configuration 6 High) ..........................355 RXMnSIDL (Receive Acceptance Mask n CONFIG6L (Configuration 6 Low) ............................355 Standard Identifier Mask, Low Byte) ................310 CONFIG7H (Configuration 7 High) ..........................356 SDFLC (Standard Data Bytes Filter CONFIG7L (Configuration 7 Low) ............................356 Length Count) ..................................................311 CVRCON (Comparator Voltage SSPCON1 (MSSP Control 1, I2C Mode) .................202 Reference Control) ...........................................269 SSPCON1 (MSSP Control 1, SPI Mode) .................193 DEVID1 (Device ID 1) ..............................................357 SSPCON2 (MSSP Control 2, I2C Mode) .................203 DEVID2 (Device ID 2) ..............................................357 SSPSTAT (MSSP Status, I2C Mode) ......................201 ECANCON (Enhanced CAN Control) ......................286 SSPSTAT (MSSP Status, SPI Mode) ......................192 DS39637D-page 482 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 STATUS .....................................................................94 Enabling SPI I/O ......................................................195 STKPTR (Stack Pointer) ............................................69 Master Mode ............................................................196 T0CON (Timer0 Control) ..........................................151 Master/Slave Connection ........................................195 T1CON (Timer 1 Control) .........................................155 Operation .................................................................194 T2CON (Timer2 Control) ..........................................161 Operation in Power-Managed Modes ......................199 T3CON (Timer3 Control) ..........................................163 Serial Clock .............................................................191 TRISE (PORTE/PSP Control) ..................................147 Serial Data In ...........................................................191 TXBIE (Transmit Buffers Interrupt Enable) ..............324 Serial Data Out ........................................................191 TXBnCON (Transmit Buffer n Control) ....................288 Slave Mode ..............................................................197 TXBnDLC (Transmit Buffer n Slave Select .............................................................191 Data Length Code) ..........................................291 Slave Select Synchronization ..................................197 TXBnDm (Transmit Buffer n Data Field Byte m) ......290 SPI Clock .................................................................196 TXBnEIDH (Transmit Buffer n Extended Typical Connection ..................................................195 Identifier, High Byte) ........................................289 SS ....................................................................................191 TXBnEIDL (Transmit Buffer n Extended SSPOV ............................................................................221 Identifier, Low Byte) .........................................290 SSPOV Status Flag .........................................................221 TXBnSIDH (Transmit Buffer n Standard SSPSTAT Register Identifier, High Byte) ........................................289 R/W Bit ............................................................204, 205 TXBnSIDL (Transmit Buffer n Standard Stack Full/Underflow Resets ..............................................70 Identifier, Low Byte) .........................................289 STATUS Register ..............................................................94 TXERRCNT (Transmit Error Count) ........................291 SUBFSR ..........................................................................413 TXSTA (Transmit Status and Control) .....................232 SUBFWB .........................................................................402 WDTCON (Watchdog Timer Control) ......................359 SUBLW ............................................................................403 RESET .............................................................................397 SUBULNK ........................................................................413 Resets ........................................................................47, 349 SUBWF ............................................................................403 Brown-out Reset (BOR) ...........................................349 SUBWFB .........................................................................404 Oscillator Start-up Timer (OST) ...............................349 SWAPF ............................................................................404 Power-on Reset (POR) ............................................349 T Power-up Timer (PWRT) .........................................349 RETFIE ............................................................................398 T0CON Register RETLW ............................................................................398 PSA Bit ....................................................................153 RETURN ..........................................................................399 T0CS Bit ..................................................................152 Return Address Stack ........................................................68 T0PS2:T0PS0 Bits ...................................................153 and Associated Registers ..........................................68 T0SE Bit ..................................................................152 Return Stack Pointer (STKPTR) ........................................69 Table Pointer Operations (table) ......................................104 Revision History ...............................................................471 Table Reads/Table Writes .................................................70 RLCF ................................................................................399 TBLRD .............................................................................405 RLNCF .............................................................................400 TBLWT ............................................................................406 RRCF ...............................................................................400 Time-out in Various Situations (table) ................................51 RRNCF ............................................................................401 Timer0 .............................................................................151 16-Bit Mode Reads and Writes ................................152 S Associated Registers ...............................................153 SCK ..................................................................................191 Clock Source Edge Select (T0SE Bit) .....................152 SDI ...................................................................................191 Clock Source Select (T0CS Bit) ..............................152 SDO .................................................................................191 Operation .................................................................152 SEC_IDLE Mode ................................................................44 Overflow Interrupt ....................................................153 SEC_RUN Mode ................................................................40 Prescaler. See Prescaler, Timer0. Serial Clock, SCK ............................................................191 Timer1 .............................................................................155 Serial Data In (SDI) ..........................................................191 16-Bit Read/Write Mode ..........................................157 Serial Data Out (SDO) .....................................................191 Associated Registers ...............................................159 Serial Peripheral Interface. See SPI Mode. Interrupt ...................................................................158 SETF ................................................................................401 Operation .................................................................156 Slave Select (SS) .............................................................191 Oscillator ..........................................................155, 157 SLEEP .............................................................................402 Oscillator Layout Considerations .............................158 Sleep Overflow Interrupt ....................................................155 OSC1 and OSC2 Pin States ......................................37 Resetting, Using a Special Event Trigger Software Simulator (MPLAB SIM) ....................................419 Output (CCP) ..................................................158 Special Event Trigger. See Compare (ECCP Mode). Special Event Trigger (ECCP) .................................178 Special Event Trigger. See Compare (ECCP Module). TMR1H Register ......................................................155 Special Features of the CPU ...........................................349 TMR1L Register ......................................................155 Special Function Registers ................................................77 Use as a Real-Time Clock .......................................158 Map ......................................................................77–82 Timer2 .............................................................................161 SPI Mode (MSSP) Associated Registers ...............................................162 Associated Registers ...............................................199 Interrupt ...................................................................162 Bus Mode Compatibility ...........................................199 Operation .................................................................161 Effects of a Reset .....................................................199 Output ......................................................................162 © 2009 Microchip Technology Inc. DS39637D-page 483

PIC18F2480/2580/4480/4580 PR2 Register ....................................................173, 179 I2C Slave Mode General Call Address Sequence TMR2 to PR2 Match Interrupt ..........................173, 179 (7 or 10-Bit Address Mode) .............................214 Timer3 ..............................................................................163 Low-Voltage Detect (VDIRMAG = 0) .......................275 16-Bit Read/Write Mode ...........................................165 Master SSP I2C Bus Data ........................................453 Associated Registers .......................................165, 172 Master SSP I2C Bus Start/Stop Bits ........................453 Operation .................................................................164 Parallel Slave Port (PIC18F4480/4580) ...................446 Oscillator ..........................................................163, 165 Parallel Slave Port (PSP) Read ...............................150 Overflow Interrupt ............................................163, 165 Parallel Slave Port (PSP) Write ...............................150 Special Event Trigger (CCP) ....................................165 PWM Auto-Shutdown (PRSEN = 0, TMR3H Register ......................................................163 Auto-Restart Disabled) ....................................188 TMR3L Register .......................................................163 PWM Auto-Shutdown (PRSEN = 1, Timing Diagrams Auto-Restart Enabled) .....................................188 A/D Conversion ........................................................457 PWM Direction Change ...........................................185 Acknowledge Sequence ..........................................224 PWM Direction Change at Near Asynchronous Reception .........................................245 100% Duty Cycle .............................................185 Asynchronous Transmission ....................................242 PWM Output ............................................................173 Asynchronous Transmission (Back-to-Back) ...........242 Repeat Start Condition ............................................220 Automatic Baud Rate Calculation ............................240 Reset, Watchdog Timer (WDT), Oscillator Start-up Auto-Wake-up Bit (WUE) During Timer (OST) and Power-up Timer (PWRT) .....443 Normal Operation .............................................246 Send Break Character Sequence ............................247 Auto-Wake-up Bit (WUE) During Sleep ...................246 Slave Synchronization .............................................197 Baud Rate Generator with Clock Arbitration ............218 Slow Rise Time (MCLR Tied to VDD, BRG Overflow Sequence .........................................240 VDD Rise > TPWRT) ............................................53 BRG Reset Due to SDA Arbitration During SPI Mode (Master Mode) .........................................196 Start Condition .................................................227 SPI Mode (Slave Mode with CKE = 0) .....................198 Brown-out Reset (BOR) ...........................................443 SPI Mode (Slave Mode with CKE = 1) .....................198 Bus Collision During a Repeated Start Stop Condition Receive or Transmit Mode ..............224 Condition (Case 1) ...........................................228 Synchronous Reception (Master Mode, SREN) ......250 Bus Collision During a Repeated Start Synchronous Transmission .....................................248 Condition (Case 2) ...........................................228 Synchronous Transmission (Through TXEN) ..........249 Bus Collision During a Start Condition Time-out Sequence on POR w/ PLL (SCL = 0) .........................................................227 Enabled (MCLR Tied to VDD) ............................53 Bus Collision During a Start Condition Time-out Sequence on Power-up (SDA only) ........................................................226 (MCLR Not Tied to VDD), Case 1 ......................52 Bus Collision During a Stop Condition Time-out Sequence on Power-up (Case 1) ...........................................................229 (MCLR Not Tied to VDD), Case 2 ......................52 Bus Collision During a Stop Condition Time-out Sequence on Power-up (Case 2) ...........................................................229 (MCLR Tied to VDD, VDD Rise Tpwrt) ................52 Bus Collision for Transmit and Acknowledge ...........225 Timer0 and Timer1 External Clock ..........................444 Capture/Compare/PWM (CCP) ................................445 Transition for Entry to Idle Mode ................................44 CLKO and I/O ..........................................................442 Transition for Entry to SEC_RUN Mode ....................41 Clock Synchronization .............................................211 Transition for Entry to Sleep Mode ............................43 EUSART Synchronous Receive (Master/Slave) ......455 Transition for Two-Speed Start-up EUSART Synchronous Transmission (INTOSC to HSPLL) ........................................360 (Master/Slave) ..................................................455 Transition for Wake From Idle to Run Mode ..............44 Example SPI Master Mode (CKE = 0) .....................447 Transition for Wake From Sleep (HSPLL) .................43 Example SPI Master Mode (CKE = 1) .....................448 Transition From RC_RUN Mode to Example SPI Slave Mode (CKE = 0) .......................449 PRI_RUN Mode .................................................42 Example SPI Slave Mode (CKE = 1) .......................450 Transition From SEC_RUN Mode to External Clock (All Modes except PLL) ....................440 PRI_RUN Mode (HSPLL) ..................................41 Fail-Safe Clock Monitor ............................................362 Transition to RC_RUN Mode .....................................42 First Start Bit Timing ................................................219 Timing Diagrams and Specifications ...............................440 Full-Bridge PWM Output ..........................................183 A/D Conversion Requirements ................................457 Half-Bridge PWM Output .........................................182 AC Characteristics High-Voltage Detect (VDIRMAG = 1) .......................276 Internal RC Accuracy .......................................441 I2C Bus Data ............................................................451 Capture/Compare/PWM Requirements ...................445 I2C Bus Start/Stop Bits .............................................451 CLKO and I/O Requirements ...................................442 I2C Master Mode (7 or 10-Bit Transmission) ...........222 EUSART Synchronous Receive Requirements .......455 I2C Master Mode (7-Bit Reception) ..........................223 EUSART Synchronous Transmission I2C Slave Mode (10-Bit Reception, SEN = 0) ..........208 Requirements ..................................................455 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........213 I2C Slave Mode (10-Bit Transmission) .....................209 I2C Slave Mode (7-Bit Reception, SEN = 0) ............206 I2C Slave Mode (7-Bit Reception, SEN = 1) ............212 I2C Slave Mode (7-Bit Transmission) .......................207 DS39637D-page 484 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 Example SPI Mode Requirements V Master Mode, CKE = 0 ....................................447 Voltage Reference Specifications ....................................436 Master Mode, CKE = 1 ....................................448 Slave Mode, CKE = 0 ......................................449 W Slave Mode, CKE = 1 ......................................450 Watchdog Timer (WDT) ...........................................349, 358 External Clock Requirements ..................................440 Associated Registers ...............................................359 High/Low-Voltage Detect Characteristics ................437 Control Register .......................................................358 I2C Bus Data Requirements (Slave Mode) ..............452 During Oscillator Failure ..........................................361 Master SSP I2C Bus Data Requirements ................454 Programming Considerations ..................................358 Master SSP I2C Bus Start/Stop Bits WCOL ......................................................219, 220, 221, 224 Requirements ..................................................453 WCOL Status Flag ...................................219, 220, 221, 224 Parallel Slave Port Requirements WWW Address ................................................................486 (PIC18F4480/4580) ........................................446 WWW, On-Line Support ......................................................7 PLL Clock .................................................................441 Reset, Watchdog Timer, Oscillator Start-up X Timer, Power-up Timer and Brown-out XORLW ...........................................................................407 Reset Requirements ........................................443 XORWF ...........................................................................408 Timer0 and Timer1 External Clock Requirements ........................................444 Top-of-Stack Access ..........................................................68 TRISE Register PSPMODE Bit ..........................................................143 TSTFSZ ...........................................................................407 Two-Speed Start-up .................................................349, 360 Two-Word Instructions Example Cases ..........................................................72 TXSTA Register BRGH Bit .................................................................235 © 2009 Microchip Technology Inc. DS39637D-page 485

PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 486 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39637D-page 487

PIC18F2480/2580/4480/4580 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2480/2580/4480/4580 Literature Number: DS39637D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39637D-page 488 © 2009 Microchip Technology Inc.

PIC18F2480/2580/4480/4580 PIC18F2480/2580/4480/4580 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18F4580-I/P 301 = Industrial temp., PDIP Range package, Extended VDD limits, QTP pattern #301. b) PIC18F2580-I/SO = Industrial temp., SOIC package, Extended VDD limits. Device PIC18F2480/2580(1), PIC18F4480/4580 (1), c) PIC18F45805-I/P = Industrial temp., PDIP PIC18F2480/2580T (2), PIC18F4480/4580T (2); package, normal VDD limits. VDD range 4.2V to 5.5V PIC18LF2480/2580(1), PIC18LF4480/4580(1), PIC18LF2480/25800T(2), PIC18LF4480/4580T(2); VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package PT = TQFP (Thin Quad Flatpack) SO = SOIC Note1: F = Standard Voltage Range SP = SPDIP (Skinny Plastic DIP) LF = Wide Voltage Range P = PDIP 2: T = in tape and reel ML = QFN Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) © 2009 Microchip Technology Inc. DS39637D-page 489

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4080 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://support.microchip.com Web Address: Fax: 852-2401-3431 India - Pune France - Paris www.microchip.com Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 ADtullaunthta, GA Fax: 61-2-9868-6755 Japan - Yokohama Germany - Munich Tel: 678-957-9614 China - Beijing Tel: 81-45-471- 6166 Tel: 49-89-627-144-0 Tel: 86-10-8528-2100 Fax: 49-89-627-144-44 Fax: 678-957-1455 Fax: 81-45-471-6122 Fax: 86-10-8528-2104 Italy - Milan Boston Korea - Daegu Westborough, MA China - Chengdu Tel: 82-53-744-4301 Tel: 39-0331-742611 Tel: 774-760-0087 Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781 Fax: 774-760-0088 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Chicago China - Hong Kong SAR Tel: 82-2-554-7200 Tel: 31-416-690399 Itasca, IL Tel: 852-2401-1200 Fax: 82-2-558-5932 or Fax: 31-416-690340 Tel: 630-285-0071 Fax: 852-2401-3431 82-2-558-5934 Spain - Madrid Fax: 630-285-0075 China - Nanjing Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Cleveland Tel: 86-25-8473-2460 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Independence, OH Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 UK - Wokingham Tel: 216-447-0464 China - Qingdao Malaysia - Penang Tel: 44-118-921-5869 Fax: 216-447-0643 Tel: 86-532-8502-7355 Tel: 60-4-227-8870 Fax: 44-118-921-5820 Dallas Fax: 86-532-8502-7205 Fax: 60-4-227-4068 Addison, TX China - Shanghai Philippines - Manila Tel: 972-818-7423 Tel: 86-21-5407-5533 Tel: 63-2-634-9065 Fax: 972-818-2924 Fax: 86-21-5407-5066 Fax: 63-2-634-9069 Detroit China - Shenyang Singapore Farmington Hills, MI Tel: 86-24-2334-2829 Tel: 65-6334-8870 Tel: 248-538-2250 Fax: 86-24-2334-2393 Fax: 65-6334-8850 Fax: 248-538-2260 China - Shenzhen Taiwan - Hsin Chu Kokomo Tel: 86-755-8203-2660 Tel: 886-3-6578-300 Kokomo, IN Fax: 86-755-8203-1760 Fax: 886-3-6578-370 Tel: 765-864-8360 Fax: 765-864-8387 China - Wuhan Taiwan - Kaohsiung Tel: 86-27-5980-5300 Tel: 886-7-536-4818 Los Angeles Fax: 86-27-5980-5118 Fax: 886-7-536-4803 Mission Viejo, CA Tel: 949-462-9523 China - Xiamen Taiwan - Taipei Tel: 86-592-2388138 Tel: 886-2-2500-6610 Fax: 949-462-9608 Fax: 86-592-2388130 Fax: 886-2-2508-0102 Santa Clara China - Xian Thailand - Bangkok Santa Clara, CA Tel: 408-961-6444 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Fax: 408-961-6445 Fax: 86-29-8833-7256 Fax: 66-2-694-1350 China - Zhuhai Toronto Mississauga, Ontario, Tel: 86-756-3210040 Canada Fax: 86-756-3210049 Tel: 905-673-0699 Fax: 905-673-6509 03/26/09 DS39637D-page 490 © 2009 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F2480-E/ML PIC18F2480-E/SO PIC18F2480-E/SP PIC18F2480-I/ML PIC18F2480-I/SO PIC18F2480-I/SP PIC18F2480T-I/ML PIC18F2480T-I/SO PIC18F2580-E/ML PIC18F2580-E/SO PIC18F2580-E/SP PIC18F2580-I/ML PIC18F2580-I/SO PIC18F2580-I/SP PIC18F2580T-I/ML PIC18F2580T-I/SO PIC18F4480-E/ML PIC18F4480-E/P PIC18F4480-E/PT PIC18F4480-I/P PIC18F4480-I/PT PIC18F4480T-I/ML PIC18F4480T-I/PT PIC18F4580-E/ML PIC18F4580-E/P PIC18F4580-E/PT PIC18F4580-I/ML PIC18F4580-I/P PIC18F4580-I/PT PIC18F4580T-I/ML PIC18F4580T-I/PT PIC18LF2480-I/ML PIC18LF2480-I/SO PIC18LF2480-I/SP PIC18LF2480T-I/ML PIC18LF2480T- I/SO PIC18LF2580-I/ML PIC18LF2580-I/SO PIC18LF2580-I/SP PIC18LF2580T-I/ML PIC18LF2580T-I/SO PIC18LF4480-I/ML PIC18LF4480-I/P PIC18LF4480-I/PT PIC18LF4480T-I/ML PIC18LF4480T-I/PT PIC18LF4580- I/ML PIC18LF4580-I/P PIC18LF4580-I/PT PIC18LF4580T-I/ML PIC18LF4580T-I/PT PIC18F4480-I/ML