PIC18FXX2 Data Sheet High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D © 2006 Microchip Technology Inc. DS39564C

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR registered trademarks of Microchip Technology Incorporated WARRANTIES OF ANY KIND WHETHER EXPRESS OR in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, hold harmless Microchip from any and all damages, claims, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active suits, or expenses resulting from such use. No licenses are Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, conveyed, implicitly or otherwise, under any Microchip PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39564C-page ii © 2006 Microchip Technology Inc.

PIC18FXX2 28/40-pin High Performance, Enhanced FLASH Microcontrollers with 10-Bit A/D High Performance RISC CPU: Peripheral Features (Continued): (cid:129) C compiler optimized architecture/instruction set (cid:129) Addressable USART module: - Source code compatible with the PIC16 and - Supports RS-485 and RS-232 PIC17 instruction sets (cid:129) Parallel Slave Port (PSP) module (cid:129) Linear program memory addressing to 32 Kbytes Analog Features: (cid:129) Linear data memory addressing to 1.5Kbytes (cid:129) Compatible 10-bit Analog-to-Digital Converter On-Chip Program Memory On-Chip Data module (A/D) with: Device RAM EEPROM - Fast sampling rate FLASH # Single Word (bytes) (bytes) - Conversion available during SLEEP (bytes) Instructions - Linearity ≤ 1 LSb PIC18F242 16K 8192 768 256 (cid:129) Programmable Low Voltage Detection (PLVD) PIC18F252 32K 16384 1536 256 - Supports interrupt on-Low Voltage Detection PIC18F442 16K 8192 768 256 (cid:129) Programmable Brown-out Reset (BOR) PIC18F452 32K 16384 1536 256 Special Microcontroller Features: (cid:129) Up to 10 MIPs operation: - DC - 40 MHz osc./clock input (cid:129) 100,000 erase/write cycle Enhanced FLASH - 4 MHz - 10 MHz osc./clock input with PLL active program memory typical (cid:129) 16-bit wide instructions, 8-bit wide data path (cid:129) 1,000,000 erase/write cycle Data EEPROM (cid:129) Priority levels for interrupts memory (cid:129) 8 x 8 Single Cycle Hardware Multiplier (cid:129) FLASH/Data EEPROM Retention: > 40 years (cid:129) Self-reprogrammable under software control Peripheral Features: (cid:129) Power-on Reset (POR), Power-up Timer (PWRT) (cid:129) High current sink/source 25 mA/25 mA and Oscillator Start-up Timer (OST) (cid:129) Three external interrupt pins (cid:129) Watchdog Timer (WDT) with its own On-Chip RC (cid:129) Timer0 module: 8-bit/16-bit timer/counter with Oscillator for reliable operation 8-bit programmable prescaler (cid:129) Programmable code protection (cid:129) Timer1 module: 16-bit timer/counter (cid:129) Power saving SLEEP mode (cid:129) Timer2 module: 8-bit timer/counter with 8-bit (cid:129) Selectable oscillator options including: period register (time-base for PWM) - 4X Phase Lock Loop (of primary oscillator) (cid:129) Timer3 module: 16-bit timer/counter - Secondary Oscillator (32 kHz) clock input (cid:129) Secondary oscillator clock option - Timer1/Timer3 (cid:129) Single supply 5V In-Circuit Serial Programming™ (cid:129) Two Capture/Compare/PWM (CCP) modules. (ICSP™) via two pins CCP pins that can be configured as: (cid:129) In-Circuit Debug (ICD) via two pins - Capture input: capture is 16-bit, CMOS Technology: max. resolution 6.25 ns (TCY/16) - Compare is 16-bit, max. resolution 100 ns (TCY) (cid:129) Low power, high speed FLASH/EEPROM - PWM output: PWM resolution is 1- to 10-bit, technology max. PWM freq. @: 8-bit resolution = 156 kHz (cid:129) Fully static design 10-bit resolution = 39 kHz (cid:129) Wide operating voltage range (2.0V to 5.5V) (cid:129) Master Synchronous Serial Port (MSSP) module, (cid:129) Industrial and Extended temperature ranges Two modes of operation: (cid:129) Low power consumption: - 3-wire SPI™ (supports all 4 SPI modes) - < 1.6 mA typical @ 5V, 4 MHz - I2C™ Master and Slave mode - 25 μA typical @ 3V, 32 kHz - < 0.2 μA typical standby current © 2006 Microchip Technology Inc. DS39564C-page 1

PIC18FXX2 Pin Diagrams +F-F EE RR PLCC N3/VN2/VN1N0VPP GDGCGM AAAAR/ PPP A3/A2/A1/A0/CLCB7/B6/B5/B4C RRRRMNRRRRN 65432143210 RA4/T0CKI 7 4444439 RB3/CCP2* RA5/AN4/SS/LVDIN 8 38 RB2/INT2 RE0/RD/AN5 9 37 RB1/INT1 RE1/WR/AN6 10 PIC18F442 36 RB0/INT0 RE2/CS/AN7 11 35 VDD VDD 12 PIC18F452 34 VSS VSS 13 33 RD7/PSP7 OSC1/CLKI 14 32 RD6/PSP6 OSC2/CLKO/RA6 15 31 RD5/PSP5 RC0/T1OSO/T1CKI 16 30 RD4/PSP4 NC 17 29 RC7/RX/DT 11222222222 89012345678 RRRRRRRRRRN CCCDDDDCCCC 1230123456 /T/C/S/P/P/P/P/S/S/T 1CCSSSSDDX OSI/CCP1K/SCLP0P1P2P3I/SDAO/CK P 2 * * 2 P X/CKDODI/SDASP3SP2SP1SP0CK/SCLCP11OSI/CC TSSPPPPSCT 6/5/4/3/2/1/0/3/2/1/ CCCDDDDCCCC RRRRRRRRRRN TQFP 43210987654 44444333333 RC7/RX/DT 1 33 NC RD4/PSP4 2 32 RC0/T1OSO/T1CKI RD5/PSP5 3 31 OSC2/CLKO/RA6 RD6/PSP6 4 30 OSC1/CLKI RD7/PSP7 5 PIC18F442 29 VSS VSS 6 28 VDD VDD 7 PIC18F452 27 RE2/AN7/CS RB0/INT0 8 26 RE1/AN6/WR RB1/INT1 9 25 RE0/AN5/RD RB2/INT2 10 24 RA5/AN4/SS/LVDIN RB3/CCP2* 11 23 RA4/T0CKI 11111111222 23456789012 NNRRRRMRRRR CCBBBBCAAAA 45/P6/P7/PLR0/A1/A2/A3/A GGG/VNNNN MCDPP012/V3/V RR EE FF -+ * RB3 is the alternate pin for the CCP2 pin multiplexing. DS39564C-page 2 © 2006 Microchip Technology Inc.

PIC18FXX2 Pin Diagrams (Cont.’d) DIP MCLR/VPP 1 40 RB7/PGD RA0/AN0 2 39 RB6/PGC RA1/AN1 3 38 RB5/PGM RA2/AN2/VREF- 4 37 RB4 RA3/AN3/VREF+ 5 36 RB3/CCP2* RA4/T0CKI 6 35 RB2/INT2 RA5/AN4/SS/LVDIN 7 34 RB1/INT1 2 2 RE0/RD/AN5 8 4 5 33 RB0/INT0 RE1/WR/AN6 9 F4 F4 32 VDD RE2/CS/AN7 10 8 8 31 VSS VDD 11 C1 C1 30 RD7/PSP7 VSS 12 PI PI 29 RD6/PSP6 OSC1/CLKI 13 28 RD5/PSP5 OSC2/CLKO/RA6 14 27 RD4/PSP4 RC0/T1OSO/T1CKI 15 26 RC7/RX/DT RC1/T1OSI/CCP2* 16 25 RC6/TX/CK RC2/CCP1 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2 Note: Pin compatible with 40-pin PIC16C7X devices. DIP, SOIC MCLR/VPP 1 28 RB7/PGD RA0/AN0 2 27 RB6/PGC RA1/AN1 3 26 RB5/PGM RA2/AN2/VREF- 4 25 RB4 RA3/AN3/VREF+ 5 2 2 24 RB3/CCP2* RA4/T0CKI 6 24 25 23 RB2/INT2 RA5/AN4/SS/LVDIN 7 F F 22 RB1/INT1 VSS 8 18 18 21 RB0/INT0 OSC1/CLKI 9 C C 20 VDD OSC2/CLKO/RA6 10 PI PI 19 VSS RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2* 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA * RB3 is the alternate pin for the CCP2 pin multiplexing. © 2006 Microchip Technology Inc. DS39564C-page 3

PIC18FXX2 Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Oscillator Configurations............................................................................................................................................................17 3.0 Reset..........................................................................................................................................................................................25 4.0 Memory Organization.................................................................................................................................................................35 5.0 FLASH Program Memory...........................................................................................................................................................55 6.0 Data EEPROM Memory.............................................................................................................................................................65 7.0 8 X 8 Hardware Multiplier...........................................................................................................................................................71 8.0 Interrupts....................................................................................................................................................................................73 9.0 I/O Ports.....................................................................................................................................................................................87 10.0 Timer0 Module.........................................................................................................................................................................103 11.0 Timer1 Module.........................................................................................................................................................................107 12.0 Timer2 Module.........................................................................................................................................................................111 13.0 Timer3 Module.........................................................................................................................................................................113 14.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................117 15.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................125 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)..............................................................165 17.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................181 18.0 Low Voltage Detect..................................................................................................................................................................189 19.0 Special Features of the CPU....................................................................................................................................................195 20.0 Instruction Set Summary..........................................................................................................................................................211 21.0 Development Support...............................................................................................................................................................253 22.0 Electrical Characteristics..........................................................................................................................................................259 23.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................289 24.0 Packaging Information..............................................................................................................................................................305 Appendix A: Revision History............................................................................................................................................................313 Appendix B: Device Differences........................................................................................................................................................313 Appendix C: Conversion Considerations...........................................................................................................................................314 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................314 Appendix E: Migration from Mid-range to Enhanced Devices...........................................................................................................315 Appendix F: Migration from High-end to Enhanced Devices............................................................................................................315 Index..................................................................................................................................................................................................317 On-Line Support.................................................................................................................................................................................327 Reader Response..............................................................................................................................................................................328 PIC18FXX2 Product Identification System.........................................................................................................................................329 DS39564C-page 4 © 2006 Microchip Technology Inc.

PIC18FXX2 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:129) Microchip’s Worldwide Web site; http://www.microchip.com (cid:129) Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. DS39564C-page 5

PIC18FXX2 NOTES: DS39564C-page 6 © 2006 Microchip Technology Inc.

PIC18FXX2 1.0 DEVICE OVERVIEW The following two figures are device block diagrams sorted by pin count: 28-pin for Figure1-1 and 40/44-pin This document contains device specific information for for Figure1-2. The 28-pin and 40/44-pin pinouts are the following devices: listed in Table1-2 and Table1-3, respectively. (cid:129) PIC18F242 (cid:129) PIC18F442 (cid:129) PIC18F252 (cid:129) PIC18F452 These devices come in 28-pin and 40/44-pin packages. The 28-pin devices do not have a Parallel Slave Port (PSP) implemented and the number of Analog-to- Digital (A/D) converter input channels is reduced to 5. An overview of features is shown in Table1-1. TABLE 1-1: DEVICE FEATURES Features PIC18F242 PIC18F252 PIC18F442 PIC18F452 Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz Program Memory (Bytes) 16K 32K 16K 32K Program Memory (Instructions) 8192 16384 8192 16384 Data Memory (Bytes) 768 1536 768 1536 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 17 17 18 18 I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 2 2 2 2 MSSP, MSSP, MSSP, MSSP, Serial Communications Addressable Addressable Addressable Addressable USART USART USART USART Parallel Communications — — PSP PSP 10-bit Analog-to-Digital Module 5 input channels 5 input channels 8 input channels 8 input channels POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, RESETS (and Delays) Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) Programmable Low Voltage Yes Yes Yes Yes Detect Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions 40-pin DIP 40-pin DIP 28-pin DIP 28-pin DIP Packages 44-pin PLCC 44-pin PLCC 28-pin SOIC 28-pin SOIC 44-pin TQFP 44-pin TQFP © 2006 Microchip Technology Inc. DS39564C-page 7

PIC18FXX2 FIGURE 1-1: PIC18F2X2 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer Data Latch RA0/AN0 8 8 8 Data RAM RA1/AN1 21 inc/dec logic RA2/AN2/VREF- RA3/AN3/VREF+ Address Latch RA4/T0CKI Address Latch 21 PCLATU PCLATH 12(2) RA5/AN4/SS/LVDIN RA6 Program Memory Address<12> (up to 2 Mbytes) PCU PCH PCL Program Counter 4 12 4 Data Latch BSR FSR0 Bank0, F 31 Level Stack FSR1 FSR2 12 16 inc/dec Decode logic Table Latch 8 PORTB ROM Latch RB0/INT0 RB1/INT1 RB2/INT2 Instruction RB3/CCP2(1) Register RB4 8 RB5/PGM Instruction RB6/PCG Decode & RB7/PGD Control PRODH PRODL OSC2/CLKO OSC1/CLKI 3 8 x 8 Multiply Power-up 8 Timer T1OSCI Timing Oscillator BIT OP WREG T1OSCO Generation Start-up Timer 8 8 8 Power-on Reset 8 4X PLL Watchdog Timer ALU<8> PORTC RC0/T1OSO/T1CKI Precision Brown-out 8 RC1/T1OSI/CCP2(1) Reset Voltage RC2/CCP1 Reference Low Voltage RC3/SCK/SCL MCLR Programming RC4/SDI/SDA RC5/SDO VDD, VSS In-Circuit RC6/TX/CK Debugger RC7/RX/DT Timer0 Timer1 Timer2 Timer3 A/D Converter Master Addressable CCP1 CCP2 Synchronous USART Data EEPROM Serial Port Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit. 2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction). 3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent. DS39564C-page 8 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 1-2: PIC18F4X2 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 21 Table Pointer Data Latch RA1/AN1 8 8 8 Data RAM RA2/AN2/VREF- (up to 4K RA3/AN3/VREF+ 21 inc/dec logic address reach) RA4/T0CKI Address Latch RA5/AN4/SS/LVDIN RA6 Address Latch 21 PCLAT U PCLATH 12(2) Program Memory Address<12> (up to 2 Mbytes) PCU PCH PCL PORTB Program Counter 4 12 4 Data Latch RB0/INT0 BSR FSR0 Bank0, F RB1/INT1 31 Level Stack FSR1 RB2/INT2 FSR2 12 RB3/CCP2(1) RB4 16 inc/dec RB5/PGM Decode RB6/PCG logic Table Latch RB7/PGD 8 ROM Latch PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1 Instruction Register RC3/SCK/SCL RC4/SDI/SDA 8 RC5/SDO Instruction Decode & RC6/TX/CK Control PRODH PRODL RC7/RX/DT OSC2/CLKO OSC1/CLKI 3 8 x 8 Multiply Power-up PORTD 8 Timer RD0/PSP0 T1OSCI Timing Oscillator BIT OP WREG RD1/PSP1 T1OSCO Generation Start-up Timer 8 8 8 RD2/PSP2 Power-on RD3/PSP3 Reset RD4/PSP4 8 RD5/PSP5 4X PLL Watchdog ALU<8> RD6/PSP6 Timer RD7/PSP7 Brown-out PVroelctaisgioen Reset 8 PORTE Reference Low Voltage MCLR Programming RE0/AN5/RD VDD, VSS In-Circuit RE1/AN6/WR Debugger RE2/AN7/CS Timer0 Timer1 Timer2 Timer3 A/D Converter Master CCP1 CCP2 Synchronous Addressable Parallel Slave Port Data EEPROM Serial Port USART Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit. 2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction). 3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent. © 2006 Microchip Technology Inc. DS39564C-page 9

PIC18FXX2 TABLE 1-2: PIC18F2X2 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type DIP SOIC MCLR/VPP 1 1 Master Clear (input) or high voltage ICSP programming enable pin. MCLR I ST Master Clear (Reset) input. This pin is an active low RESET to the device. VPP I ST High voltage ICSP programming enable pin. NC — — — — These pins should be left unconnected. OSC1/CLKI 9 9 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) OSC2/CLKO/RA6 10 10 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. RA6 I/O TTL General Purpose I/O pin. PORTA is a bi-directional I/O port. RA0/AN0 2 2 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 3 3 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 4 4 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D Reference Voltage (Low) input. RA3/AN3/VREF+ 5 5 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D Reference Voltage (High) input. RA4/T0CKI 6 6 RA4 I/O ST/OD Digital I/O. Open drain when configured as output. T0CKI I ST Timer0 external clock input. RA5/AN4/SS/LVDIN 7 7 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I ST SPI Slave Select input. LVDIN I Analog Low Voltage Detect Input. RA6 See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS39564C-page 10 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 1-2: PIC18F2X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type DIP SOIC PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 21 21 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. RB1/INT1 22 22 RB1 I/O TTL INT1 I ST External Interrupt 1. RB2/INT2 23 23 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. RB3/CCP2 24 24 RB3 I/O TTL Digital I/O. CCP2 I/O ST Capture2 input, Compare2 output, PWM2 output. RB4 25 25 I/O TTL Digital I/O. Interrupt-on-change pin. RB5/PGM 26 26 RB5 I/O TTL Digital I/O. Interrupt-on-change pin. PGM I/O ST Low Voltage ICSP programming enable pin. RB6/PGC 27 27 RB6 I/O TTL Digital I/O. Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/PGD 28 28 RB7 I/O TTL Digital I/O. Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) © 2006 Microchip Technology Inc. DS39564C-page 11

PIC18FXX2 TABLE 1-2: PIC18F2X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type DIP SOIC PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T1CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 12 12 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2 I/O ST Capture2 input, Compare2 output, PWM2 output. RC2/CCP1 13 13 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 14 14 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode RC4/SDI/SDA 15 15 RC4 I/O ST Digital I/O. SDI I ST SPI Data In. SDA I/O ST I2C Data I/O. RC5/SDO 16 16 RC5 I/O ST Digital I/O. SDO O — SPI Data Out. RC6/TX/CK 17 17 RC6 I/O ST Digital I/O. TX O — USART Asynchronous Transmit. CK I/O ST USART Synchronous Clock (see related RX/DT). RC7/RX/DT 18 18 RC7 I/O ST Digital I/O. RX I ST USART Asynchronous Receive. DT I/O ST USART Synchronous Data (see related TX/CK). VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 P — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS39564C-page 12 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type DIP PLCC TQFP MCLR/VPP 1 2 18 Master Clear (input) or high voltage ICSP programming enable pin. MCLR I ST Master Clear (Reset) input. This pin is an active low RESET to the device. VPP I ST High voltage ICSP programming enable pin. NC — — — These pins should be left unconnected. OSC1/CLKI 13 14 30 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) OSC2/CLKO/RA6 14 15 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General Purpose I/O pin. PORTA is a bi-directional I/O port. RA0/AN0 2 3 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 3 4 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 4 5 21 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D Reference Voltage (Low) input. RA3/AN3/VREF+ 5 6 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D Reference Voltage (High) input. RA4/T0CKI 6 7 23 RA4 I/O ST/OD Digital I/O. Open drain when configured as output. T0CKI I ST Timer0 external clock input. RA5/AN4/SS/LVDIN 7 8 24 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I ST SPI Slave Select input. LVDIN I Analog Low Voltage Detect Input. RA6 (See the OSC2/CLKO/RA6 pin.) Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) © 2006 Microchip Technology Inc. DS39564C-page 13

PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type DIP PLCC TQFP PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 33 36 8 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. RB1/INT1 34 37 9 RB1 I/O TTL INT1 I ST External Interrupt 1. RB2/INT2 35 38 10 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. RB3/CCP2 36 39 11 RB3 I/O TTL Digital I/O. CCP2 I/O ST Capture2 input, Compare2 output, PWM2 output. RB4 37 41 14 I/O TTL Digital I/O. Interrupt-on-change pin. RB5/PGM 38 42 15 RB5 I/O TTL Digital I/O. Interrupt-on-change pin. PGM I/O ST Low Voltage ICSP programming enable pin. RB6/PGC 39 43 16 RB6 I/O TTL Digital I/O. Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/PGD 40 44 17 RB7 I/O TTL Digital I/O. Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS39564C-page 14 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type DIP PLCC TQFP PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 15 16 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T1CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 16 18 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2 I/O ST Capture2 input, Compare2 output, PWM2 output. RC2/CCP1 17 19 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 18 20 37 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode. RC4/SDI/SDA 23 25 42 RC4 I/O ST Digital I/O. SDI I ST SPI Data In. SDA I/O ST I2C Data I/O. RC5/SDO 24 26 43 RC5 I/O ST Digital I/O. SDO O — SPI Data Out. RC6/TX/CK 25 27 44 RC6 I/O ST Digital I/O. TX O — USART Asynchronous Transmit. CK I/O ST USART Synchronous Clock (see related RX/DT). RC7/RX/DT 26 29 1 RC7 I/O ST Digital I/O. RX I ST USART Asynchronous Receive. DT I/O ST USART Synchronous Data (see related TX/CK). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) © 2006 Microchip Technology Inc. DS39564C-page 15

PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type DIP PLCC TQFP PORTD is a bi-directional I/O port, or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0 19 21 38 I/O ST Digital I/O. TTL Parallel Slave Port Data. RD1/PSP1 20 22 39 I/O ST Digital I/O. TTL Parallel Slave Port Data. RD2/PSP2 21 23 40 I/O ST Digital I/O. TTL Parallel Slave Port Data. RD3/PSP3 22 24 41 I/O ST Digital I/O. TTL Parallel Slave Port Data. RD4/PSP4 27 30 2 I/O ST Digital I/O. TTL Parallel Slave Port Data. RD5/PSP5 28 31 3 I/O ST Digital I/O. TTL Parallel Slave Port Data. RD6/PSP6 29 32 4 I/O ST Digital I/O. TTL Parallel Slave Port Data. RD7/PSP7 30 33 5 I/O ST Digital I/O. TTL Parallel Slave Port Data. PORTE is a bi-directional I/O port. RE0/RD/AN5 8 9 25 I/O RE0 ST Digital I/O. RD TTL Read control for parallel slave port (see also WR and CS pins). AN5 Analog Analog input 5. RE1/WR/AN6 9 10 26 I/O RE1 ST Digital I/O. WR TTL Write control for parallel slave port (see CS and RD pins). AN6 Analog Analog input 6. RE2/CS/AN7 10 11 27 I/O RE2 ST Digital I/O. CS TTL Chip Select control for parallel slave port (see related RD and WR). AN7 Analog Analog input 7. VSS 12, 31 13, 34 6, 29 P — Ground reference for logic and I/O pins. VDD 11, 32 12, 35 7, 28 P — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open Drain (no P diode to VDD) DS39564C-page 16 © 2006 Microchip Technology Inc.

PIC18FXX2 2.0 OSCILLATOR TABLE 2-1: CAPACITOR SELECTION FOR CONFIGURATIONS CERAMIC RESONATORS 2.1 Oscillator Types Ranges Tested: Mode Freq C1 C2 The PIC18FXX2 can be operated in eight different Oscillator modes. The user can program three configu- XT 455 kHz 68 - 100 pF 68 - 100 pF ration bits (FOSC2, FOSC1, and FOSC0) to select one 2.0 MHz 15 - 68 pF 15 - 68 pF of these eight modes: 4.0 MHz 15 - 68 pF 15 - 68 pF HS 8.0 MHz 10 - 68 pF 10 - 68 pF 1. LP Low Power Crystal 16.0 MHz 10 - 22 pF 10 - 22 pF 2. XT Crystal/Resonator These values are for design guidance only. 3. HS High Speed Crystal/Resonator See notes following this table. 4. HS + PLL High Speed Crystal/Resonator Resonators Used: with PLL enabled 5. RC External Resistor/Capacitor 455 kHz Panasonic EFO-A455K04B ± 0.3% 6. RCIO External Resistor/Capacitor with 2.0 MHz Murata Erie CSA2.00MG ± 0.5% I/O pin enabled 4.0 MHz Murata Erie CSA4.00MG ± 0.5% 7. EC External Clock 8.0 MHz Murata Erie CSA8.00MT ± 0.5% 8. ECIO External Clock with I/O pin 16.0 MHz Murata Erie CSA16.00MX ± 0.5% enabled All resonators used did not have built-in capacitors. 2.2 Crystal Oscillator/Ceramic Resonators Note 1: Higher capacitance increases the stability of the oscillator, but also increases the In XT, LP, HS or HS+PLL Oscillator modes, a crystal or start-up time. ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure2-1 shows 2: When operating below 3V VDD, or when the pin connections. using certain ceramic resonators at any voltage, it may be necessary to use The PIC18FXX2 oscillator design requires the use of a high-gain HS mode, try a lower frequency parallel cut crystal. resonator, or switch to a crystal oscillator. Note: Use of a series cut crystal may give a fre- 3: Since each resonator/crystal has its own quency out of the crystal manufacturers characteristics, the user should consult the specifications. resonator/crystal manufacturer for appro- priate values of external components, or FIGURE 2-1: CRYSTAL/CERAMIC verify oscillator performance. RESONATOR OPERATION (HS, XT OR LP CONFIGURATION) C1(1) OSC1 To Internal XTAL (3) Logic RF SLEEP RS(2) C2(1) OSC2 PIC18FXXX Note 1: See Table2-1 and Table2-2 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the Oscillator mode chosen. © 2006 Microchip Technology Inc. DS39564C-page 17

PIC18FXX2 TABLE 2-2: CAPACITOR SELECTION FOR 2.3 RC Oscillator CRYSTAL OSCILLATOR For timing-insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. Ranges Tested: The RC oscillator frequency is a function of the supply Mode Freq C1 C2 voltage, the resistor (REXT) and capacitor (CEXT) val- ues and the operating temperature. In addition to this, LP 32.0 kHz 33 pF 33 pF the oscillator frequency will vary from unit to unit due to 200 kHz 15 pF 15 pF normal process parameter variation. Furthermore, the XT 200 kHz 22-68 pF 22-68 pF difference in lead frame capacitance between package 1.0 MHz 15 pF 15 pF types will also affect the oscillation frequency, espe- cially for low CEXT values. The user also needs to take 4.0 MHz 15 pF 15 pF into account variation due to tolerance of external R HS 4.0 MHz 15 pF 15 pF and C components used. Figure2-3 shows how the 8.0 MHz 15-33 pF 15-33 pF R/C combination is connected. 20.0 MHz 15-33 pF 15-33 pF In the RC Oscillator mode, the oscillator frequency 25.0 MHz 15-33 pF 15-33 pF divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other These values are for design guidance only. logic. See notes following this table. Note: If the oscillator frequency divided by 4 sig- Crystals Used nal is not required in the application, it is 32.0 kHz Epson C-001R32.768K-A ± 20 PPM recommended to use RCIO mode to save 200 kHz STD XTL 200.000KHz ± 20 PPM current. 1.0 MHz ECS ECS-10-13-1 ± 50 PPM 4.0 MHz ECS ECS-40-20-1 ± 50 PPM FIGURE 2-3: RC OSCILLATOR MODE 8.0 MHz Epson CA-301 8.000M-C ± 30 PPM VDD 20.0 MHz Epson CA-301 20.000M-C ± 30 PPM REXT Internal OSC1 Note 1: Higher capacitance increases the stability Clock of the oscillator, but also increases the CEXT PIC18FXXX start-up time. VSS 2: Rs may be required in HS mode, as well OSC2/CLKO as XT mode, to avoid overdriving crystals FOSC/4 with low drive level specification. 3: Since each resonator/crystal has its own Recommended values:3 kΩ ≤ REXT ≤ 100 kΩ characteristics, the user should consult the CEXT > 20pF resonator/crystal manufacturer for appro- priate values of external components., or The RCIO Oscillator mode functions like the RC mode, verify oscillator performance. except that the OSC2 pin becomes an additional gen- An external clock source may also be connected to the eral purpose I/O pin. The I/O pin becomes bit 6 of OSC1 pin in the HS, XT and LP modes, as shown in PORTA (RA6). Figure2-2. FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock from OSC1 Ext. System PIC18FXXX Open OSC2 DS39564C-page 18 © 2006 Microchip Technology Inc.

PIC18FXX2 2.4 External Clock Input FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION The EC and ECIO Oscillator modes require an external (ECIO CONFIGURATION) clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscilla- Clock from OSC1 tor start-up time required after a Power-on Reset or Ext. System PIC18FXXX after a recovery from SLEEP mode. RA6 I/O (OSC2) In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other 2.5 HS/PLL logic. Figure2-4 shows the pin connections for the EC Oscillator mode. A Phase Locked Loop circuit is provided as a program- mable option for users that want to multiply the fre- FIGURE 2-4: EXTERNAL CLOCK INPUT quency of the incoming crystal oscillator signal by 4. OPERATION For an input clock frequency of 10 MHz, the internal clock frequency will be multiplied to 40 MHz. This is (EC CONFIGURATION) useful for customers who are concerned with EMI due to high frequency crystals. Clock from OSC1 The PLL can only be enabled when the oscillator con- Ext. System PIC18FXXX figuration bits are programmed for HS mode. If they are FOSC/4 OSC2 programmed for any other mode, the PLL is not enabled and the system clock will come directly from OSC1. The ECIO Oscillator mode functions like the EC mode, The PLL is one of the modes of the FOSC<2:0> config- except that the OSC2 pin becomes an additional gen- uration bits. The Oscillator mode is specified during eral purpose I/O pin. The I/O pin becomes bit 6 of device programming. PORTA (RA6). Figure2-5 shows the pin connections for the ECIO Oscillator mode. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out that is called TPLL. FIGURE 2-6: PLL BLOCK DIAGRAM (from Configuration HS Osc bit Register) PLL Enable Phase OSC2 Comparator FIN Loop VCO Crystal Filter Osc SYSCLK FOUT X U OSC1 Divide by 4 M © 2006 Microchip Technology Inc. DS39564C-page 19

PIC18FXX2 2.6 Oscillator Switching Feature tion mode. Figure2-7 shows a block diagram of the system clock sources. The clock switching feature is The PIC18FXX2 devices include a feature that allows enabled by programming the Oscillator Switching the system clock source to be switched from the main Enable (OSCSEN) bit in Configuration Register1H to a oscillator to an alternate low frequency clock source. ’0’. Clock switching is disabled in an erased device. For the PIC18FXX2 devices, this alternate clock source See Section11.0 for further details of the Timer1 oscil- is the Timer1 oscillator. If a low frequency crystal (32 lator. See Section19.0 for Configuration Register kHz, for example) has been attached to the Timer1 details. oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a Low Power Execu- FIGURE 2-7: DEVICE CLOCK SOURCES PIC18FXXX Main Oscillator OSC2 TOSC/4 SLEEP 4 x PLL OSC1 TOSC M TSCLK U Timer1 Oscillator X TT1P T1OSO T1OSCEN Enable Clock T1OSI Oscillator Source Clock Source option for other modules DS39564C-page 20 © 2006 Microchip Technology Inc.

PIC18FXX2 2.6.1 SYSTEM CLOCK SWITCH BIT The system clock source switching is performed under Note: The Timer1 oscillator must be enabled and software control. The system clock switch bit, SCS operating to switch the system clock (OSCCON<0>) controls the clock switching. When the source. The Timer1 oscillator is enabled by SCS bit is ’0’, the system clock source comes from the setting the T1OSCEN bit in the Timer1 main oscillator that is selected by the FOSC configura- control register (T1CON). If the Timer1 tion bits in Configuration Register1H. When the SCS bit oscillator is not enabled, then any write to is set, the system clock source will come from the the SCS bit will be ignored (SCS bit forced Timer1 oscillator. The SCS bit is cleared on all forms of cleared) and the main oscillator will RESET. continue to be the system clock source. REGISTER 2-1: OSCCON REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 — — — — — — — SCS bit 7 bit 0 bit 7-1 Unimplemented: Read as '0' bit 0 SCS: System Clock Switch bit When OSCSEN configuration bit = ’0’ and T1OSCEN bit is set: 1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pin When OSCSEN and T1OSCEN are in other states: bit is forced clear Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 21

PIC18FXX2 2.6.2 OSCILLATOR TRANSITIONS A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in The PIC18FXX2 devices contain circuitry to prevent Figure2-8. The Timer1 oscillator is assumed to be run- “glitches” when switching between oscillator sources. ning all the time. After the SCS bit is set, the processor Essentially, the circuitry waits for eight rising edges of is frozen at the next occurring Q1 cycle. After eight syn- the clock source that the processor is switching to. This chronization cycles are counted from the Timer1 oscil- ensures that the new clock source is stable and that its lator, operation resumes. No additional delays are pulse width will not be less than the shortest pulse required after the synchronization cycles. width of the two clock sources. FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 TT1P T1OSI 1 2 3 4 5 6 7 8 Tscs OSC1 TOSC Internal CSylosctekm TDLY SCS (OSCCON<0>) Program PC PC + 2 PC + 4 Counter Note1: Delay on internal system clock is eight oscillator cycles for synchronization. The sequence of events that takes place when switch- If the main oscillator is configured for an external crys- ing from the Timer1 oscillator to the main oscillator will tal (HS, XT, LP), then the transition will take place after depend on the mode of the main oscillator. In addition an oscillator start-up time (TOST) has occurred. A timing to eight clock cycles of the main oscillator, additional diagram, indicating the transition from the Timer1 oscil- delays may take place. lator to the main oscillator for HS, XT and LP modes, is shown in Figure2-9. FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP) Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 TT1P T1OSI OSC1 1 2 3 4 5 6 7 8 TOST TSCS OSC2 TOSC Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 6 Note1: TOST = 1024 TOSC (drawing not to scale). DS39564C-page 22 © 2006 Microchip Technology Inc.

PIC18FXX2 If the main oscillator is configured for HS-PLL mode, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS-PLL mode is shown in Figure2-10. FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TOST TPLL OSC2 TOSC TSCS PLL Clock Input 1 2 3 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 Note1: TOST = 1024 TOSC (drawing not to scale). If the main oscillator is configured in the RC, RCIO, EC or ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram, indi- cating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes, is shown in Figure2-11. FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI TOSC OSC1 1 2 3 4 5 6 7 8 OSC2 Internal System Clock SCS (OSCCON<0>) TSCS Program Counter PC PC + 2 PC + 4 Note1: RC Oscillator mode assumed. © 2006 Microchip Technology Inc. DS39564C-page 23

PIC18FXX2 2.7 Effects of SLEEP Mode on the switching currents have been removed, SLEEP mode On-Chip Oscillator achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature When the device executes a SLEEP instruction, the that will operate during SLEEP will increase the current on-chip clocks and oscillator are turned off and the consumed during SLEEP. The user can wake from device is held at the beginning of an instruction cycle SLEEP through external RESET, Watchdog Timer (Q1 state). With the oscillator off, the OSC1 and OSC2 Reset, or through an interrupt. signals will stop oscillating. Since all the transistor TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC Floating, external resistor At logic low should pull high RCIO Floating, external resistor Configured as PORTA, bit 6 should pull high ECIO Floating Configured as PORTA, bit 6 EC Floating At logic low LP, XT, and HS Feedback inverter disabled, at Feedback inverter disabled, at quiescent voltage level quiescent voltage level Note: See Table3-1, in the “Reset” section, for time-outs due to SLEEP and MCLR Reset. 2.8 Power-up Delays With the PLL enabled (HS/PLL Oscillator mode), the time-out sequence following a Power-on Reset is differ- Power up delays are controlled by two timers, so that ent from other Oscillator modes. The time-out no external RESET circuitry is required for most appli- sequence is as follows: First, the PWRT time-out is cations. The delays ensure that the device is kept in invoked after a POR time delay has expired. Then, the RESET, until the device power supply and clock are Oscillator Start-up Timer (OST) is invoked. However, stable. For additional information on RESET operation, this is still not a sufficient amount of time to allow the see Section3.0. PLL to lock at high frequencies. The PWRT timer is The first timer is the Power-up Timer (PWRT), which used to provide an additional fixed 2 ms (nominal) optionally provides a fixed delay of 72 ms (nominal) on time-out to allow the PLL ample time to lock to the power-up only (POR and BOR). The second timer is incoming clock frequency. the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. DS39564C-page 24 © 2006 Microchip Technology Inc.

PIC18FXX2 3.0 RESET Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- The PIC18FXXX differentiates between various kinds ation. Status bits from the RCON register, RI, TO, PD, of RESET: POR and BOR, are set or cleared differently in different a) Power-on Reset (POR) RESET situations, as indicated in Table3-2. These bits are used in software to determine the nature of the b) MCLR Reset during normal operation RESET. See Table3-3 for a full description of the c) MCLR Reset during SLEEP RESET states of all registers. d) Watchdog Timer (WDT) Reset (during normal A simplified block diagram of the On-Chip Reset Circuit operation) is shown in Figure3-1. e) Programmable Brown-out Reset (BOR) The Enhanced MCU devices have a MCLR noise filter f) RESET Instruction in the MCLR Reset path. The filter will detect and g) Stack Full Reset ignore small pulses. h) Stack Underflow Reset The MCLR pin is not driven low by any internal Most registers are unaffected by a RESET. Their status RESETS, including the WDT. is unknown on POR and unchanged by all other RESETS. The other registers are forced to a “RESET state” on Power-on Reset, MCLR, WDT Reset, Brown- out Reset, MCLR Reset during SLEEP and by the RESET instruction. FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Pointer Stack Full/Underflow Reset External Reset MCLR SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset BOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 PWRT On-chip RC OSC(1) 10-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table3-1 for time-out situations. © 2006 Microchip Technology Inc. DS39564C-page 25

PIC18FXX2 3.1 Power-On Reset (POR) 3.3 Oscillator Start-up Timer (OST) A Power-on Reset pulse is generated on-chip when The Oscillator Start-up Timer (OST) provides a 1024 VDD rise is detected. To take advantage of the POR cir- oscillator cycle (from OSC1 input) delay after the cuitry, just tie the MCLR pin directly (or through a resis- PWRT delay is over (parameter32). This ensures that tor) to VDD. This will eliminate external RC components the crystal oscillator or resonator has started and usually needed to create a Power-on Reset delay. A stabilized. minimum rise rate for VDD is specified The OST time-out is invoked only for XT, LP and HS (parameterD004). For a slow rise time, see Figure3-2. modes and only on Power-on Reset or wake-up from When the device starts normal operation (i.e., exits the SLEEP. RESET condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to 3.4 PLL Lock Time-out ensure operation. If these conditions are not met, the With the PLL enabled, the time-out sequence following device must be held in RESET until the operating a Power-on Reset is different from other Oscillator conditions are met. modes. A portion of the Power-up Timer is used to pro- vide a fixed time-out that is sufficient for the PLL to lock FIGURE 3-2: EXTERNAL POWER-ON to the main oscillator frequency. This PLL lock time-out RESET CIRCUIT (FOR (TPLL) is typically 2 ms and follows the oscillator SLOW VDD POWER-UP) start-up time-out (OST). 3.5 Brown-out Reset (BOR) VDD A configuration bit, BOREN, can disable (if clear/ D R programmed), or enable (if set) the Brown-out Reset R1 circuitry. If VDD falls below parameterD005 for greater MCLR than parameter35, the brown-out situation will reset C PIC18FXXX the chip. A RESET may not occur if VDD falls below parameterD005 for less than parameter35. The chip will remain in Brown-out Reset until VDD rises above BVDD. If the Power-up Timer is enabled, it will be invoked after VDD rises above BVDD; it then will keep the chip in RESET for an additional time delay Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. (parameter33). If VDD drops below BVDD while the The diode D helps discharge the capacitor Power-up Timer is running, the chip will go back into a quickly when VDD powers down. Brown-out Reset and the Power-up Timer will be initial- 2: R < 40 kΩ is recommended to make sure that ized. Once VDD rises above BVDD, the Power-up Timer the voltage drop across R does not violate will execute the additional time delay. the device’s electrical specification. 3.6 Time-out Sequence 3: R1 = 100Ω to 1 kΩ will limit any current flow- ing into MCLR from external capacitor C, in On power-up, the time-out sequence is as follows: the event of MCLR/VPP pin breakdown due to First, PWRT time-out is invoked after the POR time Electrostatic Discharge (ESD) or Electrical delay has expired. Then, OST is activated. The total Overstress (EOS). time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with 3.2 Power-up Timer (PWRT) the PWRT disabled, there will be no time-out at all. Figure3-3, Figure3-4, Figure3-5, Figure3-6 and The Power-up Timer provides a fixed nominal time-out Figure3-7 depict time-out sequences on power-up. (parameter33) only on power-up from the POR. The Power-up Timer operates on an internal RC oscillator. Since the time-outs occur from the POR pulse, if MCLR The chip is kept in RESET as long as the PWRT is is kept low long enough, the time-outs will expire. active. The PWRT’s time delay allows VDD to rise to an Bringing MCLR high will begin execution immediately acceptable level. A configuration bit is provided to (Figure3-5). This is useful for testing purposes or to enable/disable the PWRT. synchronize more than one PIC18FXXX device operat- ing in parallel. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See DC Table3-2 shows the RESET conditions for some parameterD033 for details. Special Function Registers, while Table3-3 shows the RESET conditions for all the registers. DS39564C-page 26 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Wake-up from Oscillator Brown-out SLEEP or Configuration PWRTE = 0 PWRTE = 1 Oscillator Switch HS with PLL enabled(1) 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC + 2 ms + 2ms + 2 ms + 2ms HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC EC 72 ms — 72 ms(2) — External RC 72 ms — 72 ms(2) — Note 1: 2 ms is the nominal time required for the 4x PLL to lock. 2: 72 ms is the nominal power-up timer delay, if implemented. REGISTER 3-1: RCON REGISTER BITS AND POSITIONS R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 Note 1: Refer to Section4.14 (page 53) for bit definitions. TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program RCON Condition RI TO PD POR BOR STKFUL STKUNF Counter Register Power-on Reset 0000h 0--1 1100 1 1 1 0 0 u u MCLR Reset during normal 0000h 0--u uuuu u u u u u u u operation Software Reset during normal 0000h 0--0 uuuu 0 u u u u u u operation Stack Full Reset during normal 0000h 0--u uu11 u u u u u u 1 operation Stack Underflow Reset during 0000h 0--u uu11 u u u u u 1 u normal operation MCLR Reset during SLEEP 0000h 0--u 10uu u 1 0 u u u u WDT Reset 0000h 0--u 01uu 1 0 1 u u u u WDT Wake-up PC + 2 u--u 00uu u 0 0 u u u u Brown-out Reset 0000h 0--1 11u0 1 1 1 1 0 u u Interrupt wake-up from SLEEP PC + 2(1) u--u 00uu u 1 0 u u u u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). © 2006 Microchip Technology Inc. DS39564C-page 27

PIC18FXX2 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TOSU 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3) TOSL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 242 442 252 452 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu PCLATH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PCL 242 442 252 452 0000 0000 0000 0000 PC + 2(2) TBLPTRU 242 442 252 452 --00 0000 --00 0000 --uu uuuu TBLPTRH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TBLPTRL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TABLAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PRODH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 242 442 252 452 0000 000x 0000 000u uuuu uuuu(1) INTCON2 242 442 252 452 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 242 442 252 452 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 242 442 252 452 N/A N/A N/A POSTINC0 242 442 252 452 N/A N/A N/A POSTDEC0 242 442 252 452 N/A N/A N/A PREINC0 242 442 252 452 N/A N/A N/A PLUSW0 242 442 252 452 N/A N/A N/A FSR0H 242 442 252 452 ---- xxxx ---- uuuu ---- uuuu FSR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu WREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 242 442 252 452 N/A N/A N/A POSTINC1 242 442 252 452 N/A N/A N/A POSTDEC1 242 442 252 452 N/A N/A N/A PREINC1 242 442 252 452 N/A N/A N/A PLUSW1 242 442 252 452 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ’0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’. DS39564C-page 28 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets FSR1H 242 442 252 452 ---- xxxx ---- uuuu ---- uuuu FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu INDF2 242 442 252 452 N/A N/A N/A POSTINC2 242 442 252 452 N/A N/A N/A POSTDEC2 242 442 252 452 N/A N/A N/A PREINC2 242 442 252 452 N/A N/A N/A PLUSW2 242 442 252 452 N/A N/A N/A FSR2H 242 442 252 452 ---- xxxx ---- uuuu ---- uuuu FSR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 242 442 252 452 ---x xxxx ---u uuuu ---u uuuu TMR0H 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu TMR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 242 442 252 452 1111 1111 1111 1111 uuuu uuuu OSCCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u LVDCON 242 442 252 452 --00 0101 --00 0101 --uu uuuu WDTCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u RCON(4) 242 442 252 452 0--q 11qq 0--q qquu u--u qquu TMR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuu TMR2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PR2 242 442 252 452 1111 1111 1111 1111 1111 1111 T2CON 242 442 252 452 -000 0000 -000 0000 -uuu uuuu SSPBUF 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPSTAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPCON1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPCON2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ’0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’. © 2006 Microchip Technology Inc. DS39564C-page 29

PIC18FXX2 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets ADRESH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 242 442 252 452 0000 00-0 0000 00-0 uuuu uu-u ADCON1 242 442 252 452 00-- 0000 00-- 0000 uu-- uuuu CCPR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu CCPR2H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu TMR3H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu SPBRG 242 442 252 452 0000 0000 0000 0000 uuuu uuuu RCREG 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TXREG 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TXSTA 242 442 252 452 0000 -010 0000 -010 uuuu -uuu RCSTA 242 442 252 452 0000 000x 0000 000x uuuu uuuu EEADR 242 442 252 452 0000 0000 0000 0000 uuuu uuuu EEDATA 242 442 252 452 0000 0000 0000 0000 uuuu uuuu EECON1 242 442 252 452 xx-0 x000 uu-0 u000 uu-0 u000 EECON2 242 442 252 452 ---- ---- ---- ---- ---- ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ’0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’. DS39564C-page 30 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets IPR2 242 442 252 452 ---1 1111 ---1 1111 ---u uuuu PIR2 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu(1) PIE2 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu 242 442 252 452 1111 1111 1111 1111 uuuu uuuu IPR1 242 442 252 452 -111 1111 -111 1111 -uuu uuuu 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(1) PIR1 242 442 252 452 -000 0000 -000 0000 -uuu uuuu(1) 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PIE1 242 442 252 452 -000 0000 -000 0000 -uuu uuuu TRISE 242 442 252 452 0000 -111 0000 -111 uuuu -uuu TRISD 242 442 252 452 1111 1111 1111 1111 uuuu uuuu TRISC 242 442 252 452 1111 1111 1111 1111 uuuu uuuu TRISB 242 442 252 452 1111 1111 1111 1111 uuuu uuuu TRISA(5,6) 242 442 252 452 -111 1111(5) -111 1111(5) -uuu uuuu(5) LATE 242 442 252 452 ---- -xxx ---- -uuu ---- -uuu LATD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu LATC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu LATB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5,6) 242 442 252 452 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5) PORTE 242 442 252 452 ---- -000 ---- -000 ---- -uuu PORTD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5,6) 242 442 252 452 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ’0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’. © 2006 Microchip Technology Inc. DS39564C-page 31

PIC18FXX2 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39564C-page 32 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2006 Microchip Technology Inc. DS39564C-page 33

PIC18FXX2 NOTES: DS39564C-page 34 © 2006 Microchip Technology Inc.

PIC18FXX2 4.0 MEMORY ORGANIZATION There are three memory blocks in Enhanced MCU devices. These memory blocks are: (cid:129) Program Memory (cid:129) Data RAM (cid:129) Data EEPROM Data and program memory use separate busses, which allows for concurrent access of these blocks. Additional detailed information for FLASH program memory and Data EEPROM is provided in Section5.0 and Section6.0, respectively. 4.1 Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ’0’s (a NOP instruction). The PIC18F252 and PIC18F452 each have 32Kbytes of FLASH memory, while the PIC18F242 and PIC18F442 have 16Kbytes of FLASH. This means that PIC18FX52 devices can store up to 16K of single word instructions, and PIC18FX42 devices can store up to 8K of single word instructions. The RESET vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. Figure4-1 shows the Program Memory Map for PIC18F242/442 devices and Figure4-2 shows the Program Memory Map for PIC18F252/452 devices. © 2006 Microchip Technology Inc. DS39564C-page 35

PIC18FXX2 FIGURE 4-1: PROGRAM MEMORY MAP FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR AND STACK FOR PIC18F442/242 PIC18F452/252 PC<20:0> PC<20:0> CALL,RCALL,RETURN 21 CALL,RCALL,RETURN 21 RETFIE,RETLW RETFIE,RETLW Stack Level 1 Stack Level 1 • • • • • • Stack Level 31 Stack Level 31 RESET Vector 0000h RESET Vector 0000h High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h On-Chip Program Memory 3FFFh 4000h On-Chip e Program Memory e c c a a p p S S y y or or m m e e M M er 7FFFh er s s U U Read '0' 8000h Read '0' 1FFFFFh 1FFFFFh 200000h 200000h DS39564C-page 36 © 2006 Microchip Technology Inc.

PIC18FXX2 4.2 Return Address Stack 4.2.2 RETURN STACK POINTER (STKPTR) The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC The STKPTR register contains the stack pointer value, (Program Counter) is pushed onto the stack when a the STKFUL (stack full) status bit, and the STKUNF CALL or RCALL instruction is executed, or an interrupt (stack underflow) status bits. Register4-1 shows the is acknowledged. The PC value is pulled off the stack STKPTR register. The value of the stack pointer can be on a RETURN, RETLW or a RETFIE instruction. 0 through 31. The stack pointer increments when val- PCLATU and PCLATH are not affected by any of the ues are pushed onto the stack and decrements when RETURN or CALL instructions. values are popped off the stack. At RESET, the stack pointer value will be 0. The user may read and write the The stack operates as a 31-word by 21-bit RAM and a stack pointer value. This feature can be used by a Real 5-bit stack pointer, with the stack pointer initialized to Time Operating System for return stack maintenance. 00000b after all RESETS. There is no RAM associated with stack pointer 00000b. This is only a RESET value. After the PC is pushed onto the stack 31 times (without During a CALL type instruction, causing a push onto the popping any values off the stack), the STKFUL bit is stack, the stack pointer is first incremented and the set. The STKFUL bit can only be cleared in software or RAM location pointed to by the stack pointer is written by a POR. with the contents of the PC. During a RETURN type The action that takes place when the stack becomes instruction, causing a pop from the stack, the contents full depends on the state of the STVREN (Stack Over- of the RAM location pointed to by the STKPTR are flow Reset Enable) configuration bit. Refer to transferred to the PC and then the stack pointer is Section20.0 for a description of the device configura- decremented. tion bits. If STVREN is set (default), the 31st push will The stack space is not part of either program or data push the (PC + 2) value onto the stack, set the STKFUL space. The stack pointer is readable and writable, and bit, and reset the device. The STKFUL bit will remain the address on the top of the stack is readable and writ- set and the stack pointer will be set to ‘0’. able through SFR registers. Data can also be pushed If STVREN is cleared, the STKFUL bit will be set on the to, or popped from, the stack using the top-of-stack 31st push and the stack pointer will increment to 31. SFRs. Status bits indicate if the stack pointer is at, or Any additional pushes will not overwrite the 31st push, beyond the 31 levels provided. and STKPTR will remain at 31. 4.2.1 TOP-OF-STACK ACCESS When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The top of the stack is readable and writable. Three to the PC and sets the STKUNF bit, while the stack register locations, TOSU, TOSH and TOSL hold the pointer remains at 0. The STKUNF bit will remain set contents of the stack location pointed to by the until cleared in software or a POR occurs. STKPTR register. This allows users to implement a software stack if necessary. After a CALL, RCALL or Note: Returning a value of zero to the PC on an interrupt, the software can read the pushed value by underflow has the effect of vectoring the reading the TOSU, TOSH and TOSL registers. These program to the RESET vector, where the values can be placed on a user defined software stack. stack conditions can be verified and At return time, the software can replace the TOSU, appropriate actions can be taken. TOSH and TOSL and do a return. The user must disable the global interrupt enable bits during this time to prevent inadvertent stack operations. © 2006 Microchip Technology Inc. DS39564C-page 37

PIC18FXX2 REGISTER 4-1: STKPTR REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKOVF STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7(1) STKOVF: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6(1) STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as '0' bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU TOSH TOSL STKPTR<4:0> 0x00 0x1A 0x34 00010 00011 Top of Stack 0x001A34 00010 0x000D58 00001 00000 4.2.3 PUSH AND POP INSTRUCTIONS 4.2.4 STACK FULL/UNDERFLOW RESETS Since the Top-of-Stack (TOS) is readable and writable, These resets are enabled by programming the the ability to push values onto the stack and pull values STVREN configuration bit. When the STVREN bit is off the stack without disturbing normal program execu- disabled, a full or underflow condition will set the appro- tion is a desirable option. To push the current PC value priate STKFUL or STKUNF bit, but not cause a device onto the stack, a PUSH instruction can be executed. RESET. When the STVREN bit is enabled, a full or This will increment the stack pointer and load the cur- underflow will set the appropriate STKFUL or STKUNF rent PC value onto the stack. TOSU, TOSH and TOSL bit and then cause a device RESET. The STKFUL or can then be modified to place a return address on the STKUNF bits are only cleared by the user software or stack. a POR Reset. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruc- tion discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. DS39564C-page 38 © 2006 Microchip Technology Inc.

PIC18FXX2 4.3 Fast Register Stack 4.4 PCL, PCLATH and PCLATU A “fast interrupt return” option is available for interrupts. The program counter (PC) specifies the address of the A Fast Register Stack is provided for the STATUS, instruction to fetch for execution. The PC is 21-bits WREG and BSR registers and are only one in depth. wide. The low byte is called the PCL register. This reg- The stack is not readable or writable and is loaded with ister is readable and writable. The high byte is called the current value of the corresponding register when the PCH register. This register contains the PC<15:8> the processor vectors for an interrupt. The values in the bits and is not directly readable or writable. Updates to registers are then loaded back into the working regis- the PCH register may be performed through the ters, if the FAST RETURN instruction is used to return PCLATH register. The upper byte is called PCU. This from the interrupt. register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may A low or high priority interrupt source will push values be performed through the PCLATU register. into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be The PC addresses bytes in the program memory. To used reliably for low priority interrupts. If a high priority prevent the PC from becoming misaligned with word interrupt occurs while servicing a low priority interrupt, instructions, the LSB of PCL is fixed to a value of ’0’. the stack register values stored by the low priority inter- The PC increments by 2 to address sequential rupt will be overwritten. instructions in the program memory. If high priority interrupts are not disabled during low pri- The CALL, RCALL, GOTO and program branch ority interrupts, users must save the key registers in instructions write to the program counter directly. For software during a low priority interrupt. these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. If no interrupts are used, the fast register stack can be used to restore the STATUS, WREG and BSR registers The contents of PCLATH and PCLATU will be trans- at the end of a subroutine call. To use the fast register ferred to the program counter by an operation that stack for a subroutine call, a FAST CALL instruction writes PCL. Similarly, the upper two bytes of the pro- must be executed. gram counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful Example4-1 shows a source code example that uses for computed offsets to the PC (see Section4.8.1). the fast register stack. 4.5 Clocking Scheme/Instruction EXAMPLE 4-1: FAST REGISTER STACK Cycle CODE EXAMPLE CALL SUB1, FAST ;STATUS, WREG, BSR The clock input (from OSC1) is internally divided by ;SAVED IN FAST REGISTER four to generate four non-overlapping quadrature ;STACK clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro- • gram counter (PC) is incremented every Q1, the • instruction is fetched from the program memory and latched into the instruction register in Q4. The instruc- SUB1 • • tion is decoded and executed during the following Q1 • through Q4. The clocks and instruction execution flow RETURN FAST ;RESTORE VALUES SAVED are shown in Figure4-4. ;IN FAST REGISTER STACK FIGURE 4-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC+2 PC+4 OSC2/CLKO (RC mode) Execute INST (PC-2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+2) Fetch INST (PC+4) © 2006 Microchip Technology Inc. DS39564C-page 39

PIC18FXX2 4.6 Instruction Flow/Pipelining A fetch cycle begins with the program counter (PC) incrementing in Q1. An “Instruction Cycle” consists of four Q cycles (Q1, In the execution cycle, the fetched instruction is latched Q2, Q3 and Q4). The instruction fetch and execute are into the “Instruction Register” (IR) in cycle Q1. This pipelined such that fetch takes one instruction cycle, instruction is then decoded and executed during the while decode and execute takes another instruction Q2, Q3, and Q4 cycles. Data memory is read during Q2 cycle. However, due to the pipelining, each instruction (operand read) and written during Q4 (destination effectively executes in one cycle. If an instruction write). causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example4-2). EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 4.7 Instructions in Program Memory The CALL and GOTO instructions have an absolute pro- gram memory address embedded into the instruction. The program memory is addressed in bytes. Instruc- Since instructions are always stored on word bound- tions are stored as two bytes or four bytes in program aries, the data contained in the instruction is a word memory. The Least Significant Byte of an instruction address. The word address is written to PC<20:1>, word is always stored in a program memory location which accesses the desired byte address in program with an even address (LSB =’0’). Figure4-5 shows an memory. Instruction #2 in Figure4-5 shows how the example of how instruction words are stored in the pro- instruction “GOTO 000006h’ is encoded in the program gram memory. To maintain alignment with instruction memory. Program branch instructions which encode a boundaries, the PC increments in steps of 2 and the relative address offset operate in the same manner. LSB will always read ’0’ (see Section4.4). The offset value stored in a branch instruction repre- sents the number of single word instructions that the PC will be offset by. Section20.0 provides further details of the instruction set. FIGURE 4-5: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 000006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h DS39564C-page 40 © 2006 Microchip Technology Inc.

PIC18FXX2 4.7.1 TWO-WORD INSTRUCTIONS second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action The PIC18FXX2 devices have four two-word instruc- is necessary when the two-word instruction is preceded tions: MOVFF, CALL, GOTO and LFSR. The second by a conditional instruction that changes the PC. A pro- word of these instructions has the 4 MSBs set to 1’s gram example that demonstrates this concept is shown and is a special kind of NOP instruction. The lower 12 in Example4-3. Refer to Section20.0 for further details bits of the second word contain data to be used by the of the instruction set. instruction. If the first word of the instruction is exe- cuted, the data in the second word is accessed. If the EXAMPLE 4-3: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of REG2 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes 1111 0100 0101 0110 ; 2nd operand becomes NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code 4.8 Lookup Tables 4.8.2 TABLE READS/TABLE WRITES Lookup tables are implemented two ways. These are: A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction (cid:129) Computed GOTO location. (cid:129) Table Reads Lookup table data may be stored 2 bytes per program 4.8.1 COMPUTED GOTO word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table A computed GOTO is accomplished by adding an offset latch (TABLAT) contains the data that is read from, or to the program counter (ADDWF PCL). written to program memory. Data is transferred to/from A lookup table can be formed with an ADDWF PCL program memory, one byte at a time. instruction and a group of RETLW 0xnn instructions. A description of the Table Read/Table Write operation WREG is loaded with an offset into the table before is shown in Section3.0. executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions, that returns the value 0xnn to the calling function. The offset value (value in WREG) specifies the number of bytes that the program counter should advance. In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Note: The ADDWF PCL instruction does not update PCLATH and PCLATU. A read operation on PCL must be performed to update PCLATH and PCLATU. © 2006 Microchip Technology Inc. DS39564C-page 41

PIC18FXX2 4.9 Data Memory Organization 4.9.1 GENERAL PURPOSE REGISTER FILE The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, The register file can be accessed either directly or indi- allowing up to 4096 bytes of data memory. Figure4-6 rectly. Indirect addressing operates using a File Select and Figure4-7 show the data memory organization for Register and corresponding Indirect File Operand. The the PIC18FXX2 devices. operation of indirect addressing is shown in Section4.12. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of Enhanced MCU devices may have banked memory in the Bank Select Register (BSR<3:0>) select which the GPR area. GPRs are not initialized by a Power-on bank will be accessed. The upper 4 bits for the BSR are Reset and are unchanged on all other RESETS. not implemented. Data RAM is available for use as GPR registers by all The data memory contains Special Function Registers instructions. The top half of Bank 15 (0xF80 to 0xFFF) (SFR) and General Purpose Registers (GPR). The contains SFRs. All other banks of data memory contain SFRs are used for control and status of the controller GPR registers, starting with Bank 0. and peripheral functions, while GPRs are used for data storage and scratch pad operations in the user’s appli- 4.9.2 SPECIAL FUNCTION REGISTERS cation. The SFRs start at the last location of Bank 15 The Special Function Registers (SFRs) are registers (0xFFF) and extend downwards. Any remaining space used by the CPU and Peripheral Modules for control- beyond the SFRs in the Bank may be implemented as ling the desired operation of the device. These regis- GPRs. GPRs start at the first location of Bank 0 and ters are implemented as static RAM. A list of these grow upwards. Any read of an unimplemented location registers is given in Table4-1 and Table4-2. will read as ’0’s. The SFRs can be classified into two sets; those asso- The entire data memory may be accessed directly or ciated with the “core” function and those related to the indirectly. Direct addressing may require the use of the peripheral functions. Those registers related to the BSR register. Indirect addressing requires the use of a “core” are described in this section, while those related File Select Register (FSRn) and a corresponding Indi- to the operation of the peripheral features are rect File Operand (INDFn). Each FSR holds a 12-bit described in the section of that peripheral feature. address value that can be used to access any location in the Data Memory map without banking. The SFRs are typically distributed among the peripherals whose functions they control. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect The unused SFR locations will be unimplemented and addressing or by the use of the MOVFF instruction. The read as '0's. See Table4-1 for addresses for the SFRs. MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section4.10 provides a detailed description of the Access RAM. DS39564C-page 42 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 4-6: DATA MEMORY MAP FOR PIC18F242/442 BSR<3:0> Data Memory Map 000h 00h Access RAM = 0000 07Fh Bank 0 080h GPR FFh 0FFh 00h 100h = 0001 GPR Bank 1 FFh 1FFh 00h 200h = 0010 Bank 2 GPR FFh 2FFh 300h Access Bank 00h Access RAM low 7Fh = 0011 Bank 3 Access RAM high 80h = 1110 to ReUandu s’0e0dh’ (SFRs) FFh Bank 14 When a = 0, the BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers EFFh (from Bank 15). 00h F00h = 1111 Unused F7Fh Bank 15 F80h FFh SFR FFFh When a = 1, the BSR is used to specify the RAM location that the instruction uses. © 2006 Microchip Technology Inc. DS39564C-page 43

PIC18FXX2 FIGURE 4-7: DATA MEMORY MAP FOR PIC18F252/452 BSR<3:0> Data Memory Map 000h 00h Access RAM = 0000 07Fh Bank 0 080h GPR FFh 0FFh 00h 100h = 0001 GPR Bank 1 FFh 1FFh 200h = 0010 00h Bank 2 GPR FFh 2FFh 00h 300h = 0011 Bank 3 GPR FFh 3FFh 400h = 0100 Bank 4 GPR Access Bank 4FFh 00h 00h 500h Access RAM low = 0101 7Fh Bank 5 GPR Access RAM high 80h FFh 5FFh (SFR’s) 600h FFh When a = 0, = 0110 Bank 6 Unused the BSR is ignored and the = 1110 to Read ’00h’ Access Bank is used. Bank 14 The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers EFFh (from Bank 15). 00h F00h = 1111 Unused F7Fh Bank 15 F80h FFh SFR FFFh When a = 1, the BSR is used to specify the RAM location that the instruction uses. DS39564C-page 44 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 4-1: SPECIAL FUNCTION REGISTER MAP Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch — FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh — FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah — FF9h PCL FD9h FSR2L FB9h — F99h — FF8h TBLPTRU FD8h STATUS FB8h — F98h — FF7h TBLPTRH FD7h TMR0H FB7h — F97h — FF6h TBLPTRL FD6h TMR0L FB6h — F96h TRISE(2) FF5h TABLAT FD5h T0CON FB5h — F95h TRISD(2) FF4h PRODH FD4h — FB4h — F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h — FF0h INTCON3 FD0h RCON FB0h — F90h — FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh — FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh — FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE(2) FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD(2) FEBh PLUSW0(3) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh — F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h — FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2 F87h — FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h — FE5h POSTDEC1(3) FC5h SSPCON2 FA5h — F85h — FE4h PREINC1(3) FC4h ADRESH FA4h — F84h PORTE(2) FE3h PLUSW1(3) FC3h ADRESL FA3h — F83h PORTD(2) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h — FA0h PIE2 F80h PORTA Note 1: Unimplemented registers are read as ’0’. 2: This register is not available on PIC18F2X2 devices. 3: This is not a physical register. © 2006 Microchip Technology Inc. DS39564C-page 45

PIC18FXX2 TABLE 4-2: REGISTER FILE SUMMARY Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack upper Byte (TOS<20:16>) ---0 0000 37 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 37 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 37 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 38 PCLATU — — — Holding Register for PC<20:16> ---0 0000 39 PCLATH Holding Register for PC<15:8> 0000 0000 39 PCL PC Low Byte (PC<7:0>) 0000 0000 39 TBLPTRU — — bit21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 58 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 58 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 58 TABLAT Program Memory Table Latch 0000 0000 58 PRODH Product Register High Byte xxxx xxxx 71 PRODL Product Register Low Byte xxxx xxxx 71 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 75 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 76 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 77 INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) n/a 50 POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a 50 POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) n/a 50 PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a 50 PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 (not a physical register). n/a 50 Offset by value in WREG. FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 50 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 50 WREG Working Register xxxx xxxx n/a INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) n/a 50 POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a 50 POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) n/a 50 PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) n/a 50 PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 (not a physical register). n/a 50 Offset by value in WREG. FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 50 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 50 BSR — — — — Bank Select Register ---- 0000 49 INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) n/a 50 POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a 50 POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) n/a 50 PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a 50 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 (not a physical register). n/a 50 Offset by value in WREG. FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 50 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50 STATUS — — — N OV Z DC C ---x xxxx 52 TMR0H Timer0 Register High Byte 0000 0000 105 TMR0L Timer0 Register Low Byte xxxx xxxx 105 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 103 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear. DS39564C-page 46 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: OSCCON — — — — — — — SCS ---- ---0 21 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 191 WDTCON — — — — — — — SWDTE ---- ---0 203 RCON IPEN — — RI TO PD POR BOR 0--1 11qq 53, 28, 84 TMR1H Timer1 Register High Byte xxxx xxxx 107 TMR1L Timer1 Register Low Byte xxxx xxxx 107 T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 107 TMR2 Timer2 Register 0000 0000 111 PR2 Timer2 Period Register 1111 1111 112 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 111 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 125 SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 134 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 126 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 127 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 137 ADRESH A/D Result Register High Byte xxxx xxxx 187,188 ADRESL A/D Result Register Low Byte xxxx xxxx 187,188 ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 181 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 182 CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 121, 123 CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 121, 123 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 117 CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx 121, 123 CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx 121, 123 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 117 TMR3H Timer3 Register High Byte xxxx xxxx 113 TMR3L Timer3 Register Low Byte xxxx xxxx 113 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 113 SPBRG USART1 Baud Rate Generator 0000 0000 168 RCREG USART1 Receive Register 0000 0000 175, 178, 180 TXREG USART1 Transmit Register 0000 0000 173, 176, 179 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 166 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 167 EEADR Data EEPROM Address Register 0000 0000 65, 69 EEDATA Data EEPROM Data Register 0000 0000 69 EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 65, 69 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 66 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear. © 2006 Microchip Technology Inc. DS39564C-page 47

PIC18FXX2 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 83 PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 79 PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 81 IPR1 PSPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 82 PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 78 PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 80 TRISE(3) IBF OBF IBOV PSPMODE — Data Direction bits for PORTE 0000 -111 98 TRISD(3) Data Direction Control Register for PORTD 1111 1111 96 TRISC Data Direction Control Register for PORTC 1111 1111 93 TRISB Data Direction Control Register for PORTB 1111 1111 90 TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 87 LATE(3) — — — — — Read PORTE Data Latch, ---- -xxx 99 Write PORTE Data Latch LATD(3) Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 95 LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 93 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 90 LATA — LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 87 PORTE(3) Read PORTE pins, Write PORTE Data Latch ---- -000 99 PORTD(3) Read PORTD pins, Write PORTD Data Latch xxxx xxxx 95 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 93 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 90 PORTA — RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 87 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear. DS39564C-page 48 © 2006 Microchip Technology Inc.

PIC18FXX2 4.10 Access Bank 4.11 Bank Select Register (BSR) The Access Bank is an architectural enhancement The need for a large general purpose memory space which is very useful for C compiler code optimization. dictates a RAM banking scheme. The data memory is The techniques used by the C compiler may also be partitioned into sixteen banks. When using direct useful for programs written in assembly. addressing, the BSR should be configured for the desired bank. This data memory region can be used for: BSR<3:0> holds the upper 4 bits of the 12-bit RAM (cid:129) Intermediate computational values address. The BSR<7:4> bits will always read ’0’s, and (cid:129) Local variables of subroutines writes will have no effect. (cid:129) Faster context saving/switching of variables A MOVLB instruction has been provided in the (cid:129) Common variables instruction set to assist in selecting banks. (cid:129) Faster evaluation/control of SFRs (no banking) If the currently selected bank is not implemented, any The Access Bank is comprised of the upper 128 bytes read will return all '0's and all writes are ignored. The in Bank 15 (SFRs) and the lower 128 bytes in Bank 0. STATUS register bits will be set/cleared as appropriate These two sections will be referred to as Access RAM for the instruction performed. High and Access RAM Low, respectively. Figure4-6 Each Bank extends up to FFh (256 bytes). All data and Figure4-7 indicate the Access RAM areas. memory is implemented as static RAM. A bit in the instruction word specifies if the operation is A MOVFF instruction ignores the BSR, since the 12-bit to occur in the bank specified by the BSR register or in addresses are embedded into the instruction word. the Access Bank. This bit is denoted by the ’a’ bit (for access bit). Section4.12 provides a description of indirect address- ing, which allows linear addressing of the entire RAM When forced in the Access Bank (a = 0), the last space. address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function registers, so that these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. FIGURE 4-8: DIRECT ADDRESSING Direct Addressing BSR<3:0> 7 From Opcode(3) 0 Bank Select(2) Location Select(3) 00h 01h 0Eh 0Fh 000h 100h E00h F00h Data Memory(1) 0FFh 1FFh EFFh FFFh Bank 0 Bank 1 Bank 14 Bank 15 Note 1: For register file map detail, see Table4-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. © 2006 Microchip Technology Inc. DS39564C-page 49

PIC18FXX2 4.12 Indirect Addressing, INDF and the data from the address pointed to by FSR Registers FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. Indirect addressing is a mode of addressing data mem- If INDF0, INDF1 or INDF2 are read indirectly via an ory, where the data memory address in the instruction FSR, all '0's are read (zero bit is set). Similarly, if is not fixed. An FSR register is used as a pointer to the INDF0, INDF1 or INDF2 are written to indirectly, the data memory location that is to be read or written. Since operation will be equivalent to a NOP instruction and the this pointer is in RAM, the contents can be modified by STATUS bits are not affected. the program. This can be useful for data tables in the data memory and for software stacks. Figure4-9 4.12.1 INDIRECT ADDRESSING shows the operation of indirect addressing. This shows OPERATION the moving of the value to the data memory address specified by the value of the FSR register. Each FSR register has an INDF register associated with it, plus four additional register addresses. Perform- Indirect addressing is possible by using one of the ing an operation on one of these five registers deter- INDF registers. Any instruction using the INDF register mines how the FSR will be modified during indirect actually accesses the register pointed to by the File addressing. Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF When data access is done to one of the five INDFn register indirectly, results in a no operation. The FSR locations, the address selected will configure the FSRn register contains a 12-bit address, which is shown in register to: Figure4-10. (cid:129) Do nothing to FSRn after an indirect access (no The INDFn register is not a physical register. Address- change) - INDFn ing INDFn actually addresses the register whose (cid:129) Auto-decrement FSRn after an indirect access address is contained in the FSRn register (FSRn is a (post-decrement) - POSTDECn pointer). This is indirect addressing. (cid:129) Auto-increment FSRn after an indirect access Example4-4 shows a simple use of indirect addressing (post-increment) - POSTINCn to clear the RAM in Bank1 (locations 100h-1FFh) in a (cid:129) Auto-increment FSRn before an indirect access minimum number of instructions. (pre-increment) - PREINCn (cid:129) Use the value in the WREG register as an offset EXAMPLE 4-4: HOW TO CLEAR RAM to FSRn. Do not modify the value of the WREG or (BANK1) USING INDIRECT the FSRn register after an indirect access (no ADDRESSING change) - PLUSWn LFSR FSR0 ,0x100 ; When using the auto-increment or auto-decrement fea- NEXT CLRF POSTINC0 ; Clear INDF tures, the effect on the FSR is not reflected in the ; register and STATUS register. For example, if the indirect address ; inc pointer causes the FSR to equal '0', the Z bit will not be set. BTFSS FSR0H, 1 ; All done with ; Bank1? Incrementing or decrementing an FSR affects all 12 GOTO NEXT ; NO, clear next bits. That is, when FSRnL overflows from an increment, CONTINUE ; YES, continue FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a There are three indirect addressing registers. To stack pointer, in addition to its uses for table operations address the entire data memory space (4096 bytes), in data memory. these registers are 12-bit wide. To store the 12-bits of Each FSR has an address associated with it that per- addressing information, two 8-bit registers are forms an indexed indirect access. When a data access required. These indirect addressing registers are: to this INDFn location (PLUSWn) occurs, the FSRn is 1. FSR0: composed of FSR0H:FSR0L configured to add the signed value in the WREG regis- 2. FSR1: composed of FSR1H:FSR1L ter and the value in FSR to form the address before an 3. FSR2: composed of FSR2H:FSR2L indirect access. The FSR value is not changed. In addition, there are registers INDF0, INDF1 and If an FSR register contains a value that points to one of INDF2, which are not physically implemented. Reading the INDFn, an indirect read will read 00h (zero bit is or writing to these registers activates indirect address- set), while an indirect write will be equivalent to a NOP ing, with the value in the corresponding FSR register (STATUS bits are not affected). being the address of the data. If an instruction writes a If an indirect addressing operation is done where the value to INDF0, the value will be written to the address target address is an FSRnH or FSRnL register, the pointed to by FSR0H:FSR0L. A read from INDF1 reads write operation will dominate over the pre- or post-increment/decrement functions. DS39564C-page 50 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 4-9: INDIRECT ADDRESSING OPERATION 0h RAM Instruction Executed Opcode Address FFFh 12 File Address = access of an indirect addressing register BSR<3:0> 12 12 Instruction Fetched 4 8 Opcode File FSR FIGURE 4-10: INDIRECT ADDRESSING Indirect Addressing 11 FSR Register 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table4-1. © 2006 Microchip Technology Inc. DS39564C-page 51

PIC18FXX2 4.13 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register4-2, contains as 000u u1uu (where u = unchanged). the arithmetic status of the ALU. The STATUS register It is recommended, therefore, that only BCF, BSF, can be the destination for any instruction, as with any SWAPF, MOVFF and MOVWF instructions are used to other register. If the STATUS register is the destination alter the STATUS register, because these instructions for an instruction that affects the Z, DC, C, OV, or N bits, do not affect the Z, C, DC, OV, or N bits from the then the write to these five bits is disabled. These bits STATUS register. For other instructions not affecting are set or cleared according to the device logic. There- any status bits, see Table20-2. fore, the result of an instruction with the STATUS register as destination may be different than intended. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. REGISTER 4-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 52 © 2006 Microchip Technology Inc.

PIC18FXX2 4.14 RCON Register Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is The Reset Control (RCON) register contains flag bits ’1’ on a Power-on Reset. After a Brown- that allow differentiation between the sources of a out Reset has occurred, the BOR bit will device RESET. These flags include the TO, PD, POR, be cleared, and must be set by firmware to BOR and RI bits. This register is readable and writable. indicate the occurrence of the next Brown-out Reset. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. REGISTER 4-3: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as '0' bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device RESET (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 53

PIC18FXX2 NOTES: DS39564C-page 54 © 2006 Microchip Technology Inc.

PIC18FXX2 5.0 FLASH PROGRAM MEMORY 5.1 Table Reads and Table Writes The FLASH Program Memory is readable, writable, In order to read and write program memory, there are and erasable during normal operation over the entire two operations that allow the processor to move bytes VDD range. between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on (cid:129) Table Read (TBLRD) blocks of 8 bytes at a time. Program memory is erased (cid:129) Table Write (TBLWT) in blocks of 64 bytes at a time. A bulk erase operation The program memory space is 16-bits wide, while the may not be issued from user code. data RAM space is 8-bits wide. Table Reads and Table Writing or erasing program memory will cease instruc- Writes move data between these two memory spaces tion fetches until the operation is complete. The pro- through an 8-bit register (TABLAT). gram memory cannot be accessed during the write or Table Read operations retrieve data from program erase, therefore, code cannot execute. An internal pro- memory and places it into the data RAM space. gramming timer terminates program memory writes Figure5-1 shows the operation of a Table Read with and erases. program memory and data RAM. A value written to program memory does not need to be Table Write operations store data from the data mem- a valid instruction. Executing a program memory ory space into holding registers in program memory. location that forms an invalid instruction results in a The procedure to write the contents of the holding reg- NOP. isters into program memory is detailed in Section5.5, '”Writing to FLASH Program Memory”. Figure5-2 shows the operation of a Table Write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a Table Write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 5-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. © 2006 Microchip Technology Inc. DS39564C-page 55

PIC18FXX2 FIGURE 5-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section5.5. 5.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When the FREE bit is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. (cid:129) EECON1 register The WREN bit, when set, will allow a write operation. (cid:129) EECON2 register On power-up, the WREN bit is clear. The WRERR bit is (cid:129) TABLAT register set when a write operation is interrupted by a MCLR (cid:129) TBLPTR registers Reset or a WDT Time-out Reset during normal opera- tion. In these situations, the user can check the 5.2.1 EECON1 AND EECON2 REGISTERS WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EECON1 is the control register for memory accesses. EEADR), due to RESET values of zero. EECON2 is not a physical register. Reading EECON2 Control bit WR initiates write operations. This bit cannot will read all '0's. The EECON2 register is used be cleared, only set, in software. It is cleared in hard- exclusively in the memory write and erase sequences. ware at the completion of the write operation. The Control bit EEPGD determines if the access will be a inability to clear the WR bit in software prevents the program or data EEPROM memory access. When accidental or premature termination of a write clear, any subsequent operations will operate on the operation. data EEPROM memory. When set, any subsequent Note: Interrupt flag bit EEIF, in the PIR2 register, operations will operate on the program memory. is set when the write is complete. It must Control bit CFGS determines if the access will be to the be cleared in software. configuration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on configuration registers, regardless of EEPGD (see “Special Features of the CPU”, Section19.0). When clear, memory selection access is determined by EEPGD. DS39564C-page 56 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 =Access FLASH Program memory 0 =Access Data EEPROM memory bit 6 CFGS: FLASH Program/Data EE or Configuration Select bit 1 =Access Configuration registers 0 =Access FLASH Program or Data EEPROM memory bit 5 Unimplemented: Read as '0' bit 4 FREE: FLASH Row Erase Enable bit 1 =Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 =Perform write only bit 3 WRERR: FLASH Program/Data EE Error Flag bit 1 =A write operation is prematurely terminated (any RESET during self-timed programming in normal operation) 0 =The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: FLASH Program/Data EE Write Enable bit 1 =Allows write cycles 0 =Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 =Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 =Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 =Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 =Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 57

PIC18FXX2 5.2.2 TABLAT - TABLE LATCH REGISTER 5.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes, and erases of the into the SFR space. The Table Latch is used to hold FLASH program memory. 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the Table memory and data RAM. Pointer determine which byte is read from program memory into TABLAT. 5.2.3 TBLPTR - TABLE POINTER REGISTER When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight The Table Pointer (TBLPTR) addresses a byte within program memory holding registers is written to. When the program memory. The TBLPTR is comprised of the timed write to program memory (long write) begins, three SFR registers: Table Pointer Upper Byte, Table the 19 MSbs of the Table Pointer, TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:3>), will determine which program mem- (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- ory block of 8 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low order 21 Section5.5 (“Writing to FLASH Program Memory”). bits allow the device to address up to 2 Mbytes of pro- When an erase of program memory is executed, the 16 gram memory space. The 22nd bit allows access to the MSbs of the Table Pointer (TBLPTR<21:6>) point to the Device ID, the User ID and the Configuration bits. 64-byte block that will be erased. The Least Significant The table pointer, TBLPTR, is used by the TBLRD and bits (TBLPTR<5:0>) are ignored. TBLWT instructions. These instructions can update the Figure5-3 describes the relevant boundaries of TBLPTR in one of four ways based on the table opera- TBLPTR based on FLASH program memory tion. These operations are shown in Table5-1. These operations. operations on the TBLPTR only affect the low order 21bits. TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 5-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE - TBLPTR<21:6> WRITE - TBLPTR<21:3> READ - TBLPTR<21:0> DS39564C-page 58 © 2006 Microchip Technology Inc.

PIC18FXX2 5.3 Reading the FLASH Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from pro- automatically for the next Table Read operation. gram memory and place into data RAM. Table Reads The internal program memory is typically organized by from program memory are performed one byte at a words. The Least Significant bit of the address selects time. between the high and low bytes of the word. Figure5-4 shows the interface between the internal program memory and the TABLAT. FIGURE 5-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 5-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_ODD © 2006 Microchip Technology Inc. DS39564C-page 59

PIC18FXX2 5.4 Erasing FLASH Program memory 5.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP control can larger blocks of program memory be program memory location is: bulk erased. Word erase in the FLASH array is not 1. Load table pointer with address of row being supported. erased. When initiating an erase sequence from the micro- 2. Set EEPGD bit to point to program memory, controller itself, a block of 64 bytes of program memory clear CFGS bit to access program memory, set is erased. The Most Significant 16 bits of the WREN bit to enable writes, and set FREE bit to TBLPTR<21:6> point to the block being erased. enable the erase. TBLPTR<5:0> are ignored. 3. Disable interrupts. The EECON1 register commands the erase operation. 4. Write 55h to EECON2. The EEPGD bit must be set to point to the FLASH pro- 5. Write AAh to EECON2. gram memory. The WREN bit must be set to enable 6. Set the WR bit. This will begin the row erase write operations. The FREE bit is set to select an erase cycle. operation. 7. The CPU will stall for duration of the erase For protection, the write initiate sequence for EECON2 (about 2ms using internal timer). must be used. 8. Re-enable interrupts. A long write is necessary for erasing the internal FLASH. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 5-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1,EEPGD ; point to FLASH program memory BCF EECON1,CFGS ; access FLASH program memory BSF EECON1,WREN ; enable write to memory BSF EECON1,FREE ; enable Row Erase operation BCF INTCON,GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW AAh MOVWF EECON2 ; write AAh BSF EECON1,WR ; start erase (CPU stall) BSF INTCON,GIE ; re-enable interrupts DS39564C-page 60 © 2006 Microchip Technology Inc.

PIC18FXX2 5.5 Writing to FLASH Program operations will essentially be short writes, because only Memory the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to The minimum programming block is 4 words or 8 bytes. start the programming operation with a long write. Word or byte programming is not supported. The long write is necessary for programming the inter- Table Writes are used internally to load the holding reg- nal FLASH. Instruction execution is halted while in a isters needed to program the FLASH memory. There long write cycle. The long write will be terminated by are 8 holding registers used by the Table Writes for the internal programming timer. programming. The EEPROM on-chip timer controls the write time. Since the Table Latch (TABLAT) is only a single byte, The write/erase voltages are generated by an on-chip the TBLWT instruction has to be executed 8 times for charge pump rated to operate over the voltage range of each programming operation. All of the Table Write the device for byte or word operations. FIGURE 5-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxxx7 Holding Register Holding Register Holding Register Holding Register Program Memory 5.5.1 FLASH PROGRAM MEMORY WRITE 10. Write AAh to EECON2. SEQUENCE 11. Set the WR bit. This will begin the write cycle. 12. The CPU will stall for duration of the write (about The sequence of events for programming an internal 2ms using internal timer). program memory location should be: 13. Re-enable interrupts. 1. Read 64 bytes into RAM. 14. Repeat steps 6-14 seven times, to write 2. Update data values in RAM as necessary. 64bytes. 3. Load Table Pointer with address being erased. 15. Verify the memory (Table Read). 4. Do the row erase procedure. This procedure will require about 18ms to update one 5. Load Table Pointer with address of first byte row of 64 bytes of memory. An example of the required being written. code is given in Example5-3. 6. Write the first 8 bytes into the holding registers with auto-increment (TBLWT*+ or TBLWT+*). Note: Before setting the WR bit, the table pointer address needs to be within the intended 7. Set EEPGD bit to point to program memory, address range of the 8 bytes in the holding clear the CFGS bit to access program memory, registers. and set WREN to enable byte writes. 8. Disable interrupts. 9. Write 55h to EECON2. © 2006 Microchip Technology Inc. DS39564C-page 61

PIC18FXX2 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1,EEPGD ; point to FLASH program memory BCF EECON1,CFGS ; access FLASH program memory BSF EECON1,WREN ; enable write to memory BSF EECON1,FREE ; enable Row Erase operation BCF INTCON,GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55h MOVLW AAh MOVWF EECON2 ; write AAh BSF EECON1,WR ; start erase (CPU stall) BSF INTCON,GIE ; re-enable interrupts TBLRD*- ; dummy read decrement WRITE_BUFFER_BACK MOVLW 8 ; number of write buffer groups of 8 bytes MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L PROGRAM_LOOP MOVLW 8 ; number of bytes in holding register MOVWF COUNTER WRITE_WORD_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS DS39564C-page 62 © 2006 Microchip Technology Inc.

PIC18FXX2 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1,EEPGD ; point to FLASH program memory BCF EECON1,CFGS ; access FLASH program memory BSF EECON1,WREN ; enable write to memory BCF INTCON,GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW AAh MOVWF EECON2 ; write AAh BSF EECON1,WR ; start program (CPU stall) BSF INTCON,GIE ; re-enable interrupts DECFSZ COUNTER_HI ; loop until done BRA PROGRAM_LOOP BCF EECON1,WREN ; disable write to memory 5.5.2 WRITE VERIFY 5.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the mem- To protect against spurious writes to FLASH program ory should be verified against the original value. This memory, the write initiate sequence must also be fol- should be used in applications where excessive writes lowed. See “Special Features of the CPU” can stress bits near the specification limit. (Section19.0) for more detail. 5.5.3 UNEXPECTED TERMINATION OF 5.6 FLASH Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as See “Special Features of the CPU” (Section19.0) for loss of power or an unexpected RESET, the memory details on code protection of FLASH program memory. location just programmed should be verified and repro- grammed if needed.The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situ- ations, users can check the WRERR bit and rewrite the location. TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS FF8h TBLPTRU — — bit21 Program Memory Table Pointer Upper Byte --00 0000 --00 0000 (TBLPTR<20:16>) FF7h TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 FF6h TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000 FF5h TABLAT Program Memory Table Latch 0000 0000 0000 0000 FF2h INTCON GIE/ PEIE/ TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u GIEH GIEL FA7h EECON2 EEPROM Control Register2 (not a physical register) — — FA6h EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 FA2h IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111 FA1h PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000 FA0h PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000 Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as '0'. Shaded cells are not used during FLASH/EEPROM access. © 2006 Microchip Technology Inc. DS39564C-page 63

PIC18FXX2 NOTES: DS39564C-page 64 © 2006 Microchip Technology Inc.

PIC18FXX2 6.0 DATA EEPROM MEMORY 6.1 EEADR The Data EEPROM is readable and writable during The address register can address up to a maximum of normal operation over the entire VDD range. The data 256 bytes of data EEPROM. memory is not directly mapped in the register file 6.2 EECON1 and EECON2 Registers space. Instead, it is indirectly addressed through the Special Function Registers (SFR). EECON1 is the control register for EEPROM memory There are four SFRs used to read and write the accesses. program and data EEPROM memory. These registers EECON2 is not a physical register. Reading EECON2 are: will read all '0's. The EECON2 register is used (cid:129) EECON1 exclusively in the EEPROM write sequence. (cid:129) EECON2 Control bits RD and WR initiate read and write opera- (cid:129) EEDATA tions, respectively. These bits cannot be cleared, only (cid:129) EEADR set, in software. They are cleared in hardware at the completion of the read or write operation. The inability The EEPROM data memory allows byte read and write. to clear the WR bit in software prevents the accidental When interfacing to the data memory block, EEDATA or premature termination of a write operation. holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. The WREN bit, when set, will allow a write operation. These devices have 256 bytes of data EEPROM with On power-up, the WREN bit is clear. The WRERR bit is an address range from 0h to FFh. set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal opera- The EEPROM data memory is rated for high erase/ tion. In these situations, the user can check the write cycles. A byte write automatically erases the loca- WRERR bit and rewrite the location. It is necessary to tion and writes the new data (erase-before-write). The reload the data and address registers (EEDATA and write time is controlled by an on-chip timer. The write EEADR), due to the RESET condition forcing the time will vary with voltage and temperature, as well as contents of the registers to zero. from chip to chip. Please refer to parameterD122 (Electrical Characteristics, Section22.0) for exact limits. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software. © 2006 Microchip Technology Inc. DS39564C-page 65

PIC18FXX2 REGISTER 6-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 =Access FLASH Program memory 0 =Access Data EEPROM memory bit 6 CFGS: FLASH Program/Data EE or Configuration Select bit 1 =Access Configuration or Calibration registers 0 =Access FLASH Program or Data EEPROM memory bit 5 Unimplemented: Read as '0' bit 4 FREE: FLASH Row Erase Enable bit 1 =Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 =Perform write only bit 3 WRERR: FLASH Program/Data EE Error Flag bit 1 =A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 =The write operation completed Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. bit 2 WREN: FLASH Program/Data EE Write Enable bit 1 =Allows write cycles 0 =Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 =Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 =Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 =Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 =Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 66 © 2006 Microchip Technology Inc.

PIC18FXX2 6.3 Reading the Data EEPROM (EECON1<6>), and then set control bit RD Memory (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can To read a data memory location, the user must write the be read by the next instruction. EEDATA will hold this address to the EEADR register, clear the EEPGD con- value until another read operation, or until it is written to trol bit (EECON1<7>), clear the CFGS control bit by the user (during a write operation). EXAMPLE 6-1: DATA EEPROM READ MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access program FLASH or Data EEPROM memory BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA 6.4 Writing to the Data EEPROM cution (i.e., runaway programs). The WREN bit should Memory be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared byhardware. To write an EEPROM data location, the address must After a write sequence has been initiated, EECON1, first be written to the EEADR register and the data writ- EEADR and EDATA cannot be modified. The WR bit ten to the EEDATA register. Then the sequence in will be inhibited from being set unless the WREN bit is Example6-2 must be followed to initiate the write cycle. set. The WREN bit must be set on a previous instruc- The write will not initiate if the above sequence is not tion. Both WR and WREN cannot be set with the same exactly followed (write 55h to EECON2, write AAh to instruction. EECON2, then set WR bit) for each byte. It is strongly At the completion of the write cycle, the WR bit is recommended that interrupts be disabled during this cleared in hardware and the EEPROM Write Complete codesegment. Interrupt Flag bit (EEIF) is set. The user may either Additionally, the WREN bit in EECON1 must be set to enable this interrupt, or poll this bit. EEIF must be enable writes. This mechanism prevents accidental cleared by software. writes to data EEPROM due to unexpected code exe- EXAMPLE 6-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access program FLASH or Data EEPROM memory BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable interrupts Required MOVLW 55h ; Sequence MOVWF EECON2 ; Write 55h MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable interrupts . ; user code execution . . BCF EECON1, WREN ; Disable writes on write complete (EEIF set) © 2006 Microchip Technology Inc. DS39564C-page 67

PIC18FXX2 6.5 Write Verify 6.7 Operation During Code Protect Depending on the application, good programming Data EEPROM memory has its own code protect practice may dictate that the value written to the mem- mechanism. External Read and Write operations are ory should be verified against the original value. This disabled if either of these mechanisms are enabled. should be used in applications where excessive writes The microcontroller itself can both read and write to the can stress bits near the specification limit. internal Data EEPROM, regardless of the state of the code protect configuration bit. Refer to “Special Features 6.6 Protection Against Spurious Write of the CPU” (Section19.0) for additional information. There are conditions when the device may not want to 6.8 Using the Data EEPROM write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have The data EEPROM is a high endurance, byte address- been built-in. On power-up, the WREN bit is cleared. able array that has been optimized for the storage of Also, the Power-up Timer (72 ms duration) prevents frequently changing information (e.g., program vari- EEPROMwrite. ables or other data that are updated often). Frequently The write initiate sequence and the WREN bit together changing values will typically be updated more often help prevent an accidental write during brown-out, than specification D124. If this is not the case, an array power glitch, or software malfunction. refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, cali- bration, etc.) should be stored in FLASH program memory. A simple data EEPROM refresh routine is shown in Example6-3. Note: If data EEPROM is only used to store con- stants and/or data that changes rarely, an array refresh is likely not required. See specification D124. EXAMPLE 6-3: DATA EEPROM REFRESH ROUTINE clrf EEADR ; Start at address 0 bcf EECON1,CFGS ; Set for memory bcf EECON1,EEPGD ; Set for Data EEPROM bcf INTCON,GIE ; Disable interrupts bsf EECON1,WREN ; Enable writes Loop ; Loop to refresh array bsf EECON1,RD ; Read current address movlw 55h ; movwf EECON2 ; Write 55h movlw AAh ; movwf EECON2 ; Write AAh bsf EECON1,WR ; Set WR bit to begin write btfsc EECON1,WR ; Wait for write to complete bra $-2 incfsz EEADR,F ; Increment address bra Loop ; Not zero, do it again bcf EECON1,WREN ; Disable writes bsf INTCON,GIE ; Enable interrupts DS39564C-page 68 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 6-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS FF2h INTCON GIE/ PEIE/ T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u GIEH GIEL FA9h EEADR EEPROM Address Register 0000 0000 0000 0000 FA8h EEDATA EEPROM Data Register 0000 0000 0000 0000 FA7h EECON2 EEPROM Control Register2 (not a physical register) — — FA6h EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 FA2h IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111 FA1h PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000 FA0h PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000 Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. © 2006 Microchip Technology Inc. DS39564C-page 69

PIC18FXX2 NOTES: DS39564C-page 70 © 2006 Microchip Technology Inc.

PIC18FXX2 7.0 8 X 8 HARDWARE MULTIPLIER Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: 7.1 Introduction (cid:129) Higher computational throughput An 8 x 8 hardware multiplier is included in the ALU of (cid:129) Reduces code size requirements for multiply the PIC18FXX2 devices. By making the multiply a algorithms hardware operation, it completes in a single instruction The performance increase allows the device to be used cycle. This is an unsigned multiply that gives a 16-bit in applications previously reserved for Digital Signal result. The result is stored into the 16-bit product regis- Processors. ter pair (PRODH:PRODL). The multiplier does not Table7-1 shows a performance comparison between affect any flags in the ALUSTA register. enhanced devices using the single cycle hardware mul- tiply, and performing the same function without the hardware multiply. TABLE 7-1: PERFORMANCE COMPARISON Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 μs Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 μs 6 μs Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware multiply 24 24 2.4 μs 9.6 μs 24 μs Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs 16 x 16 signed Hardware multiply 36 36 3.6 μs 14.4 μs 36 μs 7.2 Operation EXAMPLE 7-2: 8 x 8 SIGNED MULTIPLY ROUTINE Example7-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required MOVF ARG1, W when one argument of the multiply is already loaded in MULWF ARG2 ; ARG1 * ARG2 -> the WREG register. ; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit Example7-2 shows the sequence to do an 8 x 8 signed SUBWF PRODH, F ; PRODH = PRODH multiply. To account for the sign bits of the arguments, ; - ARG1 each argument’s Most Significant bit (MSb) is tested MOVF ARG2, W and the appropriate subtractions are done. BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH EXAMPLE 7-1: 8 x 8 UNSIGNED ; - ARG2 MULTIPLY ROUTINE Example7-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation7-1 shows the algorithm MOVF ARG1, W ; that is used. The 32-bit result is stored in four registers, MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL RES3:RES0. EQUATION 7-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + (ARG1L • ARG2L) © 2006 Microchip Technology Inc. DS39564C-page 71

PIC18FXX2 EXAMPLE 7-3: 16 x 16 UNSIGNED EXAMPLE 7-4: 16 x 16 SIGNED MULTIPLY ROUTINE MULTIPLY ROUTINE MOVF ARG1L, W MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L -> MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ; MOVFF PRODL, RES0 ; ; ; MOVF ARG1H, W MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H -> MULWF ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL ; PRODH:PRODL MOVFF PRODH, RES3 ; MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ; MOVFF PRODL, RES2 ; ; ; MOVF ARG1L, W MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H -> MULWF ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL ; PRODH:PRODL MOVF PRODL, W ; MOVF PRODL, W ; ADDWF RES1, F ; Add cross ADDWF RES1, F ; Add cross MOVF PRODH, W ; products MOVF PRODH, W ; products ADDWFC RES2, F ; ADDWFC RES2, F ; CLRF WREG ; CLRF WREG ; ADDWFC RES3, F ; ADDWFC RES3, F ; ; ; MOVF ARG1H, W ; MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L -> MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL ; PRODH:PRODL MOVF PRODL, W ; MOVF PRODL, W ; ADDWF RES1, F ; Add cross ADDWF RES1, F ; Add cross MOVF PRODH, W ; products MOVF PRODH, W ; products ADDWFC RES2, F ; ADDWFC RES2, F ; CLRF WREG ; CLRF WREG ; ADDWFC RES3, F ; ADDWFC RES3, F ; ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? Example7-4 shows the sequence to do a 16 x 16 BRA SIGN_ARG1 ; no, check ARG1 signed multiply. Equation7-2 shows the algorithm MOVF ARG1L, W ; used. The 32-bit result is stored in four registers, SUBWF RES2 ; RES3:RES0. To account for the sign bits of the argu- MOVF ARG1H, W ; ments, each argument pairs Most Significant bit (MSb) SUBWFB RES3 is tested and the appropriate subtractions are done. ; SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? EQUATION 7-2: 16 x 16 SIGNED BRA CONT_CODE ; no, done MULTIPLICATION MOVF ARG2L, W ; ALGORITHM SUBWF RES2 ; MOVF ARG2H, W ; RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L SUBWFB RES3 ; = (ARG1H • ARG2H • 216) + CONT_CODE (ARG1H • ARG2L • 28) + : (ARG1L • ARG2H • 28) + (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + (-1 • ARG1H<7> • ARG2H:ARG2L • 216) DS39564C-page 72 © 2006 Microchip Technology Inc.

PIC18FXX2 8.0 INTERRUPTS When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- The PIC18FXX2 devices have multiple interrupt patible with PICmicro® mid-range devices. In sources and an interrupt priority feature that allows Compatibility mode, the interrupt priority bits for each each interrupt source to be assigned a high priority source have no effect. INTCON<6> is the PEIE bit, level or a low priority level. The high priority interrupt which enables/disables all peripheral interrupt sources. vector is at 000008h and the low priority interrupt vector INTCON<7> is the GIE bit, which enables/disables all is at 000018h. High priority interrupt events will over- interrupt sources. All interrupts branch to address ride any low priority interrupts that may be in progress. 000008h in Compatibility mode. There are ten registers which are used to control When an interrupt is responded to, the Global Interrupt interrupt operation. These registers are: Enable bit is cleared to disable further interrupts. If the (cid:129) RCON IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. (cid:129) INTCON High priority interrupt sources can interrupt a low (cid:129) INTCON2 priority interrupt. (cid:129) INTCON3 The return address is pushed onto the stack and the (cid:129) PIR1, PIR2 PC is loaded with the interrupt vector address (cid:129) PIE1, PIE2 (000008h or 000018h). Once in the Interrupt Service (cid:129) IPR1, IPR2 Routine, the source(s) of the interrupt can be deter- It is recommended that the Microchip header files sup- mined by polling the interrupt flag bits. The interrupt plied with MPLAB® IDE be used for the symbolic bit flag bits must be cleared in software before re-enabling names in these registers. This allows the assembler/ interrupts to avoid recursive interrupts. compiler to automatically take care of the placement of The “return from interrupt” instruction, RETFIE, exits these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL Each interrupt source, except INT0, has three bits to if priority levels are used), which re-enables interrupts. control its operation. The functions of these bits are: For external interrupt events, such as the INT pins or (cid:129) Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. (cid:129) Enable bit that allows program execution to Individual interrupt flag bits are set, regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set (cid:129) Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify any of the Interrupt control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is cause erratic microcontroller behavior. enabled, there are two bits which enable interrupts glo- bally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set. Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits. © 2006 Microchip Technology Inc. DS39564C-page 73

PIC18FXX2 FIGURE 8-1: INTERRUPT LOGIC Wake-up if in SLEEP mode TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU INT1IF Vector to location INT1IE Peripheral Interrupt Flag bit INT1IP 0008h Peripheral Interrupt Enable bit INT2IF Peripheral Interrupt Priority bit INT2IE INT2IP GIEH/GIE TMR1IF TMR1IE TMR1IP IPE XXXXIF IPEN XXXXIE GIEL/PEIE XXXXIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF Interrupt to CPU TMR0IE Vector to Location 0018h TMR0IP TMR1IF TMR1IE RBIF TMR1IP RBIE RBIP GIEL/PEIE XXXXIF XXXXIE INT1IF GIE/GIEH XXXXIP INT1IE INT1IP Additional Peripheral Interrupts INT2IF INT2IE INT2IP DS39564C-page 74 © 2006 Microchip Technology Inc.

PIC18FXX2 8.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The INTCON Registers are readable and writable reg- its corresponding enable bit or the global isters, which contain various enable, priority and flag enable bit. User software should ensure bits. the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 8-1: INTCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 75

PIC18FXX2 REGISTER 8-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 =All PORTB pull-ups are disabled 0 =PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0:External Interrupt0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt1 Edge Select bit 1 =Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as '0' bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as '0' bit 0 RBIP: RB Port Change Interrupt Priority bit 1 =High priority 0 =Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39564C-page 76 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 8-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 =High priority 0 =Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 =High priority 0 =Low priority bit 5 Unimplemented: Read as '0' bit 4 INT2IE: INT2 External Interrupt Enable bit 1 =Enables the INT2 external interrupt 0 =Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 =Enables the INT1 external interrupt 0 =Disables the INT1 external interrupt bit 2 Unimplemented: Read as '0' bit 1 INT2IF: INT2 External Interrupt Flag bit 1 =The INT2 external interrupt occurred (must be cleared in software) 0 =The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 =The INT1 external interrupt occurred (must be cleared in software) 0 =The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2006 Microchip Technology Inc. DS39564C-page 77

PIC18FXX2 8.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the global peripheral interrupts. Due to the number of peripheral enable bit, GIE (INTCON<7>). interrupt sources, there are two Peripheral Interrupt Flag Registers (PIR1, PIR2). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 =The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 =The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit (see Section16.0 for details on TXIF functionality) 1 =The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 =The USART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 =The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 =No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 =No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 =TMR1 register overflowed (must be cleared in software) 0 = MR1 register did not overflow Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 78 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit 1 =The Write operation is complete (must be cleared in software) 0 =The Write operation is not complete, or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 =A bus collision occurred (must be cleared in software) 0 =No bus collision occurred bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit 1 =A low voltage condition occurred (must be cleared in software) 0 =The device voltage is above the Low Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 =TMR3 register overflowed (must be cleared in software) 0 =TMR3 register did not overflow bit 0 CCP2IF: CCPx Interrupt Flag bit Capture mode: 1 =A TMR1 register capture occurred (must be cleared in software) 0 =No TMR1 register capture occurred Compare mode: 1 =A TMR1 register compare match occurred (must be cleared in software) 0 =No TMR1 register compare match occurred PWM mode: Unused in this mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 79

PIC18FXX2 8.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Inter- rupt Enable Registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 8-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 80 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 8-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 81

PIC18FXX2 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Inter- rupt Priority Registers (IPR1, IPR2). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 8-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP(1): Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit set. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 82 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 8-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 EEIP: Data EEPROM/FLASH Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 83

PIC18FXX2 8.5 RCON Register The RCON register contains the bit which is used to enable prioritized interrupts (IPEN). REGISTER 8-10: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as '0' bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-3 bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register4-3 bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register4-3 bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register4-3 bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 84 © 2006 Microchip Technology Inc.

PIC18FXX2 8.6 INT0 Interrupt 8.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and In 8-bit mode (which is the default), an overflow RB2/INT2 pins are edge triggered: either rising, if the (FFh → 00h) in the TMR0 register will set flag bit corresponding INTEDGx bit is set in the INTCON2 reg- TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h) ister, or falling, if the INTEDGx bit is clear. When a valid in the TMR0H:TMR0L registers will set flag bit TMR0IF. edge appears on the RBx/INTx pin, the corresponding The interrupt can be enabled/disabled by setting/ flag bit INTxF is set. This interrupt can be disabled by clearing enable bit T0IE (INTCON<5>). Interrupt prior- clearing the corresponding enable bit INTxE. Flag bit ity for Timer0 is determined by the value contained in INTxF must be cleared in software in the Interrupt Ser- the interrupt priority bit TMR0IP (INTCON2<2>). See vice Routine before re-enabling the interrupt. All exter- Section10.0 for further details on the Timer0 module. nal interrupts (INT0, INT1 and INT2) can wake-up the processor from SLEEP, if bit INTxE was set prior to 8.8 PORTB Interrupt-on-Change going into SLEEP. If the global interrupt enable bit GIE An input change on PORTB<7:4> sets flag bit RBIF is set, the processor will branch to the interrupt vector (INTCON<0>). The interrupt can be enabled/disabled following wake-up. by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for INT1 and INT2 is determined by the Interrupt priority for PORTB interrupt-on-change is value contained in the interrupt priority bits, INT1IP determined by the value contained in the interrupt (INTCON3<6>) and INT2IP (INTCON3<7>). There is priority bit, RBIP (INTCON2<0>). no priority bit associated with INT0. It is always a high priority interrupt source. 8.9 Context Saving During Interrupts During an interrupt, the return PC value is saved on the stack. Additionally, the WREG, STATUS and BSR regis- ters are saved on the fast return stack. If a fast return from interrupt is not used (See Section4.3), the user may need to save the WREG, STATUS and BSR regis- ters in software. Depending on the user’s application, other registers may also need to be saved. Equation8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS,STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP,STATUS ; Restore STATUS © 2006 Microchip Technology Inc. DS39564C-page 85

PIC18FXX2 NOTES: DS39564C-page 86 © 2006 Microchip Technology Inc.

PIC18FXX2 9.0 I/O PORTS EXAMPLE 9-1: INITIALIZING PORTA CLRF PORTA ; Initialize PORTA by Depending on the device selected, there are either five ; clearing output ports or three ports available. Some pins of the I/O ; data latches ports are multiplexed with an alternate function from CLRF LATA ; Alternate method the peripheral features on the device. In general, when ; to clear output a peripheral is enabled, that pin may not be used as a ; data latches general purpose I/O pin. MOVLW 0x07 ; Configure A/D MOVWF ADCON1 ; for digital inputs Each port has three registers for its operation. These MOVLW 0xCF ; Value used to registers are: ; initialize data (cid:129) TRIS register (data direction register) ; direction MOVWF TRISA ; Set RA<3:0> as inputs (cid:129) PORT register (reads the levels on the pins of the ; RA<5:4> as outputs device) (cid:129) LAT register (output latch) The data latch (LAT register) is useful for read-modify- write operations on the value that the I/O pins are FIGURE 9-1: BLOCK DIAGRAM OF driving. RA3:RA0 AND RA5 PINS 9.1 PORTA, TRISA and LATA Registers RD LATA PORTA is a 7-bit wide, bi-directional port. The corre- Data sponding Data Direction register is TRISA. Setting a Bus D Q TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a VDD WR LATA Hi-Impedance mode). Clearing a TRISA bit (= 0) will or CK Q P make the corresponding PORTA pin an output (i.e., put PORTA Data Latch the contents of the output latch on the selected pin). D Q N I/O pin(1) Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. WR TRISA CK Q VSS The Data Latch register (LATA) is also memory Analog mapped. Read-modify-write operations on the LATA TRIS Latch Input Mode register reads and writes the latched output value for PORTA. RD TRISA TTL The RA4 pin is multiplexed with the Timer0 module Input clock input to become the RA4/T0CKI pin. The RA4/ Buffer Q D T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. EN The other PORTA pins are multiplexed with analog RD PORTA inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the SS Input (RA5 only) control bits in the ADCON1 register (A/D Control Register1). To A/D Converter and LVD Modules Note: On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read Note1: I/O pins have protection diodes to VDD and VSS. as ‘0’. RA6 and RA4 are configured as digital inputs. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. © 2006 Microchip Technology Inc. DS39564C-page 87

PIC18FXX2 FIGURE 9-2: BLOCK DIAGRAM OF FIGURE 9-3: BLOCK DIAGRAM OF RA4/T0CKI PIN RA6 PIN ECRA6 or RCRA6 Enable Data RD LATA Bus Data RD LATA Bus D Q WR LATA D Q or CK Q I/O pin(1) VDD PORTA N Data Latch CK Q P WR LATA D Q VSS or Data Latch PORTA WR TRISA CK Q Schmitt D Q N I/O pin(1) Trigger TRIS Latch Input Buffer CK Q VSS WR TRISA TRIS Latch RD TRISA TTL Q D Input RD TRISA Buffer ENEN ECRA6 or RD PORTA RCRA6 Enable Q D EN TMR0 Clock Input RD PORTA Note1: I/O pin has protection diode to VSS only. Note1: I/O pins have protection diodes to VDD and VSS. DS39564C-page 88 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 9-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2/VREF- bit2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit3 TTL Input/output or analog input or VREF+. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/SS/AN4/LVDIN bit5 TTL Input/output or slave select input for synchronous serial port or analog input, or low voltage detect input. OSC2/CLKO/RA6 bit6 TTL OSC2 or clock output or I/O pin. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, All Other BOR RESETS PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000 LATA — LATA Data Output Register -xxx xxxx -uuu uuuu TRISA — PORTA Data Direction Register -111 1111 -111 1111 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. © 2006 Microchip Technology Inc. DS39564C-page 89

PIC18FXX2 9.2 PORTB, TRISB and LATB The interrupt-on-change feature is recommended for Registers wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change PORTB is an 8-bit wide, bi-directional port. The corre- feature. Polling of PORTB is not recommended while sponding Data Direction register is TRISB. Setting a using the interrupt-on-change feature. TRISB bit (= 1) will make the corresponding PORTB pin RB3 can be configured by the configuration bit an input (i.e., put the corresponding output driver in a CCP2MX as the alternate peripheral pin for the CCP2 Hi-Impedance mode). Clearing a TRISB bit (= 0) will module (CCP2MX=’0’). make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). FIGURE 9-4: BLOCK DIAGRAM OF The Data Latch register (LATB) is also memory RB7:RB4 PINS mapped. Read-modify-write operations on the LATB VDD register reads and writes the latched output value for RBPU(2) PORTB. P WPuella-ukp Data Latch Data Bus EXAMPLE 9-2: INITIALIZING PORTB D Q CLRF PORTB ; Initialize PORTB by WR LATB I/O pin(1) ; clearing output or CK PORTB ; data latches TRIS Latch CLRF LATB ; Alternate method D Q ; to clear output WR TRISB TTL ; data latches CK Input MOVLW 0xCF ; Value used to Buffer ST ; initialize data Buffer ; direction MOVWF TRISB ; Set RB<3:0> as inputs RD TRISB ; RB<5:4> as outputs ; RB<7:6> as inputs RD LATB Latch Q D Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is per- RD PORTB EN Q1 formed by clearing bit RBPU (INTCON2<7>). The Set RBIF weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are Q D disabled on a Power-on Reset. RD PORTB From other EN Note: On a Power-on Reset, these pins are RB7:RB4 pins Q3 configured as digital inputs. RB7:RB5 in Serial Programming mode Four of the PORTB pins, RB7:RB4, have an interrupt- Note1: I/O pins have diode protection to VDD and VSS. on-change feature. Only pins configured as inputs can 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt- on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last Note 1: While in Low Voltage ICSP mode, the read of PORTB. The “mismatch” outputs of RB7:RB4 RB5 pin can no longer be used as a gen- are OR’ed together to generate the RB Port Change eral purpose I/O pin, and should be held Interrupt with flag bit, RBIF (INTCON<0>). low during normal operation to protect This interrupt can wake the device from SLEEP. The against inadvertent ICSP mode entry. user, in the Interrupt Service Routine, can clear the 2: When using Low Voltage ICSP program- interrupt in the following manner: ming (LVP), the pull-up on RB5 becomes a) Any read or write of PORTB (except with the disabled. If TRISB bit 5 is cleared, MOVFF instruction). This will end the mismatch thereby setting RB5 as an output, LATB condition. bit 5 must also be cleared for proper operation. b) Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. DS39564C-page 90 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 9-5: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D Q I/O pin(1) WR Port CK TRIS Latch D Q TTL Input WR TRIS CK Buffer RD TRIS Q D RD Port EN RB0/INT Schmitt Trigger RD Port Buffer Note1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). FIGURE 9-6: BLOCK DIAGRAM OF RB3 PIN VDD RBPU(2) P Weak CCP2MX Pull-up CCP Output(3) 1 VDD P Enable(3) 0 CCP Output Data Latch Data Bus D Q I/O pin(1) WR LATB or WR PORTB N CK TRIS Latch VSS D TTL WR TRISB CK Q IBnupfufetr RD TRISB RD LATB Q D RD PORTB EN RD PORTB CCP2 Input(3) Schmitt Trigger Buffer CCP2MX = 0 Note1: I/O pin has diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>). 3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register. © 2006 Microchip Technology Inc. DS39564C-page 91

PIC18FXX2 TABLE 9-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT0 bit0 TTL/ST(1) Input/output pin or external interrupt input0. Internal software programmable weak pull-up. RB1/INT1 bit1 TTL/ST(1) Input/output pin or external interrupt input1. Internal software programmable weak pull-up. RB2/INT2 bit2 TTL/ST(1) Input/output pin or external interrupt input2. Internal software programmable weak pull-up. RB3/CCP2(3) bit3 TTL/ST(4) Input/output pin or Capture2 input/Compare2 output/PWM output when CCP2MX configuration bit is enabled. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5/PGM(5) bit5 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low voltage ICSP enable pin. RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on. 4: This buffer is a Schmitt Trigger input when configured as the CCP2 input. 5: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB5 I/O function. LVP must be disabled to enable RB5 as an I/O pin and allow maximum compatibility to the other 28-pin and 40-pin mid-range devices. TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu LATB LATB Data Output Register xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 1111 -1-1 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 11-0 0-00 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS39564C-page 92 © 2006 Microchip Technology Inc.

PIC18FXX2 9.3 PORTC, TRISC and LATC The pin override value is not loaded into the TRIS reg- Registers ister. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. PORTC is an 8-bit wide, bi-directional port. The corre- RC1 is normally configured by configuration bit, sponding Data Direction register is TRISC. Setting a CCP2MX, as the default peripheral pin of the CCP2 TRISC bit (= 1) will make the corresponding PORTC module (default/erased state, CCP2MX = ’1’). pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will EXAMPLE 9-3: INITIALIZING PORTC make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by ; clearing output The Data Latch register (LATC) is also memory ; data latches mapped. Read-modify-write operations on the LATC CLRF LATC ; Alternate method register reads and writes the latched output value for ; to clear output PORTC. ; data latches MOVLW 0xCF ; Value used to PORTC is multiplexed with several peripheral functions ; initialize data (Table9-5). PORTC pins have Schmitt Trigger input ; direction buffers. MOVWF TRISC ; Set RC<3:0> as inputs When enabling peripheral functions, care should be ; RC<5:4> as outputs taken in defining TRIS bits for each PORTC pin. Some ; RC<7:6> as inputs peripherals override the TRIS bit to make a pin an out- put, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corre- sponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs. FIGURE 9-7: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) Port/Peripheral Select(2) VDD Peripheral Data Out RD LATC 0 Data Latch Data Bus D Q P WR LATC or WR PORTC CK Q 1 I/O pin(1) TRIS Latch D Q WR TRISC CK Q N RD TRISC Schmitt VSS Trigger Peripheral Output Enable(3) Q D EN RD PORTC Peripheral Data In Note1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral Select signal selects between port data (input) and peripheral output. 3: Peripheral Output Enable is only active if peripheral select is active. © 2006 Microchip Technology Inc. DS39564C-page 93

PIC18FXX2 TABLE 9-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin, Timer1 oscillator input, or Capture2 input/ Compare2 output/PWM output when CCP2MX configuration bit is set. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output. RC6/TX/CK bit6 ST Input/output port pin, Addressable USART Asynchronous Transmit, or Addressable USART Synchronous Clock. RC7/RX/DT bit7 ST Input/output port pin, Addressable USART Asynchronous Receive, or Addressable USART Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 9-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu LATC LATC Data Output Register xxxx xxxx uuuu uuuu TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged DS39564C-page 94 © 2006 Microchip Technology Inc.

PIC18FXX2 9.4 PORTD, TRISD and LATD FIGURE 9-8: PORTD BLOCK DIAGRAM Registers IN I/O PORT MODE This section is applicable only to the PIC18F4X2 devices. PORTD is an 8-bit wide, bi-directional port. The corre- RD LATD Data sponding Data Direction register is TRISD. Setting a Bus D Q TRISD bit (= 1) will make the corresponding PORTD I/O pin(1) pin an input (i.e., put the corresponding output driver in WR LATD CK a Hi-Impedance mode). Clearing a TRISD bit (= 0) will or PORTD Data Latch make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). D Q The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD WR TRISD CK Schmitt Trigger register reads and writes the latched output value for TRIS Latch Input PORTD. Buffer PORTD is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configurable as an input or RD TRISD output. Q D Note: On a Power-on Reset, these pins are configured as digital inputs. ENEN PORTD can be configured as an 8-bit wide micropro- RD PORTD cessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section9.6 for additional information on Note1: I/O pins have diode protection to VDD and VSS. the Parallel Slave Port (PSP). EXAMPLE 9-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2006 Microchip Technology Inc. DS39564C-page 95

PIC18FXX2 TABLE 9-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0. RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1. RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2. RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3. RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4. RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5. RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6. RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode. TABLE 9-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu LATD LATD Data Output Register xxxx xxxx uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD. DS39564C-page 96 © 2006 Microchip Technology Inc.

PIC18FXX2 9.5 PORTE, TRISE and LATE FIGURE 9-9: PORTE BLOCK DIAGRAM Registers IN I/O PORT MODE This section is only applicable to the PIC18F4X2 devices. PORTE is a 3-bit wide, bi-directional port. The corre- RD LATE sponding Data Direction register is TRISE. Setting a Data Bus TRISE bit (= 1) will make the corresponding PORTE pin D Q an input (i.e., put the corresponding output driver in a I/O pin(1) WR LATE Hi-Impedance mode). Clearing a TRISE bit (= 0) will or CK make the corresponding PORTE pin an output (i.e., put PORTE Data Latch the contents of the output latch on the selected pin). D Q The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE WR TRISE CK Schmitt register reads and writes the latched output value for Trigger PORTE. TRIS Latch Input Buffer PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7) which are individually configurable RD TRISE as inputs or outputs. These pins have Schmitt Trigger input buffers. Q D Register9-1 shows the TRISE register, which also controls the parallel slave port operation. ENEN PORTE pins are multiplexed with analog inputs. When RD PORTE selected as an analog input, these pins will read as '0's. TRISE controls the direction of the RE pins, even when To Analog Converter they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when Note1: I/O pins have diode protection to VDD and VSS. using them as analog inputs. Note: On a Power-on Reset, these pins are configured as analog inputs. EXAMPLE 9-5: INITIALIZING PORTE CLRF PORTE ; Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 0x07 ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 0x05 ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs © 2006 Microchip Technology Inc. DS39564C-page 97

PIC18FXX2 REGISTER 9-1: TRISE REGISTER R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 =A write occurred when a previously input word has not been read (must be cleared in software) 0 =No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode bit 3 Unimplemented: Read as '0' bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 98 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 9-9: PORTE FUNCTIONS Name Bit# Buffer Type Function Input/output port pin or read control input in Parallel Slave Port mode or analog input: RE0/RD/AN5 bit0 ST/TTL(1) RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected). Input/output port pin or write control input in Parallel Slave Port mode or analog input: RE1/WR/AN6 bit1 ST/TTL(1) WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected). Input/output port pin or chip select control input in Parallel Slave Port mode or analog input: RE2/CS/AN7 bit2 ST/TTL(1) CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode. TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS PORTE — — — — — RE2 RE1 RE0 ---- -000 ---- -000 LATE — — — — — LATE Data Output Register ---- -xxx ---- -uuu TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE. © 2006 Microchip Technology Inc. DS39564C-page 99

PIC18FXX2 9.6 Parallel Slave Port FIGURE 9-10: PORTD AND PORTE BLOCK DIAGRAM The Parallel Slave Port is implemented on the 40-pin (PARALLEL SLAVE devices only (PIC18F4X2). PORT) PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit, PSPMODE (TRISE<4>) is set. It is asynchronously readable and Data Bus D Q writable by the external world through RD control input RDx pin, RE0/RD and WR control input pin, RE1/WR. WR LATD CK Pin or It can directly interface to an 8-bit microprocessor data PORTD Data Latch TTL bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE Q D enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip RD PORTD ENEN select) input. For this functionality, the corresponding TRIS Latch data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port config- uration bits PCFG2:PCFG0 (ADCON1<2:0>) must be RD LATD set, which will configure pins RE2:RE0 as digital I/O. A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs One bit of PORTD when both the CS and RD lines are first detected low. Set Interrupt Flag The PORTE I/O pins become control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) PSPIF (PIR1<7>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs), and the ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Read TTL RD Chip Select TTL CS Write TTL WR Note: I/O pin has protection diodes to VDD and VSS. FIGURE 9-11: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF DS39564C-page 100 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 9-12: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 9-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 PORTE — — — — — RE2 RE1 RE0 ---- -000 ---- -000 LATE — — — — — LATE Data Output bits ---- -xxx ---- -uuu TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 INTCON GIE/ PEIE/ TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. © 2006 Microchip Technology Inc. DS39564C-page 101

PIC18FXX2 NOTES: DS39564C-page 102 © 2006 Microchip Technology Inc.

PIC18FXX2 10.0 TIMER0 MODULE Figure10-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure10-2 shows a The Timer0 module has the following features: simplified block diagram of the Timer0 module in 16-bit (cid:129) Software selectable as an 8-bit or 16-bit timer/ mode. counter The T0CON register (Register10-1) is a readable and (cid:129) Readable and writable writable register that controls all the aspects of Timer0, (cid:129) Dedicated 8-bit software programmable prescaler including the prescale selection. (cid:129) Clock source selectable to be external or internal (cid:129) Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode (cid:129) Edge select for external clock REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 103

PIC18FXX2 FIGURE 10-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 1 Sync with 1 Internal TMR0L Clocks RA4/T0CKI pin Programmable 0 Prescaler T0SE (2 TCY delay) 3 PSA Set Interrupt T0PS2, T0PS1, T0PS0 Flag bit TMR0IF T0CS on Overflow Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 10-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE FOSC/4 0 1 Sync with Set Interrupt 1 ICntleocrnkasl TMR0L HTigMh RB0yte Flag bit TMR0IF T0CKI pin Programmable 0 on Overflow Prescaler 8 T0SE (2 TCY delay) 3 Read TMR0L T0PS2, T0PS1, T0PS0 T0CS PSA Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39564C-page 104 © 2006 Microchip Technology Inc.

PIC18FXX2 10.1 Timer0 Operation 10.2.1 SWITCHING PRESCALER ASSIGNMENT Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software con- trol, (i.e., it can be changed “on-the-fly” during program Timer mode is selected by clearing the T0CS bit. In execution). Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0L reg- 10.3 Timer0 Interrupt ister is written, the increment is inhibited for the follow- ing two instruction cycles. The user can work around The TMR0 interrupt is generated when the TMR0 reg- this by writing an adjusted value to the TMR0L register. ister overflows from FFh to 00h in 8-bit mode, or FFFFh Counter mode is selected by setting the T0CS bit. In to 0000h in 16-bit mode. This overflow sets the TMR0IF Counter mode, Timer0 will increment, either on every bit. The interrupt can be masked by clearing the rising or falling edge of pin RA4/T0CKI. The increment- TMR0IE bit. The TMR0IE bit must be cleared in soft- ing edge is determined by the Timer0 Source Edge ware by the Timer0 module Interrupt Service Routine Select bit (T0SE). Clearing the T0SE bit selects the ris- before re-enabling this interrupt. The TMR0 interrupt ing edge. Restrictions on the external clock input are cannot awaken the processor from SLEEP, since the discussed below. timer is shut-off during SLEEP. When an external clock input is used for Timer0, it must 10.4 16-Bit Mode Timer Reads and meet certain requirements. The requirements ensure Writes the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual TMR0H is not the high byte of the timer/counter in incrementing of Timer0 after synchronization. 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure10-2). The high byte 10.2 Prescaler of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the An 8-bit counter is available as a prescaler for the Timer0 high byte of Timer0 during a read of TMR0L. This pro- module. The prescaler is not readable or writable. vides the ability to read all 16-bits of Timer0 without The PSA and T0PS2:T0PS0 bits determine the having to verify that the read of the high and low byte prescaler assignment and prescale ratio. were valid due to a rollover between successive reads Clearing bit PSA will assign the prescaler to the Timer0 of the high and low byte. module. When the prescaler is assigned to the Timer0 A write to the high byte of Timer0 must also take place module, prescale values of 1:2, 1:4,..., 1:256 are through the TMR0H buffer register. Timer0 high byte is selectable. updated with the contents of TMR0H when a write When assigned to the Timer0 module, all instructions occurs to TMR0L. This allows all 16-bits of Timer0 to be writing to the TMR0L register (e.g., CLRF TMR0, updated at once. MOVWF TMR0, BSF TMR0, x....etc.) will clear the prescaler count. Note: Writing to TMR0L when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 TRISA — PORTA Data Direction Register -111 1111 -111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. © 2006 Microchip Technology Inc. DS39564C-page 105

PIC18FXX2 NOTES: DS39564C-page 106 © 2006 Microchip Technology Inc.

PIC18FXX2 11.0 TIMER1 MODULE Figure11-1 is a simplified block diagram of the Timer1 module. The Timer1 module timer/counter has the following Register11-1 details the Timer1 control register. This features: register controls the Operating mode of the Timer1 (cid:129) 16-bit timer/counter module, and contains the Timer1 oscillator enable bit (two 8-bit registers; TMR1H and TMR1L) (T1OSCEN). Timer1 can be enabled or disabled by (cid:129) Readable and writable (both registers) setting or clearing control bit TMR1ON (T1CON<0>). (cid:129) Internal or external clock select (cid:129) Interrupt-on-overflow from FFFFh to 0000h (cid:129) RESET from CCP module special event trigger REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register Read/Write of Timer1 in one 16-bit operation 0 = Enables register Read/Write of Timer1 in two 8-bit operations bit 6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 Oscillator is enabled 0 = Timer1 Oscillator is shut-off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 107

PIC18FXX2 11.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruc- tion cycle. When TMR1CS = 1, Timer1 increments on Timer1 can operate in one of these modes: every rising edge of the external clock input or the (cid:129) As a timer Timer1 oscillator, if enabled. (cid:129) As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is (cid:129) As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is The Operating mode is determined by the clock select ignored, and the pins are read as ‘0’. bit, TMR1CS (T1CON<1>). Timer1 also has an internal “RESET input”. This RESET can be generated by the CCP module (Section14.0). FIGURE 11-1: TIMER1 BLOCK DIAGRAM CCP Special Event Trigger TMR1IF Overflow Interrupt TMR1 0 Synchronized Flag Bit CLR Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC T1CKI/T1OSO 1 T1OSCEN Prescaler Synchronize T1OSI EOnsaciblllaetor(1) IFnOteSrCn/a4l 0 1, 2, 4, 8 det Clock 2 SLEEP Input T1CKPS1:T1CKPS0 TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 11-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 8 Write TMR1L CCP Special Event Trigger Read TMR1L TOInMvteeRrrrf1uloIpFwt 8 Timer 1 TMR1 CLR 0 SyCnlocchkro Innipzuetd Flag bit High Byte TMR1L 1 TMR1ON on/off T1SYNC T1OSC T13CKI/T1OSO 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR1CS SLEEP Input T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39564C-page 108 © 2006 Microchip Technology Inc.

PIC18FXX2 11.2 Timer1 Oscillator 11.4 Resetting Timer1 using a CCP Trigger Output A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by If the CCP module is configured in Compare mode to setting control bit T1OSCEN (T1CON<3>). The oscilla- generate a “special event trigger” (CCP1M3:CCP1M0 tor is a low power oscillator rated up to 200 kHz. It will = 1011), this signal will reset Timer1 and start an A/D continue to run during SLEEP. It is primarily intended conversion (if the A/D module is enabled). for a 32 kHz crystal. Table11-1 shows the capacitor selection for the Timer1 oscillator. Note: The special event triggers from the CCP1 module will not set interrupt flag bit The user must provide a software time delay to ensure TMR1IF (PIR1<0>). proper start-up of the Timer1 oscillator. Timer1 must be configured for either Timer or Synchro- TABLE 11-1: CAPACITOR SELECTION FOR nized Counter mode to take advantage of this feature. THE ALTERNATE If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. OSCILLATOR In the event that a write to Timer1 coincides with a Osc Type Freq C1 C2 special event trigger from CCP1, the write will take precedence. LP 32 kHz TBD(1) TBD(1) In this mode of operation, the CCPR1H:CCPR1L regis- Crystal to be Tested: ters pair effectively becomes the period register for 32.768 kHz Epson C-001R32.768K-A ± 20 PPM Timer1. 11.5 Timer1 16-Bit Read/Write Mode Note 1: Microchip suggests 33 pF as a starting point in validating the oscillator circuit. Timer1 can be configured for 16-bit reads and writes (see Figure11-2). When the RD16 control bit 2: Higher capacitance increases the stability (T1CON<7>) is set, the address for TMR1H is mapped of the oscillator, but also increases the to a buffer register for the high byte of Timer1. A read start-up time. from TMR1L will load the contents of the high byte of 3: Since each resonator/crystal has its own Timer1 into the Timer1 high byte buffer. This provides characteristics, the user should consult the user with the ability to accurately read all 16-bits of the resonator/crystal manufacturer Timer1 without having to determine whether a read of for appropriate values of external the high byte followed by a read of the low byte is valid, components. due to a rollover between reads. 4: Capacitor values are for design guidance A write to the high byte of Timer1 must also take place only. through the TMR1H buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits 11.3 Timer1 Interrupt to both the high and low bytes of Timer1 at once. The TMR1 Register pair (TMR1H:TMR1L) increments The high byte of Timer1 is not directly readable or writ- from 0000h to FFFFh and rolls over to 0000h. The able in this mode. All reads and writes must take place TMR1 Interrupt, if enabled, is generated on overflow, through the Timer1 high byte buffer register. Writes to which is latched in interrupt flag bit TMR1IF (PIR1<0>). TMR1H do not clear the Timer1 prescaler. The This interrupt can be enabled/disabled by setting/ prescaler is only cleared on writes to TMR1L. clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). © 2006 Microchip Technology Inc. DS39564C-page 109

PIC18FXX2 TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. DS39564C-page 110 © 2006 Microchip Technology Inc.

PIC18FXX2 12.0 TIMER2 MODULE 12.1 Timer2 Operation The Timer2 module timer has the following features: Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is (cid:129) 8-bit timer (TMR2 register) readable and writable, and is cleared on any device (cid:129) 8-bit period register (PR2) RESET. The input clock (FOSC/4) has a prescale option (cid:129) Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits (cid:129) Software programmable prescaler (1:1, 1:4, 1:16) T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out- (cid:129) Software programmable postscaler (1:1 to 1:16) put of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a (cid:129) Interrupt on TMR2 match of PR2 TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). (cid:129) SSP module optional use of TMR2 output to generate clock shift The prescaler and postscaler counters are cleared when any of the following occurs: Timer2 has a control register shown in Register12-1. Timer2 can be shut-off by clearing control bit TMR2ON (cid:129) a write to the TMR2 register (T2CON<2>) to minimize power consumption. (cid:129) a write to the T2CON register Figure12-1 is a simplified block diagram of the Timer2 (cid:129) any device RESET (Power-on Reset, MCLR module. Register12-1 shows the Timer2 control regis- Reset, Watchdog Timer Reset, or Brown-out ter. The prescaler and postscaler selection of Timer2 Reset) are controlled by this register. TMR2 is not cleared when T2CON is written. REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale (cid:129) (cid:129) (cid:129) 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 111

PIC18FXX2 12.2 Timer2 Interrupt 12.3 Output of TMR2 The Timer2 module has an 8-bit period register, PR2. The output of TMR2 (before the postscaler) is fed to the Timer2 increments from 00h until it matches PR2 and Synchronous Serial Port module, which optionally uses then resets to 00h on the next increment cycle. PR2 is it to generate the shift clock. a readable and writable register. The PR2 register is initialized to FFh upon RESET. FIGURE 12-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 Output(1) bit TMR2IF Prescaler RESET FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS1:T2CKPS0 PR2 4 TOUTPS3:TOUTPS0 Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TMR2 Timer2 Module Register 0000 0000 0000 0000 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. DS39564C-page 112 © 2006 Microchip Technology Inc.

PIC18FXX2 13.0 TIMER3 MODULE Figure13-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following Register13-1 shows the Timer3 control register. This features: register controls the Operating mode of the Timer3 (cid:129) 16-bit timer/counter module and sets the CCP clock source. (two 8-bit registers; TMR3H and TMR3L) Register11-1 shows the Timer1 control register. This (cid:129) Readable and writable (both registers) register controls the Operating mode of the Timer1 (cid:129) Internal or external clock select module, as well as contains the Timer1 oscillator (cid:129) Interrupt-on-overflow from FFFFh to 0000h enable bit (T1OSCEN), which can be a clock source for (cid:129) RESET from CCP module trigger Timer3. REGISTER 13-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register Read/Write of Timer3 in one 16-bit operation 0 = Enables register Read/Write of Timer3 in two 8-bit operations bit 6-3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x =Timer3 is the clock source for compare/capture CCP modules 01 =Timer3 is the clock source for compare/capture of CCP2, Timer1 is the clock source for compare/capture of CCP1 00 =Timer1 is the clock source for compare/capture CCP modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 113

PIC18FXX2 13.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruc- tion cycle. When TMR3CS = 1, Timer3 increments on Timer3 can operate in one of these modes: every rising edge of the Timer1 external clock input or (cid:129) As a timer the Timer1 oscillator, if enabled. (cid:129) As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is (cid:129) As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is The Operating mode is determined by the clock select ignored, and the pins are read as ‘0’. bit, TMR3CS (T3CON<1>). Timer3 also has an internal “RESET input”. This RESET can be generated by the CCP module (Section14.0). FIGURE 13-1: TIMER3 BLOCK DIAGRAM CCP Special Trigger TMR3IF T3CCPx Overflow Interrupt Synchronized 0 Flag bit CLR Clock Input TMR3H TMR3L 1 TMR3ON On/Off T3SYNC T1OSO/ T1OSC (3) 1 T13CKI Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR3CS SLEEP Input T3CKPS1:T3CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 13-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 8 Write TMR3L Read TMR3L CCP Special Trigger Set TMR3IF Flag bit 8 TMR3 T3CCPx 0 Synchronized on Overflow Timer3 CLR Clock Input High Byte TMR3L 1 To Timer1 Clock Input TMR3ON On/Off T3SYNC T1OSC T1OSO/ 1 T13CKI Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 SLEEP Input T3CKPS1:T3CKPS0 TMR3CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39564C-page 114 © 2006 Microchip Technology Inc.

PIC18FXX2 13.2 Timer1 Oscillator 13.4 Resetting Timer3 Using a CCP Trigger Output The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting If the CCP module is configured in Compare mode to the T1OSCEN (T1CON<3>) bit. The oscillator is a low generate a “special event trigger” (CCP1M3:CCP1M0 power oscillator rated up to 200 KHz. See Section11.0 = 1011), this signal will reset Timer3. for further details. Note: The special event triggers from the CCP 13.3 Timer3 Interrupt module will not set interrupt flag bit, TMR3IF (PIR1<0>). The TMR3 Register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer3 must be configured for either Timer or Synchro- TMR3 Interrupt, if enabled, is generated on overflow, nized Counter mode to take advantage of this feature. which is latched in interrupt flag bit, TMR3IF If Timer3 is running in Asynchronous Counter mode, (PIR2<1>). This interrupt can be enabled/disabled by this RESET operation may not work. In the event that a setting/clearing TMR3 interrupt enable bit, TMR3IE write to Timer3 coincides with a special event trigger (PIE2<1>). from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer3. TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000 PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000 IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. © 2006 Microchip Technology Inc. DS39564C-page 115

PIC18FXX2 NOTES: DS39564C-page 116 © 2006 Microchip Technology Inc.

PIC18FXX2 14.0 CAPTURE/COMPARE/PWM The operation of CCP1 is identical to that of CCP2, with (CCP) MODULES the exception of the special event trigger. Therefore, operation of a CCP module in the following sections is Each CCP (Capture/Compare/PWM) module contains described with respect to CCP1. a 16-bit register which can operate as a 16-bit Capture Table14-2 shows the interaction of the CCP modules. register, as a 16-bit Compare register or as a PWM Master/Slave Duty Cycle register. Table14-1 shows the timer resources of the CCP Module modes. REGISTER 14-1: CCP1CON REGISTER/CCP2CON REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0 Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set) 1001 = Compare mode, Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set) 1010 = Compare mode, Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected) 1011 = Compare mode, Trigger special event (CCPIF bit is set) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 117

PIC18FXX2 14.1 CCP1 Module 14.2 CCP2 Module Capture/Compare/PWM Register 1 (CCPR1) is com- Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR1L (low byte) and prised of two 8-bit registers: CCPR2L (low byte) and CCPR1H (high byte). The CCP1CON register controls CCPR2H (high byte). The CCP2CON register controls the operation of CCP1. All are readable and writable. the operation of CCP2. All are readable and writable. TABLE 14-1: CCP MODE - TIMER RESOURCE CCP Mode Timer Resource Capture Timer1 or Timer3 Compare Timer1 or Timer3 PWM Timer2 TABLE 14-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture TMR1 or TMR3 time-base. Time-base can be different for each CCP. Capture Compare The compare could be configured for the special event trigger, which clears either TMR1 or TMR3 depending upon which time-base is used. Compare Compare The compare(s) could be configured for the special event trigger, which clears TMR1 or TMR3 depending upon which time-base is used. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None PWM Compare None DS39564C-page 118 © 2006 Microchip Technology Inc.

PIC18FXX2 14.3 Capture Mode 14.3.3 SOFTWARE INTERRUPT In Capture mode, CCPR1H:CCPR1L captures the When the Capture mode is changed, a false capture 16-bit value of the TMR1 or TMR3 registers when an interrupt may be generated. The user should keep bit event occurs on pin RC2/CCP1. An event is defined as CCP1IE (PIE1<2>) clear to avoid false interrupts and one of the following: should clear the flag bit, CCP1IF, following any such change in Operating mode. (cid:129) every falling edge (cid:129) every rising edge 14.3.4 CCP PRESCALER (cid:129) every 4th rising edge There are four prescaler settings, specified by bits (cid:129) every 16th rising edge CCP1M3:CCP1M0. Whenever the CCP module is The event is selected by control bits CCP1M3:CCP1M0 turned off or the CCP module is not in Capture mode, (CCP1CON<3:0>). When a capture is made, the inter- the prescaler counter is cleared. This means that any rupt request flag bit CCP1IF (PIR1<2>) is set; it must be RESET will clear the prescaler counter. cleared in software. If another capture occurs before the Switching from one capture prescaler to another may value in register CCPR1 is read, the old captured value generate an interrupt. Also, the prescaler counter will is overwritten by the new captured value. not be cleared, therefore, the first capture may be from a non-zero prescaler. Example14-1 shows the recom- 14.3.1 CCP PIN CONFIGURATION mended method for switching between capture pres- In Capture mode, the RC2/CCP1 pin should be calers. This example also clears the prescaler counter configured as an input by setting the TRISC<2> bit. and will not generate the “false” interrupt. Note: If the RC2/CCP1 is configured as an out- EXAMPLE 14-1: CHANGING BETWEEN put, a write to the port can cause a capture CAPTURE PRESCALERS condition. CLRF CCP1CON, F ; Turn CCP module off 14.3.2 TIMER1/TIMER3 MODE SELECTION MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode The timers that are to be used with the capture feature ; value and CCP ON (either Timer1 and/or Timer3) must be running in Timer MOVWF CCP1CON ; Load CCP1CON with mode or Synchronized Counter mode. In Asynchro- ; this value nous Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the T3CON register. FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set Flag bit CCP1IF T3CCP2 TMR3 Prescaler ÷ 1, 4, 16 Enable CCP1 pin CCPR1H CCPR1L TMR1 and T3CCP2 Enable Edge Detect TMR1H TMR1L CCP1CON<3:0> Q’s Set Flag bit CCP2IF T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Prescaler ÷ 1, 4, 16 Enable CCP2 pin CCPR2H CCPR2L TMR1 and Enable Edge Detect T3CCP2 T3CCP1 TMR1H TMR1L CCP2CON<3:0> Q’s © 2006 Microchip Technology Inc. DS39564C-page 119

PIC18FXX2 14.4 Compare Mode 14.4.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 (CCPR2) register Timer1 and/or Timer3 must be running in Timer mode value is constantly compared against either the TMR1 or Synchronized Counter mode if the CCP module is register pair value, or the TMR3 register pair value. using the compare feature. In Asynchronous Counter When a match occurs, the RC2/CCP1 (RC1/CCP2) pin mode, the compare operation may not work. is: 14.4.3 SOFTWARE INTERRUPT MODE (cid:129) driven High (cid:129) driven Low When generate software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if (cid:129) toggle output (High to Low or Low to High) enabled). (cid:129) remains unchanged The action on the pin is based on the value of control 14.4.4 SPECIAL EVENT TRIGGER bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the In this mode, an internal hardware trigger is generated, same time, interrupt flag bit CCP1IF (CCP2IF) is set. which may be used to initiate an action. 14.4.1 CCP PIN CONFIGURATION The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to The user must configure the CCPx pin as an output by effectively be a 16-bit programmable period register for clearing the appropriate TRISC bit. Timer1. Note: Clearing the CCP1CON register will force The special trigger output of CCPx resets either the the RC2/CCP1 compare output latch to the TMR1 or TMR3 register pair. Additionally, the CCP2 default low level. This is not the PORTC Special Event Trigger will start an A/D conversion if the I/O data latch. A/D module is enabled. Note: The special event trigger from the CCP2 module will not set the Timer1 or Timer3 interrupt flag bits. FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit, and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP2 only) Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q S Output RC2/CCP1 pin R Logic Match Comparator TRISC<2> Output Enable CCP1CON<3:0> T3CCP2 0 1 Mode Select TMR1H TMR1L TMR3H TMR3L Special Event Trigger Set Flag bit CCP2IF T3CCP1 T3CCP2 0 1 Q S Output Comparator RC1/CCP2 pin R Logic Match TRISC<1> CCPR2H CCPR2L Output Enable CCP2CON<3:0> Mode Select DS39564C-page 120 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 PIR2 — — — EEIE BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000 PIE2 — — — EEIF BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000 IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2x2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. DS39564C-page 121

PIC18FXX2 14.5 PWM Mode 14.5.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP1 pin is multiplexed with the PORTC data latch, following formula: the TRISC<2> bit must be cleared to make the CCP1 PWM period = (PR2) + 1] • 4 (cid:129)TOSC (cid:129) pin an output. (TMR2 prescale value) Note: Clearing the CCP1CON register will force PWM frequency is defined as 1 / [PWM period]. the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events low level. This is not the PORTC I/O data occur on the next increment cycle: latch. (cid:129) TMR2 is cleared Figure14-3 shows a simplified block diagram of the (cid:129) The CCP1 pin is set (exception: if PWM duty CCP module in PWM mode. cycle=0%, the CCP1 pin will not be set) For a step-by-step procedure on how to set up the CCP (cid:129) The PWM duty cycle is latched from CCPR1L into module for PWM operation, see Section14.5.3. CCPR1H Note: The Timer2 postscaler (see Section12.0) FIGURE 14-3: SIMPLIFIED PWM BLOCK is not used in the determination of the DIAGRAM PWM frequency. The postscaler could be used to have a servo update rate at a CCP1CON<5:4> Duty Cycle Registers different frequency than the PWM output. CCPR1L 14.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up CCPR1H (Slave) to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the Comparator R Q two LSbs. This 10-bit value is represented by RC2/CCP1 CCPR1L:CCP1CON<5:4>. The following equation is TMR2 (Note 1) used to calculate the PWM duty cycle in time: S PWM duty cycle = (CCPR1L:CCP1CON<5:4>) (cid:129) Comparator TRISC<2> TOSC (cid:129)(TMR2 prescale value) Clear Timer, CCPR1L and CCP1CON<5:4> can be written to at any CCP1 pin and latch D.C. time, but the duty cycle value is not latched into PR2 CCPR1H until after a match between PR2 and TMR2 Note: 8-bit timer is concatenated with 2-bit internal Q clock or 2 occurs (i.e., the period is complete). In PWM mode, bits of the prescaler to create 10-bit time-base. CCPR1H is a read only register. The CCPR1H register and a 2-bit internal latch are A PWM output (Figure14-4) has a time-base (period) used to double buffer the PWM duty cycle. This double and a time that the output stays high (duty cycle). The buffering is essential for glitchless PWM operation. frequency of the PWM is the inverse of the period When the CCPR1H and 2-bit latch match TMR2 con- (1/period). catenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. FIGURE 14-4: PWM OUTPUT The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: Period log⎛--F---O----S---C---⎞ ⎝FPWM⎠ PWM Resolution (max) = -----------------------------bits log(2) Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be TMR2 = PR2 cleared. DS39564C-page 122 © 2006 Microchip Technology Inc.

PIC18FXX2 14.5.3 SETUP FOR PWM OPERATION 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. The following steps should be taken when configuring 4. Set the TMR2 prescale value and enable Timer2 the CCP module for PWM operation: by writing to T2CON. 1. Set the PWM period by writing to the PR2 register. 5. Configure the CCP1 module for PWM operation. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 14 12 10 8 7 6.58 TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. DS39564C-page 123

PIC18FXX2 NOTES: DS39564C-page 124 © 2006 Microchip Technology Inc.

PIC18FXX2 15.0 MASTER SYNCHRONOUS 15.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8-bits of data to be synchronously MODULE transmitted and received, simultaneously. All four modes of SPI are supported. To accomplish communication, 15.1 Master SSP (MSSP) Module typically three pins are used: Overview (cid:129) Serial Data Out (SDO) - RC5/SDO The Master Synchronous Serial Port (MSSP) module is (cid:129) Serial Data In (SDI) - RC4/SDI/SDA a serial interface useful for communicating with other (cid:129) Serial Clock (SCK) - RC3/SCK/SCL/LVDIN peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave devices may be serial EEPROMs, shift registers, dis- mode of operation: play drivers, A/D converters, etc. The MSSP module (cid:129) Slave Select (SS) - RA5/SS/AN4 can operate in one of two modes: Figure15-1 shows the block diagram of the MSSP (cid:129) Serial Peripheral Interface (SPI) module when operating in SPI mode. (cid:129) Inter-Integrated Circuit (I2C) - Full Master mode FIGURE 15-1: MSSP BLOCK DIAGRAM - Slave mode (with general address call) (SPIMODE) The I2C interface supports the following modes in Internal hardware: Data Bus (cid:129) Master mode Read Write (cid:129) Multi-Master mode (cid:129) Slave mode SSPBUF reg 15.2 Control Registers RC4/SDI/SDA The MSSP module has three associated registers. SSPSR reg These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use RC5/SDO bit0 cslhoicftk of these registers and their individual configuration bits differ significantly, depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual RA5/SS/AN4 SS Control sections. Enable Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE ( ) RC3/SCK/ 4 TMR2 output SCL/LVDIN 2 2 Edge Select Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit © 2006 Microchip Technology Inc. DS39564C-page 125

PIC18FXX2 15.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together (cid:129) MSSP Control Register1 (SSPCON1) create a double buffered receiver. When SSPSR (cid:129) MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF (cid:129) Serial Receive/Transmit Buffer (SSPBUF) and the SSPIF interrupt is set. (cid:129) MSSP Shift Register (SSPSR) - Not directly During transmission, the SSPBUF is not double buff- accessible ered. A write to SSPBUF will write to both SSPBUF and SSPCON1 and SSPSTAT are the control and status SSPSR. registers in SPI mode operation. The SSPCON1 regis- ter is readable and writable. The lower 6 bits of the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/write. REGISTER 15-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode bit 6 CKE: SPI Clock Edge Select When CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK When CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5 D/A: Data/Address bit Used in I2C mode only bit 4 P: STOP bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: START bit Used in I2C mode only bit 2 R/W: Read/Write bit information Used in I2C mode only bit 1 UA: Update Address Used in I2C mode only bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 126 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 15-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 =The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 =No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = IDLE state for clock is a high level 0 = IDLE state for clock is a low level bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved, or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 127

PIC18FXX2 15.3.2 OPERATION SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL When initializing the SPI, several options need to be (SSPCON1<7>), will be set. User software must clear specified. This is done by programming the appropriate the WCOL bit so that it can be determined if the follow- control bits (SSPCON1<5:0>) and SSPSTAT<7:6>. ing write(s) to the SSPBUF register completed These control bits allow the following to be specified: successfully. (cid:129) Master mode (SCK is the clock output) When the application software is expecting to receive (cid:129) Slave mode (SCK is the clock input) valid data, the SSPBUF should be read before the next (cid:129) Clock Polarity (IDLE state of SCK) byte of data to transfer is written to the SSPBUF. Buffer (cid:129) Data input sample phase (middle or end of data full bit, BF (SSPSTAT<0>), indicates when SSPBUF output time) has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is (cid:129) Clock edge (output data on rising/falling edge of cleared. This data may be irrelevant if the SPI is only a SCK) transmitter. Generally, the MSSP Interrupt is used to (cid:129) Clock Rate (Master mode only) determine when the transmission/reception has com- (cid:129) Slave Select mode (Slave mode only) pleted. The SSPBUF must be read and/or written. If the The MSSP consists of a transmit/receive Shift Register interrupt method is not going to be used, then software (SSPSR) and a buffer register (SSPBUF). The SSPSR polling can be done to ensure that a write collision does shifts the data in and out of the device, MSb first. The not occur. Example15-1 shows the loading of the SSPBUF holds the data that was written to the SSPSR, SSPBUF (SSPSR) for data transmission. until the received data is ready. Once the 8 bits of data The SSPSR is not directly readable or writable, and have been received, that byte is moved to the SSPBUF can only be accessed by addressing the SSPBUF reg- register. Then the buffer full detect bit, BF ister. Additionally, the MSSP status register (SSPSTAT) (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are indicates the various status conditions. set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the EXAMPLE 15-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS39564C-page 128 © 2006 Microchip Technology Inc.

PIC18FXX2 15.3.3 ENABLING SPI I/O 15.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN Figure15-2 shows a typical connection between two (SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, re-initialize the initiates the data transfer by sending the SCK signal. SSPCON registers, and then set the SSPEN bit. This Data is shifted out of both shift registers on their pro- configures the SDI, SDO, SCK, and SS pins as serial grammed clock edge, and latched on the opposite port pins. For the pins to behave as the serial port func- edge of the clock. Both processors should be pro- tion, some must have their data direction bits (in the grammed to the same Clock Polarity (CKP), then both TRIS register) appropriately programmed. That is: controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) (cid:129) SDI is automatically controlled by the SPI module depends on the application software. This leads to (cid:129) SDO must have TRISC<5> bit cleared three scenarios for data transmission: (cid:129) SCK (Master mode) must have TRISC<3> bit (cid:129) Master sends data — Slave sends dummy data cleared (cid:129) Master sends data — Slave sends data (cid:129) SCK (Slave mode) must have TRISC<3> bit set (cid:129) Master sends dummy data — Slave sends data (cid:129) SS must have TRISC<4> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 15-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 © 2006 Microchip Technology Inc. DS39564C-page 129

PIC18FXX2 15.3.5 MASTER MODE Figure15-3, Figure15-5, and Figure15-6, where the MSB is transmitted first. In Master mode, the SPI clock The master can initiate the data transfer at any time rate (bit rate) is user programmable to be one of the because it controls the SCK. The master determines following: when the slave (Processor 2, Figure15-2) is to broadcast data by the software protocol. (cid:129) FOSC/4 (or TCY) (cid:129) FOSC/16 (or 4 (cid:129) TCY) In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is (cid:129) FOSC/64 (or 16 (cid:129) TCY) only going to receive, the SDO output could be dis- (cid:129) Timer2 output/2 abled (programmed as an input). The SSPSR register This allows a maximum data rate (at 40 MHz) of will continue to shift in the signal present on the SDI pin 10.00Mbps. at the programmed clock rate. As each byte is Figure15-3 shows the waveforms for Master mode. received, it will be loaded into the SSPBUF register as When the CKE bit is set, the SDO data is valid before if a normal received byte (interrupts and status bits there is a clock edge on SCK. The change of the input appropriately set). This could be useful in receiver sample is shown based on the state of the SMP bit. The applications as a “Line Activity Monitor” mode. time when the SSPBUF is loaded with the received The clock polarity is selected by appropriately program- data is shown. ming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in FIGURE 15-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (CKE = 0) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (CKE = 1) SDI (SMP = 0) bit7 bit0 Input Sample (SMP = 0) SDI (SMP = 1) bit7 bit0 Input Sample (SMP = 1) SSPIF Next Q4 cycle SSPSR to after Q2↓ SSPBUF DS39564C-page 130 © 2006 Microchip Technology Inc.

PIC18FXX2 15.3.6 SLAVE MODE longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ In Slave mode, the data is transmitted and received as pull-down resistors may be desirable, depending on the the external clock pulses appear on SCK. When the application. last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode with SS While in Slave mode, the external clock is supplied by pin control enabled (SSPCON<3:0> = the external clock source on the SCK pin. This external 0100), the SPI module will reset if the SS clock must meet the minimum high and low times as pin is set to VDD. specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE While in SLEEP mode, the slave can transmit/receive set, then the SS pin control must be data. When a byte is received, the device will wake-up enabled. from sleep. When the SPI module resets, the bit counter is forced 15.3.7 SLAVE SELECT to 0. This can be done by either forcing the SS pin to a SYNCHRONIZATION high level or clearing the SSPEN bit. The SS pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDO pin can SPI must be in Slave mode with SS pin control enabled be connected to the SDI pin. When the SPI needs to (SSPCON1<3:0> = 04h). The pin must not be driven operate as a receiver the SDO pin can be configured as low for the SS pin to function as an input. The Data an input. This disables transmissions from the SDO. Latch must be high. When the SS pin is low, transmis- The SDI can always be left as an input (SDI function), sion and reception are enabled and the SDO pin is since it cannot create a bus conflict. driven. When the SS pin goes high, the SDO pin is no FIGURE 15-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit7 bit6 bit7 bit0 SDI bit0 (SMP = 0) bit7 bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle SSPSR to after Q2↓ SSPBUF © 2006 Microchip Technology Inc. DS39564C-page 131

PIC18FXX2 FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle SSPSR to after Q2↓ SSPBUF FIGURE 15-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2↓ SSPSR to SSPBUF DS39564C-page 132 © 2006 Microchip Technology Inc.

PIC18FXX2 15.3.8 SLEEP OPERATION 15.3.10 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted and the Table15-1 shows the compatibility between the transmission/reception will remain in that state until the standard SPI modes and the states the CKP and CKE device wakes from SLEEP. After the device returns to control bits. Normal mode, the module will continue to transmit/ receive data. TABLE 15-1: SPI BUS MODES In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This allows the Standard SPI Mode Control Bits State device to be placed in SLEEP mode and data to be Terminology CKP CKE shifted into the SPI transmit/receive shift register. 0, 0 0 1 When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device 0, 1 0 0 from SLEEP. 1, 0 1 1 1, 1 1 0 15.3.9 EFFECTS OF A RESET There is also a SMP bit which controls when the data is A RESET disables the MSSP module and terminates sampled. the current transfer. TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 TRISA — PORTA Data Direction Register -111 1111 -111 1111 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. DS39564C-page 133

PIC18FXX2 15.4 I2C Mode 15.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call sup- These are: port) and provides interrupts on START and STOP bits (cid:129) MSSP Control Register1 (SSPCON1) in hardware to determine a free bus (multi-master func- (cid:129) MSSP Control Register2 (SSPCON2) tion). The MSSP module implements the Standard (cid:129) MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit addressing. (cid:129) Serial Receive/Transmit Buffer (SSPBUF) (cid:129) MSSP Shift Register (SSPSR) - Not directly Two pins are used for data transfer: accessible (cid:129) Serial clock (SCL) - RC3/SCK/SCL (cid:129) MSSP Address Register (SSPADD) (cid:129) Serial data (SDA) - RC4/SDI/SDA SSPCON, SSPCON2 and SSPSTAT are the control The user must configure these pins as inputs or outputs and status registers in I2C mode operation. The through the TRISC<4:3> bits. SSPCON and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read FIGURE 15-7: MSSP BLOCK DIAGRAM only. The upper two bits of the SSPSTAT are read/ (I2C MODE) write. SSPSR is the shift register used for shifting data in or Internal out. SSPBUF is the buffer register to which data bytes Data Bus are written to or read from. Read Write SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When SSPBUF reg RC3/SCK/SCL the SSP is configured in Master mode, the lower seven bits of SSPADD act as the baud rate generator Shift Clock reload value. SSPSR reg In receive operations, SSPSR and SSPBUF together, create a double buffered receiver. When SSPSR RC4/ MSb LSb SDI/ receives a complete byte, it is transferred to SSPBUF SDA and the SSPIF interrupt is set. Match Detect Addr Match During transmission, the SSPBUF is not double buff- ered. A write to SSPBUF will write to both SSPBUF and SSPADD reg SSPSR. START and Set, Reset STOP bit Detect S, P bits (SSPSTAT reg) DS39564C-page 134 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 15-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: STOP bit 1 = Indicates that a STOP bit has been detected last 0 = STOP bit was not detected last Note: This bit is cleared on RESET and when SSPEN is cleared. bit 3 S: START bit 1 = Indicates that a start bit has been detected last 0 = START bit was not detected last Note: This bit is cleared on RESET and when SSPEN is cleared. bit 2 R/W: Read/Write bit Information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. bit 1 UA: Update Address (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 135

PIC18FXX2 REGISTER 15-4: SSPCON1: MSSP CONTROL REGISTER1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave IDLE) 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved, or implemented in SPI mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 136 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 15-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence IDLE bit 3 RCEN: Receive Enable bit (Master mode only) 1 = Enables Receive mode for I2C 0 = Receive IDLE bit 2 PEN: STOP Condition Enable bit (Master mode only) 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition IDLE bit 1 RSEN: Repeated START Condition Enabled bit (Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition IDLE bit 0 SEN: START Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition IDLE In Slave mode: 1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled) 0 = Clock stretching is enabled for slave transmit only (Legacy mode) Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 137

PIC18FXX2 15.4.2 OPERATION 15.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON<5>). a START condition to occur. Following the START con- dition, the 8-bits are shifted into the SSPSR register. All The SSPCON1 register allows control of the I2C oper- incoming bits are sampled with the rising edge of the ation. Four mode selection bits (SSPCON<3:0>) allow clock (SCL) line. The value of register SSPSR<7:1> is one of the following I2C modes to be selected: compared to the value of the SSPADD register. The (cid:129) I2C Master mode, clock = OSC/4 (SSPADD +1) address is compared on the falling edge of the eighth (cid:129) I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match, and the BF (cid:129) I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: (cid:129) I2C Slave mode (7-bit address), with START and 1. The SSPSR register value is loaded into the STOP bit interrupts enabled SSPBUF register. (cid:129) I2C Slave mode (10-bit address), with START and 2. The buffer full bit BF is set. STOP bit interrupts enabled 3. An ACK pulse is generated. (cid:129) I2C Firmware controlled master operation, slave 4. MSSP interrupt flag bit, SSPIF (PIR1<3>) is set is IDLE (interrupt is generated if enabled) on the falling Selection of any I2C mode, with the SSPEN bit set, edge of the ninth SCL pulse. forces the SCL and SDA pins to be open drain, pro- In 10-bit Address mode, two address bytes need to be vided these pins are programmed to inputs by setting received by the slave. The five Most Significant bits the appropriate TRISC bits. To guarantee proper oper- (MSbs) of the first address byte specify if this is a 10-bit ation of the module, pull-up resistors must be provided address. Bit R/W (SSPSTAT<2>) must specify a write externally to the SCL and SDA pins. so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal 15.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the address. The sequence of events for 10-bit In Slave mode, the SCL and SDA pins must be config- address is as follows, with steps 7 through 9 for the ured as inputs (TRISC<4:3> set). The MSSP module slave-transmitter: will override the input state with the output data when required (slave-transmitter). 1. Receive first (high) byte of Address (bits SSPIF, The I2C Slave mode hardware will always generate an BF and bit UA (SSPSTAT<1>) are set). interrupt on an address match. Through the mode 2. Update the SSPADD register with second (low) select bits, the user can also choose to interrupt on byte of Address (clears bit UA and releases the START and STOP bits SCL line). 3. Read the SSPBUF register (clears bit BF) and When an address is matched or the data transfer after clear flag bit SSPIF. an address match is received, the hardware automati- cally will generate the Acknowledge (ACK) pulse and 4. Receive second (low) byte of Address (bits load the SSPBUF register with the received value SSPIF, BF, and UA are set). currently in the SSPSR register. 5. Update the SSPADD register with the first (high) byte of Address. If match releases SCL line, this Any combination of the following conditions will cause will clear bit UA. the MSSP module not to give this ACK pulse: 6. Read the SSPBUF register (clears bit BF) and (cid:129) The buffer full bit BF (SSPSTAT<0>) was set clear flag bit SSPIF. before the transfer was received. 7. Receive Repeated START condition. (cid:129) The overflow bit SSPOV (SSPCON<6>) was set 8. Receive first (high) byte of Address (bits SSPIF before the transfer was received. and BF are set). In this case, the SSPSR register value is not loaded 9. Read the SSPBUF register (clears bit BF) and into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The clear flag bit SSPIF. BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter100 and parameter101. DS39564C-page 138 © 2006 Microchip Technology Inc.

PIC18FXX2 15.4.3.2 Reception The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA When the R/W bit of the address byte is clear and an line is high (not ACK), then the data transfer is com- address match occurs, the R/W bit of the SSPSTAT plete. In this case, when the ACK is latched by the register is cleared. The received address is loaded into slave, the slave logic is reset (resets SSPSTAT regis- the SSPBUF register and the SDA line is held low ter) and the slave monitors for another occurrence of (ACK). the START bit. If the SDA line was low (ACK), the next When the address byte overflow condition exists, then transmit data must be loaded into the SSPBUF register. the no Acknowledge (ACK) pulse is given. An overflow Again, pin RC3/SCK/SCL must be enabled by setting condition is defined as either bit BF (SSPSTAT<0>) is bit CKP. set, or bit SSPOV (SSPCON1<6>) is set. An MSSP interrupt is generated for each data transfer An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- the SSPSTAT register is used to determine the status ware. The SSPSTAT register is used to determine the of the byte. The SSPIF bit is set on the falling edge of status of the byte. the ninth clock pulse. If SEN is enabled (SSPCON1<0>=1), RC3/SCK/SCL will be held low (clock stretch) following each data trans- fer. The clock must be released by setting bit CKP (SSPCON<4>). See Section15.4.4 (“Clock Stretching”), for more detail. 15.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low, regardless of SEN (see “Clock Stretching”, Section15.4.4, for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data.The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/ SCK/SCL should be enabled by setting bit CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure15-9). © 2006 Microchip Technology Inc. DS39564C-page 139

PIC18FXX2 2 FIGURE 15-8: I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus Masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D6D5D4 234 Cleared in softwarSSPBUF is read 7 D 1 K 9 C = 0 A W 8 R/ A1 7 A2 6 = 0) ess EN ddr A3 5 n S A e Receiving A5A4 34 set to ‘0’ wh e ot r A6 2 s n e o A7 1 0>) ON<6>) (CKP d SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39564C-page 140 © 2006 Microchip Technology Inc.

PIC18FXX2 2 FIGURE 15-9: I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o ata D1 7 Fr D Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S D0 8 m S o 1 Fr D 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft CKP is set in software D7 1 PIF S SCL held lowwhile CPUresponds to S K C A 9 1 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g eivin A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < < T 1 A R T DA CL S SPIF (PI F (SSPS KP S S S B C © 2006 Microchip Technology Inc. DS39564C-page 141

PIC18FXX2 FIGURE 15-10: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus Masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. 0 D 8 1 D 7 e 2 ar a Byte D3D 56 n softw ceive Dat D5D4 34 Cleared i e R 6 D 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of Address KA7A6A5A4A3A2A1 91234567 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardwarewhen SSPADD is updatedwith low byte of address UA is set indicating thatSSPADD needs to beupdated Receive First Byte of AddressR/W = 0 AC11110A9A8 12345678 Cleared in software AT<0>) SSPBUF is written withcontents of SSPSR PCON<6>) AT<1>) UA is set indicating thatthe SSPADD needs to beupdated (CKP does not reset to ‘0’ when SEN = 0) SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C DS39564C-page 142 © 2006 Microchip Technology Inc.

PIC18FXX2 2 FIGURE 15-11: I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus Masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘1’ Receive First Byte of AddressTransmitting Data ByteR/W=1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard 0 8 Clock is held low untilupdate of SSPADD has taken place 0Receive Second Byte of Address A7A6A5A4A3A2A1AK 91234567 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/W = e First Byte of Address 110A9A8AC 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv 11 12 AT<0>) AT<1>) ON<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPST UA (SSPST CKP (SSPC © 2006 Microchip Technology Inc. DS39564C-page 143

PIC18FXX2 15.4.4 CLOCK STRETCHING 15.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the The SEN bit (SSPCON2<0>) allows clock stretching to ninth clock, if the BF bit is clear. This occurs, be enabled during receives. Setting SEN will cause regardless of the state of the SEN bit. the SCL pin to be held low at the end of each data receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 15.4.4.1 Clock Stretching for 7-bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure15-9). In 7-bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF Note 1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is auto- setting the BF bit before the falling edge of matically cleared, forcing the SCL output to be held the ninth clock, the CKP bit will not be low. The CKP being cleared to ‘0’ will assert the SCL cleared and clock stretching will not occur. line low. The CKP bit must be set in the user’s ISR 2: The CKP bit can be set in software, before reception is allowed to continue. By holding the regardless of the state of the BF bit. SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master 15.4.4.4 Clock Stretching for 10-bit Slave device can initiate another receive sequence. This will Transmit Mode prevent buffer overruns from occurring (see Figure15-13). In 10-bit Slave Transmit mode, clock stretching is con- trolled during the first two address sequences by the Note 1: If the user reads the contents of the state of the UA bit, just as it is in 10-bit Slave Receive SSPBUF before the falling edge of the mode. The first two addresses are followed by a third ninth clock, thus clearing the BF bit, the address sequence, which contains the high order bits CKP bit will not be cleared and clock of the 10-bit address and the R/W bit set to ‘1’. After stretching will not occur. the third address sequence is performed, the UA bit is 2: The CKP bit can be set in software, not set, the module is now configured in Transmit regardless of the state of the BF bit. The mode, and clock stretching is controlled by the BF flag, user should be careful to clear the BF bit as in 7-bit Slave Transmit mode (see Figure15-11). in the ISR before the next receive sequence, in order to prevent an overflow condition. 15.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address, and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs, and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39564C-page 144 © 2006 Microchip Technology Inc.

PIC18FXX2 15.4.4.5 Clock Synchronization and the CKP bit If a user clears the CKP bit, the SCL output is forced to ‘0’. Setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set, and all other devices on the I2C bus have de-asserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure15-12). FIGURE 15-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL Master device CKP asserts clock Master device de-asserts clock WR SSPCON © 2006 Microchip Technology Inc. DS39564C-page 145

PIC18FXX2 2 FIGURE 15-13: I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus Masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 e Clock is held low untilCKP is set to ‘1’ ACK D0D7D6 8912 CKPwrittento ‘1’ insoftwarBF is set after falling edge of the 9th clock,CKP is reset to ‘0’ andclock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘0’ and no clockstretching will occur S K 9 = 0 AC W 8 R/ A1 7 2 A 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 >) A7 1 <6 0>) ON SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39564C-page 146 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 15-14: I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lobecause ACK = 1 ACK 0 9P Bus Masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s D 8 1 D 7 e ck is held low untilP is set to ‘1’ Receive Data Byte ACKD7D6D5D4D3D2 9123456 Cleared in softwar CKP written to ‘1’in software Clock is held low untilupdate of SSPADD has Clotaken placeCK Receive Data Byte D7D6D5D4D3D1D0D2 12345786 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock. Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA, andUA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of Address0 A7A6A5A4A3A2A1A0K 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock. UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA, andUA will remain set. Receive First Byte of AddressR/W = 1110A9A8AC 2345678 Cleared in software >) SSPBUF is written withcontents of SSPSR N<6>) >) UA is set indicating thatthe SSPADD needs to beupdated 1 1 AT<0 PCO AT<1 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C © 2006 Microchip Technology Inc. DS39564C-page 147

PIC18FXX2 15.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), The addressing procedure for the I2C bus is such that the SSPIF interrupt flag bit is set. the first byte after the START condition usually deter- When the interrupt is serviced, the source for the inter- mines which device will be the slave addressed by the rupt can be checked by reading the contents of the master. The exception is the general call address, SSPBUF. The value can be used to determine if the which can address all devices. When this address is address was device specific or a general call address. used, all devices should, in theory, respond with an Acknowledge. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is consists of all 0’s with R/W = 0. configured in 10-bit Address mode, then the second The general call address is recognized when the Gen- half of the address is not necessary, the UA bit will not eral Call Enable bit (GCEN) is enabled (SSPCON2<7> be set, and the slave will begin receiving data after the set). Following a START bit detect, 8-bits are shifted Acknowledge (Figure15-15). into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 15-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) '0' GCEN (SSPCON2<7>) '1' DS39564C-page 148 © 2006 Microchip Technology Inc.

PIC18FXX2 15.4.6 MASTER MODE Note: The MSSP Module, when configured in I2C Master mode is enabled by setting and clearing the Master mode, does not allow queueing of appropriate SSPM bits in SSPCON1 and by setting the events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a START condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the START Master mode of operation is supported by interrupt condition is complete. In this case, the generation on the detection of the START and STOP SSPBUF will not be written to and the conditions. The STOP (P) and START (S) bits are WCOL bit will be set, indicating that a write cleared from a RESET or when the MSSP module is to the SSPBUF did not occur. disabled. Control of the I2C bus may be taken when the P bit is set or the bus is IDLE, with both the S and P bits The following events will cause SSP interrupt flag bit, clear. SSPIF, to be set (SSP interrupt if enabled): In Firmware Controlled Master mode, user code con- (cid:129) START condition ducts all I2C bus operations based on START and (cid:129) STOP condition STOP bit conditions. (cid:129) Data transfer byte transmitted/received Once Master mode is enabled, the user has six (cid:129) Acknowledge Transmit options. (cid:129) Repeated START 1. Assert a START condition on SDA and SCL. 2. Assert a Repeated START condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a STOP condition on SDA and SCL. 2 FIGURE 15-16: MSSP BLOCK DIAGRAM (I C MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA in Clock ct e SSPSR Detce) MSb LSb L ur e Oo abl WCk s SCL Receive En STAARcTGk nebonitwe, rSlaeTtdeOgeP bit, Clock Cntl ck Arbitrate/(hold off cloc o Cl START bit Detect STOP bit Detect SCL in Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV © 2006 Microchip Technology Inc. DS39564C-page 149

PIC18FXX2 15.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a START condition by set- pulses and the START and STOP conditions. A trans- ting the START enable bit, SEN fer is ended with a STOP condition or with a Repeated (SSPCON2<0>). START condition. Since the Repeated START condi- 2. SSPIF is set. The MSSP module will wait the tion is also the beginning of the next serial transfer, the required start time before any other operation I2C bus will not be released. takes place. In Master Transmitter mode, serial data is output 3. The user loads the SSPBUF with the slave through SDA, while SCL outputs the serial clock. The address to transmit. first byte transmitted contains the slave address of the 4. Address is shifted out the SDA pin until all 8 bits receiving device (7 bits) and the Read/Write (R/W) bit. are transmitted. In this case, the R/W bit will be logic '0'. Serial data is 5. The MSSP Module shifts in the ACK bit from the transmitted 8 bits at a time. After each byte is transmit- slave device and writes its value into the ted, an Acknowledge bit is received. START and STOP SSPCON2 register (SSPCON2<6>). conditions are output to indicate the beginning and the 6. The MSSP module generates an interrupt at the end of a serial transfer. end of the ninth clock cycle by setting the SSPIF In Master Receive mode, the first byte transmitted con- bit. tains the slave address of the transmitting device 7. The user loads the SSPBUF with eight bits of (7bits) and the R/W bit. In this case, the R/W bit will be data. logic '1'. Thus, the first byte transmitted is a 7-bit slave 8. Data is shifted out the SDA pin until all 8 bits are address followed by a '1' to indicate receive bit. Serial transmitted. data is received via SDA, while SCL outputs the serial 9. The MSSP Module shifts in the ACK bit from the clock. Serial data is received 8 bits at a time. After each slave device and writes its value into the byte is received, an Acknowledge bit is transmitted. SSPCON2 register (SSPCON2<6>). START and STOP conditions indicate the beginning and end of transmission. 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF The baud rate generator used for the SPI mode opera- bit. tion is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See 11. The user generates a STOP condition by setting the STOP enable bit PEN (SSPCON2<2>). Section15.4.7 (“Baud Rate Generator”), for more detail. 12. Interrupt is generated once the STOP condition is complete. DS39564C-page 150 © 2006 Microchip Technology Inc.

PIC18FXX2 15.4.7 BAUD RATE GENERATOR Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal In I2C Master mode, the baud rate generator (BRG) clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure15-17). When a write occurs to SSPBUF, the baud rate generator will automatically Table 15-3 demonstrates clock rates based on begin counting. The BRG counts down to 0 and stops instruction cycles and the BRG value loaded into until another reload has taken place. The BRG count is SSPADD. decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 15-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload Reload SCL Control CLKO BRG Down Counter Fosc/4 TABLE 15-3: I2C CLOCK RATE W/BRG FSCL(2) FCY FCY*2 BRG Value (2 Rollovers of BRG) 10 MHz 20 MHz 19h 400 kHz(1) 10 MHz 20 MHz 20h 312.5 kHz 10 MHz 20 MHz 3Fh 100 kHz 4 MHz 8 MHz 0Ah 400 kHz(1) 4 MHz 8 MHz 0Dh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1 MHz 2 MHz 03h 333 kHz(1) 1 MHz 2 MHz 0Ah 100kHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. 2: Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend low time of clock period, producing the effective frequency. © 2006 Microchip Technology Inc. DS39564C-page 151

PIC18FXX2 15.4.7.1 Clock Arbitration sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. Clock arbitration occurs when the master, during any This ensures that the SCL high time will always be at receive, transmit or Repeated START/STOP condition, least one BRG rollover count, in the event that the clock de-asserts the SCL pin (SCL allowed to float high). is held low by an external device (Figure15-18). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is FIGURE 15-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL de-asserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count. BRG Reload DS39564C-page 152 © 2006 Microchip Technology Inc.

PIC18FXX2 15.4.8 I2C MASTER MODE START 15.4.8.1 WCOL Status Flag CONDITION TIMING If the user writes the SSPBUF when a START To initiate a START condition, the user sets the START sequence is in progress, the WCOL is set and the con- condition enable bit, SEN (SSPCON2<0>). If the SDA tents of the buffer are unchanged (the write doesn’t and SCL pins are sampled high, the baud rate genera- occur). tor is reloaded with the contents of SSPADD<6:0> and Note: Because queueing of events is not starts its count. If SCL and SDA are both sampled high allowed, writing to the lower 5 bits of when the baud rate generator times out (TBRG), the SSPCON2 is disabled until the START SDA pin is driven low. The action of the SDA being condition is complete. driven low, while SCL is high, is the START condition and causes the S bit (SSPSTAT<3>) to be set. Follow- ing this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the baud rate generator is suspended, leaving the SDA line held low and the START condition is complete. Note: If at the beginning of the START condition, the SDA and SCL pins are already sam- pled low, or if during the START condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF is set, the START condition is aborted, and the I2C module is reset into its IDLE state. FIGURE 15-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of START bit, SCL = 1 Hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S © 2006 Microchip Technology Inc. DS39564C-page 153

PIC18FXX2 15.4.9 I2C MASTER MODE REPEATED Immediately following the SSPIF bit getting set, the START CONDITION TIMING user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. A Repeated START condition occurs when the RSEN After the first eight bits are transmitted and an ACK is bit (SSPCON2<1>) is programmed high and the I2C received, the user may then transmit an additional eight logic module is in the IDLE state. When the RSEN bit is bits of address (10-bit mode) or eight bits of data (7-bit set, the SCL pin is asserted low. When the SCL pin is mode). sampled low, the baud rate generator is loaded with the contents of SSPADD<5:0> and begins counting. The 15.4.9.1 WCOL Status Flag SDA pin is released (brought high) for one baud rate If the user writes the SSPBUF when a Repeated generator count (TBRG). When the baud rate generator START sequence is in progress, the WCOL is set and times out, if SDA is sampled high, the SCL pin will be the contents of the buffer are unchanged (the write de-asserted (brought high). When SCL is sampled doesn’t occur). high, the baud rate generator is reloaded with the con- tents of SSPADD<6:0> and begins counting. SDA and Note: Because queueing of events is not SCL must be sampled high for one TBRG. This action is allowed, writing of the lower 5 bits of then followed by assertion of the SDA pin (SDA = 0) for SSPCON2 is disabled until the Repeated one TBRG, while SCL is high. Following this, the RSEN START condition is complete. bit (SSPCON2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the baud rate generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: (cid:129) SDA is sampled low when SCL goes from low to high. (cid:129) SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". FIGURE 15-20: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 SDA = 1, occurs here. At completion of START bit, SDA = 1, SCL = 1 hardware clear RSEN bit SCL (no change) and set SSPIF TBRG TBRG TBRG 1st bit SDA Falling edge of ninth clock Write to SSPBUF occurs here End of Xmit TBRG SCL TBRG Sr = Repeated START DS39564C-page 154 © 2006 Microchip Technology Inc.

PIC18FXX2 15.4.10 I2C MASTER MODE 15.4.10.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is Transmission of a data byte, a 7-bit address, or the cleared when the slave has sent an Acknowledge (ACK other half of a 10-bit address is accomplished by simply = 0), and is set when the slave does not Acknowledge writing a value to the SSPBUF register. This action will (ACK = 1). A slave sends an Acknowledge when it has set the buffer full flag bit, BF, and allow the baud rate recognized its address (including a general call) or generator to begin counting and start the next transmis- when the slave has properly received its data. sion. Each bit of address/data will be shifted out onto 15.4.11 I2C MASTER MODE RECEPTION the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106). SCL Master mode reception is enabled by programming the is held low for one baud rate generator rollover count receive enable bit, RCEN (SSPCON2<3>). (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter 107). Note: In the MSSP module, the RCEN bit must be set after the ACK sequence or the When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable RCEN bit will be disregarded. for that duration and some hold time after the next fall- The baud rate generator begins counting, and on each ing edge of SCL. After the eighth bit is shifted out (the rollover, the state of the SCL pin changes (high to low/ falling edge of the eighth clock), the BF flag is cleared low to high) and data is shifted into the SSPSR. After and the master releases SDA. This allows the slave the falling edge of the eighth clock, the receive enable device being addressed to respond with an ACK bit flag is automatically cleared, the contents of the during the ninth bit time if an address match occurred SSPSR are loaded into the SSPBUF, the BF flag bit is or if data was received properly. The status of ACK is set, the SSPIF flag bit is set and the baud rate genera- written into the ACKDT bit on the falling edge of the tor is suspended from counting, holding SCL low. The ninth clock. If the master receives an Acknowledge, the MSSP is now in IDLE state, awaiting the next com- Acknowledge status bit, ACKSTAT, is cleared. If not, mand. When the buffer is read by the CPU, the BF flag the bit is set. After the ninth clock, the SSPIF bit is set bit is automatically cleared. The user can then send an and the master clock (baud rate generator) is sus- Acknowledge bit at the end of reception, by setting the pended until the next data byte is loaded into the Acknowledge sequence enable bit, ACKEN SSPBUF, leaving SCL low and SDA unchanged (SSPCON2<4>). (Figure15-21). 15.4.11.1 BF Status Flag After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all seven In receive operation, the BF bit is set when an address address bits and the R/W bit are completed. On the fall- or data byte is loaded into SSPBUF from SSPSR. It is ing edge of the eighth clock, the master will de-assert cleared when the SSPBUF register is read. the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the 15.4.11.2 SSPOV Status Flag master will sample the SDA pin to see if the address In receive operation, the SSPOV bit is set when 8 bits was recognized by a slave. The status of the ACK bit is are received into the SSPSR and the BF flag bit is loaded into the ACKSTAT status bit (SSPCON2<6>). already set from a previous reception. Following the falling edge of the ninth clock transmis- sion of the address, the SSPIF is set, the BF flag is 15.4.11.3 WCOL Status Flag cleared and the baud rate generator is turned off until If the user writes the SSPBUF when a receive is another write to the SSPBUF takes place, holding SCL already in progress (i.e., SSPSR is still shifting in a data low and allowing SDA to float. byte), the WCOL bit is set and the contents of the buffer 15.4.10.1 BF Status Flag are unchanged (the write doesn’t occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 15.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2006 Microchip Technology Inc. DS39564C-page 155

PIC18FXX2 FIGURE 15-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A <6> D0 8 e 2 n AT bit SSPCON or Second Half D3D2D1 567 are service routiupt en in software slave clear ACKST Transmitting Data of 10-bit Address D6D5D4 234 Cleared in softwFrom SSP interr SSPBUF is writt From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to 0 ACK 9 re are = w R/W d R/W 8 y hard n b A1 s a 7 ed PCON2<0> SEN = 1ondition begins SEN = 0 Transmit Address to Slave A7A6A5A4A3A2 SSPBUF written with 7-bit addresstart transmit 123456 Cleared in software SSPBUF written After START condition, SEN clear Sc ST Write STAR S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS39564C-page 156 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 15-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from Masterer configured as a receiverSDA = ACKDT = 1 SDA = ACKDT = 0 ogramming SSPCON2<3>, (RCEN = 1)PEN bit = 1RCEN = 1 startRCEN clearedRCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus MasterACK is not sentterminatestransfer678998756512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr ACK from Slave R/W = 1A1ACK 798 Write to SSPCON2<0>(SEN = 1)Begin START Condition SEN = 0Write to SSPBUF occurs hereStart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 631245SCLS SSPIF Cleared in softwareSDA = 0, SCL = 1while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN © 2006 Microchip Technology Inc. DS39564C-page 157

PIC18FXX2 15.4.12 ACKNOWLEDGE SEQUENCE 15.4.13 STOP CONDITION TIMING TIMING A STOP bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the STOP sequence enable Acknowledge sequence enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/trans- (SSPCON2<4>). When this bit is set, the SCL pin is mit the SCL line is held low after the falling edge of the pulled low and the contents of the Acknowledge data bit ninth clock. When the PEN bit is set, the master will are presented on the SDA pin. If the user wishes to gen- assert the SDA line low. When the SDA line is sampled erate an Acknowledge, then the ACKDT bit should be low, the baud rate generator is reloaded and counts cleared. If not, the user should set the ACKDT bit before down to 0. When the baud rate generator times out, the starting an Acknowledge sequence. The baud rate gen- SCL pin will be brought high, and one TBRG (baud rate erator then counts for one rollover period (TBRG) and the generator rollover count) later, the SDA pin will be SCL pin is de-asserted (pulled high). When the SCL pin de-asserted. When the SDA pin is sampled high while is sampled high (clock arbitration), the baud rate gener- SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG ator counts for TBRG. The SCL pin is then pulled low. Fol- later, the PEN bit is cleared and the SSPIF bit is set lowing this, the ACKEN bit is automatically cleared, the (Figure15-24). baud rate generator is turned off and the MSSP module 15.4.13.1 WCOL Status Flag then goes into IDLE mode (Figure15-23). If the user writes the SSPBUF when a STOP sequence 15.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the con- If the user writes the SSPBUF when an Acknowledge tents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the con- occur). tents of the buffer are unchanged (the write doesn’t occur). FIGURE 15-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in Set SSPIF at the end Cleared in software of receive software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one baud rate generator period. FIGURE 15-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. Set PEN Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition. Note: TBRG = one baud rate generator period. DS39564C-page 158 © 2006 Microchip Technology Inc.

PIC18FXX2 15.4.14 SLEEP OPERATION 15.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS While in SLEEP mode, the I2C module can receive ARBITRATION addresses or data, and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from SLEEP (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 15.4.15 EFFECT OF A RESET outputs a '1' on SDA, by letting SDA float high and A RESET disables the MSSP module and terminates another master asserts a '0'. When the SCL pin floats the current transfer. high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', 15.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag BCLIF and reset the I2C In Multi-Master mode, the interrupt generation on the port to its IDLE state (Figure15-25). detection of the START and STOP conditions allows the If a transmit was in progress when the bus collision determination of when the bus is free. The STOP (P) occurred, the transmission is halted, the BF flag is and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control of the I2C bus cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services may be taken when the P bit (SSPSTAT<4>) is set, or the bus collision Interrupt Service Routine, and if the the bus is idle with both the S and P bits clear. When the I2C bus is free, the user can resume communication by bus is busy, enabling the SSP interrupt will generate the asserting a START condition. interrupt when the STOP condition occurs. If a START, Repeated START, STOP, or Acknowledge In multi-master operation, the SDA line must be moni- condition was in progress when the bus collision tored for arbitration, to see if the signal level is the occurred, the condition is aborted, the SDA and SCL expected output level. This check is performed in lines are de-asserted, and the respective control bits in hardware, with the result placed in the BCLIF bit. the SSPCON2 register are cleared. When the user ser- The states where arbitration can be lost are: vices the bus collision Interrupt Service Routine, and if (cid:129) Address Transfer the I2C bus is free, the user can resume communication by asserting a START condition. (cid:129) Data Transfer (cid:129) A START Condition The master will continue to monitor the SDA and SCL pins. If a STOP condition occurs, the SSPIF bit will be set. (cid:129) A Repeated START Condition (cid:129) An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is IDLE and the S and P bits are cleared. FIGURE 15-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA line pulled low Sample SDA. While SCL is high, Data changes by another source data doesn’t match what is driven while SCL = 0 by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF © 2006 Microchip Technology Inc. DS39564C-page 159

PIC18FXX2 15.4.17.1 Bus Collision During a START If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure15-28). If, however, a '1' is sampled on the SDA During a START condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The baud rate generator is then reloaded and the START condition (Figure15-26). counts down to 0, and during this time, if the SCL pins b) SCL is sampled low before SDA is asserted low are sampled as '0', a bus collision does not occur. At (Figure15-27). the end of the BRG count, the SCL pin is asserted low. During a START condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a START condition is that no two bus masters can assert a START condition If the SDA pin is already low, or the SCL pin is already at the exact same time. Therefore, one low, then all of the following occur: master will always assert SDA before the (cid:129) the START condition is aborted, other. This condition does not cause a bus (cid:129) the BCLIF flag is set, and collision, because the two masters must be (cid:129) the MSSP module is reset to its IDLE state allowed to arbitrate the first address follow- (Figure15-26). ing the START condition. If the address is The START condition begins with the SDA and SCL the same, arbitration must be allowed to pins de-asserted. When the SDA pin is sampled high, continue into the data portion, Repeated the baud rate generator is loaded from SSPADD<6:0> START or STOP conditions. and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition. FIGURE 15-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable START SEN cleared automatically because of bus collision. condition if SDA = 1, SCL=1 SSP module reset into IDLE state. SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software. S SSPIF SSPIF and BCLIF are cleared in software. DS39564C-page 160 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 15-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. set BCLIF SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S '0' '0' SSPIF '0' '0' FIGURE 15-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG Time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF '0' S SSPIF SDA = 0, SCL = 1 Interrupts cleared Set SSPIF in software © 2006 Microchip Technology Inc. DS39564C-page 161

PIC18FXX2 15.4.17.2 Bus Collision During a Repeated reloaded and begins counting. If SDA goes from high to START Condition low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the During a Repeated START condition, a bus collision same time. occurs if: If SCL goes from high to low before the BRG times out a) A low level is sampled on SDA when SCL goes and SDA has not already been asserted, a bus collision from low level to high level. occurs. In this case, another master is attempting to b) SCL goes low before SDA is asserted low, indi- transmit a data ’1’ during the Repeated START cating that another master is attempting to condition, Figure15-30. transmit a data ’1’. If, at the end of the BRG time-out both SCL and SDA When the user de-asserts SDA and the pin is allowed are still high, the SDA pin is driven low and the BRG is to float high, the BRG is loaded with SSPADD<6:0> reloaded and begins counting. At the end of the count, and counts down to 0. The SCL pin is then de-asserted, regardless of the status of the SCL pin, the SCL pin is and when sampled high, the SDA pin is sampled. driven low and the Repeated START condition is If SDA is low, a bus collision has occurred (i.e., another complete. master is attempting to transmit a data ’0’, Figure15-29). If SDA is sampled high, the BRG is FIGURE 15-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S '0' SSPIF '0' FIGURE 15-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF Set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S '0' SSPIF DS39564C-page 162 © 2006 Microchip Technology Inc.

PIC18FXX2 15.4.17.3 Bus Collision During a STOP The STOP condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a STOP condition if: the baud rate generator is loaded with SSPADD<6:0> a) After the SDA pin has been de-asserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is de-asserted, SCL is drive a data '0' (Figure15-31). If the SCL pin is sampled sampled low before SDA goes high. low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data '0' (Figure15-32). FIGURE 15-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, Set BCLIF SDA SDA asserted low SCL PEN BCLIF P '0' SSPIF '0' FIGURE 15-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high Assert SDA Set BCLIF SCL PEN BCLIF P '0' SSPIF '0' © 2006 Microchip Technology Inc. DS39564C-page 163

PIC18FXX2 NOTES: DS39564C-page 164 © 2006 Microchip Technology Inc.

PIC18FXX2 16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Com- munications Interface or SCI.) The USART can be con- figured as a full duplex asynchronous system that can communicate with peripheral devices, such as CRT ter- minals and personal computers, or it can be configured as a half-duplex synchronous system that can commu- nicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The USART can be configured in the following modes: (cid:129) Asynchronous (full-duplex) (cid:129) Synchronous - Master (half-duplex) (cid:129) Synchronous - Slave (half-duplex) In order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter: (cid:129) bit SPEN (RCSTA<7>) must be set (= 1), (cid:129) bit TRISC<6> must be cleared (= 0), and (cid:129) bit TRISC<7> must be set (=1). Register16-1 shows the Transmit Status and Control Register (TXSTA) and Register16-2 shows the Receive Status and Control Register (RCSTA). © 2006 Microchip Technology Inc. DS39564C-page 165

PIC18FXX2 REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as '0' bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be Address/Data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS39564C-page 166 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode - Master: 1 =Enables single receive 0 =Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 =Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set 0 =Disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be Address/Data bit or a parity bit, and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 167

PIC18FXX2 16.1 USART Baud Rate Generator Example16-1 shows the calculation of the baud rate (BRG) error for the following conditions: (cid:129) FOSC = 16 MHz The BRG supports both the Asynchronous and Syn- (cid:129) Desired Baud Rate = 9600 chronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the (cid:129) BRGH = 0 period of a free running 8-bit timer. In Asynchronous (cid:129) SYNC = 0 mode, bit BRGH (TXSTA<2>) also controls the baud It may be advantageous to use the high baud rate rate. In Synchronous mode, bit BRGH is ignored. (BRGH = 1) even for slower baud clocks. This is Table16-1 shows the formula for computation of the because the FOSC/(16(X + 1)) equation can reduce the baud rate for different USART modes, which only apply baud rate error in some cases. in Master mode (internal clock). Writing a new value to the SPBRG register causes the Given the desired baud rate and Fosc, the nearest inte- BRG timer to be reset (or cleared). This ensures the ger value for the SPBRG register can be calculated BRG does not wait for a timer overflow before using the formula in Table16-1. From this, the error in outputting the new baud rate. baud rate can be determined. 16.1.1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. EXAMPLE 16-1: CALCULATING BAUD RATE ERROR Desired Baud Rate = FOSC / (64 (X + 1)) Solving for X: X = ( (FOSC / Desired Baud Rate) / 64 ) – 1 X = ((16000000 / 9600) / 64) – 1 X = [25.042] = 25 Calculated Baud Rate = 16000000 / (64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600) / 9600 = 0.16% TABLE 16-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1)) 1 (Synchronous) Baud Rate = FOSC/(4(X+1)) N/A Legend: X = value in SPBRG (0 to 255) TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG. DS39564C-page 168 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 16-3: BAUD RATES FOR SYNCHRONOUS MODE BAUD FOSC = 40 MHz SPBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - NA - - NA - - 19.2 NA - - NA - - NA - - NA - - 76.8 76.92 +0.16 129 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 96 96.15 +0.16 103 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 300 303.03 +1.01 32 294.64 -1.79 27 297.62 -0.79 20 294.12 -1.96 16 500 500 0 19 485.30 -2.94 16 480.77 -3.85 12 500 0 9 HIGH 10000 - 0 8250 - 0 6250 - 0 5000 - 0 LOW 39.06 - 255 32.23 - 255 24.41 - 255 19.53 - 255 BAUD FOSC = 16 MHz SPBRG 10 MHz SPBRG 7.15909 MHz SPBRG 5.0688 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - 9.62 +0.23 185 9.60 0 131 19.2 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 19.20 0 65 76.8 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 74.54 -2.94 16 96 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 307.70 +2.56 12 312.50 +4.17 7 298.35 -0.57 5 316.80 +5.60 3 500 500 0 7 500 0 4 447.44 -10.51 3 422.40 -15.52 2 HIGH 4000 - 0 2500 - 0 1789.80 - 0 1267.20 - 0 LOW 15.63 - 255 9.77 - 255 6.99 - 255 4.95 - 255 BAUD FOSC = 4 MHz SPBRG 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - 0.30 +1.14 26 1.2 NA - - NA - - 1.20 +0.16 207 1.17 -2.48 6 2.4 NA - - NA - - 2.40 +0.16 103 2.73 +13.78 2 9.6 9.62 +0.16 103 9.62 +0.23 92 9.62 +0.16 25 8.20 -14.67 0 19.2 19.23 +0.16 51 19.04 -0.83 46 19.23 +0.16 12 NA - - 76.8 76.92 +0.16 12 74.57 -2.90 11 83.33 +8.51 2 NA - - 96 1000 +4.17 9 99.43 +3.57 8 83.33 -13.19 2 NA - - 300 333.33 +11.11 2 298.30 -0.57 2 250 -16.67 0 NA - - 500 500 0 1 447.44 -10.51 1 NA - - NA - - HIGH 1000 - 0 894.89 - 0 250 - 0 8.20 - 0 LOW 3.91 - 255 3.50 - 255 0.98 - 255 0.03 - 255 © 2006 Microchip Technology Inc. DS39564C-page 169

PIC18FXX2 TABLE 16-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) BAUD FOSC = 40 MHz SPBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - 2.40 -0.07 214 2.40 -0.15 162 2.40 +0.16 129 9.6 9.62 +0.16 64 9.55 -0.54 53 9.53 -0.76 40 9.47 -1.36 32 19.2 18.94 -1.36 32 19.10 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 76.8 78.13 +1.73 7 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 96 89.29 -6.99 6 103.13 +7.42 4 97.66 +1.73 3 104.17 +8.51 2 300 312.50 +4.17 1 257.81 -14.06 1 NA - - 312.50 +4.17 0 500 625 +25.00 0 NA - - NA - - NA - - HIGH 625 - 0 515.63 - 0 390.63 - 0 312.50 - 0 LOW 2.44 - 255 2.01 - 255 1.53 - 255 1.22 - 255 BAUD FOSC = 16 MHz SPBRG 10 MHz SPBRG 7.15909 MHz SPBRG 5.0688 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 1.20 +0.16 207 1.20 +0.16 129 1.20 +0.23 92 1.20 0 65 2.4 2.40 +0.16 103 2.40 +0.16 64 2.38 -0.83 46 2.40 0 32 9.6 9.62 +0.16 25 9.77 +1.73 15 9.32 -2.90 11 9.90 +3.13 7 19.2 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 19.80 +3.13 3 76.8 83.33 +8.51 2 78.13 +1.73 1 111.86 +45.65 0 79.20 +3.13 0 96 83.33 -13.19 2 78.13 -18.62 1 NA - - NA - - 300 250 -16.67 0 156.25 -47.92 0 NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 250 - 0 156.25 - 0 111.86 - 0 79.20 - 0 LOW 0.98 - 255 0.61 - 255 0.44 - 255 0.31 - 255 BAUD FOSC = 4 MHz SPBRG 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 0.30 -0.16 207 0.30 +0.23 185 0.30 +0.16 51 0.26 -14.67 1 1.2 1.20 +1.67 51 1.19 -0.83 46 1.20 +0.16 12 NA - - 2.4 2.40 +1.67 25 2.43 +1.32 22 2.23 -6.99 6 NA - - 9.6 8.93 -6.99 6 9.32 -2.90 5 7.81 -18.62 1 NA - - 19.2 20.83 +8.51 2 18.64 -2.90 2 15.63 -18.62 0 NA - - 76.8 62.50 -18.62 0 55.93 -27.17 0 NA - - NA - - 96 NA - - NA - - NA - - NA - - 300 NA - - NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 62.50 - 0 55.93 - 0 15.63 - 0 0.51 - 0 LOW 0.24 - 255 0.22 - 255 0.06 - 255 0.002 - 255 DS39564C-page 170 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) BAUD FOSC = 40 MHz SPBRG 33 MHz SPBRG 25 MHz SPBRG 20 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - 9.60 -0.07 214 9.59 -0.15 162 9.62 +0.16 129 19.2 19.23 +0.16 129 19.28 +0.39 106 19.30 +0.47 80 19.23 +0.16 64 76.8 75.76 -1.36 32 76.39 -0.54 26 78.13 +1.73 19 78.13 +1.73 15 96 96.15 +0.16 25 98.21 +2.31 20 97.66 +1.73 15 96.15 +0.16 12 300 312.50 +4.17 7 294.64 -1.79 6 312.50 +4.17 4 312.50 +4.17 3 500 500 0 4 515.63 +3.13 3 520.83 +4.17 2 416.67 -16.67 2 HIGH 2500 - 0 2062.50 - 0 1562.50 - 0 1250 - 0 LOW 9.77 - 255 8,06 - 255 6.10 - 255 4.88 - 255 BAUD FOSC = 16 MHz SPBRG 10 MHz SPBRG 7.15909 MHz SPBRG 5.0688 MHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - 2.41 +0.23 185 2.40 0 131 9.6 9.62 +0.16 103 9.62 +0.16 64 9.52 -0.83 46 9.60 0 32 19.2 19.23 +0.16 51 18.94 -1.36 32 19.45 +1.32 22 18.64 -2.94 16 76.8 76.92 +0.16 12 78.13 +1.73 7 74.57 -2.90 5 79.20 +3.13 3 96 100 +4.17 9 89.29 -6.99 6 89.49 -6.78 4 105.60 +10.00 2 300 333.33 +11.11 2 312.50 +4.17 1 447.44 +49.15 0 316.80 +5.60 0 500 500 0 1 625 +25.00 0 447.44 -10.51 0 NA - - HIGH 1000 - 0 625 - 0 447.44 - 0 316.80 - 0 LOW 3.91 - 255 2.44 - 255 1.75 - 255 1.24 - 255 BAUD FOSC = 4 MHz SPBRG 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value % % % % (Kbps) (decimal) (decimal) (decimal) (decimal) KBAUD ERROR KBAUD ERROR KBAUD ERROR KBAUD ERROR 0.3 NA - - NA - - 0.30 +0.16 207 0.29 -2.48 6 1.2 1.20 +0.16 207 1.20 +0.23 185 1.20 +0.16 51 1.02 -14.67 1 2.4 2.40 +0.16 103 2.41 +0.23 92 2.40 +0.16 25 2.05 -14.67 0 9.6 9.62 +0.16 25 9.73 +1.32 22 8.93 -6.99 6 NA - - 19.2 19.23 +0.16 12 18.64 -2.90 11 20.83 +8.51 2 NA - - 76.8 NA - - 74.57 -2.90 2 62.50 -18.62 0 NA - - 96 NA - - 111.86 +16.52 1 NA - - NA - - 300 NA - - 223.72 -25.43 0 NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 250 - 0 55.93 - 0 62.50 - 0 2.05 - 0 LOW 0.98 - 255 0.22 - 255 0.24 - 255 0.008 - 255 © 2006 Microchip Technology Inc. DS39564C-page 171

PIC18FXX2 16.2 USART Asynchronous Mode flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE In this mode, the USART uses standard non-return-to- (PIE1<4>). Flag bit TXIF will be set, regardless of the zero (NRZ) format (one START bit, eight or nine data state of enable bit TXIE and cannot be cleared in soft- bits and one STOP bit). The most common data format ware. It will reset only when new data is loaded into the is 8-bits. An on-chip dedicated 8-bit baud rate genera- TXREG register. While flag bit TXIF indicated the sta- tor can be used to derive standard baud rate frequen- tus of the TXREG register, another bit, TRMT cies from the oscillator. The USART transmits and (TXSTA<1>), shows the status of the TSR register. Sta- receives the LSb first. The USART’s transmitter and tus bit TRMT is a read-only bit, which is set when the receiver are functionally independent, but use the TSR register is empty. No interrupt logic is tied to this same data format and baud rate. The baud rate gener- bit, so the user has to poll this bit in order to determine ator produces a clock, either x16 or x64 of the bit shift if the TSR register is empty. rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in Note 1: The TSR register is not mapped in data software (and stored as the ninth data bit). memory, so it is not available to the user. Asynchronous mode is stopped during SLEEP. 2: Flag bit TXIF is set when enable bit TXEN Asynchronous mode is selected by clearing bit SYNC is set. (TXSTA<4>). To set up an asynchronous transmission: The USART Asynchronous module consists of the 1. Initialize the SPBRG register for the appropriate following important elements: baud rate. If a high speed baud rate is desired, (cid:129) Baud Rate Generator set bit BRGH (Section16.1). (cid:129) Sampling Circuit 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. (cid:129) Asynchronous Transmitter 3. If interrupts are desired, set enable bit TXIE. (cid:129) Asynchronous Receiver 4. If 9-bit transmission is desired, set transmit bit 16.2.1 USART ASYNCHRONOUS TX9. Can be used as address/data bit. TRANSMITTER 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF. The USART transmitter block diagram is shown in 6. If 9-bit transmission is selected, the ninth bit Figure16-1. The heart of the transmitter is the Transmit should be loaded in bit TX9D. (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The 7. Load data to the TXREG register (starts TXREG register is loaded with data in software. The transmission). TSR register is not loaded until the STOP bit has been Note: TXIF is not cleared immediately upon load- transmitted from the previous load. As soon as the ing data into the transmit buffer TXREG. STOP bit is transmitted, the TSR is loaded with new The flag bit becomes valid in the second data from the TXREG register (if available). Once the instruction cycle following the load TXREG register transfers the data to the TSR register instruction. (occurs in one TCY), the TXREG register is empty and FIGURE 16-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D DS39564C-page 172 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 16-2: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) START bit bit 0 bit 1 bit 7/8 STOP bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 16-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC6/TX/CK (pin) START bit bit 0 bit 1 bit 7/8 STOP bit START bit bit 0 TXIF bit (Interrupt Reg. Flag) Word 1 Word 2 TRMT bit Word 1 Word 2 (RTeragn. sEmmipt tSyh Fifltag) Transmit Shift Reg. Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. DS39564C-page 173

PIC18FXX2 16.2.2 USART ASYNCHRONOUS 16.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure16-4. This mode would typically be used in RS-485 systems. The data is received on the RC7/RX/DT pin and drives To set up an Asynchronous Reception with Address the data recovery block. The data recovery block is Detect Enable: actually a high speed shifter operating at x16 times the 1. Initialize the SPBRG register for the appropriate baud rate, whereas the main receive serial shifter oper- baud rate. If a high speed baud rate is required, ates at the bit rate or at FOSC. This mode would set the BRGH bit. typically be used in RS-232 systems. 2. Enable the asynchronous serial port by clearing To set up an Asynchronous Reception: the SYNC bit and setting the SPEN bit. 1. Initialize the SPBRG register for the appropriate 3. If interrupts are required, set the RCEN bit and baud rate. If a high speed baud rate is desired, select the desired priority level with the RCIP bit. set bit BRGH (Section16.1). 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit SYNC and setting bit SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit RCIE. 7. The RCIF bit will be set when reception is com- 4. If 9-bit reception is desired, set bit RX9. plete. The interrupt will be acknowledged if the 5. Enable the reception by setting bit CREN. RCIE and GIE bits are set. 6. Flag bit RCIF will be set when reception is com- 8. Read the RCSTA register to determine if any plete and an interrupt will be generated if enable error occurred during reception, as well as read bit RCIE was set. bit 9 of data (if applicable). 7. Read the RCSTA register to get the ninth bit (if 9. Read RCREG to determine if the device is being enabled) and determine if any error occurred addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREG register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 16-4: USART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK ÷ 64 MSb RSR Register LSb SPBRG or ÷ 16 STOP (8) 7 • • • 1 0 START Baud Rate Generator RX9 RC7/RX/DT Pin Buffer Data and Control Recovery RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE DS39564C-page 174 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 16-5: ASYNCHRONOUS RECEPTION RX (pin) START START START bit bit0 bit1 bit7/8 STOP bit bit0 bit7/8 STOP bit bit7/8 STOP bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 16-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. DS39564C-page 175

PIC18FXX2 16.3 USART Synchronous Master (PIE1<4>). Flag bit TXIF will be set, regardless of the Mode state of enable bit TXIE, and cannot be cleared in soft- ware. It will reset only when new data is loaded into the In Synchronous Master mode, the data is transmitted in TXREG register. While flag bit TXIF indicates the status a half-duplex manner (i.e., transmission and reception of the TXREG register, another bit TRMT (TXSTA<1>) do not occur at the same time). When transmitting data, shows the status of the TSR register. TRMT is a read the reception is inhibited and vice versa. Synchronous only bit, which is set when the TSR is empty. No inter- mode is entered by setting bit SYNC (TXSTA<4>). In rupt logic is tied to this bit, so the user has to poll this addition, enable bit SPEN (RCSTA<7>) is set in order bit in order to determine if the TSR register is empty. to configure the RC6/TX/CK and RC7/RX/DT I/O pins The TSR is not mapped in data memory, so it is not to CK (clock) and DT (data) lines, respectively. The available to the user. Master mode indicates that the processor transmits the To set up a Synchronous Master Transmission: master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>). 1. Initialize the SPBRG register for the appropriate baud rate (Section16.1). 16.3.1 USART SYNCHRONOUS MASTER 2. Enable the synchronous master serial port by TRANSMISSION setting bits SYNC, SPEN, and CSRC. 3. If interrupts are desired, set enable bit TXIE. The USART transmitter block diagram is shown in Figure16-1. The heart of the transmitter is the Transmit 4. If 9-bit transmission is desired, set bit TX9. (serial) Shift Register (TSR). The shift register obtains 5. Enable the transmission by setting bit TXEN. its data from the read/write transmit buffer register 6. If 9-bit transmission is selected, the ninth bit TXREG. The TXREG register is loaded with data in should be loaded in bit TX9D. software. The TSR register is not loaded until the last 7. Start transmission by loading data to the TXREG bit has been transmitted from the previous load. As register. soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the Note: TXIF is not cleared immediately upon load- TXREG register transfers the data to the TSR register ing data into the transmit buffer TXREG. (occurs in one TCYCLE), the TXREG is empty and inter- The flag bit becomes valid in the second rupt bit TXIF (PIR1<4>) is set. The interrupt can be instruction cycle following the load enabled/disabled by setting/clearing enable bit TXIE instruction. TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. DS39564C-page 176 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 16-6: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 pin Word 1 Word 2 RC6/TX/CK pin Write to TXREG Reg Write Word1 Write Word2 TXIF bit (Interrupt Flag) TRMT bitTRMT '1' '1' TXEN bit Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words. FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit © 2006 Microchip Technology Inc. DS39564C-page 177

PIC18FXX2 16.3.2 USART SYNCHRONOUS MASTER 4. If interrupts are desired, set enable bit RCIE. RECEPTION 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN. Once Synchronous mode is selected, reception is For continuous reception, set bit CREN. enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is 7. Interrupt flag bit RCIF will be set when reception sampled on the RC7/RX/DT pin on the falling edge of is complete and an interrupt will be generated if the clock. If enable bit SREN is set, only a single word the enable bit RCIE was set. is received. If enable bit CREN is set, the reception is 8. Read the RCSTA register to get the ninth bit (if continuous until CREN is cleared. If both bits are set, enabled) and determine if any error occurred then CREN takes precedence. during reception. To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the RCREG register. 1. Initialize the SPBRG register for the appropriate 10. If any error occurred, clear the error by clearing baud rate (Section16.1). bit CREN. 2. Enable the synchronous master serial port by 11. If using interrupts, ensure that the GIE and PEIE setting bits SYNC, SPEN and CSRC. bits in the INTCON register (INTCON<7:6>) are 3. Ensure bits CREN and SREN are clear. set. TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception. Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'. DS39564C-page 178 © 2006 Microchip Technology Inc.

PIC18FXX2 16.4 USART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by set- Synchronous Slave mode differs from the Master mode ting bits SYNC and SPEN and clearing bit in the fact that the shift clock is supplied externally at CSRC. the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or 2. Clear bits CREN and SREN. receive data while in SLEEP mode. Slave mode is 3. If interrupts are desired, set enable bit TXIE. entered by clearing bit CSRC (TXSTA<7>). 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting enable bit 16.4.1 USART SYNCHRONOUS SLAVE TXEN. TRANSMIT 6. If 9-bit transmission is selected, the ninth bit The operation of the Synchronous Master and Slave should be loaded in bit TX9D. modes are identical, except in the case of the SLEEP 7. Start transmission by loading data to the TXREG mode. register. If two words are written to the TXREG and then the 8. If using interrupts, ensure that the GIE and PEIE SLEEP instruction is executed, the following will occur: bits in the INTCON register (INTCON<7:6>) are set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in TXREG register. c) Flag bit TXIF will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. e) If enable bit TXIE is set, the interrupt will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. © 2006 Microchip Technology Inc. DS39564C-page 179

PIC18FXX2 16.4.2 USART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit The operation of the Synchronous Master and Slave CSRC. modes is identical, except in the case of the SLEEP mode and bit SREN, which is a “don't care” in Slave 2. If interrupts are desired, set enable bit RCIE. mode. 3. If 9-bit reception is desired, set bit RX9. If receive is enabled by setting bit CREN prior to the 4. To enable reception, set enable bit CREN. SLEEP instruction, then a word may be received during 5. Flag bit RCIF will be set when reception is com- SLEEP. On completely receiving the word, the RSR plete. An interrupt will be generated if enable bit register will transfer the data to the RCREG register, RCIE was set. and if enable bit RCIE bit is set, the interrupt generated 6. Read the RCSTA register to get the ninth bit (if will wake the chip from SLEEP. If the global interrupt is enabled) and determine if any error occurred enabled, the program will branch to the interrupt vector. during reception. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 16-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. DS39564C-page 180 © 2006 Microchip Technology Inc.

PIC18FXX2 17.0 COMPATIBLE 10-BIT The A/D module has four registers. These registers ANALOG-TO-DIGITAL are: CONVERTER (A/D) MODULE (cid:129) A/D Result High Register (ADRESH) (cid:129) A/D Result Low Register (ADRESL) The Analog-to-Digital (A/D) converter module has five (cid:129) A/D Control Register 0 (ADCON0) inputs for the PIC18F2X2 devices and eight for the (cid:129) A/D Control Register 1 (ADCON1) PIC18F4X2 devices. This module has the ADCON0 and ADCON1 register definitions that are compatible The ADCON0 register, shown in Register17-1, con- with the mid-range A/D module. trols the operation of the A/D module. The ADCON1 register, shown in Register17-2, configures the The A/D allows conversion of an analog input signal to functions of the port pins. a corresponding 10-bit digital number. REGISTER 17-1: ADCON0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold) ADCON1 ADCON0 Clock Conversion <ADCS2> <ADCS1:ADCS0> 0 00 FOSC/2 0 01 FOSC/8 0 10 FOSC/32 0 11 FRC (clock derived from the internal A/D RC oscillator) 1 00 FOSC/4 1 01 FOSC/16 1 10 FOSC/64 1 11 FRC (clock derived from the internal A/D RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (AN0) 001 = channel 1, (AN1) 010 = channel 2, (AN2) 011 = channel 3, (AN3) 100 = channel 4, (AN4) 101 = channel 5, (AN5) 110 = channel 6, (AN6) 111 = channel 7, (AN7) Note: The PIC18F2X2 devices do not implement the full 8 A/D channels; the unimplemented selections are reserved. Do not select any unimplemented channel. bit 2 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress bit 1 Unimplemented: Read as '0' bit 0 ADON: A/D On bit 1 = A/D converter module is powered up 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 181

PIC18FXX2 REGISTER 17-2: ADCON1 REGISTER R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’. bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold) ADCON1 ADCON0 Clock Conversion <ADCS2> <ADCS1:ADCS0> 0 00 FOSC/2 0 01 FOSC/8 0 10 FOSC/32 0 11 FRC (clock derived from the internal A/D RC oscillator) 1 00 FOSC/4 1 01 FOSC/16 1 10 FOSC/64 1 11 FRC (clock derived from the internal A/D RC oscillator) bit 5-4 Unimplemented: Read as '0' bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C / R <3:0> 0000 A A A A A A A A VDD VSS 8 / 0 0001 A A A A VREF+ A A A AN3 VSS 7 / 1 0010 D D D A A A A A VDD VSS 5 / 0 0011 D D D A VREF+ A A A AN3 VSS 4 / 1 0100 D D D D A D A A VDD VSS 3 / 0 0101 D D D D VREF+ D A A AN3 VSS 2 / 1 011x D D D D D D D D — — 0 / 0 1000 A A A A VREF+ VREF- A A AN3 AN2 6 / 2 1001 D D A A A A A A VDD VSS 6 / 0 1010 D D A A VREF+ A A A AN3 VSS 5 / 1 1011 D D A A VREF+ VREF- A A AN3 AN2 4 / 2 1100 D D D A VREF+ VREF- A A AN3 AN2 3 / 2 1101 D D D D VREF+ VREF- A A AN3 AN2 2 / 2 1110 D D D D D D D A VDD VSS 1 / 0 1111 D D D D VREF+ VREF- D A AN3 AN2 1 / 2 A = Analog input D = Digital I/O C/R = # of analog input channels / # of A/D voltage references Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are forced to be an analog input. DS39564C-page 182 © 2006 Microchip Technology Inc.

PIC18FXX2 The analog reference voltage is software selectable to Each port pin associated with the A/D converter can be either the device’s positive and negative supply voltage configured as an analog input (RA3 can also be a (VDD and VSS), or the voltage level on the RA3/AN3/ voltage reference) or as a digital I/O. VREF+ pin and RA2/AN2/VREF- pin. The ADRESH and ADRESL registers contain the result The A/D converter has a unique feature of being able of the A/D conversion. When the A/D conversion is to operate while the device is in SLEEP mode. To oper- complete, the result is loaded into the ADRESH/ ate in SLEEP, the A/D conversion clock must be ADRESL registers, the GO/DONE bit (ADCON0<2>) is derived from the A/D’s internal RC oscillator. cleared, and A/D interrupt flag bit, ADIF is set. The block diagram of the A/D module is shown in Figure17-1. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. FIGURE 17-1: A/D BLOCK DIAGRAM CHS<2:0> 111 AN7* 110 AN6* 101 AN5* 100 AN4 VAIN 011 (Input Voltage) AN3 010 10-bit AN2 Converter A/D 001 AN1 PCFG<3:0> 000 VDD AN0 VREF+ Reference Voltage VREF- VSS * These channels are implemented only on the PIC18F4X2 devices. © 2006 Microchip Technology Inc. DS39564C-page 183

PIC18FXX2 The value that is in the ADRESH/ADRESL registers is 5. Wait for A/D conversion to complete, by either: not modified for a Power-on Reset. The ADRESH/ (cid:129) Polling for the GO/DONE bit to be cleared ADRESL registers will contain unknown data after a (interrupts disabled) Power-on Reset. OR After the A/D module has been configured as desired, (cid:129) Waiting for the A/D interrupt the selected channel must be acquired before the con- 6. Read A/D Result registers (ADRESH/ADRESL); version is started. The analog input channels must clear bit ADIF if required. have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section17.1. 7. For next conversion, go to step 1 or step 2 as After this acquisition time has elapsed, the A/D conver- required. The A/D conversion time per bit is sion can be started. The following steps should be defined as TAD. A minimum wait of 2 TAD is followed for doing an A/D conversion: required before the next acquisition starts. 1. Configure the A/D module: 17.1 A/D Acquisition Requirements (cid:129) Configure analog pins, voltage reference and digital I/O (ADCON1) For the A/D converter to meet its specified accuracy, (cid:129) Select A/D input channel (ADCON0) the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The (cid:129) Select A/D conversion clock (ADCON0) analog input model is shown in Figure17-2. The (cid:129) Turn on A/D module (ADCON0) source impedance (RS) and the internal sampling 2. Configure A/D interrupt (if desired): switch (RSS) impedance directly affect the time (cid:129) Clear ADIF bit required to charge the capacitor CHOLD. The sampling (cid:129) Set ADIE bit switch (RSS) impedance varies over the device voltage (cid:129) Set GIE bit (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The (cid:129) Set PEIE bit maximum recommended impedance for analog 3. Wait the required acquisition time. sources is 2.5kΩ. After the analog input channel is 4. Start conversion: selected (changed), this acquisition must be done (cid:129) Set GO/DONE bit (ADCON0) before the conversion can be started. Note: When the conversion is started, the hold- ing capacitor is disconnected from the input pin. FIGURE 17-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE CHOLD = 120 pF VSS Legend:CPIN = input capacitance 6V VT = threshold voltage 5V I LEAKAGE = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 8 9 10 11 Sampling Switch (kΩ) DS39564C-page 184 © 2006 Microchip Technology Inc.

PIC18FXX2 To calculate the minimum acquisition time, Equation17-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. EQUATION 17-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 17-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) (cid:129)(1 – e (-Tc/CHOLD(RIC + RSS + RS))) or TC = -(120 pF)(1 kΩ + RSS + RS) ln(1/2048) Example17-1 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assump- tions: (cid:129) CHOLD = 120 pF (cid:129) Rs = 2.5 kΩ (cid:129) Conversion Error ≤ 1/2 LSb (cid:129) VDD = 5V → Rss = 7 kΩ (cid:129) Temperature = 50°C (system max.) (cid:129) VHOLD = 0V @ time = 0 EXAMPLE 17-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF Temperature coefficient is only required for temperatures > 25°C. TACQ = 2 μs + TC + [(Temp – 25°C)(0.05 μs/°C)] TC = -CHOLD (RIC + RSS + RS) ln(1/2048) -120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) -120 pF (10.5 kΩ) ln(0.0004883) -1.26 μs (-7.6246) 9.61 μs TACQ = 2 μs + 9.61 μs + [(50°C – 25°C)(0.05 μs/°C)] 11.61 μs + 1.25 μs 12.86 μs © 2006 Microchip Technology Inc. DS39564C-page 185

PIC18FXX2 17.2 Selecting the A/D Conversion Clock 17.3 Configuring Analog Port Pins The A/D conversion time per bit is defined as TAD. The The ADCON1, TRISA and TRISE registers control the A/D conversion requires 12 TAD per 10-bit conversion. operation of the A/D port pins. The port pins that are The source of the A/D conversion clock is software desired as analog inputs, must have their corresponding selectable. The seven possible options for TAD are: TRIS bits set (input). If the TRIS bit is cleared (output), (cid:129) 2 TOSC the digital output level (VOH or VOL) will be converted. (cid:129) 4 TOSC The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. (cid:129) 8 TOSC (cid:129) 16 TOSC Note 1: When reading the port register, all pins con- (cid:129) 32 TOSC figured as analog input channels will read as cleared (a low level). Pins configured as (cid:129) 64 TOSC digital inputs will convert an analog input. (cid:129) Internal A/D module RC oscillator (2-6μs) Analog levels on a digitally configured input For correct A/D conversions, the A/D conversion clock will not affect the conversion accuracy. (TAD) must be selected to ensure a minimum TAD time 2: Analog levels on any pin that is defined as of 1.6 μs. a digital input (including the AN4:AN0 Table17-1 shows the resultant TAD times derived from pins) may cause the input buffer to con- the device operating frequencies and the A/D clock sume current that is out of the device’s source selected. specification. TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18FXX2 PIC18LFXX2 2 TOSC 000 1.25 MHz 666 kHz 4 TOSC 100 2.50 MHz 1.33 MHz 8 TOSC 001 5.00 MHz 2.67 MHz 16 TOSC 101 10.00 MHz 5.33 MHz 32 TOSC 010 20.00 MHz 10.67 MHz 64 TOSC 110 40.00 MHz 21.33 MHz RC 011 — — DS39564C-page 186 © 2006 Microchip Technology Inc.

PIC18FXX2 17.4 A/D Conversions (or the last value written to the ADRESH:ADRESL reg- isters). After the A/D conversion is aborted, a 2 TAD wait Figure17-3 shows the operation of the A/D converter is required before the next acquisition is started. After after the GO bit has been set. Clearing the GO/DONE this 2 TAD wait, acquisition on the selected channel is bit during a conversion will abort the current conver- automatically started. The GO/DONE bit can then be sion. The A/D result register pair will NOT be updated set to start the conversion. with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue Note: The GO/DONE bit should NOT be set in to contain the value of the last completed conversion the same instruction that turns on the A/D. FIGURE 17-3: A/D CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. 17.4.1 A/D RESULT REGISTERS Format Select bit (ADFM) controls this justification. Figure17-4 shows the operation of the A/D result justi- The ADRESH:ADRESL register pair is the location fication. The extra bits are loaded with ’0’s. When an where the 10-bit A/D result is loaded at the completion A/D result will not overwrite these locations (A/D of the A/D conversion. This register pair is 16-bits wide. disable), these registers may be used as two general The A/D module gives the flexibility to left or right justify purpose 8-bit registers. the 10-bit result in the 16-bit result register. The A/D FIGURE 17-4: A/D RESULT JUSTIFICATION 10-bit Result ADFM = 1 ADFM = 0 7 2 1 0 7 0 7 0 7 6 5 0 0000 00 0000 00 ADRESH ADRESL ADRESH ADRESL 10-bit Result 10-bit Result Right Justified Left Justified © 2006 Microchip Technology Inc. DS39564C-page 187

PIC18FXX2 17.5 Use of the CCP2 Trigger (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected An A/D conversion can be started by the “special event and the minimum acquisition done before the “special trigger” of the CCP2 module. This requires that the event trigger” sets the GO/DONE bit (starts a CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- conversion). grammed as 1011 and that the A/D module is enabled If the A/D module is not enabled (ADON is cleared), the (ADON bit is set). When the trigger occurs, the GO/ “special event trigger” will be ignored by the A/D DONE bit will be set, starting the A/D conversion, and module, but will still reset the Timer1 (or Timer3) the Timer1 (or Timer3) counter will be reset to zero. counter. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead TABLE 17-2: SUMMARY OF A/D REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR RESETS INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000 PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000 IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 0000 ADRESH A/D Result Register xxxx xxxx uuuu uuuu ADRESL A/D Result Register xxxx xxxx uuuu uuuu ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 TRISA — PORTA Data Direction Register --11 1111 --11 1111 PORTE — — — — — RE2 RE1 RE0 ---- -000 ---- -000 LATE — — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear. DS39564C-page 188 © 2006 Microchip Technology Inc.

PIC18FXX2 18.0 LOW VOLTAGE DETECT The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be “turned In many applications, the ability to determine if the off” by the software, which minimizes the current device voltage (VDD) is below a specified voltage level consumption for the device. is a desirable feature. A window of operation for the Figure18-1 shows a possible application voltage curve application can be created, where the application soft- (typically for batteries). Over time, the device voltage ware can do “housekeeping tasks” before the device decreases. When the device voltage equals voltage VA, voltage exits the valid operating range. This can be the LVD logic generates an interrupt. This occurs at done using the Low Voltage Detect module. time TA. The application software then has the time, This module is a software programmable circuitry, until the device voltage is no longer in valid operating where a device voltage trip point can be specified. range, to shutdown the system. Voltage point VB is the When the voltage of the device becomes lower then the minimum valid operating voltage specification. This specified point, an interrupt flag is set. If the interrupt is occurs at time TB. The difference TB - TA is the total enabled, the program execution will branch to the inter- time for shutdown. rupt vector address and the software can then respond to that interrupt source. FIGURE 18-1: TYPICAL LOW VOLTAGE DETECT APPLICATION VA VB e g a t Vol Legend: VA = LVD trip point VB = Minimum valid device operating voltage Time TA TB The block diagram for the LVD module is shown in supply voltage is equal to the trip point, the voltage Figure18-2. A comparator uses an internally gener- tapped off of the resistor array is equal to the 1.2V ated reference voltage as the set point. When the internal reference voltage generated by the voltage selected tap output of the device voltage crosses the reference module. The comparator then generates an set point (is lower than), the LVDIF bit is set. interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Each node in the resistor divider represents a “trip Figure18-2). The trip point is selected by point” voltage. The “trip point” voltage is the minimum programming the LVDL3:LVDL0 bits (LVDCON<3:0>). supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the © 2006 Microchip Technology Inc. DS39564C-page 189

PIC18FXX2 FIGURE 18-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM VDD LVDIN LVD Control Register X U M 1 – o LVDIF 6 t + 1 LVDEN Internally Generated Reference Voltage 1.2V Typical The LVD module has an additional feature that allows LVDIN (Figure18-3). This gives users flexibility, the user to supply the trip voltage to the module from because it allows them to configure the Low Voltage an external source. This mode is enabled when bits Detect interrupt to occur at any voltage in the valid LVDL3:LVDL0 are set to 1111. In this state, the com- operating range. parator input is multiplexed from the external input pin, FIGURE 18-3: LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM VDD VDD LVD Control Register LVDIN UX LVDEN Externally Generated M Trip Point o 1 – LVD 6 t + 1 VxEN BODEN EN BGAP DS39564C-page 190 © 2006 Microchip Technology Inc.

PIC18FXX2 18.1 Control Register The Low Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry. REGISTER 18-1: LVDCON REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.5V - 4.77V 1101 = 4.2V - 4.45V 1100 = 4.0V - 4.24V 1011 = 3.8V - 4.03V 1010 = 3.6V - 3.82V 1001 = 3.5V - 3.71V 1000 = 3.3V - 3.50V 0111 = 3.0V - 3.18V 0110 = 2.8V - 2.97V 0101 = 2.7V - 2.86V 0100 = 2.5V - 2.65V 0011 = 2.4V - 2.54V 0010 = 2.2V - 2.33V 0001 = 2.0V - 2.12V 0000 = Reserved Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS39564C-page 191

PIC18FXX2 18.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, 1. Write the value to the LVDL3:LVDL0 bits the voltage normally decreases relatively slowly. This (LVDCON register), which selects the desired means that the LVD module does not need to be con- LVD Trip Point. stantly operating. To decrease the current require- ments, the LVD circuitry only needs to be enabled for 2. Ensure that LVD interrupts are disabled (the short periods, where the voltage is checked. After LVDIE bit is cleared or the GIE bit is cleared). doing the check, the LVD module may be disabled. 3. Enable the LVD module (set the LVDEN bit in the LVDCON register). Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has 4. Wait for the LVD module to stabilize (the IRVST stabilized, all status flags may be cleared. The module bit to become set). will then indicate the proper state of the system. 5. Clear the LVD interrupt flag, which may have falsely become set until the LVD module has stabilized (clear the LVDIF bit). 6. Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure18-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 18-4: LOW VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD VLVD LVDIF Enable LVD Internally Generated TIVRST Reference Stable LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated TIVRST Reference Stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists DS39564C-page 192 © 2006 Microchip Technology Inc.

PIC18FXX2 18.2.1 REFERENCE VOLTAGE SET POINT 18.3 Operation During SLEEP The Internal Reference Voltage of the LVD module may When enabled, the LVD circuitry continues to operate be used by other internal circuitry (the Programmable during SLEEP. If the device voltage crosses the trip Brown-out Reset). If these circuits are disabled (lower point, the LVDIF bit will be set and the device will wake- current consumption), the reference voltage circuit up from SLEEP. Device execution will continue from requires a time to become stable before a low voltage the interrupt vector address if interrupts have been condition can be reliably detected. This time is invariant globally enabled. of system clock speed. This start-up time is specified in electrical specification parameter 36. The low voltage 18.4 Effects of a RESET interrupt flag will not be enabled until a stable reference A device RESET forces all registers to their RESET voltage is reached. Refer to the waveform in Figure18-4. state. This forces the LVD module to be turned off. 18.2.2 CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static cur- rent. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. © 2006 Microchip Technology Inc. DS39564C-page 193

PIC18FXX2 NOTES: DS39564C-page 194 © 2006 Microchip Technology Inc.

PIC18FXX2 19.0 SPECIAL FEATURES OF THE 19.1 Configuration Bits CPU The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various There are several features intended to maximize sys- device configurations. These bits are mapped starting tem reliability, minimize cost through elimination of at program memory location 300000h. external components, provide power saving Operating modes and offer code protection. These are: The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the (cid:129) OSC Selection configuration memory space (300000h - 3FFFFFh), (cid:129) RESET which can only be accessed using Table Reads and - Power-on Reset (POR) Table Writes. - Power-up Timer (PWRT) Programming the configuration registers is done in a - Oscillator Start-up Timer (OST) manner similar to programming the FLASH memory - Brown-out Reset (BOR) (see Section5.5.1). The only difference is the configu- (cid:129) Interrupts ration registers are written a byte at a time. The (cid:129) Watchdog Timer (WDT) sequence of events for programming configuration registers is: (cid:129) SLEEP (cid:129) Code Protection 1. Load table pointer with address of configuration register being written. (cid:129) ID Locations 2. Write a single byte using the TBLWT instruction. (cid:129) In-Circuit Serial Programming 3. Set EEPGD to point to program memory, set the All PIC18FXX2 devices have a Watchdog Timer, which CFGS bit to access configuration registers, and is permanently enabled via the configuration bits or set WREN to enable byte writes. software controlled. It runs off its own RC oscillator for 4. Disable interrupts. added reliability. There are two timers that offer neces- sary delays on power-up. One is the Oscillator Start-up 5. Write 55h to EECON2. Timer (OST), intended to keep the chip in RESET until 6. Write AAh to EECON2. the crystal oscillator is stable. The other is the Power- 7. Set the WR bit. This will begin the write cycle. up Timer (PWRT), which provides a fixed delay on 8. CPU will stall for duration of write (approximately power-up only, designed to keep the part in RESET 2 ms using internal timer). while the power supply stabilizes. With these two tim- 9. Execute a NOP. ers on-chip, most applications need no external 10. Re-enable interrupts. RESET circuitry. SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options. © 2006 Microchip Technology Inc. DS39564C-page 195

PIC18FXX2 TABLE 19-1: CONFIGURATION BITS AND DEVICE IDS Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H — — OSCSEN — — FOSC2 FOSC1 FOSC0 --1- -111 300002h CONFIG2L — — — — BORV1 BORV0 BOREN PWRTEN ---- 1111 300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111 300005h CONFIG3H — — — — — — — CCP2MX ---- ---1 300006h CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1 300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 (1) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0100 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: See Register19-12 for DEVID1 values. REGISTER 19-1: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 300001h) U-0 U-0 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 — — OSCSEN — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator w/ OSC2 configured as RA6 110 = HS oscillator with PLL enabled/Clock frequency = (4 x FOSC) 101 = EC oscillator w/ OSC2 configured as RA6 100 = EC oscillator w/ OSC2 configured as divide-by-4 clock output 011 = RC oscillator 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39564C-page 196 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 19-2: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 19-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state © 2006 Microchip Technology Inc. DS39564C-page 197

PIC18FXX2 REGISTER 19-4: CONFIGURATION REGISTER 3 HIGH (CONFIG3H: BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 — — — — — — — CCP2MX bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 CCP2MX: CCP2 Mux bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 19-5: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 BKBUG — — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug. bit 6-3 Unimplemented: Read as ‘0’ bit 2 LVP: Low Voltage ICSP Enable bit 1 = Low Voltage ICSP enabled 0 = Low Voltage ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack Full/Underflow will cause RESET 0 = Stack Full/Underflow will not cause RESET Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39564C-page 198 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 19-6: CONFIGURATION REGISTER 5 LOW (CONFIG5L: BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) not code protected 0 = Block 3 (006000-007FFFh) code protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code protected 0 = Block 2 (004000-005FFFh) code protected bit 1 CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) not code protected 0 = Block 1 (002000-003FFFh) code protected bit 0 CP0: Code Protection bit 1 = Block 0 (000200-001FFFh) not code protected 0 = Block 0 (000200-001FFFh) code protected Note 1: Unimplemented in PIC18FX42 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 19-7: CONFIGURATION REGISTER 5 HIGH (CONFIG5H: BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code protected 0 = Data EEPROM code protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0001FFh) not code protected 0 = Boot Block (000000-0001FFh) code protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state © 2006 Microchip Technology Inc. DS39564C-page 199

PIC18FXX2 REGISTER 19-8: CONFIGURATION REGISTER 6 LOW (CONFIG6L: BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (006000-007FFFh) not write protected 0 = Block 3 (006000-007FFFh) write protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 (004000-005FFFh) not write protected 0 = Block 2 (004000-005FFFh) write protected bit 1 WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) not write protected 0 = Block 1 (002000-003FFFh) write protected bit 0 WRT0: Write Protection bit 1 = Block 0 (000200h-001FFFh) not write protected 0 = Block 0 (000200h-001FFFh) write protected Note 1: Unimplemented in PIC18FX42 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 19-9: CONFIGURATION REGISTER 6 HIGH (CONFIG6H: BYTE ADDRESS 30000Bh) R/C-1 R/C-1 C-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write protected 0 = Data EEPROM write protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block (000000-0001FFh) not write protected 0 = Boot Block (000000-0001FFh) write protected bit 5 WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write protected 0 = Configuration registers (300000-3000FFh) write protected Note: This bit is read only, and cannot be changed in User mode. bit 4-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C =Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39564C-page 200 © 2006 Microchip Technology Inc.

PIC18FXX2 REGISTER 19-10: CONFIGURATION REGISTER 7 LOW (CONFIG7L: BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (006000-007FFFh) not protected from Table Reads executed in other blocks 0 = Block 3 (006000-007FFFh) protected from Table Reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks 0 = Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks 0 = Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000200h-001FFFh) not protected from Table Reads executed in other blocks 0 = Block 0 (000200h-001FFFh) protected from Table Reads executed in other blocks Note 1: Unimplemented in PIC18FX42 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 19-11: CONFIGURATION REGISTER 7 HIGH (CONFIG7H: BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks 0 = Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C =Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state © 2006 Microchip Technology Inc. DS39564C-page 201

PIC18FXX2 REGISTER 19-12: DEVICE ID REGISTER 1 FOR PIC18FXX2 (DEVID1: BYTE ADDRESS 3FFFFEh) R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F252 001 = PIC18F452 100 = PIC18F242 101 = PIC18F442 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Readable bit P =Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 19-13: DEVICE ID REGISTER 2 FOR PIC18FXX2 (DEVID2: BYTE ADDRESS 3FFFFFh) R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. Legend: R = Readable bit P =Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS39564C-page 202 © 2006 Microchip Technology Inc.

PIC18FXX2 19.2 Watchdog Timer (WDT) The WDT time-out period values may be found in the Electrical Specifications (Section22.0) under parame- The Watchdog Timer is a free running on-chip RC oscil- ter D031. Values for the WDT postscaler may be lator, which does not require any external components. assigned using the configuration bits. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, Note: The CLRWDT and SLEEP instructions clear even if the clock on the OSC1/CLKI and OSC2/CLKO/ the WDT and the postscaler, if assigned to RA6 pins of the device has been stopped, for example, the WDT and prevent it from timing out and by execution of a SLEEP instruction. generating a device RESET condition. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is Note: When a CLRWDT instruction is executed in SLEEP mode, a WDT time-out causes the device to and the postscaler is assigned to the WDT, wake-up and continue with normal operation (Watch- the postscaler count will be cleared, but the dog Timer Wake-up). The TO bit in the RCON register postscaler assignment is not changed. will be cleared upon a WDT time-out. The Watchdog Timer is enabled/disabled by a device 19.2.1 CONTROL REGISTER configuration bit. If the WDT is enabled, software exe- cution may not disable this function. When the WDTEN Register19-14 shows the WDTCON register. This is a configuration bit is cleared, the SWDTEN bit enables/ readable and writable register, which contains a control disables the operation of the WDT. bit that allows software to override the WDT enable configuration bit, only when the configuration bit has disabled the WDT. REGISTER 19-14: WDTCON REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN bit 7 bit 0 bit 7-1 Unimplemented: Read as ’0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR © 2006 Microchip Technology Inc. DS39564C-page 203

PIC18FXX2 19.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming, by the value written to the CONFIG2H configuration register. FIGURE 19-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 8 - to - 1 MUX WDTPS2:WDTPS0 WDTEN SWDTEN bit Configuration bit WDT Time-out Note: WDPS2:WDPS0 are bits in register CONFIG2H. TABLE 19-2: SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG2H — — — — WDTPS2 WDTPS2 WDTPS0 WDTEN RCON IPEN — — RI TO PD POR BOR WDTCON — — — — — — — SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. DS39564C-page 204 © 2006 Microchip Technology Inc.

PIC18FXX2 19.3 Power-down Mode (SLEEP) External MCLR Reset will cause a device RESET. All other events are considered a continuation of program Power-down mode is entered by executing a SLEEP execution and will cause a “wake-up”. The TO and PD instruction. bits in the RCON register can be used to determine the If enabled, the Watchdog Timer will be cleared, but cause of the device RESET. The PD bit, which is set on keeps running, the PD bit (RCON<3>) is cleared, the power-up, is cleared when SLEEP is invoked. The TO TO (RCON<4>) bit is set, and the oscillator driver is bit is cleared, if a WDT time-out occurred (and caused turned off. The I/O ports maintain the status they had wake-up). before the SLEEP instruction was executed (driving When the SLEEP instruction is being executed, the next high, low or hi-impedance). instruction (PC + 2) is pre-fetched. For the device to For lowest current consumption in this mode, place all wake-up through an interrupt event, the corresponding I/O pins at either VDD or VSS, ensure no external cir- interrupt enable bit must be set (enabled). Wake-up is cuitry is drawing current from the I/O pin, power-down regardless of the state of the GIE bit. If the GIE bit is the A/D and disable external clocks. Pull all I/O pins clear (disabled), the device continues execution at the that are hi-impedance inputs, high or low externally, to instruction after the SLEEP instruction. If the GIE bit is avoid switching currents caused by floating inputs. The set (enabled), the device executes the instruction after T0CKI input should also be at VDD or VSS for lowest the SLEEP instruction and then branches to the inter- current consumption. The contribution from on-chip rupt address. In cases where the execution of the pull-ups on PORTB should be considered. instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The MCLR pin must be at a logic high level (VIHMC). 19.3.2 WAKE-UP USING INTERRUPTS 19.3.1 WAKE-UP FROM SLEEP When global interrupts are disabled (GIE cleared) and The device can wake-up from SLEEP through one of any interrupt source has both its interrupt enable bit the following events: and interrupt flag bit set, one of the following will occur: 1. External RESET input on MCLR pin. (cid:129) If an interrupt condition (interrupt flag bit and inter- 2. Watchdog Timer Wake-up (if WDT was rupt enable bits are set) occurs before the execu- enabled). tion of a SLEEP instruction, the SLEEP instruction 3. Interrupt from INT pin, RB port change or a will complete as a NOP. Therefore, the WDT and Peripheral Interrupt. WDT postscaler will not be cleared, the TO bit will The following peripheral interrupts can wake the device not be set and PD bits will not be cleared. from SLEEP: (cid:129) If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device 1. PSP read or write. will immediately wake-up from SLEEP. The 2. TMR1 interrupt. Timer1 must be operating as SLEEP instruction will be completely executed an asynchronous counter. before the wake-up. Therefore, the WDT and 3. TMR3 interrupt. Timer3 must be operating as WDT postscaler will be cleared, the TO bit will be an asynchronous counter. set and the PD bit will be cleared. 4. CCP Capture mode interrupt. Even if the flag bits were checked before executing a 5. Special event trigger (Timer1 in Asynchronous SLEEP instruction, it may be possible for flag bits to mode using an external clock). become set before the SLEEP instruction completes. To 6. MSSP (START/STOP) bit detect interrupt. determine whether a SLEEP instruction executed, test 7. MSSP transmit or receive in Slave mode the PD bit. If the PD bit is set, the SLEEP instruction (SPI/I2C). was executed as a NOP. 8. USART RX or TX (Synchronous Slave mode). To ensure that the WDT is cleared, a CLRWDT instruction 9. A/D conversion (when A/D clock source is RC). should be executed before a SLEEP instruction. 10. EEPROM write operation complete. 11. LVD interrupt. Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. © 2006 Microchip Technology Inc. DS39564C-page 205

PIC18FXX2 FIGURE 19-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKO(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC PC+2 PC+4 PC+4 PC + 4 0008h 000Ah Instruction Fetched Inst(PC) = SLEEP Inst(PC + 2) Inst(PC + 4) Inst(0008h) Inst(000Ah) IEnxsetrcuuctteiodn Inst(PC - 1) SLEEP Inst(PC + 2) Dummy Cycle Dummy Cycle Inst(0008h) Note 1: XT, HS or LP Oscillator mode assumed. 2: GIE = '1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes. 4: CLKO is not available in these Osc modes, but shown here for timing reference. DS39564C-page 206 © 2006 Microchip Technology Inc.

PIC18FXX2 19.4 Program Verification and Each of the five blocks has three code protection bits Code Protection associated with them. They are: (cid:129) Code Protect bit (CPn) The overall structure of the code protection on the (cid:129) Write Protect bit (WRTn) PIC18 FLASH devices differs significantly from other PICmicro devices. (cid:129) External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. Figure19-3 shows the program memory organization One of these is a boot block of 512 bytes. The remain- for 16- and 32-Kbyte devices, and the specific code der of the memory is divided into four blocks on binary protection bit associated with each block. The actual boundaries. locations of the bits are summarized in Table19-3. FIGURE 19-3: CODE PROTECTED PROGRAM MEMORY FOR PIC18F2XX/4XX MEMORY SIZE/DEVICE Block Code Protection 16Kbytes 32Kbytes Address Controlled By: (PIC18FX42) (PIC18FX52) Range 000000h Boot Block Boot Block CPB, WRTB, EBTRB 0001FFh 000200h Block 0 Block 0 CP0, WRT0, EBTR0 001FFFh 002000h Block 1 Block 1 CP1, WRT1, EBTR1 003FFFh 004000h Unimplemented Block 2 CP2, WRT2, EBTR2 Read 0’s 005FFFh 006000h Unimplemented Block 3 CP3, WRT3, EBTR3 Read 0’s 007FFFh 008000h Unimplemented Unimplemented Read 0’s Read 0’s (Unimplemented Memory Space) 1FFFFFh TABLE 19-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. © 2006 Microchip Technology Inc. DS39564C-page 207

PIC18FXX2 19.4.1 PROGRAM MEMORY outside of that block is not allowed to read, and will CODE PROTECTION result in reading ‘0’s. Figures19-4 through19-6 illustrate Table Write and Table Read protection. The user memory may be read to or written from any location using the Table Read and Table Write instruc- tions. The device ID may be read with Table Reads. Note: Code protection bits may only be written to The configuration registers may be read and written a ‘0’ from a ‘1’ state. It is not possible to with the Table Read and Table Write instructions. write a ‘1’ to a bit in the ‘0’ state. Code pro- In User mode, the CPn bits have no direct effect. CPn tection bits are only set to ‘1’ by a full chip bits inhibit external reads and writes. A block of user erase or block erase function. The full chip memory may be protected from Table Writes if the erase and block erase functions can only WRTn configuration bit is ‘0’. The EBTRn bits control be initiated via ICSP or an external Table Reads. For a block of user memory with the programmer. EBTRn bit set to ‘0’, a Table Read instruction that executes from within that block is allowed to read. A Table Read instruction that executes from a location FIGURE 19-4: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB,EBTRB = 11 0001FFh 000200h TBLPTR = 000FFF WRT0,EBTR0 = 01 PC = 001FFE TBLWT * 001FFFh 002000h WRT1,EBTR1 = 11 003FFFh 004000h PC = 004FFE TBLWT * WRT2,EBTR2 = 11 005FFFh 006000h WRT3,EBTR3 = 11 007FFFh Results: All Table Writes disabled to Blockn whenever WRTn = ‘0’. DS39564C-page 208 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 19-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB,EBTRB = 11 0001FFh 000200h TBLPTR = 000FFF WRT0,EBTR0 = 10 001FFFh 002000h PC = 002FFE TBLRD * WRT1,EBTR1 = 11 003FFFh 004000h WRT2,EBTR2 = 11 005FFFh 006000h WRT3,EBTR3 = 11 007FFFh Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = ‘0’. TABLAT register returns a value of “0”. FIGURE 19-6: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB,EBTRB = 11 0001FFh 000200h TBLPTR = 000FFF WRT0,EBTR0 = 10 PC = 001FFE TBLRD * 001FFFh 002000h WRT1,EBTR1 = 11 003FFFh 004000h WRT2,EBTR2 = 11 005FFFh 006000h WRT3,EBTR3 = 11 007FFFh Results: Table Reads permitted within Blockn, even when EBTRBn = ‘0’. TABLAT register returns the value of the data at the location TBLPTR. © 2006 Microchip Technology Inc. DS39564C-page 209

PIC18FXX2 19.4.2 DATA EEPROM To use the In-Circuit Debugger function of the micro- CODE PROTECTION controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, The entire Data EEPROM is protected from external RB7 and RB6. This will interface to the In-Circuit reads and writes by two bits: CPD and WRTD. CPD Debugger module available from Microchip or one of inhibits external reads and writes of Data EEPROM. the third party development tool companies. WRTD inhibits external writes to Data EEPROM. The CPU can continue to read and write Data EEPROM 19.8 Low Voltage ICSP Programming regardless of the protection bit settings. The LVP bit configuration register CONFIG4L enables 19.4.3 CONFIGURATION REGISTER low voltage ICSP programming. This mode allows the PROTECTION microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only The configuration registers can be write protected. The means that VPP does not have to be brought to VIHH, WRTC bit controls protection of the configuration regis- but can instead be left at the normal operating voltage. ters. In User mode, the WRTC bit is readable only. WRTC In this mode, the RB5/PGM pin is dedicated to the pro- can only be written via ICSP or an external programmer. gramming function and ceases to be a general purpose I/O pin. During programming, VDD is applied to the 19.5 ID Locations MCLR/VPP pin. To enter Programming mode, VDD must Eight memory locations (200000h - 200007h) are des- be applied to the RB5/PGM, provided the LVP bit is set. ignated as ID locations, where the user can store The LVP bit defaults to a (‘1’) from the factory. checksum or other code identification numbers. These Note 1: The High Voltage Programming mode is locations are accessible during normal execution always available, regardless of the state through the TBLRD and TBLWT instructions, or during of the LVP bit, by applying VIHH to the program/verify. The ID locations can be read when the MCLR pin. device is code protected. 2: While in low voltage ICSP mode, the RB5 The sequence for programming the ID locations is sim- pin can no longer be used as a general ilar to programming the FLASH memory (see purpose I/O pin, and should be held low Section5.5.1). during normal operation to protect against inadvertent ICSP mode entry. 19.6 In-Circuit Serial Programming 3: When using low voltage ICSP program- PIC18FXXX microcontrollers can be serially pro- ming (LVP), the pull-up on RB5 becomes grammed while in the end application circuit. This is disabled. If TRISB bit 5 is cleared, simply done with two lines for clock and data, and three thereby setting RB5 as an output, LATB other lines for power, ground and the programming bit 5 must also be cleared for proper voltage. This allows customers to manufacture boards operation. with unprogrammed devices, and then program the If Low Voltage Programming mode is not used, the LVP microcontroller just before shipping the product. This bit can be programmed to a '0' and RB5/PGM becomes also allows the most recent firmware or a custom a digital I/O pin. However, the LVP bit may only be pro- firmware to be programmed. grammed when programming is entered with VIHH on 19.7 In-Circuit Debugger MCLR/VPP. It should be noted that once the LVP bit is programmed When the DEBUG bit in configuration register to 0, only the High Voltage Programming mode is avail- CONFIG4L is programmed to a '0', the In-Circuit able and only High Voltage Programming mode can be Debugger functionality is enabled. This function allows used to program the device. simple debugging functions when used with MPLAB® When using low voltage ICSP, the part must be sup- IDE. When the microcontroller has this feature plied 4.5V to 5.5V, if a bulk erase will be executed. This enabled, some of the resources are not available for includes reprogramming of the code protect bits from general use. Table19-4 shows which features are an on-state to off-state. For all other cases of low volt- consumed by the background debugger. age ICSP, the part may be programmed at the normal TABLE 19-4: DEBUGGER RESOURCES operating voltage. This means unique user IDs, or user code can be reprogrammed or added. I/O pins RB6, RB7 Stack 2 levels Program Memory 512 bytes Data Memory 10 bytes DS39564C-page 210 © 2006 Microchip Technology Inc.

PIC18FXX2 20.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18FXXX instruction set adds many enhance- (cid:129) A literal value to be loaded into a file register ments to the previous PICmicro instruction sets, while (specified by ‘k’) maintaining an easy migration from these PICmicro instruction sets. (cid:129) The desired FSR register to load the literal value into (specified by ‘f’) Most instructions are a single program memory word (cid:129) No operand required (16-bits), but there are three instructions that require (specified by ‘—’) two program memory locations. The control instructions may use some of the following Each single word instruction is a 16-bit word divided operands: into an OPCODE, which specifies the instruction type and one or more operands, which further specify the (cid:129) A program memory address (specified by ‘n’) operation of the instruction. (cid:129) The mode of the Call or Return instructions The instruction set is highly orthogonal and is grouped (specified by ‘s’) into four basic categories: (cid:129) The mode of the Table Read and Table Write instructions (specified by ‘m’) (cid:129) Byte-oriented operations (cid:129) No operand required (cid:129) Bit-oriented operations (specified by ‘—’) (cid:129) Literal operations All instructions are a single word, except for three dou- (cid:129) Control operations ble-word instructions. These three instructions were The PIC18FXXX instruction set summary in Table20-2 made double-word instructions so that all the required lists byte-oriented, bit-oriented, literal and control information is available in these 32 bits. In the second operations. Table20-1 shows the opcode field word, the 4-MSbs are 1’s. If this second word is exe- descriptions. cuted as an instruction (by itself), it will execute as a Most byte-oriented instructions have three operands: NOP. 1. The file register (specified by ‘f’) All single word instructions are executed in a single instruction cycle, unless a conditional test is true or the 2. The destination of the result program counter is changed as a result of the instruc- (specified by ‘d’) tion. In these cases, the execution takes two instruction 3. The accessed memory cycles with the additional instruction cycle(s) executed (specified by ‘a’) as a NOP. The file register designator 'f' specifies which file The double-word instructions execute in two instruction register is to be used by the instruction. cycles. The destination designator ‘d’ specifies where the One instruction cycle consists of four oscillator periods. result of the operation is to be placed. If 'd' is zero, the Thus, for an oscillator frequency of 4 MHz, the normal result is placed in the WREG register. If 'd' is one, the instruction execution time is 1 μs. If a conditional test is result is placed in the file register specified in the true or the program counter is changed as a result of an instruction. instruction, the instruction execution time is 2 μs. All bit-oriented instructions have three operands: Two-word branch instructions (if true) would take 3 μs. 1. The file register (specified by ‘f’) Figure20-1 shows the general formats that the 2. The bit in the file register instructions can have. (specified by ‘b’) All examples use the format ‘nnh’ to represent a 3. The accessed memory hexadecimal number, where ‘h’ signifies a (specified by ‘a’) hexadecimal digit. The bit field designator 'b' selects the number of the bit The Instruction Set Summary, shown in Table20-2, affected by the operation, while the file register desig- lists the instructions recognized by the Microchip nator 'f' represents the number of the file in which the Assembler (MPASMTM). bit is located. Section20.1 provides a description of each instruction. © 2006 Microchip Technology Inc. DS39564C-page 211

PIC18FXX2 TABLE 20-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7) BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit; d = 0: store result in WREG, d = 1: store result in file register f. dest Destination either the WREG register or the specified register file location f 8-bit Register file address (0x00 to 0xFF) fs 12-bit Register file address (0x000 to 0xFFF). This is the source address. fd 12-bit Register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label Label name mm The mode of the TBLPTR register for the Table Read and Table Write instructions. Only used with Table Read and Table Write instructions: * No Change to register (such as TBLPTR with Table reads and writes) *+ Post-Increment register (such as TBLPTR with Table reads and writes) *- Post-Decrement register (such as TBLPTR with Table reads and writes) +* Pre-Increment register (such as TBLPTR with Table reads and writes) n The relative address (2’s complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions PRODH Product of Multiply high byte PRODL Product of Multiply low byte s Fast Call/Return mode select bit. s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or Unchanged WREG Working register (accumulator) x Don't care (0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location) TABLAT 8-bit Table Latch TOS Top-of-Stack PC Program Counter PCL Program Counter Low Byte PCH Program Counter High Byte PCLATH Program Counter High Byte Latch PCLATU Program Counter Upper Byte Latch GIE Global Interrupt Enable bit WDT Watchdog Timer TO Time-out bit PD Power-down bit C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative [ ] Optional ( ) Contents → Assigned to < > Register bit field ∈ In the set of italics User defined term (font is courier) DS39564C-page 212 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 0x7F k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2006 Microchip Technology Inc. DS39564C-page 213

PIC18FXX2 TABLE 20-2: PIC18FXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da0 ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 0da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF f , f Move f (source) to 1st word 2 1100 ffff ffff ffff None s d s f (destination) 2nd word 1111 ffff ffff ffff d MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N 1, 2 RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N 1, 2 RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N 1, 2 borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N 1, 2 borrow SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. DS39564C-page 214 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 2 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 1 (2) 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call subroutine1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to address1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device RESET 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. © 2006 Microchip Technology Inc. DS39564C-page 215

PIC18FXX2 TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSRx 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated. DS39564C-page 216 © 2006 Microchip Technology Inc.

PIC18FXX2 20.1 Instruction Set ADDLW ADD literal to W ADDWF ADD W to f Syntax: [ label ] ADDLW k Syntax: [ label ] ADDWF f [,d [,a] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: (W) + k → W d ∈ [0,1] a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the 8-bit literal 'k' and the result is Encoding: 0010 01da ffff ffff placed in W. Description: Add W to register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the Words: 1 result is stored back in register 'f' Cycles: 1 (default). If ‘a’ is 0, the Access Q Cycle Activity: Bank will be selected. If ‘a’ is 1, the Q1 Q2 Q3 Q4 BSR is used. Decode Read Process Write to W Words: 1 literal 'k' Data Cycles: 1 Q Cycle Activity: Example: ADDLW 0x15 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write to W = 0x10 register 'f' Data destination After Instruction W = 0x25 Example: ADDWF REG, 0, 0 Before Instruction W = 0x17 REG = 0xC2 After Instruction W = 0xD9 REG = 0xC2 © 2006 Microchip Technology Inc. DS39564C-page 217

PIC18FXX2 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: [ label ] ADDWFC f [,d [,a] Syntax: [ label ] ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N,Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with Encoding: 0010 00da ffff ffff the 8-bit literal 'k'. The result is Description: Add W, the Carry Flag and data placed in W. memory location 'f'. If 'd' is 0, the Words: 1 result is placed in W. If 'd' is 1, the result is placed in data memory loca- Cycles: 1 tion 'f'. If ‘a’ is 0, the Access Bank Q Cycle Activity: will be selected. If ‘a’ is 1, the BSR Q1 Q2 Q3 Q4 will not be overridden. Decode Read literal Process Write to W Words: 1 'k' Data Cycles: 1 Example: ANDLW 0x5F Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 Decode Read Process Write to W = 0xA3 register 'f' Data destination After Instruction W = 0x03 Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 0x02 W = 0x4D After Instruction Carry bit = 0 REG = 0x02 W = 0x50 DS39564C-page 218 © 2006 Microchip Technology Inc.

PIC18FXX2 ANDWF AND W with f BC Branch if Carry Syntax: [ label ] ANDWF f [,d [,a] Syntax: [ label ] BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if carry bit is ’1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N,Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the Description: The contents of W are AND’ed with program will branch. register 'f'. If 'd' is 0, the result is The 2’s complement number ’2n’ is stored in W. If 'd' is 1, the result is added to the PC. Since the PC will stored back in register 'f' (default). If have incremented to fetch the next ‘a’ is 0, the Access Bank will be instruction, the new address will be selected. If ‘a’ is 1, the BSR will not PC+2+2n. This instruction is then be overridden (default). a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 If Jump: Decode Read Process Write to Q1 Q2 Q3 Q4 register 'f' Data destination Decode Read literal Process Write to PC 'n' Data Example: ANDWF REG, 0, 0 No No No No operation operation operation operation Before Instruction If No Jump: W = 0x17 Q1 Q2 Q3 Q4 REG = 0xC2 After Instruction Decode Read literal Process No 'n' Data operation W = 0x02 REG = 0xC2 Example: HERE BC 5 Before Instruction PC = address (HERE) After Instruction If Carry = 1; PC = address (HERE+12) If Carry = 0; PC = address (HERE+2) © 2006 Microchip Technology Inc. DS39564C-page 219

PIC18FXX2 BCF Bit Clear f BN Branch if Negative Syntax: [ label ] BCF f,b[,a] Syntax: [ label ] BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if negative bit is ’1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ’1’, then the Description: Bit 'b' in register 'f' is cleared. If ‘a’ program will branch. is 0, the Access Bank will be The 2’s complement number ’2n’ is selected, overriding the BSR value. added to the PC. Since the PC will If ‘a’ = 1, then the bank will be have incremented to fetch the next selected as per the BSR value instruction, the new address will be (default). PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: If Jump: Decode Read Process Write register 'f' Data register 'f' Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Example: BCF FLAG_REG, 7, 0 'n' Data No No No No Before Instruction operation operation operation operation FLAG_REG = 0xC7 If No Jump: After Instruction Q1 Q2 Q3 Q4 FLAG_REG = 0x47 Decode Read literal Process No 'n' Data operation Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE+2) DS39564C-page 220 © 2006 Microchip Technology Inc.

PIC18FXX2 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC n Syntax: [ label ] BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if carry bit is ’0’ Operation: if negative bit is ’0’ (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ’0’, then the Description: If the Negative bit is ’0’, then the program will branch. program will branch. The 2’s complement number ’2n’ is The 2’s complement number ’2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then PC+2+2n. This instruction is then a two-cycle instruction. a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC 'n' Data 'n' Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No 'n' Data operation 'n' Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE+2) PC = address (HERE+2) © 2006 Microchip Technology Inc. DS39564C-page 221

PIC18FXX2 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV n Syntax: [ label ] BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if overflow bit is ’0’ Operation: if zero bit is ’0’ (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ’0’, then the Description: If the Zero bit is ’0’, then the pro- program will branch. gram will branch. The 2’s complement number ’2n’ is The 2’s complement number ’2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then PC+2+2n. This instruction is then a two-cycle instruction. a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC 'n' Data 'n' Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No 'n' Data operation 'n' Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE+2) PC = address (HERE+2) DS39564C-page 222 © 2006 Microchip Technology Inc.

PIC18FXX2 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA n Syntax: [ label ] BSF f,b[,a] Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 Operation: (PC) + 2 + 2n → PC 0 ≤ b ≤ 7 a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number Encoding: 1000 bbba ffff ffff ’2n’ to the PC. Since the PC will have incremented to fetch the next Description: Bit 'b' in register 'f' is set. If ‘a’ is 0 instruction, the new address will be Access Bank will be selected, over- PC+2+2n. This instruction is a riding the BSR value. If ‘a’ = 1, then two-cycle instruction. the bank will be selected as per the BSR value. Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process Write to PC Q1 Q2 Q3 Q4 'n' Data Decode Read Process Write No No No No register 'f' Data register 'f' operation operation operation operation Example: BSF FLAG_REG, 7, 1 Example: HERE BRA Jump Before Instruction FLAG_REG = 0x0A Before Instruction After Instruction PC = address (HERE) FLAG_REG = 0x8A After Instruction PC = address (Jump) © 2006 Microchip Technology Inc. DS39564C-page 223

PIC18FXX2 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b ≤ 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit 'b' in register ’f' is 0, then the Description: If bit 'b' in register 'f' is 1, then the next instruction is skipped. next instruction is skipped. If bit 'b' is 0, then the next instruction If bit 'b' is 1, then the next instruction fetched during the current instruction fetched during the current instruc- execution is discarded, and a NOP is tion execution, is discarded and a executed instead, making this a two- NOP is executed instead, making this cycle instruction. If ‘a’ is 0, the a two-cycle instruction. If ‘a’ is 0, the Access Bank will be selected, over- Access Bank will be selected, over- riding the BSR value. If ‘a’ = 1, then riding the BSR value. If ‘a’ = 1, then the bank will be selected as per the the bank will be selected as per the BSR value (default). BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Data No Decode Read Process Data No register 'f' operation register 'f' operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39564C-page 224 © 2006 Microchip Technology Inc.

PIC18FXX2 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if overflow bit is ’1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ’1’, then the Description: Bit 'b' in data memory location 'f' is program will branch. inverted. If ‘a’ is 0, the Access Bank The 2’s complement number ’2n’ is will be selected, overriding the BSR added to the PC. Since the PC will value. If ‘a’ = 1, then the bank will be have incremented to fetch the next selected as per the BSR value instruction, the new address will be (default). PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: If Jump: Decode Read Process Write register 'f' Data register 'f' Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Example: BTG PORTC, 4, 0 'n' Data No No No No Before Instruction: operation operation operation operation PORTC = 0111 0101 [0x75] If No Jump: After Instruction: PORTC = 0110 0101 [0x65] Q1 Q2 Q3 Q4 Decode Read literal Process No 'n' Data operation Example: HERE BOV Jump Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE+2) © 2006 Microchip Technology Inc. DS39564C-page 225

PIC18FXX2 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ n Syntax: [ label ] CALL k [,s] Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ’1’ (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ’1’, then the pro- (STATUS) → STATUSS, gram will branch. (BSR) → BSRS The 2’s complement number ’2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 PC+2+2n. This instruction is then 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 a two-cycle instruction. Description: Subroutine call of entire 2 Mbyte memory range. First, return Words: 1 address (PC+ 4) is pushed onto the Cycles: 1(2) return stack. If ’s’ = 1, the W, Q Cycle Activity: STATUS and BSR registers are If Jump: also pushed into their respective shadow registers, WS, STATUSS Q1 Q2 Q3 Q4 and BSRS. If 's' = 0, no update Decode Read literal Process Write to PC occurs (default). Then, the 20-bit 'n' Data value ’k’ is loaded into PC<20:1>. No No No No CALL is a two-cycle instruction. operation operation operation operation If No Jump: Words: 2 Q1 Q2 Q3 Q4 Cycles: 2 Decode Read literal Process No Q Cycle Activity: 'n' Data operation Q1 Q2 Q3 Q4 Decode Read literal Push PC to Read literal Example: HERE BZ Jump 'k'<7:0>, stack ’k’<19:8>, Before Instruction Write to PC PC = address (HERE) No No No No operation operation operation operation After Instruction If Zero = 1; PC = address (Jump) Example: HERE CALL THERE,1 If Zero = 0; PC = address (HERE+2) Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39564C-page 226 © 2006 Microchip Technology Inc.

PIC18FXX2 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRF f [,a] Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. If ‘a’ is 0, the Access Bank Description: CLRWDT instruction resets the will be selected, overriding the BSR Watchdog Timer. It also resets the value. If ‘a’ = 1, then the bank will postscaler of the WDT. Status bits be selected as per the BSR value TO and PD are set. (default). Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode No Process No Decode Read Process Write operation Data operation register 'f' Data register 'f' Example: CLRWDT Example: CLRF FLAG_REG,1 Before Instruction Before Instruction WDT Counter = ? FLAG_REG = 0x5A After Instruction After Instruction WDT Counter = 0x00 FLAG_REG = 0x00 WDT Postscaler = 0 TO = 1 PD = 1 © 2006 Microchip Technology Inc. DS39564C-page 227

PIC18FXX2 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: [ label ] COMF f [,d [,a] Syntax: [ label ] CPFSEQ f [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), Operation: (f) → dest skip if (f) = (W) (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register 'f' are com- plemented. If 'd' is 0, the result is Description: Compares the contents of data stored in W. If 'd' is 1, the result is memory location 'f' to the contents stored back in register 'f' (default). If of W by performing an unsigned ‘a’ is 0, the Access Bank will be subtraction. selected, overriding the BSR value. If 'f' = W, then the fetched instruc- If ‘a’ = 1, then the bank will be tion is discarded and a NOP is exe- selected as per the BSR value cuted instead, making this a two- (default). cycle instruction. If ‘a’ is 0, the Access Bank will be selected, over- Words: 1 riding the BSR value. If ‘a’ = 1, then Cycles: 1 the bank will be selected as per the Q Cycle Activity: BSR value (default). Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1(2) register 'f' Data destination Note: 3 cycles if skip and followed Example: COMF REG, 0, 0 by a 2-word instruction. Before Instruction Q Cycle Activity: REG = 0x13 Q1 Q2 Q3 Q4 After Instruction Decode Read Process No REG = 0x13 register 'f' Data operation W = 0xEC If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39564C-page 228 © 2006 Microchip Technology Inc.

PIC18FXX2 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSGT f [,a] Syntax: [ label ] CPFSLT f [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) − (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data Description: Compares the contents of data memory location 'f' to the contents memory location 'f' to the contents of the W by performing an of W by performing an unsigned unsigned subtraction. subtraction. If the contents of 'f' are greater than If the contents of 'f' are less than the contents of WREG, then the the contents of W, then the fetched fetched instruction is discarded and instruction is discarded and a NOP a NOP is executed instead, making is executed instead, making this a this a two-cycle instruction. If ‘a’ is two-cycle instruction. If ‘a’ is 0, the 0, the Access Bank will be Access Bank will be selected. If ’a’ selected, overriding the BSR value. is 1, the BSR will not be overridden If ‘a’ = 1, then the bank will be (default). selected as per the BSR value Words: 1 (default). Cycles: 1(2) Words: 1 Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed Q Cycle Activity: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process No Q1 Q2 Q3 Q4 register 'f' Data operation Decode Read Process No If skip: register 'f' Data operation Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSLT REG, 1 NLESS : Example: HERE CPFSGT REG, 0 LESS : NGREATER : Before Instruction GREATER : PC = Address (HERE) Before Instruction W = ? PC = Address (HERE) After Instruction W = ? If REG < W; After Instruction PC = Address (LESS) If REG ≥ W; If REG > W; PC = Address (NLESS) PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2006 Microchip Technology Inc. DS39564C-page 229

PIC18FXX2 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a] Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 → W<3:0>; a ∈ [0,1] else Operation: (f) – 1 → dest (W<3:0>) → W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> >9] or [C = 1] then Encoding: 0000 01da ffff ffff (W<7:4>) + 6 → W<7:4>; Description: Decrement register 'f'. If 'd' is 0, the else result is stored in W. If 'd' is 1, the (W<7:4>) → W<7:4>; result is stored back in register 'f' Status Affected: C (default). If ’a’ is 0, the Access Bank will be selected, overriding Encoding: 0000 0000 0000 0111 the BSR value. If ’a’ = 1, then the Description: DAW adjusts the eight-bit value in bank will be selected as per the W, resulting from the earlier addi- BSR value (default). tion of two variables (each in Words: 1 packed BCD format) and produces a correct packed BCD result. Cycles: 1 Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to Q Cycle Activity: register 'f' Data destination Q1 Q2 Q3 Q4 Decode Read Process Write Example: DECF CNT, 1, 0 register W Data W Before Instruction Example1: DAW CNT = 0x01 Before Instruction Z = 0 After Instruction W = 0xA5 C = 0 CNT = 0x00 DC = 0 Z = 1 After Instruction W = 0x05 C = 1 DC = 0 Example 2: Before Instruction W = 0xCE C = 0 DC = 0 After Instruction W = 0x34 C = 1 DC = 0 DS39564C-page 230 © 2006 Microchip Technology Inc.

PIC18FXX2 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ f [,d [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register 'f' are dec- Description: The contents of register 'f' are dec- remented. If 'd' is 0, the result is remented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). placed back in register 'f' (default). If the result is 0, the next instruc- If the result is not 0, the next tion, which is already fetched, is instruction, which is already discarded, and a NOP is executed fetched, is discarded, and a NOP is instead, making it a two-cycle executed instead, making it a two- instruction. If ’a’ is 0, the Access cycle instruction. If ’a’ is 0, the Bank will be selected, overriding Access Bank will be selected, the BSR value. If ’a’ = 1, then the overriding the BSR value. If ’a’ = 1, bank will be selected as per the then the bank will be selected as BSR value (default). per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register 'f' Data destination register 'f' Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 Example: HERE DCFSNZ TEMP, 1, 0 GOTO LOOP ZERO : CONTINUE NZERO : Before Instruction Before Instruction PC = Address (HERE) TEMP = ? After Instruction After Instruction CNT = CNT - 1 TEMP = TEMP - 1, If CNT = 0; If TEMP = 0; PC = Address (CONTINUE) PC = Address (ZERO) If CNT ≠ 0; If TEMP ≠ 0; PC = Address (HERE+2) PC = Address (NZERO) © 2006 Microchip Technology Inc. DS39564C-page 231

PIC18FXX2 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] GOTO k Syntax: [ label ] INCF f [,d [,a] Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 Operation: k → PC<20:1> d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff Description: GOTO allows an unconditional Description: The contents of register 'f' are branch anywhere within entire incremented. If 'd' is 0, the result is 2 Mbyte memory range. The 20-bit placed in W. If 'd' is 1, the result is value ’k’ is loaded into PC<20:1>. placed back in register 'f' (default). GOTO is always a two-cycle If ’a’ is 0, the Access Bank will be instruction. selected, overriding the BSR value. If ’a’ = 1, then the bank will be Words: 2 selected as per the BSR value Cycles: 2 (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal No Read literal Q Cycle Activity: 'k'<7:0>, operation ’k’<19:8>, Write to PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write to operation operation operation operation register 'f' Data destination Example: GOTO THERE Example: INCF CNT, 1, 0 After Instruction Before Instruction PC = Address (THERE) CNT = 0xFF Z = 0 C = ? DC = ? After Instruction CNT = 0x00 Z = 1 C = 1 DC = 1 DS39564C-page 232 © 2006 Microchip Technology Inc.

PIC18FXX2 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] INCFSZ f [,d [,a] Syntax: [ label ] INFSNZ f [,d [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 11da ffff ffff Encoding: 0100 10da ffff ffff Description: The contents of register 'f' are Description: The contents of register 'f' are incremented. If 'd' is 0, the result is incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed in W. If 'd' is 1, the result is placed back in register 'f'. (default) placed back in register 'f' (default). If the result is 0, the next instruc- If the result is not 0, the next tion, which is already fetched, is instruction, which is already discarded, and a NOP is executed fetched, is discarded, and a NOP is instead, making it a two-cycle executed instead, making it a two- instruction. If ’a’ is 0, the Access cycle instruction. If ’a’ is 0, the Bank will be selected, overriding Access Bank will be selected, over- the BSR value. If ’a’ = 1, then the riding the BSR value. If ’a’ = 1, then bank will be selected as per the the bank will be selected as per the BSR value (default). BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register 'f' Data destination register 'f' Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2006 Microchip Technology Inc. DS39564C-page 233

PIC18FXX2 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: [ label ] IORLW k Syntax: [ label ] IORWF f [,d [,a] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: (W) .OR. k → W d ∈ [0,1] a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are OR’ed with Encoding: 0001 00da ffff ffff the eight-bit literal 'k'. The result is placed in W. Description: Inclusive OR W with register 'f'. If 'd' is 0, the result is placed in W. If 'd' Words: 1 is 1, the result is placed back in Cycles: 1 register 'f' (default). If ’a’ is 0, the Q Cycle Activity: Access Bank will be selected, over- Q1 Q2 Q3 Q4 riding the BSR value. If ’a’ = 1, then the bank will be selected as per the Decode Read Process Write to W BSR value (default). literal 'k' Data Words: 1 Example: IORLW 0x35 Cycles: 1 Before Instruction Q Cycle Activity: W = 0x9A Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to register 'f' Data destination W = 0xBF Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 DS39564C-page 234 © 2006 Microchip Technology Inc.

PIC18FXX2 LFSR Load FSR MOVF Move f Syntax: [ label ] LFSR f,k Syntax: [ label ] MOVF f [,d [,a] Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] Operation: k → FSRf a ∈ [0,1] Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff Description: The 12-bit literal 'k' is loaded into Description: The contents of register 'f' are the file select register pointed to moved to a destination dependent by 'f'. upon the status of ’d’. If 'd' is 0, the Words: 2 result is placed in W. If 'd' is 1, the result is placed back in register 'f' Cycles: 2 (default). Location 'f' can be any- Q Cycle Activity: where in the 256 byte bank. If ’a’ is Q1 Q2 Q3 Q4 0, the Access Bank will be selected, overriding the BSR value. Decode Read literal Process Write 'k' MSB Data literal 'k' If ‘a’ = 1, then the bank will be MSB to selected as per the BSR value FSRfH (default). Decode Read literal Process Write literal Words: 1 'k' LSB Data 'k' to FSRfL Cycles: 1 Example: LFSR 2, 0x3AB Q Cycle Activity: Q1 Q2 Q3 Q4 After Instruction FSR2H = 0x03 Decode Read Process Write W FSR2L = 0xAB register 'f' Data Example: MOVF REG, 0, 0 Before Instruction REG = 0x22 W = 0xFF After Instruction REG = 0x22 W = 0x22 © 2006 Microchip Technology Inc. DS39564C-page 235

PIC18FXX2 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] MOVFF f ,f Syntax: [ label ] MOVLB k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ fd ≤ 4095 Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The 8-bit literal 'k' is loaded into 1st word (source) 1100 ffff ffff ffffs the Bank Select Register (BSR). 2nd word (destin.) 1111 ffff ffff ffffd Words: 1 Description: The contents of source register 'f ' s are moved to destination register Cycles: 1 'fd'. Location of source 'fs' can be Q Cycle Activity: anywhere in the 4096 byte data Q1 Q2 Q3 Q4 space (000h to FFFh), and location Decode Read literal Process Write of destination 'f ' can also be any- d 'k' Data literal 'k' to where from 000h to FFFh. BSR Either source or destination can be W (a useful special situation). Example: MOVLB 5 MOVFF is particularly useful for transferring a data memory location Before Instruction to a peripheral register (such as the BSR register = 0x02 transmit buffer or an I/O port). After Instruction BSR register = 0x05 The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Note: The MOVFF instruction should not be used to mod- ify interrupt settings while any interrupt is enabled. See Section8.0 for more information. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register 'f' Data operation (src) Decode No No Write operation operation register 'f' No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 0x33 REG2 = 0x11 After Instruction REG1 = 0x33, REG2 = 0x33 DS39564C-page 236 © 2006 Microchip Technology Inc.

PIC18FXX2 MOVLW Move literal to W MOVWF Move W to f Syntax: [ label ] MOVLW k Syntax: [ label ] MOVWF f [,a] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: k → W a ∈ [0,1] Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal 'k' is loaded into W. Description: Move data from W to register 'f'. Location 'f' can be anywhere in the Words: 1 256 byte bank. If ‘a’ is 0, the Cycles: 1 Access Bank will be selected, over- Q Cycle Activity: riding the BSR value. If ‘a’ = 1, then the bank will be selected as per the Q1 Q2 Q3 Q4 BSR value (default). Decode Read Process Write to W literal 'k' Data Words: 1 Cycles: 1 Example: MOVLW 0x5A Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = 0x5A Decode Read Process Write register 'f' Data register 'f' Example: MOVWF REG, 0 Before Instruction W = 0x4F REG = 0xFF After Instruction W = 0x4F REG = 0x4F © 2006 Microchip Technology Inc. DS39564C-page 237

PIC18FXX2 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] MULLW k Syntax: [ label ] MULWF f [,a] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: (W) x k → PRODH:PRODL a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is car- ried out between the contents of Description: An unsigned multiplication is car- W and the 8-bit literal 'k'. The ried out between the contents of 16-bit result is placed in W and the register file location 'f'. PRODH:PRODL register pair. The 16-bit result is stored in the PRODH contains the high byte. PRODH:PRODL register pair. W is unchanged. PRODH contains the high byte. None of the status flags are Both W and 'f' are unchanged. affected. None of the status flags are Note that neither overflow nor affected. carry is possible in this opera- Note that neither overflow nor tion. A zero result is possible but carry is possible in this opera- not detected. tion. A zero result is possible but not detected. If ‘a’ is 0, the Words: 1 Access Bank will be selected, Cycles: 1 overriding the BSR value. If Q Cycle Activity: ‘a’ = 1, then the bank will be selected as per the BSR value Q1 Q2 Q3 Q4 (default). Decode Read Process Write literal 'k' Data registers Words: 1 PRODH: Cycles: 1 PRODL Q Cycle Activity: Example: MULLW 0xC4 Q1 Q2 Q3 Q4 Decode Read Process Write Before Instruction register 'f' Data registers W = 0xE2 PRODH: PRODH = ? PRODL PRODL = ? After Instruction Example: MULWF REG, 1 W = 0xE2 PRODH = 0xAD Before Instruction PRODL = 0x08 W = 0xC4 REG = 0xB5 PRODH = ? PRODL = ? After Instruction W = 0xC4 REG = 0xB5 PRODH = 0x8A PRODL = 0x94 DS39564C-page 238 © 2006 Microchip Technology Inc.

PIC18FXX2 NEGF Negate f NOP No Operation Syntax: [ label ] NEGF f [,a] Syntax: [ label ] NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in Words: 1 the data memory location 'f'. If ’a’ is Cycles: 1 0, the Access Bank will be selected, overriding the BSR value. Q Cycle Activity: If ’a’ = 1, then the bank will be Q1 Q2 Q3 Q4 selected as per the BSR value. Decode No No No Words: 1 operation operation operation Cycles: 1 Example: Q Cycle Activity: Q1 Q2 Q3 Q4 None. Decode Read Process Write register 'f' Data register 'f' Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [0x3A] After Instruction REG = 1100 0110 [0xC6] © 2006 Microchip Technology Inc. DS39564C-page 239

PIC18FXX2 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] POP Syntax: [ label ] PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC+2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the Description: The PC+2 is pushed onto the top of return stack and is discarded. The the return stack. The previous TOS TOS value then becomes the previ- value is pushed down on the stack. ous value that was pushed onto the This instruction allows to implement return stack. a software stack by modifying TOS, This instruction is provided to and then push it onto the return enable the user to properly manage stack. the return stack to incorporate a Words: 1 software stack. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode PUSH PC+2 No No Q1 Q2 Q3 Q4 onto return operation operation Decode No POP TOS No stack operation value operation Example: PUSH Example: POP Before Instruction GOTO NEW TOS = 00345Ah Before Instruction PC = 000124h TOS = 0031A2h Stack (1 level down) = 014332h After Instruction PC = 000126h After Instruction TOS = 000126h Stack (1 level down) = 00345Ah TOS = 014332h PC = NEW DS39564C-page 240 © 2006 Microchip Technology Inc.

PIC18FXX2 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL n Syntax: [ label ] RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that (PC) + 2 + 2n → PC are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to Description: This instruction provides a way to 1K from the current location. First, execute a MCLR Reset in software. return address (PC+2) is pushed Words: 1 onto the stack. Then, add the 2’s complement number ’2n’ to the PC. Cycles: 1 Since the PC will have incremented Q Cycle Activity: to fetch the next instruction, the Q1 Q2 Q3 Q4 new address will be PC+2+2n. Decode Start No No This instruction is a two-cycle reset operation operation instruction. Words: 1 Example: RESET Cycles: 2 After Instruction Q Cycle Activity: Registers= Reset Value Flags* = Reset Value Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC 'n' Data Push PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE+2) © 2006 Microchip Technology Inc. DS39564C-page 241

PIC18FXX2 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] RETFIE [s] Syntax: [ label ] RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL, (TOS) → PC, if s = 1 PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged. Description: W is loaded with the eight-bit literal 'k'. The program counter is loaded Status Affected: GIE/GIEH, PEIE/GIEL. from the top of the stack (the return Encoding: 0000 0000 0001 000s address). The high address latch Description: Return from Interrupt. Stack is (PCLATH) remains unchanged. popped and Top-of-Stack (TOS) is Words: 1 loaded into the PC. Interrupts are enabled by setting either the high Cycles: 2 or low priority global interrupt Q Cycle Activity: enable bit. If ‘s’ = 1, the contents of Q1 Q2 Q3 Q4 the shadow registers WS, Decode Read Process pop PC from STATUSS and BSRS are loaded literal 'k' Data stack, Write into their corresponding registers, to W W, STATUS and BSR. If ‘s’ = 0, no No No No No update of these registers occurs operation operation operation operation (default). Words: 1 Example: Cycles: 2 CALL TABLE ; W contains table Q Cycle Activity: ; offset value Q1 Q2 Q3 Q4 ; W now has Decode No No pop PC from ; table value operation operation stack : TABLE Set GIEH or ADDWF PCL ; W = offset GIEL RETLW k0 ; Begin table No No No No RETLW k1 ; operation operation operation operation : : Example: RETFIE 1 RETLW kn ; End of table After Interrupt PC = TOS Before Instruction W = WS W = 0x07 BSR = BSRS STATUS = STATUSS After Instruction GIE/GIEH, PEIE/GIEL = 1 W = value of kn DS39564C-page 242 © 2006 Microchip Technology Inc.

PIC18FXX2 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] RETURN [s] Syntax: [ label ] RLCF f [,d [,a] Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 Operation: (TOS) → PC, d ∈ [0,1] a ∈ [0,1] if s = 1 (WS) → W, Operation: (f<n>) → dest<n+1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register 'f' are Description: Return from subroutine. The stack rotated one bit to the left through is popped and the top of the stack the Carry Flag. If 'd' is 0, the result (TOS) is loaded into the program is placed in W. If 'd' is 1, the result counter. If ‘s’= 1, the contents of the is stored back in register 'f' shadow registers WS, STATUSS (default). If ‘a’ is 0, the Access and BSRS are loaded into their cor- Bank will be selected, overriding responding registers, W, STATUS the BSR value. If ’a’ = 1, then the and BSR. If ‘s’ = 0, no update of bank will be selected as per the these registers occurs (default). BSR value (default). Words: 1 C register f Cycles: 2 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode No Process pop PC from operation Data stack Q1 Q2 Q3 Q4 No No No No Decode Read Process Write to operation operation operation operation register 'f' Data destination Example: RLCF REG, 0, 0 Example: RETURN Before Instruction After Interrupt REG = 1110 0110 C = 0 PC = TOS After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2006 Microchip Technology Inc. DS39564C-page 243

PIC18FXX2 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] RLNCF f [,d [,a] Syntax: [ label ] RRCF f [,d [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n+1>, Operation: (f<n>) → dest<n-1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register 'f' are rotated one bit to the left. If 'd' is 0, Description: The contents of register 'f' are the result is placed in W. If 'd' is 1, rotated one bit to the right through the result is stored back in register the Carry Flag. If 'd' is 0, the result 'f' (default). If ’a’ is 0, the Access is placed in W. If 'd' is 1, the result Bank will be selected, overriding is placed back in register 'f' the BSR value. If ’a’ is 1, then the (default). If ‘a’ is 0, the Access bank will be selected as per the Bank will be selected, overriding BSR value (default). the BSR value. If ’a’ is 1, then the bank will be selected as per the register f BSR value (default). Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register 'f' Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to Example: RLNCF REG, 1, 0 register 'f' Data destination Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39564C-page 244 © 2006 Microchip Technology Inc.

PIC18FXX2 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] RRNCF f [,d [,a] Syntax: [ label ] SETF f [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n-1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified regis- Encoding: 0100 00da ffff ffff ter are set to FFh. If ’a’ is 0, the Description: The contents of register 'f' are Access Bank will be selected, over- rotated one bit to the right. If 'd' is 0, riding the BSR value. If ’a’ is 1, then the result is placed in W. If 'd' is 1, the bank will be selected as per the the result is placed back in register BSR value (default). 'f' (default). If ’a’ is 0, the Access Words: 1 Bank will be selected, overriding the BSR value. If ’a’ is 1, then the Cycles: 1 bank will be selected as per the Q Cycle Activity: BSR value (default). Q1 Q2 Q3 Q4 register f Decode Read Process Write register 'f' Data register 'f' Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction REG = 0x5A Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to REG = 0xFF register 'f' Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2006 Microchip Technology Inc. DS39564C-page 245

PIC18FXX2 SLEEP Enter SLEEP mode SUBFWB Subtract f from W with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB f [,d [,a] Operands: None Operands: 0 ≤ f ≤ 255 Operation: 00h → WDT, d ∈ [0,1] 0 → WDT postscaler, a ∈ [0,1] 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register 'f' and carry flag Description: The power-down status bit (PD) is (borrow) from W (2’s complement cleared. The time-out status bit method). If 'd' is 0, the result is (TO) is set. Watchdog Timer and stored in W. If 'd' is 1, the result is its postscaler are cleared. stored in register 'f' (default). If ’a’ is The processor is put into SLEEP 0, the Access Bank will be selected, mode with the oscillator stopped. overriding the BSR value. If ’a’ is 1, then the bank will be selected as Words: 1 per the BSR value (default). Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode No Process Go to operation Data sleep Q1 Q2 Q3 Q4 Decode Read Process Write to Example: SLEEP register 'f' Data destination Before Instruction Example 1: SUBFWB REG, 1, 0 TO = ? Before Instruction PD = ? REG = 3 After Instruction W = 2 TO = 1 † C = 1 PD = 0 After Instruction † If WDT causes wake-up, this bit is cleared. REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39564C-page 246 © 2006 Microchip Technology Inc.

PIC18FXX2 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF f [,d [,a] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: k – (W) → W d ∈ [0,1] a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal 'k'. The result is placed in W. Description: Subtract W from register 'f' (2’s complement method). If 'd' is 0, Words: 1 the result is stored in W. If 'd' is 1, Cycles: 1 the result is stored back in regis- Q Cycle Activity: ter 'f' (default). If ’a’ is 0, the Access Bank will be selected, Q1 Q2 Q3 Q4 overriding the BSR value. If ’a’ is Decode Read Process Write to W 1, then the bank will be selected literal 'k' Data as per the BSR value (default). Example 1: SUBLW 0x02 Words: 1 Before Instruction Cycles: 1 W = 1 Q Cycle Activity: C = ? After Instruction Q1 Q2 Q3 Q4 W = 1 Decode Read Process Write to C = 1 ; result is positive register 'f' Data destination Z = 0 N = 0 Example 1: SUBWF REG, 1, 0 Example 2: SUBLW 0x02 Before Instruction REG = 3 Before Instruction W = 2 W = 2 C = ? C = ? After Instruction After Instruction REG = 1 W = 0 W = 2 C = 1 ; result is zero C = 1 ; result is positive Z = 1 Z = 0 N = 0 N = 0 Example 3: SUBLW 0x02 Example 2: SUBWF REG, 0, 0 Before Instruction Before Instruction REG = 2 W = 3 C = ? W = 2 C = ? After Instruction After Instruction W = FF ; (2’s complement) REG = 2 C = 0 ; result is negative W = 0 Z = 0 C = 1 ; result is zero N = 1 Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2006 Microchip Technology Inc. DS39564C-page 247

PIC18FXX2 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: [ label ] SUBWFB f [,d [,a] Syntax: [ label ] SWAPF f [,d [,a] Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0101 10da ffff ffff Encoding: 0011 10da ffff ffff Description: Subtract W and the carry flag (bor- row) from register 'f' (2’s complement Description: The upper and lower nibbles of reg- method). If 'd' is 0, the result is stored ister 'f' are exchanged. If 'd' is 0, the in W. If 'd' is 1, the result is stored result is placed in W. If 'd' is 1, the back in register 'f' (default). If ’a’ is 0, result is placed in register 'f' the Access Bank will be selected, (default). If ’a’ is 0, the Access overriding the BSR value. If ’a’ is 1, Bank will be selected, overriding then the bank will be selected as per the BSR value. If ’a’ is 1, then the the BSR value (default). bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to register 'f' Data destination Decode Read Process Write to register 'f' Data destination Example 1: SUBWFB REG, 1, 0 Before Instruction Example: SWAPF REG, 1, 0 REG = 0x19 (0001 1001) Before Instruction W = 0x0D (0000 1101) REG = 0x53 C = 1 After Instruction After Instruction REG = 0x0C (0000 1011) REG = 0x35 W = 0x0D (0000 1101) C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 0x1B (0001 1011) W = 0x1A (0001 1010) C = 0 After Instruction REG = 0x1B (0001 1011) W = 0x00 C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 0x03 (0000 0011) W = 0x0E (0000 1101) C = 1 After Instruction REG = 0xF5 (1111 0100) ; [2’s comp] W = 0x0E (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39564C-page 248 © 2006 Microchip Technology Inc.

PIC18FXX2 TBLRD Table Read TBLRD Table Read (cont’d) Syntax: [ label ] TBLRD ( *; *+; *-; +*) Example1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 0x55 Operation: if TBLRD *, TBLPTR = 0x00A356 (Prog Mem (TBLPTR)) → TABLAT; MEMORY(0x00A356) = 0x34 TBLPTR - No Change; After Instruction if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT; TABLAT = 0x34 TBLPTR = 0x00A357 (TBLPTR) +1 → TBLPTR; Example2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; Before Instruction (TBLPTR) -1 → TBLPTR; TABLAT = 0xAA if TBLRD +*, TBLPTR = 0x01A357 (TBLPTR) +1 → TBLPTR; MEMORY(0x01A357) = 0x12 (Prog Mem (TBLPTR)) → TABLAT; MEMORY(0x01A358) = 0x34 After Instruction Status Affected:None TABLAT = 0x34 Encoding: 0000 0000 0000 10nn TBLPTR = 0x01A358 nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the con- tents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: (cid:129) no change (cid:129) post-increment (cid:129) post-decrement (cid:129) pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write TABLAT) Memory) © 2006 Microchip Technology Inc. DS39564C-page 249

PIC18FXX2 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Before Instruction TABLAT = 0x55 Operation: if TBLWT*, TBLPTR = 0x00A356 (TABLAT) → Holding Register; HOLDING REGISTER TBLPTR - No Change; (0x00A356) = 0xFF if TBLWT*+, After Instructions (table write completion) (TABLAT) → Holding Register; TABLAT = 0x55 (TBLPTR) +1 → TBLPTR; TBLPTR = 0x00A357 if TBLWT*-, HOLDING REGISTER (TABLAT) → Holding Register; (0x00A356) = 0x55 (TBLPTR) -1 → TBLPTR; Example 2: TBLWT +*; if TBLWT+*, (TBLPTR) +1 → TBLPTR; Before Instruction (TABLAT) → Holding Register; TABLAT = 0x34 TBLPTR = 0x01389A Status Affected: None HOLDING REGISTER (0x01389A) = 0xFF Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (0x01389B) = 0xFF =1 *+ After Instruction (table write completion) =2 *- TABLAT = 0x34 =3 +* TBLPTR = 0x01389B HOLDING REGISTER Description: This instruction uses the 3 LSbs of the (0x01389A) = 0xFF TBLPTR to determine which of the 8 HOLDING REGISTER (0x01389B) = 0x34 holding registers the TABLAT data is written to. The 8 holding registers are used to program the contents of Pro- gram Memory (P.M.). See Section5.0 for information on writing to FLASH memory. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: (cid:129) no change (cid:129) post-increment (cid:129) post-decrement (cid:129) pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No No No operation operation operation operation (Read (Write to Holding TABLAT) Register or Memory) DS39564C-page 250 © 2006 Microchip Technology Inc.

PIC18FXX2 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed Description: If 'f' = 0, the next instruction, with the 8-bit literal 'k'. The result fetched during the current instruc- is placed in W. tion execution, is discarded and a Words: 1 NOP is executed, making this a two- cycle instruction. If ’a’ is 0, the Cycles: 1 Access Bank will be selected, over- Q Cycle Activity: riding the BSR value. If ’a’ is 1, Q1 Q2 Q3 Q4 then the bank will be selected as Decode Read Process Write to W per the BSR value (default). literal 'k' Data Words: 1 Cycles: 1(2) Example: XORLW 0xAF Note: 3 cycles if skip and followed Before Instruction by a 2-word instruction. W = 0xB5 Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = 0x1A Decode Read Process No register 'f' Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 0x00, PC = Address (ZERO) If CNT ≠ 0x00, PC = Address (NZERO) © 2006 Microchip Technology Inc. DS39564C-page 251

PIC18FXX2 XORWF Exclusive OR W with f Syntax: [ label ] XORWF f [,d [,a] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in the register 'f' (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ’a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register 'f' Data destination Example: XORWF REG, 1, 0 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 DS39564C-page 252 © 2006 Microchip Technology Inc.

PIC18FXX2 21.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: (cid:129) Edit your source files (either assembly or ‘C’) The PICmicro® microcontrollers are supported with a full range of hardware and software development tools: (cid:129) One touch assemble (or compile) and download to PICmicro emulator and simulator tools (auto- (cid:129) Integrated Development Environment matically updates all project information) - MPLAB® IDE Software (cid:129) Debug using: (cid:129) Assemblers/Compilers/Linkers - source files - MPASMTM Assembler - absolute listing file - MPLAB C17 and MPLAB C18 C Compilers - machine code - MPLINKTM Object Linker/ The ability to use MPLAB IDE with multiple debugging MPLIBTM Object Librarian tools allows users to easily switch from the cost- (cid:129) Simulators effective simulator to a full-featured emulator with - MPLAB SIM Software Simulator minimal retraining. (cid:129) Emulators 21.2 MPASM Assembler - MPLAB ICE 2000 In-Circuit Emulator - ICEPIC™ In-Circuit Emulator The MPASM assembler is a full-featured universal (cid:129) In-Circuit Debugger macro assembler for all PICmicro MCU’s. - MPLAB ICD The MPASM assembler has a command line interface (cid:129) Device Programmers and a Windows shell. It can be used as a stand-alone - PRO MATE® II Universal Device Programmer application on a Windows 3.x or greater system, or it - PICSTART® Plus Entry-Level Development can be used through MPLAB IDE. The MPASM assem- bler generates relocatable object files for the MPLINK Programmer object linker, Intel® standard HEX files, MAP files to (cid:129) Low Cost Demonstration Boards detail memory usage and symbol reference, an abso- - PICDEMTM 1 Demonstration Board lute LST file that contains source lines and generated - PICDEM 2 Demonstration Board machine code, and a COD file for debugging. - PICDEM 3 Demonstration Board The MPASM assembler features include: - PICDEM 17 Demonstration Board (cid:129) Integration into MPLAB IDE projects. - KEELOQ® Demonstration Board (cid:129) User-defined macros to streamline assembly code. 21.1 MPLAB Integrated Development (cid:129) Conditional assembly for multi-purpose source Environment Software files. The MPLAB IDE software brings an ease of software (cid:129) Directives that allow complete control over the development previously unseen in the 8-bit microcon- assembly process. troller market. The MPLAB IDE is a Windows® based application that contains: 21.3 MPLAB C17 and MPLAB C18 C Compilers (cid:129) An interface to debugging tools - simulator The MPLAB C17 and MPLAB C18 Code Development - programmer (sold separately) Systems are complete ANSI ‘C’ compilers for - emulator (sold separately) Microchip’s PIC17CXXX and PIC18CXXX family of - in-circuit debugger (sold separately) microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not (cid:129) A full-featured editor found with other compilers. (cid:129) A project manager For easier source level debugging, the compilers pro- (cid:129) Customizable toolbar and key mapping vide symbol information that is compatible with the (cid:129) A status bar MPLAB IDE memory display. (cid:129) On-line help © 2006 Microchip Technology Inc. DS39564C-page 253

PIC18FXX2 21.4 MPLINK Object Linker/ 21.6 MPLAB ICE High Performance MPLIB Object Librarian Universal In-Circuit Emulator with MPLAB IDE The MPLINK object linker combines relocatable objects created by the MPASM assembler and the The MPLAB ICE universal in-circuit emulator is intended MPLAB C17 and MPLAB C18 C compilers. It can also to provide the product development engineer with a link relocatable objects from pre-compiled libraries, complete microcontroller design tool set for PICmicro using directives from a linker script. microcontrollers (MCUs). Software control of the The MPLIB object librarian is a librarian for pre- MPLAB ICE in-circuit emulator is provided by the compiled code to be used with the MPLINK object MPLAB Integrated Development Environment (IDE), linker. When a routine from a library is called from which allows editing, building, downloading and source another source file, only the modules that contain that debugging from a single environment. routine will be linked in with the application. This allows The MPLAB ICE 2000 is a full-featured emulator sys- large libraries to be used efficiently in many different tem with enhanced trace, trigger and data monitoring applications. The MPLIB object librarian manages the features. Interchangeable processor modules allow the creation and modification of library files. system to be easily reconfigured for emulation of differ- The MPLINK object linker features include: ent processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to (cid:129) Integration with MPASM assembler and MPLAB support new PICmicro microcontrollers. C17 and MPLAB C18 C compilers. The MPLAB ICE in-circuit emulator system has been (cid:129) Allows all memory areas to be defined as sections designed as a real-time emulation system, with to provide link-time flexibility. advanced features that are generally found on more The MPLIB object librarian features include: expensive development tools. The PC platform and (cid:129) Easier linking because single libraries can be Microsoft® Windows environment were chosen to best included instead of many smaller files. make these features available to you, the end user. (cid:129) Helps keep code maintainable by grouping 21.7 ICEPIC In-Circuit Emulator related modules together. (cid:129) Allows libraries to be created and modules to be The ICEPIC low cost, in-circuit emulator is a solution added, listed, replaced, deleted or extracted. for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- 21.5 MPLAB SIM Software Simulator Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X The MPLAB SIM software simulator allows code devel- or PIC16CXXX products through the use of inter- opment in a PC-hosted environment by simulating the changeable personality modules, or daughter boards. PICmicro series microcontrollers on an instruction The emulator is capable of emulating without target level. On any given instruction, the data areas can be application circuitry being present. examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debug- ging using the MPLAB C17 and the MPLAB C18 C com- pilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. DS39564C-page 254 © 2006 Microchip Technology Inc.

PIC18FXX2 21.8 MPLAB ICD In-Circuit Debugger 21.11 PICDEM 1 Low Cost PICmicro Demonstration Board Microchip's In-Circuit Debugger, MPLAB ICD, is a pow- erful, low cost, run-time development tool. This tool is The PICDEM 1 demonstration board is a simple board based on the FLASH PICmicro MCUs and can be used which demonstrates the capabilities of several of to develop for this and other PICmicro microcontrollers. Microchip’s microcontrollers. The microcontrollers sup- The MPLAB ICD utilizes the in-circuit debugging capa- ported are: PIC16C5X (PIC16C54 to PIC16C58A), bility built into the FLASH devices. This feature, along PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, with Microchip's In-Circuit Serial ProgrammingTM proto- PIC17C42, PIC17C43 and PIC17C44. All necessary col, offers cost-effective in-circuit FLASH debugging hardware and software is included to run basic demo from the graphical user interface of the MPLAB programs. The user can program the sample microcon- Integrated Development Environment. This enables a trollers provided with the PICDEM 1 demonstration designer to develop and debug source code by watch- board on a PROMATE II device programmer, or a ing variables, single-stepping and setting break points. PICSTART Plus development programmer, and easily Running at full speed enables testing hardware in real- test firmware. The user can also connect the time. PICDEM1 demonstration board to the MPLAB ICE in- circuit emulator and download the firmware to the emu- 21.9 PRO MATE II Universal Device lator for testing. A prototype area is available for the Programmer user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features The PRO MATE II universal device programmer is a include an RS-232 interface, a potentiometer for simu- full-featured programmer, capable of operating in lated analog input, push button switches and eight stand-alone mode, as well as PC-hosted mode. The LEDs connected to PORTB. PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has program- 21.12 PICDEM 2 Low Cost PIC16CXX mable VDD and VPP supplies, which allow it to verify Demonstration Board programmed memory at VDD min and VDD max for max- imum reliability. It has an LCD display for instructions The PICDEM 2 demonstration board is a simple dem- and error messages, keys to enter commands and a onstration board that supports the PIC16C62, modular detachable socket assembly to support various PIC16C64, PIC16C65, PIC16C73 and PIC16C74 package types. In stand-alone mode, the PRO MATE II microcontrollers. All the necessary hardware and soft- device programmer can read, verify, or program ware is included to run the basic demonstration pro- PICmicro devices. It can also set code protection in this grams. The user can program the sample mode. microcontrollers provided with the PICDEM2 demon- stration board on a PRO MATE II device programmer, 21.10 PICSTART Plus Entry Level or a PICSTART Plus development programmer, and Development Programmer easily test firmware. The MPLAB ICE in-circuit emula- tor may also be used with the PICDEM 2 demonstration The PICSTART Plus development programmer is an board to test firmware. A prototype area has been pro- easy-to-use, low cost, prototype programmer. It con- vided to the user for adding additional hardware and nects to the PC via a COM (RS-232) port. MPLAB connecting it to the microcontroller socket(s). Some of Integrated Development Environment software makes the features include a RS-232 interface, push button using the programmer simple and efficient. switches, a potentiometer for simulated analog input, a The PICSTART Plus development programmer sup- serial EEPROM to demonstrate usage of the I2CTM bus ports all PICmicro devices with up to 40 pins. Larger pin and separate headers for connection to an LCD count devices, such as the PIC16C92X and module and a keypad. PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. © 2006 Microchip Technology Inc. DS39564C-page 255

PIC18FXX2 21.13 PICDEM 3 Low Cost PIC16CXXX 21.14 PICDEM 17 Demonstration Board Demonstration Board The PICDEM 17 demonstration board is an evaluation The PICDEM 3 demonstration board is a simple dem- board that demonstrates the capabilities of several onstration board that supports the PIC16C923 and Microchip microcontrollers, including PIC17C752, PIC16C924 in the PLCC package. It will also support PIC17C756A, PIC17C762 and PIC17C766. All neces- future 44-pin PLCC microcontrollers with an LCD Mod- sary hardware is included to run basic demo programs, ule. All the necessary hardware and software is which are supplied on a 3.5-inch disk. A programmed included to run the basic demonstration programs. The sample is included and the user may erase it and user can program the sample microcontrollers pro- program it with the other sample programs using the vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or the PICSTART PRO MATE II device programmer, or a PICSTART Plus Plus development programmer, and easily debug and development programmer with an adapter socket, and test the sample code. In addition, the PICDEM17 dem- easily test firmware. The MPLAB ICE in-circuit emula- onstration board supports downloading of programs to tor may also be used with the PICDEM 3 demonstration and executing out of external FLASH memory on board. board to test firmware. A prototype area has been pro- The PICDEM 17 demonstration board is also usable vided to the user for adding hardware and connecting it with the MPLAB ICE in-circuit emulator, or the to the microcontroller socket(s). Some of the features PICMASTER emulator and all of the sample programs include a RS-232 interface, push button switches, a can be run and modified using either emulator. Addition- potentiometer for simulated analog input, a thermistor ally, a generous prototype area is available for user and separate headers for connection to an external hardware. LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 21.15 KEELOQ Evaluation and commons and 12 segments, that is capable of display- Programming Tools ing time, temperature and day of the week. The KEELOQ evaluation and programming tools support PICDEM 3 demonstration board provides an additional Microchip’s HCS Secure Data Products. The HCS eval- RS-232 interface and Windows software for showing uation kit includes a LCD display to show changing the demultiplexed LCD signals on a PC. A simple serial codes, a decoder to decode transmissions and a interface allows the user to construct a hardware programming interface to program test transmitters. demultiplexer for the LCD signals. DS39564C-page 256 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 21-1: DEVELOPMENT TOOLS FROM MICROCHIP 7. 0152PCM ! 6, 7 7 4, 7 XXXFRCM ! ! ! ! 73, 2, 7 5, XXXSCH ! ! ! ! 4, 6 6 XXC39 63, //XXXXCC4522 ! ! C62, 6 1 C XXXF81CIP ! ! ! ! ! ! ! ! h PI wit 1) 2XXC81CIP ! ! ! ! ! ! ! 00 4 6 1 V D XX7C71CIP ! ! ! ! ! ! ! er ( g g u X4C71CIP ! ! ! ! ! ! ! eb D uit XX9C61CIP ! ! ! ! ! ! ! Circ n- D I XX8F61CIP ! ! ! ! ! ! C ® I B A X8F61CIP L /X8C61CIP ! ! ! ! ! ! ! MP e h e t XX7C61CIP ! ! ! ! ! ! us o w t o X7C61CIP ! ! ! ! *! ! ! †! †! n h o n o X26F61CIP ! ! **! **! **! mati or nf XXXC61CIP ! ! ! ! ! ! ! m for i o c p. X6C61CIP ! ! ! ! *! ! ! †! hi c o cr mi XX0X50XC0C462111CCCIIPPIP ®MPLAB Integrated!!!Development Environment ®MPLAB C17 C Compiler ®MPLAB C18 C Compiler TMMPASM Assembler/!!! TMMPLINKObject Linker ®MPLAB ICE In-Circuit Emulator!!! TMICEPIC In-Circuit Emulator!! ®MPLAB ICD In-Circuit Debugger ®PICSTART Plus Entry Level!!!Development Programmer ®PRO MATE II !!!Universal Device Programmer TMPICDEM 1 Demonstration !Board TMPICDEM 2 Demonstration Board TMPICDEM 3 Demonstration Board TMPICDEM 14A Demonstration !Board TMPICDEM 17 Demonstration Board ® KLEvaluation KitEEOQ ®KL Transponder KitEEOQ TMmicroID Programmer’s Kit TM125 kHz microID Developer’s Kit TM125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision TM Developer’s KitmicroID MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site at www.Contact Microchip Technology Inc. for availability date.Development tool is available on select devices. slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***† © 2006 Microchip Technology Inc. DS39564C-page 257

PIC18FXX2 NOTES: DS39564C-page 258 © 2006 Microchip Technology Inc.

PIC18FXX2 22.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Voltage on RA4 with respect to Vss...............................................................................................................0V to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)...................................................200mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200mA Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200mA Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. 3: PORTD and PORTE not available on the PIC18F2X2 devices. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. DS39564C-page 259

PIC18FXX2 FIGURE 22-1: PIC18FXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18FXXX 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 22-2: PIC18LFXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LFXXX 4.5V e g 4.2V 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz 40 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. DS39564C-page 260 © 2006 Microchip Technology Inc.

PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) PIC18LFXX2 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX2 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. VDD Supply Voltage D001 PIC18LFXX2 2.0 — 5.5 V HS, XT, RC and LP Osc mode D001 PIC18FXX2 4.2 — 5.5 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section3.1 (Power-on Reset) for details to ensure internal Power-on Reset signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section3.1 (Power-on Reset) for details to ensure internal Power-on Reset signal VBOR Brown-out Reset Voltage D005 PIC18LFXX2 BORV1:BORV0 = 11 1.98 — 2.14 V 85°C ≥ T ≥ 25°C BORV1:BORV0 = 10 2.67 — 2.89 V BORV1:BORV0 = 01 4.16 — 4.5 V BORV1:BORV0 = 00 4.45 — 4.83 V D005 PIC18FXX2 BORV1:BORV0 = 1x N.A. — N.A. V Not in operating voltage range of device BORV1:BORV0 = 01 4.16 — 4.5 V BORV1:BORV0 = 00 4.45 — 4.83 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not additive. Once one of these modules is enabled, the other may also be enabled without further penalty. © 2006 Microchip Technology Inc. DS39564C-page 261

PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX2 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. IDD Supply Current(2,4) D010 PIC18LFXX2 XT osc configuration — .5 1 mA VDD = 2.0V, +25°C, FOSC = 4 MHz — .5 1.25 mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz — 1.2 2 mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz RC osc configuration — .3 1 mA VDD = 2.0V, +25°C, FOSC = 4 MHz — .3 1 mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz — 1.5 3 mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz RCIO osc configuration — .3 1 mA VDD = 2.0V, +25°C, FOSC = 4 MHz — .3 1 mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz — .75 3 mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz D010 PIC18FXX2 XT osc configuration — 1.2 1.5 mA VDD = 4.2V, +25°C, FOSC = 4 MHz — 1.2 2 mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz — 1.2 3 mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz RC osc configuration — 1.5 3 mA VDD = 4.2V, +25°C, FOSC = 4 MHz — 1.5 4 mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz — 1.6 4 mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz RCIO osc configuration — .75 2 mA VDD = 4.2V, +25°C, FOSC = 4 MHz — .75 3 mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz — .8 3 mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz D010A PIC18LFXX2 LP osc, FOSC = 32 kHz, WDT disabled — 14 30 μA VDD = 2.0V, -40°C to +85°C D010A PIC18FXX2 LP osc, FOSC = 32 kHz, WDT disabled — 40 70 μA VDD = 4.2V, -40°C to +85°C — 50 100 μA VDD = 4.2V, -40°C to +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not additive. Once one of these modules is enabled, the other may also be enabled without further penalty. DS39564C-page 262 © 2006 Microchip Technology Inc.

PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX2 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. IDD Supply Current(2,4) (Continued) D010C PIC18LFXX2 EC, ECIO osc configurations — 10 25 mA VDD = 4.2V, -40°C to +85°C D010C PIC18FXX2 EC, ECIO osc configurations — 10 25 mA VDD = 4.2V, -40°C to +125°C D013 PIC18LFXX2 HS osc configuration — .6 2 mA FOSC = 4 MHz, VDD = 2.0V — 10 15 mA FOSC = 25 MHz, VDD = 5.5V HS + PLL osc configurations — 15 25 mA FOSC = 10 MHz, VDD = 5.5V D013 PIC18FXX2 HS osc configuration — 10 15 mA FOSC = 25 MHz, VDD = 5.5V HS + PLL osc configurations — 15 25 mA FOSC = 10 MHz, VDD = 5.5V D014 PIC18LFXX2 Timer1 osc configuration — 15 55 μA FOSC = 32 kHz, VDD = 2.0V D014 PIC18FXX2 Timer1 osc configuration — — 200 μA FOSC = 32 kHz, VDD = 4.2V, -40°C to +85°C — — 250 μA FOSC = 32 kHz, VDD = 4.2V, -40°C to +125°C IPD Power-down Current(3) D020 PIC18LFXX2 — .08 .9 μA VDD = 2.0V, +25°C — .1 4 μA VDD = 2.0V, -40°C to +85°C — 3 10 μA VDD = 4.2V, -40°C to +85°C D020 PIC18FXX2 — .1 .9 μA VDD = 4.2V, +25°C — 3 10 μA VDD = 4.2V, -40°C to +85°C D021B — 15 25 μA VDD = 4.2V, -40°C to +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not additive. Once one of these modules is enabled, the other may also be enabled without further penalty. © 2006 Microchip Technology Inc. DS39564C-page 263

PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX2 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. Module Differential Current D022 ΔIWDT Watchdog Timer — .75 1.5 μA VDD = 2.0V, +25°C PIC18LFXX2 — 2 8 μA VDD = 2.0V, -40°C to +85°C — 10 25 μA VDD = 4.2V, -40°C to +85°C D022 Watchdog Timer — 7 15 μA VDD = 4.2V, +25°C PIC18FXX2 — 10 25 μA VDD = 4.2V, -40°C to +85°C — 25 40 μA VDD = 4.2V, -40°C to +125°C D022A ΔIBOR Brown-out Reset(5) — 29 35 μA VDD = 2.0V, +25°C PIC18LFXX2 — 29 45 μA VDD = 2.0V, -40°C to +85°C — 33 50 μA VDD = 4.2V, -40°C to +85°C D022A Brown-out Reset(5) — 36 40 μA VDD = 4.2V, +25°C PIC18FXX2 — 36 50 μA VDD = 4.2V, -40°C to +85°C — 36 65 μA VDD = 4.2V, -40°C to +125°C D022B ΔILVD Low Voltage Detect(5) — 29 35 μA VDD = 2.0V, +25°C PIC18LFXX2 — 29 45 μA VDD = 2.0V, -40°C to +85°C — 33 50 μA VDD = 4.2V, -40°C to +85°C D022B Low Voltage Detect(5) — 33 40 μA VDD = 4.2V, +25°C PIC18FXX2 — 33 50 μA VDD = 4.2V, -40°C to +85°C — 33 65 μA VDD = 4.2V, -40°C to +125°C D025 ΔITMR1 Timer1 Oscillator — 5.2 30 μA VDD = 2.0V, +25°C PIC18LFXX2 — 5.2 40 μA VDD = 2.0V, -40°C to +85°C — 6.5 50 μA VDD = 4.2V, -40°C to +85°C D025 Timer1 Oscillator — 6.5 40 μA VDD = 4.2V, +25°C PIC18FXX2 — 6.5 50 μA VDD = 4.2V, -40°C to +85°C — 6.5 65 μA VDD = 4.2V, -40°C to +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not additive. Once one of these modules is enabled, the other may also be enabled without further penalty. DS39564C-page 264 © 2006 Microchip Technology Inc.

PIC18FXX2 22.2 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer Vss 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer Vss 0.2 VDD V RC3 and RC4 Vss 0.3 VDD V D032 MCLR VSS 0.2 VDD V D032A OSC1 (in XT, HS and LP modes) VSS 0.3 VDD V and T1OSI D033 OSC1 (in RC and EC mode)(1) VSS 0.2 VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25 VDD + VDD V VDD < 4.5V 0.8V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger buffer 0.8 VDD VDD V RC3 and RC4 0.7 VDD VDD V D042 MCLR, OSC1 (EC mode) 0.8 VDD VDD V D042A OSC1 (in XT, HS and LP modes) 0.7 VDD VDD V and T1OSI D043 OSC1 (RC mode)(1) 0.9 VDD VDD V IIL Input Leakage Current(2,3) D060 I/O ports .02 ±1 μA VSS ≤ VPIN ≤ VDD, Pin at hi-impedance D061 MCLR — ±1 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±1 μA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 450 μA VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. © 2006 Microchip Technology Inc. DS39564C-page 265

PIC18FXX2 22.2 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D080A — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC mode) -40°C to +85°C D083A — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C VOH Output High Voltage(3) D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D090A VDD – 0.7 — V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (RC mode) -40°C to +85°C D092A VDD – 0.7 — V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C D150 VOD Open Drain High Voltage — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA — 400 pF In I2C mode Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. DS39564C-page 266 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 22-3: LOW VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be VLVD cleared in software) (LVDIF set by hardware) 37 LVDIF TABLE 22-1: LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D420 VLVD LVD Voltage on VDD LVV = 0001 1.98 2.06 2.14 V T ≥ 25°C transition high to LVV = 0010 2.18 2.27 2.36 V T ≥ 25°C low LVV = 0011 2.37 2.47 2.57 V T ≥ 25°C LVV = 0100 2.48 2.58 2.68 V LVV = 0101 2.67 2.78 2.89 V LVV = 0110 2.77 2.89 3.01 V LVV = 0111 2.98 3.1 3.22 V LVV = 1000 3.27 3.41 3.55 V LVV = 1001 3.47 3.61 3.75 V LVV = 1010 3.57 3.72 3.87 V LVV = 1011 3.76 3.92 4.08 V LVV = 1100 3.96 4.13 4.3 V LVV = 1101 4.16 4.33 4.5 V LVV = 1110 4.45 4.64 4.83 V © 2006 Microchip Technology Inc. DS39564C-page 267

PIC18FXX2 TABLE 22-2: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC Characteristics Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.25 V D113 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory D120 ED Cell Endurance 100K 1M — E/W -40°C to +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(1) Program FLASH Memory D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP port D132A VIW VDD for Externally Timed Erase 4.5 — 5.5 V Using ICSP port or Write D132B VPEW VDD for Self-timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133 TIE ICSP Block Erase Cycle Time — 4 — ms VDD ≥ 4.5V D133A TIW ICSP Erase or Write Cycle Time 1 — — ms VDD ≥ 4.5V (externally timed) D133A TIW Self-timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Refer to Section6.8 for a more detailed discussion on data EEPROM endurance. DS39564C-page 268 © 2006 Microchip Technology Inc.

PIC18FXX2 22.3 AC (Timing) Characteristics 22.3.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition © 2006 Microchip Technology Inc. DS39564C-page 269

PIC18FXX2 22.3.2 TIMING CONDITIONS The temperature and voltages specified in Table22-3 apply to all timing specifications unless otherwise noted. Figure22-4 specifies the load conditions for the timing specifications. TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section22.1 and Section22.2. LC parts operate for industrial temperatures only. FIGURE 22-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports DS39564C-page 270 © 2006 Microchip Technology Inc.

PIC18FXX2 22.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 22-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 22-4: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 40 MHz EC, ECIO, -40°C to +85°C Oscillator Frequency(1) DC 25 MHz EC, ECIO, +85°C to +125°C DC 4 MHz RC osc 0.1 4 MHz XT osc 4 25 MHz HS osc 4 10 MHz HS + PLL osc, -40°C to +85°C 4 6.25 MHz HS + PLL osc, +85°C to +125°C 5 200 kHz LP Osc mode 1 TOSC External CLKI Period(1) 25 — ns EC, ECIO, -40°C to +85°C Oscillator Period(1) 40 — ns EC, ECIO, +85°C to +125°C 250 — ns RC osc 250 10,000 ns XT osc 40 250 ns HS osc 100 250 ns HS + PLL osc, -40°C to +85°C 160 250 ns HS + PLL osc, +85°C to +125°C 25 — μs LP osc 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, -40°C to +85°C 160 — ns TCY = 4/FOSC, +85°C to +125°C 3 TosL, External Clock in (OSC1) 30 — ns XT osc TosH High or Low Time 2.5 — μs LP osc 10 — ns HS osc 4 TosR, External Clock in (OSC1) — 20 ns XT osc TosF Rise or Fall Time — 50 ns LP osc — 7.5 ns HS osc Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. © 2006 Microchip Technology Inc. DS39564C-page 271

PIC18FXX2 TABLE 22-5: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. — FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only — FSYS On-chip VCO System Frequency 16 — 40 MHz HS mode only — t PLL Start-up Time (Lock Time) — — 2 ms rc — ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 22-6: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin Old Value New Value (output) 20, 21 Note: Refer to Figure22-4 for load conditions. DS39564C-page 272 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 22-6: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 10 TosH2ckL OSC1↑ to CLKO↓ — 75 200 ns (Note 1) 11 TosH2ckH OSC1↑ to CLKO↑ — 75 200 ns (Note 1) 12 TckR CLKO rise time — 35 100 ns (Note 1) 13 TckF CLKO fall time — 35 100 ns (Note 1) 14 TckL2ioV CLKO↓ to Port out valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port in valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port in hold after CLKO ↑ 0 — — ns (Note 1) 17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns 18 TosH2ioI OSC1↑ (Q2 cycle) to Port PIC18FXXX 100 — — ns input invalid (I/O in hold time) 18A PIC18LFXXX 200 — — ns 19 TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20 TioR Port output rise time PIC18FXXX — 10 25 ns 20A PIC18LFXXX — — 60 ns VDD = 2V 21 TioF Port output fall time PIC18FXXX — 10 25 ns 21A PIC18LFXXX — — 60 ns VDD = 2V 22†† TINP INT pin high or low time TCY — — ns 23†† TRBP RB7:RB4 change INT high or low time TCY — — ns 24†† TRCP RC7:RC4 change INT high or low time 20 ns †† These parameters are asynchronous events not related to any internal clock edges. Note1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. FIGURE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure22-4 for load conditions. © 2006 Microchip Technology Inc. DS39564C-page 273

PIC18FXX2 FIGURE 22-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V Typical VIRVST Enable Internal Reference Voltage Internal Reference Voltage stable 36 TABLE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 7 18 33 ms (No Postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power up Timer Period 28 72 132 ms 34 TIOZ I/O Hi-impedance from MCLR Low — 2 — μs or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005) 36 TIVRST Time for Internal Reference — 20 500 μs Voltage to become stable 37 TLVD Low Voltage Detect Pulse Width 200 — — μs VDD ≤ VLVD (see D420) DS39564C-page 274 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 22-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure22-4 for load conditions. TABLE 22-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — ns With Prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — ns With Prescaler 10 — ns 42 Tt0P T0CKI Period No Prescaler TCY + 10 — ns With Prescaler Greater of: — ns N = prescale 20 nS or TCY + 40 value N (1, 2, 4,..., 256) 45 Tt1H T1CKI High Synchronous, no prescaler 0.5TCY + 20 — ns Time Synchronous, PIC18FXXX 10 — ns with prescaler PIC18LFXXX 25 — ns Asynchronous PIC18FXXX 30 — ns PIC18LFXXX 50 — ns 46 Tt1L T1CKI Low Synchronous, no prescaler 0.5TCY + 5 — ns Time Synchronous, PIC18FXXX 10 — ns with prescaler PIC18LFXXX 25 — ns Asynchronous PIC18FXXX 30 — ns PIC18LFXXX 50 — ns 47 Tt1P T1CKI input Synchronous Greater of: — ns N = prescale period 20 nS or TCY + 40 value N (1, 2, 4, 8) Asynchronous 60 — ns Ft1 T1CKI oscillator input frequency range DC 50 kHz 48 Tcke2tmrI Delay from external T1CKI clock edge to timer 2 TOSC 7 TOSC — increment © 2006 Microchip Technology Inc. DS39564C-page 275

PIC18FXX2 FIGURE 22-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure22-4 for load conditions. TABLE 22-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param. Symbol Characteristic Min Max Units Conditions No. 50 TccL CCPx input low No Prescaler 0.5 TCY + 20 — ns time With PIC18FXXX 10 — ns Prescaler PIC18LFXXX 20 — ns 51 TccH CCPx input No Prescaler 0.5 TCY + 20 — ns high time With PIC18FXXX 10 — ns Prescaler PIC18LFXXX 20 — ns 52 TccP CCPx input period 3 TCY + 40 — ns N = prescale N value (1,4 or 16) 53 TccR CCPx output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 54 TccF CCPx output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V DS39564C-page 276 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 22-11: PARALLEL SLAVE PORT TIMING (PIC18F4X2) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure22-4 for load conditions. TABLE 22-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X2) Param. Symbol Characteristic Min Max Units Conditions No. 62 TdtV2wrH Data in valid before WR↑ or CS↑ 20 — ns (setup time) 25 — ns Extended Temp. Range 63 TwrH2dtI WR↑ or CS↑ to data–in invalid PIC18FXXX 20 — ns (hold time) PIC18LFXXX 35 — ns VDD = 2V 64 TrdL2dtV RD↓ and CS↓ to data–out valid — 80 ns — 90 ns Extended Temp. Range 65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 30 ns 66 TibfINH Inhibit of the IBF flag bit being cleared from — 3 TCY WR↑ or CS↑ © 2006 Microchip Technology Inc. DS39564C-page 277

PIC18FXX2 FIGURE 22-12: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit6 - - - - - -1 LSb 75, 76 SDI MSb In bit6 - - - -1 LSb In 74 73 Note: Refer to Figure22-4 for load conditions. TABLE 22-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param. Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — ns TssL2scL 71 TscH SCK input high time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK input low time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns TscL2diL 75 TdoR SDO data output rise time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 76 TdoF SDO data output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 78 TscR SCK output rise time PIC18FXXX — 25 ns (Master mode) PIC18LFXXX — 60 ns VDD = 2V 79 TscF SCK output fall time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 80 TscH2doV, SDO data output valid after SCK PIC18FXXX — 50 ns TscL2doV edge PIC18LFXXX — 150 ns VDD = 2V Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. DS39564C-page 278 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 22-13: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit6 - - - - - -1 LSb 75, 76 SDI MSb In bit6 - - - -1 LSb In 74 Note: Refer to Figure22-4 for load conditions. TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 71 TscH SCK input high time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK input low time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns TscL2diL 75 TdoR SDO data output rise time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 76 TdoF SDO data output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 78 TscR SCK output rise time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 79 TscF SCK output fall time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 80 TscH2doV, SDO data output valid after SCK PIC18FXXX — 50 ns TscL2doV edge PIC18LFXXX — 150 ns VDD = 2V 81 TdoV2scH, SDO data output setup to SCK edge TCY — ns TdoV2scL Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. © 2006 Microchip Technology Inc. DS39564C-page 279

PIC18FXX2 FIGURE 22-14: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit6 - - - -1 LSb In 74 73 Note: Refer to Figure22-4 for load conditions. TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE=0)) Param. No. Symbol Characteristic Min Max Units Conditions 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — ns TssL2scL 71 TscH SCK input high time (Slave mode) Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK input low time (Slave mode) Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns TscL2diL 75 TdoR SDO data output rise time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 76 TdoF SDO data output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 77 TssH2doZ SS↑ to SDO output hi-impedance 10 50 ns 78 TscR SCK output rise time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 79 TscF SCK output fall time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 80 TscH2doV, SDO data output valid after SCK edge PIC18FXXX — 50 ns TscL2doV PIC18LFXXX — 150 ns VDD = 2V 83 TscH2ssH, SS ↑ after SCK edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. DS39564C-page 280 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 22-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit6 - - - - - -1 LSb 75, 76 77 SDI MSb In bit6 - - - -1 LSb In 74 Note: Refer to Figure22-4 for load conditions. TABLE 22-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param. No. Symbol Characteristic Min Max Units Conditions 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — ns TssL2scL 71 TscH SCK input high time Continuous 1.25 TCY + 30 — ns (Slave mode) 71A Single Byte 40 — ns (Note 1) 72 TscL SCK input low time Continuous 1.25 TCY + 30 — ns (Slave mode) 72A Single Byte 40 — ns (Note 1) 73A TB2B Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns TscL2diL 75 TdoR SDO data output rise time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 76 TdoF SDO data output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 77 TssH2doZ SS↑ to SDO output hi-impedance 10 50 ns 78 TscR SCK output rise time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 79 TscF SCK output fall time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 80 TscH2doV, SDO data output valid after SCK PIC18FXXX — 50 ns TscL2doV edge PIC18LFXXX — 150 ns VDD = 2V 82 TssL2doV SDO data output valid after SS↓ edge PIC18FXXX — 50 ns PIC18LFXXX — 150 ns VDD = 2V 83 TscH2ssH, SS ↑ after SCK edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. © 2006 Microchip Technology Inc. DS39564C-page 281

PIC18FXX2 FIGURE 22-16: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure22-4 for load conditions. TABLE 22-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup time 400 kHz mode 600 — START condition 91 THD:STA START condition 100 kHz mode 4000 — ns After this period, the first Hold time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO STOP condition 100 kHz mode 4700 — ns Setup time 400 kHz mode 600 — 93 THD:STO STOP condition 100 kHz mode 4000 — ns Hold time 400 kHz mode 600 — FIGURE 22-17: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure22-4 for load conditions. DS39564C-page 282 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 22-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 4.0 — μs PIC18FXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — μs PIC18FXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs PIC18FXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 102 TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL fall 100 kHz mode — 1000 ns VDD ≥ 4.2V time 400 kHz mode 20 + 0.1 CB 300 ns VDD ≥ 4.2V 90 TSU:STA START condition 100 kHz mode 4.7 — μs Only relevant for Repeated setup time 400 kHz mode 0.6 — μs START condition 91 THD:STA START condition hold 100 kHz mode 4.0 — μs After this period, the first clock time 400 kHz mode 0.6 — μs pulse is generated 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO STOP condition 100 kHz mode 4.7 — μs setup time 400 kHz mode 0.6 — μs 109 TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start D102 CB Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification) before the SCL line is released. © 2006 Microchip Technology Inc. DS39564C-page 283

PIC18FXX2 FIGURE 22-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure22-4 for load conditions. TABLE 22-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated START condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 22-19: MASTER SSP I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure22-4 for load conditions. DS39564C-page 284 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 22-18: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from rise time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 1000 ns VDD ≥ 4.2V fall time 400 kHz mode 20 + 0.1 CB 300 ns VDD ≥ 4.2V 90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated START condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first hold time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data input 100 kHz mode 0 — ns hold time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data input 100 kHz mode 250 — ns (Note 2) setup time 400 kHz mode 100 — ns 92 TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ms setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output valid from 100 kHz mode — 3500 ns clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmission can start D102 CB Bus capacitive loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode) before the SCL line is released. © 2006 Microchip Technology Inc. DS39564C-page 285

PIC18FXX2 FIGURE 22-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure22-4 for load conditions. TABLE 22-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid PIC18FXXX — 50 ns PIC18LFXXX — 150 ns VDD = 2V 121 Tckr Clock out rise time and fall time PIC18FXXX — 25 ns (Master mode) PIC18LFXXX — 60 ns VDD = 2V 122 Tdtr Data out rise time and fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V FIGURE 22-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure22-4 for load conditions. TABLE 22-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TdtV2ckl SYNC RCV (MASTER & SLAVE) Data hold before CK ↓ (DT hold time) 10 — ns 126 TckL2dtl Data hold after CK ↓ (DT hold time) PIC18FXXX 15 — ns PIC18LFXXX 20 — ns VDD = 2V DS39564C-page 286 © 2006 Microchip Technology Inc.

PIC18FXX2 TABLE 22-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX2 (INDUSTRIAL, EXTENDED) PIC18LFXX2 (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit A03 EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.0V A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.0V A05 EG Gain error — — <±1 LSb VREF = VDD = 5.0V A06 EOFF Offset error — — <±1.5 LSb VREF = VDD = 5.0V A10 — Monotonicity guaranteed(2) — VSS ≤ VAIN ≤ VREF A20 VREF Reference Voltage 1.8V — — V VDD < 3.0V A20A (VREFH – VREFL) 3V — — V VDD ≥ 3.0V A21 VREFH Reference voltage High AVSS — AVDD + 0.3V V A22 VREFL Reference voltage Low AVSS – 0.3V — VREFH V A25 VAIN Analog input voltage AVSS – 0.3V — AVDD + 0.3V V VDD ≥ 2.5V (Note 3) A30 ZAIN Recommended impedance of — — 2.5 kΩ (Note 4) analog voltage source A50 IREF VREF input current (Note 1) — — 5 μA During VAIN acquisition — — 150 μA During A/D conversion cycle Note 1: Vss ≤ VAIN ≤ VREF 2: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes. 3: For VDD < 2.5V, VAIN should be limited to < .5 VDD. 4: Maximum allowed impedance for analog voltage source is 10 kΩ. This requires higher acquisition times. FIGURE 22-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 nS), which also disconnects the holding capacitor from the analog input. © 2006 Microchip Technology Inc. DS39564C-page 287

PIC18FXX2 TABLE 22-22: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D clock period PIC18FXXX 1.6 20(4) μs TOSC based PIC18FXXX 2.0 6.0 μs A/D RC mode 131 TCNV Conversion time 11 12 TAD (not including acquisition time) (Note 1) 132 TACQ Acquisition time (Note 2) 5 — μs VREF = VDD = 5.0V 10 — μs VREF = VDD = 2.5V 135 TSWC Switching Time from convert → sample — (Note 3) Note 1: ADRES register may be read on the following TCY cycle. 2: The time for the holding capacitor to acquire the “New” input voltage, when the new input value has not changed by more than 1 LSB from the last sampled voltage. The source impedance (RS) on the input channels is 50Ω. See Section17.0 for more information on acquisition time consideration. 3: On the next Q4 cycle of the device clock. 4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. DS39564C-page 288 © 2006 Microchip Technology Inc.

PIC18FXX2 23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean+3σ) or (mean-3σ) respectively, where σ is a standard deviation, over the whole temperature range. FIGURE 23-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 12 Typical: statistical mean @ 25°C 5.5V 10 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.0V 8 4.5V 4.0V A) m (DD 6 3.5V I 4 3.0V 2 2.5V 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) FIGURE 23-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 12 5.5V Typical: statistical mean @ 25°C 5.0V Maximum: mean + 3σ (-40°C to 125°C) 10 Minimum: mean – 3σ (-40°C to 125°C) 4.5V 8 4.0V A) 3.5V m (D 6 D I 3.0V 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) © 2006 Microchip Technology Inc. DS39564C-page 289

PIC18FXX2 FIGURE 23-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 20 18 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 16 5.5V 14 5.0V 12 4.5V A) m (D 10 4.2V D I 8 6 4 2 0 4 5 6 7 8 9 10 FOSC (MHz) FIGURE 23-4: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) 20 18 Typical: statistical mean @ 25°C 5.5V Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 16 5.0V 14 4.5V 12 A) 4.2V m (D 10 D I 8 6 4 2 0 4 5 6 7 8 9 10 FOSC (MHz) DS39564C-page 290 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 23-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 2,000 1,800 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) 5.5V Minimum: mean – 3σ (-40°C to 125°C) 1,600 5.0V 1,400 4.5V 1,200 4.0V A)A) μ (D (uD 1,000 3.5V DD II 3.0V 800 2.5V 600 2.0V 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 23-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2,000 5.5V 1,800 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.0V 1,600 4.5V 1,400 4.0V 1,200 A) 3.5V μ (D 1,000 D 3.0V I 800 2.5V 600 2.0V 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) © 2006 Microchip Technology Inc. DS39564C-page 291

PIC18FXX2 FIGURE 23-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 100 Typical: statistical mean @ 25°C 90 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 80 5.5V 70 5.0V 60 A) 4.5V (uD 50 ID 4.0V 40 3.5V 3.0V 30 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 23-8: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 140 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) 5.5V 120 Minimum: mean – 3σ (-40°C to 125°C) 5.0V 100 4.5V 80 A) 4.0V u (D D 3.5V I 60 3.0V 2.5V 40 2.0V 20 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) DS39564C-page 292 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 23-9: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 16 Typical: statistical mean @ 25°C 5.5V 14 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.0V 12 4.5V 10 4.2V A) 4.0V m (D 8 D I 6 3.5V 4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 23-10: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 16 Typical: statistical mean @ 25°C 5.5V 14 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.0V 12 4.5V 10 4.2V 4.0V A) m (D 8 D I 3.5V 6 4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) © 2006 Microchip Technology Inc. DS39564C-page 293

PIC18FXX2 FIGURE 23-11: TYPICAL AND MAXIMUM IDD vs. VDD (TIMER1 AS MAIN OSCILLATOR, 32.768kHz, C1 AND C2 = 47pF) 180 160 Typical: statistical mean @ 25°C 140 Maximum: mean + 3σ (-10°C to 70°C) Minimum: mean – 3σ (-10°C to 70°C) 120 100 A)A) μu ( (DD IIDP 80 MMaxa x(+ (7700°CC)) 60 TTyypp ((+2255C°)C) 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20pF, +25°C) 4,500 Operation above 4 MHz is not recommended. 4,000 3.3kΩ 3,500 3,000 5.1kΩ z) 2,500 H k q ( e Fr 2,000 1,500 10kΩ 1,000 500 100kΩ 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39564C-page 294 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 23-13: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100pF, +25°C) 2,000 1,800 1,600 3.3kΩ 1,400 1,200 z) 5.1kΩ H q (k 1,000 e Fr 800 600 10kΩ 400 200 100kΩ 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-14: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300pF, +25°C) 800 700 600 3.3kΩ 500 z) 5.1kΩ H M q ( 400 e Fr 300 10kΩ 200 100 100kΩ 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2006 Microchip Technology Inc. DS39564C-page 295

PIC18FXX2 FIGURE 23-15: IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (-40°C to +125°C) 10 Max (+85°C) A) (uD 1 P I Typ (+25°C) 0.1 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-16: ΔIBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00 - 2.16V) 90 80 70 DDeevvicicee MMaaxx ( +(112255C°C)) HHeeldld i nin 60 RREesSeEtT 50 MMaaxx ((+8855C°)C) A) μ (D D I 40 TTypyp ( +(2255C°C)) 30 DDeevvicicee inin 20 SSLleEeEpP 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39564C-page 296 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 23-17: TYPICAL AND MAXIMUM ΔITMR1 vs. VDD OVER TEMPERATURE (-10°C TO +70°C, TIMER1 WITH OSCILLATOR, XTAL = 32kHz, C1 AND C2 = 47pF) 14 Typical: statistical mean @ 25°C 12 Maximum: mean + 3σ (-10°C to 70°C) Minimum: mean – 3σ (-10°C to 70°C) MMaaxx ( +(7700C°C)) 10 8 A)A) μu TTypyp ( +(2255C°C)) ( (DD PP II 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-18: TYPICAL AND MAXIMUM ΔIWDT vs. VDD OVER TEMPERATURE (WDT ENABLED) 70 Typical: statistical mean @ 25°C 60 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 50 40 A) MaMxa (x+ (112255°CC)) μ (D P I 30 MMaaxx ( +(8855C°C)) 20 10 TyTpy p(+ (2255°CC)) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2006 Microchip Technology Inc. DS39564C-page 297

PIC18FXX2 FIGURE 23-19: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C) 50 Typical: statistical mean @ 25°C 45 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 40 MMaaxx ((+112255C°)C) 35 MMAaXx (+(8855C°C)) s) 30 m d ( o eri 25 P TTyypp DT (+(2255C°C)) W 20 15 MMiinn (-(4-400°CC)) 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-20: ΔILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5 - 4.78V) 90 80 MMaaxx ( +(112255C°C)) 70 60 MMaaxx ((+112255C°)C) 50 A) μ (DD TTypy p( +(2255C°C)) I 40 TTyypp ( (+2255C°)C) 30 LVDIF can be cleared by firmware 20 LVDIF state is unknown 10 LVDIF is set by hardware 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39564C-page 298 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 23-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C) 5.5 5.0 4.5 MMaaxx 4.0 TTypyp ( +(2255C°C)) 3.5 V) 3.0 (H O MMiinn V 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 23-22: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C) 3.0 2.5 2.0 MMaaxx V) (H 1.5 O V TyTpy p(+ (2255°CC)) 1.0 MMinin 0.5 0.0 0 5 10 15 20 25 IOH (-mA) © 2006 Microchip Technology Inc. DS39564C-page 299

PIC18FXX2 FIGURE 23-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C) 1.8 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.2 1.0 V) (OL MMaaxx V 0.8 0.6 0.4 TyTpy (p+ (2255°CC)) 0.2 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 23-24: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C) 2.5 Typical: statistical mean @ 25°C 2.0 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.5 V) (L O V 1.0 MMaaxx TTypyp ( +(2255C°C)) 0.5 0.0 0 5 10 15 20 25 IOL (-mA) DS39564C-page 300 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 23-25: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.0 Typical: statistical mean @ 25°C 3.5 Maximum: mean + 3σ (-40°C to 125°C) VIH Max Minimum: mean – 3σ (-40°C to 125°C) 3.0 2.5 VIH Min V) (N 2.0 VI VIL Max 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-26: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C) 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) VTH (Max) 1.2 VTH (Min) 1.0 V) (N 0.8 VI 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2006 Microchip Technology Inc. DS39564C-page 301

PIC18FXX2 FIGURE 23-27: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40°C TO +125°C) 3.5 VIH Max Typical: statistical mean @ 25°C 3.0 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 2.5 2.0 VILMax V) (N VI VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-28: A/D NON-LINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C) 4 3.5 --4400C°C SB) 3 L arity ( +2255C°C e 2.5 n nli No +8855C°C al 2 gr e nt al or I 1.5 nti e er Diff 1 0.5 1+2152C5°C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) DS39564C-page 302 © 2006 Microchip Technology Inc.

PIC18FXX2 FIGURE 23-29: A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C) 3 2.5 B) S L y ( arilt 2 e n nli o N al 1.5 gr e nt or I MMaaxx ((--4400°CC t oto 1 +2152C5)°C) al nti 1 e er TTyypp ((+2255C°)C) Diff 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) © 2006 Microchip Technology Inc. DS39564C-page 303

PIC18FXX2 NOTES: DS39564C-page 304 © 2006 Microchip Technology Inc.

PIC18FXX2 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC18F242-I/SPe3 XXXXXXXXXXXXXXXXX 0610017 YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F242-E/SOe3 XXXXXXXXXXXXXXXXXXXX 0610017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC18F442-I/Pe3 XXXXXXXXXXXXXXXXXX 0610017 XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. DS39564C-page 305

PIC18FXX2 Package Marking Information (Cont’d) 44-Lead TQFP Example XXXXXXXXXX PIC18F452 XXXXXXXXXX -E/PTe3 XXXXXXXXXX 0610017 YYWWNNN 44-Lead PLCC Example XXXXXXXXXX PIC18F442 XXXXXXXXXX -I/Le3 XXXXXXXXXX 0610017 YYWWNNN DS39564C-page 306 © 2006 Microchip Technology Inc.

PIC18FXX2 24.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A2 A L c β A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 8.26 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .040 .053 .065 1.02 1.33 1.65 Lower Lead Width B .016 .019 .022 0.41 0.48 0.56 Overall Row Spacing § eB .320 .350 .430 8.13 8.89 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 © 2006 Microchip Technology Inc. DS39564C-page 307

PIC18FXX2 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .288 .295 .299 7.32 7.49 7.59 Overall Length D .695 .704 .712 17.65 17.87 18.08 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle Top φ 0 4 8 0 4 8 Lead Thickness c .009 .011 .013 0.23 0.28 0.33 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 DS39564C-page 308 © 2006 Microchip Technology Inc.

PIC18FXX2 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 α n 1 E A A2 L c β B1 A1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 40 40 Pitch p .100 2.54 Top to Seating Plane A .160 .175 .190 4.06 4.45 4.83 Molded Package Thickness A2 .140 .150 .160 3.56 3.81 4.06 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88 Molded Package Width E1 .530 .545 .560 13.46 13.84 14.22 Overall Length D 2.045 2.058 2.065 51.94 52.26 52.45 Tip to Seating Plane L .120 .130 .135 3.05 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .030 .050 .070 0.76 1.27 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .620 .650 .680 15.75 16.51 17.27 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016 © 2006 Microchip Technology Inc. DS39564C-page 309

PIC18FXX2 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45° α A c φ β A1 A2 L F Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .031 0.80 Pins per Side n1 11 11 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff A1 .002 .004 .006 0.05 0.10 0.15 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) F .039 REF. 1.00 REF. φ Foot Angle 0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .012 .015 .017 0.30 0.38 0.44 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MS-026 Drawing No. C04-076 Revised 07-22-05 DS39564C-page 310 © 2006 Microchip Technology Inc.

PIC18FXX2 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45° CH1 x 45° α A3 A2 35° A B1 c β B A1 p E2 D2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .050 1.27 Pins per Side n1 11 11 Overall Height A .165 .173 .180 4.19 4.39 4.57 Molded Package Thickness A2 .145 .153 .160 3.68 3.87 4.06 Standoff § A1 .020 .028 .035 0.51 0.71 0.89 Side 1 Chamfer Height A3 .024 .029 .034 0.61 0.74 0.86 Corner Chamfer 1 CH1 .040 .045 .050 1.02 1.14 1.27 Corner Chamfer (others) CH2 .000 .005 .010 0.00 0.13 0.25 Overall Width E .685 .690 .695 17.40 17.53 17.65 Overall Length D .685 .690 .695 17.40 17.53 17.65 Molded Package Width E1 .650 .653 .656 16.51 16.59 16.66 Molded Package Length D1 .650 .653 .656 16.51 16.59 16.66 Footprint Width E2 .590 .620 .630 14.99 15.75 16.00 Footprint Length D2 .590 .620 .630 14.99 15.75 16.00 Lead Thickness c .008 .011 .013 0.20 0.27 0.33 Upper Lead Width B1 .026 .029 .032 0.66 0.74 0.81 Lower Lead Width B .013 .020 .021 0.33 0.51 0.53 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048 © 2006 Microchip Technology Inc. DS39564C-page 311

PIC18FXX2 NOTES: DS39564C-page 312 © 2006 Microchip Technology Inc.

PIC18FXX2 APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (June 2001) The differences between the devices listed in this data Original data sheet for the PIC18FXX2 family. sheet are shown in TableB-1. Revision B (August 2002) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section22.0 have been updated and there have been minor corrections to the data sheet text. Revision C (October 2006) Packaging diagrams updated. TABLE B-1: DEVICE DIFFERENCES Feature PIC18F242 PIC18F252 PIC18F442 PIC18F452 Program Memory (Kbytes) 16 32 16 32 Data Memory (Bytes) 768 1536 768 1536 A/D Channels 5 5 8 8 Parallel Slave Port (PSP) No No Yes Yes 40-pin DIP 40-pin DIP 28-pin DIP 28-pin DIP Package Types 44-pin PLCC 44-pin PLCC 28-pin SOIC 28-pin SOIC 44-pin TQFP 44-pin TQFP © 2006 Microchip Technology Inc. DS39564C-page 313

PIC18FXX2 APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for con- verting from previous versions of a device to the ones This section discusses how to migrate from a Baseline listed in this data sheet. Typically, these changes are device (i.e., PIC16C5X) to an Enhanced MCU device due to the differences in the process technology used. (i.e., PIC18FXXX). An example of this type of conversion is from a The following are the list of modifications over the PIC16C74A to a PIC16C74B. PIC16C5X microcontroller family: Not Applicable Not Currently Available DS39564C-page 314 © 2006 Microchip Technology Inc.

PIC18FXX2 APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and dif- mid-range MCU devices (i.e., PIC16CXXX) and the ferences between the high-end MCU devices (i.e., enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e., AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18F442”. The changes discussed, while device PIC18FXXX Migration”. This Application Note is specific, are generally applicable to all mid-range to available as Literature Number DS00726. enhanced device migrations. This Application Note is available as Literature Number DS00716. © 2006 Microchip Technology Inc. DS39564C-page 315

PIC18FXX2 NOTES: DS39564C-page 316 © 2006 Microchip Technology Inc.

PIC18FXX2 INDEX A Block Diagrams A/D Converter ..........................................................183 A/D ...................................................................................181 Analog Input Model ..................................................184 A/D Converter Flag (ADIF Bit) .................................183 Baud Rate Generator ..............................................151 A/D Converter Interrupt, Configuring .......................184 Capture Mode Operation .........................................119 Acquisition Requirements ........................................184 Compare Mode Operation .......................................120 ADCON0 Register ....................................................181 Low Voltage Detect ADCON1 Register ....................................................181 External Reference Source .............................190 ADRESH Register ....................................................181 Internal Reference Source ...............................190 ADRESH/ADRESL Registers ..................................183 MSSP ADRESL Register ....................................................181 I2C Mode .........................................................134 Analog Port Pins ................................................99, 100 MSSP (SPI Mode) ...................................................125 Analog Port Pins, Configuring ..................................186 On-Chip Reset Circuit ................................................25 Associated Registers ...............................................188 Parallel Slave Port (PORTD and PORTE) ...............100 Configuring the Module ............................................184 PIC18F2X2 ..................................................................8 Conversion Clock (TAD) ...........................................186 PIC18F4X2 ..................................................................9 Conversion Status (GO/DONE Bit) ..........................183 PLL ............................................................................19 Conversions .............................................................187 PORTC (Peripheral Output Override) ........................93 Converter Characteristics ........................................287 PORTD (I/O Mode) ....................................................95 Equations PORTE (I/O Mode) ....................................................97 Acquisition Time ...............................................185 PWM Operation (Simplified) ....................................122 Minimum Charging Time ..................................185 RA3:RA0 and RA5 Port Pins .....................................87 Examples RA4/T0CKI Pin ..........................................................88 Calculating the Minimum Required RA6 Pin .....................................................................88 Acquisition Time ......................................185 RB2:RB0 Port Pins ....................................................91 Result Registers .......................................................187 RB3 Pin .....................................................................91 Special Event Trigger (CCP) ............................120, 188 RB7:RB4 Port Pins ....................................................90 TAD vs. Device Operating Frequencies ....................186 Table Read Operation ...............................................55 Use of the CCP2 Trigger ..........................................188 Table Write Operation ................................................56 Absolute Maximum Ratings .............................................259 Table Writes to FLASH Program Memory .................61 AC (Timing) Characteristics .............................................269 Timer0 in 16-bit Mode ..............................................104 Load Conditions for Device Timing Timer0 in 8-bit Mode ................................................104 Specifications ...................................................270 Timer1 .....................................................................108 Parameter Symbology .............................................269 Timer1 (16-bit R/W Mode) .......................................108 Temperature and Voltage Specifications - AC .........270 Timer2 .....................................................................112 Timing Conditions ....................................................270 Timer3 .....................................................................114 ACKSTAT Status Flag .....................................................155 Timer3 (16-bit R/W Mode) .......................................114 ADCON0 Register ............................................................181 USART GO/DONE Bit ...........................................................183 Asynchronous Receive ....................................174 ADCON1 Register ............................................................181 Asynchronous Transmit ...................................172 ADDLW ............................................................................217 Watchdog Timer ......................................................204 ADDWF ............................................................................217 BN ....................................................................................220 ADDWFC .........................................................................218 BNC .................................................................................221 ADRESH Register ............................................................181 BNN .................................................................................221 ADRESH/ADRESL Registers ...........................................183 BNOV ...............................................................................222 ADRESL Register ............................................................181 BNZ ..................................................................................222 Analog-to-Digital Converter. See A/D BOR. See Brown-out Reset ANDLW ............................................................................218 BOV .................................................................................225 ANDWF ............................................................................219 BRA .................................................................................223 Assembler BRG. See Baud Rate Generator MPASM Assembler ..................................................253 Brown-out Reset (BOR) .....................................................26 B BSF ..................................................................................223 Baud Rate Generator .......................................................151 BTFSC .............................................................................224 BC ....................................................................................219 BTFSS .............................................................................224 BCF ..................................................................................220 BTG .................................................................................225 BF Status Flag .................................................................155 Bus Collision During a STOP Condition ..........................163 BZ ....................................................................................226 © 2006 Microchip Technology Inc. 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PIC18FXX2 C D CALL ................................................................................226 Data EEPROM Memory Capture (CCP Module) .....................................................119 Associated Registers .................................................69 Associated Registers ...............................................121 EEADR Register ........................................................65 CCP Pin Configuration .............................................119 EECON1 Register ......................................................65 CCPR1H:CCPR1L Registers ...................................119 EECON2 Register ......................................................65 Software Interrupt .....................................................119 Operation During Code Protect .................................68 Timer1/Timer3 Mode Selection ................................119 Protection Against Spurious Write .............................68 Capture/Compare/PWM (CCP) ........................................117 Reading .....................................................................67 Capture Mode. See Capture Using ..........................................................................68 CCP1 ........................................................................118 Write Verify ................................................................68 CCPR1H Register ............................................118 Writing ........................................................................67 CCPR1L Register ............................................118 Data Memory .....................................................................42 CCP2 ........................................................................118 General Purpose Registers .......................................42 CCPR2H Register ............................................118 Map for PIC18F242/442 ............................................43 CCPR2L Register ............................................118 Map for PIC18F252/452 ............................................44 Compare Mode. See Compare Special Function Registers ........................................42 Interaction of Two CCP Modules .............................118 DAW ................................................................................230 PWM Mode. See PWM DC and AC Characteristics Timer Resources ......................................................118 Graphs and Tables ..................................................289 Clocking Scheme/Instruction Cycle ....................................39 DC Characteristics ....................................................261, 265 CLRF ................................................................................227 DCFSNZ ..........................................................................231 CLRWDT ..........................................................................227 DECF ...............................................................................230 Code Examples DECFSZ ..........................................................................231 16 x 16 Signed Multiply Routine .................................72 Development Support ......................................................253 16 x 16 Unsigned Multiply Routine .............................72 Device Differences ...........................................................313 8 x 8 Signed Multiply Routine .....................................71 Device Overview ..................................................................7 8 x 8 Unsigned Multiply Routine .................................71 Features .......................................................................7 Changing Between Capture Prescalers ...................119 Direct Addressing ...............................................................51 Data EEPROM Read .................................................67 Example .....................................................................49 Data EEPROM Refresh Routine ................................68 E Data EEPROM Write ..................................................67 Erasing a FLASH Program Memory Row ..................60 Electrical Characteristics ..................................................259 Fast Register Stack ....................................................39 Errata ...................................................................................5 How to Clear RAM (Bank1) Using F Indirect Addressing ............................................50 Initializing PORTA ......................................................87 Firmware Instructions .......................................................211 Initializing PORTB ......................................................90 FLASH Program Memory ...................................................55 Initializing PORTC ......................................................93 Associated Registers .................................................63 Initializing PORTD ......................................................95 Control Registers .......................................................56 Initializing PORTE ......................................................97 Erase Sequence ........................................................60 Loading the SSPBUF (SSPSR) Register .................128 Erasing .......................................................................60 Reading a FLASH Program Memory Word ................59 Operation During Code Protect .................................63 Saving STATUS, WREG and BSR Reading .....................................................................59 Registers in RAM ...............................................85 TABLAT Register .......................................................58 Writing to FLASH Program Memory .....................62–63 Table Pointer .............................................................58 Code Protection ...............................................................195 Boundaries Based on Operation ........................58 COMF ...............................................................................228 Table Pointer Boundaries ..........................................58 Compare (CCP Module) ...................................................120 Table Reads and Table Writes ..................................55 Associated Registers ...............................................121 Block Diagrams CCP Pin Configuration .............................................120 Reads from FLASH Program Memory .......59 CCPR1 Register .......................................................120 Writing to ....................................................................61 Software Interrupt .....................................................120 Protection Against Spurious Writes ...................63 Special Event Trigger ........................109, 115, 120, 188 Unexpected Termination ....................................63 Timer1/Timer3 Mode Selection ................................120 Write Verify ........................................................63 Configuration Bits .............................................................195 G Context Saving During Interrupts .......................................85 Conversion Considerations ..............................................314 General Call Address Support .........................................148 CPFSEQ ..........................................................................228 GOTO ..............................................................................232 CPFSGT ...........................................................................229 CPFSLT ...........................................................................229 DS39564C-page 318 © 2006 Microchip Technology Inc.

PIC18FXX2 I Instruction Set ..................................................................211 ADDLW ....................................................................217 I/O Ports .............................................................................87 I2C (MSSP Module) ADDWF ....................................................................217 ADDWFC .................................................................218 ACK Pulse ................................................................139 ANDLW ....................................................................218 Read/Write Bit Information (R/W Bit) .......................139 I2C (SSP Module) ANDWF ....................................................................219 BC ............................................................................219 ACK Pulse ................................................................138 I2C Master Mode Reception .............................................155 BCF .........................................................................220 I2C Mode BN ............................................................................220 BNC .........................................................................221 Clock Stretching .......................................................144 I2C Mode (MSSP Module) ................................................134 BNN .........................................................................221 BNOV ......................................................................222 Registers ..................................................................134 I2C Module BNZ .........................................................................222 BOV .........................................................................225 ACK Pulse ........................................................138, 139 BRA .........................................................................223 Acknowledge Sequence Timing ...............................158 BSF ..........................................................................223 Baud Rate Generator ...............................................151 BTFSC .....................................................................224 Bus Collision BTFSS .....................................................................224 Repeated START Condition ............................162 BTG .........................................................................225 START Condition .............................................160 BZ ............................................................................226 Clock Arbitration .......................................................152 CALL ........................................................................226 Effect of a RESET ....................................................159 CLRF .......................................................................227 General Call Address Support .................................148 CLRWDT .................................................................227 Master Mode ............................................................149 COMF ......................................................................228 Operation .........................................................150 CPFSEQ ..................................................................228 Repeated START Condition Timing .................154 CPFSGT ..................................................................229 Master Mode START Condition ...............................153 CPFSLT ...................................................................229 Master Mode Transmission ......................................155 DAW ........................................................................230 Multi-Master Communication, Bus Collision DCFSNZ ..................................................................231 and Arbitration ..................................................159 DECF .......................................................................230 Multi-Master Mode ...................................................159 DECFSZ ..................................................................231 Operation .................................................................138 GOTO ......................................................................232 Read/Write Bit Information (R/W Bit) ...............138, 139 INCF ........................................................................232 Serial Clock (RC3/SCK/SCL) ...................................139 INCFSZ ....................................................................233 Slave Mode ..............................................................138 INFSNZ ....................................................................233 Addressing .......................................................138 IORLW .....................................................................234 Reception .........................................................139 IORWF .....................................................................234 Transmission ....................................................139 LFSR .......................................................................235 Slave Mode Timing (10-bit Reception, MOVF ......................................................................235 SEN = 0) ..........................................................142 MOVFF ....................................................................236 Slave Mode Timing (10-bit Reception, MOVLB ....................................................................236 SEN = 1) ..........................................................147 MOVLW ...................................................................237 Slave Mode Timing (10-bit Transmission) ................143 MOVWF ...................................................................237 Slave Mode Timing (7-bit Reception, MULLW ....................................................................238 SEN = 0) ..........................................................140 MULWF ....................................................................238 Slave Mode Timing (7-bit Reception, NEGF .......................................................................239 SEN = 1) ..........................................................146 NOP .........................................................................239 Slave Mode Timing (7-bit Transmission) ..................141 POP .........................................................................240 SLEEP Operation .....................................................159 PUSH .......................................................................240 STOP Condition Timing ...........................................158 RCALL .....................................................................241 ICEPIC In-Circuit Emulator ..............................................254 RESET .....................................................................241 ID Locations .............................................................195, 210 RETFIE ....................................................................242 INCF .................................................................................232 RETLW ....................................................................242 INCFSZ ............................................................................233 RETURN ..................................................................243 In-Circuit Debugger ..........................................................210 RLCF .......................................................................243 In-Circuit Serial Programming (ICSP) ......................195, 210 RLNCF .....................................................................244 Indirect Addressing ............................................................51 RRCF .......................................................................244 INDF and FSR Registers ...........................................50 RRNCF ....................................................................245 Indirect Addressing Operation ............................................51 SETF .......................................................................245 Indirect File Operand ..........................................................42 SLEEP .....................................................................246 INFSNZ ............................................................................233 SUBFWB .................................................................246 Instruction Cycle .................................................................39 SUBLW ....................................................................247 Instruction Flow/Pipelining .................................................40 SUBWF ....................................................................247 Instruction Format ............................................................213 SUBWFB .................................................................248 SWAPF ....................................................................248 © 2006 Microchip Technology Inc. DS39564C-page 319

PIC18FXX2 TBLRD .....................................................................249 M TBLWT .....................................................................250 Master SSP (MSSP) Module Overview ...........................125 TSTFSZ ....................................................................251 Master Synchronous Serial Port (MSSP). See MSSP. XORLW ....................................................................251 Master Synchronous Serial Port. See MSSP XORWF ....................................................................252 Memory Organization Summary Table ........................................................214 Data Memory .............................................................42 Instructions in Program Memory ........................................40 Program Memory .......................................................35 Two-Word Instructions ...............................................41 Memory Programming Requirements ..............................268 INT Interrupt (RB0/INT). See Interrupt Sources Migration from Baseline to Enhanced Devices ................314 INTCON Register Migration from High-End to Enhanced Devices ...............315 RBIF Bit ......................................................................90 Migration from Mid-Range to Enhanced Devices ............315 INTCON Registers .......................................................75–77 MOVF ..............................................................................235 Inter-Integrated Circuit. See I2C MOVFF ............................................................................236 Interrupt Sources ..............................................................195 MOVLB ............................................................................236 A/D Conversion Complete ........................................184 MOVLW ...........................................................................237 Capture Complete (CCP) .........................................119 MOVWF ...........................................................................237 Compare Complete (CCP) .......................................120 MPLAB C17 and MPLAB C18 C Compilers .....................253 INT0 ...........................................................................85 MPLAB ICD In-Circuit Debugger .....................................255 Interrupt-on-Change (RB7:RB4 ) ...............................90 MPLAB ICE High Performance Universal In-Circuit PORTB, Interrupt-on-Change ....................................85 Emulator with MPLAB IDE .......................................254 RB0/INT Pin, External ................................................85 MPLAB Integrated Development TMR0 .........................................................................85 Environment Software .............................................253 TMR0 Overflow ........................................................105 MPLINK Object Linker/MPLIB Object Librarian ...............254 TMR1 Overflow ................................................107, 109 MSSP ...............................................................................125 TMR2 to PR2 Match .................................................112 Control Registers (general) ......................................125 TMR2 to PR2 Match (PWM) ............................111, 122 Enabling SPI I/O ......................................................129 TMR3 Overflow ................................................113, 115 Operation .................................................................128 USART Receive/Transmit Complete ........................165 Typical Connection ..................................................129 Interrupts ............................................................................73 MSSP Module Logic ...........................................................................74 SPI Master Mode .....................................................130 Interrupts, Enable Bits SPI Master./Slave Connection .................................129 CCP1 Enable (CCP1IE Bit) ......................................119 SPI Slave Mode .......................................................131 Interrupts, Flag Bits MULLW ............................................................................238 A/D Converter Flag (ADIF Bit) ..................................183 MULWF ............................................................................238 CCP1 Flag (CCP1IF Bit) ..........................................119 CCP1IF Flag (CCP1IF Bit) .......................................120 N Interrupt-on-Change (RB7:RB4) Flag NEGF ...............................................................................239 (RBIF Bit) ...........................................................90 NOP .................................................................................239 IORLW .............................................................................234 IORWF .............................................................................234 O IPR Registers ...............................................................82–83 Opcode Field Descriptions ...............................................212 K OPTION_REG Register PSA Bit ....................................................................105 KEELOQ Evaluation and Programming Tools ...................256 T0CS Bit ..................................................................105 L T0PS2:T0PS0 Bits ...................................................105 T0SE Bit ...................................................................105 LFSR ................................................................................235 Oscillator Configuration ......................................................17 Lookup Tables EC ..............................................................................17 Computed GOTO .......................................................41 ECIO ..........................................................................17 Table Reads, Table Writes .........................................41 HS ..............................................................................17 Low Voltage Detect ..........................................................189 HS + PLL ...................................................................17 Converter Characteristics .........................................267 LP ..............................................................................17 Effects of a RESET ..................................................193 RC ..............................................................................17 Operation .................................................................192 RCIO ..........................................................................17 Current Consumption .......................................193 XT ..............................................................................17 During SLEEP ..................................................193 Oscillator Selection ..........................................................195 Reference Voltage Set Point ............................193 Oscillator, Timer1 ..............................................107, 109, 115 Typical Application ...................................................189 Oscillator, Timer3 .............................................................113 LVD. See Low Voltage Detect. .........................................189 Oscillator, WDT ................................................................203 DS39564C-page 320 © 2006 Microchip Technology Inc.

PIC18FXX2 P RC7/RX/DT ................................................................15 RD0/PSP0 .................................................................16 Packaging ........................................................................305 RD1/PSP1 .................................................................16 Details ......................................................................307 RD2/PSP2 .................................................................16 Marking Information .................................................305 RD3/PSP3 .................................................................16 Parallel Slave Port RD4/PSP4 .................................................................16 PORTD ....................................................................100 RD5/PSP5 .................................................................16 Parallel Slave Port (PSP) ...........................................95, 100 RD6/PSP6 .................................................................16 Associated Registers ...............................................101 RD7/PSP7 .................................................................16 RE0/RD/AN5 Pin ................................................99, 100 RE0/RD/AN5 ..............................................................16 RE1/WR/AN6 Pin ...............................................99, 100 RE1/WR/AN6 .............................................................16 RE2/CS/AN7 Pin ................................................99, 100 RE2/CS/AN7 ..............................................................16 Select (PSPMODE Bit) ......................................95, 100 PIC18F2X2 Pin Functions VDD ............................................................................16 MCLR/VPP ..................................................................10 VSS ............................................................................16 PIC18FXX2 Voltage-Frequency Graph OSC1/CLKI ................................................................10 (Industrial) ................................................................260 OSC2/CLKO/RA6 ......................................................10 PIC18LFXX2 Voltage-Frequency Graph RA0/AN0 ....................................................................10 (Industrial) ................................................................260 RA1/AN1 ....................................................................10 PICDEM 1 Low Cost PICmicro RA2/AN2/VREF- ..........................................................10 Demonstration Board ...............................................255 RA3/AN3/VREF+ .........................................................10 PICDEM 17 Demonstration Board ...................................256 RA4/T0CKI .................................................................10 PICDEM 2 Low Cost PIC16CXX RA5/AN4/SS/LVDIN ...................................................10 Demonstration Board ...............................................255 RB0/INT0 ...................................................................11 PICDEM 3 Low Cost PIC16CXXX RB1/INT1 ...................................................................11 Demonstration Board ...............................................256 RB2/INT2 ...................................................................11 PICSTART Plus Entry Level Development RB3/CCP2 .................................................................11 Programmer .............................................................255 RB4 ............................................................................11 PIE Registers ................................................................80–81 RB5/PGM ...................................................................11 Pinout I/O Descriptions RB6/PGC ...................................................................11 PIC18F2X2 ................................................................10 RB7/PGD ...................................................................11 PIR Registers ................................................................78–79 RC0/T1OSO/T1CKI ...................................................12 PLL Lock Time-out .............................................................26 RC1/T1OSI/CCP2 ......................................................12 Pointer, FSR ......................................................................50 RC2/CCP1 .................................................................12 POP .................................................................................240 RC3/SCK/SCL ...........................................................12 POR. See Power-on Reset RC4/SDI/SDA ............................................................12 PORTA RC5/SDO ...................................................................12 Associated Registers .................................................89 RC6/TX/CK ................................................................12 LATA Register ...........................................................87 RC7/RX/DT ................................................................12 PORTA Register ........................................................87 VDD .............................................................................12 TRISA Register ..........................................................87 VSS .............................................................................12 PORTB PIC18F4X2 Pin Functions Associated Registers .................................................92 MCLR/VPP ..................................................................13 LATB Register ...........................................................90 OSC1/CLKI ................................................................13 PORTB Register ........................................................90 OSC2/CLKO ..............................................................13 RB0/INT Pin, External ................................................85 RA0/AN0 ....................................................................13 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ..........90 RA1/AN1 ....................................................................13 TRISB Register ..........................................................90 RA2/AN2/VREF- ..........................................................13 PORTC RA3/AN3/VREF+ .........................................................13 Associated Registers .................................................94 RA4/T0CKI .................................................................13 LATC Register ...........................................................93 RA5/AN4/SS/LVDIN ...................................................13 PORTC Register ........................................................93 RB0/INT .....................................................................14 RC3/SCK/SCL Pin ...................................................139 RB1 ............................................................................14 RC7/RX/DT Pin ........................................................168 RB2 ............................................................................14 TRISC Register ...................................................93, 165 RB3 ............................................................................14 PORTD RB4 ............................................................................14 Associated Registers .................................................96 RB5/PGM ...................................................................14 LATD Register ...........................................................95 RB6/PGC ...................................................................14 Parallel Slave Port (PSP) Function ............................95 RB7/PGD ...................................................................14 PORTD Register ........................................................95 RC0/T1OSO/T1CKI ...................................................15 TRISD Register ..........................................................95 RC1/T1OSI/CCP2 ......................................................15 RC2/CCP1 .................................................................15 RC3/SCK/SCL ...........................................................15 RC4/SDI/SDA ............................................................15 RC5/SDO ...................................................................15 RC6/TX/CK ................................................................15 © 2006 Microchip Technology Inc. DS39564C-page 321

PIC18FXX2 PORTE Registers Analog Port Pins ................................................99, 100 ADCON0 (A/D Control 0) .........................................181 Associated Registers .................................................99 ADCON1 (A/D Control 1) .........................................182 LATE Register ............................................................97 CCP1CON and CCP2CON PORTE Register ........................................................97 (Capture/Compare/PWM Control) ...................117 PSP Mode Select (PSPMODE Bit) ....................95, 100 CONFIG1H (Configuration 1 High) ..........................196 RE0/RD/AN5 Pin ................................................99, 100 CONFIG2H (Configuration 2 High) ..........................197 RE1/WR/AN6 Pin ...............................................99, 100 CONFIG2L (Configuration 2 Low) ...........................197 RE2/CS/AN7 Pin ................................................99, 100 CONFIG3H (Configuration 3 High) ..........................198 TRISE Register ..........................................................97 CONFIG4L (Configuration 4 Low) ...........................198 Postscaler, WDT CONFIG5H (Configuration 5 High) ..........................199 Assignment (PSA Bit) ...............................................105 CONFIG5L (Configuration 5 Low) ...........................199 Rate Select (T0PS2:T0PS0 Bits) .............................105 CONFIG6H (Configuration 6 High) ..........................200 Switching Between Timer0 and WDT ......................105 CONFIG6L (Configuration 6 Low) ...........................200 Power-down Mode. See SLEEP CONFIG7H (Configuration 7 High) ..........................201 Power-on Reset (POR) ......................................................26 CONFIG7L (Configuration 7 Low) ...........................201 Oscillator Start-up Timer (OST) .................................26 DEVID1 (Device ID Register 1) ...............................202 Power-up Timer (PWRT) ............................................26 DEVID2 (Device ID Register 2) ...............................202 Prescaler, Capture ...........................................................119 EECON1 (Data EEPROM Control 1) ....................57, 66 Prescaler, Timer0 .............................................................105 File Summary ........................................................46–48 Assignment (PSA Bit) ...............................................105 INTCON (Interrupt Control) ........................................75 Rate Select (T0PS2:T0PS0 Bits) .............................105 INTCON2 (Interrupt Control 2) ...................................76 Switching Between Timer0 and WDT ......................105 INTCON3 (Interrupt Control 3) ...................................77 Prescaler, Timer2 .............................................................122 IPR1 (Peripheral Interrupt Priority 1) .........................82 PRO MATE II Universal Device Programmer ...................255 IPR2 (Peripheral Interrupt Priority 2) .........................83 Product Identification System ...........................................327 LVDCON (LVD Control) ...........................................191 Program Counter OSCCON (Oscillator Control) ....................................21 PCL Register ..............................................................39 PIE1 (Peripheral Interrupt Enable 1) ..........................80 PCLATH Register .......................................................39 PIE2 (Peripheral Interrupt Enable 2) ..........................81 PCLATU Register .......................................................39 PIR1 (Peripheral Interrupt Request 1) .......................78 Program Memory PIR2 (Peripheral Interrupt Request 2) .......................79 Interrupt Vector ..........................................................35 RCON (Register Control) ...........................................84 Map and Stack for PIC18F442/242 ............................36 RCON (RESET Control) ............................................53 Map and Stack for PIC18F452/252 ............................36 RCSTA (Receive Status and Control) .....................167 RESET Vector ............................................................35 SSPCON1 (MSSP Control 1) Program Verification and Code Protection .......................207 I2C Mode .........................................................136 Associated Registers ...............................................207 SPI Mode .........................................................127 Programming, Device Instructions ...................................211 SSPCON2 (MSSP Control 2) PSP.See Parallel Slave Port. I2C Mode .........................................................137 Pulse Width Modulation. See PWM (CCP Module). SSPSTAT (MSSP Status) PUSH ...............................................................................240 I2C Mode .........................................................135 PWM (CCP Module) .........................................................122 SPI Mode .........................................................126 Associated Registers ...............................................123 STATUS .....................................................................52 CCPR1H:CCPR1L Registers ...................................122 STKPTR (Stack Pointer) ............................................38 Duty Cycle ................................................................122 T0CON (Timer0 Control) .........................................103 Example Frequencies/Resolutions ...........................123 T1CON (Timer 1 Control) ........................................107 Period .......................................................................122 T2CON (Timer 2 Control) ........................................111 Setup for PWM Operation ........................................123 T3CON (Timer3 Control) .........................................113 TMR2 to PR2 Match .........................................111, 122 TRISE ........................................................................98 TXSTA (Transmit Status and Control) .....................166 Q WDTCON (Watchdog Timer Control) ......................203 Q Clock ............................................................................122 RESET ................................................................25, 195, 241 Brown-out Reset (BOR) ...........................................195 R MCLR Reset (During SLEEP) ....................................25 RAM. See Data Memory MCLR Reset (Normal Operation) ..............................25 RC Oscillator ......................................................................18 Oscillator Start-up Timer (OST) ...............................195 RCALL ..............................................................................241 Power-on Reset (POR) .......................................25, 195 RCSTA Register Power-up Timer (PWRT) .........................................195 SPEN Bit ..................................................................165 Programmable Brown-out Reset (BOR) ....................25 Register File .......................................................................42 RESET Instruction .....................................................25 Stack Full Reset .........................................................25 Stack Underflow Reset ..............................................25 Watchdog Timer (WDT) Reset ..................................25 DS39564C-page 322 © 2006 Microchip Technology Inc.

PIC18FXX2 RETFIE ............................................................................242 T RETLW .............................................................................242 TABLAT Register ...............................................................58 RETURN ..........................................................................243 Table Pointer Operations (table) ........................................58 Revision History ...............................................................313 TBLPTR Register ...............................................................58 RLCF ................................................................................243 TBLRD .............................................................................249 RLNCF .............................................................................244 TBLWT .............................................................................250 RRCF ...............................................................................244 Time-out Sequence ...........................................................26 RRNCF .............................................................................245 Time-out in Various Situations ...................................27 S Timer0 ..............................................................................103 16-bit Mode Timer Reads and Writes ......................105 SCI. See USART Associated Registers ...............................................105 SCK ..................................................................................125 Clock Source Edge Select (T0SE Bit) .....................105 SDI ...................................................................................125 Clock Source Select (T0CS Bit) ...............................105 SDO .................................................................................125 Operation .................................................................105 Serial Clock, SCK .............................................................125 Overflow Interrupt ....................................................105 Serial Communication Interface. See USART Prescaler. See Prescaler, Timer0 Serial Data In, SDI ...........................................................125 Timer1 ..............................................................................107 Serial Data Out, SDO .......................................................125 16-bit Read/Write Mode ...........................................109 Serial Peripheral Interface. See SPI Associated Registers ...............................................110 SETF ................................................................................245 Operation .................................................................108 Slave Select Synchronization ...........................................131 Oscillator ...........................................................107, 109 Slave Select, SS ..............................................................125 Overflow Interrupt .............................................107, 109 SLEEP ...............................................................195, 205, 246 Special Event Trigger (CCP) ............................109, 120 Software Simulator (MPLAB SIM) ....................................254 TMR1H Register ......................................................107 Special Event Trigger. See Compare TMR1L Register .......................................................107 Special Features of the CPU ............................................195 Timer2 ..............................................................................111 Configuration Registers ...................................196–201 Associated Registers ...............................................112 Special Function Registers ................................................42 Operation .................................................................111 Map ............................................................................45 Postscaler. See Postscaler, Timer2 SPI PR2 Register ....................................................111, 122 Master Mode ............................................................130 Prescaler. See Prescaler, Timer2 Serial Clock ..............................................................125 SSP Clock Shift ................................................111, 112 Serial Data In ...........................................................125 TMR2 Register .........................................................111 Serial Data Out ........................................................125 TMR2 to PR2 Match Interrupt ...................111, 112, 122 Slave Select .............................................................125 Timer3 ..............................................................................113 SPI Clock .................................................................130 Associated Registers ...............................................115 SPI Mode .................................................................125 Operation .................................................................114 SPI Master/Slave Connection ..........................................129 Oscillator ...........................................................113, 115 SPI Module Overflow Interrupt .............................................113, 115 Associated Registers ...............................................133 Special Event Trigger (CCP) ...................................115 Bus Mode Compatibility ...........................................133 TMR3H Register ......................................................113 Effects of a RESET ..................................................133 TMR3L Register .......................................................113 Master/Slave Connection .........................................129 Timing Diagrams Slave Mode ..............................................................131 Bus Collision Slave Select Synchronization ..................................131 Transmit and Acknowledge .....................159 Slave Synch Timing .................................................131 A/D Conversion ........................................................287 SLEEP Operation .....................................................133 Acknowledge Sequence ..........................................158 SS ....................................................................................125 Baud Rate Generator with Clock Arbitration ............152 SSP BRG Reset Due to SDA Arbitration During I2C Mode. See I2C START Condition .............................................161 SPI Mode .................................................................125 Brown-out Reset (BOR) ...........................................274 SPI Mode. See SPI Bus Collision SSPBUF Register ....................................................130 Start Condition (SDA Only) ..............................160 SSPSR Register ......................................................130 Bus Collision During a Repeated TMR2 Output for Clock Shift ............................111, 112 START Condition (Case 1) ..............................162 SSPOV Status Flag ..........................................................155 Bus Collision During a Repeated SSPSTAT Register START Condition (Case 2) ..............................162 R/W Bit .............................................................138, 139 Bus Collision During a START Condition Status Bits (SCL = 0) .........................................................161 Significance and the Initialization Condition Bus Collision During a STOP Condition for RCON Register .............................................27 (Case 1) ...........................................................163 SUBFWB ..........................................................................246 Bus Collision During a STOP Condition SUBLW ............................................................................247 (Case 2) ...........................................................163 SUBWF ............................................................................247 Capture/Compare/PWM (CCP1 and CCP2) ............276 SUBWFB ..........................................................................248 CLKO and I/O ..........................................................272 SWAPF ............................................................................248 Clock Synchronization .............................................145 © 2006 Microchip Technology Inc. DS39564C-page 323

PIC18FXX2 Example SPI Master Mode (CKE = 0) .....................278 USART Synchronous Transmission Example SPI Master Mode (CKE = 1) .....................279 (Through TXEN) ..............................................177 Example SPI Slave Mode (CKE = 0) .......................280 Wake-up from SLEEP via Interrupt ..........................206 Example SPI Slave Mode (CKE = 1) .......................281 Timing Diagrams Requirements External Clock (All Modes except PLL) ....................271 Master SSP I2C Bus START/STOP Bits ..................284 First START Bit Timing ............................................153 Timing Requirements I2C Bus Data ............................................................282 A/D Conversion ........................................................288 I2C Bus START/STOP Bits ......................................282 Capture/Compare/PWM (CCP1 and CCP2) ............276 I2C Master Mode (Reception, 7-bit Address) ...........157 CLKO and I/O ..........................................................273 I2C Master Mode (Transmission, Example SPI Mode (Master Mode, CKE = 0) ..........278 7 or 10-bit Address) .........................................156 Example SPI Mode (Master Mode, CKE = 1) ..........279 I2C Slave Mode Timing (10-bit Reception, Example SPI Mode (Slave Mode, CKE = 0) ............280 SEN = 0) ..........................................................142 Example SPI Slave Mode (CKE = 1) .......................281 I2C Slave Mode Timing (10-bit Transmission) .........143 External Clock ..........................................................271 I2C Slave Mode Timing (7-bit Reception, I2C Bus Data (Slave Mode) .....................................283 SEN = 0) ..........................................................140 Master SSP I2C Bus Data ........................................285 I2C Slave Mode Timing (7-bit Reception, Parallel Slave Port (PIC18F4X2) .............................277 SEN = 1) ..................................................146, 147 RESET, Watchdog Timer, Oscillator Start-up I2C Slave Mode Timing (7-bit Transmission) ...........141 Timer, Power-up Timer and Low Voltage Detect ..................................................192 Brown-out Reset Requirements .......................274 Master SSP I2C Bus Data ........................................284 Timer0 and Timer1 External Clock ..........................275 Master SSP I2C Bus START/STOP Bits ..................284 USART Synchronous Receive .................................286 Parallel Slave Port (PIC18F4X2) ..............................277 USART Synchronous Transmission ........................286 Parallel Slave Port (Read) ........................................101 Timing Specifications Parallel Slave Port (Write) ........................................100 PLL Clock ................................................................272 PWM Output .............................................................122 TRISE Register Repeat START Condition .........................................154 PSPMODE Bit .....................................................95, 100 RESET, Watchdog Timer (WDT), TSTFSZ ...........................................................................251 Oscillator Start-up Timer (OST) and Two-Word Instructions Power-up Timer (PWRT) .................................273 Example Cases ..........................................................41 Slave Synchronization ..............................................131 TXSTA Register Slaver Mode General Call Address Sequence BRGH Bit .................................................................168 (7 or 10-bit Address Mode) ..............................148 U Slow Rise Time (MCLR Tied to VDD) .........................33 SPI Mode (Master Mode) .........................................130 Universal Synchronous Asynchronous SPI Mode (Slave Mode with CKE = 0) .....................132 Receiver Transmitter. See USART SPI Mode (Slave Mode with CKE = 1) .....................132 USART .............................................................................165 Stop Condition Receive or Transmit Mode ..............158 Asynchronous Mode ................................................172 Time-out Sequence on POR w/PLL Enabled Associated Registers, Receive ........................175 (MCLR Tied to VDD) ...........................................33 Associated Registers, Transmit .......................173 Time-out Sequence on Power-up Receiver ..........................................................174 (MCLR Not Tied to VDD) Transmitter .......................................................172 Case 1 ................................................................32 Baud Rate Generator (BRG) ...................................168 Case 2 ................................................................32 Associated Registers .......................................168 Time-out Sequence on Power-up Baud Rate Error, Calculating ...........................168 (MCLR Tied to VDD) ...........................................32 Baud Rate Formula ..........................................168 Timer0 and Timer1 External Clock ...........................275 Baud Rates for Asynchronous Mode Timing for Transition Between Timer1 and (BRGH = 0) ..............................................170 OSC1 (HS with PLL) ..........................................23 Baud Rates for Asynchronous Mode Transition Between Timer1 and OSC1 (BRGH = 1) ..............................................171 (HS, XT, LP) .......................................................22 Baud Rates for Synchronous Mode .................169 Transition Between Timer1 and OSC1 High Baud Rate Select (BRGH Bit) .................168 (RC, EC) ............................................................23 Sampling ..........................................................168 Transition from OSC1 to Timer1 Oscillator ................22 Serial Port Enable (SPEN Bit) .................................165 USART Asynchronous Master Transmission ...........173 Synchronous Master Mode ......................................176 USART Asynchronous Master Transmission Associated Registers, Reception .....................178 (Back to Back) ..................................................173 Associated Registers, Transmit .......................176 USART Asynchronous Reception ............................175 Reception ........................................................178 USART Synchronous Receive (Master/Slave) .........286 Transmission ...................................................176 USART Synchronous Reception Synchronous Slave Mode ........................................179 (Master Mode, SREN) ......................................178 Associated Registers, Receive ........................180 USART Synchronous Transmission .........................177 Associated Registers, Transmit .......................179 USART Synchronous Transmission Reception ........................................................180 (Master/Slave) ..................................................286 Transmission ...................................................179 DS39564C-page 324 © 2006 Microchip Technology Inc.

PIC18FXX2 W X Wake-up from SLEEP ..............................................195, 205 XORLW ............................................................................251 Using Interrupts ........................................................205 XORWF ...........................................................................252 Watchdog Timer (WDT) ...........................................195, 203 Associated Registers ...............................................204 Control Register .......................................................203 Postscaler ........................................................203, 204 Programming Considerations ..................................203 RC Oscillator ............................................................203 Time-out Period .......................................................203 WCOL ..............................................................................153 WCOL Status Flag ............................................153, 155, 158 WWW, On-Line Support .......................................................5 © 2006 Microchip Technology Inc. DS39564C-page 325

PIC18FXX2 NOTES: DS39564C-page 326 © 2006 Microchip Technology Inc.

PIC18FXX2 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to (cid:129) Distributor or Representative customers. Accessible by using your favorite Internet (cid:129) Local Sales Office browser, the web site contains the following (cid:129) Field Application Engineer (FAE) information: (cid:129) Technical Support (cid:129) Product Support – Data sheets and errata, (cid:129) Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help (cid:129) General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com (cid:129) Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2006 Microchip Technology Inc. DS39564C-page 327

PIC18FXX2 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18FXX2 Literature Number: DS39564C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Advance Information DS39564C-page 328 © 2006 Microchip Technology Inc.

PIC18FXX2 PIC18FXX2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. − X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF452 - I/P 301 = Industrial temp., Range PDIP package, Extended VDD limits, QTP pattern #301. b) PIC18LF242 - I/SO = Industrial temp., Device PIC18FXX2(1), PIC18FXX2T(2); SOIC package, Extended VDD limits. VDD range 4.2V to 5.5V c) PIC18F442 - E/P = Extended temp., PIC18LFXX2(1), PIC18LFXX2T(2); PDIP package, normal VDD limits. VDD range 2.5V to 5.5V Temperature I = -40°C to +85°C (Industrial) Range E = -40°C to +125°C(Extended) Package PT = TQFP (Thin Quad Flatpack) Note 1: F = Standard Voltage range SO = SOIC LF = Wide Voltage Range SP = Skinny Plastic DIP 2: T = in tape and reel - SOIC, P = PDIP PLCC, and TQFP L = PLCC packages only. Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) © 2006 Microchip Technology Inc. DS39564C-page 329

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F452T-I/PT PIC18F452T-I/ML PIC18F442T-I/ML PIC18F442T-I/PT PIC18F452-I/PT PIC18F452-I/PG PIC18F442-I/PT PIC18LF242T-I/SO PIC18LF252T-I/SO PIC18LF452T-I/L PIC18LF442T-I/L PIC18F252-I/SO PIC18F442-I/ML PIC18F452-I/ML PIC18F442-E/L PIC18F442-E/P PIC18F242-I/SO PIC18F252-I/SP PIC18F242- I/SP PIC18F452-I/L PIC18F452-I/P PIC18F452-E/L PIC18F452-E/P PIC18F442-E/PT PIC18F442-I/PTG PIC18F452-E/PT PIC18F442T-I/L PIC18F452T-I/L PIC18F242T-I/SO PIC18F252-I/SPG PIC18F252T-I/SO PIC18F452T-I/PTG PIC18F252-I/SOG PIC18LF452-I/L PIC18LF452-I/P PIC18F242-E/SO PIC18F252-E/SO PIC18F252-E/SP PIC18F452-I/PTG PIC18F452-E/ML PIC18F242-E/SP PIC18F442-E/ML PIC18F442-I/P PIC18F442-I/L PIC18F242T-E/SO PIC18LF252-I/SOG PIC18F252T-I/SOG PIC18LF252T-I/SOG PIC18LF442T-I/PT PIC18LF452T-I/PT PIC18LF442T-I/ML PIC18LF452T-I/ML PIC18LF242-I/SP PIC18LF442-I/ML PIC18LF452-I/PT PIC18LF452-I/ML PIC18LF252-I/SP PIC18LF252-I/SO PIC18LF442-I/PT PIC18LF242-I/SO PIC18LF442-I/P PIC18LF442-I/L PIC18F252T-E/SO PIC18F442T-E/ML PIC18F452T-E/ML