PIC18F2423/2523/4423/4523 Data Sheet 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc. DS39755C

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39755C-page 2 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology Power Management Features: Peripheral Highlights (Continued): • Run: CPU on, Peripherals on • Master Synchronous Serial Port (MSSP) module • Idle: CPU off, Peripherals on Supporting 3-Wire SPI (all four modes) and I2C™ • Sleep: CPU off, Peripherals off Master and Slave modes • Ultra Low 50 nA Input Leakage • Enhanced USART module: • Run mode Currents Down to 11 μA Typical - Support for RS-485, RS-232 and LIN/J2602 • Idle mode Currents Down to 2.5 μA Typical - RS-232 operation using internal oscillator • Sleep mode Current Down to 100 μA Typical block (no external crystal required) • Timer1 Oscillator: 900 nA, 32 kHz, 2V - Auto-wake-up on Start bit • Watchdog Timer: 1.4 μA, 2V Typical - Auto-Baud Detect (ABD) • Two-Speed Oscillator Start-up Special Microcontroller Features: Flexible Oscillator Structure: • C Compiler Optimized Architecture: Optional • Four Crystal modes, up to 40 MHz Extended Instruction Set Designed to Optimize • 4x Phase Lock Loop (PLL) – Available for Crystal Re-Entrant Code and Internal Oscillators • 100,000 Erase/Write Cycle, Enhanced Flash • Two External RC modes, up to 4 MHz Program Memory Typical • Two External Clock modes, up to 40 MHz • 1,000,000 Erase/Write Cycle, Data EEPROM • Internal Oscillator Block: Memory Typical - Fast wake from Sleep and Idle, 1 μs typical • Flash/Data EEPROM Retention: 100 Years Typical - 8 user-selectable frequencies, from 31 kHz to 8 MHz • Self-Programmable under Software Control - Provides a complete range of clock speeds, • Priority Levels for Interrupts from 31 kHz to 32 MHz, when used with PLL • 8 x 8 Single-Cycle Hardware Multiplier - User-tunable to Compensate for Frequency Drift • Extended Watchdog Timer (WDT): Programmable • Secondary Oscillator using Timer1 @ 32 kHz Period, from 4ms to 131s • Fail-Safe Clock Monitor: • Single-Supply In-Circuit Serial Programming™ - Allows for safe shutdown if peripheral clock stops (ICSP™) via Two Pins • In-Circuit Debug (ICD) via Two Pins Peripheral Highlights: • Operating Voltage Range: 2.0V to 5.5V • 12-Bit, Up to 13-Channel Analog-to-Digital Converter • Programmable, 16-Level High/Low-Voltage module (A/D): Detection (HLVD) module: Supports Interrupt on - Auto-acquisition capability High/Low-Voltage Detection - Conversion available during Sleep mode • Programmable Brown-out Reset (BOR): With • Dual Analog Comparators with Input Multiplexing Software-Enable Option • High-Current Sink/Source 25mA/25mA • Three Programmable External Interrupts Note: This document is supplemented by the • Four Input Change Interrupts “PIC18F2420/2520/4420/4520 Data Sheet” • Up to Two Capture/Compare/PWM (CCP) (DS39631). See Section1.0 “Device modules, One with Auto-Shutdown (28-pin devices) Overview”. • Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only): - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart Program Memory Data Memory MSSP T CCP/ R Device (Fblyatsehs) #I nSsintrgulce-tiWonosrd ( SbyRtAesM) E(EbPyRteOs)M I/O A1/D2- B(ciht) (EPCWCMP) SPI MI2aCs™ter EUSA Comp. 8T/i1m6e-Brsit PIC18F2423 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3 PIC18F2523 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3 PIC18F4423 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3 PIC18F4523 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3 © 2009 Microchip Technology Inc. DS39755C-page 3

PIC18F2423/2523/4423/4523 Pin Diagrams 28-Pin PDIP, SOIC MCLR/VPP/RE3 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6//KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 25 RB4/KBI0/AN11 RA3/AN3/VREF+ 5 33 24 RB3/AN9/CCP2(2) RA4/T0CKI/C1OUT 6 4252 23 RB2/INT2/AN8 RA5/AN4/SS/HLVDIN/C2OUT 7 F2F2 22 RB1/INT1/AN10 VSS 8 88 21 RB0/INT0/FLT0/AN12 11 OSC1/CLKI(3)/RA7 9 CC 20 VDD OSC2/CLKO(3)/RA6 10 PIPI 19 VSS RC0/T1OSO/T13CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2(2) 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA 28-Pin QFN(1) RE3GDGCGMN11 A1/AN1A0/AN0 CLR/V/PPB7/KBI3/PB6/KBI2/PB5/KBI1/PB4KBI0/A RR MRRRR 28272625242322 RA2/AN2/VREF-/CVREF 1 21 RB3/AN9/CCP2(2) RA3/AN3/VREF+ 2 20 RB2/INT2/AN8 RA4/T0CKI/C1OUT 3 PIC18F2423 19 RB1/INT1/AN10 RA5/AN4/SS/HLVDIN/C2OUT 4 PIC18F2523 18 RB0/INT0/FLT0/AN12 VSS 5 17 VDD OSC1/CLKI(3)/RA7 6 16 VSS OSC2/CLKO(3)/RA6 7 15 RC7/RX/DT 8 91011121314 C0/T1OSO/T13CKI(2)C1/T1OSI/CCP2RC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CK RR Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS. 2: RB3 is the alternate pin for CCP2 multiplexing. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. For additional information, see Section2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). DS39755C-page 4 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 Pin Diagrams (Continued) 40-Pin PDIP MCLR/VPP/RE3 1 40 RB7/KBI3/PGD RA0/AN0 2 39 RB6/KBI2/PGC RA1/AN1 3 38 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 37 RB4/KBI0/AN11 RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2(1) RA4/T0CKI/C1OUT 6 35 RB2/INT2/AN8 RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/INT1/AN10 RE0/RD/AN5 8 33 33 RB0/INT0/FLT0/AN12 22 RE1/WR/AN6 9 45 32 VDD 44 RE2/CS/AN7 10 FF 31 VSS VDD 11 1818 30 RD7/PSP7/P1D VSS 12 CC 29 RD6/PSP6/P1C OSC1/CLKI(2)/RA7 13 PIPI 28 RD5/PSP5/P1B OSC2/CLKO(2)/RA6 14 27 RD4/PSP4 RC0/T1OSO/T13CKI 15 26 RC7/RX/DT RC1/T1OSI/CCP2(1) 16 25 RC6/TX/CK RC2/CCP1/P1A 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2 44-Pin TQFP 1) (2 TX/CKSDOSDI/SDAPSP3PSP2PSP1PSP0SCK/SCLCCP1/P1AT1OSI/CCP 6/5/4/3/2/1/0/3/2/1/ CCCDDDDCCCC RRRRRRRRRRN 43210987654 44444333333 RC7/RX/DT 1 33 NC RD4/PSP4 2 32 RC0/T1OSO/T13CKI RD5/PSP5/P1B 3 31 OSC2/CLKO(2)/RA6 RD6/PSP6/P1C 4 30 OSC1/CLKI(2)/RA7 RD7/PSP7/P1D 5 PIC18F4423 29 VSS VSS 6 PIC18F4523 28 VDD VDD 7 27 RE2/CS/AN7 RB0/INT0/FLT0/AN12 8 26 RE1/WR/AN6 RB1/INT1/AN10 9 25 RE0/RD/AN5 RB2/INT2/AN8 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB3/AN9/CCP2(1) 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 CC1MCD301F+ NNRB4/KBI0/AN1RB5/KBI1/PGRB6/KBI2/PGRB7/KBI3/PGMCLR/V/REPPRA0/ANRA1/ANN2/V-/CVREFRERA3/AN3/VREF A 2/ A R Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. For additional information, see Section2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). © 2009 Microchip Technology Inc. DS39755C-page 5

PIC18F2423/2523/4423/4523 Pin Diagrams (Continued) 44-Pin QFN(1) (2)2CKI TX/CKSDOSDI/SDAPSP3PSP2PSP1PSP0SCK/SCLCCP1/P1AT1OSI/CCPT1OSO/T13 6/5/4/3/2/1/0/3/2/1/0/ CCCDDDDCCCC RRRRRRRRRRR 43210987654 RC7/RX/DT 1 4444433333333 OSC2/CLKO(3)/RA6 RD4/PSP4 2 32 OSC1/CLKI(3)/RA7 RD5/PSP5/P1B 3 31 VSS RD6/PSP6/P1C 4 30 VSS RD7/PSP7/P1D 5 PIC18F4423 29 VDD VSS 6 28 VDD VDD 7 PIC18F4523 27 RE2/CS/AN7 VDD 8 26 RE1/WR/AN6 RB0/INT0/FLT0/AN12 9 25 RE0/RD/AN5 RB1/INT1/AN10 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB2/INT2/AN8 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 (2)RB3/AN9/CCP2NCRB4/KBI0/AN11RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDMCLR/V/RE3PPRA0/AN0RA1/AN12/AN2/V-/CVREFREFRA3/AN3/V+REF A R Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS. 2: RB3 is the alternate pin for CCP2 multiplexing. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. For additional information, see Section2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). DS39755C-page 6 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 12-Bit Analog-to-Digital Converter (A/D) Module.......................................................................................................................25 3.0 Special Features of the CPU......................................................................................................................................................35 4.0 Electrical Characteristics............................................................................................................................................................37 5.0 Packaging Information................................................................................................................................................................43 Appendix A: Revision History...............................................................................................................................................................45 Appendix B: Device Differences..........................................................................................................................................................45 Appendix C: Conversion Considerations.............................................................................................................................................46 Appendix D: Migration from Baseline to Enhanced Devices................................................................................................................46 Appendix E: Migration from Mid-Range to Enhanced Devices............................................................................................................47 Appendix F: Migration from High-End to Enhanced Devices...............................................................................................................47 Index................................................................................................................................................................................................... 49 The Microchip Web Site.......................................................................................................................................................................51 Customer Change Notification Service................................................................................................................................................51 Customer Support................................................................................................................................................................................51 Reader Response................................................................................................................................................................................52 Product Identification System..............................................................................................................................................................53 © 2009 Microchip Technology Inc. DS39755C-page 7

PIC18F2423/2523/4423/4523 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39755C-page 8 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device-specific information for the following devices: All of the devices in the PIC18F2423/2523/4423/4523 family offer ten different oscillator options, allowing • PIC18F2423 • PIC18LF2423 users a wide range of choices in developing application • PIC18F2523 • PIC18LF2523 hardware. These include: • PIC18F4423 • PIC18LF4423 • Four Crystal modes, using crystals or ceramic resonators. • PIC18F4523 • PIC18LF4523 • Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 Note: This data sheet documents only the devices’ clock output) or one pin (oscillator input, with the features and specifications that are in addition second pin reassigned as general I/O). to, or different from, the features and specifi- • Two External RC Oscillator modes with the same cations of the PIC18F2420/2520/4420/4520 pin options as the External Clock modes. devices. For information on the features and specifications shared by the PIC18F2423/ • An internal oscillator block that offers eight clock 2523/4423/4523 and PIC18F2420/2520/ frequencies: an 8MHz clock and an INTRC source 4420/4520 devices, see the “PIC18F2420/ (approximately 31kHz), as well as a range of six 2520/4420/4520 Data Sheet” (DS39631). user-selectable clock frequencies, between 125kHz to 4MHz. This option frees the two This family offers the advantages of all PIC18 oscillator pins for use as additional general microcontrollers – namely, high computational perfor- purpose I/O. mance at an economical price – with the addition of • A Phase Lock Loop (PLL) frequency multiplier, high-endurance, Enhanced Flash program memory. available to both the High-Speed Crystal and On top of these features, the PIC18F2423/2523/4423/ Internal Oscillator modes, allowing clock speeds 4523 family introduces design enhancements that of up to 40MHz from the HS clock source. Used make these microcontrollers a logical choice for many with the internal oscillator, the PLL gives users a high-performance, power-sensitive applications. complete selection of clock speeds, from 31kHz to 32MHz, all without using an external crystal or 1.1 New Core Features clock circuit. 1.1.1 nanoWatt TECHNOLOGY Besides its availability as a clock source, the internal oscillator block provides a stable reference source that All of the devices in the PIC18F2423/2523/4423/4523 gives the family additional features for robust family incorporate a range of features that can signifi- operation: cantly reduce power consumption during operation. Key items include: • Fail-Safe Clock Monitor: Constantly monitors the main clock source against a reference signal • Alternate Run Modes: By clocking the controller provided by the internal oscillator. If a clock failure from the Timer1 source or the internal oscillator occurs, the controller is switched to the internal block, power consumption during code execution oscillator block, allowing for continued operation can be reduced by as much as 90%. or a safe application shutdown. • Multiple Idle Modes: The controller also can run • Two-Speed Start-up: Allows the internal oscillator with its CPU core disabled and the peripherals still to serve as the clock source from Power-on Reset, active. In these states, power consumption can be or wake-up from Sleep mode, until the primary clock reduced even further, to as little as 4% of normal source is available. operation requirements. • On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. • Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section4.0 “Electrical Characteristics” for values. © 2009 Microchip Technology Inc. DS39755C-page 9

PIC18F2423/2523/4423/4523 1.2 Other Special Features 1.3 Details on Individual Family Members • 12-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a Devices in the PIC18F2423/2523/4423/4523 family are channel to be selected and a conversion to be available in 28-pin and 40/44-pin packages. Block initiated without waiting for a sampling period, diagrams for the two groups are shown in Figure1-1 thereby reducing code overhead. and Figure1-2. • Memory Endurance: The Enhanced Flash cells The devices are differentiated from each other in these for both program memory and data EEPROM are ways: rated to last for many thousands of erase/write • Flash Program Memory: cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without - PIC18F2423/4423 devices – 16Kbytes refresh is conservatively estimated to be greater - PIC18F2523/4523 devices – 32Kbytes than 40 years. • A/D Channels: • Self-Programmability: These devices can write - PIC18F2423/2523 devices – 10 to their own program memory spaces under inter- - PIC18F4423/4523 devices – 13 nal software control. By using a bootloader routine • I/O Ports: located in the protected Boot Block at the top of program memory, it is possible to create an - PIC18F2423/2523 devices – Three bidirectional application that can update itself in the field. ports • Extended Instruction Set: The PIC18F2423/ - PIC18F4423/4523 devices – Five bidirectional 2523/4423/4523 family introduces an optional ports extension to the PIC18 instruction set that adds • CCP and Enhanced CCP Implementation: eight new instructions and an Indexed Addressing - PIC18F2423/2523 devices – Two standard mode. This extension, enabled as a device con- CCP modules figuration option, has been specifically designed - PIC18F4423/4523 devices – One standard to optimize re-entrant application code originally CCP module and one ECCP module developed in high-level languages, such as C. • Parallel Slave Port – Present only on • Enhanced CCP module: In PWM mode, this PIC18F4423/4523 devices module provides one, two or four modulated All other features for devices in this family are identical. outputs for controlling half-bridge and full-bridge These are summarized in Table1-1. drivers. Other features include auto-shutdown, for disabling PWM outputs on interrupt or other select The pinouts for all devices are listed in Table1-2 and conditions, and auto-restart, to reactivate outputs Table1-3. once the condition has cleared. Members of the PIC18F2423/2523/4423/4523 family • Enhanced Addressable USART: This serial are available only as low-voltage devices, designated communication module is capable of standard by “LF” (such as PIC18LF2423), and function over an RS-232 operation and provides support for the extended VDD range of 2.0V to 5.5V. LIN/J2602 bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • Extended Watchdog Timer (WDT): This Enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section4.0 “Electrical Characteristics” for time-out periods. DS39755C-page 10 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 TABLE 1-1: DEVICE FEATURES Features PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16,384 32,768 16,384 32,768 Program Memory (Instructions) 8,192 16,384 8,192 16,384 Data Memory (Bytes) 768 1,536 768 1,536 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 2 2 1 1 Enhanced 0 0 1 1 Capture/Compare/PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications (PSP) No No Yes Yes 12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Stack Full, Stack Stack Full, Stack Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT Programmable Yes Yes Yes Yes High/Low-Voltage Detect Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set enabled Instruction Set enabled Instruction Set enabled Instruction Set enabled Packages 28-Pin PDIP 28-Pin PDIP 40-Pin PDIP 40-Pin PDIP 28-Pin SOIC 28-Pin SOIC 44-Pin QFN 44-Pin QFN 28-Pin QFN 28-Pin QFN 44-Pin TQFP 44-Pin TQFP © 2009 Microchip Technology Inc. DS39755C-page 11

PIC18F2423/2523/4423/4523 FIGURE 1-1: PIC18F2423/2523 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 8 8 Data Latch PORTA RA0/AN0 Data Memory RA1/AN1 21 PCLAT U PCLATH ( 3.9Kbytes ) RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ 20 Address Latch RA4/T0CKI/C1OUT PCU PCH PCL RA5/AN4/SS/HLVDIN/C2OUT Program Counter 12 OSC2/CLKO(3)/RA6 Data Address<12> OSC1/CLKI(3)/RA7 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (16/32Kbytes) FSR1 Data Latch FSR2 12 PORTB RB0/INT0/FLT0/AN12 inc/dec 8 logic RB1/INT1/AN10 Table Latch RB2/INT2/AN8 RB3/AN9/CCP2(1) RB4/KBI0/AN11 Address ROM Latch RB5/KBI1/PGM Instruction Bus <16> Decode RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T13CKI 3 8 RC1/T1OSI/CCP2(1) RC2/CCP1 BITOP W RC3/SCK/SCL 8 8 8 RC4/SDI/SDA RC5/SDO OSC1(3) OInsBtceloilrlcnakatolr PoTwimere-rup 8 8 RRCC67//TRXX//CDKT OSC2(3) Oscillator ALU<8> INTRC Start-up Timer T1OSI Oscillator Power-on 8 Reset 8 MHz T1OSO Oscillator Watchdog Timer Precision MCLR(2) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBeafnedr eGnacpe PORTE In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor MCLR/VPP/RE3(2) BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 ADC Comparator CCP1 CCP2 MSSP EUSART 12-Bit Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. For additional information, see Section2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). DS39755C-page 12 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 FIGURE 1-2: PIC18F4423/4523 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0 Data Latch RA1/AN1 inc/dec logic 8 8 RA2/AN2/VREF-/CVREF Data Memory RA3/AN3/VREF+ 21 PCLAT U PCLATH ( 3.9Kbytes ) RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT 20 PCU PCH PCL Address Latch OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 Program Counter 12 Data Address<12> PORTB 31 Level Stack RB0/INT0/FLT0/AN12 Address Latch 4 12 4 RB1/INT1/AN10 BSR Access Program Memory STKPTR FSR0 Bank RB2/INT2/AN8 (16/32Kbytes) FSR1 RB3/AN9/CCP2(1) Data Latch FSR2 12 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A IR RC3/SCK/SCL RC4/SDI/SDA 8 RC5/SDO Instruction State Machine RC6/TX/CK Decode and Control Signals RC7/RX/DT Control PRODH PRODL 8 x 8 Multiply 3 8 PORTD RD0/PSP0:RD4/PSP4 BITOP W 8 8 8 RD5/PSP5/P1B RD6/PSP6/P1C OSC1(3) Internal Power-up RD7/PSP7/P1D OsBcloillcaktor Timer 8 8 OSC2(3) Oscillator ALU<8> INTRC Start-up Timer T1OSI Oscillator Power-on 8 Reset 8 MHz T1OSO Oscillator Watchdog PORTE Timer Precision RE0/RD/AN5 MCLR(2) Single-Supply Brown-out Band Gap RE1/WR/AN6 Programming Reset Reference RE2/CS/AN7 In-Circuit Fail-Safe MCLR/VPP/RE3(2) VDD,VSS Debugger Clock Monitor BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 ADC Comparator ECCP1 CCP2 MSSP EUSART 12-Bit Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. For additional information, see Section2.0 “Oscillator Configurations” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). © 2009 Microchip Technology Inc. DS39755C-page 13

PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name PDIP, Description QFN Type Type SOIC MCLR/VPP/RE3 1 26 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI/RA7 9 6 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 10 7 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39755C-page 14 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PDIP, Description QFN Type Type SOIC PORTA is a bidirectional I/O port. RA0/AN0 2 27 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 3 28 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF-/CVREF 4 1 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Comparator reference voltage output. RA3/AN3/VREF+ 5 2 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT 6 3 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RA5/AN4/SS/HLVDIN/ 7 4 C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39755C-page 15

PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PDIP, Description QFN Type Type SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 21 18 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST PWM Fault input for CCP1. AN12 I Analog Analog Input 12. RB1/INT1/AN10 22 19 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. AN10 I Analog Analog Input 10. RB2/INT2/AN8 23 20 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. AN8 I Analog Analog Input 8. RB3/AN9/CCP2 24 21 RB3 I/O TTL Digital I/O. AN9 I Analog Analog Input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0/AN11 25 22 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN11 I Analog Analog Input 11. RB5/KBI1/PGM 26 23 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 27 24 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 28 25 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39755C-page 16 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PDIP, Description QFN Type Type SOIC PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 11 8 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 12 9 RC1 I/O ST Digital I/O. T1OSI I Analog Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1 13 10 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK/SCL 14 11 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O I2C Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 15 12 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O I2C I2C data I/O. RC5/SDO 16 13 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 17 14 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 18 15 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). RE3 — — — — See MCLR/VPP/RE3 pin. VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39755C-page 17

PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type MCLR/VPP/RE3 1 18 18 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI/RA7 13 32 30 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; analog otherwise. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39755C-page 18 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTA is a bidirectional I/O port. RA0/AN0 2 19 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 3 20 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF-/CVREF 4 21 21 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Comparator reference voltage output. RA3/AN3/VREF+ 5 22 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT 6 23 23 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RA5/AN4/SS/HLVDIN/ 7 24 24 C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39755C-page 19

PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 33 9 8 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST PWM Fault input for Enhanced CCP1. AN12 I Analog Analog Input 12. RB1/INT1/AN10 34 10 9 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. AN10 I Analog Analog Input 10. RB2/INT2/AN8 35 11 10 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. AN8 I Analog Analog Input 8. RB3/AN9/CCP2 36 12 11 RB3 I/O TTL Digital I/O. AN9 I Analog Analog Input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0/AN11 37 14 14 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN11 I Analog Analog Input 11. RB5/KBI1/PGM 38 15 15 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39755C-page 20 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 15 34 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 16 35 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1/P1A 17 36 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — Enhanced CCP1 output. RC3/SCK/SCL 18 37 37 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O I2C Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 23 42 42 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O I2C I2C data I/O. RC5/SDO 24 43 43 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 26 1 1 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39755C-page 21

PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled. RD0/PSP0 19 38 38 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. RD1/PSP1 20 39 39 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. RD2/PSP2 21 40 40 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. RD3/PSP3 22 41 41 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. RD4/PSP4 27 2 2 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. RD5/PSP5/P1B 28 3 3 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. P1B O — Enhanced CCP1 output. RD6/PSP6/P1C 29 4 4 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. P1C O — Enhanced CCP1 output. RD7/PSP7/P1D 30 5 5 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. P1D O — Enhanced CCP1 output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39755C-page 22 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTE is a bidirectional I/O port. RE0/RD/AN5 8 25 25 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port (see also WR and CS pins). AN5 I Analog Analog Input 5. RE1/WR/AN6 9 26 26 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port (see CS and RD pins). AN6 I Analog Analog Input 6. RE2/CS/AN7 10 27 27 RE2 I/O ST Digital I/O. CS I TTL Chip select control for Parallel Slave Port (see related RD and WR). AN7 I Analog Analog Input 7. RE3 — — — — — See MCLR/VPP/RE3 pin. VSS 12, 31 6, 30, 6, 29 P — Ground reference for logic and I/O pins. 31 VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins. 28, 29 NC — 13 12, 13, — — No connect. 33, 34 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power I2C = I2C™/SMBus Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39755C-page 23

PIC18F2423/2523/4423/4523 NOTES: DS39755C-page 24 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 2.0 12-BIT ANALOG-TO-DIGITAL Of the ADCONx registers: CONVERTER (A/D) MODULE • ADCON0 (shown in Register2-1) – Controls the module’s operation The Analog-to-Digital (A/D) Converter module has • ADCON1 (Register2-2) – Configures the 10inputs for the PIC18F2423/2523 devices and 13 for functions of the port pins the PIC18F4423/4523 devices. This module allows • ADCON2 (Register2-3) – Configures the A/D conversion of an analog input signal to a corresponding clock source, programmed acquisition time and 12-bit digital number. justification The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Note 1: These channels are not implemented on PIC18F2423/2523 devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. © 2009 Microchip Technology Inc. DS39755C-page 25

PIC18F2423/2523/4423/4523 REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits: PCFG<3:0> N12 N11 N10 N9 N8 (2)N7 (2)N6 (2)N5 N4 N3 N2 N1 N0 A A A A A A A A A A A A A 0000(1) A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 0111(1) D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. 2: AN5 through AN7 are only available on PIC18F4423/4523 devices. DS39755C-page 26 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2009 Microchip Technology Inc. DS39755C-page 27

PIC18F2423/2523/4423/4523 The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (VDD and VSS), or the voltage level on the RA3/AN3/ conversion in progress is aborted. VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D Converter can be The A/D Converter has a unique feature of being able configured as an analog input or as a digital I/O. The to operate while the device is in Sleep mode. To oper- ADRESH and ADRESL registers contain the result of ate in Sleep, the A/D conversion clock must be derived the A/D conversion. When the A/D conversion is com- from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared The output of the sample and hold is the input into the and A/D Interrupt Flag bit, ADIF, is set. converter, which generates the result via successive approximation. The block diagram of the A/D module is shown in Figure2-1. FIGURE 2-1: A/D BLOCK DIAGRAM CHS<3:0> 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7(1) 0110 AN6(1) 0101 AN5(1) 0100 AN4 VAIN 12-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG<1:0> AN1 VDD(2) 0000 AN0 X0 VREF+ X1 Reference Voltage 1X VREF- 0X VSS(2) Note 1: Channels, AN5 through AN7, are not available on PIC18F2423/2523 devices. 2: I/O pins have diode protection to VDD and VSS. DS39755C-page 28 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 The value in the ADRESH:ADRESL registers is 5. Wait for the A/D conversion to complete by either: unknown following POR and BOR Resets and is not • Polling for the GO/DONE bit to be cleared affected by any other Reset. OR After the A/D module has been configured as desired, • Waiting for the A/D interrupt the selected channel must be acquired before the 6. Read the A/D Result registers (ADRESH:ADRESL) conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. and clear the ADIF bit, if required. To determine acquisition time, see Section2.1 “A/D 7. For the next conversion, go to step 1 or step 2, Acquisition Requirements”. as required. After this acquisition time has elapsed, the A/D conver- The A/D conversion time per bit is defined as sion can be started. An acquisition time can be TAD. A minimum wait of 2 TAD is required before programmed to occur between setting the GO/DONE the next acquisition starts. bit and the actual start of the conversion. FIGURE 2-2: A/D TRANSFER FUNCTION The following steps should be followed to perform an A/D conversion: 1. Configure the A/D module: FFFh • Configure analog pins, voltage reference and digital I/O (ADCON1) FFEh • Select A/D input channel (ADCON0) ut p • Select A/D acquisition time (ADCON2) ut O • Select A/D conversion clock (ADCON2) e d • Turn on the A/D module (ADCON0) Co 003h al 2. Configure the A/D interrupt (if desired): git Di 002h • Clear ADIF bit • Set ADIE bit 001h • Set GIE bit 3. Wait the required acquisition time (if required). 000h B B B B B B B B B B 4. Start conversion by setting the GO/DONE bit LS LS LS LS LS LS LS LS LS LS (ADCON0<1>). 0.5 1 1.5 2 2.5 3 4094 094.5 4095 095.5 4 4 Analog Input Voltage FIGURE 2-3: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS VAIN CPIN ILEAKAGE CHOLD = 25 pF 5 pF VT = 0.6V ±100 nA VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage 6V ILEAKAGE = Leakage Current at the pin due to 5V various junctions VDD 4V 3V RIC = Interconnect Resistance 2V SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) 1 2 3 4 RSS = Sampling Switch Resistance SamplingSwitch(kΩ) © 2009 Microchip Technology Inc. DS39755C-page 29

PIC18F2423/2523/4423/4523 2.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation2-1 may be used. This equation assumes that 1/2 LSb error For the A/D Converter to meet its specified accuracy, is used (4,096 steps for the A/D). The 1/2 LSb error is the the charge holding capacitor (CHOLD) must be allowed maximum error allowed for the A/D to meet its specified to fully charge to the input channel voltage level. The resolution. analog input model is shown in Figure2-3. Example2-3 shows the calculation of the minimum The source impedance (RS) and the internal sampling required acquisition time, TACQ. This calculation is switch (RSS) impedance directly affect the time based on the application system assumptions shown in required to charge the capacitor, CHOLD. The sampling Table2-1: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage TABLE 2-1: TACQ ASSUMPTIONS at the analog input (due to pin leakage current). The CHOLD = 25 pF maximum recommended impedance for analog Rs = 2.5 kΩ sources is 2.5kΩ. Conversion Error ≤ 1/2 LSb After the analog input channel is selected (changed), VDD = 3V → Rss = 4 kΩ the channel must be sampled for at least the minimum acquisition time before starting a conversion. Temperature = 85°C (system maximum) Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 2-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 2-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096) EQUATION 2-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/4095) μs -(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0004883) μs 1.56 μs TACQ = 0.2 μs + 1.56 μs + 1.2 μs 2.96 μs DS39755C-page 30 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 2.2 Selecting and Configuring 2.3 Selecting the A/D Conversion Acquisition Time Clock The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The acquisition time that occurs each time the GO/DONE A/D conversion requires 13 TAD per 12-bit conversion. bit is set. It also gives users the option of having an The source of the A/D conversion clock is software automatically determined acquisition time. selectable. Acquisition time may be set with the ACQT<2:0> bits There are seven possible options for TAD: (ADCON2<5:3>), which provide a range of 2 to 20TAD. • 2 TOSC • 32 TOSC When the GO/DONE bit is set, the A/D module con- tinues to sample the input for the selected acquisition • 4 TOSC • 64 TOSC time, then automatically begins a conversion. Since the • 8 TOSC • Internal RC Oscillator acquisition time is programmed, there may be no need • 16 TOSC to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the Manual acquisition time is selected when minimum TAD. (For more information, see parameter130 ACQT<2:0>=000. When the GO/DONE bit is set, on page41.) sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time Table2-2 shows the resultant TAD times derived from has passed between selecting the desired input the device operating frequencies and the A/D clock channel and setting the GO/DONE bit. This option is source selected. also the default Reset state of the ACQT<2:0> bits and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 2-2: TAD vs. DEVICE OPERATING FREQUENCIES A/D Clock Source (TAD) Assumes TAD Min. = 0.8 μs Operation ADCS<2:0> Maximum FOSC 2 TOSC 000 2.50 MHz 4 TOSC 100 5.00 MHz 8 TOSC 001 10.00 MHz 16 TOSC 101 20.00 MHz 32 TOSC 010 40.00 MHz 64 TOSC 110 40.00 MHz RC(2) x11 1.00 MHz(1) Note 1: The RC source has a typical TAD time of 2.5 μs. 2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC divider should be used instead; otherwise, the A/D accuracy specification may not be met. © 2009 Microchip Technology Inc. DS39755C-page 31

PIC18F2423/2523/4423/4523 2.4 Operation in Power-Managed 2.5 Configuring Analog Port Pins Modes The ADCON1, TRISA, TRISB and TRISE registers all The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits source and frequency while in a power-managed mode. set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. If the A/D is expected to operate while the device is in a power-managed mode, the ADCS<2:0> bits in The A/D operation is independent of the state of the ADCON2 should be updated in accordance with the CHS<3:0> bits and the TRIS bits. clock source to be used. The ACQT<2:0> bits do not Note1: When reading the PORT register, all pins need to be adjusted as the ADCS<2:0> bits adjust the configured as analog input channels will TAD time for the new clock speed. After entering the read as cleared (a low level). Analog con- mode, an A/D acquisition or conversion may be started. version on pins configured as digital pins Once started, the device should continue to be clocked can be performed. The voltage on the pin by the same clock source until the conversion has been will be accurately converted. completed. 2: Analog levels on any pin defined as a If desired, the device may be placed into the digital input may cause the digital input corresponding Idle mode during the conversion. If the buffer to consume current out of the device clock frequency is less than 1MHz, the A/D RC device’s specification limits. clock source should be selected. 3: The PBADEN bit in Configuration Operation in Sleep mode requires the A/D FRC clock to Register 3H configures PORTB pins to be selected. If bits, ACQT<2:0>, are set to ‘000’ and a reset as analog or digital pins by controlling conversion is started, the conversion will be delayed how the PCFG<3:0> bits in ADCON1 are one instruction cycle to allow execution of the SLEEP reset. instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. DS39755C-page 32 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 2.6 A/D Conversions After the A/D conversion is completed or aborted, a 2TCY wait is required before the next acquisition can Figure2-4 shows the operation of the A/D Converter be started. After this wait, acquisition on the selected after the GO/DONE bit has been set and the channel is automatically started. ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep Note: The GO/DONE bit should NOT be set in mode before the conversion begins. the same instruction that turns on the A/D. Code should wait at least 3 TAD after Figure2-5 shows the operation of the A/D Converter enabling the A/D before beginning an after the GO/DONE bit has been set, the ACQT<2:0> acquisition and conversion cycle. bits have been set to ‘010’ and a 4TAD acquisition time has been selected before the conversion starts. 2.7 Discharge Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will The discharge phase is used to initialize the value of NOT be updated with the partially completed A/D the holding capacitor. The array is discharged before conversion sample. This means, the ADRESH:ADRESL every sample. This feature helps to optimize the unity- registers will continue to contain the value of the last gain amplifier, as the circuit always needs to charge the completed conversion (or the last value written to the capacitor array, rather than charge/discharge based on ADRESH:ADRESL registers). previous measure values. FIGURE 2-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY – TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11TAD12TAD13 TAD1 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge (typically 200 ns) Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 2-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 TAD1 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Time Conversion starts Discharge (Holding capacitor is disconnected) (typically Points to end of TACQT period (current black arrow) 200 ns) Set GO/DONE bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. © 2009 Microchip Technology Inc. DS39755C-page 33

PIC18F2423/2523/4423/4523 2.8 Use of the CCP2 Trigger The appropriate analog input channel must be selected and the minimum acquisition period is either timed by An A/D conversion can be started by the Special Event the user or an appropriate TACQ time is selected before Trigger of the CCP2 module. This requires that the the Special Event Trigger sets the GO/DONE bit (starts CCP2M<3:0> bits (CCP2CON<3:0>) be programmed a conversion). as ‘1011’ and that the A/D module is enabled (ADON If the A/D module is not enabled (ADON is cleared), the bit is set). When the trigger occurs, the GO/DONE bit Special Event Trigger will be ignored by the A/D will be set, starting the A/D acquisition and conversion, module, but will still reset the Timer1 (or Timer3) and the Timer1 (or Timer3) counter will be reset to zero. counter. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH:ADRESL to the desired location). TABLE 2-3: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF (Note 4) PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF (Note 4) PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE (Note 4) IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP (Note 4) PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF (Note 4) PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE (Note 4) IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP (Note 4) ADRESH A/D Result Register High Byte (Note 4) ADRESL A/D Result Register Low Byte (Note 4) ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON (Note 4) ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 (Note 4) ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 (Note 4) PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 (Note 4) TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register (Note 4) PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Note 4) TRISB PORTB Data Direction Control Register (Note 4) LATB PORTB Data Latch Register (Read and Write to Data Latch) (Note 4) PORTE(1) — — — — RE3(3) RE2 RE1 RE0 (Note 4) TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 (Note 4) LATE(1) — — — — — PORTE Data Latch Register (Note 4) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These registers and/or bits are not implemented on PIC18F2423/2523 devices and are read as ‘0’. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. 4: For these Reset values, see Section 4.0 “Reset” of the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). DS39755C-page 34 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 3.0 SPECIAL FEATURES OF THE 3.1 Device ID Registers CPU The Device ID registers are read-only registers. They identify the device type and revision for device pro- Note: For additional details on the Configuration grammers and can be read by firmware using table bits, refer to Section 23.1 “Configuration reads. Bits” in the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). Device ID informa- tion presented in this section is for the PIC18F2423/2523/4423/4523 devices only. TABLE 3-1: DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 3FFFFEh DEVID1(1) DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0 xxxx xxxx(2) 3FFFFFh DEVID2(1) DEV11 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 xxxx xxxx(2) Legend: x = unknown, u = unchanged, — = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: DEVID registers are read-only and cannot be programmed by the user. 2: See Register3-1 and Register3-2 for DEVID1 and DEVID2 values. REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2423/2523/4423/4523 R R R R R R R R DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 DEV<3:0>: Device ID bits 1101 = PIC18F4423 1001 = PIC18F4523 0101 = PIC18F2423 0001 = PIC18F2523 bit 3-0 REV<3:0>: Revision ID bits These bits are used to indicate the device revision. © 2009 Microchip Technology Inc. DS39755C-page 35

PIC18F2423/2523/4423/4523 REGISTER 3-2: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2423/2523/4423/4523 R R R R R R R R DEV11(1) DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-0 DEV<11:4>: Device ID bits(1) These bits are used with the DEV<3:0> bits in Device ID Register 1 to identify the part number. 0001 0001 = PIC18F2423/2523 devices 0001 0000 = PIC18F4423/4523 devices Note 1: These values for DEV<11:4> may be shared with other devices. The specific device is always identified by using the entire DEV<11:0> bit sequence. DS39755C-page 36 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 4.0 ELECTRICAL CHARACTERISTICS Note: Other than some basic data, this section documents only the PIC18F2423/2523/4423/4523 devices’ specifi- cations that differ from those of the PIC18F2420/2520/4420/4520 devices. For detailed information on the electrical specifications shared by the PIC18F2423/2523/4423/4523 and PIC18F2420/2520/4420/4520 devices, see the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39755C-page 37

PIC18F2423/2523/4423/4523 FIGURE 4-1: PIC18F2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18F2423/2523/4423/4523 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 4-2: PIC18F2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V 5.0V PIC18F2423/2523/4423/4523 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 25 MHz Frequency DS39755C-page 38 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 FIGURE 4-3: PIC18LF2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LF2423/2523/4423/4523 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz 40 MHz Frequency FMAX = (16.36MHz/V) (VDDAPPMIN – 2.0V) + 4MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. © 2009 Microchip Technology Inc. DS39755C-page 39

PIC18F2423/2523/4423/4523 TABLE 4-1: A/D CONVERTER CHARACTERISTICS:PIC18F2423/2523/4423/4523 (INDUSTRIAL) PIC18LF2423/2523/4423/4523 (INDUSTRIAL) Param Sym Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 12 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — <±1 ±2.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V — — ±2.0 LSB VDD = 5.0V A04 EDL Differential Linearity Error — <±1 +1.5/-1.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V — — +1.5/-1.0 LSB VDD = 5.0V A06 EOFF Offset Error — <±1 ±5 LSB VDD = 3.0V ΔVREF ≥ 3.0V — — ±3 LSB VDD = 5.0V A07 EGN Gain Error — <±1 ±1.25 LSB VDD = 3.0V ΔVREF ≥ 3.0V — — ±2.00 LSB VDD = 5.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 3 — VDD – VSS V For 12-bit resolution. (VREFH – VREFL) A21 VREFH Reference Voltage High VSS + 3.0V — VDD + 0.3V V For 12-bit resolution. A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V For 12-bit resolution. A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended — — 2.5 kΩ Impedance of Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. DS39755C-page 40 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 FIGURE 4-4: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 . . . . . . A/D DATA 11 10 9 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 4-2: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXXXX 0.8 12.5(1) μs TOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μs VDD = 3.0V; TOSC based, VREF full range PIC18FXXXX — 1 μs A/D RC mode PIC18LFXXXX — 3 μs VDD = 3.0V; A/D RC mode 131 TCNV Conversion Time 13 14 TAD (not including acquisition time)(2) 132 TACQ Acquisition Time(3) 1.4 — μs 135 TSWC Switching Time from Convert → Sample — (Note 4) 137 TDIS Discharge Time 0.2 — μs Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. © 2009 Microchip Technology Inc. DS39755C-page 41

PIC18F2423/2523/4423/4523 NOTES: DS39755C-page 42 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 5.0 PACKAGING INFORMATION For packaging information, see Section 28.0 “Packaging Information” in the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). © 2009 Microchip Technology Inc. DS39755C-page 43

PIC18F2423/2523/4423/4523 NOTES: DS39755C-page 44 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (June 2006) The differences between the devices listed in this data Original data sheet for PIC18F2423/2523/4423/4523 sheet are shown in TableB-1. devices. Revision B (January 2007) This revision includes updates to the packaging diagrams. Revision C (September 2009) Electrical specifications updated. Preliminary condition status removed. Converted document to the “mini data sheet” format. TABLE B-1: DEVICE DIFFERENCES Features PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523 Program Memory (Bytes) 16384 32768 16384 32768 Program Memory (Instructions) 8192 16384 8192 16384 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 2 2 1 1 Enhanced 0 0 1 1 Capture/Compare/PWM Modules Parallel Communications (PSP) No No Yes Yes 12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Packages 28-Pin PDIP 28-Pin PDIP 40-Pin PDIP 40-Pin PDIP 28-Pin SOIC 28-Pin SOIC 44-Pin TQFP 44-Pin TQFP 28-Pin QFN 28-Pin QFN 44-Pin QFN 44-Pin QFN © 2009 Microchip Technology Inc. DS39755C-page 45

PIC18F2423/2523/4423/4523 APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the This section discusses how to migrate from a Baseline ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device are due to the differences in the process technology (i.e., PIC18FXXX). used. An example of this type of conversion is from a The following are the list of modifications over the PIC16C74A to a PIC16C74B. PIC16C5X microcontroller family: Not Applicable Not Currently Available DS39755C-page 46 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e., enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e., AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18C442”. The changes discussed, while device PIC18CXXX Migration”. This Application Note is specific, are generally applicable to all mid-range to available as Literature Number DS00726. enhanced device migrations. This Application Note is available as Literature Number DS00716. © 2009 Microchip Technology Inc. DS39755C-page 47

PIC18F2423/2523/4423/4523 NOTES: DS39755C-page 48 © 2009 Microchip Technology Inc.

INDEX A I A/D......................................................................................25 Internet Address.................................................................51 A/D Converter Interrupt, Configuring..........................29 Interrupt Sources Acquisition Requirements...........................................30 A/D Conversion Complete..........................................29 ADCON0 Register.......................................................25 M ADCON1 Register.......................................................25 ADCON2 Register.......................................................25 Microchip Internet Web Site................................................51 ADRESH Register.................................................25, 28 Migration from Baseline to Enhanced Devices...................46 ADRESL Register.......................................................25 Migration from High-End to Enhanced Devices..................47 Analog Port Pins, Configuring.....................................32 Migration from Mid-Range to Enhanced Devices...............47 Associated Registers..................................................34 P Configuring the Module...............................................29 Conversion Clock (TAD)..............................................31 Packaging Information........................................................43 Conversion Status (GO/DONE Bit).............................28 Pin Functions Conversions................................................................33 MCLR/VPP/RE3....................................................14, 18 Converter Characteristics...........................................40 OSC1/CLKI/RA7...................................................14, 18 Discharge....................................................................33 OSC2/CLKO/RA6.................................................14, 18 Operation in Power-Managed Modes.........................32 RA0/AN0...............................................................15, 19 Selecting and Configuring Acquisition Time...............31 RA1/AN1...............................................................15, 19 Special Event Trigger (CCP).......................................34 RA2/AN2/VREF-/CVREF.........................................15, 19 Use of the CCP2 Trigger.............................................34 RA3/AN3/VREF+...................................................15, 19 Absolute Maximum Ratings................................................37 RA4/T0CKI/C1OUT..............................................15, 19 ADCON0 Register...............................................................25 RA5/AN4/SS/HLVDIN/C2OUT..............................15, 19 GO/DONE Bit..............................................................28 RB0/INT0/FLT0/AN12...........................................16, 20 ADCON1 Register...............................................................25 RB1/INT1/AN10....................................................16, 20 ADCON2 Register...............................................................25 RB2/INT2/AN8......................................................16, 20 ADRESH Register...............................................................25 RB3/AN9/CCP2....................................................16, 20 ADRESL Register.........................................................25, 28 RB4/KBI0/AN11....................................................16, 20 Analog-to-Digital Converter. See A/D. RB5/KBI1/PGM.....................................................16, 20 RB6/KBI2/PGC.....................................................16, 20 B RB7/KBI3/PGD.....................................................16, 20 Block Diagrams RC0/T1OSO/T13CKI............................................17, 21 A/D..............................................................................28 RC1/T1OSI/CCP2.................................................17, 21 Analog Input Model.....................................................29 RC2/CCP1..................................................................17 PIC18F2423/2523 (28-Pin).........................................12 RC2/CCP1/P1A..........................................................21 PIC18F4423/4523 (40/44-Pin)....................................13 RC3/SCK/SCL......................................................17, 21 RC4/SDI/SDA.......................................................17, 21 C RC5/SDO..............................................................17, 21 Compare (CCP Module) RC6/TX/CK...........................................................17, 21 Special Event Trigger..................................................34 RC7/RX/DT...........................................................17, 21 Conversion Considerations.................................................46 RD0/PSP0..................................................................22 Customer Change Notification Service...............................51 RD1/PSP1..................................................................22 Customer Notification Service.............................................51 RD2/PSP2..................................................................22 Customer Support...............................................................51 RD3/PSP3..................................................................22 RD4/PSP4..................................................................22 D RD5/PSP5/P1B..........................................................22 Device Differences..............................................................45 RD6/PSP6/P1C..........................................................22 Device Overview...................................................................9 RD7/PSP7/P1D..........................................................22 Details on Individual Family Members........................10 RE0/RD/AN5...............................................................23 Features (table)...........................................................11 RE1/WR/AN6..............................................................23 New Core Features.......................................................9 RE2/CS/AN7...............................................................23 Other Special Features...............................................10 VDD.......................................................................17, 23 Documentation VSS.......................................................................17, 23 Related Data Sheet.......................................................9 Pinout I/O Descriptions PIC18F2423/2523......................................................14 E PIC18F4423/4523......................................................18 Electrical Characteristics.....................................................37 Power-Managed Modes Equations and A/D Operation......................................................32 A/D Acquisition Time...................................................30 A/D Minimum Charging Time......................................30 Calculating the Minimum Required Acquisition Time..................................................30 Errata....................................................................................8 DS39755C-page 49 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 R T Reader Response...............................................................52 Timing Diagrams Registers A/D Conversion...........................................................41 ADCON0 (A/D Control 0)............................................25 Timing Diagrams and Specifications ADCON1 (A/D Control 1)............................................26 A/D Conversion Requirements...................................41 ADCON2 (A/D Control 2)............................................27 V DEVID1 (Device ID 1).................................................35 DEVID2 Voltage-Frequency Graphics (Device ID 2).......................................................36 PIC18F2423/2523/4423/4523 (Extended)..................38 Revision History..................................................................45 PIC18F2423/2523/4423/4523 (Industrial)...................38 PIC18LF2423/2523/4423/4523 (Industrial).................39 S W Special Features of the CPU...............................................35 WWW Address...................................................................51 WWW, On-Line Support.......................................................8 DS39755C-page 50 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39755C-page 51

PIC18F2423/2523/4423/4523 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2423/2523/4423/4523 Literature Number: DS39755C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39755C-page 52 © 2009 Microchip Technology Inc.

PIC18F2423/2523/4423/4523 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18F4523-I/P 301 = Industrial temp., PDIP Range package, Extended VDD limits, QTP pattern #301. b) PIC18F4523-I/PT = Industrial temp., TQFP package, Extended VDD limits. Device PIC18F2423(1), PIC18F2523(1), PIC18F4423T(2), c) PIC18F4523-E/P = Extended temp., PDIP PIC18F4523T(2); package, normal VDD limits. VDD range 4.2V to 5.5V PIC18F2423(1), PIC18F2523(1), PIC18F4423T(2), PIC18F4523T(2); VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package PT = TQFP (Thin Quad Flat pack) ML = QFN Note1: F = Standard Voltage Range SO = SOIC LF = Wide Voltage Range SP = Skinny Plastic DIP 2: T = In tape and reel PLCC, and TQFP P = PDIP packages only. Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) © 2009 Microchip Technology Inc. DS39755C-page 53

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4080 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://support.microchip.com Web Address: Fax: 852-2401-3431 India - Pune France - Paris www.microchip.com Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 ADtullaunthta, GA Fax: 61-2-9868-6755 Japan - Yokohama Germany - Munich Tel: 678-957-9614 China - Beijing Tel: 81-45-471- 6166 Tel: 49-89-627-144-0 Tel: 86-10-8528-2100 Fax: 49-89-627-144-44 Fax: 678-957-1455 Fax: 81-45-471-6122 Fax: 86-10-8528-2104 Italy - Milan Boston Korea - Daegu Westborough, MA China - Chengdu Tel: 82-53-744-4301 Tel: 39-0331-742611 Tel: 774-760-0087 Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781 Fax: 774-760-0088 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Chicago China - Hong Kong SAR Tel: 82-2-554-7200 Tel: 31-416-690399 Itasca, IL Tel: 852-2401-1200 Fax: 82-2-558-5932 or Fax: 31-416-690340 Tel: 630-285-0071 Fax: 852-2401-3431 82-2-558-5934 Spain - Madrid Fax: 630-285-0075 China - Nanjing Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Cleveland Tel: 86-25-8473-2460 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Independence, OH Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 UK - Wokingham Tel: 216-447-0464 China - Qingdao Malaysia - Penang Tel: 44-118-921-5869 Fax: 216-447-0643 Tel: 86-532-8502-7355 Tel: 60-4-227-8870 Fax: 44-118-921-5820 Dallas Fax: 86-532-8502-7205 Fax: 60-4-227-4068 Addison, TX China - Shanghai Philippines - Manila Tel: 972-818-7423 Tel: 86-21-5407-5533 Tel: 63-2-634-9065 Fax: 972-818-2924 Fax: 86-21-5407-5066 Fax: 63-2-634-9069 Detroit China - Shenyang Singapore Farmington Hills, MI Tel: 86-24-2334-2829 Tel: 65-6334-8870 Tel: 248-538-2250 Fax: 86-24-2334-2393 Fax: 65-6334-8850 Fax: 248-538-2260 China - Shenzhen Taiwan - Hsin Chu Kokomo Tel: 86-755-8203-2660 Tel: 886-3-6578-300 Kokomo, IN Fax: 86-755-8203-1760 Fax: 886-3-6578-370 Tel: 765-864-8360 Fax: 765-864-8387 China - Wuhan Taiwan - Kaohsiung Tel: 86-27-5980-5300 Tel: 886-7-536-4818 Los Angeles Fax: 86-27-5980-5118 Fax: 886-7-536-4803 Mission Viejo, CA Tel: 949-462-9523 China - Xiamen Taiwan - Taipei Tel: 86-592-2388138 Tel: 886-2-2500-6610 Fax: 949-462-9608 Fax: 86-592-2388130 Fax: 886-2-2508-0102 Santa Clara China - Xian Thailand - Bangkok Santa Clara, CA Tel: 408-961-6444 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Fax: 408-961-6445 Fax: 86-29-8833-7256 Fax: 66-2-694-1350 China - Zhuhai Toronto Mississauga, Ontario, Tel: 86-756-3210040 Canada Fax: 86-756-3210049 Tel: 905-673-0699 Fax: 905-673-6509 03/26/09 DS39755C-page 54 © 2009 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F2423-E/ML PIC18F2423-E/SO PIC18F2423-E/SP PIC18F2423-I/ML PIC18F2423-I/SO PIC18F2423-I/SP PIC18F2423T-I/ML PIC18F2423T-I/SO PIC18F2523-E/ML PIC18F2523-E/SO PIC18F2523-E/SP PIC18F2523-I/ML PIC18F2523-I/SO PIC18F2523-I/SP PIC18F2523T-I/ML PIC18F2523T-I/SO PIC18F4423-E/ML PIC18F4423-E/P PIC18F4423-E/PT PIC18F4423-I/ML PIC18F4423-I/P PIC18F4423-I/PT PIC18F4423T-I/ML PIC18F4423T-I/PT PIC18LF2423-I/ML PIC18LF2423-I/SO PIC18LF2423-I/SP PIC18LF2523-I/ML PIC18LF2523-I/SO PIC18LF2523- I/SP PIC18LF4423-I/ML PIC18LF4423-I/P PIC18LF4423-I/PT PIC18LF4523-I/ML PIC18LF4523-I/P PIC18LF4523- I/PT PIC18LF2423T-I/ML PIC18LF2423T-I/SO PIC18LF2523T-I/ML PIC18LF2523T-I/SO PIC18LF4423T-I/ML PIC18LF4423T-I/PT PIC18LF4523T-I/ML PIC18LF4523T-I/PT PIC18F4523-I/ML PIC18F4523T-I/ML PIC18F4523-I/P PIC18F4523-E/PT PIC18F4523-E/ML PIC18F4523-I/PT PIC18F4523T-I/PT PIC18F4523-E/P