PIC18F2221/2321/4221/4321 Family Data Sheet Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc. DS39689F

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39689F-page 2 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology Power-Managed Modes: Peripheral Highlights (Continued): • Run: CPU On, Peripherals On • Master Synchronous Serial Port (MSSP) module • Idle: CPU Off, Peripherals On Supporting 3-Wire SPI (all 4 modes) and I2C™ • Sleep: CPU Off, Peripherals Off Master and Slave modes • Idle mode Currents Down to 2.5μA Typical • Enhanced Addressable USART module: • Sleep mode Currents Down to 500nA Typical - Supports RS-485, RS-232 and LIN/J2602 • Timer1 Oscillator: 1.8μA, 32kHz, 2V Typical - Auto-wake-up on Start bit • Watchdog Timer: 1.6μA, 2V Typical - Auto-Baud Detect • Two-Speed Oscillator Start-up • 10-Bit, up to 13-Channel Analog-to-Digital Converter module (A/D): Flexible Oscillator Structure: - Auto-acquisition capability - Conversion available during Sleep • Four Crystal modes, up to 40MHz • Dual Analog Comparators with Input Multiplexing • 4x Phase Lock Loop (PLL) – Available for Crystal • Programmable 16-Level High/Low-Voltage and Internal Oscillators Detection (HLVD) module: • Two External RC modes, up to 4 MHz - Supports interrupt on High/Low-Voltage Detection • Two External Clock modes, up to 40 MHz • Internal Oscillator Block: Special Microcontroller Features: - 8 user-selectable frequencies, from 31kHz to 8MHz • C Compiler Optimized Architecture: - Provides a complete range of clock speeds - Optional extended instruction set designed to from 31kHz to 32MHz when used with PLL optimize re-entrant code - User-tunable to compensate for frequency drift • 100,000 Erase/Write Cycle Enhanced Flash • Secondary Oscillator using Timer1 @ 32 kHz Program Memory Typical • Fail-Safe Clock Monitor • 1,000,000 Erase/Write Cycle Data EEPROM - Allows for safe shutdown if peripheral clock stops Memory Typical • Flash/Data EEPROM Retention: 100 Years Typical Peripheral Highlights: • Self-Programmable under Software Control • Priority Levels for Interrupts • High-Current Sink/Source 25mA/25mA • 8 x 8 Single-Cycle Hardware Multiplier • Three Programmable External Interrupts • Extended Watchdog Timer (WDT): • Four Input Change Interrupts - Programmable period from 4ms to 131s • Up to 2 Capture/Compare/PWM (CCP) modules, • Single-Supply 5V In-Circuit Serial one with Auto-Shutdown (28-pin devices) Programming™ (ICSP™) via Two Pins • Enhanced Capture/Compare/PWM (ECCP) • In-Circuit Debug (ICD) via Two Pins module (40/44-pin devices only): • Wide Operating Voltage Range: 2.0V to 5.5V - One, two or four PWM outputs • Programmable Brown-out Reset (BOR) with - Selectable polarity Software Enable Option) - Programmable dead time - Auto-shutdown and auto-restart - Device (FblyaPtserohsg)ra#mI nS sMintergumlceo-tiWroynosrd ( SbyRDtAaetsMa) MEe(EbmPyoRterOys)M I/O A1/D0- B(ciht) (EPCCWCCPMP/) SPMI SSMIP2aCs™ter EUSART Comp. 8T/i1m6e-Brsit PIC18F2221 4K 2048 512 256 25 10 2/0 Y Y 1 2 1/3 PIC18F2321 8K 4096 512 256 25 10 2/0 Y Y 1 2 1/3 PIC18F4221 4K 2048 512 256 36 13 1/1 Y Y 1 2 1/3 PIC18F4321 8K 4096 512 256 36 13 1/1 Y Y 1 2 1/3 © 2009 Microchip Technology Inc. DS39689F-page 3

PIC18F2221/2321/4221/4321 FAMILY Pin Diagrams 28-Pin SPDIP, SOIC, SSOP MCLR/VPP/RE3 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6//KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 25 RB4/KBI0/AN11 RA3/AN3/VREF+ 5 1 1 24 RB3/AN9/CCP2 2 2 RA4/T0CKI/C1OUT 6 2 3 23 RB2/INT2/AN8 RA5/AN4/SS/HLVDIN/C2OUT 7 F2 F2 22 RB1/INT1/AN10 VSS 8 18 18 21 RB0/INT0/FLT0/AN12 OSC1/CLKI/RA7 9 C C 20 VDD OSC2/CLKO/RA6 10 PI PI 19 VSS RC0/T1OSO/T13CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA 28-Pin QFN RE3GDGCGMN11 N1N0V/PPBI3/PBI2/PBI1/PBI0/A AAR/KKKK A1/A0/CLB7/B6/B5/B4/ RRMRRRR 28272625242322 RA2/AN2/VREF-/CVREF 1 21 RB3/AN9/CCP2(1) RA3/AN3/VREF+ 2 20 RB2/INT2/AN8 RA4/T0CKI/C1OUT 3 PIC18F2221 19 RB1/INT1/AN10 RA5/AN4/SS/HLVDIN/C2OUT 4 PIC18F2321 18 RB0/INT0/FLT0/AN12 VSS 5 17 VDD OSC1/CLKI/RA7 6 16 VSS OSC2/CLKO/RA6 7 15 RC7/RX/DT 8 91011121314 OSO/T13CKI(1)OSI/CCP2RC2/CCP1C3/SCK/SCLC4/SDI/SDARC5/SDORC6/TX/CK C0/T1C1/T1 RR RR Note1: RB3 is the alternate pin for CCP2 multiplexing. DS39689F-page 4 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY Pin Diagrams (Continued) 40-Pin PDIP MCLR/VPP/RE3 1 40 RB7/KBI3/PGD RA0/AN0 2 39 RB6/KBI2/PGC RA1/AN1 3 38 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 37 RB4/KBI0/AN11 RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2 RA4/T0CKI/C1OUT 6 35 RB2/INT2/AN8 RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/INT1/AN10 RE0/RD/AN5 8 1 1 33 RB0/INT0/FLT0/AN12 2 2 RE1/WR/AN6 9 2 3 32 VDD RE2/CS/AN7 10 F4 F4 31 VSS VDD 11 18 18 30 RD7/PSP7/P1D VSS 12 C C 29 RD6/PSP6/P1C OSC1/CLKI/RA7 13 PI PI 28 RD5/PSP5/P1B OSC2/CLKO/RA6 14 27 RD4/PSP4 RC0/T1OSO/T13CKI 15 26 RC7/RX/DT RC1/T1OSI/CCP2 16 25 RC6/TX/CK RC2/CCP1/P1A 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2 (1)2CKI 44-Pin QFN(2) TX/CKSDOSDI/SDAPSP3PSP2PSP1PSP0SCK/SCLCCP1/P1AT1OSI/CCPT1OSO/T13 6/5/4/3/2/1/0/3/2/1/0/ CCCDDDDCCCC RRRRRRRRRRR 43210987654 44444333333 RC7/RX/DT 1 33 OSC2/CLKO/RA6 RD4/PSP4 2 32 OSC1/CLKI/RA7 RD5/PSP5/P1B 3 31 VSS RD6/PSP6/P1C 4 30 VSS RD7/PSP7/P1D 5 PIC18F4221 29 VDD VSS 6 PIC18F4321 28 VDD VDD 7 27 RE2/CS/AN7 VDD 8 26 RE1/WR/AN6 RB0/INT0/FLT0/AN12 9 25 RE0/RD/AN5 RB1/INT1/AN10 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB2/INT2/AN8 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 (1)RB3/AN9/CCP2NCRB4/KBI0/AN11RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDMCLR/V/RE3PPRA0/AN0RA1/AN12/AN2/V-/CVREFREFRA3/AN3/V+REF A R Note1: RB3 is the alternate pin for CCP2 multiplexing. 2: For the QFN package, it is recommended that the bottom pad be connected to VSS. © 2009 Microchip Technology Inc. DS39689F-page 5

PIC18F2221/2321/4221/4321 FAMILY Pin Diagrams (Continued) 44-Pin TQFP 1) (2 TX/CKSDOSDI/SDAPSP3PSP2PSP1PSP0SCK/SCLCCP1/P1AT1OSI/CCP 6/5/4/3/2/1/0/3/2/1/ CCCDDDDCCCC RRRRRRRRRRN 43210987654 44444333333 RC7/RX/DT 1 33 NC RD4/PSP4 2 32 RC0/T1OSO/T13CKI RD5/PSP5/P1B 3 31 OSC2/CLKO/RA6 RD6/PSP6/P1C 4 30 OSC1/CLKI/RA7 RD7/PSP7/P1D 5 PIC18F4221 29 VSS VSS 6 PIC18F4321 28 VDD VDD 7 27 RE2/CS/AN7 RB0/INT0/FLT0/AN12 8 26 RE1/WR/AN6 RB1/INT1/AN10 9 25 RE0/RD/AN5 RB2/INT2/AN8 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB3/AN9/CCP2(1) 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 CC1MCD301F+ NNRB4/KBI0/AN1RB5/KBI1/PGRB6/KBI2/PGRB7/KBI3/PGMCLR/V/REPPRA0/ANRA1/ANN2/V-/CVREFRERA3/AN3/VREF A 2/ A R Note 1: RB3 is the alternate pin for CCP2 multiplexing. DS39689F-page 6 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Guidelines for Getting Started with PIC18F Microcontrollers.....................................................................................................25 3.0 Oscillator Configurations............................................................................................................................................................29 4.0 Power-Managed Modes.............................................................................................................................................................39 5.0 Reset..........................................................................................................................................................................................47 6.0 Memory Organization.................................................................................................................................................................59 7.0 Flash Program Memory..............................................................................................................................................................79 8.0 Data EEPROM Memory.............................................................................................................................................................89 9.0 8 x 8 Hardware Multiplier............................................................................................................................................................95 10.0 Interrupts....................................................................................................................................................................................97 11.0 I/O Ports...................................................................................................................................................................................111 12.0 Timer0 Module.........................................................................................................................................................................129 13.0 Timer1 Module.........................................................................................................................................................................133 14.0 Timer2 Module.........................................................................................................................................................................139 15.0 Timer3 Module.........................................................................................................................................................................141 16.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................145 17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................153 18.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................167 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................211 20.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................233 21.0 Comparator Module..................................................................................................................................................................243 22.0 Comparator Voltage Reference Module...................................................................................................................................249 23.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................253 24.0 Special Features of the CPU....................................................................................................................................................259 25.0 Instruction Set Summary..........................................................................................................................................................279 26.0 Development Support...............................................................................................................................................................329 27.0 Electrical Characteristics..........................................................................................................................................................333 28.0 Packaging Information..............................................................................................................................................................373 Appendix A: Revision History.............................................................................................................................................................385 Appendix B: Device Differences........................................................................................................................................................386 Appendix C: Conversion Considerations...........................................................................................................................................387 Appendix D: Migration from Baseline to Enhanced Devices..............................................................................................................387 Appendix E: Migration From Mid-Range to Enhanced Devices.........................................................................................................388 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................388 Index................................................................................................................................................................................................. 389 The Microchip Web Site.....................................................................................................................................................................399 Customer Change Notification Service..............................................................................................................................................399 Customer Support..............................................................................................................................................................................399 Reader Response..............................................................................................................................................................................400 PIC18F2221/2321/4221/4321 Product Identification System............................................................................................................401 © 2009 Microchip Technology Inc. DS39689F-page 7

PIC18F2221/2321/4221/4321 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39689F-page 8 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device specific information for the following devices: All of the devices in the PIC18F2221/2321/4221/4321 family offer ten different oscillator options, allowing • PIC18F2221 • PIC18LF2221 users a wide range of choices in developing application • PIC18F2321 • PIC18LF2321 hardware. These include: • PIC18F4221 • PIC18LF4221 • Four Crystal modes, using crystals or ceramic resonators. • PIC18F4321 • PIC18LF4321 • Two External Clock modes, offering the option of This family offers the advantages of all PIC18 micro- using two pins (oscillator input and a divide-by-4 controllers – namely, high computational performance at clock output) or one pin (oscillator input, with the an economical price – with the addition of high- second pin reassigned as general I/O). endurance, Enhanced Flash program memory. On top of • Two External RC Oscillator modes with the same these features, the PIC18F2221/2321/4221/4321 family pin options as the External Clock modes. introduces design enhancements that make these micro- controllers a logical choice for many high-performance, • Two Internal Oscillator modes which provide power sensitive applications. an 8MHz clock and an INTRC source (approximately 31kHz), as well as a range of 1.1 New Core Features 6 user-selectable clock frequencies, between 125kHz to 4MHz, for a total of 8 clock frequencies. 1.1.1 nanoWatt TECHNOLOGY One or both of the oscillator pins can be used for general purpose I/O. All of the devices in the PIC18F2221/2321/4221/4321 • A Phase Lock Loop (PLL) frequency multiplier, family incorporate a range of features that can signifi- available to both the high-speed crystal and cantly reduce power consumption during operation. internal oscillator modes, which allows clock Key items include: speeds of up to 40MHz. Used with the internal • Alternate Run Modes: By clocking the controller oscillator, the PLL gives users a complete selection from the Timer1 source or the internal oscillator of clock speeds, from 31kHz to 32MHz – all block, power consumption during code execution without using an external crystal or clock circuit. can be reduced by as much as 90%. Besides its availability as a clock source, the internal • Multiple Idle Modes: The controller can also run oscillator block provides a stable reference source that with its CPU core disabled but the peripherals still gives the family additional features for robust active. In these states, power consumption can be operation: reduced even further, to as little as 4% of normal • Fail-Safe Clock Monitor: This option constantly operation requirements. monitors the main clock source against a reference • On-the-Fly Mode Switching: The signal provided by the internal oscillator. If a clock power-managed modes are invoked by user code failure occurs, the controller is switched to the during operation, allowing the user to incorporate internal oscillator block, allowing for continued power-saving ideas into their application’s low-speed operation or a safe application software design. shutdown. • Low Consumption in Key Modules: The • Two-Speed Start-up: This option allows the power requirements for both Timer1 and the internal oscillator to serve as the clock source Watchdog Timer are minimized. See from Power-on Reset, or wake-up from Sleep Section27.0 “Electrical Characteristics” for mode, until the primary clock source is available. values. © 2009 Microchip Technology Inc. DS39689F-page 9

PIC18F2221/2321/4221/4321 FAMILY 1.2 Other Special Features 1.3 Details on Individual Family Members • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are Devices in the PIC18F2221/2321/4221/4321 family are rated to last for many thousands of erase/write available in 28-pin and 40/44-pin packages. Block cycles – up to 100,000 for program memory and diagrams for the two groups are shown in Figure1-1 and 1,000,000 for EEPROM. Data retention without Figure1-2. refresh is conservatively estimated to be greater The devices are differentiated from each other in five than 40 years. ways: • Self-Programmability: These devices can write to their own program memory spaces under internal 1. Flash program memory (4 Kbytes for software control. By using a bootloader routine, PIC18F2221/4221 devices, 8 Kbytes for located in the protected Boot Block at the top of PIC18F2321/4321). program memory, it becomes possible to create an 2. A/D channels (10 for 28-pin devices, 13 for application that can update itself in the field. 40/44-pin devices). • Extended Instruction Set: The PIC18F2221/ 3. I/O ports (3 bidirectional ports on 28-pin devices, 2321/4221/4321 family introduces an optional 5 bidirectional ports on 40/44-pin devices). extension to the PIC18 instruction set, which adds 4. CCP and Enhanced CCP implementation 8 new instructions and an Indexed Addressing (28-pin devices have 2 standard CCP mode. This extension, enabled as a device con- modules, 40/44-pin devices have one standard figuration option, has been specifically designed CCP module and one ECCP module). to optimize re-entrant application code originally 5. Parallel Slave Port (present only on 40/44-pin developed in high-level languages, such as C. devices). • Enhanced CCP Module: In PWM mode, this All other features for devices in this family are identical. module provides 1, 2 or 4 modulated outputs for These are summarized in Table1-1. controlling half-bridge and full-bridge drivers. Other features include auto-shutdown, for The pinouts for all devices are listed in Table1-2 and disabling PWM outputs on interrupt or other select Table1-3. conditions and auto-restart, to reactivate outputs Like all Microchip PIC18 devices, members of the once the condition has cleared. PIC18F2221/2321/4221/4321 family are available as • Enhanced Addressable USART: This serial both standard and low-voltage devices. Standard communication module is capable of standard devices with Enhanced Flash memory, designated with RS-232 operation and provides support for the an “F” in the part number (such as PIC18F2321), LIN/J2602 bus protocol. Other enhancements accommodate an operating VDD range of 4.2V to 5.5V. include automatic baud rate detection and a 16-bit Low-voltage parts, designated by “LF” (such as Baud Rate Generator for improved resolution. PIC18LF2321), function over an extended VDD range When the microcontroller is using the internal of 2.0V to 5.5V. oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. • Extended Watchdog Timer (WDT): This Enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section27.0 “Electrical Characteristics” for time-out periods. DS39689F-page 10 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-1: DEVICE FEATURES Features PIC18F2221 PIC18F2321 PIC18F4221 PIC18F4321 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 4096 8192 4096 8192 Program Memory (Instructions) 2048 4096 2048 4096 Data Memory (Bytes) 512 512 512 512 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 2 2 1 1 Enhanced Capture/Compare/ 0 0 1 1 PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications (PSP) No No Yes Yes 10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Programmable Low-Voltage Yes Yes Yes Yes Detect Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set Instruction Set Instruction Set Instruction Set enabled enabled enabled enabled Packages 28-pin SPDIP 28-pin SPDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 44-pin QFN 44-pin QFN 28-pin SSOP 28-pin SSOP 44-pin TQFP 44-pin TQFP 28-pin QFN 28-pin QFN © 2009 Microchip Technology Inc. DS39689F-page 11

PIC18F2221/2321/4221/4321 FAMILY FIGURE 1-1: PIC18F2221/2321 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch PORTA inc/dec logic 8 8 RA0/AN0 Data Memory RA1/AN1 21 PCLAT U PCLATH (3.9Kbytes) RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ 20 Address Latch RA4/T0CKI/C1OUT PCU PCH PCL RA5/AN4/SS/HLVDIN/C2OUT Program Counter 12 OSC2/CLKO(3)/RA6 Data Address<12> OSC1/CLKI(3)/RA7 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (4Kbytes) FSR1 Data Latch FSR2 12 PORTB RB0/INT0/FLT0/AN12 inc/dec 8 logic RB1/INT1/AN10 Table Latch RB2/INT2/AN8 RB3/AN9/CCP2(1) RB4/KBI0/AN11 Address ROM Latch RB5/KBI1/PGM Instruction Bus <16> Decode RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State Machine Decode & Control Signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T13CKI 3 8 RC1/T1OSI/CCP2(1) RC2/CCP1 BITOP W RC3/SCK/SCL 8 8 8 RC4/SDI/SDA RC5/SDO OSC1(3) Internal Power-up RC6/TX/CK Oscillator Timer 8 8 Block RC7/RX/DT OSC2(3) Oscillator ALU<8> INTRC Start-up Timer T1OSI Oscillator Power-on 8 Reset 8 MHz T1OSO Oscillator Watchdog Timer Precision MCLR(2) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBeafnedr eGnacpe PORTE In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor MCLR/VPP/RE3(2) BOR Data LVD EEPROM Timer0 Timer1 Timer2 Timer3 ADC Comparator CCP1 CCP2 MSSP EUSART 10-Bit Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section3.0 “Oscillator Configurations” for additional information. DS39689F-page 12 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 1-2: PIC18F4221/4321 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0 Data Latch RA1/AN1 inc/dec logic 8 8 RA2/AN2/VREF-/CVREF Data Memory RA3/AN3/VREF+ 21 PCLAT U PCLATH (3.9Kbytes) RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT 20 PCU PCH PCL Address Latch OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 Program Counter 12 Data Address<12> PORTB 31 Level Stack RB0/INT0/FLT0/AN12 Address Latch 4 12 4 RB1/INT1/AN10 BSR Access Program Memory STKPTR FSR0 Bank RB2/INT2/AN8 (8Kbytes) FSR1 RB3/AN9/CCP2(1) Data Latch FSR2 12 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A IR RC3/SCK/SCL RC4/SDI/SDA 8 RC5/SDO Instruction State Machine RC6/TX/CK Decode & Control Signals RC7/RX/DT Control PRODH PRODL 8 x 8 Multiply 3 8 PORTD RD0/PSP0:RD4/PSP4 BITOP W 8 8 8 RD5/PSP5/P1B RD6/PSP6/P1C OSC1(3) Internal Power-up RD7/PSP7/P1D Oscillator Timer 8 8 Block OSC2(3) Oscillator ALU<8> INTRC Start-up Timer T1OSI Oscillator Power-on 8 Reset 8 MHz T1OSO Oscillator Watchdog PORTE Timer RE0/RD/AN5 Precision MCLR(2) Single-Supply Brown-out Band Gap RE1/WR/AN6 Programming Reset Reference RE2/CS/AN7 In-Circuit Fail-Safe MCLR/VPP/RE3(2) VDD,VSS Debugger Clock Monitor BOR Data LVD EEPROM Timer0 Timer1 Timer2 Timer3 ADC Comparator ECCP1 CCP2 MSSP EUSART 10-Bit Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section3.0 “Oscillator Configurations” for additional information. © 2009 Microchip Technology Inc. DS39689F-page 13

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name SPDIP, Description Type Type SOIC, QFN SSOP MCLR/VPP/RE3 1 26 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI/RA7 9 6 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 10 7 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC, EC and INTIO modes, OSC2 pin outputs CLKO which has one-fourth the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39689F-page 14 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SPDIP, Description Type Type SOIC, QFN SSOP PORTA is a bidirectional I/O port. RA0/AN0 2 27 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 3 28 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF-/CVREF 4 1 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Comparator reference voltage output. RA3/AN3/VREF+ 5 2 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT 6 3 RA4 I/O ST Digital I/O. Open-collector output. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RA5/AN4/SS/HLVDIN/ 7 4 C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39689F-page 15

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SPDIP, Description Type Type SOIC, QFN SSOP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 21 18 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST PWM Fault input for CCP1. AN12 I Analog Analog Input 12. RB1/INT1/AN10 22 19 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. AN10 I Analog Analog Input 10. RB2/INT2/AN8 23 20 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. AN8 I Analog Analog Input 8. RB3/AN9/CCP2 24 21 RB3 I/O TTL Digital I/O. AN9 I Analog Analog Input 9. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0/AN11 25 22 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN11 I Analog Analog Input 11. RB5/KBI1/PGM 26 23 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ programming enable pin. RB6/KBI2/PGC 27 24 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-circuit debugger and ICSP programming clock pin. RB7/KBI3/PGD 28 25 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-circuit debugger and ICSP programming data pin. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39689F-page 16 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name SPDIP, Description Type Type SOIC, QFN SSOP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 11 8 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator analog output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 12 9 RC1 I/O ST Digital I/O. T1OSI I Analog Timer1 oscillator analog input. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1 13 10 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK/SCL 14 11 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O I2C Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 15 12 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O I2C I2C data I/O. RC5/SDO 16 13 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 17 14 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 18 15 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). RE3 — — — — See MCLR/VPP/RE3 pin. VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39689F-page 17

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP MCLR/VPP/RE3 1 18 18 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI/RA7 13 32 30 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; analog otherwise. CLKI I Analog External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC, EC and INTIO modes, OSC2 pin outputs CLKO which has one-fourth the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39689F-page 18 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTA is a bidirectional I/O port. RA0/AN0 2 19 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 3 20 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF-/CVREF 4 21 21 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Comparator reference voltage output. RA3/AN3/VREF+ 5 22 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT 6 23 23 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RA5/AN4/SS/HLVDIN/ 7 24 24 C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39689F-page 19

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 33 9 8 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST PWM Fault input for Enhanced CCP1. AN12 I Analog Analog input 12. RB1/INT1/AN10 34 10 9 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. AN10 I Analog Analog Input 10. RB2/INT2/AN8 35 11 10 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. AN8 I Analog Analog Input 8. RB3/AN9/CCP2 36 12 11 RB3 I/O TTL Digital I/O. AN9 I Analog Analog Input 9. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0/AN11 37 14 14 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN11 I Analog Analog input 11. RB5/KBI1/PGM 38 15 15 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-circuit debugger and ICSP programming clock pin. RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-circuit debugger and ICSP programming data pin. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39689F-page 20 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 15 34 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator analog output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 16 35 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator analog input. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1/P1A 17 36 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — Enhanced CCP1 output. RC3/SCK/SCL 18 37 37 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O I2C Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 23 42 42 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O I2C I2C data I/O. RC5/SDO 24 43 43 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 26 1 1 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39689F-page 21

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled. RD0/PSP0 19 38 38 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. RD1/PSP1 20 39 39 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. RD2/PSP2 21 40 40 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. RD3/PSP3 22 41 41 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. RD4/PSP4 27 2 2 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. RD5/PSP5/P1B 28 3 3 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. P1B O — Enhanced CCP1 output. RD6/PSP6/P1C 29 4 4 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. P1C O — Enhanced CCP1 output. RD7/PSP7/P1D 30 5 5 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. P1D O — Enhanced CCP1 output. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39689F-page 22 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 1-3: PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTE is a bidirectional I/O port. RE0/RD/AN5 8 25 25 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port (see also WR and CS pins). AN5 I Analog Analog Input 5. RE1/WR/AN6 9 26 26 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port (see CS and RD pins). AN6 I Analog Analog Input 6. RE2/CS/AN7 10 27 27 RE2 I/O ST Digital I/O. CS I TTL Chip Select control for Parallel Slave Port (see related RD and WR). AN7 I Analog Analog Input 7. RE3 — — — — — See MCLR/VPP/RE3 pin. VSS 12, 31 6, 30, 6, 29 P — Ground reference for logic and I/O pins. 31 VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins. 28, 29 NC — 13 12, 13, — — No Connect. 33, 34 Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39689F-page 23

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 24 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH PIC18F MINIMUM CONNECTIONS MICROCONTROLLERS C2(1) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F2221/2321/4221/4321 R1 DD SS family family of 8-bit microcontrollers requires attention V V R2 to a minimal set of device pin connections before MCLR proceeding with development. C1 VDD The following pins must always be connected: PIC18FXXXX C3(1) • All VDD and VSS pins VSS (see Section2.2 “Power Supply Pins”) VSS C6(1) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(1) C4(1) These pins must also be connected if they are being used in the end application: • PGC/PGD pins used for In-Circuit Serial Key (all values are recommendations): Programming™ (ICSP™) and debugging purposes C1 through C6: 0.1 μF, 20V ceramic (see Section2.4 “ICSP Pins”) C7: 10 μF, 16V tantalum or ceramic • OSCI and OSCO pins when an external oscillator R1: 10 kΩ source is used R2: 100Ω to 470Ω (see Section2.5 “External Oscillator Pins”) Note 1: The example shown is for a PIC18F device Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs. • VREF+/VREF- pins used when external voltage Other devices may have more or less pairs; adjust the number of decoupling capacitors reference for analog modules is implemented appropriately. Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1. © 2009 Microchip Technology Inc. DS39689F-page 25

PIC18F2221/2321/4221/4321 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: device Reset, and device programming The use of decoupling capacitors on every pair of and debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 μF (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented depending on the should be a low-ESR device with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01μF to 0.001μF. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1μF in parallel with 0.001μF). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC18FXXXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1≤10kΩ is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10kΩ. Ensure that the On boards with power traces running longer than six MCLR pin VIH and VIL specifications are met. inches in length, it is suggested to use a tank capacitor 2: R2≤470Ω will limit any current flowing into for integrated circuits including microcontrollers to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7μF to 47μF. DS39689F-page 26 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 2.4 ICSP Pins Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The The PGC and PGD pins are used for In-Circuit Serial grounded copper pour should be routed directly to the Programming (ICSP) and debugging purposes. It is MCU ground. Do not run any signal traces or power recommended to keep the trace length between the traces inside the ground pour. Also, if using a ICSP connector and the ICSP pins on the device as two-sided board, avoid any traces on the other side of short as possible. If the ICSP connector is expected to the board where the crystal is placed. A suggested experience an ESD event, a series resistor is recom- layout is shown in Figure2-3. mended, with the value in the range of a few tens of For additional information and design guidance on ohms, not to exceed 100Ω. oscillator circuits, please refer to these Microchip Pull-up resistors, series diodes and capacitors on the Application Notes, available at the corporate web site PGC and PGD pins are not recommended as they will (www.microchip.com): interfere with the programmer/debugger com- • AN826, “Crystal Oscillator Basics and Crystal munications to the device. If such discrete components Selection for rfPIC™ and PICmicro® Devices” are an application requirement, they should be removed from the circuit during programming and debugging. • AN849, “Basic PICmicro® Oscillator Design” Alternatively, refer to the AC/DC characteristics and • AN943, “Practical PICmicro® Oscillator Analysis timing requirements information in the respective device and Design” Flash programming specification for information on • AN949, “Making Your Oscillator Work” capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. FIGURE 2-3: SUGGESTED PLACEMENT For device emulation, ensure that the “Communication OF THE OSCILLATOR Channel Select” (i.e., PGC/PGD pins) programmed CIRCUIT into the device matches the physical connections for the ICSP to the MPLAB® ICD 2, MPLAB ICD 3 or REAL ICE™ emulator. Main Oscillator 13 For more information on the ICD 2, ICD 3 and REAL Guard Ring 14 ICE emulator connection requirements, refer to the following documents that are available on the 15 Microchip web site. Guard Trace 16 • “MPLAB® ICD 2 In-Circuit Debugger User’s Secondary 17 Guide” (DS51331) Oscillator 18 • “Using MPLAB® ICD 2” (poster) (DS51265) • “MPLAB® ICD 2 Design Advisory” (DS51566) 19 • “Using MPLAB® ICD 3” (poster) (DS51765) 20 • “MPLAB® ICD 3 Design Advisory” (DS51764) • “MPLAB® REAL ICE™ In-Circuit Emulator User’s 2.6 Unused I/Os Guide” (DS51616) • “Using MPLAB® REAL ICE™ In-Circuit Emulator” Unused I/O pins should be configured as outputs and (poster) (DS51749) driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the 2.5 External Oscillator Pins output to logic low. Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. © 2009 Microchip Technology Inc. DS39689F-page 27

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 28 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 3.0 OSCILLATOR FIGURE 3-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (XT, LP, HS OR HSPLL 3.1 Oscillator Types CONFIGURATION) The PIC18F2221/2321/4221/4321 family of devices C1(1) OSC1 can be operated in ten different oscillator modes. The To user can program the Configuration bits, FOSC<3:0>, Internal in Configuration Register 1H to select one of these ten XTAL (3) Logic RF modes: Sleep 1. LP Low-Power Crystal RS(2) 2. XT Crystal/Resonator C2(1) OSC2 PIC18FXXXX 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator Note 1: See Table3-1 and Table3-2 for initial values of with PLL enabled C1 and C2. 5. RC External Resistor/Capacitor with 2: A series resistor (RS) may be required for AT FOSC/4 output on RA6 strip cut crystals. 6. RCIO External Resistor/Capacitor with I/O 3: RF varies with the oscillator mode chosen. on RA6 7. INTIO1 Internal Oscillator with FOSC/4 output TABLE 3-1: CAPACITOR SELECTION FOR on RA6 and I/O on RA7 CERAMIC RESONATORS 8. INTIO2 Internal Oscillator with I/O on RA6 and RA7 Typical Capacitor Values Used: 9. EC External Clock with FOSC/4 output Mode Freq OSC1 OSC2 10. ECIO External Clock with I/O on RA6 XT 3.58 MHz 22 pF 22 pF 3.2 Crystal Oscillator/Ceramic Capacitor values are for design guidance only. Resonators Different capacitor values may be required to produce acceptable oscillator operation. The user should test In XT, LP, HS or HSPLL Oscillator modes, a crystal or the performance of the oscillator over the expected ceramic resonator is connected to the OSC1 and VDD and temperature range for the application. Refer OSC2 pins to establish oscillation. Figure3-1 shows to the following application notes for oscillator specific the pin connections. information: The oscillator design requires the use of a parallel cut • AN588, “PIC® Microcontroller Oscillator Design crystal. Guide” Note: Use of a series cut crystal may give a • AN826, “Crystal Oscillator Basics and Crystal frequency out of the crystal manufacturer’s Selection for rfPIC® and PIC® Devices” specifications. • AN849, “Basic PIC® Oscillator Design” • AN943, “Practical PIC® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table3-2 for additional information. Note: When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor may be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330Ω. © 2009 Microchip Technology Inc. DS39689F-page 29

PIC18F2221/2321/4221/4321 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR An external clock source may also be connected to the QUARTZ CRYSTALS OSC1 pin in the HS mode, as shown in Figure3-2. When operated in this mode, parameters D033 and Typical Capacitor Values D043 apply. Crystal Tested: Osc Type Freq C1 C2 FIGURE 3-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC LP 32 kHz 22 pF 22 pF CONFIGURATION) XT 1 MHz 22 pF 22 pF 4 MHz 22 pF 22 pF HS 4 MHz 22 pF 22 pF Clock from OSC1 10 MHz 22 pF 22 pF Ext. System PIC18FXXXX 20 MHz 22 pF 22 pF Open OSC2 (HS Mode) 25 MHz 22 pF 22 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce 3.3 External Clock Input acceptable oscillator operation. The user should test the performance of the oscillator over the expected The EC and ECIO Oscillator modes require an external VDD and temperature range for the application. Refer clock source to be connected to the OSC1 pin. There is to the following application notes for oscillator specific no oscillator start-up time required after a Power-on information: Reset or after an exit from Sleep mode. • AN588, “PIC® Microcontroller Oscillator Design In the EC Oscillator mode, the oscillator frequency Guide” divided by 4 is available on the OSC2 pin. This signal • AN826, “Crystal Oscillator Basics and Crystal may be used for test purposes or to synchronize other Selection for rfPIC® and PIC® Devices” logic. Figure3-3 shows the pin connections for the EC • AN849, “Basic PIC® Oscillator Design” Oscillator mode. • AN943, “Practical PIC® Oscillator Analysis and FIGURE 3-3: EXTERNAL CLOCK Design” INPUT OPERATION • AN949, “Making Your Oscillator Work” (EC CONFIGURATION) See the notes following this table for additional information. Clock from OSC1/CLKI Ext. System PIC18FXXXX Note1: Higher capacitance increases the stability FOSC/4 OSC2/CLKO of the oscillator but also increases the start-up time. The ECIO Oscillator mode functions like the EC mode, 2: When operating below 3V VDD, or when except that the OSC2 pin becomes an additional using certain ceramic resonators at any general purpose I/O pin. The I/O pin becomes bit 6 of voltage, it may be necessary to use the PORTA (RA6). Figure3-4 shows the pin connections HS mode or switch to a crystal oscillator. for the ECIO Oscillator mode. When operated in this 3: Since each resonator/crystal has its own mode, parameters D033A and D043A apply. characteristics, the user should consult the resonator/crystal manufacturer for FIGURE 3-4: EXTERNAL CLOCK appropriate values of external INPUT OPERATION components. (ECIO CONFIGURATION) 4: Rs may be required to avoid overdriving crystals with low drive level specification. Clock from OSC1/CLKI 5: Always verify oscillator performance over Ext. System PIC18FXXXX the VDD and temperature range that is RA6 I/O (OSC2) expected for the application. DS39689F-page 30 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 3.4 RC Oscillator 3.5 PLL Frequency Multiplier For timing insensitive applications, the RC and RCIO A Phase Locked Loop (PLL) circuit is provided as an Oscillator modes offer additional cost savings. The option for users who wish to use a lower frequency actual oscillator frequency is a function of several oscillator circuit or to clock the device up to its highest factors: rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due • supply voltage to high-frequency crystals or users who require higher • values of the external resistor (REXT) and clock speeds from an internal oscillator. capacitor (CEXT) • operating temperature 3.5.1 HSPLL OSCILLATOR MODE Given the same device, operating voltage, temperature The HSPLL mode makes use of the HS mode oscillator and component values, there will also be unit-to-unit for frequencies up to 10 MHz. A PLL then multiplies the frequency variations. These are due to factors such as: oscillator output frequency by 4 to produce an internal • normal manufacturing variation clock frequency up to 40 MHz. The PLLEN bit is not available when this mode is configured as the primary • difference in lead frame capacitance between clock source. package types (especially for low CEXT values) • variations within the tolerance of limits of REXT The PLL is only available to the crystal oscillator when and CEXT the FOSC<3:0> Configuration bits are programmed for HSPLL mode (= 0110). In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal FIGURE 3-7: HSPLL BLOCK DIAGRAM may be used for test purposes or to synchronize other logic. Figure3-5 shows how the R/C combination is HS Oscillator Enable connected. PLL Enable (from Configuration Register 1H) FIGURE 3-5: RC OSCILLATOR MODE VDD OSC2 Phase HS Mode FIN Comparator REXT Internal OSC1 Crystal FOUT OSC1 Osc Clock CEXT Loop PIC18FXXXX Filter VSS OSC2/CLKO FOSC/4 ÷4 VCO Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ XSYSCLK 20 pF ≤ CEXT ≤ 300 pF U M The RCIO Oscillator mode (Figure3-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). 3.5.2 PLL AND INTOSC The PLL is also available to the internal oscillator block FIGURE 3-6: RCIO OSCILLATOR MODE when the internal oscillator block is configured as the VDD primary clock source. In this configuration, the PLL is enabled in software and generates a clock output of up REXT to 32MHz. The operation of INTOSC with the PLL is Internal described in Section3.6.4 “PLL in INTOSC Modes”. OSC1 Clock CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ 20 pF ≤ CEXT ≤ 300 pF © 2009 Microchip Technology Inc. DS39689F-page 31

PIC18F2221/2321/4221/4321 FAMILY 3.6 Internal Oscillator Block 3.6.2 INTOSC OUTPUT FREQUENCY The PIC18F2221/2321/4221/4321 family of devices The internal oscillator block is calibrated at the factory includes an internal oscillator block which generates to produce an INTOSC output frequency of 8MHz. two different clock signals; either can be used as the The INTRC oscillator operates independently of the microcontroller’s clock source. This may eliminate the INTOSC source. Any changes in INTOSC across need for external oscillator circuits on the OSC1 and/or voltage and temperature are not necessarily reflected OSC2 pins. by changes in INTRC or vice versa. The main output (INTOSC) is an 8MHz clock source, 3.6.3 OSCTUNE REGISTER which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of The INTOSC output has been calibrated at the clock frequencies from 31kHz to 4MHz. The INTOSC factory but can be adjusted in the user’s application. output is enabled when a clock frequency from 125kHz This is done by writing to TUN<4:0> to 8MHz is selected. The INTOSC output can also be (OSCTUNE<4:0>) in the OSCTUNE register enabled when 31kHz is selected, depending on the (Register3-1). INTSRC bit (OSCTUNE<7>). When the OSCTUNE register is modified, the INTOSC The other clock source is the internal RC oscillator frequency will begin shifting to the new frequency. (INTRC), which provides a nominal 31kHz output. Code execution continues during this shift. There is no INTRC is enabled if it is selected as the device clock indication that the shift has occurred. The INTRC is not source; it is also enabled automatically when any of the affected by OSCTUNE. following are enabled: The OSCTUNE register also implements the INTSRC • Power-up Timer (OSCTUNE<7>) and PLLEN (OSCTUNE<6>) bits, • Fail-Safe Clock Monitor which control certain features of the internal oscillator block. The INTSRC bit allows users to select which • Watchdog Timer internal oscillator provides the clock source when the • Two-Speed Start-up 31kHz frequency option is selected. This is covered in These features are discussed in greater detail in greater detail in Section3.7.1 “Oscillator Control Section24.0 “Special Features of the CPU”. Register”. The clock source frequency (INTOSC direct, INTRC The PLLEN bit controls the operation of the Phase direct or INTOSC postscaler) is selected by configuring Locked Loop (PLL) in Internal Oscillator modes (see the IRCF bits of the OSCCON register (page37). Figure3-10). 3.6.1 INTIO MODES FIGURE 3-10: INTOSC AND PLL BLOCK Using the internal oscillator as the clock source elimi- DIAGRAM nates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct 8 or 4 MHz PLLEN configurations are available: (OSCTUNE<6>) • In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 (see Figure3-8) for digital input and output. Phase • In INTIO2 mode, OSC1 functions as RA7 and FIN Comparator INTOSC OSC2 functions as RA6 (see Figure3-9), both for FOUT digital input and output. Loop FIGURE 3-8: INTIO1 OSCILLATOR MODE Filter RA7 I/O (OSC1) PIC18FXXXX FOSC/4 OSC2 ÷4 VCO SYSCLK CLKO X U M OSC2 X FIGURE 3-9: INTIO2 OSCILLATOR MODE U M RA6 RA7 I/O (OSC1) PIC18FXXXX RA6 I/O (OSC2) DS39689F-page 32 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 3.6.4 PLL IN INTOSC MODES 3.6.5 INTOSC FREQUENCY DRIFT The 4x Phase Locked Loop (PLL) can be used with the The factory calibrates the internal oscillator block internal oscillator block to produce faster device clock output (INTOSC) for 8MHz. However, this frequency speeds than are normally possible with the internal may drift as VDD or temperature changes and can oscillator sources. When enabled, the PLL produces a affect the controller operation in a variety of ways. It is clock speed of 16 MHz or 32MHz. possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect Unlike HSPLL mode, the PLL is controlled through on the INTRC clock source frequency. software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. If PLL is Tuning the INTOSC source requires knowing when to enabled and a Two-Speed Start-up from wake is make the adjustment, in which direction it should be performed, execution is delayed until the PLL starts. made and in some cases, how large a change is needed. Three compensation techniques are discussed The PLL is available when the device is configured to in Section3.6.5.1 “Compensating with the use the internal oscillator block as its primary clock EUSART”, Section3.6.5.2 “Compensating with the source (FOSC<3:0> = 1001 or 1000). Additionally, the Timers” and Section3.6.5.3 “Compensating with the PLL will only function when the selected output fre- CCP Module in Capture Mode” but other techniques quency is either 4MHz or 8MHz (OSCCON<6:4> = 111 may be used. or 110). If both of these conditions are not met, the PLL is disabled and the PLLEN bit remains clear (writes are ignored). REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 8MHz INTOSC source (divide-by-256 enabled) 0 = 31kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4MHz and 8MHz only) 0 = PLL disabled Note1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes” for details. bit 5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency • • • • 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • • • 10000 = Minimum frequency Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 33

PIC18F2221/2321/4221/4321 FAMILY 3.6.5.1 Compensating with the EUSART 3.6.5.3 Compensating with the CCP Module in Capture Mode An adjustment may be required when the EUSART begins to generate framing errors or receives data with A CCP module can use free running Timer1 (or errors while in Asynchronous mode. Framing errors Timer3), clocked by the internal oscillator block and an indicate that the device clock frequency is too high. To external event with a known period (i.e., AC power adjust for this, decrement the value in OSCTUNE to frequency). The time of the first event is captured in the reduce the clock frequency. On the other hand, errors CCPRxH:CCPRxL registers and is recorded for use in data may suggest that the clock speed is too low. To later. When the second event causes a capture, the compensate, increment OSCTUNE to increase the time of the first event is subtracted from the time of the clock frequency. second event. Since the period of the external event is known, the time difference between events can be 3.6.5.2 Compensating with the Timers calculated. This technique compares device clock speed to some If the measured time is much greater than the reference clock. Two timers may be used; one timer is calculated time, the internal oscillator block is running clocked by the peripheral clock, while the other is too fast. To compensate, decrement the OSCTUNE clocked by a fixed reference source, such as the register. If the measured time is much less than the Timer1 oscillator. calculated time, the internal oscillator block is running Both timers are cleared, but the timer clocked by the too slow. To compensate, increment the OSCTUNE reference generates interrupts. When an interrupt register. occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. DS39689F-page 34 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 3.7 Clock Sources and Oscillator The secondary oscillators are those external sources Switching not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the The PIC18F2221/2321/4221/4321 family of devices controller is placed in a power-managed mode. includes a feature that allows the device clock source The PIC18F2221/2321/4221/4321 family of devices to be switched from the main oscillator to an alternate offers the Timer1 oscillator as a secondary oscillator. clock source. These devices also offer two alternate This oscillator, in all power-managed modes, is often clock sources. When an alternate clock source is the time base for functions such as a Real-Time Clock. enabled, the various power-managed operating modes are available. Most often, a 32.768kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI Essentially, there are three clock sources for these pins. Like the LP mode oscillator circuit, loading devices: capacitors are also connected from each pin to ground. • Primary oscillators The Timer1 oscillator is discussed in greater detail in • Secondary oscillators Section13.3 “Timer1 Oscillator”. • Internal oscillator block In addition to being a primary clock source, the internal The primary oscillators include the External Crystal oscillator block is available as a power-managed and Resonator modes, the External RC modes, the mode clock source. The INTRC source is also used as External Clock modes and the internal oscillator block. the clock source for several special features, such as The particular mode is defined by the FOSC<3:0> Con- the WDT and Fail-Safe Clock Monitor. figuration bits. The details of these modes are covered The clock sources for the PIC18F2221/2321/4221/4321 earlier in this chapter. family of devices are shown in Figure3-11. See Section24.0 “Special Features of the CPU” for Configuration register details. FIGURE 3-11: PIC18F2221/2321/4221/4321 FAMILY CLOCK DIAGRAM Primary Oscillator LP, XT, HS, RC, EC OSC2 Sleep HSPLL, INTOSC/PLL 4 x PLL OSC1 OSCTUNE<6> Secondary Oscillator T1OSC X Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator OSCCON<6:4> Internal Oscillator OSCCON<6:4> 8 MHz CPU 111 4 MHz Internal 110 Oscillator 2 MHz IDLEN Block er 1 MHz 101 Clock S8o MurHcze 8 MHz stscal 500 kHz 100101MUX Control INTRC (INTOSC) Po 250 kHz 010 FOSC<3:0> OSCCON< 1:0> Source 125 kHz 001 Clock Source Option 1 31 kHz 31 kHz (INTRC) 000 for Other Modules 0 OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up © 2009 Microchip Technology Inc. DS39689F-page 35

PIC18F2221/2321/4221/4321 FAMILY 3.7.1 OSCILLATOR CONTROL REGISTER the primary clock is providing the device clock in primary clock modes. The IOFS bit indicates when the The OSCCON register (Register3-2) controls several internal oscillator block has stabilized and is providing aspects of the device clock’s operation, both in full the device clock in RC Clock modes. The T1RUN bit power operation and in power-managed modes. (T1CON<6>) indicates when the Timer1 oscillator is The System Clock Select bits, SCS<1:0>, select the providing the device clock in secondary clock modes. clock source. The available clock sources are the In power-managed modes, only one of these three bits primary clock (defined by the FOSC<3:0> Configura- will be set at any time. If none of these bits are set, the tion bits), the secondary clock (Timer1 oscillator) and INTRC is providing the clock or the internal oscillator the internal oscillator block. The clock source changes block has just started and is not yet stable. immediately after either of the SCS<1:0> bits are The IDLEN bit controls whether the device goes into changed, following a brief clock transition interval. The Sleep mode or one of the Idle modes when the SLEEP SCS bits are reset on all forms of Reset. instruction is executed. The Internal Oscillator Frequency Select bits The use of the flag and control bits in the OSCCON (IRCF<2:0>) select the frequency output of the internal register is discussed in more detail in Section4.0 oscillator block to drive the device clock. The choices “Power-Managed Modes”. are the INTRC source (31kHz), the INTOSC source (8MHz) or one of the frequencies derived from the Note1: The Timer1 oscillator must be enabled to INTOSC postscaler (31.25kHz to 4MHz). If the select the secondary clock source. The internal oscillator block is supplying the device clock, Timer1 oscillator is enabled by setting the changing the states of these bits will have an immedi- T1OSCEN bit in the Timer1 Control regis- ate change on the internal oscillator’s output. On ter (T1CON<3>). If the Timer1 oscillator device Resets, the default output frequency of the is not enabled, then any attempt to select internal oscillator block is set at 1MHz. a secondary clock source will be ignored. When a nominal output frequency of 31kHz is selected 2: It is recommended that the Timer1 (IRCF<2:0> = 000), users may choose which internal oscillator be operating and stable before oscillator acts as the source. This is done with the selecting the secondary clock source or a INTSRC bit in the OSCTUNE register (OSCTUNE<7>). very long delay may occur while the Setting this bit selects INTOSC as a 31.25kHz clock Timer1 oscillator starts. source derived from the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31kHz) as the 3.7.2 OSCILLATOR TRANSITIONS clock source and disables the INTOSC to reduce current consumption. The PIC18F2221/2321/4221/4321 family of devices con- tains circuitry to prevent clock “glitches” when switching This option allows users to select the tunable and more between clock sources. A short pause in the device clock precise INTOSC as a clock source, while maintaining occurs during the clock switch. The length of this pause power savings with a very low clock speed. Addition- is the sum of two cycles of the old clock source and three ally, the INTOSC source will already be stable should a to four cycles of the new clock source. This formula switch to a higher frequency be needed quickly. assumes that the new clock source is stable. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Clock transitions are discussed in greater detail in Watchdog Timer and the Fail-Safe Clock Monitor. Section4.1.2 “Entering Power-Managed Modes”. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer and PLL Start-up Timer (if enabled) have timed out and DS39689F-page 36 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode when a SLEEP instruction is executed 0 = Device enters Sleep mode when a SLEEP instruction is executed bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8MHz (INTOSC drives clock directly) 110 = 4MHz 101 = 2MHz 100 = 1MHz(3) 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Note1: Reset state depends on state of the IESO Configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 37

PIC18F2221/2321/4221/4321 FAMILY 3.8 Effects of Power-Managed Modes 3.9 Power-up Delays on the Various Clock Sources Power-up delays are controlled by two or three timers, When PRI_IDLE mode is selected, the designated pri- so that no external Reset circuitry is required for most mary oscillator continues to run without interruption. applications. The delays ensure that the device is kept For all other power-managed modes, the oscillator in Reset until the device power supply is stable under using the OSC1 pin is disabled. The OSC1 pin (and normal circumstances and the primary clock is operat- OSC2 pin in Crystal Oscillator modes) will stop ing and stable. For additional information on power-up oscillating. delays, see Section5.5 “Device Reset Timers”. In secondary clock modes (SEC_RUN and The first timer is the Power-up Timer (PWRT) which SEC_IDLE), the Timer1 oscillator is operating and provides a fixed delay on power-up (parameter 33, providing the device clock. The Timer1 oscillator may Table27-10). It is enabled by clearing (= 0) the also run in all power-managed modes if required to PWRTEN Configuration bit (CONFIG2L<0>). clock Timer1 or Timer3. 3.9.1 DELAYS FOR POWER-UP AND In internal oscillator modes (RC_RUN and RC_IDLE), RETURN TO PRIMARY CLOCK the internal oscillator block provides the device clock source. The 31kHz INTRC output can be used directly The second timer is the Oscillator Start-up Timer to provide the clock and may be enabled to support (OST), intended to delay execution until the crystal various special features, regardless of the power- oscillator is stable (LP, XT and HS modes). The OST managed mode (see Section24.2 “Watchdog Timer does this by counting 1024 oscillator cycles before (WDT)”, Section24.3 “Two-Speed Start-up” and allowing the oscillator to clock the device. Section24.4 “Fail-Safe Clock Monitor” for more When the HSPLL Oscillator mode is selected, a third information). The INTOSC output at 8MHz may be timer delays execution for an additional 2ms following used directly to clock the device or may be divided the HS mode OST delay, so the PLL can lock to the down by the postscaler. The INTOSC output is disabled incoming clock frequency. At the end of these delays, if the clock is provided directly from the INTRC output. the OSTS bit (OSCCON<3>) is set. The INTOSC output is also enabled for Two-Speed There is a delay of interval TCSD (parameter 38, Start-up at 1MHz after a Reset. Table27-10), once execution is allowed to start, when If the Sleep mode is selected, all clock sources are the controller becomes ready to execute instructions. stopped. Since all the transistor switching currents This delay runs concurrently with any other delays. have been stopped, Sleep mode achieves the lowest This may be the only delay that occurs when any of the current consumption of the device (only leakage EC, RC or INTIO modes are used as the primary clock currents). source. Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a Real- Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 27.2“DC Characteristics”. TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor pulls high At logic low (clock/4 output) RCIO Floating, external resistor pulls high Configured as PORTA, bit 6 INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6 ECIO Floating, driven by external clock Configured as PORTA, bit 6 EC Floating, driven by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table5-2 in Section5.0 “Reset” for time-outs due to Sleep and MCLR Reset. DS39689F-page 38 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The SCS<1:0 bits allow the selection of one of three PIC18F2221/2321/4221/4321 family devices offer a clock sources for power-managed modes. They are: total of seven operating modes for more efficient power-management. These modes provide a variety of • the primary clock, as defined by the FOSC<3:0> options for selective power conservation in applications Configuration bits where resources may be limited (i.e., battery-powered • the secondary clock (the Timer1 oscillator) devices). • the internal oscillator block (for RC modes) There are three categories of power-managed modes: 4.1.2 ENTERING POWER-MANAGED • Run modes MODES • Idle modes Switching from one power-managed mode to another • Sleep mode begins by loading the OSCCON register. The These categories define which portions of the device SCS1:SCS0 bits select the clock source and determine are clocked and sometimes, what speed. The Run and which Run or Idle mode is to be used. Changing these Idle modes may use any of the three available clock bits causes an immediate switch to the new clock sources (primary, secondary or internal oscillator source, assuming that it is running. The switch may block); the Sleep mode does not use a clock source. also be subject to clock transition delays. These are The power-managed modes include several power- discussed in Section4.1.3 “Clock Transitions and saving features offered on previous PIC® devices. One Status Indicators” and subsequent sections. is the clock switching feature, offered in other PIC18 Entry to the power-managed Idle or Sleep modes is devices, allowing the controller to use the Timer1 oscil- triggered by the execution of a SLEEP instruction. The lator in place of the primary oscillator. Also included is actual mode that results depends on the status of the the Sleep mode, offered by all PIC devices, where all IDLEN bit. device clocks are stopped. Depending on the current mode and the mode being switched to, a change to a power-managed mode does 4.1 Selecting Power-Managed Modes not always require setting all of these bits. Many Selecting a power-managed mode requires two transitions may be done by changing the oscillator select decisions: if the CPU is to be clocked or not and the bits, or changing the IDLEN bit, prior to issuing a SLEEP selection of a clock source. The IDLEN bit instruction. If the IDLEN bit is already configured (OSCCON<7>) controls CPU clocking, while the correctly, it may only be necessary to perform a SLEEP SCS<1:0 bits (OSCCON<1:0>) select the clock source. instruction to switch to the desired mode. The individual modes, bit settings, clock sources and affected modules are summarized in Table4-1. TABLE 4-1: POWER-MANAGED MODES OSCCON Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN<7>(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block.(2) This is the normal full power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. DS39689F-page 39

PIC18F2221/2321/4221/4321 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS 4.2 Run Modes INDICATORS In the Run modes, clocks to both the core and The length of the transition between clock sources is peripherals are active. The difference between these the sum of two cycles of the old clock source and three modes is the clock source. to four cycles of the new clock source. This formula assumes that the new clock source is stable. 4.2.1 PRI_RUN MODE Three bits indicate the current clock source and its The PRI_RUN mode is the normal, full power execution status. They are: mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up • OSTS (OSCCON<3>) is enabled (see Section24.3 “Two-Speed Start-up” • IOFS (OSCCON<2>) or Section24.4 “Fail-Safe Clock Monitor” for • T1RUN (T1CON<6>) details). In this mode, the OSTS bit is set. The IOFS bit In general, only one of these bits will be set while in a may be set if the internal oscillator block is the primary given power-managed mode. When the OSTS bit is clock source (see Section3.7.1 “Oscillator Control set, the primary clock is providing the device clock. Register”). When the IOFS bit is set, the INTOSC output is providing a stable 8MHz clock source to a divider that 4.2.2 SEC_RUN MODE actually drives the device clock. When the T1RUN bit is The SEC_RUN mode is the compatible mode to the set, the Timer1 oscillator is providing the clock. If none “clock switching” feature offered in other PIC18 of these bits are set, then either the INTRC clock devices. In this mode, the CPU and peripherals are source is clocking the device, or the INTOSC source is clocked from the Timer1 oscillator. This gives users the not yet stable. option of lower power consumption while still using a If the internal oscillator block is configured as the primary high-accuracy clock source. clock source by the FOSC<3:0> Configuration bits, then SEC_RUN mode is entered by setting the SCS<1:0> both the OSTS and IOFS bits may be set when in bits to ‘01’. The device clock source is switched to the PRI_RUN or PRI_IDLE modes. This indicates that the Timer1 oscillator (see Figure4-1), the primary oscillator primary clock (INTOSC) is generating a stable 8MHz is shut down, the T1RUN bit (T1CON<6>) is set and the output. Switching the clock source to the Timer1 OSTS bit is cleared. oscillator would clear the OSTS bit. Note: The Timer1 oscillator should already be Note1: Caution should be used when modifying a running prior to entering SEC_RUN mode. single IRCF bit. If VDD is less than 3V, it is If the T1OSCEN bit is not set when the possible to select a higher clock speed SCS<1:0> bits are set to ‘01’, entry to than is supported by the low VDD. SEC_RUN mode will not occur. If the Improper device operation may result if Timer1 oscillator is enabled, but not yet the VDD/FOSC specifications are violated. running, device clocks will be delayed until 2: Executing a SLEEP instruction does not the oscillator has started. In such situa- necessarily place the device into Sleep tions, initial oscillator operation is far from mode. It acts as the trigger to place the stable and unpredictable operation may controller into either the Sleep mode or result. one of the Idle modes, depending on the setting of the IDLEN bit. On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the 4.1.4 MULTIPLE SLEEP COMMANDS Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch The power-managed mode that is invoked with the back to the primary clock occurs (see Figure4-2). SLEEP instruction is determined by the setting of the When the clock switch is complete, the T1RUN bit is IDLEN bit at the time the instruction is executed. If cleared, the OSTS bit is set and the primary clock is another SLEEP instruction is executed, the device will providing the clock. The IDLEN and SCS bits are not enter the power-managed mode specified by IDLEN at affected by the wake-up; the Timer1 oscillator that time. If IDLEN has changed, the device will enter continues to run. the new power-managed mode specified by the new setting. DS39689F-page 40 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 SCS<1:0> bits Changed OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. 4.2.3 RC_RUN MODE This mode is entered by setting the SCS1 bit to ‘1’. Although it is ignored, it is recommended that the SCS0 In RC_RUN mode, the CPU and peripherals are bit also be cleared; this is to maintain software compat- clocked from the internal oscillator block using the ibility with future devices. When the clock source is INTOSC multiplexer. In this mode, the primary clock is switched to the INTOSC multiplexer (see Figure4-3), shut down. When using the INTRC source, this mode the primary oscillator is shut down and the OSTS bit is provides the best power conservation of all the Run cleared. The IRCF bits may be modified at any time to modes, while still executing code. It works well for user immediately change the clock speed. applications which are not highly timing sensitive or do not require high-speed clocks at all times. Note: Caution should be used when modifying a If the primary clock source is the internal oscillator block single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes than is supported by the low VDD. Improper device operation may result if during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. the VDD/FOSC specifications are violated. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2009 Microchip Technology Inc. DS39689F-page 41

PIC18F2221/2321/4221/4321 FAMILY If the IRCF bits and the INTSRC bit are all clear, the On transitions from RC_RUN mode to PRI_RUN mode, INTOSC output is not enabled and the IOFS bit will the device continues to be clocked from the INTOSC remain clear; there will be no indication of the current multiplexer while the primary clock is started. When the clock source. The INTRC source is providing the primary clock becomes ready, a clock switch to the device clocks. primary clock occurs (see Figure4-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS If the IRCF bits are changed from all clear (thus, bit is set and the primary clock is providing the device enabling the INTOSC output) or if INTSRC is set, the clock. The IDLEN and SCS bits are not affected by the IOFS bit becomes set after the INTOSC output switch. The INTRC source will continue to run if either becomes stable. Clocks to the device continue while the WDT or the Fail-Safe Clock Monitor is enabled. the INTOSC source stabilizes after an interval of TIOBST (parameter 39, Table27-10). If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n OSC1 Clock Transition(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 SCS<1:0> bits Changed OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS39689F-page 42 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode in the PIC18F2221/ The Idle modes allow the controller’s CPU to be 2321/4221/4321 family devices is identical to the leg- selectively shut down while the peripherals continue to acy Sleep mode offered in all other PIC devices. It is operate. Selecting a particular Idle mode allows users entered by clearing the IDLEN bit (the default state on to further manage power consumption. device Reset) and executing the SLEEP instruction. If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is This shuts down the selected oscillator (Figure4-5). All executed, the peripherals will be clocked from the clock clock source status bits are cleared. source selected using the SCS<1:0> bits; however, the Entering the Sleep mode from any other mode does not CPU will not be clocked. The clock source status bits are require a clock switch. This is because no clocks are not affected. Setting IDLEN and executing a SLEEP needed once the controller has entered Sleep. If the instruction provides a quick method of switching from a WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode. operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue continue to run. to operate. If the Timer1 oscillator is enabled, it will also When a wake event occurs in Sleep mode (by interrupt, continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS<1:0> bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure4-6), or it will be clocked time-out or a Reset. When a wake event occurs, CPU from the internal oscillator block if either the Two-Speed execution is delayed by an interval of TCSD Start-up or the Fail-Safe Clock Monitor are enabled (parameter38, Table27-10) while it becomes ready to (see Section24.0 “Special Features of the CPU”). In execute code. When the CPU begins executing code, either case, the OSTS bit is set when the primary clock it resumes with the same clock source for the current is providing the device clocks. The IDLEN and SCS bits Idle mode. For example, when waking from RC_IDLE are not affected by the wake-up. mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 PC + 6 Wake Event OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39689F-page 43

PIC18F2221/2321/4221/4321 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by the fastest resumption of device operation with its more setting the IDLEN bit and executing a SLEEP accurate primary clock source, since the clock source instruction. If the device is in another Run mode, set the does not have to “warm-up” or transition from another IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and oscillator. execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, PRI_IDLE mode is entered from PRI_RUN mode by the OSTS bit is cleared and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCS bits and execute SLEEP. be clocked from the Timer1 oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the Timer1 oscillator. The by the FOSC<3:0> Configuration bits. The OSTS bit IDLEN and SCS bits are not affected by the wake-up; remains set (see Figure4-7). the Timer1 oscillator continues to run (see Figure4-8). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval TCSD (parame- running prior to entering SEC_IDLE mode. ter 38, Table27-10) is required between the wake event If the T1OSCEN bit is not set when writing and when code execution starts. This is required to the SCS<1:0> bits, entry to SEC_IDLE allow the CPU to become ready to execute instructions. mode will not occur. If the Timer1 oscillator After the wake-up, the OSTS bit remains set. The is enabled but not yet running, peripheral IDLEN and SCS bits are not affected by the wake-up clocks will be delayed until the oscillator (see Figure4-8). has started. In such situations, initial oscil- lator operation is far from stable and unpredictable operation may result. FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event DS39689F-page 44 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 4.4.3 RC_IDLE MODE On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ In RC_IDLE mode, the CPU is disabled but the periph- GIEH bit (INTCON<7>) is set. Otherwise, code execution erals continue to be clocked from the internal oscillator continues or resumes without branching (see block using the INTOSC multiplexer. This mode allows Section10.0 “Interrupts”). for controllable power conservation during Idle periods. A fixed delay of interval TCSD following the wake event From RC_RUN, this mode is entered by setting the is required when leaving Sleep and Idle modes. This IDLEN bit and executing a SLEEP instruction. If the delay is required for the CPU to prepare for execution. device is in another Run mode, first set IDLEN, then set Instruction execution resumes on the first clock cycle the SCS1 bit and execute SLEEP. Although its value is following this delay. ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future 4.5.2 EXIT BY WDT TIME-OUT devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF A WDT time-out will cause different actions depending bits before executing the SLEEP instruction. When the on which power-managed mode the device is in when clock source is switched to the INTOSC multiplexer, the the time-out occurs. primary oscillator is shut down and the OSTS bit is If the device is not executing code (all Idle modes and cleared. Sleep mode), the time-out will result in an exit from the If the IRCF bits are set to any non-zero value, or the power-managed mode (see Section4.2 “Run INTSRC bit is set, the INTOSC output is enabled. The Modes” and Section4.3 “Sleep Mode”). If the device IOFS bit becomes set, after the INTOSC output is executing code (all Run modes), the time-out will becomes stable, after an interval of TIOBST result in a WDT Reset (see Section24.2 “Watchdog (parameter39, Table27-10). Clocks to the peripherals Timer (WDT)”). continue while the INTOSC source stabilizes. If the The WDT timer and postscaler are cleared by IRCF bits were previously at a non-zero value, or executing a SLEEP or CLRWDT instruction, the loss of a INTSRC was set before the SLEEP instruction was currently selected clock source (if the Fail-Safe Clock executed and the INTOSC source was already stable, Monitor is enabled) and modifying the IRCF bits in the the IOFS bit will remain set. If the IRCF bits and OSCCON register if the internal oscillator block is the INTSRC are all clear, the INTOSC output will not be device clock source. enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. 4.5.3 EXIT BY RESET When a wake event occurs, the peripherals continue to Normally, the device is held in Reset by the Oscillator be clocked from the INTOSC multiplexer. After a delay of Start-up Timer (OST) until the primary clock becomes TCSD following the wake event, the CPU begins execut- ready. At that time, the OSTS bit is set and the device ing code being clocked by the INTOSC multiplexer. The begins executing code. If the internal oscillator block is IDLEN and SCS bits are not affected by the wake-up. the new clock source, the IOFS bit is set instead. The INTRC source will continue to run if either the WDT The exit delay time from Reset to the start of code or the Fail-Safe Clock Monitor is enabled. execution depends on both the clock sources before and after the wake-up and the type of oscillator if the 4.5 Exiting Idle and Sleep Modes new clock source is the primary clock. Exit delays are summarized in Table4-2. An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. Code execution can begin before the primary clock This section discusses the triggers that cause exits becomes ready. If either the Two-Speed Start-up (see from power-managed modes. The clocking subsystem Section24.3 “Two-Speed Start-up”) or Fail-Safe actions are discussed in each of the power-managed Clock Monitor (see Section24.4 “Fail-Safe Clock modes (see Section4.2 “Run Modes”, Section4.3 Monitor”) is enabled, the device may begin execution “Sleep Mode” and Section4.4 “Idle Modes”). as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the 4.5.1 EXIT BY INTERRUPT internal oscillator block. Execution is clocked by the Any of the available interrupt sources can cause the internal oscillator block until either the primary clock device to exit from an Idle mode, or the Sleep mode to becomes ready or a power-managed mode is entered a Run mode. To enable this functionality, an interrupt before the primary clock becomes ready; the primary source must be enabled by setting its enable bit in one clock is then shut down. of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. DS39689F-page 45

PIC18F2221/2321/4221/4321 FAMILY 4.5.4 EXIT WITHOUT AN OSCILLATOR In these instances, the primary clock source either START-UP DELAY does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not Certain exits from power-managed modes do not require an oscillator start-up delay (RC, EC and INTIO invoke the OST at all. There are two cases: Oscillator modes). However, a fixed delay of interval • PRI_IDLE mode, where the primary clock source TCSD following the wake event is still required when is not stopped; and leaving Sleep and Idle modes to allow the CPU to • the primary clock source is not any of the LP, XT, prepare for execution. Instruction execution resumes HS or HSPLL modes. on the first clock cycle following this delay. TABLE 4-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Clock Source Clock Ready Status Exit Delay before Wake-up after Wake-up Bit (OSCCON) LP, XT, HS Primary Device Clock HSPLL OSTS TCSD(1) (PRI_IDLE mode) EC, RC INTOSC(2) IOFS LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS T1OSC EC, RC TCSD(1) INTOSC(2) TIOBST(4) IOFS LP, XT, HS TOST(3) INTOSC(3) HSPLL TOST + trc(3) OSTS EC, RC TCSD(1) INTOSC(2) None IOFS LP, XT, HS TOST(3) None HSPLL TOST + trc(3) OSTS (Sleep mode) EC, RC TCSD(1) INTOSC(2) TIOBST(4) IOFS Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section4.4 “Idle Modes”). On Reset, INTOSC defaults to 1MHz. 2: Includes both the INTOSC 8MHz source and postscaler derived frequencies. 3: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is also designated as TPLL. 4: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period. DS39689F-page 46 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 5.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure5-1. The PIC18F2221/2321/4221/4321 family devices differentiate between various kinds of Reset: 5.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register5-1). The lower five bits of the regis- c) MCLR Reset during power-managed modes ter indicate that a specific Reset event has occurred. In d) Watchdog Timer (WDT) Reset (during most cases, these bits can only be cleared by the event execution) and must be set by the application after the event. The e) Programmable Brown-out Reset (BOR) state of these flag bits, taken together, can be read to f) RESET Instruction indicate the type of Reset that just occurred. This is described in more detail in Section5.6 “Reset State g) Stack Full Reset of Registers”. h) Stack Underflow Reset The RCON register also has control bits for setting This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the POR and BOR and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in start-up timers. Stack Reset events are covered in Section10.0 “Interrupts”. BOR is covered in Section6.1.2.4 “Stack Full and Underflow Resets”. Section5.4 “Brown-out Reset (BOR)”. WDT Resets are covered in Section24.2 “Watchdog Timer (WDT)”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset BOREN S OST/PWRT OST 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 32 μs PWRT 65.5 ms INTRC(1) 11-Bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table5-2 for time-out situations. © 2009 Microchip Technology Inc. DS39689F-page 47

PIC18F2221/2321/4221/4321 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section5.6 “Reset State of Registers” for additional information. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after Power-on Reset). DS39689F-page 48 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 5.2 Master Clear (MCLR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. The MCLR pin is not driven low by any internal Resets, D R including the WDT. R1 MCLR In PIC18F2221/2321/4221/4321 family devices, the MCLR input can be disabled with the MCLRE Configu- C PIC18FXXXX ration bit. When MCLR is disabled, the pin becomes a digital input. See Section11.5 “PORTE, TRISE and LATE Registers” for more information. Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. 5.3 Power-on Reset (POR) The diode D helps discharge the capacitor A Power-on Reset pulse is generated on-chip quickly when VDD powers down. whenever VDD rises above a certain threshold. This 2: R < 40kΩ is recommended to make sure that the voltage drop across R does not violate allows the device to start in the initialized state when the device’s electrical specification. VDD is adequate for operation. 3: R1 ≥ 1 kΩ will limit any current flowing into To take advantage of the POR circuitry, tie the MCLR MCLR from external capacitor C, in the event pin through a resistor (1kΩ to 10kΩ) to VDD. This will of MCLR/VPP pin breakdown, due to eliminate external RC components usually needed to Electrostatic Discharge (ESD) or Electrical create a Power-on Reset delay. A minimum rise rate for Overstress (EOS). VDD is specified (parameter D004). For a slow rise time, see Figure5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. Power-on Reset events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2009 Microchip Technology Inc. DS39689F-page 49

PIC18F2221/2321/4221/4321 FAMILY 5.4 Brown-out Reset (BOR) change BOR configuration. It also allows the user to tailor device power consumption in software by elimi- PIC18F2221/2321/4221/4321 family devices implement nating the incremental current that the BOR consumes. a BOR circuit that provides the user with a number of While the BOR current is typically very small, it may configuration and power-saving options. The BOR is have some impact in low-power applications. controlled by the BORV<1:0> and BOREN<1:0> Configuration bits. There are a total of four BOR Note: Even when BOR is under software control, configurations which are summarized in Table5-1. the Brown-out Reset voltage level is still set by the BORV<1:0> Configuration bits. The BOR threshold is set by the BORV<1:0> bits. If BOR It cannot be changed in software. is enabled (any values of BOREN<1:0>, except ‘00’), any drop of VDD below VBOR (parameter D005) for 5.4.2 DETECTING BOR greater than TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR When Brown-out Reset is enabled, the BOR bit always for less than TBOR. The chip will remain in Brown-out resets to ‘0’ on any Brown-out Reset or Power-on Reset until VDD rises above VBOR. Reset event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading If the Power-up Timer is enabled, it will be invoked after the state of BOR alone. A more reliable method is to VDD rises above VBOR; it then will keep the chip in simultaneously check the state of both POR and BOR. Reset for an additional time delay, TPWRT This assumes that the POR bit is reset to ‘1’ in software (parameter33). If VDD drops below VBOR while the immediately after any Power-on Reset event. If BOR is Power-up Timer is running, the chip will go back into a ‘0’ while POR is ‘1’, it can be reliably assumed that a Brown-out Reset and the Power-up Timer will be Brown-out Reset event has occurred. initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. 5.4.3 DISABLING BOR IN SLEEP MODE BOR and the Power-on Timer (PWRT) are When BOREN<1:0> = 10, the BOR remains under independently configured. Enabling BOR Reset does hardware control and operates as previously not automatically enable the PWRT. described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the 5.4.1 SOFTWARE ENABLED BOR device returns to any other operating mode, BOR is When BOREN<1:0> = 01, the BOR can be enabled or automatically re-enabled. disabled by the user in software. This is done with the This mode allows for applications to recover from control bit, SBOREN (RCON<6>). Setting SBOREN brown-out situations, while actively executing code, enables the BOR to function as previously described. when the device requires BOR protection the most. At Clearing SBOREN disables the BOR entirely. The the same time, it saves additional power in Sleep mode SBOREN bit operates only in this mode; otherwise it is by eliminating the small incremental BOR current. read as ‘0’. Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to TABLE 5-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled in software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. DS39689F-page 50 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 5.5 Device Reset Timers 5.5.3 PLL LOCK TIME-OUT PIC18F2221/2321/4221/4321 family devices incorpo- With the PLL enabled in HSPLL mode, the time-out rate three separate on-chip timers that help regulate the sequence following a Power-on Reset is slightly differ- Power-on Reset process. Their main function is to ent from other oscillator modes. A separate timer is ensure that the device clock is stable before code is used to provide a fixed time-out that is sufficient for the executed. These timers are: PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the • Power-up Timer (PWRT) oscillator start-up time-out. • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 5.5.1 POWER-UP TIMER (PWRT) 1. After the POR pulse has cleared, PWRT time-out The Power-up Timer (PWRT) of the PIC18F2221/ is invoked (if enabled). 2321/4221/4321 family devices is an 11-bit counter 2. Then, the OST is activated. which uses the INTRC source as the clock input. This yields an approximate time interval of The total time-out will vary based on oscillator configu- 2048x32μs=65.6ms. While the PWRT is counting, ration and the status of the PWRT. Figure5-3, the device is held in Reset. Figure5-4, Figure5-5, Figure5-6 and Figure5-7 all depict time-out sequences on power-up, with the The power-up time delay depends on the INTRC clock Power-up Timer enabled and the device operating in and will vary from chip to chip due to temperature and HS Oscillator mode. Figures 5-3 through 5-6 also process variation. See DC parameter 33 for details. apply to devices operating in XT or LP modes. For The PWRT is enabled by clearing the PWRTEN devices in RC mode and with the PWRT disabled, there Configuration bit. will be no time-out at all. 5.5.2 OSCILLATOR START-UP TIMER Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bring- (OST) ing MCLR high will begin execution immediately The Oscillator Start-up Timer (OST) provides a 1024 (Figure5-5). This is useful for testing purposes or to oscillator cycle (from OSC1 input) delay after the synchronize more than one PIC18FXXXX device PWRT delay is over (parameter 33). This ensures that operating in parallel. the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power-managed modes. TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Reset Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. DS39689F-page 51

PIC18F2221/2321/4221/4321 FAMILY FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39689F-page 52 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2009 Microchip Technology Inc. DS39689F-page 53

PIC18F2221/2321/4221/4321 FAMILY 5.6 Reset State of Registers Table5-4 describes the Reset states for all of the Special Function Registers. These are categorized by Most registers are unaffected by a Reset. Their status Power-on and Brown-out Resets, Master Clear and is unknown on POR and unchanged by all other WDT Resets and WDT wake-ups. Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table5-3. These bits are used in software to determine the nature of the Reset. TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 0 0 0 0 RESET Instruction 0000h 0 u u u u u u Brown-out 0000h 1 1 1 u 0 u u MCLR during power-managed Run modes 0000h u 1 u u u u u MCLR during power-managed Idle modes 0000h u 1 0 u u u u and Sleep mode WDT Time-out during full power or 0000h u 0 u u u u u power-managed Run mode MCLR during full power execution 0000h u u u u u u u Stack Full Reset (STVREN = 1) 0000h u u u u u 1 u Stack Underflow Reset (STVREN = 1) 0000h u u u u u u 1 Stack Underflow Error (not an actual Reset, 0000h u u u u u u 1 STVREN = 0) WDT time-out during power-managed Idle or PC + 2 u 0 0 u u u u Sleep modes Interrupt exit from power-managed modes PC + 2(1) u u 0 u u u u Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN<1:0> Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’. DS39689F-page 54 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets TOSU 2221 2321 4221 4321 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2221 2321 4221 4321 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2221 2321 4221 4321 --00 0000 --00 0000 --uu uuuu PCLATH 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu PCL 2221 2321 4221 4321 0000 0000 0000 0000 PC + 2(2) TBLPTRU 2221 2321 4221 4321 --00 0000 --00 0000 --uu uuuu TBLPTRH 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu TABLAT 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu PRODH 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2221 2321 4221 4321 0000 000x 0000 000u uuuu uuuu(1) INTCON2 2221 2321 4221 4321 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 2221 2321 4221 4321 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 2221 2321 4221 4321 N/A N/A N/A POSTINC0 2221 2321 4221 4321 N/A N/A N/A POSTDEC0 2221 2321 4221 4321 N/A N/A N/A PREINC0 2221 2321 4221 4321 N/A N/A N/A PLUSW0 2221 2321 4221 4321 N/A N/A N/A FSR0H 2221 2321 4221 4321 ---- 0000 ---- 0000 ---- uuuu FSR0L 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2221 2321 4221 4321 N/A N/A N/A POSTINC1 2221 2321 4221 4321 N/A N/A N/A POSTDEC1 2221 2321 4221 4321 N/A N/A N/A PREINC1 2221 2321 4221 4321 N/A N/A N/A PLUSW1 2221 2321 4221 4321 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 55

PIC18F2221/2321/4221/4321 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets FSR1H 2221 2321 4221 4321 ---- 0000 ---- 0000 ---- uuuu FSR1L 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2221 2321 4221 4321 ---- 0000 ---- 0000 ---- uuuu INDF2 2221 2321 4221 4321 N/A N/A N/A POSTINC2 2221 2321 4221 4321 N/A N/A N/A POSTDEC2 2221 2321 4221 4321 N/A N/A N/A PREINC2 2221 2321 4221 4321 N/A N/A N/A PLUSW2 2221 2321 4221 4321 N/A N/A N/A FSR2H 2221 2321 4221 4321 ---- 0000 ---- 0000 ---- uuuu FSR2L 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2221 2321 4221 4321 ---x xxxx ---u uuuu ---u uuuu TMR0H 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu TMR0L 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2221 2321 4221 4321 1111 1111 1111 1111 uuuu uuuu OSCCON 2221 2321 4221 4321 0100 q000 0100 q000 uuuu uuqu HLVDCON 2221 2321 4221 4321 0-00 0101 0-00 0101 u-uu uuuu WDTCON 2221 2321 4221 4321 ---- ---0 ---- ---0 ---- ---u RCON(4) 2221 2321 4221 4321 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2221 2321 4221 4321 0000 0000 u0uu uuuu uuuu uuuu TMR2 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu PR2 2221 2321 4221 4321 1111 1111 1111 1111 1111 1111 T2CON 2221 2321 4221 4321 -000 0000 -000 0000 -uuu uuuu SSPBUF 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu SSPCON1 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu SSPCON2 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39689F-page 56 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets ADRESH 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2221 2321 4221 4321 --00 0000 --00 0000 --uu uuuu ADCON1 2221 2321 4221 4321 --00 0qqq --00 0qqq --uu uuuu ADCON2 2221 2321 4221 4321 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu 2221 2321 4221 4321 --00 0000 --00 0000 --uu uuuu CCPR2H 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 2221 2321 4221 4321 --00 0000 --00 0000 --uu uuuu BAUDCON 2221 2321 4221 4321 0100 0-00 0100 0-00 --uu uuuu ECCP1DEL 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu 2221 2321 4221 4321 0000 00-- 0000 00-- uuuu uu-- CVRCON 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu CMCON 2221 2321 4221 4321 0000 0111 0000 0111 uuuu uuuu TMR3H 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 2221 2321 4221 4321 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu SPBRG 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu RCREG 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu TXREG 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu TXSTA 2221 2321 4221 4321 0000 0010 0000 0010 uuuu uuuu RCSTA 2221 2321 4221 4321 0000 000x 0000 000x uuuu uuuu EEADR 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu EEDATA 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu EECON2 2221 2321 4221 4321 0000 0000 0000 0000 0000 0000 EECON1 2221 2321 4221 4321 xx-0 x000 uu-0 u000 uu-0 u000 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 57

PIC18F2221/2321/4221/4321 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets IPR2 2221 2321 4221 4321 11-1 1111 11-1 1111 uu-u uuuu PIR2 2221 2321 4221 4321 00-0 0000 00-0 0000 uu-u uuuu(1) PIE2 2221 2321 4221 4321 00-0 0000 00-0 0000 uu-u uuuu IPR1 2221 2321 4221 4321 1111 1111 1111 1111 uuuu uuuu 2221 2321 4221 4321 -111 1111 -111 1111 -uuu uuuu PIR1 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu(1) 2221 2321 4221 4321 -000 0000 -000 0000 -uuu uuuu(1) PIE1 2221 2321 4221 4321 0000 0000 0000 0000 uuuu uuuu 2221 2321 4221 4321 -000 0000 -000 0000 -uuu uuuu OSCTUNE 2221 2321 4221 4321 00-0 0000 00-0 0000 uu-u uuuu TRISE 2221 2321 4221 4321 0000 -111 0000 -111 uuuu -uuu TRISD 2221 2321 4221 4321 1111 1111 1111 1111 uuuu uuuu TRISC 2221 2321 4221 4321 1111 1111 1111 1111 uuuu uuuu TRISB 2221 2321 4221 4321 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2221 2321 4221 4321 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATE 2221 2321 4221 4321 ---- -xxx ---- -uuu ---- -uuu LATD 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 2221 2321 4221 4321 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTE 2221 2321 4221 4321 ---- xxxx ---- uuuu ---- uuuu 2221 2321 4221 4321 ---- x--- ---- u--- ---- u--- PORTD 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2221 2321 4221 4321 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2221 2321 4221 4321 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39689F-page 58 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are three types of memory in PIC18 Enhanced PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a • Data EEPROM NOP instruction). As Harvard architecture devices, the data and program The PIC18F2221 and PIC18F4221 each have 4Kbytes memories use separate busses; this allows for con- of Flash memory and can store up to 2048 single-word current access of the two memory spaces. The data instructions. The PIC18F2321 and PIC18F4321 each EEPROM, for practical purposes, can be regarded as have 8Kbytes of Flash memory and can store up to a peripheral device, since it is addressed and accessed 4096 single-word instructions. through a set of control registers. PIC18 devices have two interrupt vectors. The Reset Additional detailed information on the operation of the vector address is at 0000h and the interrupt vector Flash program memory is provided in Section7.0 addresses are at 0008h and 0018h. “Flash Program Memory”. Data EEPROM is The program memory maps for PIC18F2221/4221 and discussed separately in Section8.0 “Data EEPROM PIC18F2321/4321 devices are shown in Figure6-1. Memory”. FIGURE 6-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2221/2321/4221/4321 FAMILY DEVICES PIC18FX221 PIC18FX321 PC<20:0> PC<20:0> CALL,RCALL,RETURN 21 CALL,RCALL,RETURN 21 RETFIE,RETLW RETFIE,RETLW Stack Level 1 Stack Level 1 ••• ••• Stack Level 31 Stack Level 31 Reset Vector 0000h Reset Vector 0000h High-Priority Interrupt Vector 0008h High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h Low-Priority Interrupt Vector 0018h On-Chip Program Memory On-Chip Program Memory 0FFFh 1000h ce 1FFFh ce a a Sp 2000h Sp y y or or m m e e M M er er Us Us Read ‘0’ Read ‘0’ 1FFFFFh 1FFFFFh 200000h 200000h © 2009 Microchip Technology Inc. DS39689F-page 59

PIC18F2221/2321/4221/4321 FAMILY 6.1.1 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the Top-of- low byte, known as the PCL register, is both readable Stack Special Function Registers. Data can also be and writable. The high byte, or PCH register, contains pushed to, or popped from the stack, using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack; register contains the PC<20:16> bits; it is also not the Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack; the contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section6.1.4.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full or has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 6.1.2.1 Top-of-Stack Access a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is readable and writable. A set of three registers, The CALL, RCALL, GOTO and program branch TOSU:TOSH:TOSL, hold the contents of the stack instructions write to the program counter directly. For location pointed to by the STKPTR register (Figure6-2). these instructions, the contents of PCLATH and This allows users to implement a software stack if PCLATU are not transferred to the program counter. necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the 6.1.2 RETURN ADDRESS STACK TOSU:TOSH:TOSL registers. These values can be The return address stack allows any combination of up placed on a user-defined software stack. At return time, to 31 program calls and interrupts to occur. The PC is the software can return these values to pushed onto the stack when a CALL or RCALL instruc- TOSU:TOSH:TOSL and do a return. tion is executed or an interrupt is Acknowledged. The The user must disable the global interrupt enable bits PC value is pulled off the stack on a RETURN, RETLW while accessing the stack to prevent inadvertent stack or a RETFIE instruction. PCLATU and PCLATH are not corruption. affected by any of the RETURN or CALL instructions. FIGURE 6-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 DS39689F-page 60 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 6.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register6-1) contains the Stack to the PC and sets the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bits. The value set until cleared by software or until a POR occurs. of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 6.1.2.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack the stack without disturbing normal program execution Overflow Reset Enable) Configuration bit. (Refer to is a desirable feature. The PIC18 instruction set Section24.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by decre- Any additional pushes will not overwrite the 31st push menting the Stack Pointer. The previous value pushed and STKPTR will remain at 31. onto the stack then becomes the TOS value. REGISTER 6-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 61

PIC18F2221/2321/4221/4321 FAMILY 6.1.2.4 Stack Full and Underflow Resets 6.1.4 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow will set the appropriate STKFUL or program memory. For PIC18 devices, look-up tables STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 6.1.4.1 Computed GOTO 6.1.3 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example6-2. WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only A look-up table can be formed with an ADDWF PCL one level deep and is neither readable nor writable. It is instruction and a group of RETLW nn instructions. The loaded with the current value of the corresponding W register is loaded with an offset into the table before register when the processor vectors for an interrupt. All executing a call to that table. The first instruction of the interrupt sources will push values into the stack regis- called routine is the ADDWF PCL instruction. The next ters. The values in the registers are then loaded back instruction executed will be one of the RETLW nn into their associated registers if the RETFIE, FAST instructions that returns the value ‘nn’ to the calling instruction is used to return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of stack registers cannot be used reliably to return from bytes that the program counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low-priority interrupt, the Stack regis- In this method, only one data byte may be stored in ter values stored by the low-priority interrupt will be each instruction location and room on the return overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 6-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example6-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 6.1.4.2 Table Reads and Table Writes EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word by using table reads and writes. The • Table Pointer (TBLPTR) register specifies the byte • address and the Table Latch (TABLAT) register contains the data that is read from or written to program SUB1 • memory. Data is transferred to or from program • memory one byte at a time. RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Table read and table write operations are discussed further in Section7.1 “Table Reads and Table Writes”. DS39689F-page 62 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one internal or external source, is internally divided by four instruction cycle, while the decode and execute take to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the pipe- (Q1, Q2, Q3 and Q4). Internally, the program counter is lining, each instruction effectively executes in one incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to from the program memory and latched into the change (e.g., GOTO), then two cycles are required to Instruction Register (IR) during Q4. The instruction is complete the instruction (Example6-3). decoded and executed during the following Q1 through A fetch cycle begins with the Program Counter (PC) Q4. The clocks and instruction execution flow are incrementing in Q1. shown in Figure6-3. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. DS39689F-page 63

PIC18F2221/2321/4221/4321 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as two bytes or four bytes in program word address. The word address is written to PC<20:1>, memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure6-4 shows how the with an even address (LSb = 0). To maintain alignment instruction GOTO 0006h is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSb will always read ‘0’ (see Section6.1.1 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure6-4 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section24.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-4: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, The standard PIC18 instruction set has four two-word a NOP is executed instead. This is necessary for cases instructions: CALL, MOVFF, GOTO and LSFR. In all when the two-word instruction is preceded by a condi- cases, the second word of the instructions always has tional instruction that changes the PC. Example6-4 ‘1111’ as its four Most Significant bits; the other 12 bits shows how this works. are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction spec- Note: See Section6.6 “PIC18 Instruction ifies a special form of NOP. If the instruction is executed Execution and the Extended Instruc- tion Set” for information on two-word in proper sequence – immediately after the first word – the data in the second word is accessed and used by instructions in the extended instruction set. EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code DS39689F-page 64 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 6.3 Data Memory Organization 6.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.5 “Data Memory and the write operation. For PIC18 devices, this is accomplished Extended Instruction Set” for more with a RAM banking scheme. This divides the memory information. space into 16 contiguous banks of 256 bytes. Depend- The data memory in PIC18 devices is implemented as ing on the instruction, each location can be addressed static RAM. Each register in the data memory has a directly by its full 12-bit address, or an 8-bit low-order 12-bit address, allowing up to 4096 bytes of data address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16banks that contain 256 bytes each; PIC18F2221/ of the Bank Pointer, known as the Bank Select Register 2321/4221/4321 family devices implement 2 banks. (BSR). This SFR holds the four Most Significant bits of Figure6-5 shows the data memory organization for the a location’s address; the instruction itself includes the PIC18F2221/2321/4221/4321 family devices. 8Least Significant bits. Only the four lower bits of the The data memory contains Special Function Registers BSR are implemented (BSR3:BSR0). The upper four (SFRs) and General Purpose Registers (GPRs). The bits are unused; they will always read ‘0’ and cannot be SFRs are used for control and status of the controller written to. The BSR can be loaded directly by using the and peripheral functions, while GPRs are used for data MOVLB instruction. storage and scratchpad operations in the user’s The value of the BSR indicates the bank in data application. Any read of an unimplemented location will memory; the 8 bits in the instruction show the location read as ‘0’s. in the bank and can be thought of as an offset from the The instruction set and architecture allow operations bank’s lower boundary. The relationship between the across all banks. The entire data memory may be BSR’s value and the bank division in data memory is accessed by Direct, Indirect or Indexed Addressing shown in Figure6-6. modes. Addressing modes are discussed later in this Since up to 16 registers may share the same low-order subsection. address, the user must always be careful to ensure that To ensure that commonly used registers (SFRs and the proper bank is selected before performing a data select GPRs) can be accessed in a single cycle, PIC18 read or write. For example, writing what should be devices implement an Access Bank. This is a 256-byte program data to an 8-bit address of F9h, while the BSR memory space that provides fast access to SFRs and is 0Fh, will end up resetting the program counter. the lower portion of GPR Bank 0 without using the While any bank can be selected, only those banks that BSR. Section6.3.2 “Access Bank” provides a are actually implemented can be read or written to. detailed description of the Access RAM. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure6-5 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. DS39689F-page 65

PIC18F2221/2321/4221/4321 FAMILY FIGURE 6-5: DATA MEMORY MAP FOR PIC18F2221/2321/4221/4321 FAMILY DEVICES When a = 0, The BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). BSR<3:0> Data Memory Map The second 128 bytes are 000h Special Function Registers 00h Access RAM = 0000 07Fh (from Bank 15). Bank 0 080h GPR FFh 0FFh When a = 1, = 0001 100h Bank 1 GPR The BSR specifies the Bank 1FFh used by the instruction. Access Bank 00h Access RAM Low 7Fh = 0010 80h Bank 2 Access RAM High Unused = 1110 to Read ‘00h’ (SFRs) FFh Bank 14 EFFh 00h F00h = 1111 Unused F7Fh Bank 15 F80h FFh SFR FFFh DS39689F-page 66 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 6-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) From Opcode(2) 7 0 7 0 0 0 0 0 0 0 0 1 Data Memory 1 1 1 1 1 1 1 1 000h 00h Bank 0 Bank Select(2) 100h FFh 00h Bank 1 FFh 200h 00h Bank 2 through Bank 14 F00h 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK however, the instruction is forced to use the Access Bank address map; the current value of the BSR is While the use of the BSR with an embedded 8-bit ignored entirely. address allows users to address the entire range of data memory, it also means that the user must always Using this “forced” addressing allows the instruction to ensure that the correct bank is selected. Otherwise, operate on a data address in a single cycle, without data may be read from or written to the wrong location. updating the BSR first. For 8-bit addresses of 80h and This can be disastrous if a GPR is the intended target above, this means that users can evaluate and operate of an operation, but an SFR is written to instead. on SFRs more efficiently. The Access RAM below 80h Verifying and/or changing the BSR for each read or is a good place for data values that the user might need write to data memory can become very inefficient. to access rapidly, such as immediate computational results or common program variables. Access RAM To streamline access for the most commonly used data also allows for faster and more code efficient context memory locations, the data memory is configured with saving and switching of variables. an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different The Access Bank consists of the first 128 bytes of when the extended instruction set is enabled (XINST memory (00h-7Fh) in Bank 0 and the last 128 bytes of Configuration bit = 1). This is discussed in more detail memory (80h-FFh) in Block 15. The lower half is known in Section6.5.3 “Mapping the Access Bank in as the “Access RAM” and is composed of GPRs. This Indexed Literal Offset Addressing Mode”. upper half is also where the device’s SFRs are 6.3.3 GENERAL PURPOSE mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear REGISTER FILE fashion by an 8-bit address (Figure6-5). PIC18 devices may have banked memory in the GPR The Access Bank is used by core PIC18 instructions area. This is data RAM which is available for use by all that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0 the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom of uses the BSR and the 8-bit address included in the the SFR area. GPRs are not initialized by a Power-on opcode for the data memory address. When ‘a’ is ‘0’, Reset and are unchanged on all other Resets. © 2009 Microchip Technology Inc. DS39689F-page 67

PIC18F2221/2321/4221/4321 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associ- ated with the “core” device functionality (ALU, Resets The Special Function Registers (SFRs) are registers and interrupts) and those related to the peripheral used by the CPU and peripheral modules for controlling functions. The reset and interrupt registers are the desired operation of the device. These registers are described in their respective chapters, while the ALU’s implemented as static RAM. SFRs start at the top of STATUS register is described later in this section. data memory (FFFh) and extend downward to occupy Registers related to the operation of a peripheral feature the top half of Bank 15 (F80h to FFFh). A list of these are described in the chapter for that peripheral. registers is given in Table6-1 and Table6-2. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2221/2321/4221/4321 FAMILY DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2) FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL(3) F97h —(2) FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3) FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2) FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2) FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2) FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2) FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2) FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on 28-pin devices. DS39689F-page 68 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 55, 60 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 55, 60 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 55, 60 STKPTR STKFUL(6) STKUNF(6) — SP4 SP3 SP2 SP1 SP0 00-0 0000 55, 61 PCLATU — — Holding Register for PC<21:16> --00 0000 55, 60 PCLATH Holding Register for PC<15:8> 0000 0000 55, 60 PCL PC Low Byte (PC<7:0>) 0000 0000 55, 60 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 55, 82 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 55, 82 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 55, 82 TABLAT Program Memory Table Latch 0000 0000 55, 82 PRODH Product Register High Byte xxxx xxxx 55, 95 PRODL Product Register Low Byte xxxx xxxx 55, 95 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 55, 99 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 55, 100 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 55, 101 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 55, 74 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 55, 74 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 55, 74 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 55, 74 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 55, 74 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 55, 74 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 55, 74 WREG Working Register xxxx xxxx 55 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 55, 74 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 55, 74 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 55, 74 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 55, 74 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A 55, 74 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 56, 74 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 56, 74 BSR — — — — Bank Select Register ---- 0000 56, 65 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 56, 74 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 56, 74 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 56, 74 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 56, 74 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A 56, 74 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 56, 74 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 56, 74 STATUS — — — N OV Z DC C ---x xxxx 56, 72 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software or by a POR. © 2009 Microchip Technology Inc. DS39689F-page 69

PIC18F2221/2321/4221/4321 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR page: TMR0H Timer0 Register High Byte 0000 0000 56, 131 TMR0L Timer0 Register Low Byte xxxx xxxx 56, 131 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 56, 129 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 37, 56 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 56, 253 WDTCON — — — — — — — SWDTEN --- ---0 56, 270 RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 48, 54, 108 TMR1H Timer1 Register High Byte xxxx xxxx 56, 137 TMR1L Timer1 Register Low Byte xxxx xxxx 56, 137 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 56, 133 TMR2 Timer2 Register 0000 0000 56, 140 PR2 Timer2 Period Register 1111 1111 56, 140 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 56, 139 SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 56, 175, 176 SSPADD MSSP Address Register in I2C™ Slave mode. MSSP Baud Rate Reload Register in I2C Master mode. 0000 0000 56, 176 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 56, 168, 177 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 56, 169, 178 SSPCON2 GCEN ACKSTAT ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/ SEN 0000 0000 56, 179 ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 ADRESH A/D Result Register High Byte xxxx xxxx 57, 242 ADRESL A/D Result Register Low Byte xxxx xxxx 57, 242 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 57, 233 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 57, 234 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 57, 235 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 57, 146 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 57, 146 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 57, 145, 153 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 57, 146 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 57, 146 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 57, 145 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 57, 214 ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 0000 0000 57, 162 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 0000 0000 57, 163 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 57, 249 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 57, 243 TMR3H Timer3 Register High Byte xxxx xxxx 57, 143 TMR3L Timer3 Register Low Byte xxxx xxxx 57, 143 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 57, 141 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software or by a POR. DS39689F-page 70 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED) Value on Details on File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR page: SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 57, 216 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 57, 216 RCREG EUSART Receive Register 0000 0000 57, 224 TXREG EUSART Transmit Register 0000 0000 57, 221 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 57, 212 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 57, 213 EEADR EEPROM Address Register 0000 0000 57, 80, 89 EEDATA EEPROM Data Register 0000 0000 57, 80, 89 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 57, 80, 89 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 57, 81, 90 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 11-1 1111 58, 107 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 00-0 0000 58, 103 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 00-0 0000 58, 105 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 58, 106 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 58, 102 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 58, 104 OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 33, 58 TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 58, 124 TRISD(2) PORTD Data Direction Control Register 1111 1111 58, 120 TRISC PORTC Data Direction Control Register 1111 1111 58, 117 TRISB PORTB Data Direction Control Register 1111 1111 58, 114 TRISA TRISA7(5) TRISA6(5) PORTA Data Direction Control Register 1111 1111 58, 111 LATE(2) — — — — — PORTE Data Latch Register ---- -xxx 58, 123 (Read and Write to Data Latch) LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 58, 120 LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 58, 117 LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 58, 114 LATA LATA7(5) LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 58, 111 PORTE — — — — RE3(4) RE2(2) RE1(2) RE0(2) ---- xxxx 58, 123 PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 58, 120 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 58, 117 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 58, 114 PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 58, 111 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0); otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software or by a POR. © 2009 Microchip Technology Inc. DS39689F-page 71

PIC18F2221/2321/4221/4321 FAMILY 6.3.5 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register6-2, contains register, because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an instruc- the instruction set summaries in Table24-2 and tion that affects the Z, DC, C, OV or N bits, the results Table24-3. of the instruction are not written; instead, the STATUS register is updated according to the instruction Note: The C and DC bits operate as the borrow performed. Therefore, the result of an instruction with and digit borrow bits, respectively, in the STATUS register as its destination may be different subtraction. than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). REGISTER 6-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 72 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 6.4 Data Addressing Modes The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR Note: The execution of some instructions in the (Section6.3.1 “Bank Select Register (BSR)”) are core PIC18 instruction set are changed used with the address to determine the complete 12-bit when the PIC18 extended instruction set is address of the register. When ‘a’ is ‘0’, the address is enabled. See Section6.5 “Data Memory interpreted as being a register in the Access Bank. and the Extended Instruction Set” for Addressing that uses the Access RAM is sometimes more information. also known as Direct Forced Addressing mode. The data memory space can be addressed in several A few instructions, such as MOVFF, include the entire ways. For most instructions, the addressing mode is 12-bit address (either source or destination) in their fixed. Other instructions may use up to three modes, opcodes. In these cases, the BSR is ignored entirely. depending on which operands are used and whether or The destination of the operation’s results is determined not the extended instruction set is enabled. by the destination bit ‘d’. When ‘d’ is ‘1’, the results are The addressing modes are: stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Inherent the W register. Instructions without the ‘d’ argument • Literal have a destination that is implicit in the instruction; their • Direct destination is either the target register being operated • Indirect on or the W register. An additional addressing mode, Indexed Literal Offset, 6.4.3 INDIRECT ADDRESSING is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is Indirect addressing allows the user to access a location discussed in greater detail in Section6.5.1 “Indexed in data memory without giving a fixed address in the Addressing with Literal Offset”. instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written 6.4.1 INHERENT AND LITERAL to. Since the FSRs are themselves located in RAM as ADDRESSING Special Function Registers, they can also be directly manipulated under program control. This makes FSRs Many PIC18 control instructions do not need any very useful in implementing data structures, such as argument at all; they either perform an operation that tables and arrays in data memory. globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent The registers for indirect addressing are also Addressing. Examples include SLEEP, RESET and DAW. implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with Other instructions work in a similar way but require an auto-incrementing, auto-decrementing or offsetting additional explicit argument in the opcode. This is with another value. This allows for efficient code, using known as Literal Addressing mode because they loops, such as the example of clearing an entire RAM require some literal value as an argument. Examples bank in Example6-5. include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples EXAMPLE 6-5: HOW TO CLEAR RAM include CALL and GOTO, which include a 20-bit (BANK 1) USING program memory address. INDIRECT ADDRESSING 6.4.2 DIRECT ADDRESSING LFSR FSR0, 100h ; Direct addressing specifies all or part of the source NEXT CLRF POSTINC0 ; Clear INDF and/or destination address of the operation within the ; register then ; inc pointer opcode itself. The options are specified by the BTFSS FSR0H,1 ; All done with arguments accompanying the instruction. ; Bank1? In the core PIC18 instruction set, bit-oriented and byte- BRA NEXT ; NO, clear next oriented instructions use some version of direct CONTINUE ; YES, continue addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section6.3.3 “General Purpose Register File”) or a location in the Access Bank (Section6.3.2 “Access Bank”) as the data source for the instruction. © 2009 Microchip Technology Inc. DS39689F-page 73

PIC18F2221/2321/4221/4321 FAMILY 6.4.3.1 FSR Registers and the 6.4.3.2 FSR Registers and POSTINC, INDF Operand POSTDEC, PREINC and PLUSW At the core of indirect addressing are three sets of In addition to the INDF operand, each FSR register pair registers: FSR0, FSR1 and FSR2. Each represents a also has four additional indirect operands. Like INDF, pair of 8-bit registers, FSRnH and FSRnL. The four these are “virtual” registers that cannot be indirectly upper bits of the FSRnH register are not used so each read or written to. Accessing these registers actually FSR pair holds a 12-bit value. This represents a value accesses the associated FSR register pair, but also that can address the entire range of the data memory performs a specific action on its stored value. They are: in a linear fashion. The FSR register pairs, then, serve • POSTDEC: accesses the FSR value, then as pointers to data memory locations. automatically decrements it by 1 afterwards Indirect addressing is accomplished with a set of • POSTINC: accesses the FSR value, then Indirect File Operands, INDF0 through INDF2. These automatically increments it by 1 afterwards can be thought of as “virtual” registers: they are • PREINC: increments the FSR value by 1, then mapped in the SFR space but are not physically imple- uses it in the operation mented. Reading or writing to a particular INDF register • PLUSW: adds the signed value of the W register actually accesses its corresponding FSR register pair. (range of -127 to 128) to that of the FSR and uses A read from INDF1, for example, reads the data at the the new value in the operation. address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the In this context, accessing an INDF register uses the contents of their corresponding FSR as a pointer to the value in the FSR registers without changing them. Sim- instruction’s target. The INDF operand is just a ilarly, accessing a PLUSW register gives the FSR value convenient way of using the pointer. offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual Because indirect addressing uses a full 12-bit address, registers changes the value of the FSR registers. data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no Operations on the FSRs with POSTDEC, POSTINC effect on determining the target address. and PREINC affect the entire register pair; that is, roll- overs of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). FIGURE 6-7: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 indirect addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h ECCh. This means the contents of Bank 14 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory DS39689F-page 74 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY The PLUSW register can be used to implement a form 6.5.1 INDEXED ADDRESSING WITH of indexed addressing in the data memory space. By LITERAL OFFSET manipulating the value in the W register, users can Enabling the PIC18 extended instruction set changes reach addresses that are fixed offsets from pointer the behavior of indirect addressing using the FSR2 addresses. In some applications, this can be used to register pair within Access RAM. Under the proper implement some powerful program control structure, conditions, instructions that use the Access Bank – that such as software stacks, inside of data memory. is, most bit-oriented and byte-oriented instructions – can 6.4.3.3 Operations by FSRs on FSRs invoke a form of indexed addressing using an offset specified in the instruction. This special addressing Indirect addressing operations that target other FSRs or mode is known as Indexed Addressing with Literal virtual registers represent special cases. For example, Offset, or Indexed Literal Offset mode. using an FSR to point to one of the virtual registers will When using the extended instruction set, this not result in successful operations. As a specific case, addressing mode requires the following: assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using • The use of the Access Bank is forced (‘a’ = 0); INDF0 as an operand will return 00h. Attempts to write and to INDF1 using INDF0 as the operand will result in a NOP. • The file address argument is less than or equal to On the other hand, using the virtual registers to write to 5Fh. an FSR pair may not occur as planned. In these cases, Under these conditions, the file address of the instruc- the value will be written to the FSR pair but without any tion is not interpreted as the lower byte of an address incrementing or decrementing. Thus, writing to INDF2 (used with the BSR in direct addressing), or as an 8-bit or POSTDEC2 will write the same value to the address in the Access Bank. Instead, the value is FSR2H:FSR2L. interpreted as an offset value to an Address Pointer, Since the FSRs are physical registers mapped in the specified by FSR2. The offset and the contents of SFR space, they can be manipulated through all direct FSR2 are added to obtain the target address of the operations. Users should proceed cautiously when operation. working on these registers, particularly if their code 6.5.2 INSTRUCTIONS AFFECTED BY uses indirect addressing. INDEXED LITERAL OFFSET MODE Similarly, operations by indirect addressing are generally permitted on all other SFRs. Users should exercise the Any of the core PIC18 instructions that can use direct appropriate caution that they do not inadvertently addressing are potentially affected by the Indexed change settings that might affect the operation of the Literal Offset Addressing mode. This includes all device. byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. 6.5 Data Memory and the Extended Instructions that only use Inherent or Literal Addressing modes are unaffected. Instruction Set Additionally, byte-oriented and bit-oriented instructions Enabling the PIC18 extended instruction set (XINST are not affected if they do not use the Access Bank Configuration bit = 1) significantly changes certain (Access RAM bit is ‘1’), or include a file address of 60h aspects of data memory and its addressing. Specifically, or above. Instructions meeting these criteria will the use of the Access Bank for many of the core PIC18 continue to execute as before. A comparison of the dif- instructions is different. This is due to the introduction of ferent possible addressing modes when the extended a new addressing mode for the data memory space. instruction set is enabled is shown in Figure6-8. What does not change is just as important. The size of Those who desire to use bit-oriented or byte-oriented the data memory space is unchanged, as well as its instructions in the Indexed Literal Offset mode should linear addressing. The SFR map remains the same. note the changes to assembler syntax for this mode. Core PIC18 instructions can still operate in both Direct This is described in more detail in Section24.2.1 and Indirect Addressing mode; inherent and literal “Extended Instruction Syntax”. instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2009 Microchip Technology Inc. DS39689F-page 75

PIC18F2221/2321/4221/4321 FAMILY FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When ‘a’ = 0 and ‘f’ ≥ 60h: The instruction executes in 060h 080h Direct Forced mode. ‘f’ is inter- Bank 0 preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 through 60h locations 060h to 07Fh Bank 14 80h (Bank0) and F80h to FFFh Valid range for ‘f’ (Bank 15) of data memory. FFh Locations below 60h are not F00h Access RAM available in this addressing Bank 15 mode. F80h SFRs FFFh Data Memory When ‘a’ = 0 and ‘f’ ≤ 5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 080h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F80h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When ‘a’ = 1 (all values of ‘f’): 000h 00000000 The instruction executes in Bank 0 080h Direct mode (also known as Direct Long mode). ‘f’ is inter- 100h preted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F80h SFRs FFFh Data Memory DS39689F-page 76 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 6.5.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET tions using the Indexed Literal Offset Addressing ADDRESSING MODE mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access 6.6 PIC18 Instruction Execution and RAM (00h to 5Fh) are mapped. Rather than containing the Extended Instruction Set just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined Enabling the extended instruction set adds eight “window” that can be located anywhere in the data additional commands to the existing PIC18 instruction memory space. The value of FSR2 establishes the set. These instructions are executed as described in lower boundary of the addresses mapped into the Section24.2 “Extended Instruction Set”. window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section6.3.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure6-9. FIGURE 6-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING MODE Example Situation: 000h ADDWF f, d, a Bank 0 05Fh FSR2H:FSR2L = 120h 07Fh Locations in the region Bank 0 from the FSR2 Pointer 100h Bank 1 (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Locations in Bank 0, from Bank 0 060h to 07Fh, are mapped 7Fh as usual to the middle of Bank 2 80h the Access Bank. through SFRs Special Function Regis- Bank 14 ters at F80h through FFFh FFh are mapped to 80h Access Bank through FFh, as usual. F00h Bank 0 addresses below Bank 15 5Fh can still be addressed F80h by using the BSR. SFRs FFFh Data Memory © 2009 Microchip Technology Inc. DS39689F-page 77

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 78 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 8 bytes at a time. Program memory is erased The program memory space is 16 bits wide, while the in blocks of 64 bytes at a time. A bulk erase operation data RAM space is 8 bits wide. Table reads and table may not be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and place it into the data RAM space. or erase, therefore, code cannot execute. An internal Figure7-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory A value written to program memory does not need to be space into holding registers in program memory. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section7.5 “Writing NOP. to Flash Program Memory”. Figure7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. DS39689F-page 79

PIC18F2221/2321/4221/4321 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section7.5 “Writing to Flash Program Memory”. 7.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register On power-up, the WREN bit is clear. The WRERR bit is • TABLAT register set in hardware when the WR bit is set and cleared • TBLPTR registers when the internal programming timer expires and the write operation is complete. 7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR bit The EECON1 register (Register7-1) is the control may read as ‘1’. This can indicate that a register for memory accesses. The EECON2 register is write operation was prematurely termi- not a physical register; it is used exclusively in the nated by a Reset, or a write operation was memory write and erase sequences. Reading attempted improperly. EECON2 will read all ‘0’s. The WR control bit initiates write operations. The bit The EEPGD control bit determines if the access will be cannot be cleared, only set, in software; it is cleared in a program or data EEPROM memory access. When hardware at the completion of the write operation. clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent Note: The EEIF interrupt flag bit (PIR2<4>) is set operations will operate on the program memory. when the write is complete. It must be cleared in software. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section24.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. DS39689F-page 80 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase/write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 81

PIC18F2221/2321/4221/4321 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch register is used to Flash program memory. hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR memory and data RAM. determine which byte is read from program memory into TABLAT. 7.2.3 TBLPTR – TABLE POINTER REGISTER When the timed write to program memory begins (via the WR bit), the 19 MSbs of the TBLPTR The Table Pointer (TBLPTR) register addresses a byte (TBLPTR<21:3>) determine which program memory within the program memory. The TBLPTR is comprised block of 8 bytes is written to. The Table Pointer regis- of three SFR registers: Table Pointer Upper Byte, Table ter’s three LSBs (TBLPTR<2:0>) are ignored. For more Pointer High Byte and Table Pointer Low Byte detail, see Section7.5 “Writing to Flash Program (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- Memory”. ters join to form a 22-bit wide pointer. The low-order 21bits allow the device to address up to 2 Mbytes of When an erase of program memory is executed, the program memory space. The 22nd bit allows access to 16MSbs of the Table Pointer register (TBLPTR<21:6>) the device ID, the user ID and the Configuration bits. point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can Figure7-3 describes the relevant boundaries of update the TBLPTR in one of four ways based on the TBLPTR based on Flash program memory operations. table operation. These operations are shown in Table7-1. These operations on the TBLPTR only affect the low-order 21bits. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE TBLPTR<21:6> TABLE WRITE TBLPTR<21:3> TABLE READ – TBLPTR<21:0> DS39689F-page 82 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 7.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and place it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_ODD © 2009 Microchip Technology Inc. DS39689F-page 83

PIC18F2221/2321/4221/4321 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP control, can larger blocks of program memory be program memory location is: bulk erased. Word erase in the Flash array is not 1. Load Table Pointer register with address of row supported. being erased. When initiating an erase sequence from the micro- 2. Set the EECON1 register for the erase operation: controller itself, a block of 64 bytes of program memory • set EEPGD bit to point to program memory; is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory; TBLPTR<21:6> point to the block being erased. • set WREN bit to enable writes; TBLPTR<5:0> are ignored. • set FREE bit to enable the erase. The EECON1 register commands the erase operation. 3. Disable interrupts. The EEPGD bit must be set to point to the Flash 4. Write 55h to EECON2. program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2. operation. 6. Set the WR bit. This will begin the row erase cycle. For protection, the write initiate sequence for EECON2 must be used. 7. The CPU will stall for duration of the erase (about 2ms using internal timer). A long write is necessary for erasing the internal Flash. 8. Re-enable interrupts. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39689F-page 84 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 7.5 Writing to Flash Program Memory The long write is necessary for programming the internal Flash. Instruction execution is halted while in a The minimum programming block is 4 words or 8bytes. long write cycle. The long write will be terminated by Word or byte programming is not supported. the internal programming timer. Table writes are used internally to load the holding The EEPROM on-chip timer controls the write time. registers needed to program the Flash memory. There The write/erase voltages are generated by an on-chip are 8 holding registers used by the table writes for charge pump, rated to operate over the voltage range programming. of the device. Since the Table Latch (TABLAT) is only a single byte, Note: The default value of the holding registers on the TBLWT instruction may need to be executed 8times device Resets and after write operations is for each programming operation. All of the table write FFh. A write of FFh to a holding register operations will essentially be short writes because only does not modify that byte. This means that the holding registers are written. At the end of updating individual bytes of program memory may be the 8 holding registers, the EECON1 register must be modified, provided that the modification written to in order to start the programming operation with does not attempt to change any bit from a a long write. ‘0’ to a ‘1’. When modifying individual bytes, it is not necessary to load all 8 holding registers before executing a write operation. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxxx7 Holding Register Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY 9. Write 55h to EECON2. WRITE SEQUENCE 10. Write 0AAh to EECON2. The sequence of events for programming an internal 11. Set the WR bit. This will begin the write cycle. program memory location should be: 12. The CPU will stall for duration of the write (about 2ms using internal timer). 1. Read 64 bytes into RAM. 13. Repeat from step 5 seven more times. 2. Update data values in RAM as necessary. 14. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 15. Verify the memory (table read). 4. Execute the row erase procedure. This procedure will require about 18ms to update one 5. Load Table Pointer register with address of first row of 64 bytes of memory. An example of the required byte being written. code is given in Example7-3. 6. Write the 8 bytes into the holding registers. Note: Before setting the WR bit, the Table 7. Set the EECON1 register for the write operation: Pointer address needs to be within the • set EEPGD bit to point to program memory; intended address range of the 8 bytes in the holding register. • clear the CFGS bit to access program memory; • set WREN to enable byte writes. 8. Disable interrupts. © 2009 Microchip Technology Inc. DS39689F-page 85

PIC18F2221/2321/4221/4321 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64' ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; 6 LSB = 0 MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data and increment FSR0 DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word and increment FSR0 MOVWF POSTINC0 MOVLW NEW_DATA_HIGH ; update buffer word MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; 6 LSB = 0 MOVWF TBLPTRL BCF EECON1, CFGS ; point to PROG/EEPROM memory BSF EECON1, EEPGD ; point to Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h ; Required sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write AAh BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts WRITE_BUFFER_BACK MOVLW 8 ; number of write buffer groups of 8 bytes MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L PROGRAM_LOOP MOVLW 8 ; number of bytes in holding register MOVWF COUNTER WRITE_WORD_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data and increment FSR0 MOVWF TABLAT ; present data to table latch TBLWT+* ; short write ; to internal TBLWT holding register, increment ; TBLPTR DECFSZ COUNTER ; loop until buffers are full GOTO WRITE_WORD_TO_HREGS DS39689F-page 86 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BCF INTCON, GIE ; disable interrupts MOVLW 55h ; required sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write AAh BSF EECON1, WR ; start program (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts DECFSZ COUNTER_HI ; loop until done GOTO PROGRAM_LOOP BCF EECON1, WREN ; disable write to memory 7.5.2 WRITE VERIFY 7.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section24.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more detail. 7.5.3 UNEXPECTED TERMINATION OF 7.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section24.5 “Program Verification and Code location just programmed should be verified and repro- Protection” for details on code protection of Flash grammed if needed. If the write operation is interrupted program memory. by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 55 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 55 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 55 TABLAT Program Memory Table Latch 55 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 EECON2 EEPROM Control Register 2 (not a physical register) 57 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 57 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. DS39689F-page 87

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 88 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 8.0 DATA EEPROM MEMORY The EECON1 register (Register8-1) is the control register for data and program memory access. Control The data EEPROM is a nonvolatile memory array, bit EEPGD determines if the access will be to program separate from the data RAM and program memory, that or data EEPROM memory. When clear, operations will is used for long-term storage of program data. It is not access the data EEPROM memory. When set, program directly mapped in either the register file or program memory is accessed. memory space but is indirectly addressed through the Control bit CFGS determines if the access will be to the Special Function Registers (SFRs). The EEPROM is Configuration registers or to program memory/data readable and writable during normal operation over the EEPROM memory. When set, subsequent operations entire VDD range. access Configuration registers. When CFGS is clear, Four SFRs are used to read and write to the data the EEPGD bit selects either program Flash or data EEPROM as well as the program memory. They are: EEPROM memory. • EECON1 The WREN bit, when set, will allow a write operation. • EECON2 On power-up, the WREN bit is clear. The WRERR bit is • EEDATA set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the • EEADR write operation is complete. The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds Note: During normal operation, the WRERR bit the 8-bit data for read/write and the EEADR register is read as ‘1’. This can indicate that a write holds the address of the EEPROM location being operation was prematurely terminated by accessed. a Reset, or a write operation was attempted improperly. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the The WR control bit initiates write operations. The bit location and writes the new data (erase-before-write). cannot be cleared, only set, in software; it is cleared in The write time is controlled by an on-chip timer. It will hardware at the completion of the write operation. vary with voltage and temperature as well as from chip Note: The EEIF interrupt flag bit (PIR2<4>) is set to chip. Please refer to parameter D122 (Table27-1 in when the write is complete. It must be Section27.0 “Electrical Characteristics”) for exact cleared in software. limits. Control bits, RD and WR, start read and erase/write 8.1 EECON1 and EECON2 Registers operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the Access to the data EEPROM is controlled by two operation. registers: EECON1 and EECON2. These are the same registers which control access to the program memory The RD bit cannot be set when accessing program and are used in a similar manner for the data memory (EEPGD = 1). Program memory is read using EEPROM. table read instructions. See Section7.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. © 2009 Microchip Technology Inc. DS39689F-page 89

PIC18F2221/2321/4221/4321 FAMILY REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 90 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 8.2 Reading the Data EEPROM Additionally, the WREN bit in EECON1 must be set to Memory enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code To read a data memory location, the user must write the execution (i.e., runaway programs). The WREN bit address to the EEADR register, clear the EEPGD should be kept clear at all times, except when updating control bit (EECON1<7>) and then set control bit, RD the EEPROM. The WREN bit is not cleared by (EECON1<0>). The data is available on the very next hardware. instruction cycle; therefore, the EEDATA register can After a write sequence has been initiated, EECON1, be read by the next instruction. EEDATA will hold this EEADR and EEDATA cannot be modified. The WR bit value until another read operation, or until it is written to will be inhibited from being set unless the WREN bit is by the user (during a write operation). set. The WREN bit must be set on a previous instruc- The basic process is shown in Example8-1. tion. Both WR and WREN cannot be set with the same instruction. 8.3 Writing to the Data EEPROM At the completion of the write cycle, the WR bit is Memory cleared in hardware and the EEPROM Interrupt Flag bit, EEIF, is set. The user may either enable this To write an EEPROM data location, the address must interrupt, or poll this bit. EEIF must be cleared by first be written to the EEADR register and the data software. written to the EEDATA register. The sequence in Example8-2 must be followed to initiate the write cycle. 8.4 Write Verify The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to Depending on the application, good programming EECON2, then set WR bit) for each byte. It is strongly practice may dictate that the value written to the mem- recommended that interrupts be disabled during this ory should be verified against the original value. This codesegment. should be used in applications where excessive writes can stress bits near the specification limit. EXAMPLE 8-1: DATA EEPROM READ MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA EXAMPLE 8-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete GOTO $-2 BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set) © 2009 Microchip Technology Inc. DS39689F-page 91

PIC18F2221/2321/4221/4321 FAMILY 8.5 Operation During Code-Protect 8.7 Using the Data EEPROM Data EEPROM memory has its own code-protect bits in The data EEPROM is a high-endurance, byte Configuration Words. External read and write addressable array that has been optimized for the operations are disabled if code protection is enabled. storage of frequently changing data. Such data is typically updated at least one time within the number of The microcontroller itself can both read and write to the writes defined by specification, D124. If any location internal data EEPROM, regardless of the state of the storing data is not written at least this often, the data code-protect Configuration bit. Refer to Section24.0 EEPROM array must be refreshed. For this reason, “Special Features of the CPU” for additional values that change infrequently, or not at all, should be information. stored in Flash program memory. 8.6 Protection Against Spurious Write A simple data EEPROM refresh routine is shown in Example8-3. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, Note: If data EEPROM is only used to store con- the WREN bit is cleared. In addition, writes to the stants and/or data that changes often, an EEPROM are blocked during the Power-up Timer array refresh is likely not required. See period (TPWRT, parameter33). specification, D124. The write initiate sequence and the WREN bit together help prevent an accidental write during Brown-out Reset, power glitch or software malfunction. EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes LOOP ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS39689F-page 92 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 EEADR EEPROM Address Register 57 EEDATA EEPROM Data Register 57 EECON2 EEPROM Control Register 2 (not a physical register) 57 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 57 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. DS39689F-page 93

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 94 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 9.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W advantages of higher computational throughput and MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table9-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 9.2 Operation Example9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 μs Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 μs 6 μs Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs 16 x 16 signed Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs © 2009 Microchip Technology Inc. DS39689F-page 95

PIC18F2221/2321/4221/4321 FAMILY Example9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED unsigned multiplication. Equation9-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) + MULTIPLICATION (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216) = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + EXAMPLE 9-4: 16 x 16 SIGNED (ARG1L • ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L -> EXAMPLE 9-3: 16 x 16 UNSIGNED ; PRODH:PRODL MULTIPLY ROUTINE MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; MOVF ARG1H, W ; Example9-4 shows the sequence to do a 16 x 16 SUBWFB RES3 signed multiply. Equation9-2 shows the algorithm ; used. The 32-bit result is stored in four registers SIGN_ARG1 (RES3:RES0). To account for the sign bits of the BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? arguments, the MSb for each argument pair is tested BRA CONT_CODE ; no, done and the appropriate subtractions are done. MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39689F-page 96 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 10.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are The PIC18F2221/2321/4221/4321 family devices have compatible with PIC® mid-range devices. In multiple interrupt sources and an interrupt priority Compatibility mode, the interrupt priority bits for each feature that allows most interrupt sources to be source have no effect. INTCON<6> is the PEIE bit, assigned a high-priority level or a low-priority level. The which enables/disables all peripheral interrupt sources. high-priority interrupt vector is at 0008h and the low- INTCON<7> is the GIE bit, which enables/disables all priority interrupt vector is at 0018h. High-priority interrupt sources. All interrupts branch to address interrupt events will interrupt any low-priority interrupts 0008h in Compatibility mode. that may be in progress. When an interrupt is responded to, the global interrupt There are ten registers which are used to control enable bit is cleared to disable further interrupts. If the interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a low- • INTCON priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2 PC is loaded with the interrupt vector address (0008h • PIE1, PIE2 or 0018h). Once in the Interrupt Service Routine, the • IPR1, IPR2 source(s) of the interrupt can be determined by polling It is recommended that the Microchip header files the interrupt flag bits. The interrupt flag bits must be supplied with MPLAB® IDE be used for the symbolic bit cleared in software before re-enabling interrupts to names in these registers. This allows the assembler/ avoid recursive interrupts. compiler to automatically take care of the placement of The “return from interrupt” instruction, RETFIE, exits these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL In general, interrupt sources have three bits to control if priority levels are used), which re-enables interrupts. their operation. They are: For external interrupt events, such as the INTx pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set, regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is cause erratic microcontroller behavior. enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vec- tor immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. DS39689F-page 97

PIC18F2221/2321/4221/4321 FAMILY FIGURE 10-1: PIC18 INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU INT1IF Vector to Location INT1IE SSPIF INT1IP 0008h SSPIE INT2IF SSPIP INT2IE INT2IP GIE/GIEH ADIF ADIE ADIP IPEN RCIF IPEN RCIE PEIE/GIEL RCIP IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation SSPIF SSPIE SSPIP Interrupt to CPU TMR0IF Vector to Location TMR0IE 0018h ADIF TMR0IP ADIE ADIP RBIF RBIE RCIF RBIP GIE/GIEH RCIE PEIE/GIEL RCIP INT1IF INT1IE INT1IP Additional Peripheral Interrupts INT2IF INT2IE INT2IP DS39689F-page 98 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 10.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers, which contain various enable, priority and interrupt enable bit. User software should flag bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 99

PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39689F-page 100 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. DS39689F-page 101

PIC18F2221/2321/4221/4321 FAMILY 10.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). 2: User software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred Note1: This bit is unimplemented on 28-pin devices and will read as ‘0’. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 102 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A high/low-voltage condition occurred; direction determined by VDIRMAG bit (HLVDCON<7>) 0 = A high/low-voltage condition has not occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 103

PIC18F2221/2321/4221/4321 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note1: This bit is unimplemented on 28-pin devices and will read as ‘0’. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 104 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 105

PIC18F2221/2321/4221/4321 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority Note1: This bit is unimplemented on 28-pin devices and will read as ‘0’. bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 106 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 10-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 107

PIC18F2221/2321/4221/4321 FAMILY 10.5 RCON Register The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section5.1 “RCON The RCON register contains flag bits which are used to Register”. determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 10-10: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16XXX Compatibility mode) bit 6 SBOREN: Software BOR Enable bit(1) For details of bit operation, see Register5-1. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register5-1. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register5-1. bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register5-1. bit 1 POR: Power-on Reset Status bit(2) For details of bit operation, see Register5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register5-1. Note1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: Actual Reset values are determined by device configuration and the nature of the device Reset. See Register5-1 for additional information. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 108 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and In 8-bit mode (which is the default), an overflow in the RB2/INT2 pins are edge-triggered. If the corresponding TMR0 register (FFh→00h) will set flag bit, TMR0IF. In INTEDGx bit in the INTCON2 register is set (= 1), the 16-bit mode, an overflow in the TMR0H:TMR0L interrupt is triggered by a rising edge; if the bit is clear, register pair (FFFFh → 0000h) will set TMR0IF. The the trigger is on the falling edge. When a valid edge interrupt can be enabled/disabled by setting/clearing appears on the RBx/INTx pin, the corresponding flag enable bit, TMR0IE (INTCON<5>). Interrupt priority for bit, INTxF, is set. This interrupt can be disabled by Timer0 is determined by the value contained in the clearing the corresponding enable bit, INTxE. Flag bit, interrupt priority bit, TMR0IP (INTCON2<2>). See INTxF, must be cleared in software in the Interrupt Section12.0 “Timer0 Module” for further details on Service Routine before re-enabling the interrupt. the Timer0 module. All external interrupts (INT0, INT1 and INT2) can wake- 10.8 PORTB Interrupt-on-Change up the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global An input change on PORTB<7:4> sets flag bit, RBIF Interrupt Enable bit, GIE, is set, the processor will (INTCON<0>). The interrupt can be enabled/disabled branch to the interrupt vector following wake-up. by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for INT1 and INT2 is determined by Interrupt priority for PORTB interrupt-on-change is the value contained in the interrupt priority bits, determined by the value contained in the interrupt INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). priority bit, RBIP (INTCON2<0>). There is no priority bit associated with INT0. It is always a high-priority interrupt source. 10.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS © 2009 Microchip Technology Inc. DS39689F-page 109

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 110 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 11.0 I/O PORTS Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. Depending on the device selected and features The Data Latch (LATA) register is also memory mapped. enabled, there are up to five ports available. Some pins Read-modify-write operations on the LATA register read of the I/O ports are multiplexed with an alternate and write the latched output value for PORTA. function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not The RA4 pin is multiplexed with the Timer0 module be used as a general purpose I/O pin. clock input and one of the comparator outputs to become the RA4/T0CKI/C1OUT pin. Pins RA6 and Each port has three registers for its operation. These RA7 are multiplexed with the main oscillator pins. They registers are: are enabled as oscillator or I/O pins by the selection of • TRIS register (Data Direction register) the main oscillator in the Configuration register (see • PORT register (reads the levels on the pins of the Section24.1 “Configuration Bits” for details). When device) they are not used as port pins, RA6 and RA7 and their • LAT register (Data Latch register) associated TRIS and LAT bits are read as ‘0’. The Data Latch (LAT register) is useful for read-modify- The other PORTA pins are multiplexed with analog write operations on the value that the I/O pins are inputs, the analog VREF+ and VREF- inputs and the driving. comparator voltage reference output. The operation of pins RA<3:0> and RA5 as A/D converter inputs is A simplified model of a generic I/O port, without the selected by clearing or setting the control bits in the interfaces to other peripherals, is shown in Figure11-1. ADCON1 register (A/D Control Register 1). FIGURE 11-1: GENERIC I/O PORT Pins RA0 through RA5 may also be used as comparator inputs or outputs by setting the appropriate bits in the OPERATION CMCON register. To use RA<3:0> as digital inputs, it is also necessary to turn off the comparators. RD LAT Note: On a Power-on Reset, RA5 and RA<3:0> Data are configured as analog inputs and read Bus D Q as ‘0’. RA4 is configured as a digital input. WR LAT I/O pin(1) orPORT The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input. CK All other PORTA pins have TTL input levels and full Data Latch CMOS output drivers. D Q The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. WR TRIS CK The user must ensure the bits in the TRISA register are TRIS Latch Input maintained set when using them as analog inputs. Buffer EXAMPLE 11-1: INITIALIZING PORTA RD TRIS CLRF PORTA ; Initialize PORTA by ; clearing output Q D ; data latches CLRF LATA ; Alternate method ENEN ; to clear output ; data latches RD PORT MOVLW 0Fh ; Configure all A/D MOVWF ADCON1 ; for digital inputs Note1: I/O pins have diode protection to VDD and VSS. MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to 11.1 PORTA, TRISA and LATA Registers ; initialize data ; direction PORTA is an 8-bit wide, bidirectional port. The corre- MOVWF TRISA ; Set RA<7:6,3:0> as inputs sponding Data Direction register is TRISA. Setting a ; RA<5:4> as outputs TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2009 Microchip Technology Inc. DS39689F-page 111

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-1: PORTA I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D Input Channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D Input Channel 1 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RA2/AN2/ RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when VREF-/CVREF CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D Input Channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and comparator voltage reference low input. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D Input Channel 3 and Comparator C1+ input. Default input configuration on POR. VREF+ 1 I ANA A/D and comparator voltage reference high input. RA4/T0CKI/C1OUT RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI 1 I ST Timer0 clock input. C1OUT 0 O DIG Comparator 1 output; takes priority over port data. RA5/AN4/SS/ RA5 0 O DIG LATA<5> data output; not affected by analog input. HLVDIN/C2OUT 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D Input Channel 4. Default configuration on POR. SS 1 I TTL Slave Select input for MSSP (MSSP module). HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. OSC2/CLKO/RA6 RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes). CLKO x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator modes. OSC1/CLKI/RA7 RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes. 1 I TTL PORTA<7> data input. Disabled in external oscillator modes. OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS39689F-page 112 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 58 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 58 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 58 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 57 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 57 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 113

PIC18F2221/2321/4221/4321 FAMILY 11.2 PORTB, TRISB and LATB Four of the PORTB pins (RB<7:4>) have an interrupt- Registers on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin PORTB is an 8-bit wide, bidirectional port. The configured as an output is excluded from the interrupt- corresponding Data Direction register is TRISB. Setting on-change comparison). The input pins (of RB<7:4>) a TRISB bit (= 1) will make the corresponding PORTB are compared with the old value latched on the last pin an input (i.e., put the corresponding output driver in read of PORTB. The “mismatch” outputs of RB<7:4> a High-Impedance mode). Clearing a TRISB bit (= 0) are ORed together to generate the RB Port Change will make the corresponding PORTB pin an output (i.e., Interrupt with Flag bit, RBIF (INTCON<0>). put the contents of the output latch on the selected pin). This interrupt can wake the device from Sleep mode or The Data Latch register (LATB) is also memory any of the Idle modes. The user, in the Interrupt Service mapped. Read-modify-write operations on the LATB Routine, can clear the interrupt in the following manner: register read and write the latched output value for a) Any read or write of PORTB (except with the PORTB. MOVFF (ANY), PORTB instruction). b) 1 TCY. EXAMPLE 11-2: INITIALIZING PORTB c) Clear flag bit, RBIF. CLRF PORTB ; Initialize PORTB by ; clearing output A mismatch condition will continue to set flag bit, RBIF. ; data latches Reading PORTB and waiting 1 TCY will end the CLRF LATB ; Alternate method mismatch condition and allow flag bit, RBIF, to be ; to clear output cleared. Also, if the port pin returns to its original state, ; data latches the mismatch condition will be cleared. MOVLW 0Fh ; Set RB<4:0> as The interrupt-on-change feature is recommended for MOVWF ADCON1 ; digital I/O pins ; (required if config bit wake-up on key depression operation and operations ; PBADEN is set) where PORTB is only used for the interrupt-on-change MOVLW 0CFh ; Value used to feature. Polling of PORTB is not recommended while ; initialize data using the interrupt-on-change feature. ; direction RB3 can be configured by the Configuration bit, MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs CCP2MX, as the alternate peripheral pin for the CCP2 ; RB<7:6> as inputs module (CCP2MX = 0). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB<4:0> are configured as analog inputs by default and read as ‘0’; RB<7:5> are configured as digital inputs. By clearing the Configuration bit, PBADEN, RB<4:0> will alternatively be configured as digital inputs on POR. DS39689F-page 114 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-3: PORTB I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RB0/INT0/FLT0/ RB0 0 O DIG LATB<0> data output; not affected by analog input. AN12 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT0 1 I ST External Interrupt 0 input. FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. AN12 1 I ANA A/D Input Channel 12.(1) RB1/INT1/AN10 RB1 0 O DIG LATB<1> data output; not affected by analog input. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT1 1 I ST External Interrupt 1 input. AN10 1 I ANA A/D Input Channel 10.(1) RB2/INT2/AN8 RB2 0 O DIG LATB<2> data output; not affected by analog input. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT2 1 I ST External Interrupt 2 input. AN8 1 I ANA A/D Input Channel 8.(1) RB3/AN9/CCP2 RB3 0 O DIG LATB<3> data output; not affected by analog input. 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) AN9 1 I ANA A/D Input Channel 9.(1) CCP2(2) 0 O DIG CCP2 compare and PWM output. 1 I ST CCP2 capture input. RB4/KBI0/AN11 RB4 0 O DIG LATB<4> data output; not affected by analog input. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) KBI0 1 I TTL Interrupt-on-change pin. AN11 1 I ANA A/D Input Channel 11.(1) RB5/KBI1/PGM RB5 0 O DIG LATB<5> data output. 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt-on-change pin. PGM x I ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP Configuration bit; all other pin functions disabled. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-change pin. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(3) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-change pin. PGD x O DIG Serial execution data output for ICSP and ICD operation.(3) x I ST Serial execution data input for ICSP and ICD operation.(3) Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2009 Microchip Technology Inc. DS39689F-page 115

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 58 LATB PORTB Data Latch Register (Read and Write to Data Latch) 58 TRISB PORTB Data Direction Register 58 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 55 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 55 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. DS39689F-page 116 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 11.3 PORTC, TRISC and LATC Note: On a Power-on Reset, these pins are Registers configured as digital inputs. PORTC is an 8-bit wide, bidirectional port. The The contents of the TRISC register are affected by corresponding Data Direction register is TRISC. Set- peripheral overrides. Reading TRISC always returns ting a TRISC bit (= 1) will make the corresponding the current contents, even though a peripheral device PORTC pin an input (i.e., put the corresponding output may be overriding one or more of the pins. driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an EXAMPLE 11-3: INITIALIZING PORTC output (i.e., put the contents of the output latch on the CLRF PORTC ; Initialize PORTC by selected pin). ; clearing output The Data Latch register (LATC) is also memory ; data latches mapped. Read-modify-write operations on the LATC CLRF LATC ; Alternate method register read and write the latched output value for ; to clear output PORTC. ; data latches MOVLW 0CFh ; Value used to PORTC is multiplexed with several peripheral functions ; initialize data (Table11-5). The pins have Schmitt Trigger input ; direction buffers. RC1 is normally configured by Configuration MOVWF TRISC ; Set RC<3:0> as inputs bit, CCP2MX, as the default peripheral pin of the CCP2 ; RC<5:4> as outputs module (default/erased state, CCP2MX = 1). ; RC<7:6> as inputs When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. © 2009 Microchip Technology Inc. DS39689F-page 117

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-5: PORTC I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RC0/T1OSO/ RC0 0 O DIG LATC<0> data output. T13CKI 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/CCP2 RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2(1) 0 O DIG CCP2 compare and PWM output; takes priority over port data. 1 I ST CCP2 capture input. RC2/CCP1/P1A RC2 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. CCP1 0 O DIG CCP1 compare or PWM output; takes priority over port data. 1 I ST CCP1 capture input. P1A(2) 0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK/SCL RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data. 1 I ST SPI clock input (MSSP module). SCL 0 O DIG I2C™ clock output (MSSP module); takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP module); input type depends on module setting. RC4/SDI/SDA RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. SDI 1 I ST SPI data input (MSSP module). SDA 1 O DIG I2C data output (MSSP module); takes priority over port data. 1 I I2C/SMB I2C data input (MSSP module); input type depends on module setting. RC5/SDO RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO 0 O DIG SPI data output (MSSP module); takes priority over port data. RC6/TX/CK RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX 1 O DIG Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. CK 1 O DIG Synchronous serial clock output (EUSART module); takes priority over port data. 1 I ST Synchronous serial clock input (EUSART module). RC7/RX/DT RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX 1 I ST Asynchronous serial receive data input (EUSART module). DT 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module). User must configure as an input. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3. 2: Enhanced PWM output is available only on PIC18F4221/4321 devices. DS39689F-page 118 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 58 LATC PORTC Data Latch Register (Read and Write to Data Latch) 58 TRISC PORTC Data Direction Register 58 © 2009 Microchip Technology Inc. DS39689F-page 119

PIC18F2221/2321/4221/4321 FAMILY 11.4 PORTD, TRISD and LATD PORTD can also be configured as an 8-bit wide micro- Registers processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input Note: PORTD is only available on 40/44-pin buffers are TTL. See Section11.6 “Parallel Slave devices. Port” for additional information on the Parallel Slave Port (PSP). PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Set- Note: When the Enhanced PWM mode is used ting a TRISD bit (= 1) will make the corresponding with either dual or quad outputs, the PSP PORTD pin an input (i.e., put the corresponding output functions of PORTD are automatically driver in a High-Impedance mode). Clearing a TRISD disabled. bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the EXAMPLE 11-4: INITIALIZING PORTD selected pin). CLRF PORTD ; Initialize PORTD by The Data Latch register (LATD) is also memory ; clearing output mapped. Read-modify-write operations on the LATD ; data latches register read and write the latched output value for CLRF LATD ; Alternate method ; to clear output PORTD. ; data latches All pins on PORTD are implemented with Schmitt Trigger MOVLW 0CFh ; Value used to input buffers. Each pin is individually configurable as an ; initialize data input or output. ; direction MOVWF TRISD ; Set RD<3:0> as inputs Three of the PORTD pins are multiplexed with outputs ; RD<5:4> as outputs P1B, P1C and P1D of the Enhanced CCP module. The ; RD<7:6> as inputs operation of these additional PWM output pins is covered in greater detail in Section17.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39689F-page 120 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-7: PORTD I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. PSP0 x O DIG PSP read data output (LATD<0>); takes priority over port data. x I TTL PSP write data input. RD1/PSP1 RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. PSP1 x O DIG PSP read data output (LATD<1>); takes priority over port data. x I TTL PSP write data input. RD2/PSP2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. PSP2 x O DIG PSP read data output (LATD<2>); takes priority over port data. x I TTL PSP write data input. RD3/PSP3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. PSP3 x O DIG PSP read data output (LATD<3>); takes priority over port data. x I TTL PSP write data input. RD4/PSP4 RD4 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. PSP4 x O DIG PSP read data output (LATD<4>); takes priority over port data. x I TTL PSP write data input. RD5/PSP5/P1B RD5 0 O DIG LATD<5> data output. 1 I ST PORTD<5> data input. PSP5 x O DIG PSP read data output (LATD<5>); takes priority over port data. x I TTL PSP write data input. P1B 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD6/PSP6/P1C RD6 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input. PSP6 x O DIG PSP read data output (LATD<6>); takes priority over port data. x I TTL PSP write data input. P1C 0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD7/PSP7/P1D RD7 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. PSP7 x O DIG PSP read data output (LATD<7>); takes priority over port data. x I TTL PSP write data input. P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. DS39689F-page 121

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 58 LATD PORTD Data Latch Register (Read and Write to Data Latch) 58 TRISD PORTD Data Direction Register 58 TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 58 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. DS39689F-page 122 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 11.5 PORTE, TRISE and LATE The fourth pin of PORTE (MCLR/VPP/RE3) is an input Registers only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), Depending on the particular PIC18F2221/2321/4221/ it functions as a digital input only pin; as such, it does not 4321 family device selected, PORTE is implemented in have TRIS or LAT bits associated with its operation. two different ways. Otherwise, it functions as the device’s Master Clear For 40/44-pin devices, PORTE is a 4-bit wide port. input. In either configuration, RE3 also functions as the Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ programming voltage input during programming. AN7) are individually configurable as inputs or outputs. Note: On a Power-on Reset, RE3 is enabled as These pins have Schmitt Trigger input buffers. When a digital input only if Master Clear selected as analog inputs, these pins will read as ‘0’. functionality is disabled. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding EXAMPLE 11-5: INITIALIZING PORTE PORTE pin an input (i.e., put the corresponding output CLRF PORTE ; Initialize PORTE by driver in a High-Impedance mode). Clearing a TRISE ; clearing output bit (= 0) will make the corresponding PORTE pin an ; data latches output (i.e., put the contents of the output latch on the CLRF LATE ; Alternate method selected pin). ; to clear output ; data latches TRISE controls the direction of the RE pins, even when MOVLW 0Fh ; Configure A/D they are being used as analog inputs. The user must MOVWF ADCON1 ; for digital inputs make sure to keep the pins configured as inputs when MOVLW 03h ; Value used to using them as analog inputs. ; initialize data ; direction Note: On a Power-on Reset, RE<2:0> are MOVWF TRISE ; Set RE<0> as inputs configured as analog inputs. ; RE<1> as outputs ; RE<2> as inputs The upper four bits of the TRISE register also control the operation of the Parallel Slave Port. Their operation 11.5.1 PORTE IN 28-PIN DEVICES is explained in Register11-1. The Data Latch register (LATE) is also memory For 28-pin devices, PORTE is only available when mapped. Read-modify-write operations on the LATE Master Clear functionality is disabled (MCLRE = 0). In these cases, PORTE is a single bit, input only port register, read and write the latched output value for comprised of RE3 only. The pin operates as previously PORTE. described. © 2009 Microchip Technology Inc. DS39689F-page 123

PIC18F2221/2321/4221/4321 FAMILY REGISTER 11-1: TRISE REGISTER (40/44-PIN DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3 Unimplemented: Read as ‘0’ bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 124 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 11-9: PORTE I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RE0/RD/AN5 RE0 0 O DIG LATE<0> data output; not affected by analog input. 1 I ST PORTE<0> data input; disabled when analog input enabled. RD 1 I TTL PSP read enable input (PSP enabled). AN5 1 I ANA A/D Input Channel 5; default input configuration on POR. RE1/WR/AN6 RE1 0 O DIG LATE<1> data output; not affected by analog input. 1 I ST PORTE<1> data input; disabled when analog input enabled. WR 1 I TTL PSP write enable input (PSP enabled). AN6 1 I ANA A/D Input Channel 6; default input configuration on POR. RE2/CS/AN7 RE2 0 O DIG LATE<2> data output; not affected by analog input. 1 I ST PORTE<2> data input; disabled when analog input enabled. CS 1 I TTL PSP write enable input (PSP enabled). AN7 1 I ANA A/D Input Channel 7; default input configuration on POR. MCLR/VPP/RE3(1) MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is set. VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always available, regardless of pin mode. RE3 —(2) I ST PORTE<3> data input; enabled when MCLRE Configuration bit is clear. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin devices. 2: RE3 does not have a corresponding TRIS bit to control data direction. TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE — — — — RE3(1,2) RE2 RE1 RE0 58 LATE(2) — — — — — PORTE Data Latch Register 58 (Read and Write to Data Latch) TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 58 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2009 Microchip Technology Inc. DS39689F-page 125

PIC18F2221/2321/4221/4321 FAMILY 11.6 Parallel Slave Port The timing for the control signals in Write and Read modes is shown in Figure11-3 and Figure11-4, Note: The Parallel Slave Port is only available on respectively. 40/44-pin devices. FIGURE 11-2: PORTD AND PORTE In addition to its function as a general I/O port, PORTD BLOCK DIAGRAM can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is (PARALLEL SLAVE PORT) controlled by the 4 upper bits of the TRISE register (Register11-1). Setting control bit, PSPMODE One bit of PORTD (TRISE<4>), enables PSP operation as long as the Data Bus Enhanced CCP module is not operating in Dual Output D Q or Quad Output PWM mode. In Slave mode, the port is RDx pin asynchronously readable and writable by the external WR LATD CK or world. WR PORTD Data Latch TTL The PSP can directly interface to an 8-bit micro- processor data bus. The external microprocessor can Q D read or write the PORTD latch as an 8-bit latch. Setting the control bit, PSPMODE, enables the PORTE I/O RD PORTD ENEN pins to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits RD LATD of the TRISE register (TRISE<2:0>) must be config- ured as inputs (set). The A/D port configuration bits, Set Interrupt Flag PFCG<3:0> (ADCON1<3:0>), must also be set to a PSPIF (PIR1<7>) value in the range of ‘1010’ through ‘1111’. A write to the PSP occurs when both the CS and WR PORTE Pins lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set Read TTL RD when the write ends. Chip Select A read from the PSP occurs when both the CS and RD TTL CS lines are first detected low. The data in PORTD is read out and the OBF bit is clear. If the user writes new data Write TTL WR to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the Note: I/O pins have diode protection to VDD and VSS. PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP. When this happens, the IBF and OBF bits can be polled and the appropriate action taken. DS39689F-page 126 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 58 LATD PORTD Data Latch Register (Read and Write to Data Latch) 58 TRISD PORTD Data Direction Register 58 PORTE — — — — RE3 RE2 RE1 RE0 58 LATE — — — — — PORTE Data Latch Register 58 (Read and Write to Data Latch) TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 58 INTCON GIE/GIEH PEIE/GIEL TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 127

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 128 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or coun- A simplified block diagram of the Timer0 module in 8-bit ter in both 8-bit or 16-bit modes mode is shown in Figure12-1. Figure12-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 129

PIC18F2221/2321/4221/4321 FAMILY 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter; the timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 12.2 Timer0 Reads and Writes in every clock by default unless a different prescaler value 16-Bit Mode is selected (see Section12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode; it is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0 which is not directly readable nor TMR0 register. writable (refer to Figure12-2). TMR0H is updated with The Counter mode is selected by setting the T0CS bit the contents of the high byte of Timer0 during a read of (= 1). In this mode, Timer0 increments either on every TMR0L. This provides the ability to read all 16 bits of rising or falling edge of pin RA4/T0CKI. The increment- Timer0 without having to verify that the read of the high ing edge is determined by the Timer0 Source Edge and low byte were valid, due to a rollover between Select bit, T0SE (T0CON<4>); clearing this bit selects successive reads of the high and low byte. the rising edge. Restrictions on the external clock input Similarly, a write to the high byte of Timer0 must also are discussed below. take place through the TMR0H Buffer register. The high An external clock source can be used to drive Timer0; byte is updated with the contents of TMR0H when a however, it must meet certain requirements to ensure write occurs to TMR0L. This allows all 16 bits of Timer0 that the external clock can be synchronized with the to be updated at once. FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TOSC Delay) 8 T0CS 3 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 1 SIynntecr nwaitlh TMR0L HTigMh RB0yte STMetR 0IF T0CKI pin Programmable 0 Clocks 8 on Overflow Prescaler T0SE (2 TOSC Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39689F-page 130 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>) which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before re- TMR0, BSF TMR0, etc.) clear the prescaler count. enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TMR0L Timer0 Register Low Byte 56 TMR0H Timer0 Register High Byte 56 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 56 TRISA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 58 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 131

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 132 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 13.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure13-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure13-2. features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt-on-overflow Timer1 is controlled through the T1CON Control • Reset on CCP Special Event Trigger register (Register13-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 =Timer1 oscillator is enabled 0 =Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 133

PIC18F2221/2321/4221/4321 FAMILY 13.1 Timer1 Operation cycle (Fosc/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI and RC0/ • Synchronous Counter T1OSO/T13CKI pins become inputs. This means the • Asynchronous Counter values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Peripheral Clock T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 TMR1L HiTgMh RB1yte STMetR 1IF (CCP Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Peripheral Clock T1OSCEN(1) TMR1CS Timer1 T1CKPS<1:0> On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HiTgMh RB1yte STMetR 1IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39689F-page 134 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 13.2 Timer1 16-Bit Read/Write Mode TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Timer1 can be configured for 16-bit reads and writes (see Figure13-2). When the RD16 control bit Osc Type Freq C1 C2 (T1CON<7>) is set, the address for TMR1H is mapped LP 32kHz 27pF(1) 27pF(1) to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Note1: Microchip suggests these values as a Timer1 into the Timer1 high byte buffer. This provides starting point in validating the oscillator the user with the ability to accurately read all 16 bits of circuit. Timer1 without having to determine whether a read of 2: Higher capacitance increases the stability the high byte, followed by a read of the low byte, has of the oscillator but also increases the become invalid due to a rollover between reads. start-up time. A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for write occurs to TMR1L. This allows a user to write all appropriate values of external 16 bits to both the high and low bytes of Timer1 at once. components. The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance writable in this mode. All reads and writes must take only. place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. 13.3.1 USING TIMER1 AS A The prescaler is only cleared on writes to TMR1L. CLOCK SOURCE 13.3 Timer1 Oscillator The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select An on-chip crystal oscillator circuit is incorporated bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device between pins T1OSI (input) and T1OSO (amplifier switches to SEC_RUN mode; both the CPU and output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the Enable bit, T1OSCEN (T1CON<3>). The oscillator is a IDLEN bit (OSCCON<7>) is cleared and a SLEEP low-power circuit rated for 32kHz crystals. It will instruction is executed, the device enters SEC_IDLE continue to run during all power-managed modes. The mode. Additional details are available in Section4.0 circuit for a typical LP oscillator is shown in Figure13-3. “Power-Managed Modes”. Table13-1 shows the capacitor selection for the Timer1 Whenever the Timer1 oscillator is providing the clock oscillator. source, the Timer1 system clock status flag, T1RUN The user must provide a software time delay to ensure (T1CON<6>), is set. This can be used to determine the proper start-up of the Timer1 oscillator. controller’s current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe FIGURE 13-3: EXTERNAL COMPONENTS Clock Monitor. If the Clock Monitor is enabled and the FOR THE TIMER1 Timer1 oscillator fails while providing the clock, polling LP OSCILLATOR the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. C1 PIC18FXXXX 27 pF 13.3.2 LOW-POWER TIMER1 OPTION T1OSI The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. XTAL 32.768 kHz When the LPT1OSC Configuration bit is set, the Timer1 oscillator operates in a low-power mode. When T1OSO LPT1OSC is not set, Timer1 operates at a higher power C2 level. Power consumption for a particular mode is 27 pF relatively constant, regardless of the device’s operating mode. The default Timer1 configuration is the higher Note: See the Notes with Table13-1 for additional power mode. information about capacitor selection. As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. © 2009 Microchip Technology Inc. DS39689F-page 135

PIC18F2221/2321/4221/4321 FAMILY 13.3.3 TIMER1 OSCILLATOR LAYOUT 13.5 Resetting Timer1 Using the CCP CONSIDERATIONS Special Event Trigger The Timer1 oscillator circuit draws very little power If either of the CCP modules is configured to use during operation. Due to the low-power nature of the Timer1 and generate a Special Event Trigger in Com- oscillator, it may also be sensitive to rapidly changing pare mode (CCP1M<3:0> or CCP2M<3:0>=1011), signals in close proximity. this signal will reset Timer1. The trigger from CCP2 will The oscillator circuit, shown in Figure13-3, should be also start an A/D conversion if the A/D module is located as close as possible to the microcontroller. enabled (see Section16.3.4 “Special Event Trigger” There should be no circuits passing within the oscillator for more information). circuit boundaries other than VSS or VDD. The module must be configured as either a timer or a If a high-speed circuit must be located near the synchronous counter to take advantage of this feature. oscillator (such as the CCP1 pin in Output Compare or When used this way, the CCPRH:CCPRL register pair PWM mode, or the primary oscillator using the OSC2 effectively becomes a period register for Timer1. pin), a grounded guard ring around the oscillator circuit, If Timer1 is running in Asynchronous Counter mode, as shown in Figure13-4, may be helpful when used on this Reset operation may not work. a single-sided PCB or in addition to a ground plane. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take FIGURE 13-4: OSCILLATOR CIRCUIT precedence. WITH GROUNDED GUARD RING Note: The Special Event Triggers from the CCP2 module will not set the TMR1IF VDD interrupt flag bit (PIR1<0>). VSS 13.6 Using Timer1 as a Real-Time Clock OSC1 Adding an external LP oscillator to Timer1 (such as the OSC2 one described in Section13.3 “Timer1 Oscillator”) gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time RC0 base and several lines of application code to calculate the time. When operating in Sleep mode and using a RC1 battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. RC2 The application code routine, RTCisr, shown in Note: Not drawn to scale. Example13-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 13.4 Timer1 Interrupt register pair to overflow, triggers the interrupt and calls The TMR1 register pair (TMR1H:TMR1L) increments the routine, which increments the seconds counter by from 0000h to FFFFh and rolls over to 0000h. The one. Additional counters for minutes and hours are Timer1 interrupt, if enabled, is generated on overflow incremented as the previous counter overflow. which is latched in interrupt flag bit, TMR1IF Since the register pair is 16 bits wide, counting up to (PIR1<0>). This interrupt can be enabled or disabled overflow the register directly from a 32.768kHz clock by setting or clearing the Timer1 Interrupt Enable bit, would take 2 seconds. To force the overflow at the TMR1IE (PIE1<0>). required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered. Doing so may introduce cumulative errors over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. DS39689F-page 136 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b'00001111' ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TMR1L Timer1 Register Low Byte 56 TMR1H Timer1 Register High Byte 56 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56 Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 137

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 138 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 timer module incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by- • 8-bit timer and period registers (TMR2 and PR2, 16 prescale options. These are selected by the prescaler respectively) control bits, T2CKPS<1:0> (T2CON<1:0>). The value of • Readable and writable (both registers) TMR2 is compared to that of the Period register, PR2, on • Software programmable prescaler (1:1, 1:4 and each clock cycle. When the two values match, the com- 1:16) parator generates a match signal as the timer output. • Software programmable postscaler (1:1 through This signal also resets the value of TMR2 to 00h on the 1:16) next cycle and drives the output counter/postscaler (see • Interrupt on TMR2 to PR2 match Section14.2 “Timer2 Interrupt”). • Optional use as the shift clock for the MSSP The TMR2 and PR2 registers are both directly readable module and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. The module is controlled through the T2CON register Both the prescaler and postscaler counters are cleared (Register14-1), which enables or disables the timer on the following events: and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON • a write to the TMR2 register (T2CON<2>), to minimize power consumption. • a write to the T2CON register A simplified block diagram of the module is shown in • any device Reset (Power-on Reset, MCLR Reset, Figure14-1. Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 139

PIC18F2221/2321/4221/4321 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) the CCP modules, where it is used as a time base for provides the input for the 4-bit output counter/post- operations in PWM mode. scaler. This counter generates the TMR2 match inter- Timer2 can be optionally used as the shift clock source rupt flag which is latched in TMR2IF (PIR1<1>). The for the MSSP module operating in SPI mode. interrupt is enabled by setting the TMR2 Match Inter- Additional information is provided in Section18.0 rupt Enable bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TMR2 Timer2 Register 56 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 56 PR2 Timer2 Period Register 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. DS39689F-page 140 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. A block diagram of the module’s The Timer3 timer/counter module incorporates these operation in Read/Write mode is shown in Figure15-2. features: The Timer3 module is controlled through the T3CON • Software selectable operation as a 16-bit timer or register (Register15-1). It also selects the clock source counter options for the CCP modules (see Section16.1.1 • Readable and writable 8-bit registers (TMR3H “CCP Modules and Timer Resources” for more and TMR3L) information). • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits 1x = Timer3 is the capture/compare clock source for the CCP modules 01 = Timer3 is the capture/compare clock source for CCP2; Timer1 is the capture/compare clock source for CCP1 00 = Timer1 is the capture/compare clock source for the CCP modules bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 141

PIC18F2221/2321/4221/4321 FAMILY 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared Timer3 can operate in one of three modes: (= 0), Timer3 increments on every internal instruction • Timer cycle (FOSC/4). When the bit is set, Timer3 increments • Synchronous Counter on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. • Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 15-1: TIMER3 BLOCK DIAGRAM (8-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS<1:0> T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T13CKI/T1OSO 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS<1:0> On/Off T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39689F-page 142 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure15-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>). from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or Timer3 into the Timer3 High Byte Buffer register. This clearing the Timer3 Interrupt Enable bit, TMR3IE provides the user with the ability to accurately read all (PIE2<1>). 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low 15.5 Resetting Timer3 Using the CCP byte, has become invalid due to a rollover between Special Event Trigger reads. If either of the CCP modules is configured to use Timer3 A write to the high byte of Timer3 must also take place and to generate a Special Event Trigger in Compare through the TMR3H Buffer register. The Timer3 high mode (CCP1M<3:0> or CCP2M<3:0>=1011), this byte is updated with the contents of TMR3H when a signal will reset Timer3. It will also start an A/D conver- write occurs to TMR3L. This allows a user to write all sion if the A/D module is enabled (see Section16.3.4 16 bits to both the high and low bytes of Timer3 at once. “Special Event Trigger” for more information). The high byte of Timer3 is not directly readable or The module must be configured as either a timer or writable in this mode. All reads and writes must take synchronous counter to take advantage of this feature. place through the Timer3 High Byte Buffer register. When used this way, the CCPR2H:CCPR2L register Writes to TMR3H do not clear the Timer3 prescaler. pair effectively becomes a period register for Timer3. The prescaler is only cleared on writes to TMR3L. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source In the event that a write to Timer3 coincides with a Special Event Trigger from a CCP module, the write will The Timer1 internal oscillator may be used as the clock take precedence. source for Timer3. The Timer1 oscillator is enabled by Note: The Special Event Triggers from the setting the T1OSCEN (T1CON<3>) bit. To use it as the CCP2 module will not set the TMR3IF Timer3 clock source, the TMR3CS bit must also be set. interrupt flag bit (PIR2<1>). As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section13.0 “Timer1 Module”. TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 TMR3L Timer3 Register Low Byte 57 TMR3H Timer3 Register High Byte 57 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. DS39689F-page 143

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 144 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 16.0 CAPTURE/COMPARE/PWM The Capture and Compare operations described in this (CCP) MODULES chapter apply to all standard and Enhanced CCP modules. PIC18F2221/2321/4221/4321 family devices all have Note: Throughout this section and Section17.0 two CCP (Capture/Compare/PWM) modules. Each “Enhanced Capture/Compare/PWM (ECCP) module contains a 16-bit register which can operate as Module”, references to the register and bit a 16-bit Capture register, a 16-bit Compare register or names for CCP modules are referred to a PWM Master/Slave Duty Cycle register. generically by the use of ‘x’ or ‘y’ in place In 28-pin devices, the two standard CCP modules of the specific module number. Thus, (CCP1 and CCP2) operate as described in this “CCPxCON” might refer to the control regis- chapter. In 40/44-pin devices, CCP1 is implemented ter for CCP1, CCP2 or ECCP1. “CCPxCON” as an Enhanced CCP module with standard Capture is used throughout these sections to refer to and Compare modes and Enhanced PWM modes. the module control register, regardless of The ECCP implementation is discussed in whether the CCP module is a standard or Section17.0 “Enhanced Capture/Compare/PWM Enhanced implementation. (ECCP) Module”. REGISTER 16-1: CCPxCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCP pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 145

PIC18F2221/2321/4221/4321 FAMILY 16.1 CCP Module Configuration The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the Each Capture/Compare/PWM module is associated T3CON register (Register15-1). Both modules may be with a control register (generically, CCPxCON) and a active at any given time and may share the same timer data register (CCPRx). The data register, in turn, is resource if they are configured to operate in the same comprised of two 8-bit registers: CCPRxL (low byte) mode (Capture/Compare or PWM) at the same time. The and CCPRxH (high byte). All registers are both interactions between the two modules are summarized in readable and writable. Figure16-1 and Figure16-2. In Timer1 in Asynchronous Counter mode, the capture operation will not work. 16.1.1 CCP MODULES AND TIMER RESOURCES 16.1.2 CCP2 PIN ASSIGNMENT The CCP modules utilize Timers 1, 2 or 3, depending The pin assignment for CCP2 (Capture input, Compare on the mode selected. Timer1 and Timer3 are available and PWM output) can change, based on device config- to modules in Capture or Compare modes, while uration. The CCP2MX Configuration bit determines Timer2 is available for modules in PWM mode. which pin CCP2 is multiplexed to. By default, it is assigned to RC1 (CCP2MX = 1). If the Configuration bit TABLE 16-1: CCP MODE – TIMER is cleared, CCP2 is multiplexed with RB3. RESOURCES Changing the pin assignment of CCP2 does not CCP/ECCP Mode Timer Resource automatically change any requirements for configuring the port pin. Users must always verify that the appropri- Capture Timer1 or Timer3 ate TRIS register is configured correctly for CCP2 Compare Timer1 or Timer3 operation, regardless of where it is located. PWM Timer2 TABLE 16-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different for each CCP. Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on trigger event can also be done. Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Operation of CCP2 could be affected if it is using the same timer as a time base. Compare Compare Either module can be configured for the Special Event Trigger to reset the time base. Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if both modules are using the same time base. Capture PWM(1) None Compare PWM(1) None PWM(1) Capture None PWM(1) Compare None PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). Note 1: Includes standard and Enhanced PWM operation. DS39689F-page 146 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 16.2 Capture Mode 16.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPRxH:CCPRxL register pair When the Capture mode is changed, a false capture captures the 16-bit value of the TMR1 or TMR3 interrupt may be generated. The user should keep the registers when an event occurs on the corresponding CCPxIE interrupt enable bit clear to avoid false CCPx pin. An event is defined as one of the following: interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. • every falling edge • every rising edge 16.2.4 CCP PRESCALER • every 4th rising edge There are four prescaler settings in Capture mode. • every 16th rising edge They are specified as part of the operating mode The event is selected by the mode select bits, selected by the mode select bits (CCPxM<3:0>). Whenever the CCP module is turned off or Capture CCPxM<3:0> (CCPxCON<3:0>). When a capture is mode is disabled, the prescaler counter is cleared. This made, the interrupt request flag bit, CCPxIF, is set; it means that any Reset will clear the prescaler counter. must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old Switching from one capture prescaler to another may captured value is overwritten by the new captured value. generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from 16.2.1 CCP PIN CONFIGURATION a non-zero prescaler. Example16-1 shows the In Capture mode, the appropriate CCPx pin should be recommended method for switching between capture configured as an input by setting the corresponding prescalers. This example also clears the prescaler TRIS direction bit. counter and will not generate the “false” interrupt. Note: If RB3/CCP2 or RC1/CCP2 is configured EXAMPLE 16-1: CHANGING BETWEEN as an output, a write to the port can cause CAPTURE PRESCALERS a capture condition. (CCP2 SHOWN) 16.2.2 TIMER1/TIMER3 MODE SELECTION CLRF CCP2CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the The timers that are to be used with the capture feature ; new prescaler mode (Timer1 and/or Timer3) must be running in Timer mode or ; value and CCP ON Synchronized Counter mode. In Asynchronous Counter MOVWF CCP2CON ; Load CCP2CON with mode, the capture operation will not work. The timer to be ; this value used with each CCP module is selected in the T3CON register (see Section16.1.1 “CCP Modules and Timer Resources”). FIGURE 16-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF T3CCP2 TMR3 Enable CCP1 pin Prescaler and CCPR1H CCPR1L ÷ 1, 4, 16 Edge Detect TMR1 T3CCP2 Enable 4 TMR1H TMR1L CCP1CON<3:0> Set CCP2IF 4 Q1:Q4 4 CCP2CON<3:0> T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Enable CCP2 pin Prescaler and CCPR2H CCPR2L ÷ 1, 4, 16 Edge Detect TMR1 Enable T3CCP2 TMR1H TMR1L T3CCP1 © 2009 Microchip Technology Inc. DS39689F-page 147

PIC18F2221/2321/4221/4321 FAMILY 16.3 Compare Mode 16.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is Timer1 and/or Timer3 must be running in Timer mode constantly compared against either the TMR1 or TMR3 or Synchronized Counter mode if the CCP module is register pair value. When a match occurs, the CCPx pin using the compare feature. In Asynchronous Counter can be: mode, the compare operation may not work. • driven high 16.3.3 SOFTWARE INTERRUPT MODE • driven low When the Generate Software Interrupt mode is chosen • toggled (high-to-low or low-to-high) (CCPxM<3:0> = 1010), the corresponding CCPx pin is • remain unchanged (that is, reflects the state of the not affected. Only a CCP interrupt is generated, if I/O latch) enabled and the CCPxIE bit is set. The action on the pin is based on the value of the mode 16.3.4 SPECIAL EVENT TRIGGER select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. Both CCP modules are equipped with a Special Event Trigger. This is an internal hardware signal generated 16.3.1 CCP PIN CONFIGURATION in Compare mode to trigger actions by other modules. The user must configure the CCPx pin as an output by The Special Event Trigger is enabled by selecting clearing the appropriate TRIS bit. the Compare Special Event Trigger mode (CCPxM<3:0> = 1011). Note: Clearing the CCP2CON register will force For either CCP module, the Special Event Trigger resets the RB3 or RC1 compare output latch the Timer register pair for whichever timer resource is (depending on device configuration) to the currently assigned as the module’s time base. This default low level. This is not the PORTB or allows the CCPRx registers to serve as a programmable PORTC I/O data latch. period register for either timer. The Special Event Trigger for CCP2 can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. FIGURE 16-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set CCP1IF (Timer1/Timer3 Reset) CCPR1H CCPR1L CCP1 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP1CON<3:0> TMR1H TMR1L 0 0 1 TMR3H TMR3L 1 Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) T3CCP1 T3CCP2 Set CCP2IF CCP2 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR2H CCPR2L CCP2CON<3:0> DS39689F-page 148 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 RCON IPEN SBOREN(1) — RI TO PD POR BOR 54 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 TRISB PORTB Data Direction Register 58 TRISC PORTC Data Direction Register 58 TMR1L Timer1 Register Low Byte 56 TMR1H Timer1 Register High Byte 56 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56 TMR3H Timer3 Register High Byte 57 TMR3L Timer3 Register Low Byte 57 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 57 CCPR1L Capture/Compare/PWM Register 1 Low Byte 57 CCPR1H Capture/Compare/PWM Register 1 High Byte 57 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 57 CCPR2L Capture/Compare/PWM Register 2 Low Byte 57 CCPR2H Capture/Compare/PWM Register 2 High Byte 57 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 149

PIC18F2221/2321/4221/4321 FAMILY 16.4 PWM Mode 16.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP2 pin is multiplexed with a PORTB or PORTC following formula: data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. EQUATION 16-1: Note: Clearing the CCP2CON register will force PWM Period = [(PR2) + 1] • 4 • TOSC • the RB3 or RC1 output latch (depending on (TMR2 Prescale Value) device configuration) to the default low level. This is not the PORTB or PORTC I/O PWM frequency is defined as 1/[PWM period]. data latch. When TMR2 is equal to PR2, the following three events Figure16-3 shows a simplified block diagram of the occur on the next increment cycle: CCP module in PWM mode. • TMR2 is cleared For a step-by-step procedure on how to set up the CCP • The CCPx pin is set (exception: if PWM duty module for PWM operation, see Section16.4.4 cycle=0%, the CCPx pin will not be set) “Setup for PWM Operation”. • The PWM duty cycle is latched from CCPRxL into CCPRxH FIGURE 16-3: SIMPLIFIED PWM BLOCK Note: The Timer2 postscalers (see Section14.0 DIAGRAM “Timer2 Module”) are not used in the CCPxCON<5:4> determination of the PWM frequency. The Duty Cycle Registers postscaler could be used to have a servo CCPRxL update rate at a different frequency than the PWM output. 16.4.2 PWM DUTY CYCLE CCPRxH (Slave) CCPx Output The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up Comparator R Q to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contains the TMR2 (Note 1) two LSbs. This 10-bit value is represented by S CCPRxL:CCPxCON<5:4>. The following equation is used to calculate the PWM duty cycle in time: Comparator Corresponding Clear Timer, TRIS bit CCPx pin and EQUATION 16-2: latch D.C. PR2 PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • Note1: The 8-bit TMR2 value is concatenated with the 2-bit TOSC • (TMR2 Prescale Value) internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. CCPRxL and CCPxCON<5:4> can be written to at any A PWM output (Figure16-4) has a time base (period) time, but the duty cycle value is not latched into and a time that the output stays high (duty cycle). CCPRxH until after a match between PR2 and TMR2 The frequency of the PWM is the inverse of the occurs (i.e., the period is complete). In PWM mode, period (1/period). CCPRxH is a read-only register. FIGURE 16-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS39689F-page 150 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY The CCPRxH register and a 2-bit internal latch are EQUATION 16-3: used to double-buffer the PWM duty cycle. This ⎛FOSC⎞ double-buffering is essential for glitchless PWM log⎝F----P---W-----M---⎠ operation. PWM Resolution (max) = -----------------------------bits log(2) When the CCPRxH and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCPx pin is cleared. Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be The maximum PWM resolution (bits) for a given PWM cleared. frequency is given by the equation: TABLE 16-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 16.4.3 PWM AUTO-SHUTDOWN 16.4.4 SETUP FOR PWM OPERATION (CCP1 ONLY) The following steps should be taken when configuring The PWM auto-shutdown features of the Enhanced CCP the CCP module for PWM operation: module are also available to CCP1 in 28-pin devices. The 1. Set the PWM period by writing to the PR2 operation of this feature is discussed in detail in register. Section17.4.7 “Enhanced PWM Auto-Shutdown”. 2. Set the PWM duty cycle by writing to the Auto-shutdown features are not available for CCP2. CCPRxL register and CCPxCON<5:4> bits. 3. Make the CCPx pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. 5. Configure the CCPx module for PWM operation. © 2009 Microchip Technology Inc. DS39689F-page 151

PIC18F2221/2321/4221/4321 FAMILY TABLE 16-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 RCON IPEN SBOREN(1) — RI TO PD POR BOR 54 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TRISB PORTB Data Direction Register 58 TRISC PORTC Data Direction Register 58 TMR2 Timer2 Register 56 PR2 Timer2 Period Register 56 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 56 CCPR1L Capture/Compare/PWM Register 1 Low Byte 57 CCPR1H Capture/Compare/PWM Register 1 High Byte 57 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 57 CCPR2L Capture/Compare/PWM Register 2 Low Byte 57 CCPR2H Capture/Compare/PWM Register 2 High Byte 57 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 57 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 57 ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These bits are unimplemented on 28-pin devices and read as ‘0’. DS39689F-page 152 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 17.0 ENHANCED CAPTURE/ Enhanced features are discussed in detail in COMPARE/PWM (ECCP) Section17.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of the MODULE ECCP module are the same as described for the standard CCP module. Note: The ECCP module is implemented only in 40/44-pin devices. The control register for the Enhanced CCP module is shown in Register17-1. It differs from the CCPxCON In PIC18F4221/4321 devices, CCP1 is implemented registers in PIC18F2221/2321 devices in that the two as a standard CCP module with Enhanced PWM Most Significant bits are implemented to control PWM capabilities. These include the provision for 2 or functionality. 4output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The REGISTER 17-1: CCP1CON REGISTER (ECCP1 MODULE, 40/44-PIN DEVICES) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M<3:0>: Enhanced CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Capture mode 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF) 1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF) 1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 153

PIC18F2221/2321/4221/4321 FAMILY In addition to the expanded range of modes available 17.2 Capture and Compare Modes through the CCP1CON and ECCP1AS registers, the ECCP module has an additional register associated Except for the operation of the Special Event Trigger with Enhanced PWM operation and auto-shutdown discussed below, the Capture and Compare modes of features; it is: the ECCP module are identical in operation to that of CCP2. These are discussed in detail in Section16.2 • ECCP1DEL (PWM Dead-Band Delay) “Capture Mode” and Section16.3 “Compare Mode”. No changes are required when moving 17.1 ECCP Outputs and Configuration between 28-pin and 40/44-pin devices. The Enhanced CCP module may have up to four PWM 17.2.1 SPECIAL EVENT TRIGGER outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are The Special Event Trigger output of ECCP1 resets the multiplexed with I/O pins on PORTC and PORTD. The TMR1 or TMR3 register pair, depending on which timer outputs that are active depend on the CCP operating resource is currently selected. This allows the CCPR1 mode selected. The pin assignments are summarized register to effectively be a 16-bit programmable period in Table17-1. register for Timer1 or Timer3. To configure the I/O pins as PWM outputs, the proper 17.3 Standard PWM Mode PWM mode must be selected by setting the P1M<1:0> and CCP1M<3:0> bits. The appropriate TRISC and When configured in Single Output mode, the ECCP TRISD direction bits for the port pins must also be set module functions identically to the standard CCP as outputs. module in PWM mode, as described in Section16.4 “PWM Mode”. This is also sometimes referred to as 17.1.1 ECCP MODULES AND TIMER “Compatible CCP” mode, as in Table17-1. RESOURCES Note: When setting up single output PWM Like the standard CCP modules, the ECCP module can operations, users are free to use either utilize Timers 1, 2 or 3, depending on the mode of the processes described in selected. Timer1 and Timer3 are available for modules Section 16.4.4 “Setup for PWM in Capture or Compare modes, while Timer2 is avail- Operation” or Section17.4.9 “Setup able for modules in PWM mode. Interactions between for PWM Operation”. The latter is more the standard and Enhanced CCP modules are identical generic and will work for either single or to those described for standard CCP modules. multi-output PWM. Additional details on timer resources are provided in Section16.1.1 “CCP Modules and Timer Resources”. TABLE 17-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES CCP1CON ECCP Mode RC2 RD5 RD6 RD7 Configuration All 40/44-pin devices: Compatible CCP 00xx 11xx CCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7 Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. DS39689F-page 154 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 17.4 Enhanced PWM Mode 17.4.1 PWM PERIOD The Enhanced PWM mode provides additional PWM The PWM period is specified by writing to the PR2 output options for a broader range of control applica- register. The PWM period can be calculated using the tions. The module is a backward compatible version of following equation. the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to EQUATION 17-1: select the polarity of the signal (either active-high or PWM Period = [(PR2) + 1] • 4 • TOSC • active-low). The module’s output mode and polarity are (TMR2 Prescale Value) configured by setting the P1M<1:0> and CCP1M<3:0> bits of the CCP1CON register. PWM frequency is defined as 1/[PWM period]. When Figure17-1 shows a simplified block diagram of PWM TMR2 is equal to PR2, the following three events occur operation. All control registers are double-buffered and on the next increment cycle: are loaded at the beginning of a new PWM cycle (the • TMR2 is cleared period boundary when Timer2 resets) in order to • The CCP1 pin is set (if PWM duty cycle=0%, the prevent glitches on any of the outputs. The exception is CCP1 pin will not be set) the PWM Dead-Band Delay register, ECCP1DEL, • The PWM duty cycle is copied from CCPR1L into which is loaded at either the duty cycle boundary or the CCPR1H period boundary (whichever comes first). Because of the buffering, the module waits until the assigned timer Note: The Timer2 postscaler (see Section14.0 resets, instead of starting immediately. This means that “Timer2 Module”) is not used in the Enhanced PWM waveforms do not exactly match the determination of the PWM frequency. The standard PWM waveforms, but are instead offset by postscaler could be used to have a servo one full instruction cycle (4 TOSC). update rate at a different frequency than As before, the user must manually configure the the PWM output. appropriate TRIS bits for output. FIGURE 17-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRISx<x> CCPR1H (Slave) P1B P1B Output TRISx<x> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISx<x> P1D P1D Comparator Clear Timer, TRISx<x> set CCP1 pin and latch D.C. PR2 ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. DS39689F-page 155

PIC18F2221/2321/4221/4321 FAMILY 17.4.2 PWM DUTY CYCLE EQUATION 17-3: The PWM duty cycle is specified by writing to the log(FOSC) CCPR1L register and to the CCP1CON<5:4> bits. Up FPWM PWM Resolution (max) = bits to 10-bit resolution is available. The CCPR1L contains log(2) the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is Note: If the PWM duty cycle value is longer than calculated by the following equation. the PWM period, the CCP1 pin will not be cleared. EQUATION 17-2: PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • 17.4.3 PWM OUTPUT CONFIGURATIONS TOSC • (TMR2 Prescale Value) The P1M<1:0> bits in the CCP1CON register allow one of four configurations: CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into • Single Output CCPR1H until a match between PR2 and TMR2 occurs • Half-Bridge Output (i.e., the period is complete). In PWM mode, CCPR1H • Full-Bridge Output, Forward mode is a read-only register. • Full-Bridge Output, Reverse mode The CCPR1H register and a 2-bit internal latch are The Single Output mode is the standard PWM mode used to double-buffer the PWM duty cycle. This discussed in Section17.4 “Enhanced PWM Mode”. double-buffering is essential for glitchless PWM The Half-Bridge and Full-Bridge Output modes are operation. When the CCPR1H and 2-bit latch match covered in detail in the sections that follow. TMR2, concatenated with an internal 2-bit Q clock or The general relationship of the outputs in all two bits of the TMR2 prescaler, the CCP1 pin is configurations is summarized in Figure17-2. cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. TABLE 17-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39689F-page 156 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 17-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 PR2 + 1 CCP1CON SIGNAL Duty <7:6> Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive FIGURE 17-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 PR2 + 1 CCP1CON SIGNAL Duty <7:6> Cycle Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section17.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. DS39689F-page 157

PIC18F2221/2321/4221/4321 FAMILY 17.4.4 HALF-BRIDGE MODE FIGURE 17-4: HALF-BRIDGE PWM OUTPUT In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal Period Period is output on the P1A pin, while the complementary PWM Duty Cycle output signal is output on the P1B pin (Figure17-4). This mode can be used for half-bridge applications, as shown P1A(2) in Figure17-5, or for full-bridge applications where four td power switches are being modulated with two PWM td signals. P1B(2) In Half-Bridge Output mode, the programmable dead- band delay can be used to prevent shoot-through (1) (1) (1) current in half-bridge power devices. The value of bits, PDC<6:0>, sets the number of instruction cycles before td = Dead-Band Delay the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section17.4.6 PR2 register. “Programmable Dead-Band Delay” for more details 2: Output signals are shown as active-high. of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTD<5> data latches, the TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 17-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) V+ PIC18F4X21 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F4X21 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS39689F-page 158 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 17.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The In Full-Bridge Output mode, four pins are used as TRISC<2> and TRISD<7:5> bits must be cleared to outputs; however, only two outputs are active at a time. make the P1A, P1B, P1C and P1D pins outputs. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure17-6. FIGURE 17-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. DS39689F-page 159

PIC18F2221/2321/4221/4321 FAMILY FIGURE 17-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F4X21 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 17.4.5.1 Direction Change in Full-Bridge Mode Figure17-9 shows an example where the PWM direction changes from forward to reverse at a near In the Full-Bridge Output mode, the P1M1 bit in the 100% duty cycle. At time t1, the outputs P1A and P1D CCP1CON register allows user to control the forward/ become inactive, while output P1C becomes active. In reverse direction. When the application firmware this example, since the turn-off time of the power changes this direction control bit, the module will devices is longer than the turn-on time, a shoot-through assume the new direction on the next PWM cycle. current may flow through power devices, QC and QD Just before the end of the current PWM period, the (see Figure17-7), for the duration of ‘t’. The same modulated outputs (P1B and P1D) are placed in their phenomenon will occur to power devices, QA and QB, inactive state, while the unmodulated outputs (P1A and for PWM direction change from reverse to forward. P1C) are switched to drive in the opposite direction. If changing PWM direction at high duty cycle is required This occurs in a time interval of 4TOSC * (Timer2 for an application, one of the following requirements Prescale Value) before the next PWM period begins. must be met: The Timer2 prescaler will be either 1, 4 or 16, depend- ing on the value of the T2CKPS<1:0> bits 1. Reduce PWM for a PWM period before (T2CON<1:0>). During the interval from the switch of changing directions. the unmodulated outputs to the beginning of the next 2. Use switch drivers that can drive the switches off period, the modulated outputs (P1B and P1D) remain faster than they can drive them on. inactive. This relationship is shown in Figure17-8. Other options to prevent shoot-through current may Note that in the Full-Bridge Output mode, the ECCP1 exist. module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39689F-page 160 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 17-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 17-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC t (2) ON External Switch C(1) t (3) OFF External Switch D(1) Potential t = t – t (2,3) OFF ON Shoot-Through Current(1) Note1: All signals are shown as active-high. 2: t is the turn-on delay of power switch QC and its driver. ON 3: t is the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. DS39689F-page 161

PIC18F2221/2321/4221/4321 FAMILY 17.4.6 PROGRAMMABLE DEAD-BAND A shutdown event can be caused by either of the DELAY comparator modules, a low level on the Fault input pin (FLT0) or any combination of these three sources. The Note: Programmable dead-band delay is not comparators may be used to monitor a voltage input implemented in 28-pin devices with proportional to a current being monitored in the bridge standard CCP modules. circuit. If the voltage exceeds a threshold, the In half-bridge applications, where all power switches comparator switches state and triggers a shutdown. are modulated at the PWM frequency at all times, the Alternatively, a low digital signal on FLT0 can also trigger power switches normally require more time to turn off a shutdown. The auto-shutdown feature can be disabled than to turn on. If both the upper and lower power by not selecting any auto-shutdown sources. The auto- switches are switched at the same time (one turned on shutdown sources to be used are selected using the and the other turned off), both switches may be on for ECCPAS<2:0> bits (ECCP1AS<6:4>). a short period of time until one switch completely turns When a shutdown occurs, the output pins are asyn- off. During this brief interval, a very high current (shoot- chronously placed in their shutdown states, specified through current) may flow through both power by the PSSAC<1:0> and PSSBD<1:0> bits switches, shorting the bridge supply. To avoid this (ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/ potentially destructive shoot-through current from P1D) may be set to drive high, drive low or be tri-stated flowing during switching, turning on either of the power (not driving). The ECCPASE bit (ECCP1AS<7>) is also switches is normally delayed to allow the other switch set to hold the Enhanced PWM outputs in their to completely turn off. shutdown states. In the Half-Bridge Output mode, a digitally programmable The ECCPASE bit is set by hardware when a shutdown dead-band delay is available to avoid shoot-through event occurs. If automatic restarts are not enabled, the current from destroying the bridge power switches. The ECCPASE bit is cleared by firmware when the cause of delay occurs at the signal transition from the nonactive the shutdown clears. If automatic restarts are enabled, state to the active state (see Figure17-4 for illustra- the ECCPASE bit is automatically cleared when the tion). Bits PDC<6:0> of the ECCP1DEL register cause of the auto-shutdown has cleared. (Register17-2) set the delay period in terms of micro- If the ECCPASE bit is set when a PWM period begins, controller instruction cycles (TCY or 4 TOSC). These bits the PWM outputs remain in their shutdown state for that are not available on 28-pin devices as the standard entire PWM period. When the ECCPASE bit is cleared, CCP module does not support half-bridge operation. the PWM outputs will return to normal operation at the 17.4.7 ENHANCED PWM AUTO-SHUTDOWN beginning of the next PWM period. When the ECCP1 is programmed for any of the Note: Writing to the ECCPASE bit is disabled Enhanced PWM modes, the active output pins may be while a shutdown condition is active. configured for auto-shutdown. Auto-shutdown immedi- ately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. REGISTER 17-2: ECCP1DEL: PWM DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) bit 7 bit 0 bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits(1) Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Note1: Unimplemented on 28-pin devices; bits read ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 162 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 17-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) bit 7 bit 0 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits 111 = FLT0 or Comparator 1 or Comparator 2 110 = FLT0 or Comparator 2 101 = FLT0 or Comparator 1 100 = FLT0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled bit 3-2 PSSAC<1:0>: Pins A and C Shutdown State Control bits 1x =Pins A and C are tri-state (40/44-pin devices); PWM output is tri-state (28-pin devices) 01 =Drive Pins A and C to ‘1’ 00 =Drive Pins A and C to ‘0’ bit 1-0 PSSBD<1:0>: Pins B and D Shutdown State Control bits(1) 1x =Pins B and D tri-state 01 =Drive Pins B and D to ‘1’ 00 =Drive Pins B and D to ‘0’ Note1: Unimplemented on 28-pin devices; bits read as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 163

PIC18F2221/2321/4221/4321 FAMILY 17.4.7.1 Auto-Shutdown and 17.4.8 START-UP CONSIDERATIONS Automatic Restart When the ECCP module is used in the PWM mode, the The auto-shutdown feature can be configured to allow application hardware must use the proper external pull- automatic restarts of the module following a shutdown up and/or pull-down resistors on the PWM output pins. event. This is enabled by setting the PRSEN bit of the When the microcontroller is released from Reset, all of ECCP1DEL register (ECCP1DEL<7>). the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in In Shutdown mode with PRSEN = 1 (Figure17-10), the the OFF state until the microcontroller drives the I/O ECCPASE bit will remain set for as long as the cause pins with the proper signal levels, or activates the PWM of the shutdown continues. When the shutdown condi- output(s). tion clears, the ECCP1ASE bit is cleared. If PRSEN =0 (Figure17-11), once a shutdown condition occurs, the The CCP1M<1:0> bits (CCP1CON<1:0>) allow the ECCPASE bit will remain set until it is cleared by user to choose whether the PWM output signals are firmware. Once ECCPASE is cleared, the Enhanced active-high or active-low for each pair of PWM output PWM will resume at the beginning of the next PWM pins (P1A/P1C and P1B/P1D). The PWM output period. polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configura- Note: Writing to the ECCPASE bit is disabled tion while the PWM pins are configured as outputs is while a shutdown condition is active. not recommended, since it may result in damage to the Independent of the PRSEN bit setting, if the auto- application circuits. shutdown source is one of the comparators, the The P1A, P1B, P1C and P1D output latches may not be shutdown condition is a level. The ECCPASE bit in the proper states when the PWM module is initialized. cannot be cleared as long as the cause of the shutdown Enabling the PWM pins for output at the same time as persists. the ECCP module may cause damage to the applica- The Auto-Shutdown mode can be forced by writing a ‘1’ tion circuit. The ECCP module must be enabled in the to the ECCPASE bit. proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The com- pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 17-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) PWM Period PWM Period PWM Period PWM Activity Dead Time Dead Time Dead Time Duty Cycle Duty Cycle Duty Cycle ShutdownEvent ECCPASE bit FIGURE 17-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) PWM Period PWM Period PWM Period PWM Activity Dead Time Dead Time Dead Time Duty Cycle Duty Cycle Duty Cycle ShutdownEvent ECCPASE bit ECCPASE Cleared by Firmware DS39689F-page 164 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 17.4.9 SETUP FOR PWM OPERATION 17.4.10 OPERATION IN POWER-MANAGED MODES The following steps should be taken when configuring the ECCP module for PWM operation: In Sleep mode, all clock sources are disabled. Timer2 1. Configure the PWM pins, P1A and P1B (and will not increment and the state of the module will not P1C and P1D, if used), as inputs by setting the change. If the ECCP pin is driving a value, it will continue corresponding TRIS bits. to drive that value. When the device wakes up, it will 2. Set the PWM period by loading the PR2 register. continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from INTOSC and 3. If auto-shutdown is required, do the following: the postscaler may not be stable immediately. • Disable auto-shutdown (ECCPASE = 0) In PRI_IDLE mode, the primary clock will continue to • Configure source (FLT0, Comparator 1 or clock the ECCP module without change. In all other Comparator 2) power-managed modes, the selected power-managed • Wait for non-shutdown condition mode clock will clock Timer2. Other power-managed 4. Configure the ECCP module for the desired mode clocks will most likely be different than the PWM mode and configuration by loading the primary clock frequency. CCP1CON register with the appropriate values: • Select one of the available output 17.4.10.1 Operation with Fail-Safe configurations and direction with the P1M<1:0 Clock Monitor bits. If the Fail-Safe Clock Monitor is enabled, a clock failure • Select the polarities of the PWM output will force the device into the power-managed RC_RUN signals with the CCP1M<3:0> bits. mode and the OSCFIF bit (PIR2<7>) will be set. The 5. Set the PWM duty cycle by loading the CCPR1L ECCP will then be clocked from the internal oscillator register and CCP1CON<5:4> bits. clock source, which may have a different clock 6. For Half-Bridge Output mode, set the dead- frequency than the primary clock. band delay by loading ECCP1DEL<6:0> with See the previous section for additional details. the appropriate value. 7. If auto-shutdown operation is required, load the 17.4.11 EFFECTS OF A RESET ECCP1AS register: Both Power-on Reset and subsequent Resets will force • Select the auto-shutdown sources using the all ports to Input mode and the CCP registers to their ECCPAS<2:0> bits. Reset states. • Select the shutdown states of the PWM This forces the Enhanced CCP module to reset to a output pins using the PSSAC<1:0> and state compatible with the standard CCP module. PSSBD<1:0> bits. • Set the ECCPASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 8. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). • Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: • Wait until TMRx overflows (TMRxIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. DS39689F-page 165

PIC18F2221/2321/4221/4321 FAMILY TABLE 17-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 RCON IPEN SBOREN(1) — RI TO PD POR BOR 54 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 TRISB PORTB Data Direction Register 58 TRISC PORTC Data Direction Register 58 TRISD(2) PORTD Data Direction Register 58 TMR1L Timer1 Register Low Byte 56 TMR1H Timer1 Register High Byte 56 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56 TMR2 Timer2 Register 56 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 56 PR2 Timer2 Period Register 56 TMR3L Timer3 Register Low Byte 57 TMR3H Timer3 Register High Byte 57 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 57 CCPR1L Capture/Compare/PWM Register 1 Low Byte 57 CCPR1H Capture/Compare/PWM Register 1 High Byte 57 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 57 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 57 ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are unimplemented on 28-pin devices; always maintain these bits clear. DS39689F-page 166 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.0 MASTER SYNCHRONOUS 18.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four SPI modes are supported. To accomplish communication, 18.1 Master SSP (MSSP) Module typically three pins are used: Overview • Serial Data Out (SDO) – SDO • Serial Data In (SDI) – SDI/SDA The Master Synchronous Serial Port (MSSP) module is • Serial Clock (SCK) – SCK/SCL a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave devices may be serial EEPROMs, shift registers, mode of operation: display drivers, A/D converters, etc. The MSSP module • Slave Select (SS) can operate in one of two modes: Figure18-1 shows the block diagram of the MSSP • Serial Peripheral Interface (SPI) module when operating in SPI mode. • Inter-Integrated Circuit (I2C™) - Full Master mode FIGURE 18-1: MSSP BLOCK DIAGRAM - Slave mode (with address masking for both (SPIMODE) 10-bit and 7-bit addressing) Internal The I2C interface supports the following modes in Data Bus hardware: Read Write • Master mode • Multi-Master mode SSPBUF reg • Slave mode SDI/SDA 18.2 Control Registers SSPSR reg The MSSP module has three associated registers. SDO bit 0 Shift Clock These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual Configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. SS SS Control Additional details are provided under the individual Enable sections. Edge Select 2 Clock Select SSPM<3:0> SMP:CKE 4 (T M R 2 O u tp u t) SCK/SCL 2 2 Edge Select Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit © 2009 Microchip Technology Inc. DS39689F-page 167

PIC18F2221/2321/4221/4321 FAMILY 18.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer Register and the SSPIF interrupt is set. (SSPBUF) During transmission, the SSPBUF is not double- • MSSP Shift Register (SSPSR) – Not directly buffered. A write to SSPBUF will write to both SSPBUF accessible and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 18-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C™ mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 168 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 169

PIC18F2221/2321/4221/4321 FAMILY 18.3.2 OPERATION (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following When initializing the SPI, several options need to be write(s) to the SSPBUF register completed successfully. specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). When the application software is expecting to receive These control bits allow the following to be specified: valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The • Master mode (SCK is the clock output) Buffer Full bit, BF (SSPSTAT<0>), indicates when • Slave mode (SCK is the clock input) SSPBUF has been loaded with the received data • Clock Polarity (Idle state of SCK) (transmission is complete). When the SSPBUF is read, • Data Input Sample Phase (middle or end of data the BF bit is cleared. This data may be irrelevant if the output time) SPI is only a transmitter. Generally, the MSSP interrupt • Clock Edge (output data on rising/falling edge is used to determine when the transmission/reception of SCK) has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, • Clock Rate (Master mode only) then software polling can be done to ensure that a write • Slave Select mode (Slave mode only) collision does not occur. Example18-1 shows the The MSSP consists of a transmit/receive shift register loading of the SSPBUF (SSPSR) for data transmission. (SSPSR) and a buffer register (SSPBUF). The SSPSR The SSPSR is not directly readable or writable and can shifts the data in and out of the device, MSb first. The only be accessed by addressing the SSPBUF register. SSPBUF holds the data that was written to the SSPSR Additionally, the MSSP Status register (SSPSTAT) until the received data is ready. Once the 8 bits of data indicates the various status conditions. have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF Note: To avoid lost data in Master mode, a read of (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are the SSPBUF must be performed to clear the set. This double-buffering of the received data Buffer Full (BF) detect bit (SSPSTAT<0>) (SSPBUF) allows the next byte to start reception before between each transmission. reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data Note: The SSPBUF register cannot be used with will be ignored and the write collision detect bit, WCOL read-modify-write instructions, such as BCF, BTFSC and COMF, etc. EXAMPLE 18-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS39689F-page 170 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.3.3 ENABLING SPI I/O Any serial port function that is not desired may be overridden by programming the corresponding data To enable the serial port, MSSP Enable bit, SSPEN direction (TRIS) register to the opposite value. (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the 18.3.4 TYPICAL CONNECTION SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial Figure18-2 shows a typical connection between two port pins. For the pins to behave as the serial port microcontrollers. The master controller (Processor 1) function, some must have their data direction bits (in initiates the data transfer by sending the SCK signal. the TRIS register) appropriately programmed as Data is shifted out of both shift registers on their pro- follows: grammed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to • SDI is automatically controlled by the SPI module the same Clock Polarity (CKP), then both controllers • SDO must have TRISC<5> bit cleared would send and receive data at the same time. • SCK (Master mode) must have TRISC<3> bit Whether the data is meaningful (or dummy data) cleared depends on the application software. This leads to • SCK (Slave mode) must have TRISC<3> bit set three scenarios for data transmission: • SS must have TRISA<5> bit set • Master sends data – Slave sends dummy data • Master sends data – Slave sends data • Master sends dummy data – Slave sends data FIGURE 18-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 © 2009 Microchip Technology Inc. DS39689F-page 171

PIC18F2221/2321/4221/4321 FAMILY 18.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, The master can initiate the data transfer at any time would give waveforms for SPI communication as because it controls the SCK. The master determines shown in Figure18-3, Figure18-5 and Figure18-6, when the slave (Processor 2, Figure18-2) is to where the MSB is transmitted first. In Master mode, the broadcast data by the software protocol. SPI clock rate (bit rate) is user-programmable to be one In Master mode, the data is transmitted/received as of the following: soon as the SSPBUF register is written to. If the SPI • FOSC/4 (or TCY) operation is only going to receive, the SDO output could be disabled (programmed as an input). The • FOSC/16 (or 4 • TCY) SSPSR register will continue to shift in the signal pres- • FOSC/64 (or 16 • TCY) ent on the SDI pin at the programmed clock rate. As • Timer2 output/2 each byte is received, it will be loaded into the SSPBUF This allows a maximum data rate (at 40 MHz) of register as if a normal received byte (interrupts and sta- 10.00Mbps. tus bits appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. Figure18-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 18-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2↓ SSPBUF DS39689F-page 172 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.3.6 SLAVE MODE SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a In Slave mode, the data is transmitted and received as transmitted byte and becomes a floating output. External the external clock pulses appear on SCK. When the pull-up/pull-down resistors may be desirable depending last bit is latched, the SSPIF interrupt flag bit is set. on the application. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock Note 1: When the SPI interface is in Slave mode line can be observed by reading the SCK pin. The Idle with SS pin control enabled state is determined by the CKP bit (SSPCON1<4>). (SSPCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external 2: If the SPI interface is used in Slave mode clock must meet the minimum high and low times as with CKE set, then the SS pin control specified in the electrical specifications. must be enabled. While in Sleep mode, the slave can transmit/receive When the SPI module resets, the bit counter is forced data. When a byte is received, the device will wake-up to ‘0’. This can be done by either forcing the SS pin to from Sleep. a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can 18.3.7 SLAVE SELECT be connected to the SDI pin. When the SPI needs to SYNCHRONIZATION operate as a receiver, the SDO pin can be configured The SS pin allows a Synchronous Slave mode. The SPI as an input. This disables transmissions from the SDO. operation must be in Slave mode with the SS pin control The SDI can always be left as an input (SDI function) enabled (SSPCON1<3:0> = 04h). When the SS pin is since it cannot create a bus conflict. low, transmission and reception are enabled and the FIGURE 18-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2↓ SSPBUF © 2009 Microchip Technology Inc. DS39689F-page 173

PIC18F2221/2321/4221/4321 FAMILY FIGURE 18-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2↓ SSPBUF FIGURE 18-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF DS39689F-page 174 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.3.8 OPERATION IN POWER-MANAGED 18.3.9 EFFECTS OF A RESET MODES A Reset disables the MSSP module and terminates the In SPI Master mode, module clocks may be operating current transfer. at a different speed than when in full power mode. In 18.3.10 BUS MODE COMPATIBILITY the case of Sleep mode, all clocks are halted. Table18-1 shows the compatibility between the In Idle modes, a clock is provided to the peripherals. standard SPI modes and the states of the CKP and That clock should be from the primary clock source, the CKE control bits. secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section3.7 “Clock Sources TABLE 18-1: SPI BUS MODES and Oscillator Switching” for additional information. In most cases, the speed that the master clocks SPI Standard SPI Mode Control Bits State data is not important; however, this should be Terminology CKP CKE evaluated for each system. If MSSP interrupts are enabled, they can wake the 0, 0 0 1 controller from Sleep mode, or one of the Idle modes, 0, 1 0 0 when the master completes sending data. If an exit 1, 0 1 1 from Sleep or Idle mode is not desired, MSSP 1, 1 1 0 interrupts should be disabled. There is also an SMP bit which controls when the data If the Sleep mode is selected, all module clocks are is sampled. halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/ Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. TABLE 18-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 58 TRISC PORTC Data Direction Control Register 58 SSPBUF MSSP Receive Buffer/Transmit Register 56 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 56 SSPSTAT SMP CKE D/A P S R/W UA BF 56 Legend: Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 175

PIC18F2221/2321/4221/4321 FAMILY 18.4 I2C Mode 18.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPSR) – Not directly • Serial clock (SCL) – RC3/SCK/SCL accessible • Serial data (SDA) – RC4/SDI/SDA • MSSP Address Register (SSPADD) The user must configure these pins as inputs or outputs SSPCON1, SSPCON2 and SSPSTAT are the control through the TRISC<4:3> bits. and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and FIGURE 18-7: MSSP BLOCK DIAGRAM writable. The lower 6 bits of the SSPSTAT are read-only. (I2C™ MODE) The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or Internal out. SSPBUF is the buffer register to which data bytes Data Bus are written to or read from. Read Write SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the RC3/SCK/SCL SSPBUF reg MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload Shift value. Clock In receive operations, SSPSR and SSPBUF together SSPSR reg create a double-buffered receiver. When SSPSR RC4/SDI/ MSb LSb SDA receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. Match Detect Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT reg) DS39689F-page 176 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 2 R/W: Read/Write Information bit (I2C™ mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 177

PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C™ conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as inputs. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 178 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT/ ACKEN(1)/ RCEN(1)/ PEN(1)/ RSEN(1)/ SEN(1) ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT/ADMSK5: Acknowledge Data bit In Master Receive mode: 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. In Slave mode: 1 = Address masking of ADD5 enabled 0 = Address masking of ADD5 disabled bit 4 ACKEN/ADMSK4: Acknowledge Sequence Enable bit In Master Receive mode:(1) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle In Slave mode: 1 = Address masking of ADD4 enabled 0 = Address masking of ADD4 disabled bit 3 RCEN/ADMSK3: Receive Enable bit In Master Receive mode:(1) 1 = Enables Receive mode for I2C 0 = Receive Idle In Slave mode: 1 = Address masking of ADD3 enabled 0 = Address masking of ADD3 disabled bit 2 PEN/ADMSK2: Stop Condition Enable bit In Master mode:(1) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle In Slave mode: 1 = Address masking of ADD2 enabled 0 = Address masking of ADD2 disabled bit 1 RSEN/ADMSK1: Repeated Start Condition Enable bit In Master mode:(1) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle In Slave mode (7-Bit Addressing mode): 1 = Address masking of ADD1 enabled 0 = Address masking of ADD1 disabled In Slave mode (10-Bit Addressing mode): 1 = Address masking of ADD1 and ADD0 enabled 0 = Address masking of ADD1 and ADD0 disabled © 2009 Microchip Technology Inc. DS39689F-page 179

PIC18F2221/2321/4221/4321 FAMILY REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) – CONTINUED R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT/ ACKEN(1)/ RCEN(1)/ PEN(1)/ RSEN(1)/ SEN(1) ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 bit 7 bit 0 bit 0 SEN: Start Condition Enable/Stretch Enable bit(1) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 18-6: SSPADD: MSSP ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 bit 7-0 ADD<7:0>: MSSP Address bits Note1: MSSP Address register in I2C Slave mode. MSSP Baud Rate register in I2C Master mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 180 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.2 OPERATION 18.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON1<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C the 8 bits are shifted into the SSPSR register. All incom- ing bits are sampled with the rising edge of the clock operation. Four mode selection bits (SSPCON1<3:0>) allow one of the following I2C modes to be selected: (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The • I2C Master mode clock address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is Idle 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is Selection of any I2C mode with the SSPEN bit set, set (interrupt is generated, if enabled) on the forces the SCL and SDA pins to be open-drain, falling edge of the ninth SCL pulse. provided these pins are programmed to inputs by In 10-Bit Addressing mode, two address bytes need to setting the appropriate TRISC bits. To ensure proper be received by the slave. The five Most Significant bits operation of the module, pull-up resistors must be (MSbs) of the first address byte specify if this is a 10-bit provided externally to the SCL and SDA pins. address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. 18.4.3 SLAVE MODE For a 10-bit address, the first byte would equal ‘11110 In Slave mode, the SCL and SDA pins must be config- A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the ured as inputs (TRISC<4:3> set). The MSSP module address. The sequence of events for 10-bit address is as will override the input state with the output data when follows, with steps 7 through 9 for the slave-transmitter: required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPIF, The I2C Slave mode hardware will always generate an BF and UA (SSPSTAT<1>) are set). interrupt on an address match. Address masking will 2. Update the SSPADD register with second (low) allow the hardware to generate an interrupt for more byte of address (clears bit UA and releases the than one address (up to 31 in 7-Bit Addressing mode SCL line). and up to 63 in 10-Bit Addressing mode). Through the 3. Read the SSPBUF register (clears bit BF) and mode select bits, the user can also choose to interrupt clear flag bit, SSPIF. on Start and Stop bits 4. Receive second (low) byte of address (bits When an address is matched, or the data transfer after SSPIF, BF and UA are set). an address match is received, the hardware auto- 5. Update the SSPADD register with the first (high) matically will generate the Acknowledge (ACK) pulse byte of address. If match releases SCL line, this and load the SSPBUF register with the received value will clear bit UA. currently in the SSPSR register. 6. Read the SSPBUF register (clears bit BF) and Any combination of the following conditions will cause clear flag bit, SSPIF. the MSSP module not to give this ACK pulse: 7. Receive Repeated Start condition. • The Buffer Full bit, BF (SSPSTAT<0>), was set 8. Receive first (high) byte of address (bits SSPIF before the transfer was received. and BF are set). • The overflow bit, SSPOV (SSPCON1<6>), was 9. Read the SSPBUF register (clears bit BF) and set before the transfer was received. clear flag bit, SSPIF. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2009 Microchip Technology Inc. DS39689F-page 181

PIC18F2221/2321/4221/4321 FAMILY 18.4.3.2 Address Masking • 10-Bit Addressing mode Masking an address bit causes that bit to become a Address mask bits, ADMSK<5:2>, mask the “don’t care”. When one address bit is masked, two corresponding address bits in the SSPADD register. In addresses will be Acknowledged and cause an inter- addition, ADMSK<1> simultaneously masks the two rupt. It is possible to mask more than one address bit at LSBs of the address, ADD<1:0>. For any ADMSK bits a time, which makes it possible to Acknowledge up to that are active (ADMSK<n> = 1), the corresponding 31 addresses in 7-Bit Addressing mode and up to address bit is ignored (ADD<n> = x). Also note that 63addresses in 10-Bit Addressing mode (see although in 10-Bit Addressing mode, the upper address Example18-2). bits reuse part of the SSPADD register bits, the address The I2C slave behaves the same way whether address mask bits do not interact with those bits. They only affect the lower address bits. masking is used or not. However, when address mask- ing is used, the I2C slave can Acknowledge multiple Note1: ADMSK<1> masks the two Least addresses and cause interrupts. When this occurs, it is Significant bits of the address. necessary to determine which address caused the 2: The two Most Significant bits of the interrupt by checking the SSPBUF register. address are not affected by address • 7-Bit Addressing mode masking. Address mask bits, ADMSK<5:1>, mask the corre- sponding address bits in the SSPADD register. For any ADMSK bits that are active (ADMSK<n> = 1), the corresponding address bit is ignored (ADD<n> = x). For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an active address mask. EXAMPLE 18-2: ADDRESS MASKING 7-Bit Addressing mode: SSPADD<7:1> = 1010 0000 ADMSK<5:1> = 00 111 Addresses Acknowledged = 0xA0, 0xA2, 0xA4, 0xA6, 0xA8, 0xAA, 0xAC, 0xAE 10-Bit Addressing mode: SSPADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not affected) ADMSK<5:1> = 00 111 Addresses Acknowledged = 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF The upper two bits are not affected by the address masking. DS39689F-page 182 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.3.3 Reception 18.4.3.4 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section18.4.4 “Clock When the address byte overflow condition exists, then Stretching” for more detail). By stretching the clock, the no Acknowledge (ACK) pulse is given. An overflow the master will be unable to assert another clock pulse condition is defined as either bit BF (SSPSTAT<0>) is until the slave is done preparing the transmit data. The set, or bit SSPOV (SSPCON1<6>) is set. transmit data must be loaded into the SSPBUF register An MSSP interrupt is generated for each data transfer which also loads the SSPSR register. Then pin RC3/ byte. Flag bit, SSPIF (PIR1<3>), must be cleared in SCK/SCL should be enabled by setting bit, CKP software. The SSPSTAT register is used to determine (SSPCON1<4>). The eight data bits are shifted out on the status of the byte. the falling edge of the SCL input. This ensures that the If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL SDA signal is valid during the SCL high time will be held low (clock stretch) following each data (Figure18-10). transfer. The clock must be released by setting bit, The ACK pulse from the master-receiver is latched on CKP (SSPCON1<4>). See Section18.4.4 “Clock the rising edge of the ninth SCL input pulse. If the SDA Stretching” for more detail. line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. © 2009 Microchip Technology Inc. DS39689F-page 183

PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D6D5D4 234 Cleared in softwarSSPBUF is read 7 D 1 = 0 ACK 9 W 8 R/ A1 7 2 )0 A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e ot r A6 2 s n e A7 1 >) 0>) ON1<6>) (CKP do SDA SCLS SSPIF (PIR1<3 BF (SSPSTAT< SSPOV (SSPC CKP DS39689F-page 184 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 pt. u D1 7 nterr n i D2 6 e a s u Data D3 5 e d ca Receiving D5D4 34 ared in softwarPBUF is read owledged an D6 2 CleSS Ackn e D7 1 ’).0 X will b K 9 a ‘ X. R/W = 0 AC 8 a ‘’ or 1 5.X.A3. Receiving Address SDAA7A6A5XA3XX SCL1234567S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) CKP(CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can be either x 2:In this example, an address equal to A7.A6.A © 2009 Microchip Technology Inc. DS39689F-page 185

PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING) P R S ACK 9 PIF I S D0 8 m S o Data D1 7 Fr Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S D0 8 m S o 1 Fr D 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft ding CKP is set in software D7 1 SCL held lowwhile CPUresponds to SSPIF Clear by rea K C A 9 1 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g eivin A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < < T 1 A R T DA CL S SPIF (PI F (SSPS KP S S S B C DS39689F-page 186 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 18-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK = 01001 (RECEPTION, 10-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 Clock is held low untilClock is held low untilupdate of SSPADD has update of SSPADD has taken placetaken place Receive First Byte of AddressReceive Second Byte of AddressReceive Data ByteR/W = 0 ACKACKDA11110A9A8A7A6A5XA3A2XXD7D6D5D4D3D1D2 CL1234567891234567891234576S SPIF (PIR1<3>) Cleared in softwareCleared in softwareCleared in software F (SSPSTAT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag SPOV (SSPCON1<6>) A (SSPSTAT<1>) UA is set indicating thatCleared by hardware whenCleared by hardwarethe SSPADD needs to beSSPADD is updated with highwhen SSPADD is updatedupdatedbyte of addresswith low byte of address UA is set indicating thatSSPADD needs to beupdated KP(CKP does not reset to ‘’ when SEN = )00 Note1: = Don’t care (i.e., address bit can be either a ‘’ or a ‘’).x10 2:In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt. 3:Note that the Most Significant bits of the address are not affected by the bit masking. S S S B S U C © 2009 Microchip Technology Inc. DS39689F-page 187

PIC18F2221/2321/4221/4321 FAMILY FIGURE 18-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACK11110A9A8A7A6A5A4A3A2A1 1234567891234567 1<3>) Cleared in softwareCleared in software AT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag PCON1<6>) AT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdated (CKP does not reset to ‘’ when SEN = )00 R T S T SDA SCLS SSPIF (PI BF (SSPS SSPOV (S UA (SSPS KP C DS39689F-page 188 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W=1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/e First Byte of Address 110A9A8 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv 11 12 1<3>) AT<0>) AT<1>) ON1<4>) SDA SCLS SSPIF (PIR BF (SSPST UA (SSPST CKP (SSPC © 2009 Microchip Technology Inc. DS39689F-page 189

PIC18F2221/2321/4221/4321 FAMILY 18.4.4 CLOCK STRETCHING 18.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. 7-Bit Slave Transmit mode implements clock stretch- The SEN bit (SSPCON2<0>) allows clock stretching to ing by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 18.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-Bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure18-10). ninth clock at the end of the ACK sequence if the BF Note1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge of automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be held low. The CKP bit being cleared to ‘0’ will assert cleared and clock stretching will not occur. the SCL line low. The CKP bit must be set in the user’s 2: The CKP bit can be set in software ISR before reception is allowed to continue. By holding regardless of the state of the BF bit. the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. 18.4.4.4 Clock Stretching for 10-Bit Slave This will prevent buffer overruns from occurring (see Transmit Mode Figure18-15). In 10-Bit Slave Transmit mode, clock stretching is Note1: If the user reads the contents of the controlled during the first two address sequences by SSPBUF before the falling edge of the the state of the UA bit, just as it is in 10-Bit Slave ninth clock, thus clearing the BF bit, the Receive mode. The first two addresses are followed CKP bit will not be cleared and clock by a third address sequence which contains the high- stretching will not occur. order bits of the 10-bit address and the R/W bit set to ‘1’. After the third address sequence is performed, the 2: The CKP bit can be set in software UA bit is not set, the module is now configured in regardless of the state of the BF bit. The Transmit mode and clock stretching is controlled by user should be careful to clear the BF bit the BF flag as in 7-Bit Slave Transmit mode (see in the ISR before the next receive Figure18-13). sequence in order to prevent an overflow condition. 18.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39689F-page 190 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.4.5 Clock Synchronization and already asserted the SCL line. The SCL output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This When the CKP bit is cleared, the SCL output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCL (see SCL output low until the SCL output is already Figure18-14). sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 18-14: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX – 1 SCL Master device asserts clock CKP Master device deasserts clock WR SSPCON © 2009 Microchip Technology Inc. DS39689F-page 191

PIC18F2221/2321/4221/4321 FAMILY 2 FIGURE 18-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 >) 6 A7 1 >) 0>) ON1< DA CLS SPIF (PIR1<3 F (SSPSTAT< SPOV (SSPC KP S S S B S C DS39689F-page 192 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 18-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING) w ent. Clock is not held lobecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s D 8 1 D 7 e Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPADD register beforethe falling edge of the ninth clock will haveno effect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of AddressW = 0 A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/ 11110A9A8 12345678 1<3>) Cleared in software AT<0>) SSPBUF is written withcontents of SSPSR PCON1<6>) AT<1>) UA is set indicating thatthe SSPADD needs to beupdated R T S T SDA SCLS SSPIF (PI BF (SSPS SSPOV (S UA (SSPS KP C © 2009 Microchip Technology Inc. DS39689F-page 193

PIC18F2221/2321/4221/4321 FAMILY 18.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit (SSPSTAT<1>) is set. If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the half of the address is not necessary, the UA bit will not General Call Enable bit, GCEN, is enabled be set and the slave will begin receiving data after the (SSPCON2<7> is set). Following a Start bit detect, Acknowledge (Figure18-17). 8bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 18-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS39689F-page 194 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start Master mode of operation is supported by interrupt condition is complete. In this case, the generation on the detection of the Start and Stop SSPBUF will not be written to and the conditions. The Stop (P) and Start (S) bits are cleared WCOL bit will be set, indicating that a write from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is to the SSPBUF did not occur. set, or the bus is Idle, with both the S and P bits clear. The following events will cause the MSSP Interrupt In Firmware Controlled Master mode, user code Flag bit, SSPIF, to be set (MSSP interrupt, if enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmit 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 18-18: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e SSPSR Detce) MSb LSb L ur e Oo abl WCk s SCL Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT); Clock Arbitration Set SSPIF, BCLIF; Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV © 2009 Microchip Technology Inc. DS39689F-page 195

PIC18F2221/2321/4221/4321 FAMILY 18.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA, while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPCON2 register. ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all 8 bits are logic ‘1’. Thus, the first byte transmitted is a 7-bit slave transmitted. address followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDA, while SCL outputs the slave device and writes its value into the serial clock. Serial data is received 8 bits at a time. After SSPCON2 register. each byte is received, an Acknowledge bit is transmit- ted. Start and Stop conditions indicate the beginning 10. The MSSP module generates an interrupt at the and end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See the Stop Enable bit, PEN (SSPCON2<2>). Section18.4.7 “Baud Rate” for more detail. 12. Interrupt is generated once the Stop condition is complete. DS39689F-page 196 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.7 BAUD RATE Once the given operation is complete (i.e., transmis- In I2C Master mode, the Baud Rate Generator (BRG) sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure18-19). When a write occurs to SSPBUF, the Baud Rate Generator will automatically Table18-3 demonstrates clock rates based on begin counting. The BRG counts down to 0 and stops instruction cycles and the BRG value loaded into until another reload has taken place. The BRG count is SSPADD. decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 18-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<6:0> SSPM<3:0> Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 18-3: I2C™ CLOCK RATE W/BRG FSCL Fosc FCY FCY * 2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz 4 MHz 1 MHz 2 MHz 09h 100 kHz 4 MHz 1 MHz 2 MHz 00h 1 MHz © 2009 Microchip Technology Inc. DS39689F-page 197

PIC18F2221/2321/4221/4321 FAMILY 18.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure18-20). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 18-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS39689F-page 198 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.8 I2C MASTER MODE START Note: If at the beginning of the Start condition, CONDITION TIMING the SDA and SCL pins are already sam- To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, the Enable bit, SEN (SSPCON2<0>). If the SDA and SCL SCL line is sampled low before the SDA pins are sampled high, the Baud Rate Generator is line is driven low, a bus collision occurs, reloaded with the contents of SSPADD<6:0> and starts the Bus Collision Interrupt Flag, BCLIF, is its count. If SCL and SDA are both sampled high when set, the Start condition is aborted and the the Baud Rate Generator times out (TBRG), the SDA I2C module is reset into its Idle state. pin is driven low. The action of the SDA being driven 18.4.8.1 WCOL Status Flag low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the If the user writes the SSPBUF when a Start sequence Baud Rate Generator is reloaded with the contents of is in progress, the WCOL is set and the contents of the SSPADD<6:0> and resumes its count. When the Baud buffer are unchanged (the write doesn’t occur). Rate Generator times out (TBRG), the SEN bit Note: Because queueing of events is not (SSPCON2<0>) will be automatically cleared by allowed, writing to the lower 5 bits of hardware; the Baud Rate Generator is suspended, SSPCON2 is disabled until the Start leaving the SDA line held low and the Start condition is condition is complete. complete. FIGURE 18-21: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S © 2009 Microchip Technology Inc. DS39689F-page 199

PIC18F2221/2321/4221/4321 FAMILY 18.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDA is sampled low when SCL goes the SCL pin is asserted low. When the SCL pin is from low-to-high. sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. • SCL goes low before SDA is The SDA pin is released (brought high) for one Baud asserted low. This may indicate that Rate Generator count (TBRG). When the Baud Rate another master is attempting to Generator times out, if SDA is sampled high, the SCL transmit a data ‘1’. pin will be deasserted (brought high). When SCL is Immediately following the SSPIF bit getting set, the user sampled high, the Baud Rate Generator is reloaded may write the SSPBUF with the 7-bit address in 7-bit with the contents of SSPADD<6:0> and begins count- mode, or the default first address in 10-bit mode. After ing. SDA and SCL must be sampled high for one TBRG. the first eight bits are transmitted and an ACK is This action is then followed by assertion of the SDA pin received, the user may then transmit an additional eight (SDA = 0) for one TBRG while SCL is high. Following bits of address (10-bit mode) or eight bits of data (7-bit this, the RSEN bit (SSPCON2<1>) will be automatically mode). cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a 18.4.9.1 WCOL Status Flag Start condition is detected on the SDA and SCL pins, If the user writes the SSPBUF when a Repeated Start the S bit (SSPSTAT<3>) will be set. The SSPIF bit will sequence is in progress, the WCOL is set and the not be set until the Baud Rate Generator has timed out. contents of the buffer are unchanged (the write doesn’t occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. FIGURE 18-22: REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here. SDA = 1, At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG SDA 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPBUF occurs here end of Xmit TBRG SCL TBRG Sr = Repeated Start DS39689F-page 200 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.10 I2C MASTER MODE TRANSMISSION 18.4.10.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is other half of a 10-bit address is accomplished by simply cleared when the slave has sent an Acknowledge writing a value to the SSPBUF register. This action will (ACK=0) and is set when the slave does not Acknowl- set the Buffer Full flag bit, BF and allow the Baud Rate edge (ACK = 1). A slave sends an Acknowledge when Generator to begin counting and start the next it has recognized its address (including a general call), transmission. Each bit of address/data will be shifted or when the slave has properly received its data. out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification 18.4.11 I2C MASTER MODE RECEPTION parameter106). SCL is held low for one Baud Rate Master mode reception is enabled by programming the Generator rollover count (TBRG). Data should be valid Receive Enable bit, RCEN (SSPCON2<3>). before SCL is released high (see data setup time specification parameter 107). When the SCL pin is Note: The MSSP module must be in an Idle state released high, it is held that way for TBRG. The data on before the RCEN bit is set or the RCEN bit the SDA pin must remain stable for that duration and will be disregarded. some hold time after the next falling edge of SCL. After The Baud Rate Generator begins counting and on each the eighth bit is shifted out (the falling edge of the eighth rollover, the state of the SCL pin changes (high-to-low/ clock), the BF flag is cleared and the master releases low-to-high) and data is shifted into the SSPSR. After SDA. This allows the slave device being addressed to the falling edge of the eighth clock, the receive enable respond with an ACK bit during the ninth bit time if an flag is automatically cleared, the contents of the address match occurred, or if data was received SSPSR are loaded into the SSPBUF, the BF flag bit is properly. The status of ACK is written into the ACKDT set, the SSPIF flag bit is set and the Baud Rate Gener- bit on the falling edge of the ninth clock. If the master ator is suspended from counting, holding SCL low. The receives an Acknowledge, the Acknowledge Status bit, MSSP is now in Idle state awaiting the next command. ACKSTAT, is cleared. If not, the bit is set. After the ninth When the buffer is read by the CPU, the BF flag bit is clock, the SSPIF bit is set and the master clock (Baud automatically cleared. The user can then send an Rate Generator) is suspended until the next data byte Acknowledge bit at the end of reception by setting the is loaded into the SSPBUF, leaving SCL low and SDA Acknowledge Sequence Enable bit, ACKEN unchanged (Figure18-23). (SSPCON2<4>). After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL until all 18.4.11.1 BF Status Flag seven address bits and the R/W bit are completed. On In receive operation, the BF bit is set when an address the falling edge of the eighth clock, the master will or data byte is loaded into SSPBUF from SSPSR. It is deassert the SDA pin, allowing the slave to respond cleared when the SSPBUF register is read. with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the 18.4.11.2 SSPOV Status Flag address was recognized by a slave. The status of the In receive operation, the SSPOV bit is set when 8 bits ACK bit is loaded into the ACKSTAT status bit are received into the SSPSR and the BF flag bit is (SSPCON2<6>). Following the falling edge of the ninth already set from a previous reception. clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is 18.4.11.3 WCOL Status Flag turned off until another write to the SSPBUF takes If the user writes the SSPBUF when a receive is place, holding SCL low and allowing SDA to float. already in progress (i.e., SSPSR is still shifting in a data 18.4.10.1 BF Status Flag byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 18.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL flag is set and the contents of the buffer are unchanged (the write doesn’t occur) after 2TCY after the SSPBUF write. If SSPBUF is rewritten within 2 TCY, the WCOL bit is set and SSPBUF is updated. This may result in a corrupted transfer. The user should verify that the WCOL flag is clear after each write to SSPBUF to ensure the transfer is correct. © 2009 Microchip Technology Inc. DS39689F-page 201

PIC18F2221/2321/4221/4321 FAMILY FIGURE 18-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESSING) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routinefrom MSSP interrupt SSPBUF is written in software From D7 1 w SPIF o S = ‘’0 SCL held lwhile CPUsponds to CK re R/W = 0 A1A ss and R/W, 789 d by hardware ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared in software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS39689F-page 202 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 18-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from Masterer configured as a receiverSDA = ACKDT = SDA = ACKDT = 10ogramming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus masterACK is not sentterminatestransfer678998756512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr ACK from Slave R/W = 1A1ACK 798 Write to SSPCON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 631245SCLS SSPIF Cleared in softwareSDA = , SCL = 01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN © 2009 Microchip Technology Inc. DS39689F-page 203

PIC18F2221/2321/4221/4321 FAMILY 18.4.12 ACKNOWLEDGE SEQUENCE 18.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/ (SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is erate an Acknowledge, then the ACKDT bit should be sampled low, the Baud Rate Generator is reloaded and cleared. If not, the user should set the ACKDT bit before counts down to 0. When the Baud Rate Generator starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is SCL pin is sampled high (clock arbitration), the Baud sampled high while SCL is high, the P bit Rate Generator counts for TBRG. The SCL pin is then (SSPSTAT<4>) is set. A TBRG later, the PEN bit is pulled low. Following this, the ACKEN bit is automatically cleared and the SSPIF bit is set (Figure18-26). cleared, the Baud Rate Generator is turned off and the 18.4.13.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure18-25). If the user writes the SSPBUF when a Stop sequence 18.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 18-25: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in SSPIF set at Cleared in software the end of receive software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 18-26: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS39689F-page 204 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.14 SLEEP OPERATION 18.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 18.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 18.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure18-27). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge monitored for arbitration to see if the signal level is the condition was in progress when the bus collision expected output level. This check is performed in occurred, the condition is aborted, the SDA and SCL hardware with the result placed in the BCLIF bit. lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user ser- The states where arbitration can be lost are: vices the bus collision Interrupt Service Routine and if • Address Transfer the I2C bus is free, the user can resume communication • Data Transfer by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 18-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data doesn’t match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF © 2009 Microchip Technology Inc. DS39689F-page 205

PIC18F2221/2321/4221/4321 FAMILY 18.4.17.1 Bus Collision During a If the SDA pin is sampled low during this count, the Start Condition BRG is reset and the SDA line is asserted early (Figure18-30). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure18-28). counts down to 0; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure18-29). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus masters can assert a Start condition at the If the SDA pin is already low, or the SCL pin is already exact same time. Therefore, one master low, then all of the following occur: will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus • the BCLIF flag is set and collision because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address (Figure18-28). following the Start condition. If the address The Start condition begins with the SDA and SCL pins is the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 18-28: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 MSSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS39689F-page 206 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 18-29: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 18-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software © 2009 Microchip Technology Inc. DS39689F-page 207

PIC18F2221/2321/4221/4321 FAMILY 18.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure18-31). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition, When the user deasserts SDA and the pin is allowed to see Figure18-32. float high, the BRG is loaded with SSPADD<6:0> and If, at the end of the BRG time-out, both SCL and SDA counts down to 0. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 18-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 18-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF DS39689F-page 208 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 18.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure18-33). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure18-34). FIGURE 18-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 18-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’ © 2009 Microchip Technology Inc. DS39689F-page 209

PIC18F2221/2321/4221/4321 FAMILY TABLE 18-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 58 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 58 SSPBUF MSSP Receive Buffer/Transmit Register 56 SSPADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 56 TMR2 Timer2 Register 56 PR2 Timer2 Period Register 56 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 56 SSPCON2 GCEN ACKSTAT ACKDT/ ACKEN/ RCEN/ PEN/ RSEN/ SEN 56 ADMSK5 ADMSK5 ADMSK5 ADMSK5 ADMSK5 SSPSTAT SMP CKE D/A P S R/W UA BF 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode. DS39689F-page 210 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 19.0 ENHANCED UNIVERSAL The pins of the Enhanced USART are multiplexed SYNCHRONOUS with PORTC. In order to configure RC6/TX/CK and RC7/RX/DT as an EUSART: ASYNCHRONOUS RECEIVER • bit SPEN (RCSTA<7>) must be set (= 1) TRANSMITTER (EUSART) • bit TRISC<7> must be set (= 1) The Enhanced Universal Synchronous Asynchronous • bit TRISC<6> must be set (= 1) Receiver Transmitter (EUSART) module is one of the Note: The EUSART control will automatically two serial I/O modules. (Generically, the USART is also reconfigure the pin from input to output as known as a Serial Communications Interface or SCI.) needed. The EUSART can be configured as a full-duplex asynchronous system that can communicate with The operation of the Enhanced USART module is peripheral devices, such as CRT terminals and controlled through three registers: personal computers. It can also be configured as a half- • Transmit Status and Control (TXSTA) duplex synchronous system that can communicate • Receive Status and Control (RCSTA) with peripheral devices, such as A/D or D/A integrated • Baud Rate Control (BAUDCON) circuits, serial EEPROMs, etc. These are detailed on the following pages in The Enhanced USART module implements additional Register19-1, Register19-2 and Register19-3, features, including automatic baud rate detection and respectively. calibration, automatic wake-up on Sync Break recep- tion and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN/J2602 bus) systems. The EUSART can be configured in the following modes: • Asynchronous (full duplex) with: - Auto-wake-up on Break signal - Auto-baud calibration - 12-bit Break character transmission • Synchronous – Master (half duplex) with selectable clock polarity • Synchronous – Slave (half duplex) with selectable clock polarity © 2009 Microchip Technology Inc. DS39689F-page 211

PIC18F2221/2321/4221/4321 FAMILY REGISTER 19-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 212 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 19-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 213

PIC18F2221/2321/4221/4321 FAMILY REGISTER 19-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 RXDTP: Received Data Polarity Select bit Asynchronous mode: 1 = Receive data (RX) is inverted (active-low) 0 = Receive data (RX) is not inverted (active-high) Synchronous mode: No affect. bit 4 TXCKP: Clock and Data Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TX) is a low level 0 = Idle state for transmit (TX) is a high level Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 214 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 19.1 Baud Rate Generator (BRG) Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This The BRG is a dedicated 8-bit or 16-bit generator that ensures the BRG does not wait for a timer overflow supports both the Asynchronous and Synchronous before outputting the new baud rate. modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) Note: A BRG value of 0 is not supported. selects 16-bit mode. 19.1.1 OPERATION IN POWER-MANAGED The SPBRGH:SPBRG register pair controls the period MODES of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also The device clock is used to generate the desired baud control the baud rate. In Synchronous mode, BRGH is rate. When one of the power-managed modes is ignored. Table19-1 shows the formula for computation entered, the new clock source may be operating at a of the baud rate for different EUSART modes which different frequency. This may require an adjustment to only apply in Master mode (internally generated clock). the value in the SPBRG register pair. Given the desired baud rate and FOSC, the nearest 19.1.2 SAMPLING integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table19-1. From this, The data on the RX pin is sampled three times by a the error in baud rate can be determined. An example majority detect circuit to determine if a high or a low calculation is shown in Example19-1. Typical baud level is present at the RX pin when SYNC is clear or rates and error values for the various Asynchronous when BRG16 and BRGH are both not set. The data on modes are shown in Table19-2. It may be advantageous the RX pin is sampled once when SYNC is set or when to use the high baud rate (BRGH = 1) or the 16-bit BRG BRGH16 and BRGH are both set. to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. TABLE 19-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair © 2009 Microchip Technology Inc. DS39689F-page 215

PIC18F2221/2321/4221/4321 FAMILY EXAMPLE 19-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 19-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39689F-page 216 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — © 2009 Microchip Technology Inc. DS39689F-page 217

PIC18F2221/2321/4221/4321 FAMILY TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39689F-page 218 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 19.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure19-1) begins whenever a Start bit is received Some combinations of oscillator frequency and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible self-averaging. due to bit error rates. Overall system timing and communication baud rates In the Auto-Baud Rate Detect (ABD) mode, the clock to must be taken into consideration when the BRG is reversed. Rather than the BRG clocking the using the Auto-Baud Rate Detection incoming RX signal, the RX signal is timing the BRG. In feature. ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial 3: To maximize the baud rate range, it is byte stream. recommended to set the BRG16 bit if the auto-baud feature is used. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII TABLE 19-4: BRG COUNTER “U”, which is also the LIN/J2602 bus Sync character) in CLOCK RATES order to calculate the proper bit rate. The measurement BRG16 BRGH BRG Counter Clock is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incom- 0 0 FOSC/512 ing signal. After a Start bit, the SPBRG begins counting 0 1 FOSC/128 up, using the preselected clock source on the first rising 1 0 FOSC/128 edge of RX. After eight bits on the RX pin, or the fifth ris- ing edge, an accumulated value totalling the proper BRG 1 1 FOSC/32 period is left in the SPBRGH:SPBRG register pair. Once the 5th edge is seen (this should correspond to the Stop 19.1.3.1 ABD and EUSART Transmission bit), the ABDEN bit is automatically cleared. Since the BRG clock is reversed during ABD acquisi- If a rollover of the BRG occurs (an overflow from FFFFh tion, the EUSART transmitter cannot be used during to 0000h), the event is trapped by the ABDOVF status ABD. This means that whenever the ABDEN bit is set, bit (BAUDCON<7>). It is set in hardware by BRG TXREG cannot be written to. Users should also ensure rollovers and can be set or cleared by the user in that ABDEN does not become set during a transmit software. ABD mode remains active after rollover sequence. Failing to do this may result in unpredictable events and the ABDEN bit remains set (Figure19-2). EUSART operation. While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock can be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG1 and SPBRGH1 as a 16-bit counter This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table19-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. © 2009 Microchip Technology Inc. DS39689F-page 219

PIC18F2221/2321/4221/4321 FAMILY FIGURE 19-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 19-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39689F-page 220 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 19.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty The Asynchronous mode of operation is selected by and the TXIF flag bit (PIR1<4>) is set. This interrupt can clearing the SYNC bit (TXSTA<4>). In this mode, the be enabled or disabled by setting or clearing the interrupt EUSART uses standard Non-Return-to-Zero (NRZ) enable bit, TXIE (PIE1<4>). TXIF will be set regardless of format (one Start bit, eight or nine data bits and one the state of TXIE; it cannot be cleared in software. TXIF Stop bit). The most common data format is 8 bits. An is also not cleared immediately upon loading TXREG, but on-chip dedicated 8-bit/16-bit Baud Rate Generator becomes valid in the second instruction cycle following can be used to derive standard baud rate frequencies the load instruction. Polling TXIF immediately following a from the oscillator. load of TXREG will return invalid results. The EUSART transmits and receives the LSb first. The While TXIF indicates the status of the TXREG register, EUSART’s transmitter and receiver are functionally another bit, TRMT (TXSTA<1>), shows the status of independent but use the same data format and baud the TSR register. TRMT is a read-only bit which is set rate. The Baud Rate Generator produces a clock, either when the TSR register is empty. No interrupt logic is x16 or x64 of the bit shift rate depending on the BRGH tied to this bit so the user has to poll this bit in order to and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity determine if the TSR register is empty. is not supported by the hardware but can be implemented in software and stored as the 9th data bit. The TXCKP bit (BAUDCON<4>) allows the TX signal to be inverted (polarity reversed). Devices that buffer The TXCKP (BAUDCON<4>) and RXDTP signals from TTL to RS-232 levels also invert the signal (BAUDCON<5>) bits allow the TX and RX signals to be (when TTL = 1, RS-232 = negative). Inverting the inverted (polarity reversed). Devices that buffer signals polarity of the TX pin data by setting the TXCKP bit between TTL and RS-232 levels also invert the signal. allows for use of circuits that provide buffering without Setting the TXCKP and RXDTP bits allows for the use of inverting the signal. circuits that provide buffering without inverting the signal. In Asynchronous mode, clock polarity is selected with Note1: The TSR register is not mapped in data the TXCKP bit (BAUDCON<4>). Setting TXCKP sets memory so it is not available to the user. the Idle state on CK as high, while clearing the bit sets 2: Flag bit TXIF is set when enable bit TXEN the Idle state as low. Data polarity is selected with the is set. RXDTP bit (BAUDCON<5>). Setting RXDTP inverts To set up an Asynchronous Transmission: data on RX, while clearing the bit has no affect on received data. 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH When operating in Asynchronous mode, the EUSART and BRG16 bits, as required, to achieve the module consists of the following important elements: desired baud rate. • Baud Rate Generator 2. Enable the asynchronous serial port by clearing • Sampling Circuit bit, SYNC, and setting bit, SPEN. • Asynchronous Transmitter 3. If the signal from the TX pin is to be inverted, set • Asynchronous Receiver the TXCKP bit. • Auto-Wake-up on Break signal 4. If interrupts are desired, set enable bit, TXIE. • 12-bit Break Character Transmit 5. If 9-bit transmission is desired, set transmit bit, • Auto-Baud Rate Detection TX9; can be used as address/data bit. • Pin State Polarity 6. Enable the transmission by setting bit, TXEN, which will also set bit, TXIF. 19.2.1 EUSART ASYNCHRONOUS 7. If 9-bit transmission is selected, the ninth bit TRANSMITTER should be loaded in bit, TX9D. 8. Load data to the TXREG register (starts The EUSART transmitter block diagram is shown in transmission). Figure19-3. The heart of the transmitter is the Transmit 9. If using interrupts, ensure that the GIE and PEIE (Serial) Shift Register (TSR). The Shift register obtains bits in the INTCON register (INTCON<7:6>) are its data from the Read/Write Transmit Buffer register, set. TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). © 2009 Microchip Technology Inc. DS39689F-page 221

PIC18F2221/2321/4221/4321 FAMILY FIGURE 19-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXCKP TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register TX pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGH SPBRG TX9 Baud Rate Generator TX9D FIGURE 19-4: ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TX NOT INVERTED) Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 19-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK), TXCKP = 0 (TX NOT INVERTED) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS39689F-page 222 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 TXREG EUSART Transmit Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 223

PIC18F2221/2321/4221/4321 FAMILY 19.2.2 EUSART ASYNCHRONOUS 19.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure19-6. This mode would typically be used in RS-485 systems. The data is received on the RX pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGH:SPBRG registers for the whereas the main receive serial shifter operates at the appropriate baud rate. Set or clear the BRGH bit rate or at FOSC. This mode would typically be used and BRG16 bits, as required, to achieve the in RS-232 systems. desired baud rate. The RXDTP bit (BAUDCON<5>) allows the RX signal to 2. Enable the asynchronous serial port by clearing be inverted (polarity reversed). Devices that buffer the SYNC bit and setting the SPEN bit. signals from RS-232 to TTL levels also perform an inver- 3. If the signal at the RX pin is to be inverted, set sion of the signal (when RS-232 = positive, TTL = 0). the RXDTP bit. If the signal from the TX pin is to Inverting the polarity of the RX pin data by setting the be inverted, set the TXCKP bit. RXDTP bit allows for the use of circuits that provide 4. If interrupts are required, set the RCEN bit and buffering without inverting the signal. select the desired priority level with the RCIP bit. To set up an Asynchronous Reception: 5. Set the RX9 bit to enable 9-bit reception. 1. Initialize the SPBRGH:SPBRG registers for the 6. Set the ADDEN bit to enable address detect. appropriate baud rate. Set or clear the BRGH 7. Enable reception by setting the CREN bit. and BRG16 bits, as required, to achieve the 8. The RCIF bit will be set when reception is desired baud rate. complete. The interrupt will be Acknowledged if 2. Enable the asynchronous serial port by clearing the RCIE and GIE bits are set. bit, SYNC, and setting bit, SPEN. 9. Read the RCSTA register to determine if any 3. If the signal at the RX pin is to be inverted, set error occurred during reception, as well as read the RXDTP bit. bit 9 of data (if applicable). 4. If interrupts are desired, set enable bit, RCIE. 10. Read RCREG to determine if the device is being 5. If 9-bit reception is desired, set bit, RX9. addressed. 6. Enable the reception by setting bit, CREN. 11. If any error occurred, clear the CREN bit. 7. Flag bit, RCIF, will be set when reception is 12. If the device has been addressed, clear the complete and an interrupt will be generated if ADDEN bit to allow all received data into the enable bit, RCIE, was set. receive buffer and interrupt the CPU. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing enable bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. DS39689F-page 224 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 19-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG ÷ o6r4 MSb RSR Register LSb ÷ 16 or Stop (8) 7 • • • 1 0 Start Baud Rate Generator ÷ 4 RX9 Pin Buffer Data and Control Recovery RX RX9D RCREG Register FIFO RXDTP SPEN 8 Interrupt RCIF Data Bus RCIE FIGURE 19-7: ASYNCHRONOUS RECEPTION, TXCKP = 0 (TX NOT INVERTED) RX (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (overrun) bit to be set. TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 RCREG EUSART Receive Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 225

PIC18F2221/2321/4221/4321 FAMILY 19.2.4 AUTO-WAKE-UP ON SYNC and cause data or framing errors. To work properly, BREAK CHARACTER therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 During Sleep mode, all clocks to the EUSART are devices or 000h (12 bits) for the LIN/J2602 bus. suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be per- Oscillator start-up time must also be considered, formed. The auto-wake-up feature allows the controller especially in applications using oscillators with longer to wake-up due to activity on the RX/DT line while the start-up intervals (i.e., XT or HS mode). The Sync EUSART is operating in Asynchronous mode. Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval The auto-wake-up feature is enabled by setting the to allow enough time for the selected oscillator to start WUE bit (BAUDCON<1>). Once set, the typical receive and provide proper initialization of the EUSART. sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event 19.2.4.2 Special Considerations Using independent of the CPU mode. A wake-up event the WUE Bit consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a The timing of WUE and RCIF events may cause some Wake-up Signal character for the LIN/J2602 protocol.) confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the Following a wake-up event, the module generates an EUSART in an Idle mode. The wake-up event causes a RCIF interrupt. The interrupt is generated synchro- receive interrupt by setting the RCIF bit. The WUE bit is nously to the Q clocks in normal operating modes cleared after this when a rising edge is seen on RX/DT. (Figure19-8) and asynchronously, if the device is in The interrupt condition is then cleared by reading the Sleep mode (Figure19-9). The interrupt condition is RCREG register. Ordinarily, the data in RCREG will be cleared by reading the RCREG register. dummy data and should be discarded. The WUE bit is automatically cleared once a low-to- The fact that the WUE bit has been cleared (or is still high transition is observed on the RX line following the set) and the RCIF flag is set should not be used as an wake-up event. At this point, the EUSART module is in indicator of the integrity of the data in RCREG. Users Idle mode and returns to normal operation. This signals should consider implementing a parallel method in to the user that the Sync Break event is over. firmware to verify received data integrity. 19.2.4.1 Special Considerations Using To assure that no actual data is lost, check the RCIDL Auto-Wake-up bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may Since auto-wake-up functions by sensing rising edge then be set just prior to entering the Sleep mode. transitions on RX/DT, information with any state changes before the Stop bit may signal a false end-of-character FIGURE 19-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RX/DT Line RCIF Cleared due to user read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 19-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RX/DT Line Note 1 RCIF Cleared due to user read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS39689F-page 226 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 19.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The EUSART module has the capability of sending the 2. Set the TXEN and SENDB bits to set up the special Break character sequences that are required by Break character. the LIN/J2602 bus standard. The Break character 3. Load the TXREG with a dummy character to transmit consists of a Start bit, followed by twelve ‘0’ initiate transmission (the value is ignored). bits and a Stop bit. The Frame Break character is sent 4. Write ‘55h’ to TXREG to load the Sync character whenever the SENDB and TXEN bits (TXSTA<3> and into the transmit FIFO buffer. TXSTA<5>) are set while the Transmit Shift register is 5. After the Break has been sent, the SENDB bit is loaded with data. Note that the value of data written to reset by hardware. The Sync character now TXREG will be ignored and all ‘0’s will be transmitted. transmits in the preconfigured mode. The SENDB bit is automatically reset by hardware after When the TXREG becomes empty, as indicated by the the corresponding Stop bit is sent. This allows the user TXIF, the next data byte can be written to TXREG. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 19.2.6 RECEIVING A BREAK CHARACTER character in the LIN/J2602 specification). The Enhanced USART module can receive a Break Note that the data value written to the TXREG for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling loca- active or Idle, just as it does during normal transmis- tion (13 bits for Break versus Start bit and 8 data bits for sion. See Figure19-10 for the timing of the Break typical data). character sequence. The second method uses the auto-wake-up feature 19.2.5.1 Break and Sync Transmit Sequence described in Section19.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSART will sample the next two transitions on RX/DT, header made up of a Break, followed by an Auto-Baud cause an RCIF interrupt and receive the next data byte Sync byte. This sequence is typical of a LIN/J2602 bus followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. FIGURE 19-10: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) © 2009 Microchip Technology Inc. DS39689F-page 227

PIC18F2221/2321/4221/4321 FAMILY 19.3 EUSART Synchronous Once the TXREG register transfers the data to the TSR Master Mode register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be The Master mode indicates that the processor trans- enabled or disabled by setting or clearing the interrupt mits the master clock on the CK line. The Synchronous enable bit, TXIE (PIE1<4>). TXIF is set regardless of Master mode is entered by setting the CSRC bit the state of enable bit TXIE; it cannot be cleared in (TXSTA<7>). In this mode, the data is transmitted in a software. It will reset only when new data is loaded into half-duplex manner (i.e., transmission and reception do the TXREG register. not occur at the same time). When transmitting data, While flag bit TXIF indicates the status of the TXREG the reception is inhibited and vice versa. Synchronous register, another bit, TRMT (TXSTA<1>), shows the mode is entered by setting bit SYNC (TXSTA<4>). In status of the TSR register. TRMT is a read-only bit which addition, enable bit SPEN (RCSTA<7>) is set in order is set when the TSR is empty. No interrupt logic is tied to to configure the TX and RX pins to CK (clock) and DT this bit so the user has to poll this bit in order to deter- (data) lines, respectively. mine if the TSR register is empty. The TSR is not The Master mode indicates that the processor mapped in data memory so it is not available to the user. transmits the master clock on the CK line. To set up a Synchronous Master Transmission: Clock polarity (CK) is selected with the TXCKP bit 1. Initialize the SPBRGH:SPBRG registers for the (BAUDCON<4>). Setting TXCKP sets the Idle state on appropriate baud rate. Set or clear the BRG16 CK as high, while clearing the bit sets the Idle state as bit, as required, to achieve the desired baud rate. low. 2. Enable the synchronous master serial port by 19.3.1 EUSART SYNCHRONOUS MASTER setting bits, SYNC, SPEN and CSRC. TRANSMISSION 3. If the signal from the CK pin is to be inverted, set the TXCKP bit. The EUSART transmitter block diagram is shown in 4. If interrupts are desired, set enable bit, TXIE. Figure19-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains 5. If 9-bit transmission is desired, set bit, TX9. its data from the Read/Write Transmit Buffer register, 6. Enable the transmission by setting bit, TXEN. TXREG. The TXREG register is loaded with data in 7. If 9-bit transmission is selected, the ninth bit software. The TSR register is not loaded until the last should be loaded in bit, TX9D. bit has been transmitted from the previous load. As 8. Start transmission by loading data to the TXREG soon as the last bit is transmitted, the TSR is loaded register. with new data from the TXREG (if available). 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 19-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin (TXCKP = 0) RC6/TX/CK pin (TXCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. DS39689F-page 228 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 19-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 TXREG EUSART Transmit Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 229

PIC18F2221/2321/4221/4321 FAMILY 19.3.2 EUSART SYNCHRONOUS 4. If the signal from the CK pin is to be inverted, set MASTER RECEPTION the TXCKP bit. 5. If interrupts are desired, set enable bit, RCIE. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, 6. If 9-bit reception is desired, set bit, RX9. SREN (RCSTA<5>), or the Continuous Receive 7. If a single reception is required, set bit, SREN. Enable bit, CREN (RCSTA<4>). Data is sampled on the For continuous reception, set bit, CREN. RX pin on the falling edge of the clock. 8. Interrupt flag bit, RCIF, will be set when reception If enable bit SREN is set, only a single word is received. is complete and an interrupt will be generated if If enable bit CREN is set, the reception is continuous the enable bit, RCIE, was set. until CREN is cleared. If both bits are set, then CREN 9. Read the RCSTA register to get the 9th bit (if takes precedence. enabled) and determine if any error occurred during reception. To set up a Synchronous Master Reception: 10. Read the 8-bit received data by reading the 1. Initialize the SPBRGH:SPBRG registers for the RCREG register. appropriate baud rate. Set or clear the BRG16 11. If any error occurred, clear the error by clearing bit, as required, to achieve the desired baud rate. bit, CREN. 2. Enable the synchronous master serial port by 12. If using interrupts, ensure that the GIE and PEIE bits setting bits, SYNC, SPEN and CSRC. in the INTCON register (INTCON<7:6>) are set. 3. Ensure bits, CREN and SREN, are clear. FIGURE 19-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK pin (TXCKP = 0) RC6/TX/CK pin (TXCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 RCREG EUSART Receive Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. DS39689F-page 230 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 19.4 EUSART Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTA<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CK pin (instead of being supplied 3. If interrupts are desired, set enable bit, TXIE. internally in Master mode). This allows the device to 4. If the signal from the CK pin is to be inverted, set transfer or receive data while in any power-managed the TXCKP bit. mode. 5. If 9-bit transmission is desired, set bit, TX9. 6. Enable the transmission by setting enable bit, 19.4.1 EUSART SYNCHRONOUS TXEN. SLAVE TRANSMISSION 7. If 9-bit transmission is selected, the ninth bit The operation of the Synchronous Master and Slave should be loaded in bit TX9D. modes are identical, except in the case of the Sleep 8. Start transmission by loading data to the mode. TXREGx register. If two words are written to the TXREG and then the 9. If using interrupts, ensure that the GIE and PEIE SLEEP instruction is executed, the following will occur: bits in the INTCON register (INTCON<7:6>) are a) The first word will immediately transfer to the set. TSR register and transmit. b) The second word will remain in the TXREG register. c) Flag bit, TXIF, will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. e) If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 TXREG EUSART Transmit Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 231

PIC18F2221/2321/4221/4321 FAMILY 19.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit RCIE. Slave mode. 3. If the signal from the CK pin is to be inverted, set If receive is enabled by setting the CREN bit prior to the TXCKP bit. entering Sleep or any Idle mode, then a word may be 4. If 9-bit reception is desired, set bit, RX9. received while in this low-power mode. Once the word 5. To enable reception, set enable bit, CREN. is received, the RSR register will transfer the data to the 6. Flag bit, RCIF, will be set when reception is RCREG register; if the RCIE enable bit is set, the complete. An interrupt will be generated if interrupt generated will wake the chip from the low- enable bit, RCIE, was set. power mode. If the global interrupt is enabled, the 7. Read the RCSTA register to get the 9th bit (if program will branch to the interrupt vector. enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57 RCREG EUSART Receive Register 57 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 57 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 57 SPBRGH EUSART Baud Rate Generator Register High Byte 57 SPBRG EUSART Baud Rate Generator Register Low Byte 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. DS39689F-page 232 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 20.0 10-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register20-1, CONVERTER (A/D) MODULE controls the operation of the A/D module. The ADCON1 register, shown in Register20-2, configures The Analog-to-Digital (A/D) converter module has the functions of the port pins. The ADCON2 register, 10inputs for the 28-pin devices and 13 for the 40/44-pin shown in Register20-3, configures the A/D clock devices. This module allows conversion of an analog source, programmed acquisition time and justification. input signal to a corresponding 10-bit digital number. The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) REGISTER 20-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) Note1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 233

PIC18F2221/2321/4221/4321 FAMILY REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits PCFG<3:0> N12 N11 N10 N9 N8 (2)N7 (2)N6 (2)N5 N4 N3 N2 N1 N0 A A A A A A A A A A A A A 0000(1) A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 0111(1) D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D A = Analog input D = Digital I/O Note1: The POR value of the PCFG bits depends on the value of the PBADEN Con- figuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. 2: AN5 through AN7 are available only on 40/44-pin devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39689F-page 234 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 235

PIC18F2221/2321/4221/4321 FAMILY The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (VDD and VSS), or the voltage level on the RA3/AN3/ conversion in progress is aborted. VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D converter can be The A/D converter has a unique feature of being able configured as an analog input, or as a digital I/O. The to operate while the device is in Sleep mode. To ADRESH and ADRESL registers contain the result of operate in Sleep, the A/D conversion clock must be the A/D conversion. When the A/D conversion is derived from the A/D’s internal RC oscillator. complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit The output of the sample and hold is the input into the (ADCON0 register) is cleared and A/D Interrupt Flag bit, converter, which generates the result via successive ADIF, is set. The block diagram of the A/D module is approximation. shown in Figure20-1. FIGURE 20-1: A/D BLOCK DIAGRAM CHS<3:0> 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7(1) 0110 AN6(1) 0101 AN5(1) 0100 AN4 VAIN 10-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG<1:0> AN1 VDD 0000 AN0 X0 VREF+ X1 Reference Voltage 1X VREF- 0X VSS Note 1: Channels AN5 through AN7 are not available on 28-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39689F-page 236 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY The value in the ADRESH:ADRESL registers is not 5. Wait for A/D conversion to complete, by either: modified for a Power-on Reset. The ADRESH:ADRESL • Polling for the GO/DONE bit to be cleared registers will contain unknown data after a Power-on OR Reset. • Waiting for the A/D interrupt After the A/D module has been configured as desired, 6. Read A/D Result registers (ADRESH:ADRESL); the selected channel must be acquired before the conversion is started. The analog input channels must clear bit ADIF, if required. have their corresponding TRIS bits selected as an 7. For next conversion, go to step 1 or step 2, as input. To determine acquisition time, see Section20.1 required. The A/D conversion time per bit is “A/D Acquisition Requirements”. After this acquisi- defined as TAD. A minimum wait of 2 TAD is tion time has elapsed, the A/D conversion can be required before the next acquisition starts. started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual FIGURE 20-2: A/D TRANSFER FUNCTION start of the conversion. The following steps should be followed to perform an A/D 3FFh conversion: 1. Configure the A/D module: 3FEh • Configure analog pins, voltage reference and put ut digital I/O (ADCON1) O e • Select A/D input channel (ADCON0) od C • Select A/D acquisition time (ADCON2) al 003h git • Select A/D conversion clock (ADCON2) Di 002h • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): 001h • Clear ADIF bit • Set ADIE bit 000h B B B B B B B B B B • Set GIE bit S S S S S S S S S S L L L L L L L L L L 34.. WStaaritt tchoen rveeqrsuiiorend: acquisition time (if required). 0.5 1 1.5 2 2.5 3 1022 1022.5 1023 1023.5 Analog Input Voltage • Set GO/DONE bit (ADCON0 register) FIGURE 20-3: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage 6V ILEAKAGE = Leakage Current at the pin due to 5V various junctions VDD 4V 3V RIC = Interconnect Resistance 2V SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) 1 2 3 4 RSS = Sampling Switch Resistance SamplingSwitch(kΩ) © 2009 Microchip Technology Inc. DS39689F-page 237

PIC18F2221/2321/4221/4321 FAMILY 20.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation20-1 may be used. This equation assumes For the A/D converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure20-3. The Example20-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5 kΩ. After the analog input channel is VDD = 5V → Rss = 2 kΩ selected (changed), the channel must be sampled for Temperature = 85°C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 20-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 20-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 20-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) -(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) 1.05 μs TACQ = 0.2 μs + 1 μs + 1.2 μs 2.4 μs DS39689F-page 238 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 20.2 Selecting and Configuring 20.3 Selecting the A/D Conversion Acquisition Time Clock The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The acquisition time that occurs each time the GO/DONE A/D conversion requires 11 TAD per 10-bit conversion. bit is set. It also gives users the option to use an The source of the A/D conversion clock is software automatically determined acquisition time. selectable. There are seven possible options for TAD: Acquisition time may be set with the ACQT<2:0> bits • 2 TOSC (ADCON2<5:3>), which provides a range of 2 to • 4 TOSC 20TAD. When the GO/DONE bit is set, the A/D module • 8 TOSC continues to sample the input for the selected acquisi- • 16 TOSC tion time, then automatically begins a conversion. Since the acquisition time is programmed, there may • 32 TOSC be no need to wait for an acquisition time between • 64 TOSC selecting a channel and setting the GO/DONE bit. • Internal RC Oscillator Manual acquisition is selected when For correct A/D conversions, the A/D conversion clock ACQT<2:0>=000. When the GO/DONE bit is set, (TAD) must be as short as possible, but greater than the sampling is stopped and a conversion begins. The user minimum TAD (see parameter 130 for more is responsible for ensuring the required acquisition time information). has passed between selecting the desired input Table20-1 shows the resultant TAD times derived from channel and setting the GO/DONE bit. This option is the device operating frequencies and the A/D clock also the default Reset state of the ACQT<2:0> bits and source selected. is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS<2:0> PIC18F2X21/4X21 PIC18LF2X21/4X21(4) 2 TOSC 000 2.86 MHz 1.43 kHz 4 TOSC 100 5.71 MHz 2.86 MHz 8 TOSC 001 11.43 MHz 5.72 MHz 16 TOSC 101 22.86 MHz 11.43 MHz 32 TOSC 010 40.0 MHz 22.86 MHz 64 TOSC 110 40.0 MHz 22.86 MHz RC(3) x11 1.00 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 1.2 μs. 2: The RC source has a typical TAD time of 2.5 μs. 3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power (PIC18LFXXXX) devices only. © 2009 Microchip Technology Inc. DS39689F-page 239

PIC18F2221/2321/4221/4321 FAMILY 20.4 Operation in Power-Managed 20.5 Configuring Analog Port Pins Modes The ADCON1, TRISA, TRISB and TRISE registers all The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits source and frequency while in a power-managed mode. set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and The A/D operation is independent of the state of the ADCS<2:0> bits in ADCON2 should be updated in CHS<3:0> bits and the TRIS bits. accordance with the clock source to be used in that Note1: When reading the Port register, all pins mode. After entering the mode, an A/D acquisition or configured as analog input channels will conversion may be started. Once started, the device read as cleared (a low level). Pins should continue to be clocked by the same clock configured as digital inputs will convert as source until the conversion has been completed. analog inputs. Analog levels on a digitally If desired, the device may be placed into the configured input will be accurately corresponding Idle mode during the conversion. If the converted. device clock frequency is less than 1MHz, the A/D RC 2: Analog levels on any pin defined as a clock source should be selected. digital input may cause the digital input Operation in Sleep mode requires the A/D FRC clock to buffer to consume current out of the be selected. If bits ACQT<2:0> are set to ‘000’ and a device’s specification limits. conversion is started, the conversion will be delayed 3: The PBADEN bit in Configuration one instruction cycle to allow execution of the SLEEP Register 3H configures PORTB pins to instruction and entry to Sleep mode. The IDLEN bit reset as analog or digital pins by control- (OSCCON<7>) must have already been cleared prior ling how the PCFG<3:0> bits in ADCON1 to starting the conversion. are reset. DS39689F-page 240 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 20.6 A/D Conversions After the A/D conversion is completed or aborted, a 2TAD wait is required before the next acquisition can be Figure20-4 shows the operation of the A/D converter started. After this wait, acquisition on the selected after the GO/DONE bit has been set and the channel is automatically started. ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep Note: The GO/DONE bit should NOT be set in mode before the conversion begins. the same instruction that turns on the A/D. Figure20-5 shows the operation of the A/D converter 20.7 Discharge after the GO/DONE bit has been set and the ACQT<2:0> bits are set to ‘010’ and selecting a 4TAD The discharge phase is used to initialize the value of acquisition time before the conversion starts. the capacitor array. The array is discharged before Clearing the GO/DONE bit during a conversion will abort every sample. This feature helps to optimize the unity- the current conversion. The A/D Result register pair will gain amplifier, as the circuit always needs to charge the NOT be updated with the partially completed A/D capacitor array, rather than charge/discharge based on conversion sample. This means the ADRESH:ADRESL previous measure values. registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). FIGURE 20-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 20-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Discharge Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. © 2009 Microchip Technology Inc. DS39689F-page 241

PIC18F2221/2321/4221/4321 FAMILY 20.8 Use of the CCP2 Trigger (moving ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected An A/D conversion can be started by the Special Event and the minimum acquisition period is either timed by Trigger of the CCP2 module. This requires that the the user, or an appropriate TACQ time selected before CCP2M<3:0> bits (CCP2CON<3:0>) be programmed the Special Event Trigger sets the GO/DONE bit (starts as ‘1011’ and that the A/D module is enabled (ADON a conversion). bit is set). When the trigger occurs, the GO/DONE bit If the A/D module is not enabled (ADON is cleared), the will be set, starting the A/D acquisition and conversion Special Event Trigger will be ignored by the A/D module and the Timer1 (or Timer3) counter will be reset to zero. but will still reset the Timer1 (or Timer3) counter. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead TABLE 20-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 ADRESH A/D Result Register High Byte 57 ADRESL A/D Result Register Low Byte 57 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 57 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 57 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 57 PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 58 TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 58 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 58 TRISB PORTB Data Direction Control Register 58 LATB PORTB Data Latch Register (Read and Write to Data Latch) 58 PORTE — — — — RE3(3) RE2(1) RE1(1) RE0(1) 58 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 58 LATE(1) — — — — — PORTE Data Latch Register 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These registers and/or bits are unimplemented on 28-pin devices and are read as ‘0’. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. DS39689F-page 242 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 21.0 COMPARATOR MODULE The CMCON register (Register21-1) selects the comparator input and output configuration. Block The analog comparator module contains two diagrams of the various comparator configurations are comparators that can be configured in a variety of shown in Figure21-1. ways. The inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip voltage reference (see Section22.0 “Comparator Voltage Reference Module”). The digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110: 1 = C1 VIN- connects to RA3/AN3/VREF+ C2 VIN- connects to RA2/AN2/VREF-/CVREF 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 bit 2-0 CM<2:0>: Comparator Mode bits Figure21-1 shows the Comparator modes and the CM<2:0> bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 243

PIC18F2221/2321/4221/4321 FAMILY 21.1 Comparator Configuration comparator output level may not be valid for the specified mode change delay shown in Section27.0 There are eight modes of operation for the comparators, “Electrical Characteristics”. shown in Figure21-1. Bits CM<2:0> of the CMCON register are used to select these modes. The TRISA reg- Note: Comparator interrupts should be disabled ister controls the data direction of the comparator pins during a Comparator mode change; for each mode. If the Comparator mode is changed, the otherwise, a false interrupt may occur. FIGURE 21-1: COMPARATOR I/O OPERATING MODES Comparators Reset Comparators Off (POR Default Value) CM<2:0> = 000 CM<2:0> = 111 RA0/AN0 A VIN- RA0/AN0 D VIN- RA3/AN3/ A VIN+ C1 Off (Read as ‘0’) RA3/AN3/ D VIN+ C1 Off (Read as ‘0’) VREF+ VREF+ RA1/AN1 A VIN- RA1/AN1 D VIN- RA2/AN2/ A VIN+ C2 Off (Read as ‘0’) RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) VREF-/CVREF VREF-/CVREF Two Independent Comparators Two Independent Comparators with Outputs CM<2:0> = 010 CM<2:0> = 011 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A VIN+ C1 C1OUT VREF+ VREF+ RA4/T0CKI/C1OUT* RA1/AN1 A VIN- RA2/AN2/ A VIN+ C2 C2OUT RA1/AN1 A VIN- VREF-/CVREF RA2/AN2/ A VIN+ C2 C2OUT VREF-/CVREF RA5/AN4/SS/HLVDIN/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM<2:0> = 100 CM<2:0> = 101 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A VIN+ C1 C1OUT VREF+ VREF+ RA4/T0CKI/C1OUT* RA1/AN1 A VIN- RA2/AN2/ D VIN+ C2 C2OUT RA1/AN1 A VIN- VREF-/CVREF RA2/AN2/ D VIN+ C2 C2OUT VREF-/CVREF RA5/AN4/SS/HLVDIN/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM<2:0> = 001 CM<2:0> = 110 RA0/AN0 A VIN- RA0/AN0 A CIS = 0 VIN- RVRAE3F/A+N3/ A VIN+ C1 C1OUT RVRAE3F/A+N3/ A CIS = 1 VIN+ C1 C1OUT RA4/T0CKI/C1OUT* RA1/AN1 A CIS = 0 VIN- RA1/AN1 D VIN- RVRAE2F/A-/CNV2/REFA CIS = 1 VIN+ C2 C2OUT RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) CVREF VREF-/CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs. DS39689F-page 244 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 21.2 Comparator Operation 21.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure21-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the the digital output. When the analog input at VIN+ is less comparator voltage reference module. This module is than the analog input VIN-, the output of the comparator described in more detail in Section22.0 “Comparator is a digital low level. When the analog input at VIN+ is Voltage Reference Module”. greater than the analog input VIN-, the output of the The internal reference is only available in the mode comparator is a digital high level. The shaded areas of where four inputs are multiplexed to two comparators the output of the comparator in Figure21-2 represent (CM<2:0>=110). In this mode, the internal voltage ref- the uncertainty, due to input offsets and response time. erence is applied to the VIN+ pin of both comparators. 21.3 Comparator Reference 21.4 Comparator Response Time Depending on the comparator operating mode, either Response time is the minimum time, after selecting a an external or internal voltage reference may be used. new reference voltage or input source, before the The analog signal present at VIN- is compared to the comparator output has a valid level. If the internal ref- signal at VIN+ and the digital output of the comparator erence is changed, the maximum delay of the internal is adjusted accordingly (Figure21-2). voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of FIGURE 21-2: SINGLE COMPARATOR the comparators should be used (see Section27.0 “Electrical Characteristics”). 21.5 Comparator Outputs VIN+ + Output The comparator outputs are read through the CMCON VIN- – register. These bits are read-only. The comparator outputs may also be directly output to the RA4 and RA5 I/O pins. When enabled, multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the VIN- comparators is related to the input offset voltage and the response time given in the specifications. VIN+ Figure21-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ Output disable for the RA4 and RA5 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<5:4>). 21.3.1 EXTERNAL REFERENCE SIGNAL Note1: When reading the Port register, all pins When external voltage references are used, the configured as analog inputs will read as a comparator module can be configured to have the ‘0’. Pins configured as digital inputs will comparators operate from the same or different convert an analog input according to the reference sources. However, threshold detector Schmitt Trigger input specification. applications may require the same reference. The 2: Analog levels on any pin defined as a reference signal must be between VSS and VDD and digital input may cause the input buffer to can be applied to either pin of the comparator(s). consume more current than is specified. © 2009 Microchip Technology Inc. DS39689F-page 245

PIC18F2221/2321/4221/4321 FAMILY FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port Pins P TI To RA4 or UL - RA5 pin M D Q Bus CxINV Data Read CMCON EN D Q Set CMIF bit EN CL From Other Reset Comparator 21.6 Comparator Interrupts 21.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The Each operational comparator will consume additional CMIF bit must be reset by clearing it. Since it is also current, as shown in the comparator specifications. To possible to write a ‘1’ to this register, a simulated minimize power consumption while in Sleep mode, turn interrupt may be initiated. off the comparators (CM<2:0>=111) before entering Both the CMIE bit (PIE2<6>) and the PEIE bit Sleep. If the device wakes up from Sleep, the contents (INTCON<6>) must be set to enable the interrupt. In of the CMCON register are not affected. addition, the GIE bit (INTCON<7>) must also be set. If 21.8 Effects of a Reset any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt A device Reset forces the CMCON register to its Reset condition occurs. state, causing the comparator modules to be turned off Note: If a change in the CMCON register (CM<2:0>=111). However, the input pins (RA0 (C1OUT or C2OUT) should occur when a through RA3) are configured as analog inputs by read operation is being executed (start of default on device Reset. The I/O configuration for these the Q2 cycle), then the CMIF (PIR2 pins is determined by the setting of the PCFG<3:0> bits register) interrupt flag may not get set. (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset The user, in the Interrupt Service Routine, can clear the time. interrupt in the following manner: a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. DS39689F-page 246 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 21.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10kΩ is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure21-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 21-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 57 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 57 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 58 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 58 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 58 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39689F-page 247

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 248 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 22.0 COMPARATOR VOLTAGE used is selected by the CVRR bit (CVRCON<5>). The REFERENCE MODULE primary difference between the ranges is the size of the steps selected by the CVREF selection bits The comparator voltage reference is a 16-tap resistor (CVR<3:0>), with one range offering finer resolution. ladder network that provides a selectable reference The equations used to calculate the output of the voltage. Although its primary purpose is to provide a comparator voltage reference are as follows: reference for the analog comparators, it may also be If CVRR = 1: used independently of them. CVREF = ((CVR<3:0>)/24) x CVRSRC A block diagram of the module is shown in Figure22-1. If CVRR = 0: The resistor ladder is segmented to provide two ranges CVREF = (CVRSRC x 1/4) + (((CVR<3:0>)/32) x of CVREF values and has a power-down function to CVRSRC) conserve power when the reference is not being used. The comparator reference supply voltage can come The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit 22.1 Configuring the Comparator (CVRCON<4>). Voltage Reference The settling time of the comparator voltage reference The voltage reference module is controlled through the must be considered when changing the CVREF CVRCON register (Register22-1). The comparator output (see Table27-3 in Section27.0 “Electrical voltage reference provides two ranges of output Characteristics”). voltage, each with 16 distinct levels. The range to be REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin Note1: CVROE overrides the TRISA<2> bit setting. bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0 ≤ (CVR<3:0>) ≤ 15) When CVRR = 1: CVREF = ((CVR<3:0>)/24) • (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) • (CVRSRC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39689F-page 249

PIC18F2221/2321/4221/4321 FAMILY FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 22.2 Voltage Reference Accuracy/Error 22.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA2 pin by clearing (Figure22-1) keep CVREF from approaching the bit, CVROE (CVRCON<6>) and selects the high-voltage reference source rails. The voltage reference is derived range by clearing bit, CVRR (CVRCON<5>). The CVR from the reference source; therefore, the CVREF output value select bits are also cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 22.5 Connection Considerations found in Section27.0 “Electrical Characteristics”. The voltage reference module operates independently 22.3 Operation During Sleep of the comparator module. The output of the reference generator may be connected to the RA2 pin if the When the device wakes up from Sleep through an CVROE bit is set. Enabling the voltage reference interrupt or a Watchdog Timer time-out, the contents of output onto RA2 when it is configured as a digital input the CVRCON register are not affected. To minimize will increase current consumption. Connecting RA2 as current consumption in Sleep mode, the voltage a digital output with CVRSS enabled will also increase reference should be disabled. current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure22-2 shows an example buffering technique. DS39689F-page 250 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF R(1) Module + Voltage RA2 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 57 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 57 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 58 Legend: Shaded cells are not used with the comparator voltage reference. Note 1: PORTA pins are enabled based on oscillator configuration. © 2009 Microchip Technology Inc. DS39689F-page 251

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 252 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 23.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register23-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned PIC18F2221/2321/4221/4321 family devices have a off” by the user under software control, which High/Low-Voltage Detect module (HLVD). This is a minimizes the current consumption for the device. programmable circuit that allows the user to specify both The block diagram for the HLVD module is shown in a device voltage trip point and the direction of change Figure23-1. from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. REGISTER 23-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note: See Table27-4 in Section27.0 “Electrical Characteristics” for the specifications. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown The module is enabled by setting the HLVDEN bit. The VDIRMAG bit determines the overall operation of Each time that the HLVD module is enabled, the the module. When VDIRMAG is cleared, the module circuitry requires some time to stabilize. The IRVST bit monitors for drops in VDD below a predetermined set is a read-only bit and is used to indicate when the circuit point. When the bit is set, the module monitors for rises is stable. The module can only generate an interrupt in VDD above the set point. after the circuit is stable and IRVST is set. © 2009 Microchip Technology Inc. DS39689F-page 253

PIC18F2221/2321/4221/4321 FAMILY 23.1 Operation The trip point voltage is software programmable to any one of 16 values. The trip point is selected by When the HLVD module is enabled, a comparator uses programming the HLVDL<3:0> bits (HLVDCON<3:0>). an internally generated reference voltage as the set The HLVD module has an additional feature that allows point. The set point is compared with the trip point, the user to supply the trip voltage to the module from an where each node in the resistor divider represents a external source. This mode is enabled when bits trip point voltage. The “trip point” voltage is the voltage HLVDL<3:0> are set to ‘1111’. In this state, the level at which the device detects a high or low-voltage comparator input is multiplexed from the external input event, depending on the configuration of the module. pin, HLVDIN. This gives users flexibility because it When the supply voltage is equal to the trip point, the allows them to configure the High/Low-Voltage Detect voltage tapped off of the resistor array is equal to the interrupt to occur at any voltage in the valid operating internal reference voltage generated by the voltage range. reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. FIGURE 23-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDIN HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage BOREN Reference DS39689F-page 254 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 23.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only module: need to be enabled for short periods where the voltage 1. Disable the module by clearing the HLVDEN bit is checked. After doing the check, the HLVD module (HLVDCON<4>). may be disabled. 2. Write the value to the HLVDL<3:0> bits that selects the desired HLVD trip point. 23.4 HLVD Start-up Time 3. Set the VDIRMAG bit to detect high voltage The internal reference voltage of the HLVD module, (VDIRMAG = 1) or low voltage (VDIRMAG = 0). specified in electrical specification parameter D420, 4. Enable the HLVD module by setting the may be used by other internal circuitry, such as the HLVDEN bit. Programmable Brown-out Reset. If the HLVD or other 5. Clear the HLVD interrupt flag (PIR2<2>), which circuits using the voltage reference are disabled to may have been set from a previous interrupt. lower the device’s current consumption, the reference 6. Enable the HLVD interrupt if interrupts are voltage circuit will require time to become stable before desired by setting the HLVDIE and GIE bits a low or high-voltage condition can be reliably (PIE<2> and INTCON<7>). An interrupt will not detected. This start-up time, TIRVST, is an interval that be generated until the IRVST bit is set. is independent of device clock speed. It is specified in electrical specification parameter 36. 23.3 Current Consumption The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For When the module is enabled, the HLVD comparator this reason, brief excursions beyond the set point may and voltage divider are enabled and will consume static not be detected during this interval. Refer to current. The total current consumption, when enabled, Figure23-2 or Figure23-3. is specified in electrical specification parameter D022B. FIGURE 23-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VDD VLVD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists © 2009 Microchip Technology Inc. DS39689F-page 255

PIC18F2221/2321/4221/4321 FAMILY FIGURE 23-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 23.5 Applications FIGURE 23-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, the ability to detect a drop below or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect a Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An VA attach would indicate a high-voltage detect from, for VB example, 3.3V to 5V (the voltage on USB) and vice e g versa for a detach. This feature could save a design a a few extra components and an attach signal (input pin). olt V For general battery applications, Figure23-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA. The interrupt could cause the execution of an ISR, Time TA TB which would allow the application to perform “house- keeping tasks” and perform a controlled shutdown Legend: VA = HLVD trip point before the device voltage exits the valid operating VB = Minimum valid device range at TB. The HLVD, thus, would give the applica- operating voltage tion a time window, represented by the difference between TA and TB, to safely exit. DS39689F-page 256 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 23.6 Operation During Sleep 23.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 23-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 56 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 58 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 58 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. © 2009 Microchip Technology Inc. DS39689F-page 257

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 258 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 24.0 SPECIAL FEATURES OF THE The inclusion of an internal RC oscillator also provides CPU the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for PIC18F2221/2321/4221/4321 family devices include background monitoring of the peripheral clock and several features intended to maximize reliability and automatic switchover in the event of its failure. Two- minimize cost through elimination of external Speed Start-up enables code to be executed almost components. These are: immediately on start-up, while the primary clock source completes its start-up delays. • Oscillator Selection All of these features are enabled and configured by • Resets: setting the appropriate Configuration register bits. - Power-on Reset (POR) - Power-up Timer (PWRT) 24.1 Configuration Bits - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various • Interrupts device configurations. These bits are mapped starting • Watchdog Timer (WDT) at program memory location 300000h. • Fail-Safe Clock Monitor The user will note that address 300000h is beyond the • Two-Speed Start-up user program memory space. In fact, it belongs to the • Code Protection configuration memory space (300000h-3FFFFFh), which • ID Locations can only be accessed using table reads and table writes. • In-Circuit Serial Programming Programming the Configuration registers is done in a The oscillator can be configured for the application manner similar to programming the Flash memory. The depending on frequency, power, accuracy and cost. All WR bit in the EECON1 register starts a self-timed write of the options are discussed in detail in Section3.0 to the Configuration register. In normal operation mode, “Oscillator Configurations”. a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data A complete discussion of device Resets and interrupts for the Configuration register write. Setting the WR bit is available in previous sections of this data sheet. starts a long write to the Configuration register. The In addition to their Power-up and Oscillator Start-up Configuration registers are written a byte at a time. To Timers provided for Resets, PIC18F2221/2321/4221/ write or erase a configuration cell, a TBLWT instruction 4321 family devices have a Watchdog Timer, which is can write a ‘1’ or a ‘0’ into the cell. For additional details either permanently enabled via the Configuration bits on Flash programming, refer to Section7.5 “Writing or software controlled (if configured as disabled). to Flash Program Memory”. TABLE 24-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011 300006h CONFIG4L DEBUG XINST BBSIZ1 BBSIZ0 r LVP — STVREN 1000 01-1 300008h CONFIG5L — — — — — — CP1 CP0 ---- --11 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — — — WRT1 WRT0 ---- --11 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 ---- --11 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(1) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2) 3FFFFFh DEVID2(1) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, maintain as ‘0’. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F2221/4221 devices; maintain these bits set. 2: See Register24-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. © 2009 Microchip Technology Inc. DS39689F-page 259

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39689F-page 260 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2) bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = Minimum setting . . . 00 = Maximum setting bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note1: See Section 27.1 “DC Characteristics” for the specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2009 Microchip Technology Inc. DS39689F-page 261

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39689F-page 262 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1 MCLRE — — — — LPT1OSC PBADEN CCP2MX bit 7 bit 0 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Read as ‘0’ bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 CCP2MX: CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2009 Microchip Technology Inc. DS39689F-page 263

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 U-0 U-0 r-0 R/P-1 U-0 R/P-1 DEBUG XINST BBSIZ1 BBSIZ0 — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5-4 BBSIZ<1:0>: Boot Block Size Select bits PIC18F4221/4321 Devices: 1x = 1024 Words 01 = 512 Words 00 = 256 Words PIC18F2221/2321 Devices: 1x = 512 Words x1 = 512 Words 00 = 256 Words bit 3 Reserved: Maintain as ‘0’ bit 2 LVP: Single-Supply ICSP™ Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: r = Reserved bit, program as ‘0’ R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39689F-page 264 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — CP1 CP0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 CP1: Code Protection bit 1 = Block 1 not code-protected(1) 0 = Block 1 code-protected(1) bit 0 CP0: Code Protection bit 1 = Block 0 not code-protected(1) 0 = Block 0 code-protected(1) Note1: See Figure24-5 for variable block boundaries. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block not code-protected(1) 0 = Boot block code-protected(1) bit 5-0 Unimplemented: Read as ‘0’ Note1: See Figure24-5 for variable block boundaries. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2009 Microchip Technology Inc. DS39689F-page 265

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — WRT1 WRT0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 WRT1: Write Protection bit 1 = Block 1 not write-protected(1) 0 = Block 1 write-protected(1) bit 0 WRT0: Write Protection bit 1 = Block 0 not write-protected(1) 0 = Block 0 write-protected(1) Note1: See Figure24-5 for variable block boundaries. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block not write-protected(2) 0 = Boot block write-protected(2) bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode. 2: See Figure24-5 for block boundaries. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39689F-page 266 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — EBTR1 EBTR0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 EBTR1: Table Read Protection bit 1 = Block 1 not protected from table reads executed in other blocks(1) 0 = Block 1 protected from table reads executed in other blocks(1) bit 0 EBTR0: Table Read Protection bit 1 = Block 0 not protected from table reads executed in other blocks(1) 0 = Block 0 protected from table reads executed in other blocks(1) Note1: See Figure24-5 for variable block boundaries. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block not protected from table reads executed in other blocks(1) 0 = Boot block protected from table reads executed in other blocks(1) bit 5-0 Unimplemented: Read as ‘0’ Note1: See Figure24-5 for variable block boundaries. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2009 Microchip Technology Inc. DS39689F-page 267

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2221/2321/4221/4321 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV<2:0>: Device ID bits 000 = PIC18F4321 010 = PIC18F4221 001 = PIC18F2321 011 = PIC18F2221 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2221/2321/4221/4321 DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV<10:3>: Device ID bits These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. 0010 0001 = PIC18F2221/2321/4221/4321 devices Note: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39689F-page 268 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 24.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For PIC18F2221/2321/4221/4321 family devices, the when executed. WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal 2: Changing the setting of the IRCF bits WDT period is 4ms and has the same stability as the (OSCCON<6:4>) clears the WDT and INTRC oscillator. postscaler counts. The 4ms period of the WDT is multiplied by a 16-bit 3: When a CLRWDT instruction is executed, postscaler. Any output of the WDT postscaler is the postscaler count will be cleared. selected by a multiplexer, controlled by bits in Configu- ration Register 2H. Available periods range from 4ms 24.2.1 CONTROL REGISTER to 131.072 seconds (2.18 minutes). The WDT and Register24-14 shows the WDTCON register. This is a postscaler are cleared when any of the following events readable and writable register which contains a control occur: a SLEEP or CLRWDT instruction is executed, the bit that allows software to override the WDT enable IRCF bits (OSCCON<6:4>) are changed or a clock Configuration bit, but only if the Configuration bit has failure has occurred. disabled the WDT. FIGURE 24-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT WDTEN WDT Counter INTRC Source ÷128 Wake-up from Power-Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets 4 WDTPS<3:0> Sleep © 2009 Microchip Technology Inc. DS39689F-page 269

PIC18F2221/2321/4221/4321 FAMILY REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note1: This bit has no effect if the Configuration bit, WDTEN, is enabled. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page RCON IPEN SBOREN(1) — RI TO PD POR BOR 56 WDTCON — — — — — — — SWDTEN 56 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. DS39689F-page 270 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 24.3 Two-Speed Start-up In all other power-managed modes, Two-Speed Start- up is not used. The device will be clocked by the The Two-Speed Start-up feature helps to minimize the currently selected clock source until the primary clock latency period from oscillator start-up to code execution source becomes available. The setting of the IESO bit by allowing the microcontroller to use the INTOSC is ignored. oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO 24.3.1 SPECIAL CONSIDERATIONS FOR Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTOSC oscillator in Two-Speed Start- primary oscillator mode is LP, XT, HS or HSPLL up, the device still obeys the normal command (crystal-based modes). Other sources do not require sequences for entering power-managed modes, an OST start-up delay; for these, Two-Speed Start-up including multiple SLEEP instructions (refer to should be disabled. Section4.1.4 “Multiple Sleep Commands”). In When enabled, Resets and wake-ups from Sleep mode practice, this means that user code can change the cause the device to configure itself to run from the SCS<1:0> bit settings or issue SLEEP instructions internal oscillator block as the clock source, following before the OST times out. This would allow an applica- the time-out of the Power-up Timer after a Power-on tion to briefly wake-up, perform routine “housekeeping” Reset is enabled. This allows almost immediate code tasks and return to Sleep before the device starts to execution while the primary oscillator starts and the operate from the primary oscillator. OST is running. Once the OST times out, the device User code can also check if the primary clock source is automatically switches to PRI_RUN mode. currently providing the device clocking by checking the To use a higher clock speed on wake-up, the INTOSC status of the OSTS bit (OSCCON<3>). If the bit is set, or postscaler clock sources can be selected to provide the primary oscillator is providing the clock. Otherwise, a higher clock speed by setting bits, IRCF<2:0>, the internal oscillator block is providing the clock during immediately after Reset. For wake-ups from Sleep, the wake-up from Reset or Sleep mode. INTOSC or postscaler clock sources can be selected by setting the IRCF<2:0> bits prior to entering Sleep mode. FIGURE 24-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake from Interrupt Event OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. © 2009 Microchip Technology Inc. DS39689F-page 271

PIC18F2221/2321/4221/4321 FAMILY 24.4 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits, IRCF<2:0>, microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting the IRCF<2:0> bits prior to entering Sleep function is enabled by setting the FCMEN Configuration mode. bit. The FSCM will detect failures of the primary or second- When FSCM is enabled, the INTRC oscillator runs at ary clock sources only. If the internal oscillator block all times to monitor clocks to peripherals and provide a fails, no failure would be detected, nor would any action backup clock in the event of a clock failure. Clock be possible. monitoring (shown in Figure24-3) is accomplished by creating a sample clock signal, which is the INTRC 24.4.1 FSCM AND THE WATCHDOG TIMER output divided by 64. This allows ample time between Both the FSCM and the WDT are clocked by the FSCM sample clocks for a peripheral clock edge to INTRC oscillator. Since the WDT operates with a occur. The peripheral device clock and the sample separate divider and counter, disabling the WDT has clock are presented as inputs to the Clock Monitor latch no effect on the operation of the INTRC oscillator when (CM). The CM is set on the falling edge of the device the FSCM is enabled. clock source, but cleared on the rising edge of the sample clock. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. FIGURE 24-3: FSCM BLOCK DIAGRAM Depending on the frequency selected by the IRCF<2:0> bits, this may mean a substantial change in Clock Monitor the speed of code execution. If the WDT is enabled Latch (CM) (edge-triggered) with a small prescale value, a decrease in clock speed Peripheral allows a WDT time-out to occur and a subsequent S Q Clock device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and INTRC decreasing the likelihood of an erroneous time-out. ÷ 64 C Q Source 24.4.2 EXITING FAIL-SAFE OPERATION (32 μs) 488 Hz (2.048 ms) The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Clock Reset, the controller starts the primary clock source Failure specified in Configuration Register 1H (with any Detected required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The Clock failure is tested for on the falling edge of the INTOSC multiplexer provides the device clock until the sample clock. If a sample clock falling edge occurs primary clock source becomes ready (similar to a Two- while CM is still set, a clock failure has been detected Speed Start-up). The clock source is then switched to (Figure24-4). This causes the following: the primary clock (indicated by the OSTS bit in the • the FSCM generates an oscillator fail interrupt by OSCCON register becoming set). The Fail-Safe Clock setting bit, OSCFIF (PIR2<7>); Monitor then resumes monitoring the peripheral clock. • the device clock source is switched to the internal The primary clock source may never become ready oscillator block (OSCCON is not updated to show during start-up. In this case, operation is clocked by the the current clock source – this is the fail-safe INTOSC multiplexer. The OSCCON register will remain condition); and in its Reset state until a power-managed mode is • the WDT is reset. entered. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section4.1.4 “Multiple Sleep Commands” and Section24.3.1 “Special Considerations for Using Two-Speed Start-up” for more details. DS39689F-page 272 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 24-4: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 24.4.3 FSCM INTERRUPTS IN 24.4.4 POR OR WAKE FROM SLEEP POWER-MANAGED MODES The FSCM is designed to detect oscillator failure at any By entering a power-managed mode, the clock point after the device has exited Power-on Reset multiplexer selects the clock source selected by the (POR) or low-power Sleep mode. When the primary OSCCON register. Fail-Safe Monitoring of the power- device clock is EC, RC or INTRC modes, monitoring managed clock source resumes in the power-managed can begin immediately following these events. mode. For oscillator modes involving a crystal or resonator If an oscillator failure occurs during power-managed (HS, HSPLL, LP or XT), the situation is somewhat operation, the subsequent events depend on whether different. Since the oscillator may require a start-up or not the oscillator failure interrupt is enabled. If time considerably longer than the FCSM sample clock enabled (OSCFIF=1), code execution will be clocked time, a false clock failure may be detected. To prevent by the INTOSC multiplexer. An automatic transition this, the internal oscillator block is automatically config- back to the failed clock source will not occur. ured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed If the interrupt is disabled, subsequent interrupts while out). This is identical to Two-Speed Start-up mode. in Idle mode will cause the CPU to begin executing Once the primary clock is stable, the INTRC returns to instructions while being clocked by the INTOSC its role as the FSCM source. source. Note: The same logic that prevents false oscilla- tor failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator’s failure to start at all follow- ing these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section24.3.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power- managed mode is selected, the primary clock is disabled. © 2009 Microchip Technology Inc. DS39689F-page 273

PIC18F2221/2321/4221/4321 FAMILY 24.5 Program Verification and Each of the three blocks has three code protection bits Code Protection associated with them. They are: • Code-Protect bit (CPn) The overall structure of the code protection on the • Write-Protect bit (WRTn) PIC18 Flash devices differs significantly from other PIC® devices. • External Block Table Read bit (EBTRn) The user program memory is divided into three blocks. Figure24-5 shows the program memory organization One of these is a boot block of variable size. The for 4 and 8-Kbyte devices and the specific code remainder of the memory is divided into two blocks on protection bit associated with each block. The actual binary boundaries. locations of the bits are summarized in Table24-3. FIGURE 24-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2221/2321/4221/4321 FAMILY DEVICES Address Block Code Protection MEMORY SIZE/DEVICE Range Controlled By: 8Kbytes 4Kbytes (PIC18FX321) (PIC18FX221) BBSIZ<1:0> 11/10 01 00 11/10/01 00 000000h Boot Block Boot Block CPB, WRTB, EBTRB Boot Block 256 words Boot Block 256 words 0001FFh 512 words 512 words 000200h Boot Block 0003FFh 1K word Block 0 000400h Block 0 0.75K words 0.5K words CP0, WRT0, EBTR0 0007FFh Block 0 000800h Block 0 1.75K words 1.5K words Block 0 Block 1 Block 1 1K word 1K word 1K word 000FFFh 001000h CP1, WRT1, EBTR1 Block 1 Block 1 Block 1 2K words 2K words 2K words Unimplemented Reads all ‘0’s 001FFFh Unimplemented 002000h (Unimplemented Memory Reads all ‘0’s Space) 1FFFFFh DS39689F-page 274 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — — — CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — — — WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. 24.5.1 PROGRAM MEMORY A table read instruction that executes from a location CODE PROTECTION outside of that block is not allowed to read and will result in reading ‘0’s. Figures24-6 through24-8 illustrate table The program memory may be read to or written from write and table read protection. any location using the table read and table write instructions. The device ID may be read with table Note: Code protection bits may only be written to reads. The Configuration registers may be read and a ‘0’ from a ‘1’ state. It is not possible to written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full In normal execution mode, the CPn bits have no direct chip erase or block erase function. The full effect. CPn bits inhibit external reads and writes. A chip erase and block erase functions can block of user memory may be protected from table only be initiated via ICSP operation or an writes if the WRTn Configuration bit is ‘0’. The EBTRn external programmer. bits control table reads. For a block of user memory with the EBTRn bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. FIGURE 24-6: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory(1) Configuration Bit Settings Boot Block WRTB, EBTRB = 11 TBLPTR = 0008FFh Block 0 WRT0, EBTR0 = 01 PC = 003FFEh TBLWT* Block 1 WRT1, EBTR1 = 11 PC = 00BFFEh TBLWT* Results:All table writes disabled to Blockn whenever WRTn = 0. Note1: See Figure24-5 for block boundaries. © 2009 Microchip Technology Inc. DS39689F-page 275

PIC18F2221/2321/4221/4321 FAMILY FIGURE 24-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory(1) Configuration Bit Settings Boot Block WRTB, EBTRB = 11 TBLPTR = 0008FFh Block 0 WRT0, EBTR0 = 10 PC = 007FFEh Block 1 WRT1, EBTR1 = 11 TBLRD* Results:All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. Note1: See Figure24-5 for block boundaries. FIGURE 24-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory(1) Configuration Bit Settings Boot Block WRTB, EBTRB = 11 TBLPTR = 0008FFh Block 0 WRT0, EBTR0 = 10 PC = 003FFEh TBLRD* Block 1 WRT1, EBTR1 = 11 Results:Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. Note1: See Figure24-5 for block boundaries. DS39689F-page 276 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 24.5.2 DATA EEPROM To use the In-Circuit Debugger function of the micro- CODE PROTECTION controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP/RE3, VDD, The entire data EEPROM is protected from external VSS, RB7 and RB6. This will interface to the In-Circuit reads and writes by two bits: CPD and WRTD. CPD Debugger module available from Microchip or one of inhibits external reads and writes of data EEPROM. the third party development tool companies. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM 24.9 Single-Supply ICSP Programming under normal operation, regardless of the protection bit settings. The LVP Configuration bit enables Single-Supply ICSP Programming (formerly known as Low-Voltage ICSP 24.5.3 CONFIGURATION REGISTER Programming or LVP). When Single-Supply Program- PROTECTION ming is enabled, the microcontroller can be programmed The Configuration registers can be write-protected. without requiring high voltage being applied to the The WRTC bit controls protection of the Configuration MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then registers. In normal execution mode, the WRTC bit is dedicated to controlling Program mode entry and is not readable only. WRTC can only be written via ICSP available as a general purpose I/O pin. operation or an external programmer. While programming, using Single-Supply Program- ming, VDD is applied to the MCLR/VPP/RE3 pin as in 24.6 ID Locations normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store Note1: High-voltage programming is always checksum or other code identification numbers. These available, regardless of the state of the locations are both readable and writable during normal LVP bit or the PGM pin, by applying VIHH execution through the TBLRD and TBLWT instructions to the MCLR pin. or during program/verify. The ID locations can be read 2: By default, Single-Supply ICSP Program- when the device is code-protected. ming is enabled in unprogrammed devices (as supplied from Microchip) and 24.7 In-Circuit Serial Programming erased devices. PIC18F2221/2321/4221/4321 family microcontrollers 3: When Single-Supply ICSP Programming can be serially programmed while in the end applica- is enabled, the RB5 pin can no longer be tion circuit. This is simply done with two lines for clock used as a general purpose I/O pin. and data and three other lines for power, ground and 4: When LVP is enabled, externally pull the the programming voltage. This allows customers to PGM pin to VSS to allow normal program manufacture boards with unprogrammed devices and execution. then program the microcontroller just before shipping If Single-Supply ICSP Programming mode will not be the product. This also allows the most recent firmware used, the LVP bit can be cleared. RB5/KBI1/PGM then or a custom firmware to be programmed. becomes available as the digital I/O pin, RB5. The LVP bit may be set or cleared only when using standard 24.8 In-Circuit Debugger high-voltage programming (VIHH applied to the MCLR/ When the DEBUG Configuration bit is programmed to VPP/RE3 pin). Once LVP has been disabled, only the a ‘0’, the In-Circuit Debugger functionality is enabled. standard high-voltage programming is available and This function allows simple debugging functions when must be used to program the device. used with MPLAB® IDE. When the microcontroller has Memory that is not code-protected can be erased using this feature enabled, some resources are not available either a block erase, or erased row by row, then written for general use. Table24-4 shows which resources are at any specified VDD. If code-protected memory is to be required by the background debugger. erased, a block erase is required. If a block erase is to be performed when using Low-Voltage ICSP TABLE 24-4: DEBUGGER RESOURCES Programming, the device must be supplied with VDD of I/O Pins: RB6, RB7 4.5V to 5.5V. Stack: 2 levels Program Memory: 512 bytes Data Memory: 10 bytes © 2009 Microchip Technology Inc. DS39689F-page 277

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 278 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 25.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: PIC18F2221/2321/4221/4321 family devices incorpo- • A literal value to be loaded into a file register rate the standard set of 75 PIC18 core instructions, as (specified by ‘k’) well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a • The desired FSR register to load the literal value software stack. The extended set is discussed later in into (specified by ‘f’) this section. • No operand required (specified by ‘—’) 25.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations program counter is changed as a result of the • Control operations instruction. In these cases, the execution takes two The PIC18 instruction set summary in Table25-2 lists instruction cycles, with the additional instruction byte-oriented, bit-oriented, literal and control cycle(s) executed as a NOP. operations. Table25-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1μs. If a conditional test is 3. The accessed memory (specified by ‘a’) true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 μs. The file register designator ‘f’ specifies which file Two-word branch instructions (if true) would take 3 μs. register is to be used by the instruction. The destination Figure25-1 shows the general formats that the designator ‘d’ specifies where the result of the instructions can have. All examples use the convention operation is to be placed. If ‘d’ is zero, the result is ‘nnh’ to represent a hexadecimal number. placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table25-2, lists the standard instructions recognized by the All bit-oriented instructions have three operands: Microchip MPASM™ Assembler. 1. The file register (specified by ‘f’) Section25.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. © 2009 Microchip Technology Inc. DS39689F-page 279

PIC18F2221/2321/4221/4321 FAMILY TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User-defined term (font is Courier New). DS39689F-page 280 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2009 Microchip Technology Inc. DS39689F-page 281

PIC18F2221/2321/4221/4321 FAMILY TABLE 25-2: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da0 ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 0da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st Word 2 1100 ffff ffff ffff None fd (destination) 2nd Word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39689F-page 282 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine 1st Word 2 1110 110s kkkk kkkk None 2nd Word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st Word 2 1110 1111 kkkk kkkk None 2nd Word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. © 2009 Microchip Technology Inc. DS39689F-page 283

PIC18F2221/2321/4221/4321 FAMILY TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd Word 2 1110 1110 00ff kkkk None to FSR(f) 1st Word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39689F-page 284 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) + k → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: ADDLW 15h Section25.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = 10h After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). © 2009 Microchip Technology Inc. DS39689F-page 285

PIC18F2221/2321/4221/4321 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Decode Read literal Process Write to W If ‘a’ is ‘0’ and the extended instruction ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 05Fh mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = A3h Literal Offset Mode” for details. After Instruction Words: 1 W = 03h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39689F-page 286 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: If Carry bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ‘1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC+2+2n. This instruction is then a GPR bank (default). two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section25.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to Words: 1 ‘n’ Data PC Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39689F-page 287

PIC18F2221/2321/4221/4321 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: If Negative bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank (default). incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC+2+2n. This instruction is then a in Indexed Literal Offset Addressing two-cycle instruction. mode whenever f ≤ 95 (5Fh). See Words: 1 Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1(2) Literal Offset Mode” for details. Q Cycle Activity: Words: 1 If Jump: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to Q Cycle Activity: ‘n’ Data PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No Before Instruction ‘n’ Data operation FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39689F-page 288 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: If Carry bit is ‘0’, Operation: If Negative bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39689F-page 289

PIC18F2221/2321/4221/4321 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: If Overflow bit is ‘0’, Operation: If Zero bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39689F-page 290 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 Operation: (PC) + 2 + 2n → PC a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next instruction, Description: Bit ‘b’ in register ‘f’ is set. the new address will be PC+2+2n. This If ‘a’ is ‘0’, the Access Bank is selected. instruction is a two-cycle instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section25.2.3 “Byte-Oriented and Decode Read literal Process Write to Bit-Oriented Instructions in Indexed ‘n’ Data PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah © 2009 Microchip Technology Inc. DS39689F-page 291

PIC18F2221/2321/4221/4321 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in set is enabled, this instruction operates Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and See Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39689F-page 292 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: If Overflow bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank (default). instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC+2+2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to ‘n’ Data PC Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39689F-page 293

PIC18F2221/2321/4221/4321 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: If Zero bit is ‘1’, (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>; Status Affected: None if s = 1, Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS, will branch. (BSR) → BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk PC+2+2n. This instruction is then a 19 8 two-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and Q Cycle Activity: BSR registers are also pushed into their If Jump: respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs (default). Then, the Decode Read literal Process Write to 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data PC CALL is a two-cycle instruction. No No No No Words: 2 operation operation operation operation If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal PUSH PC to Read literal ‘k’<7:0>, stack ‘k’<19:8>, Example: HERE BZ Jump Write to PC No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction If Zero = 1; Example: HERE CALL THERE, 1 PC = address (Jump) If Zero = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39689F-page 294 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f, 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the If ‘a’ is ‘1’, the BSR is used to select the postscaler of the WDT. Status bits, TO GPR bank (default). and PD, are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section25.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Decode No Process No operation Data operation Words: 1 Cycles: 1 Example: CLRWDT Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WDT Counter = ? Decode Read Process Write After Instruction register ‘f’ Data register ‘f’ WDT Counter = 00h WDT Postscaler = 0 TO = 1 Example: CLRF FLAG_REG, 1 PD = 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h © 2009 Microchip Technology Inc. DS39689F-page 295

PIC18F2221/2321/4221/4321 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f) → dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank (default). instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank (default). mode whenever f ≤ 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section25.2.3 “Byte-Oriented and set is enabled, this instruction operates Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode” for details. mode whenever f ≤ 95 (5Fh). See Words: 1 Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: 3 cycles if skip and followed register ‘f’ Data destination by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h Q1 Q2 Q3 Q4 W = ECh No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39689F-page 296 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory Description: Compares the contents of data memory location ‘f’ to the contents of the W by location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the , If the contents of ‘f’ are less than the contents of WREG then the fetched contents of W, then the fetched instruction is discarded and a NOP is instruction is discarded and a NOP is executed instead, making this a executed instead, making this a two-cycle instruction. two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Note: 3 cycles if skip and followed Section25.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process No Cycles: 1(2) Note: 3 cycles if skip and followed register ‘f’ Data operation by a 2-word instruction. If skip: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No Decode Read Process No operation operation operation operation register ‘f’ Data operation If skip and followed by 2-word instruction: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; Before Instruction PC = Address (LESS) PC = Address (HERE) If REG ≥ W; W = ? PC = Address (NLESS) After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2009 Microchip Technology Inc. DS39689F-page 297

PIC18F2221/2321/4221/4321 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then, a ∈ [0,1] (W<3:0>) + 6 → W<3:0>; else, Operation: (f) – 1 → dest ( W<3:0>) → W<3:0> Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then, Encoding: 0000 01da ffff ffff ( W<7:4>) + 6 + DC → W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the else, result is stored in W. If ‘d’ is ‘1’, the (W<7:4>) + DC → W<7:4> result is stored back in register ‘f’ Status Affected: C (default). If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the Description: DAW adjusts the eight-bit value in W GPR bank (default). resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Example 1: Decode Read Process Write to DAW register ‘f’ Data destination Before Instruction W = A5h Example: DECF CNT, 1, 0 C = 0 DC = 0 Before Instruction After Instruction CNT = 01h Z = 0 W = 05h After Instruction C = 1 DC = 0 CNT = 00h Z = 1 Example 2: Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39689F-page 298 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, If the result is not ‘0’, the next which is already fetched, is discarded instruction, which is already fetched, is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section25.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Bit-Oriented Instructions in Indexed Section25.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1 PC = Address (CONTINUE) If TEMP = 0; If CNT ≠ 0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP ≠ 0; PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39689F-page 299

PIC18F2221/2321/4221/4321 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k → PC<20:1> a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire incremented. If ‘d’ is ‘0’, the result is 2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is value ‘k’ is loaded into PC<20:1>. placed back in register ‘f’ (default). GOTO is always a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 2 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section25.2.3 “Byte-Oriented and Decode Read literal No Read literal Bit-Oriented Instructions in Indexed ‘k’<7:0>, operation ‘k’<19:8>, Literal Offset Mode” for details. Write to PC Words: 1 No No No No operation operation operation operation Cycles: 1 Q Cycle Activity: Example: GOTO THERE Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to PC = Address (THERE) register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39689F-page 300 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result ≠ 0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is not ‘0’, the next If the result is ‘0’, the next instruction, instruction, which is already fetched, is which is already fetched, is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2009 Microchip Technology Inc. DS39689F-page 301

PIC18F2221/2321/4221/4321 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) .OR. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: IORLW 35h mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 9Ah Literal Offset Mode” for details. After Instruction Words: 1 W = BFh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39689F-page 302 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] a ∈ [0,1] Operation: k → FSRf Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to File Select Register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read literal Process Write If ‘a’ is ‘1’, the BSR is used to select the ‘k’ MSB Data literal ‘k’ GPR bank (default). MSB to If ‘a’ is ‘0’ and the extended instruction FSRfH set is enabled, this instruction operates Decode Read literal Process Write literal in Indexed Literal Offset Addressing ‘k’ LSB Data ‘k’ to FSRfL mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Example: LFSR 2, 3ABh Literal Offset Mode” for details. After Instruction Words: 1 FSR2H = 03h FSR2L = ABh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h © 2009 Microchip Technology Inc. DS39689F-page 303

PIC18F2221/2321/4221/4321 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ f ≤ 4095 d Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value of 2nd word (destin.) 1111 ffff ffff ffffd BSR<7:4> always remains ‘0’, regardless Description: The contents of source register ‘f ’ are of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Either source or destination can be W Decode Read Process Write literal (a useful special situation). literal ‘k’ Data ‘k’ to BSR MOVFF is particularly useful for transferring a data memory location to a Example: MOVLB 5 peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h The MOVFF instruction cannot use the After Instruction PCL, TOSU, TOSH or TOSL as the BSR Register = 05h destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39689F-page 304 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: k → W Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 5Ah Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh © 2009 Microchip Technology Inc. DS39689F-page 305

PIC18F2221/2321/4221/4321 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x k → PRODH:PRODL Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in the PRODH:PRODL register register file location ‘f’. The 16-bit pair. PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the None of the Status flags are affected. high byte. Both W and ‘f’ are Note that neither Overflow nor Carry is unchanged. possible in this operation. A Zero result None of the Status flags are affected. is possible but not detected. Note that neither Overflow nor Carry is possible in this operation. A Zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write set is enabled, this instruction literal ‘k’ Data registers operates in Indexed Literal Offset PRODH: Addressing mode whenever PRODL f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Bit-Oriented Example: MULLW 0C4h Instructions in Indexed Literal Offset Mode” for details. Before Instruction Words: 1 W = E2h PRODH = ? Cycles: 1 PRODL = ? Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = E2h PRODH = ADh Decode Read Process Write PRODL = 08h register ‘f’ Data registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39689F-page 306 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode No No No in Indexed Literal Offset Addressing operation operation operation mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Example: Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] © 2009 Microchip Technology Inc. DS39689F-page 307

PIC18F2221/2321/4221/4321 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC+2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39689F-page 308 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n → PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC+2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC+2+2n. This instruction is a two-cycle instruction. Decode Start No No Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to Flags* = Reset Value ‘n’ Data PC PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) © 2009 Microchip Technology Inc. DS39689F-page 309

PIC18F2221/2321/4221/4321 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL; (TOS) → PC, if s = 1, PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS, are loaded into their corresponding registers, W, Decode Read Process POP PC STATUS and BSR. If ‘s’ = 0, no update literal ‘k’ Data from stack, of these registers occurs (default). Write to W No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS W = WS RETLW kn ; End of table BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS39689F-page 310 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (TOS) → PC; a ∈ [0,1] if s = 1, (WS) → W, Operation: (f<n>) → dest<n + 1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’ (default). registers, WS, STATUSS and BSRS, If ‘a’ is ‘0’, the Access Bank is are loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, STATUS and BSR. If select the GPR bank (default). ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs (default). set is enabled, this instruction operates in Indexed Literal Offset Words: 1 Addressing mode whenever Cycles: 2 f ≤ 95 (5Fh). See Section25.2.3 Q Cycle Activity: “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Q1 Q2 Q3 Q4 Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2009 Microchip Technology Inc. DS39689F-page 311

PIC18F2221/2321/4221/4321 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default). GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank (default). in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates Section25.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See Literal Offset Mode” for details. Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39689F-page 312 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n – 1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default). placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See per the BSR value (default). Section25.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG, 1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2009 Microchip Technology Inc. DS39689F-page 313

PIC18F2221/2321/4221/4321 FAMILY SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: 00h → WDT, a ∈ [0,1] 0 → WDT postscaler, 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. with the oscillator stopped. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section25.2.3 “Byte-Oriented and Decode No Process Go to Bit-Oriented Instructions in Indexed operation Data Sleep Literal Offset Mode” for details. Words: 1 Example: SLEEP Cycles: 1 Before Instruction Q Cycle Activity: TO = ? PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1† register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 Before Instruction † If WDT causes wake-up, this bit is cleared. REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39689F-page 314 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k – (W) → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the Q Cycle Activity: result is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is Decode Read Process Write to W selected. If ‘a’ is ‘1’, the BSR is used literal ‘k’ Data to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction Before Instruction operates in Indexed Literal Offset W = 01h Addressing mode whenever C = ? f ≤ 95 (5Fh). See Section25.2.3 After Instruction “Byte-Oriented and Bit-Oriented W = 01h C = 1 ; result is positive Instructions in Indexed Literal Offset Z = 0 Mode” for details. N = 0 Words: 1 Example 2: SUBLW 02h Cycles: 1 Before Instruction W = 02h Q Cycle Activity: C = ? Q1 Q2 Q3 Q4 After Instruction W = 00h Decode Read Process Write to C = 1 ; result is zero register ‘f’ Data destination Z = 1 N = 0 Example 1: SUBWF REG, 1, 0 Example 3: SUBLW 02h Before Instruction REG = 3 Before Instruction W = 2 W = 03h C = ? C = ? After Instruction After Instruction REG = 1 W = FFh ; (2’s complement) W = 2 C = 0 ; result is negative C = 1 ; result is positive Z = 0 Z = 0 N = 1 N = 0 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2009 Microchip Technology Inc. DS39689F-page 315

PIC18F2221/2321/4221/4321 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement Description: The upper and lower nibbles of register method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) C = 1 REG = 35h Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39689F-page 316 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR)) → TABLAT, MEMORY (00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR)) → TABLAT, TBLPTR = 00A357h (TBLPTR) + 1 → TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, Before Instruction (TBLPTR) – 1 → TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY (01A357h) = 12h (TBLPTR) + 1 → TBLPTR, MEMORY (01A358h) = 34h (Prog Mem (TBLPTR)) → TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT) © 2009 Microchip Technology Inc. DS39689F-page 317

PIC18F2221/2321/4221/4321 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT) → Holding Register, TBLPTR = 00A356h TBLPTR – No Change; HOLDING REGISTER (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT) → Holding Register, TABLAT = 55h (TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT) → Holding Register, (00A356h) = 55h (TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*; if TBLWT+*, (TBLPTR) + 1 → TBLPTR, Before Instruction (TABLAT) → Holding Register TABLAT = 34h TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written (01389Bh) = 34h to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section7.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register ) DS39689F-page 318 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode Read Process Write to W in Indexed Literal Offset Addressing literal ‘k’ Data mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Example: XORLW 0AFh Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = B5h Words: 1 After Instruction Cycles: 1(2) W = 1Ah Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39689F-page 319

PIC18F2221/2321/4221/4321 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39689F-page 320 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 25.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table25-3. Detailed descriptions are In addition to the standard 75 instructions of the PIC18 provided in Section25.2.2 “Extended Instruction instruction set, PIC18F2221/2321/4221/4321 family Set”. The opcode field descriptions in Table25-1 devices also provide an optional extension to the core (page280) apply to both the standard and extended CPU functionality. The added features include eight PIC18 instruction sets. additional instructions that augment indirect and indexed addressing operations and the implementation Note: The instruction set extension and the of Indexed Literal Offset Addressing mode for many of Indexed Literal Offset Addressing mode the standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in the assembler. are disabled by default. To enable them, users must set The syntax for these commands is the XINST Configuration bit. provided as a reference for users who may The instructions in the extended set (with the exception be reviewing code that has been generated of CALLW, MOVSF and MOVSS) can all be classified as by a compiler. literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. 25.2.1 EXTENDED INSTRUCTION SYNTAX Two of the instructions, ADDFSR and SUBFSR, each Most of the extended instructions use indexed have an additional special instantiation for using FSR2. arguments, using one of the File Select Registers and These versions (ADDULNK and SUBULNK) allow for some offset to specify a source or destination register. automatic return after execution. When an argument for an instruction serves as part of The extended instructions are specifically implemented indexed addressing, it is enclosed in square brackets to optimize re-entrant program code (that is, code that (“[ ]”). This is done to indicate that the argument is used is recursive or that uses a software stack) written in as an index or offset. The MPASM™ Assembler will high-level languages, particularly C. Among other flag an error if it determines that an index or offset value things, they allow users working in high-level is not bracketed. languages to perform certain operations on data When the extended instruction set is enabled, brackets structures more efficiently. These include: are also used to indicate index arguments in byte- • Dynamic allocation and deallocation of software oriented and bit-oriented instructions. This is in addition stack space when entering and leaving to other changes in their syntax. For more details, see subroutines Section25.2.3.1 “Extended Instruction Syntax with • Function Pointer invocation Standard PIC18 Commands”. • Software Stack Pointer manipulation Note: In the past, square brackets have been • Manipulation of variables located in a software used to denote optional arguments in the stack PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st Word 2 1110 1011 0zzz zzzz None fd (destination) 2nd Word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination)2nd Word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return © 2009 Microchip Technology Inc. DS39689F-page 321

PIC18F2221/2321/4221/4321 FAMILY 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2, Operation: FSR(f) + k → FSR(f) (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the TOS. Cycles: 1 The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during the Q1 Q2 Q3 Q4 second cycle. Decode Read Process Write to This may be thought of as a special literal ‘k’ Data FSR case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on Example: ADDFSR 2, 23h FSR2. Before Instruction Words: 1 FSR2 = 03FFh Cycles: 2 After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). DS39689F-page 322 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0 ≤ z ≤ 127 s 0 ≤ f ≤ 4095 Operation: (PC + 2) → TOS, d (W) → PCL, Operation: ((FSR2) + z ) → f s d (PCLATH) → PCH, Status Affected: None (PCLATU) → PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffff d Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of s latched into PCH and PCU, FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the value returned will be 00h. Q1 Q2 Q3 Q4 Decode Read PUSH PC to No Words: 2 WREG stack operation Cycles: 2 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Decode No No Write Before Instruction operation operation register ‘f’ PC = address (HERE) PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h Example: MOVSF [05h], REG2 TOS = address (HERE + 2) PCLATH = 10h Before Instruction PCLATU = 00h FSR2 = 80h W = 06h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h © 2009 Microchip Technology Inc. DS39689F-page 323

PIC18F2221/2321/4221/4321 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255 0 ≤ z ≤ 127 d Operation: k → (FSR2), Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1 → FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. FSR2 Description The contents of the source register are is decremented by 1 after the operation. moved to the destination register. The This instruction allows users to push values addresses of the source and destination onto a software stack. registers are determined by adding the 7-bit literal offsets ‘z ’ or ‘z ’, Words: 1 s d respectively, to the value of FSR2. Both Cycles: 1 registers can be located anywhere in the 4096-byte data memory space Q Cycle Activity: (000h to FFFh). Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to PCL, TOSU, TOSH or TOSL as the data destination destination register. If the resultant source address points to an indirect addressing register, the Example: PUSHL 08h value returned will be 00h. If the resultant destination address points to Before Instruction an indirect addressing register, the FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h instruction will execute as a NOP. Words: 2 After Instruction FSR2H:FSR2L = 01EBh Cycles: 2 Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39689F-page 324 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2, Operation: FSR(f – k) → FSR(f) (TOS) → PC Status Affected: None Status None Encoding: 1110 1001 ffkk kkkk Affected: Description: The 6-bit literal ‘k’ is subtracted from Encoding: 1110 1001 11kk kkkk the contents of the FSR specified Description: The 6-bit literal ‘k’ is subtracted from the by ‘f’. contents of the FSR2. A RETURN is then Words: 1 executed by loading the PC with the TOS. The instruction takes two cycles to Cycles: 1 execute; a NOP is performed during the Q Cycle Activity: second cycle. Q1 Q2 Q3 Q4 This may be thought of as a special case of Decode Read Process Write to the SUBFSR instruction, where f = 3 (binary register ‘f’ Data destination ‘11’); it operates only on FSR2. Words: 1 Cycles: 2 Example: SUBFSR 2, 23h Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 FSR2 = 03FFh Decode Read Process Write to After Instruction register ‘f’ Data destination FSR2 = 03DCh No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2009 Microchip Technology Inc. DS39689F-page 325

PIC18F2221/2321/4221/4321 FAMILY 25.2.3 BYTE-ORIENTED AND 25.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set register argument, ‘f’, in the standard byte-oriented and extension may cause legacy applications bit-oriented commands is replaced with the literal offset to behave erratically or fail entirely. value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing mode (Section6.5.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an the standard PIC18 instruction set are interpreted. error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing mode, the Access RAM either as a location in the Access Bank (‘a’ = 0) or in a argument is never specified; it will automatically be GPR bank designated by the BSR (‘a’ = 1). When the assumed to be ‘0’. This is in contrast to standard extended instruction set is enabled and ‘a’ = 0, operation (extended instruction set disabled) when ‘a’ however, a file register argument of 5Fh or less is is set on the basis of the target address. Declaring the interpreted as an offset from the pointer value in FSR2 Access RAM bit in this mode will also generate an error and not as a literal address. For practical purposes, this in the MPASM Assembler. means that all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit- The destination argument, ‘d’, functions as before. oriented instructions, or almost half of the core PIC18 In the latest versions of the MPASM Assembler, instructions – may behave differently when the language support for the extended instruction set must extended instruction set is enabled. be explicitly invoked. This is done with either the When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the Access RAM are essentially remapped to their original source listing. values. This may be useful in creating backward 25.2.4 CONSIDERATIONS WHEN compatible code. If this technique is used, it may be ENABLING THE EXTENDED necessary to save the value of FSR2 and restore it INSTRUCTION SET when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the instruc- must also keep in mind the syntax requirements of the tion set may not be beneficial to all users. In particular, extended instruction set (see Section25.2.3.1 users who are not writing code that uses a software “Extended Instruction Syntax with Standard PIC18 stack may not benefit from using the extensions to the Commands”). instruction set. Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing can be very useful for dynamic stack and pointer mode may create issues with legacy applications manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address register. Users who are accustomed to the PIC18 registers in the Access Bank below 5Fh. Since these programming must keep in mind that, when the addresses are interpreted as literal offsets to FSR2 extended instruction set is enabled, register addresses when the instruction set extension is enabled, the of 5Fh or less are used for Indexed Literal Offset application may read or write to the wrong data Addressing mode. addresses. Representative examples of typical byte-oriented and When porting an application to the PIC18F2221/2321/ bit-oriented instructions in the Indexed Literal Offset 4221/4321 family, it is very important to consider the Addressing mode are provided on the following page to type of code. A large, re-entrant application that is show how execution is affected. The operand written in ‘C’ and would benefit from efficient conditions shown in the examples are applicable to all compilation will do well when using the instruction set instructions of these types. extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39689F-page 326 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 Operands: 0 ≤ f ≤ 95 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in Cycles: 1 register ‘f’ (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Example: ADDWF [OFST], 0 Contents of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Set Indexed Contents SETF of 0A2Ch = 20h (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2009 Microchip Technology Inc. DS39689F-page 327

PIC18F2221/2321/4221/4321 FAMILY 25.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set of the PIC18F2221/2321/4221/4321 family family of • A menu option, or dialog box within the devices. This includes the MPLAB C18 C Compiler, environment, that allows the user to configure the MPASM Assembly language and MPLAB Integrated language tool and its settings for the project Development Environment (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing mode. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended information. instruction set, XINST must be set during programming. DS39689F-page 328 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 26.0 DEVELOPMENT SUPPORT 26.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS39689F-page 329

PIC18F2221/2321/4221/4321 FAMILY 26.2 MPLAB C Compilers for Various 26.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 26.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 26.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 26.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39689F-page 330 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 26.7 MPLAB SIM Software Simulator 26.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 26.10 PICkit 3 In-Circuit Debugger/ Programmer and 26.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables. © 2009 Microchip Technology Inc. DS39689F-page 331

PIC18F2221/2321/4221/4321 FAMILY 26.11 PICkit 2 Development 26.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 26.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39689F-page 332 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39689F-page 333

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-1: PIC18F2221/2321/4221/4321 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 27-2: PIC18F2221/2321/4221/4321 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V 5.0V 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 25 MHz Frequency DS39689F-page 334 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-3: PIC18LF2221/2321/4221/4321 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V 4.5V e g 4.2V 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz 25 MHz 40 MHz Frequency FMAX = (9.54 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. © 2009 Microchip Technology Inc. DS39689F-page 335

PIC18F2221/2321/4221/4321 FAMILY 27.1 DC Characteristics: Supply Voltage PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage PIC18LF2X21/4X21 2.0 — 5.5 V PIC18F2X21/4X21 4.2 — 5.5 V D001C AVDD Analog Supply Voltage VDD – 0.3V — VDD + 0.3V V D001D AVSS Analog Ground Voltage VSS – 0.3V — VSS + 0.3V V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See section on Power-on Reset for to Ensure Internal details Power-on Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset for to Ensure Internal details Power-on Reset Signal VBOR Brown-out Reset Voltage D005 PIC18LF2X21/4X21 BORV<1:0> = 11 2.00 2.11 2.22 V BORV<1:0> = 10 2.65 2.79 2.93 V D005 All devices BORV<1:0> = 01(2) 4.11 4.33 4.55 V BORV<1:0> = 00 4.36 4.59 4.82 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: With BOR enabled, full-speed operation (FOSC = 40 MHz) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency. DS39689F-page 336 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) PIC18LF2X21/4X21 0.5 0.7 μA -40°C VDD = 2.0V 0.5 0.7 μA +25°C (Sleep mode) 0.5 1.7 μA +85°C PIC18LF2X21/4X21 0.6 0.9 μA -40°C VDD = 3.0V 0.6 0.9 μA +25°C (Sleep mode) 0.6 1.9 μA +85°C All Devices 0.9 2.0 μA -40°C 0.9 2.0 μA +25°C VDD = 5.0V 0.9 6.5 μA +85°C (Sleep mode) Extended Devices Only 7.5 70 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. © 2009 Microchip Technology Inc. DS39689F-page 337

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF2X21/4X21 13 19 μA -40°C 13 19 μA +25°C VDD = 2.0V 13 17 μA +85°C PIC18LF2X21/4X21 41 45 μA -40°C 34 38 μA +25°C VDD = 3.0V FOSC = 31kHz (RC_RUN mode, 27 30 μA +85°C INTRC source) All Devices 104 115 μA -40°C 86 95 μA +25°C VDD = 5.0V 67 75 μA +85°C Extended Devices Only 68 100 μA +125°C PIC18LF2X21/4X21 0.31 0.35 mA -40°C 0.31 0.35 mA +25°C VDD = 2.0V 0.31 0.35 mA +85°C PIC18LF2X21/4X21 0.55 0.60 mA -40°C 0.51 0.60 mA +25°C VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, 0.47 0.60 mA +85°C INTOSC source) All Devices 1.0 1.3 mA -40°C 0.94 1.3 mA +25°C VDD = 5.0V 0.88 1.2 mA +85°C Extended Devices Only 0.88 1.2 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. DS39689F-page 338 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF2X21/4X21 0.69 0.9 mA -40°C 0.70 0.9 mA +25°C VDD = 2.0V 0.71 0.9 mA +85°C PIC18LF2X21/4X21 1.17 1.45 mA -40°C 1.15 1.45 mA +25°C VDD = 3.0V FOSC = 4MHz (RC_RUN mode, 1.14 1.45 mA +85°C INTOSC source) All Devices 2.24 2.9 mA -40°C 2.20 2.9 mA +25°C VDD = 5.0V 2.16 2.8 mA +85°C Extended Devices Only 2.18 2.8 mA +125°C PIC18LF2X21/4X21 3 5 μA -40°C 3 5 μA +25°C VDD = 2.0V 3 5.6 μA +85°C PIC18LF2X21/4X21 4 7 μA -40°C 5 7 μA +25°C VDD = 3.0V FOSC = 31 kHz (RC_IDLE mode, 5 10 μA +85°C INTRC source) All Devices 10 12 μA -40°C 10 12 μA +25°C VDD = 5.0V 10 16 μA +85°C Extended Devices Only 17 50 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. © 2009 Microchip Technology Inc. DS39689F-page 339

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF2X21/4X21 160 230 μA -40°C 170 230 μA +25°C VDD = 2.0V 170 230 μA +85°C PIC18LF2X21/4X21 220 330 μA -40°C 240 330 μA +25°C VDD = 3.0V FOSC = 1MHz (RC_IDLE mode, 250 330 μA +85°C INTOSC source) All Devices 410 500 μA -40°C 420 500 μA +25°C VDD = 5.0V 430 500 μA +85°C Extended Devices Only 450 500 μA +125°C PIC18LF2X21/4X21 310 440 μA -40°C 330 440 μA +25°C VDD = 2.0V 340 440 μA +85°C PIC18LF2X21/4X21 480 750 μA -40°C 500 750 μA +25°C VDD = 3.0V FOSC = 4MHz (RC_IDLE mode, 520 750 μA +85°C INTOSC source) All Devices 0.91 1.3 mA -40°C 0.93 1.3 mA +25°C VDD = 5.0V 0.96 1.3 mA +85°C Extended Devices Only 0.98 1.3 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. DS39689F-page 340 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF2X21/4X21 0.22 0.35 mA -40°C 0.22 0.35 mA +25°C VDD = 2.0V 0.21 0.3 mA +85°C PIC18LF2X21/4X21 0.51 0.55 mA -40°C 0.45 0.50 mA +25°C VDD = 3.0V FOSC = 1MHz (PRI_RUN mode, 0.39 0.45 mA +85°C EC oscillator) All Devices 1.14 1.15 mA -40°C 0.99 1.1 mA +25°C VDD = 5.0V 0.83 1.1 mA +85°C Extended Devices Only 0.80 1.1 mA +125°C PIC18LF2X21/4X21 610 870 μA -40°C 610 870 μA +25°C VDD = 2.0V 610 870 μA +85°C PIC18LF2X21/4X21 1.16 1.83 mA -40°C 1.10 1.83 mA +25°C VDD = 3.0V FOSC = 4MHz (PRI_RUN mode, 1.07 1.83 mA +85°C EC oscillator) All Devices 2.35 2.85 mA -40°C 2.24 2.85 mA +25°C VDD = 5.0V 2.14 2.85 mA +85°C Extended Devices Only 2.14 2.85 mA +125°C Extended Devices Only 9 15 mA +125°C VDD = 4.2V FOSC = 25MHz 12 20 mA +125°C (PRI_RUN mode, VDD = 5.0V EC oscillator) All Devices 16 19 mA -40°C 14 19 mA +25°C VDD = 4.2V 14 19 mA +85°C FOSC = 40MHz (PRI_RUN mode, All Devices 17 22.7 mA -40°C EC oscillator) 17 22.7 mA +25°C VDD = 5.0V 17 22.7 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. © 2009 Microchip Technology Inc. DS39689F-page 341

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All Devices 7 10 mA -40°C 6 10 mA +25°C FOSC = 4MHz, VDD = 4.2V 16 MHz internal 6 10 mA +85°C (PRI_RUN HS+PLL) Extended Devices Only 6 10 mA +125°C All Devices 10 12 mA -40°C 9 12 mA +25°C FOSC = 4MHz, VDD = 5.0V 16 MHz internal 9 12 mA +85°C (PRI_RUN HS+PLL) Extended Devices Only 9 12 mA +125°C All Devices 17 19 mA -40°C FOSC = 10MHz, 15 19 mA +25°C VDD = 4.2V 40 MHz internal 15 19 mA +85°C (PRI_RUN HS+PLL) All Devices 18 23 mA -40°C FOSC = 10MHz, 18 23 mA +25°C VDD = 5.0V 40 MHz internal 18 23 mA +85°C (PRI_RUN HS+PLL) Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. DS39689F-page 342 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF2X21/4X21 51 75 μA -40°C 54 75 μA +25°C VDD = 2.0V 60 75 μA +85°C PIC18LF2X21/4X21 83 123 μA -40°C 88 123 μA +25°C VDD = 3.0V FOSC = 1MHz (PRI_IDLE mode, 93 123 μA +85°C EC oscillator) All Devices 180 260 μA -40°C 180 260 μA +25°C VDD = 5.0V 180 260 μA +85°C Extended Devices Only 190 260 μA +125°C PIC18LF2X21/4X21 210 290 μA -40°C 220 290 μA +25°C VDD = 2.0V 230 290 μA +85°C PIC18LF2X21/4X21 350 480 μA -40°C 360 480 μA +25°C VDD = 3.0V FOSC = 4MHz (PRI_IDLE mode, 370 480 μA +85°C EC oscillator) All Devices 0.69 1 mA -40°C 0.70 1 mA +25°C VDD = 5.0V 0.72 1 mA +85°C Extended Devices Only 0.74 1 mA +125°C Extended Devices Only 3.7 4.0 mA +125°C VDD = 4.2V FOSC = 25MHz 4.6 5.0 mA +125°C (PRI_IDLE mode, VDD = 5.0V EC oscillator) All Devices 6.0 7.3 mA -40°C 6.2 7.3 mA +25°C VDD = 4.2V 6.6 7.3 mA +85°C FOSC = 40MHz (PRI_IDLE mode, All Devices 6.8 9.2 mA -40°C EC oscillator) 7.0 9.2 mA +25°C VDD = 5.0V 7.1 9.2 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. © 2009 Microchip Technology Inc. DS39689F-page 343

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF2X21/4X21 12 19 μA -40°C(5) — 19 μA -10°C VDD = 2.0V 13 19 μA +25°C 13 19 μA +85°C PIC18LF2X21/4X21 40 45 μA -40°C(5) — 45 μA -10°C FOSC = 32kHz VDD = 3.0V (SEC_RUN mode, 33 45 μA +25°C Timer1 as clock)(3) 27 45 μA +85°C All Devices 101 115 μA -40°C(5) — 110 μA -10°C VDD = 5.0V 83 110 μA +25°C 65 88 μA +85°C PIC18LF2X21/4X21 2.5 5 μA -40°C(5) — 5 μA -10°C VDD = 2.0V 3.0 5 μA +25°C 3.5 8 μA +85°C PIC18LF2X21/4X21 3.9 7 μA -40°C(5) — 7 μA -10°C FOSC = 32kHz VDD = 3.0V (SEC_IDLE mode, 4.5 7 μA +25°C Timer1 as clock)(3) 5.2 10.7 μA +85°C All Devices 7.5 10 μA -40°C(5) — 10 μA -10°C VDD = 5.0V 8.0 10 μA +25°C 8.6 15 μA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. DS39689F-page 344 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD) D022 Watchdog Timer 1.6 2.5 μA -40°C (ΔIWDT) 1.6 2.5 μA +25°C VDD = 2.0V 1.5 2.5 μA +85°C 2.3 3.5 μA -40°C 2.2 3.5 μA +25°C VDD = 3.0V 2.1 3 μA +85°C 3.4 7.4 μA -40°C 3.9 7.4 μA +25°C VDD = 5.0V 4.4 7.4 μA +85°C 4.5 7.4 μA +125°C D022A Brown-out Reset(4) 34 45 μA -40°C to +85°C VDD = 3.0V (ΔIBOR) 40 62.6 μA -40°C to +85°C VDD = 5.0V 42 62.6 μA -40°C to +125°C 0 2 μA -40°C to +85°C VDD = 3.0V Sleep mode, 0 5 μA -40°C to +125°C VDD = 5.0V BOREN<1:0> = 10 D022B High/Low-Voltage 23 35 μA -40°C to +85°C VDD = 2.0V (ΔILVD) Detect(4) 23 35 μA -40°C to +85°C VDD = 3.0V 28 35 μA -40°C to +85°C VDD = 5.0V 30 40 μA -40°C to +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. © 2009 Microchip Technology Inc. DS39689F-page 345

PIC18F2221/2321/4221/4321 FAMILY 27.2 DC Characteristics: Power-Down and Supply Current PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) PIC18LF2221/2321/4221/4321 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2221/2321/4221/4321 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. D025 Timer1 Oscillator 2.1 4.5 μA -40°C(5) (ΔIOSCB) — 4.5 μA -10°C VDD = 2.0V 1.8 4.5 μA +25°C 2.1 4.5 μA +85°C 2.2 6.0 μA -40°C(5) 32kHz Tuning Fork, — 6 μA -10°C VDD = 3.0V Crystal on Timer1 2.6 6.0 μA +25°C Oscillator(3) 2.9 6.0 μA +85°C 3.0 8.0 μA -40°C(5) — 8 μA -10°C VDD = 5.0V 3.2 8.0 μA +25°C 3.4 8.0 μA +85°C D026 A/D Converter 1.0 2.0 μA -40°C to +85°C VDD = 2.0V (ΔIAD) 1.0 2.0 μA -40°C to +85°C VDD = 3.0V A/D on, Not Converting 1.0 2.0 μA -40°C to +85°C VDD = 5.0V 2.0 8.0 μA -40°C to +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: Low-power, Timer1 oscillator is selected unless otherwise indicated, where LPT1OSC (CONFIG3H<2>) = 1. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 5: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. DS39689F-page 346 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 27.3 DC Characteristics: PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O Ports: D030 with TTL Buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V D031A RC3 and RC4 VSS 0.3 VDD V I2C™ enabled D031B VSS 0.8 V SMBus enabled D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V RC, EC modes(1) D033B OSC1 VSS 0.3 V XT, LP modes D034 T13CKI VSS 0.3 V VIH Input High Voltage I/O Ports: D040 with TTL Buffer 0.25 VDD + VDD V VDD < 4.5V 0.8V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V D041A RC3 and RC4 0.7 VDD VDD V I2C™ enabled D041B 2.1 VDD V SMBus enabled, VSS ≥ 3V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC mode D043B OSC1 0.9 VDD VDD V RC mode(1) D043C OSC1 1.6 VDD V XT, LP modes D044 T13CKI 1.6 VDD V IIL Input Leakage Current(2,3) D060 I/O Ports — ±200 nA VDD < 5.5V, VSS ≤ VPIN ≤ VDD, Pin at High-Impedance — ±50 nA VDD < 3V, VSS ≤ VPIN ≤ VDD, Pin at High-Impedance D061 MCLR — ±1 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±1 μA Vss ≤ VPIN ≤ VDD Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2009 Microchip Technology Inc. DS39689F-page 347

PIC18F2221/2321/4221/4321 FAMILY 27.3 DC Characteristics: PIC18F2221/2321/4221/4321 (Industrial) PIC18LF2221/2321/4221/4321 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. IPU Weak Pull-up Current D070 IPURB PORTB Weak Pull-up Current 50 400 μA VDD = 5V, VPIN = VSS VOL Output Low Voltage D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40°C to +85°C VOH Output High Voltage(3) D090 I/O Ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40°C to +85°C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 Pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O Pins and OSC2 — 50 pF Maximum that allows the (in RC mode) AC Timing Specifications to be met D102 CB SCL, SDA — 400 pF Maximum bus capacitance permitted by I2C™ Specification Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS39689F-page 348 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Data EEPROM Memory D120 ED Byte Endurance 1M 10M — E/W -40°C to +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write, VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 100K 1M — E/W -40°C to +85°C Cycles before Refresh(1) D125 IDDP Supply Current during — 10 — mA Programming Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 3.0 — 5.5 V Using ICSP™ port, 25°C D132B VPEW VDD for Self-Timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA Programming † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Refer to Section8.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. © 2009 Microchip Technology Inc. DS39689F-page 349

PIC18F2221/2321/4221/4321 FAMILY TABLE 27-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C for industrial (unless otherwise stated) -40°C < TA < +125°C for extended (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1) — 150 400 ns PIC18FXXXX D303A — 150 600 ns PIC18LFXXXX, VDD = 2.0V D304 TMC2OV Comparator Mode Change to — — 10 μs Output Valid Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 27-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C for industrial (unless otherwise stated) -40°C < TA < +125°C for extended (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k — Ω D310 TSET Settling Time(1) — — 10 μs Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. DS39689F-page 350 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be cleared in software) VLVD (HLVDIF set by hardware) HLVDIF(1) Note1: VDIRMAG = 0. TABLE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D420 HLVD Voltage on VDD LVV = 0000 2.06 2.17 2.28 V Transition High-to-Low LVV = 0001 2.12 2.23 2.34 V LVV = 0010 2.24 2.36 2.48 V LVV = 0011 2.32 2.44 2.56 V LVV = 0100 2.47 2.60 2.73 V LVV = 0101 2.65 2.79 2.93 V LVV = 0110 2.74 2.89 3.04 V LVV = 0111 2.96 3.12 3.28 V LVV = 1000 3.22 3.39 3.56 V LVV = 1001 3.37 3.55 3.73 V LVV = 1010 3.52 3.71 3.90 V LVV = 1011 3.70 3.90 4.10 V LVV = 1100 3.90 4.11 4.32 V LVV = 1101 4.11 4.33 4.55 V LVV = 1110 4.36 4.59 4.82 V LVV = 1111 1.10 1.20 1.30 V HLVDIN Input/Internal Reference Voltage © 2009 Microchip Technology Inc. DS39689F-page 351

PIC18F2221/2321/4221/4321 FAMILY 27.4 AC (Timing) Characteristics 27.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS39689F-page 352 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 27.4.2 TIMING CONDITIONS Note: Because of space limitations, the generic The temperature and voltages specified in Table27-5 terms “PIC18FXXXX” and “PIC18LFXXXX” apply to all timing specifications unless otherwise are used throughout this section to refer to noted. Figure27-5 specifies the load conditions for the the PIC18F2221/2321/4221/4321 and timing specifications. PIC18LF2221/2321/4221/4321 families of devices specifically and only those devices. TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section27.1 and Section27.3. LF parts operate for industrial temperatures only. FIGURE 27-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports © 2009 Microchip Technology Inc. DS39689F-page 353

PIC18F2221/2321/4221/4321 FAMILY 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator mode DC 25 MHz HS Oscillator mode DC 40 MHz EC Oscillator mode 4 10 MHz HS+PLL Oscillator mode DC 50 kHz LP Oscillator mode Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 5 200 kHz LP Oscillator mode 1 TOSC External CLKI Period(1) 1000 — ns XT, RC Oscillator mode 40 — ns HS Oscillator mode 25 — ns EC Oscillator mode 100 250 ns HS+PLL Oscillator mode 32 — μs LP Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 250 1 μs XT Oscillator mode 40 250 ns HS Oscillator mode 5 209 μs LP Oscillator mode 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial 160 — ns TCY = 4/FOSC, Extended 3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode TOSH High or Low Time 2.5 — μs LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode TOSF Rise or Fall Time — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS39689F-page 354 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 27-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1) PIC18LF2221/2321/4221/4321 -2 +/-1 2 % +25°C VDD = 2.0-5.5V -5 — 5 % -10°C to +85°C VDD = 2.0-5.5V -10 +/-1 10 % -40°C to +85°C VDD = 2.0-5.5V PIC18F2221/2321/4221/4321 -2 +/-1 2 % +25°C VDD = 4.2-5.5V -5 — 5 % -10°C to +85°C VDD = 4.2-5.5V -10 +/-1 10 % -40°C to +85°C VDD = 4.2-5.5V INTRC Accuracy @ Freq = 31 kHz PIC18LF2221/2321/4221/4321 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.0-5.5V PIC18F2221/2321/4221/4321 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.2-5.5V Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. © 2009 Microchip Technology Inc. DS39689F-page 355

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-7: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure27-5 for load conditions. TABLE 27-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12 TckR CLKO Rise Time — 35 100 ns (Note 1) 13 TckF CLKO Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port In Hold after CLKO ↑ 0 — — ns (Note 1) 17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1 ↑ (Q2 cycle) to PIC18FXXXX 100 — — ns 18A Port Input Invalid PIC18LFXXXX 200 — — ns VDD = 2.0V (I/O in hold time) 19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time) 0 — — ns 20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns 20A PIC18LFXXXX — — 60 ns VDD = 2.0V 21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns 21A PIC18LFXXXX — — 60 ns VDD = 2.0V 22† TINP INTx Pin High or Low Time TCY — — ns 23† TRBP RB<7:4> Change INTx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39689F-page 356 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins FIGURE 27-9: BROWN-OUT RESET TIMING VDD BVDD 35 VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 3.56 4.19 4.82 ms (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 57 67 77 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — μs Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005) 36 TIRVST Time for Internal Reference — 20 50 μs Voltage to become Stable 37 TLVD High/Low-Voltage Detect Pulse Width 200 — — μs VDD ≤ VLVD 38 TCSD CPU Start-up Time — 10 — μs 39 TIOBST Time for INTOSC to Stabilize — 1 — μs © 2009 Microchip Technology Inc. DS39689F-page 357

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 TABLE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 Tt0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 Tt1H T13CKI Synchronous, no prescaler 0.5 TCY + 20 — ns High Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 46 Tt1L T13CKI Synchronous, no prescaler 0.5 TCY + 5 — ns Low Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 47 Tt1P T13CKI Synchronous Greater of: — ns N = prescale Input 20ns or value (1, 2, 4, 8) Period (TCY + 40)/N Asynchronous 60 — ns Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 Tcke2tmrI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment DS39689F-page 358 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-11: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 TABLE 27-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TccL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 51 TccH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 52 TccP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TccR CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 54 TccF CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V © 2009 Microchip Technology Inc. DS39689F-page 359

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-12: PARALLEL SLAVE PORT TIMING (PIC18F4221/4321) RE2/CS RE0/RD RE1/WR 65 RD<7:0> 62 64 63 Note: Refer to Figure27-5 for load conditions. TABLE 27-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4221/4321) Param. Symbol Characteristic Min Max Units Conditions No. 62 TdtV2wrH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TwrH2dtI WR ↑ or CS ↑ to Data–In PIC18FXXXX 20 — ns Invalid (hold time) PIC18LFXXXX 35 — ns VDD = 2.0V 64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from — 3 TCY WR ↑ or CS ↑ DS39689F-page 360 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-13: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS SCK (CKP = 0) 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 20 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns of Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 40 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time — 25 ns 80 TscH2doV, SDO Data Output Valid after PIC18FXXXX — 50 ns TscL2doV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V © 2009 Microchip Technology Inc. DS39689F-page 361

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-14: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 20 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns of Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 40 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time — 25 ns 80 TscH2doV, SDO Data Output Valid after PIC18FXXXX — 50 ns TscL2doV SCK Edge PIC18LFXXXX 100 ns VDD = 2.0V 81 TdoV2scH, SDO Data Output Setup to SCK Edge TCY — ns TdoV2scL DS39689F-page 362 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SDI MSb In bit 6 - - - -1 LSb In 74 73 TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input 3 TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 20 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 40 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS ↑ to SDO Output High-Impedance 10 50 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns TscL2doV PIC18LFXXXX 100 ns VDD = 2.0V 83 TscH2ssH, SS ↑ after SCK edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39689F-page 363

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-16: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 TABLE 27-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input 3 TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 40 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS ↑ to SDO Output High-Impedance 10 50 ns 80 TscH2doV, SDO Data Output Valid after SCK PIC18FXXXX — 50 ns TscL2doV Edge PIC18LFXXXX — 100 ns VDD = 2.0V 82 TssL2doV SDO Data Output Valid after SS ↓ PIC18FXXXX — 50 ns Edge PIC18LFXXXX — 100 ns VDD = 2.0V 83 TscH2ssH, SS ↑ after SCK Edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39689F-page 364 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-17: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition TABLE 27-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 27-18: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out © 2009 Microchip Technology Inc. DS39689F-page 365

PIC18F2221/2321/4221/4321 FAMILY TABLE 27-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs 400 kHz mode 0.6 — μs MSSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs MSSP Module 1.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated Setup Time 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period, the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 106 THD:DAT Data Input Hold 100 kHz mode 0 — ns Time 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 2) Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 4.7 — μs Setup Time 400 kHz mode 0.6 — μs 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS39689F-page 366 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-19: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition TABLE 27-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 27-20: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out © 2009 Microchip Technology Inc. DS39689F-page 367

PIC18F2221/2321/4221/4321 FAMILY TABLE 27-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new transmission 400 kHz mode 1.3 — ms can start D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter 107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released. DS39689F-page 368 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-21: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 TABLE 27-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 Tckrf Clock Out Rise Time and Fall Time PIC18FXXXX — 20 ns (Master mode) PIC18LFXXXX — 50 ns VDD = 2.0V 122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V FIGURE 27-22: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 TABLE 27-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TdtV2ckl SYNC RCV (MASTER & SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TckL2dtl Data Hold after CK ↓ (DT hold time) 15 — ns © 2009 Microchip Technology Inc. DS39689F-page 369

PIC18F2221/2321/4221/4321 FAMILY TABLE 27-24: A/D CONVERTER CHARACTERISTICS Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±2 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 1.8 — — V VDD < 3.0V (VREFH – VREFL) 3 — — V VDD ≥ 3.0V A21 VREFH Reference Voltage High — — VDD + 3.0V V A22 VREFL Reference Voltage Low VSS – 0.3V — — V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.5 kΩ Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. DS39689F-page 370 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY FIGURE 27-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 27-25: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μs VDD = 2.0V; TOSC based, VREF full range PIC18FXXXX — 1 μs A/D RC mode PIC18LFXXXX — 3 μs VDD = 2.0V; A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time)(2) 132 TACQ Acquisition Time(3) 1.4 — μs -40°C to +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) 137 TDIS Discharge Time 0.2 — μs Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES register may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. © 2009 Microchip Technology Inc. DS39689F-page 371

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 372 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC18F2321-I/SPe3 XXXXXXXXXXXXXXXXX 0910017 YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F2321-E/SOe3 XXXXXXXXXXXXXXXXXXXX 0910017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN Example XXXXXXXX 18F2321 XXXXXXXX /ML e3 YYWWNNN 0910017 28-Lead SSOP Example XXXXXXXXXXXX PIC18F2321 XXXXXXXXXXXX -I/SSe3 YYWWNNN 0910017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS39689F-page 373

PIC18F2221/2321/4221/4321 FAMILY 28.1 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC18F4321-I/Pe3 XXXXXXXXXXXXXXXXXX 0910017 XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead QFN Example XXXXXXXXXX PIC18F4321 XXXXXXXXXX -I/MLe3 XXXXXXXXXX 0910017 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX PIC18F4321 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 0910017 YYWWNNN DS39689F-page 374 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1 © 2009 Microchip Technology Inc. DS39689F-page 375

PIC18F2221/2321/4221/4321 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)#(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)#(cid:24)(cid:9)(cid:25)(cid:9)$(cid:12)(cid:8)(cid:6)%(cid:9)&’((cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)#(cid:22)) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e b h α h φ c A A2 L A1 L1 β 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)?(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:3)(cid:20)(cid:4)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)-(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:4)(cid:20)-(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:5)(cid:20)(cid:29)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:5)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:23)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)< = (cid:4)(cid:20)-- 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)B = (cid:30)(cid:29)B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)B = (cid:30)(cid:29)B !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:3)1 DS39689F-page 376 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7),(cid:6)(cid:9)(cid:23)-(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)./.(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)*+! 0(cid:12)(cid:18)1(cid:9)(cid:27)’(((cid:9)(cid:28)(cid:28)(cid:9))(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13),(cid:18)1 !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)(cid:29)1 © 2009 Microchip Technology Inc. DS39689F-page 377

PIC18F2221/2321/4221/4321 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7),(cid:6)(cid:9)(cid:23)-(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)./.(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)*+! 0(cid:12)(cid:18)1(cid:9)(cid:27)’(((cid:9)(cid:28)(cid:28)(cid:9))(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13),(cid:18)1 !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS39689F-page 378 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)12(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)#(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)(’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)#(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B (cid:23)B <B 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1 © 2009 Microchip Technology Inc. DS39689F-page 379

PIC18F2221/2321/4221/4321 FAMILY 3(cid:27)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9).(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:29) = (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:29)(cid:24)(cid:4) = (cid:20)?(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)<(cid:29) = (cid:20)(cid:29)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)<(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) = (cid:20)(cid:3)(cid:4)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< = (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:5)(cid:4)(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)?1 DS39689F-page 380 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7),(cid:6)(cid:9)(cid:23)-(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)/(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)*+! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-< ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)-1 © 2009 Microchip Technology Inc. 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PIC18F2221/2321/4221/4321 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7),(cid:6)(cid:9)(cid:23)-(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)/(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)*+! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS39689F-page 382 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)41(cid:12)(cid:13)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)5(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)4(cid:24)(cid:9)(cid:25)(cid:9)6(cid:27)/6(cid:27)/6(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)4*+(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B -(cid:20)(cid:29)B (cid:5)B : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)D(cid:2)!(cid:7)E(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1 © 2009 Microchip Technology Inc. DS39689F-page 383

PIC18F2221/2321/4221/4321 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)41(cid:12)(cid:13)(cid:9)*(cid:21)(cid:7)(cid:8)(cid:9)+(cid:16)(cid:7)(cid:18)5(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)4(cid:24)(cid:9)(cid:25)(cid:9)6(cid:27)/6(cid:27)/6(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)4*+(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS39689F-page 384 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY APPENDIX A: REVISION HISTORY Revision A (July 2005) Original data sheet for PIC18F2221/2321/4221/4321 devices. Revision B (August 2006) Updated Section 26.0 “Electrical Characteristic”. Revision C (October 2006) This revision includes updates to the packaging diagrams. Revision D (January 2007) This revision includes updates to the packaging diagrams. Revision E (February 2007) This revision includes updates to the packaging diagrams. Revision F (September 2009) This revision includes a new chapter, Section2.0 “Guidelines for Getting Started with PIC18F Microcontrollers”. There are also updates to Section27.0 “Electrical Characteristics”, Section28.0 “Packaging Information” and minor text edits throughout document. © 2009 Microchip Technology Inc. DS39689F-page 385

PIC18F2221/2321/4221/4321 FAMILY APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in TableB-1. TABLE B-1: DEVICE DIFFERENCES Features PIC18F2221 PIC18F2321 PIC18F4221 PIC18F4321 Program Memory (Bytes) 4096 8192 4096 8192 Program Memory (Instructions) 2048 4096 2048 4096 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 2 2 1 1 Enhanced Capture/Compare/ 0 0 1 1 PWM Modules Parallel Communications (PSP) No No Yes Yes 10-Bit Analog-to-Digital Module 10 input channels 10 input channels 13 input channels 13 input channels Packages 28-pin SPDIP 28-pin SPDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 44-pin TQFP 44-pin TQFP 28-pin SSOP 28-pin SSOP 44-pin QFN 44-pin QFN 28-pin QFN 28-pin QFN DS39689F-page 386 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the This section discusses how to migrate from a Baseline ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device are due to the differences in the process technology (i.e., PIC18FXXX). used. An example of this type of conversion is from a The following are the list of modifications over the PIC16C74A to a PIC16C74B. PIC16C5X microcontroller family: The PIC18F2221/2321/4221/4321 family of devices is Not Currently Available functionally the same as the PIC18F4320 family. Code written for a PIC18F4320 will generally work on a PIC18F4321 with few or no changes. The following is a list of changes the user should be aware of when migrating an application from the PIC18F4320 to the PIC18F4321. Code written for the PIC18F4321 may not run as expected due to these differences. 1. Entry to power-managed modes has changed. Modifying the SCS1:SCS0 bits (OSCCON<1:0>) immediately changes the current clock source. It is not necessary to execute a SLEEP instruction to change clock sources. Refer to Section4.1.2 “Entering Power-Managed Modes” for details. 2. Exit from power-managed modes has changed. A WDT wake or interrupt does not cause an automatic return to PRI_RUN mode. The controller will execute code while continuing to use the current clock source. If the controller was operating in RC_IDLE or RC_RUN mode, an interrupt will cause entry to RC_RUN mode until code selects another power-managed mode. Refer to Section4.4 “Idle Modes” for details. 3. The extended instruction set can be con- figured as enabled using the XINST bit (CONFIG4L<6>). The access memory map is also modified when the extended instruction set is enabled. Refer to Section6.5 “Data Memory and the Extended Instruction Set” and Section24.2 “Extended Instruction Set” for details. 4. There may also be changes to the electrical spec- ifications. Refer to Section27.0 “Electrical Characteristics” for details. © 2009 Microchip Technology Inc. DS39689F-page 387

PIC18F2221/2321/4221/4321 FAMILY APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e., Enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the Enhanced devices (i.e., AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18C442”. The changes discussed, while device PIC18CXXX Migration”. specific, are generally applicable to all mid-range to This Application Note is available as Literature Number Enhanced device migrations. DS00726. This Application Note is available as Literature Number DS00716. DS39689F-page 388 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY INDEX A Block Diagrams A/D ...........................................................................236 A/D ...................................................................................233 Analog Input Model ..................................................237 Acquisition Requirements ........................................238 Baud Rate Generator ..............................................197 ADCON0 Register ....................................................233 Capture Mode Operation .........................................147 ADCON1 Register ....................................................233 Comparator Analog Input Model ..............................247 ADCON2 Register ....................................................233 Comparator I/O Operating Modes ...........................244 ADRESH Register ............................................233, 236 Comparator Output ..................................................246 ADRESL Register ....................................................233 Comparator Voltage Reference ...............................250 Analog Port Pins, Configuring ..................................240 Comparator Voltage Reference Output Associated Registers ...............................................242 Buffer Example ................................................251 Configuring the Module ............................................237 Compare Mode Operation .......................................148 Conversion Clock (TAD) ...........................................239 Device Clock ..............................................................35 Conversion Requirements .......................................371 Enhanced PWM .......................................................155 Conversion Status (GO/DONE Bit) ..........................236 EUSART Receive ....................................................225 Conversions .............................................................241 EUSART Transmit ...................................................222 Converter Characteristics ........................................370 External Power-on Reset Circuit Converter Interrupt, Configuring ..............................237 Discharge .................................................................241 (Slow VDD Power-up) ........................................49 Fail-Safe Clock Monitor ...........................................272 Operation in Power-Managed Modes ......................240 Generic I/O Port .......................................................111 Selecting and Configuring Acquisition Time ............239 High/Low-Voltage Detect with External Input ..........254 Special Event Trigger (CCP) ....................................242 HSPLL .......................................................................31 Special Event Trigger (ECCP) .................................154 Interrupt Logic ............................................................98 Use of the CCP2 Trigger ..........................................242 INTOSC and PLL .......................................................32 Absolute Maximum Ratings .............................................333 MSSP (I2C Master Mode) ........................................195 AC (Timing) Characteristics .............................................352 MSSP (I2C Mode) ....................................................176 Load Conditions for Device Timing MSSP (SPI Mode) ...................................................167 Specifications ...................................................353 On-Chip Reset Circuit ................................................47 Parameter Symbology .............................................352 PIC18F2221/2321 .....................................................12 Temperature and Voltage Specifications .................353 PIC18F4221/4321 .....................................................13 Timing Conditions ....................................................353 PORTD and PORTE (Parallel Slave Port) ...............126 AC Characteristics PWM Operation (Simplified) ....................................150 Internal RC Accuracy ...............................................355 Reads from Flash Program Memory .........................83 Access Bank Single Comparator ...................................................245 Mapping with Indexed Literal Offset Table Read Operation ...............................................79 Addressing Mode ...............................................77 Table Write Operation ...............................................80 ACKSTAT ........................................................................201 Table Writes to Flash Program Memory ....................85 ACKSTAT Status Flag .....................................................201 Timer0 in 16-Bit Mode .............................................130 ADCON0 Register ............................................................233 Timer0 in 8-Bit Mode ...............................................130 GO/DONE Bit ...........................................................236 Timer1 .....................................................................134 ADCON1 Register ............................................................233 Timer1 (16-Bit Read/Write Mode) ............................134 ADCON2 Register ............................................................233 Timer2 .....................................................................140 ADDFSR ..........................................................................322 Timer3 .....................................................................142 ADDLW ............................................................................285 Timer3 (16-Bit Read/Write Mode) ............................142 ADDULNK ........................................................................322 Watchdog Timer ......................................................269 ADDWF ............................................................................285 BN ....................................................................................288 ADDWFC .........................................................................286 BNC .................................................................................289 ADRESH Register ............................................................233 BNN .................................................................................289 ADRESL Register ....................................................233, 236 BNOV ..............................................................................290 Analog-to-Digital Converter. See A/D. BNZ .................................................................................290 ANDLW ............................................................................286 BOR. See Brown-out Reset. ANDWF ............................................................................287 BOV .................................................................................293 Assembler BRA .................................................................................291 MPASM Assembler ..................................................330 Break Character (12-Bit) Transmit and Receive ..............227 Auto-Wake-up on Sync Break Character .........................226 BRG. See Baud Rate Generator. B Brown-out Reset (BOR) .....................................................50 Bank Select Register (BSR) ...............................................65 Detecting ...................................................................50 Baud Rate Generator .......................................................197 Disabling in Sleep Mode ............................................50 BC ....................................................................................287 Software Enabled ......................................................50 BCF ..................................................................................288 BSF ..................................................................................291 BF ....................................................................................201 BTFSC .............................................................................292 BF Status Flag .................................................................201 BTFSS .............................................................................292 BTG .................................................................................293 BZ ....................................................................................294 © 2009 Microchip Technology Inc. DS39689F-page 389

PIC18F2221/2321/4221/4321 FAMILY C Effects of a Reset ....................................................246 Interrupts .................................................................246 C Compilers Operation .................................................................245 MPLAB C18 .............................................................330 Operation During Sleep ...........................................246 MPLAB C30 .............................................................330 Outputs ....................................................................245 CALL ................................................................................294 Reference ................................................................245 CALLW .............................................................................323 External Signal ................................................245 Capture (CCP Module) .....................................................147 Internal Signal ..................................................245 Associated Registers ...............................................149 Response Time ........................................................245 CCP Pin Configuration .............................................147 Comparator Specifications ...............................................350 CCPRxH:CCPRxL Registers ...................................147 Comparator Voltage Reference .......................................249 Prescaler ..................................................................147 Accuracy and Error ..................................................250 Software Interrupt ....................................................147 Associated Registers ...............................................251 Timer1/Timer3 Mode Selection ................................147 Configuring ..............................................................249 Capture (ECCP Module) ..................................................154 Connection Considerations ......................................250 Capture/Compare/PWM (CCP) ........................................145 Effects of a Reset ....................................................250 Capture Mode. See Capture. Operation During Sleep ...........................................250 CCPRxH Register ....................................................146 Compare (CCP Module) ..................................................148 CCPRxL Register .....................................................146 CCPRx Register ......................................................148 Compare Mode. See Compare. Pin Configuration .....................................................148 Interaction of Two CCP Modules .............................146 Software Interrupt ....................................................148 Module Configuration ...............................................146 Special Event Trigger ..............................143, 148, 242 Pin Assignment ........................................................146 Timer1/Timer3 Mode Selection ................................148 Timer Resources ......................................................146 Compare (ECCP Module) ................................................154 Clock Sources ....................................................................35 Special Event Trigger ..............................................154 Selecting the 31 kHz Source ......................................36 Computed GOTO ...............................................................62 Selection Using OSCCON Register ...........................36 Configuration Bits ............................................................259 CLRF ................................................................................295 Context Saving During Interrupts .....................................109 CLRWDT ..........................................................................295 Conversion Considerations ..............................................387 Code Examples CPFSEQ ..........................................................................296 16 x 16 Signed Multiply Routine ................................96 CPFSGT ..........................................................................297 16 x 16 Unsigned Multiply Routine ............................96 CPFSLT ...........................................................................297 8 x 8 Signed Multiply Routine ....................................95 Crystal Oscillator/Ceramic Resonator ................................29 8 x 8 Unsigned Multiply Routine ................................95 Customer Change Notification Service ............................399 Address Masking .....................................................182 Customer Notification Service .........................................399 Changing Between Capture Prescalers ...................147 Customer Support ............................................................399 Computed GOTO Using an Offset Value ...................62 Data EEPROM Read .................................................91 D Data EEPROM Refresh Routine ................................92 Data Addressing Modes ....................................................73 Data EEPROM Write .................................................91 Comparing Options with the Extended Erasing a Flash Program Memory Row .....................84 Instruction Set Enabled .....................................76 Fast Register Stack ....................................................62 Direct .........................................................................73 How to Clear RAM (Bank 1) Using Indirect Indexed Literal Offset ................................................75 Addressing .........................................................73 Instructions Affected ..........................................75 Implementing a Real-Time Clock Using a Indirect .......................................................................73 Timer1 Interrupt Service ..................................137 Inherent and Literal ....................................................73 Initializing PORTA ....................................................111 Data EEPROM Memory .....................................................89 Initializing PORTB ....................................................114 Associated Registers .................................................93 Initializing PORTC ....................................................117 EEADR Register ........................................................89 Initializing PORTD ....................................................120 EECON1 Register ......................................................89 Initializing PORTE ....................................................123 EECON2 Register ......................................................89 Loading the SSPBUF (SSPSR) Register .................170 EEDATA Register ......................................................89 Reading a Flash Program Memory Word ..................83 Operation During Code-Protect .................................92 Saving STATUS, WREG and BSR Protection Against Spurious Write .............................92 Registers in RAM .............................................109 Reading .....................................................................91 Writing to Flash Program Memory .......................86–87 Using .........................................................................92 Code Protection .......................................................259, 274 Write Verify ................................................................91 Associated Registers ...............................................275 Writing .......................................................................91 Configuration Register Protection ............................277 Data Memory .....................................................................65 Data EEPROM .........................................................277 Access Bank ..............................................................67 Program Memory .....................................................275 and the Extended Instruction Set ..............................75 COMF ...............................................................................296 Bank Select Register (BSR) ......................................65 Comparator ......................................................................243 General Purpose Registers .......................................67 Analog Input Connection Considerations .................247 Map for PIC18F2221/2321/4221/4321 Family ...........66 Associated Registers ...............................................247 Special Function Registers ........................................68 Configuration ............................................................244 DS39689F-page 390 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY DAW .................................................................................298 Synchronous Master Mode ......................................228 DC Characteristics ...........................................................347 Associated Registers, Receive ........................230 Power-Down and Supply Current ............................337 Associated Registers, Transmit .......................229 Supply Voltage .........................................................336 Reception ........................................................230 DCFSNZ ..........................................................................299 Transmission ...................................................228 DECF ...............................................................................298 Synchronous Slave Mode ........................................231 DECFSZ ...........................................................................299 Associated Registers, Receive ........................232 Development Support ......................................................329 Associated Registers, Transmit .......................231 Device Differences ...........................................................386 Reception ........................................................232 Device Overview ..................................................................9 Transmission ...................................................231 Details on Individual Family Members .......................10 Extended Instruction Set Features (table) ..........................................................11 ADDFSR ..................................................................322 New Core Features ......................................................9 ADDULNK ...............................................................322 Other Special Features ..............................................10 and Using MPLAB Tools .........................................328 Device Reset Timers ..........................................................51 CALLW ....................................................................323 Oscillator Start-up Timer (OST) .................................51 Considerations for Use ............................................326 PLL Lock Time-out .....................................................51 MOVSF ....................................................................323 Power-up Timer (PWRT) ...........................................51 MOVSS ....................................................................324 Time-out Sequence ....................................................51 PUSHL .....................................................................324 Direct Addressing ...............................................................74 SUBFSR ..................................................................325 SUBULNK ................................................................325 E Syntax ......................................................................321 Effect on Standard PIC MCU Instructions ........................326 External Clock Input ...........................................................30 Effects of Power-Managed Modes on Various F Clock Sources ............................................................38 Electrical Characteristics ..................................................333 Fail-Safe Clock Monitor ...........................................259, 272 Enhanced Capture/Compare/PWM (ECCP) ....................153 Exiting Operation .....................................................272 Associated Registers ...............................................166 Interrupts in Power-Managed Modes ......................273 Capture and Compare Modes ..................................154 POR or Wake From Sleep .......................................273 Capture Mode. See Capture (ECCP Module). WDT During Oscillator Failure .................................272 Outputs and Configuration .......................................154 Fast Register Stack ...........................................................62 Pin Configurations for ECCP1 .................................154 Firmware Instructions ......................................................279 PWM Mode. See PWM (ECCP Module). Flash Program Memory .....................................................79 Standard PWM Mode ...............................................154 Associated Registers .................................................87 Timer Resources ......................................................154 Control Registers .......................................................80 Enhanced PWM Mode. See PWM (ECCP Module). ........155 EECON1 and EECON2 .....................................80 Enhanced Universal Synchronous Asynchronous Receiver TABLAT (Table Latch) Register ........................82 Transmitter (EUSART). See EUSART. TBLPTR (Table Pointer) Register ......................82 Equations Erase Sequence ........................................................84 A/D Acquisition Time ................................................238 Erasing ......................................................................84 A/D Minimum Charging Time ...................................238 Operation During Code-Protect .................................87 Calculating the Minimum Required Reading .....................................................................83 Acquisition Time ..............................................238 Table Pointer Errata ...................................................................................8 Boundaries ........................................................82 EUSART Boundaries Based on Operation .......................82 Asynchronous Mode ................................................221 Operations with TBLRD and TBLWT (table) .....82 12-Bit Break Transmit and Receive .................227 Table Reads and Table Writes ..................................79 Associated Registers, Receive ........................225 Write Sequence .........................................................85 Associated Registers, Transmit .......................223 Writing .......................................................................85 Auto-Wake-up on Sync Break .........................226 Protection Against Spurious Writes ...................87 Receiver ...........................................................224 Unexpected Termination ...................................87 Setting up 9-Bit Mode with Address Detect .....224 Write Verify ........................................................87 Transmitter .......................................................221 FSCM. See Fail-Safe Clock Monitor. Baud Rate Generator G Operation in Power-Managed Mode ................215 Baud Rate Generator (BRG) ....................................215 GOTO ..............................................................................300 Associated Registers .......................................216 H Auto-Baud Rate Detect ....................................219 Baud Rate Error, Calculating ...........................216 Hardware Multiplier ............................................................95 Baud Rates, Asynchronous Modes .................217 Introduction ................................................................95 High Baud Rate Select (BRGH Bit) .................215 Operation ...................................................................95 Sampling ..........................................................215 Performance Comparison ..........................................95 © 2009 Microchip Technology Inc. DS39689F-page 391

PIC18F2221/2321/4221/4321 FAMILY High/Low-Voltage Detect .................................................253 Instruction Cycle ................................................................63 Applications ..............................................................256 Clocking Scheme .......................................................63 Associated Registers ...............................................257 Instruction Flow/Pipelining .................................................63 Characteristics .........................................................351 Instruction Set ..................................................................279 Current Consumption ...............................................255 ADDLW ....................................................................285 Effects of a Reset .....................................................257 ADDWF ....................................................................285 Operation .................................................................254 ADDWF (Indexed Literal Offset Mode) ....................327 During Sleep ....................................................257 ADDWFC .................................................................286 Setup ........................................................................255 ANDLW ....................................................................286 Start-up Time ...........................................................255 ANDWF ....................................................................287 Typical Application ...................................................256 BC ............................................................................287 HLVD. See High/Low-Voltage Detect. .............................253 BCF .........................................................................288 BN ............................................................................288 I BNC .........................................................................289 I/O Ports ...........................................................................111 BNN .........................................................................289 I2C Mode (MSSP) BNOV ......................................................................290 Acknowledge Sequence Timing ...............................204 BNZ .........................................................................290 Associated Registers ...............................................210 BOV .........................................................................293 Baud Rate Generator ...............................................197 BRA .........................................................................291 Bus Collision BSF ..........................................................................291 During a Repeated Start Condition ..................208 BSF (Indexed Literal Offset Mode) ..........................327 During a Start Condition ...................................206 BTFSC .....................................................................292 During a Stop Condition ...................................209 BTFSS .....................................................................292 Clock Arbitration .......................................................198 BTG .........................................................................293 Clock Stretching .......................................................190 BZ ............................................................................294 10-Bit Slave Receive Mode (SEN = 1) .............190 CALL ........................................................................294 10-Bit Slave Transmit Mode .............................190 CLRF .......................................................................295 7-Bit Slave Receive Mode (SEN = 1) ...............190 CLRWDT .................................................................295 7-Bit Slave Transmit Mode ...............................190 COMF ......................................................................296 Clock Synchronization and the CKP Bit ...................191 CPFSEQ ..................................................................296 Effects of a Reset .....................................................205 CPFSGT ..................................................................297 General Call Address Support .................................194 CPFSLT ...................................................................297 I2C Clock Rate w/BRG .............................................197 DAW ........................................................................298 Master Mode ............................................................195 DCFSNZ ..................................................................299 Operation .........................................................196 DECF .......................................................................298 Reception .........................................................201 DECFSZ ..................................................................299 Repeated Start Condition Timing .....................200 Extended Instruction Set .........................................321 Start Condition Timing .....................................199 General Format ........................................................281 Transmission ....................................................201 GOTO ......................................................................300 Multi-Master Communication, Bus Collision INCF ........................................................................300 and Arbitration ..................................................205 INCFSZ ....................................................................301 Multi-Master Mode ...................................................205 INFSNZ ....................................................................301 Operation .................................................................181 IORLW .....................................................................302 Read/Write Bit Information (R/W Bit) .......................181 IORWF .....................................................................302 Read/Write Bit Information (R/W Bit) .......................183 LFSR .......................................................................303 Registers ..................................................................176 MOVF ......................................................................303 Serial Clock (RC3/SCK/SCL) ...................................183 MOVFF ....................................................................304 Slave Mode ..............................................................181 MOVLB ....................................................................304 Address Masking .............................................182 MOVLW ...................................................................305 Addressing .......................................................181 MOVWF ...................................................................305 Reception .........................................................183 MULLW ....................................................................306 Transmission ....................................................183 MULWF ....................................................................306 Sleep Operation .......................................................205 NEGF .......................................................................307 Stop Condition Timing ..............................................204 NOP .........................................................................307 ID Locations .............................................................259, 277 Opcode Field Descriptions .......................................280 INCF .................................................................................300 POP .........................................................................308 INCFSZ ............................................................................301 PUSH .......................................................................308 In-Circuit Debugger ..........................................................277 RCALL .....................................................................309 In-Circuit Serial Programming (ICSP) ......................259, 277 RESET .....................................................................309 Single-Supply ...........................................................277 RETFIE ....................................................................310 Indexed Literal Offset Addressing RETLW ....................................................................310 and Standard PIC18 Instructions .............................326 RETURN ..................................................................311 Indexed Literal Offset Mode .............................................326 RLCF .......................................................................311 Indirect Addressing ............................................................74 RLNCF .....................................................................312 INFSNZ ............................................................................301 RRCF .......................................................................312 Initialization Conditions for all Registers ......................55–58 DS39689F-page 392 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY RRNCF ....................................................................313 MOVSS ............................................................................324 SETF ........................................................................313 MOVWF ...........................................................................305 SETF (Indexed Literal Offset Mode) ........................327 MPLAB ASM30 Assembler, Linker, Librarian ..................330 SLEEP .....................................................................314 MPLAB ICD 2 In-Circuit Debugger ..................................331 Standard Instructions ...............................................279 MPLAB ICE 2000 High-Performance Universal SUBFWB ..................................................................314 In-Circuit Emulator ...................................................331 SUBLW ....................................................................315 MPLAB Integrated Development Environment SUBWF ....................................................................315 Software ..................................................................329 SUBWFB ..................................................................316 MPLAB PM3 Device Programmer ...................................331 SWAPF ....................................................................316 MPLAB REAL ICE In-Circuit Emulator System ...............331 TBLRD .....................................................................317 MPLINK Object Linker/MPLIB Object Librarian ...............330 TBLWT .....................................................................318 MSSP TSTFSZ ...................................................................319 ACK Pulse .......................................................181, 183 XORLW ....................................................................319 Control Registers (general) .....................................167 XORWF ....................................................................320 I2C Mode. See I2C Mode. INTCON Registers .....................................................99–101 Module Overview .....................................................167 Inter-Integrated Circuit. See I2C. SPI Master/Slave Connection ..................................171 Internal Oscillator Block .....................................................32 SPI Mode. See SPI Mode. Adjustment .................................................................32 SSPBUF Register ....................................................172 INTIO Modes ..............................................................32 SSPSR Register ......................................................172 INTOSC Frequency Drift ............................................33 MULLW ............................................................................306 INTOSC Output Frequency ........................................32 MULWF ............................................................................306 OSCTUNE Register ...................................................32 N PLL in INTOSC Modes ..............................................33 Internal RC Oscillator NEGF ...............................................................................307 Use with WDT ..........................................................269 NOP .................................................................................307 Internet Address ...............................................................399 O Interrupt Sources .............................................................259 A/D Conversion Complete .......................................237 Oscillator Configuration .....................................................29 Capture Complete (CCP) .........................................147 EC ..............................................................................29 Compare Complete (CCP) .......................................148 ECIO ..........................................................................29 Interrupt-on-Change (RB7:RB4) ..............................114 HS ..............................................................................29 INTx Pin ...................................................................109 HSPLL .......................................................................29 PORTB, Interrupt-on-Change ..................................109 Internal Oscillator Block .............................................32 TMR0 .......................................................................109 INTIO1 .......................................................................29 TMR0 Overflow ........................................................131 INTIO2 .......................................................................29 TMR1 Overflow ........................................................133 LP ..............................................................................29 TMR2 to PR2 Match (PWM) ............................150, 155 RC .............................................................................29 TMR3 Overflow ................................................141, 143 RCIO ..........................................................................29 Interrupts ............................................................................97 XT ..............................................................................29 INTOSC, INTRC. See Internal Oscillator Block. Oscillator Selection ..........................................................259 IORLW .............................................................................302 Oscillator Start-up Timer (OST) ...................................38, 51 IORWF .............................................................................302 Oscillator Switching ...........................................................35 IPR Registers ...................................................................106 Oscillator Transitions .........................................................36 Oscillator, Timer1 .....................................................133, 143 L Oscillator, Timer3 .............................................................141 LFSR ................................................................................303 P Low-Voltage ICSP Programming. See Single-Supply ICSP Programming Packaging Information .....................................................373 Marking ....................................................................373 M Parallel Slave Port (PSP) .........................................120, 126 Master Clear (MCLR) .........................................................49 Associated Registers ...............................................127 Master Synchronous Serial Port (MSSP). See MSSP. CS (Chip Select) ......................................................126 Memory Organization .........................................................59 PORTD ....................................................................126 Data Memory .............................................................65 RD (Read Input) ......................................................126 Program Memory .......................................................59 Select (PSPMODE Bit) ....................................120, 126 Memory Programming Requirements ..............................349 WR (Write Input) ......................................................126 Microchip Internet Web Site .............................................399 PICSTART Plus Development Programmer ....................332 Migration from Baseline to Enhanced Devices ................387 PIE Registers ...................................................................104 Migration from High-End to Enhanced Devices ...............388 Pin Functions Migration from Mid-Range to Enhanced Devices ............388 MCLR/VPP/RE3 ...................................................14, 18 MOVF ...............................................................................303 OSC1/CLKI/RA7 ..................................................14, 18 MOVFF ............................................................................304 OSC2/CLKO/RA6 ................................................14, 18 MOVLB ............................................................................304 RA0/AN0 ..............................................................15, 19 MOVLW ...........................................................................305 RA1/AN1 ..............................................................15, 19 MOVSF ............................................................................323 © 2009 Microchip Technology Inc. DS39689F-page 393

PIC18F2221/2321/4221/4321 FAMILY RA2/AN2/VREF-/CVREF ........................................15, 19 PORTE RA3/AN3/VREF+ ...................................................15, 19 Associated Registers ...............................................125 RA4/T0CKI/C1OUT ..............................................15, 19 LATE Register .........................................................123 RA5/AN4/SS/HLVDIN/C2OUT .............................15, 19 PORTE Register ......................................................123 RB0/INT0/FLT0/AN12 ..........................................16, 20 PSP Mode Select (PSPMODE Bit) ..........................120 RB1/INT1/AN10 ...................................................16, 20 TRISE Register ........................................................123 RB2/INT2/AN8 .....................................................16, 20 Power-Managed Modes .....................................................39 RB3/AN9/CCP2 ...................................................16, 20 and A/D Operation ...................................................240 RB4/KBI0/AN11 ...................................................16, 20 and EUSART Operation ..........................................215 RB5/KBI1/PGM ....................................................16, 20 and PWM Operation ................................................165 RB6/KBI2/PGC ....................................................16, 20 and SPI Operation ...................................................175 RB7/KBI3/PGD ....................................................16, 20 Clock Sources ............................................................39 RC0/T1OSO/T13CKI ...........................................17, 21 Clock Transitions and Status Indicators ....................40 RC1/T1OSI/CCP2 ................................................17, 21 Effects on Clock Sources ...........................................38 RC2/CCP1 .................................................................17 Entering .....................................................................39 RC2/CCP1/P1A .........................................................21 Exiting Idle and Sleep Modes ....................................45 RC3/SCK/SCL .....................................................17, 21 By Interrupt ........................................................45 RC4/SDI/SDA ......................................................17, 21 By Reset ............................................................45 RC5/SDO .............................................................17, 21 By WDT Time-out ..............................................45 RC6/TX/CK ..........................................................17, 21 Without an Oscillator Start-up Delay .................46 RC7/RX/DT ..........................................................17, 21 Idle Modes .................................................................43 RD0/PSP0 ..................................................................22 PRI_IDLE ...........................................................44 RD1/PSP1 ..................................................................22 RC_IDLE ...........................................................45 RD2/PSP2 ..................................................................22 SEC_IDLE .........................................................44 RD3/PSP3 ..................................................................22 Multiple Sleep Commands .........................................40 RD4/PSP4 ..................................................................22 Run Modes ................................................................40 RD5/PSP5/P1B ..........................................................22 PRI_RUN ...........................................................40 RD6/PSP6/P1C ..........................................................22 RC_RUN ............................................................41 RD7/PSP7/P1D ..........................................................22 SEC_RUN .........................................................40 RE0/RD/AN5 ..............................................................23 Sleep Mode ...............................................................43 RE1/WR/AN6 .............................................................23 Summary (table) ........................................................39 RE2/CS/AN7 ..............................................................23 Power-on Reset (POR) ......................................................49 VDD .......................................................................17, 23 Power-up Timer (PWRT) ...........................................51 VSS .......................................................................17, 23 Time-out Sequence ...................................................51 Pinout I/O Descriptions Power-up Delays ...............................................................38 PIC18F2221/2321 ......................................................14 Power-up Timer (PWRT) ...................................................38 PIC18F4221/4321 ......................................................18 Prescaler PIR Registers ...................................................................102 Timer2 .....................................................................156 PLL Frequency Multiplier ...................................................31 Prescaler, Timer0 ............................................................131 HSPLL Oscillator Mode ..............................................31 Prescaler, Timer2 ............................................................151 Use with INTOSC .......................................................31 PRI_IDLE Mode .................................................................44 POP ..................................................................................308 PRI_RUN Mode .................................................................40 POR. See Power-on Reset. Program Counter ...............................................................60 PORTA PCL, PCH and PCU Registers ..................................60 Associated Registers ...............................................113 PCLATH and PCLATU Registers ..............................60 LATA Register ..........................................................111 Program Memory PORTA Register ......................................................111 and Extended Instruction Set ....................................77 TRISA Register ........................................................111 Instructions ................................................................64 PORTB Two-Word ..........................................................64 Associated Registers ...............................................116 Interrupt Vector ..........................................................59 LATB Register ..........................................................114 Look-up Tables ..........................................................62 PORTB Register ......................................................114 Map and Stack (diagram) ..........................................59 TRISB Register ........................................................114 Reset Vector ..............................................................59 PORTC Program Verification ........................................................274 Associated Registers ...............................................119 Programming, Device Instructions ...................................279 LATC Register .........................................................117 PSP. See Parallel Slave Port. PORTC Register ......................................................117 Pulse-Width Modulation. See PWM (CCP Module) and RC3/SCK/SCL Pin ...................................................183 PWM (ECCP Module). TRISC Register ........................................................117 PUSH ...............................................................................308 PORTD PUSH and POP Instructions ..............................................61 Associated Registers ...............................................122 PUSHL .............................................................................324 LATD Register .........................................................120 PWM (CCP Module) Parallel Slave Port (PSP) Function ..........................120 Associated Registers ...............................................152 PORTD Register ......................................................120 Auto-Shutdown (CCP1 Only) ...................................151 TRISD Register ........................................................120 Duty Cycle ...............................................................150 DS39689F-page 394 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY Example Frequencies/Resolutions ..........................151 ECCP1DEL (PWM Dead-Band Delay) ....................162 Operation Setup .......................................................151 EECON1 (Data EEPROM Control 1) ...................81, 90 Period .......................................................................150 HLVDCON (High/Low-Voltage Detect Control) .......253 TMR2 to PR2 Match ........................................150, 155 INTCON (Interrupt Control) .......................................99 PWM (ECCP Module) ......................................................155 INTCON2 (Interrupt Control 2) ................................100 CCPR1H:CCPR1L Registers ...................................155 INTCON3 (Interrupt Control 3) ................................101 Duty Cycle ................................................................156 IPR1 (Peripheral Interrupt Priority 1) .......................106 Effects of a Reset .....................................................165 IPR2 (Peripheral Interrupt Priority 2) .......................107 Enhanced PWM Auto-Shutdown .............................162 OSCCON (Oscillator Control) ....................................37 Example Frequencies/Resolutions ..........................156 OSCTUNE (Oscillator Tuning) ...................................33 Full-Bridge Application Example ..............................160 PIE1 (Peripheral Interrupt Enable 1) .......................104 Full-Bridge Mode ......................................................159 PIE2 (Peripheral Interrupt Enable 2) .......................105 Direction Change .............................................160 PIR1 (Peripheral Interrupt Request (Flag) 1) ...........102 Half-Bridge Mode .....................................................158 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........103 Half-Bridge Output Mode Applications RCON (Reset Control) .......................................48, 108 Example ...........................................................158 RCSTA (Receive Status and Control) .....................213 Operation in Power-Managed Modes ......................165 SSPADD(MSSP Address) .......................................180 Operation with Fail-Safe Clock Monitor ...................165 SSPCON1 (MSSP Control 1, I2C Mode) .................178 Output Configurations ..............................................156 SSPCON1 (MSSP Control 1, SPI Mode) ................169 Output Relationships (Active-High) ..........................157 SSPCON2 (MSSP Control 2, I2C Mode) .................179 Output Relationships (Active-Low) ...........................157 SSPSTAT (MSSP Status, I2C Mode) ......................177 Period .......................................................................155 SSPSTAT (MSSP Status, SPI Mode) ......................168 Programmable Dead-Band Delay ............................162 STATUS ....................................................................72 Setup for PWM Operation ........................................165 STKPTR (Stack Pointer) ............................................61 Start-up Considerations ...........................................164 T0CON (Timer0 Control) .........................................129 T1CON (Timer1 Control) .........................................133 Q T2CON (Timer2 Control) .........................................139 Q Clock ....................................................................151, 156 T3CON (Timer3 Control) .........................................141 TRISE (PORTE/PSP Control) .................................124 R TXSTA (Transmit Status and Control) .....................212 RAM. See Data Memory. WDTCON (Watchdog Timer Control) ......................270 RC Oscillator RESET .............................................................................309 RCIO Oscillator Mode ................................................31 Reset State of Registers ....................................................54 RC_IDLE Mode ..................................................................45 Resets .......................................................................47, 259 RC_RUN Mode ..................................................................41 Brown-out Reset (BOR) ...........................................259 RCALL .............................................................................309 Oscillator Start-up Timer (OST) ...............................259 RCON Register Power-on Reset (POR) ............................................259 Bit Status During Initialization ....................................54 Power-up Timer (PWRT) .........................................259 Reader Response ............................................................400 RETFIE ............................................................................310 Register File .......................................................................67 RETLW ............................................................................310 Register File Summary ................................................69–71 RETURN ..........................................................................311 Registers Return Address Stack ........................................................60 ADCON0 (A/D Control 0) .........................................233 Associated Registers .................................................60 ADCON1 (A/D Control 1) .........................................234 Return Stack Pointer (STKPTR) ........................................61 ADCON2 (A/D Control 2) .........................................235 Revision History ...............................................................385 BAUDCON (Baud Rate Control) ..............................214 RLCF ...............................................................................311 CCP1CON (Enhanced Capture/Compare/PWM RLNCF .............................................................................312 Control 1) .........................................................153 RRCF ...............................................................................312 CCPxCON (CCPx Control) ......................................145 RRNCF ............................................................................313 CMCON (Comparator Control) ................................243 S CONFIG1H (Configuration 1 High) ..........................260 CONFIG2H (Configuration 2 High) ..........................262 SCK .................................................................................167 CONFIG2L (Configuration 2 Low) ............................261 SDI ...................................................................................167 CONFIG3H (Configuration 3 High) ..........................263 SDO .................................................................................167 CONFIG4L (Configuration 4 Low) ............................264 SEC_IDLE Mode ...............................................................44 CONFIG5H (Configuration 5 High) ..........................265 SEC_RUN Mode ................................................................40 CONFIG5L (Configuration 5 Low) ............................265 Serial Clock, SCK ............................................................167 CONFIG6H (Configuration 6 High) ..........................266 Serial Data In (SDI) ..........................................................167 CONFIG6L (Configuration 6 Low) ............................266 Serial Data Out (SDO) .....................................................167 CONFIG7H (Configuration 7 High) ..........................267 Serial Peripheral Interface. See SPI Mode. CONFIG7L (Configuration 7 Low) ............................267 SETF ...............................................................................313 CVRCON (Comparator Voltage Single-Supply ICSP Programming. Reference Control) ..........................................249 Slave Select (SS) .............................................................167 DEVID1 (Device ID 1) ..............................................268 SLEEP .............................................................................314 DEVID2 (Device ID 2) ..............................................268 Sleep ECCP1AS (ECCP Auto-Shutdown Control) .............163 OSC1 and OSC2 Pin States ......................................38 © 2009 Microchip Technology Inc. DS39689F-page 395

PIC18F2221/2321/4221/4321 FAMILY Software Simulator (MPLAB SIM) ....................................330 TMR1L Register .......................................................133 Special Event Trigger. See Compare (CCP Mode). Use as a Real-Time Clock .......................................136 Special Event Trigger. See Compare (ECCP Module). Timer2 ..............................................................................139 Special Features of the CPU ............................................259 Associated Registers ...............................................140 Special Function Registers ................................................68 Interrupt ...................................................................140 Map ............................................................................68 Operation .................................................................139 SPI Mode (MSSP) Output ......................................................................140 Associated Registers ...............................................175 PR2 Register ...................................................150, 155 Bus Mode Compatibility ...........................................175 TMR2 to PR2 Match Interrupt ..................................155 Effects of a Reset .....................................................175 TMR2-to-PR2 Match Interrupt .................................150 Enabling SPI I/O ......................................................171 Timer3 ..............................................................................141 Master Mode ............................................................172 16-Bit Read/Write Mode ..........................................143 Master/Slave Connection .........................................171 Associated Registers ...............................................143 Operation .................................................................170 Operation .................................................................142 Operation in Power-Managed Modes ......................175 Oscillator ..........................................................141, 143 Serial Clock ..............................................................167 Overflow Interrupt ............................................141, 143 Serial Data In ...........................................................167 Special Event Trigger (CCP) ...................................143 Serial Data Out ........................................................167 TMR3H Register ......................................................141 Slave Mode ..............................................................173 TMR3L Register .......................................................141 Slave Select .............................................................167 Timing Diagrams Slave Select Synchronization ..................................173 A/D Conversion ........................................................371 SPI Clock .................................................................172 Acknowledge Sequence ..........................................204 Typical Connection ..................................................171 Asynchronous Reception .........................................225 SS ....................................................................................167 Asynchronous Transmission ....................................222 SSPOV .............................................................................201 Asynchronous Transmission (Back to Back) ...........222 SSPOV Status Flag ..........................................................201 Automatic Baud Rate Calculation ............................220 SSPSTAT Register Auto-Wake-up Bit (WUE) During R/W Bit .............................................................181, 183 Normal Operation ............................................226 Stack Full/Underflow Resets ..............................................62 Auto-Wake-up Bit (WUE) During Sleep ...................226 SUBFSR ...........................................................................325 Baud Rate Generator with Clock Arbitration ............198 SUBFWB ..........................................................................314 BRG Overflow Sequence .........................................220 SUBLW ............................................................................315 BRG Reset Due to SDA Arbitration During SUBULNK ........................................................................325 Start Condition .................................................207 SUBWF ............................................................................315 Brown-out Reset (BOR) ...........................................357 SUBWFB ..........................................................................316 Bus Collision During a Repeated Start SWAPF ............................................................................316 Condition (Case 1) ...........................................208 Bus Collision During a Repeated Start T Condition (Case 2) ...........................................208 Table Reads/Table Writes ..................................................62 Bus Collision During a Start Condition TBLRD .............................................................................317 (SCL = 0) .........................................................207 TBLWT .............................................................................318 Bus Collision During a Stop Condition (Case 1) ......209 Time-out in Various Situations (table) ................................51 Bus Collision During a Stop Condition (Case 2) ......209 Timer0 ..............................................................................129 Bus Collision During Start Condition Associated Registers ...............................................131 (SDA Only) ......................................................206 Operation .................................................................130 Bus Collision for Transmit and Acknowledge ..........205 Overflow Interrupt ....................................................131 Capture/Compare/PWM (All CCP Modules) ............359 Prescaler ..................................................................131 CLKO and I/O ..........................................................356 Prescaler Assignment (PSA Bit) ..............................131 Clock Synchronization .............................................191 Prescaler Select (T0PS2:T0PS0 Bits) .....................131 Clock/Instruction Cycle ..............................................63 Prescaler. See Prescaler, Timer0. EUSART Synchronous Receive (Master/Slave) ......369 Reads and Writes in 16-Bit Mode ............................130 EUSART Synchronous Transmission Source Edge Select (T0SE Bit) ................................130 (Master/Slave) .................................................369 Source Select (T0CS Bit) .........................................130 Example SPI Master Mode (CKE = 0) .....................361 Switching Prescaler Assignment ..............................131 Example SPI Master Mode (CKE = 1) .....................362 Timer1 ..............................................................................133 Example SPI Slave Mode (CKE = 0) .......................363 16-Bit Read/Write Mode ...........................................135 Example SPI Slave Mode (CKE = 1) .......................364 Associated Registers ...............................................137 External Clock (All Modes Except PLL) ...................354 Interrupt ....................................................................136 Fail-Safe Clock Monitor ...........................................273 Operation .................................................................134 First Start Bit Timing ................................................199 Oscillator ..........................................................133, 135 Full-Bridge PWM Output ..........................................159 Layout Considerations .....................................136 Half-Bridge PWM Output .........................................158 Low-Power Option ...........................................135 High/Low-Voltage Detect Characteristics ................351 Overflow Interrupt ....................................................133 High-Voltage Detect Operation (VDIRMAG = 1) .....256 Resetting, Using the CCP Special Event Trigger .....136 I2C Bus Data ............................................................365 Special Event Trigger (ECCP) .................................154 I2C Bus Start/Stop Bits ............................................365 TMR1H Register ......................................................133 DS39689F-page 396 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY I2C Master Mode (7 or 10-Bit Transmission) ...........202 Timing Diagrams and Specifications ...............................354 I2C Master Mode (7-Bit Reception) ..........................203 Capture/Compare/PWM Requirements I2C Slave Mode (10-Bit Reception, SEN = 0, (All CCP Modules) ...........................................359 ADMSK = 01001) .............................................187 CLKO and I/O Requirements ...................................356 I2C Slave Mode (10-Bit Reception, SEN = 0) ..........188 EUSART Synchronous Receive Requirements .......369 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........193 EUSART Synchronous Transmission Requirements .... I2C Slave Mode (10-Bit Transmission) .....................189 369 I2C Slave Mode (7-Bit Reception, SEN = 0, Example SPI Mode Requirements ADMSK = 01011) .............................................185 (Master Mode, CKE = 0) ..................................361 I2C Slave Mode (7-Bit Reception, SEN = 0) ............184 Example SPI Mode Requirements I2C Slave Mode (7-Bit Reception, SEN = 1) ............192 (Master Mode, CKE = 1) ..................................362 I2C Slave Mode (7-Bit Transmission) .......................186 Example SPI Mode Requirements I2C Slave Mode General Call Address (Slave Mode, CKE = 0) ....................................363 Sequence (7 or 10-Bit Addressing Mode) ........194 Example SPI Mode Requirements I2C Stop Condition Receive or Transmit Mode ........204 (Slave Mode, CKE = 1) ....................................364 Low-Voltage Detect Operation (VDIRMAG = 0) ......255 External Clock Requirements ..................................354 Master SSP I2C Bus Data ........................................367 I2C Bus Data Requirements (Slave Mode) ..............366 Master SSP I2C Bus Start/Stop Bits ........................367 I2C Bus Start/Stop Requirements (Slave Mode) .....365 Parallel Slave Port (PIC18F4221/4321) ...................360 Master SSP I2C Bus Data Requirements ................368 Parallel Slave Port (PSP) Read ...............................127 Master SSP I2C Bus Start/Stop Bits Parallel Slave Port (PSP) Write ...............................127 Requirements ..................................................367 PWM Auto-Shutdown (PRSEN = 0, Parallel Slave Port Requirements Auto-Restart Disabled) ....................................164 (PIC18F4221/4321) .........................................360 PWM Auto-Shutdown (PRSEN = 1, PLL Clock ................................................................355 Auto-Restart Enabled) .....................................164 Reset, Watchdog Timer, Oscillator Start-up PWM Direction Change ...........................................161 Timer, Power-up Timer and PWM Direction Change at Near Brown-out Reset Requirements ......................357 100% Duty Cycle .............................................161 Timer0 and Timer1 External Clock PWM Output ............................................................150 Requirements ..................................................358 Repeated Start Condition .........................................200 Top-of-Stack Access ..........................................................60 Reset, Watchdog Timer (WDT), Oscillator Start-up TRISE Register Timer (OST), Power-up Timer (PWRT) ...........357 PSPMODE Bit .........................................................120 Send Break Character Sequence ............................227 TSTFSZ ...........................................................................319 Slave Synchronization .............................................173 Two-Speed Start-up .................................................259, 271 Slow Rise Time (MCLR Tied to VDD, Two-Word Instructions VDD Rise > TPWRT) ............................................53 Example Cases .........................................................64 SPI Mode (Master Mode) .........................................172 TXSTA Register SPI Mode (Slave Mode, CKE = 0) ...........................174 BRGH Bit .................................................................215 SPI Mode (Slave Mode, CKE = 1) ...........................174 V Synchronous Reception (Master Mode, SREN) ......230 Synchronous Transmission ......................................228 Voltage Reference Specifications ....................................350 Synchronous Transmission (Through TXEN) ..........229 W Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ...........................................53 Watchdog Timer (WDT) ...........................................259, 269 Time-out Sequence on Power-up Associated Registers ...............................................270 (MCLR Not Tied to VDD, Case 1) .......................52 Control Register .......................................................269 Time-out Sequence on Power-up During Oscillator Failure ..........................................272 (MCLR Not Tied to VDD, Case 2) .......................52 Programming Considerations ..................................269 Time-out Sequence on Power-up WCOL ......................................................199, 200, 201, 204 (MCLR Tied to VDD, VDD Rise < TPWRT) ...........52 WCOL Status Flag ...................................199, 200, 201, 204 Timer0 and Timer1 External Clock ..........................358 WWW Address ................................................................399 Transition for Entry to Idle Mode ................................44 WWW, On-Line Support ......................................................8 Transition for Entry to SEC_RUN Mode ....................41 X Transition for Entry to Sleep Mode ............................43 Transition for Two-Speed Start-up XORLW ...........................................................................319 (INTOSC to HSPLL) ........................................271 XORWF ...........................................................................320 Transition for Wake from Idle to Run Mode ...............44 Transition for Wake from Sleep (HSPLL) ...................43 Transition from RC_RUN Mode to PRI_RUN Mode ..42 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) ..................................41 Transition to RC_RUN Mode .....................................42 © 2009 Microchip Technology Inc. DS39689F-page 397

PIC18F2221/2321/4221/4321 FAMILY NOTES: DS39689F-page 398 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39689F-page 399

PIC18F2221/2321/4221/4321 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2221/2321/4221/4321 Fa m i l y Literature Number: DS39689F Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39689F-page 400 © 2009 Microchip Technology Inc.

PIC18F2221/2321/4221/4321 FAMILY PIC18F2221/2321/4221/4321 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18F4321-I/P 301 = Industrial temp., PDIP Range package, Extended VDD limits, QTP pattern #301. b) PIC18LF2321-I/SO = Industrial temp., SOIC package, Extended VDD limits. Device PIC18F2221/2321(1), PIC18F4221/4321(1), c) PIC18LF4321-I/P = Industrial temp., PDIP PIC18F2221/2321T(2), PIC18F4221/4321T(2); package, normal VDD limits. VDD range 4.2V to 5.5V PIC18LF2221/2321(1), PIC18LF4221/4321(1), PIC18LF2221/2321T(2), PIC18LF4221/4321T(2); VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package PT = TQFP (Thin Quad Flatpack) SO = SOIC Note1: F = Standard Voltage Range SS = SSOP LF = Wide Voltage Range SP = Skinny Plastic DIP 2: T = in tape and reel P = PDIP ML = QFN Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) © 2009 Microchip Technology Inc. DS39689F-page 401

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